aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/clk/imx
diff options
context:
space:
mode:
authorFrank Li <Frank.Li@freescale.com>2015-05-18 14:45:02 -0400
committerShawn Guo <shawn.guo@linaro.org>2015-06-03 02:49:37 -0400
commitf53947456f98085b26d689b63c63c5e60fd1349b (patch)
tree8641a37f31f2ed24efde9e1b2467d41a45062d42 /drivers/clk/imx
parentd930d56825e934dc464cdad3f909333f994a89f3 (diff)
ARM: clk: imx: update pllv3 to support imx7
Add type IMX_PLLV3_ENET_IMX7 Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'drivers/clk/imx')
-rw-r--r--drivers/clk/imx/clk-pllv3.c9
-rw-r--r--drivers/clk/imx/clk.h1
2 files changed, 9 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 260035be11ac..f0d15fb9d783 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -24,12 +24,14 @@
24 24
25#define BM_PLL_POWER (0x1 << 12) 25#define BM_PLL_POWER (0x1 << 12)
26#define BM_PLL_LOCK (0x1 << 31) 26#define BM_PLL_LOCK (0x1 << 31)
27#define IMX7_ENET_PLL_POWER (0x1 << 5)
27 28
28/** 29/**
29 * struct clk_pllv3 - IMX PLL clock version 3 30 * struct clk_pllv3 - IMX PLL clock version 3
30 * @clk_hw: clock source 31 * @clk_hw: clock source
31 * @base: base address of PLL registers 32 * @base: base address of PLL registers
32 * @powerup_set: set POWER bit to power up the PLL 33 * @powerup_set: set POWER bit to power up the PLL
34 * @powerdown: pll powerdown offset bit
33 * @div_mask: mask of divider bits 35 * @div_mask: mask of divider bits
34 * @div_shift: shift of divider bits 36 * @div_shift: shift of divider bits
35 * 37 *
@@ -40,6 +42,7 @@ struct clk_pllv3 {
40 struct clk_hw hw; 42 struct clk_hw hw;
41 void __iomem *base; 43 void __iomem *base;
42 bool powerup_set; 44 bool powerup_set;
45 u32 powerdown;
43 u32 div_mask; 46 u32 div_mask;
44 u32 div_shift; 47 u32 div_shift;
45}; 48};
@@ -49,7 +52,7 @@ struct clk_pllv3 {
49static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) 52static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
50{ 53{
51 unsigned long timeout = jiffies + msecs_to_jiffies(10); 54 unsigned long timeout = jiffies + msecs_to_jiffies(10);
52 u32 val = readl_relaxed(pll->base) & BM_PLL_POWER; 55 u32 val = readl_relaxed(pll->base) & pll->powerdown;
53 56
54 /* No need to wait for lock when pll is not powered up */ 57 /* No need to wait for lock when pll is not powered up */
55 if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) 58 if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
@@ -293,6 +296,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
293 if (!pll) 296 if (!pll)
294 return ERR_PTR(-ENOMEM); 297 return ERR_PTR(-ENOMEM);
295 298
299 pll->powerdown = BM_PLL_POWER;
300
296 switch (type) { 301 switch (type) {
297 case IMX_PLLV3_SYS: 302 case IMX_PLLV3_SYS:
298 ops = &clk_pllv3_sys_ops; 303 ops = &clk_pllv3_sys_ops;
@@ -306,6 +311,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
306 case IMX_PLLV3_AV: 311 case IMX_PLLV3_AV:
307 ops = &clk_pllv3_av_ops; 312 ops = &clk_pllv3_av_ops;
308 break; 313 break;
314 case IMX_PLLV3_ENET_IMX7:
315 pll->powerdown = IMX7_ENET_PLL_POWER;
309 case IMX_PLLV3_ENET: 316 case IMX_PLLV3_ENET:
310 ops = &clk_pllv3_enet_ops; 317 ops = &clk_pllv3_enet_ops;
311 break; 318 break;
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 6bae5374dc83..8b112182a83b 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -39,6 +39,7 @@ enum imx_pllv3_type {
39 IMX_PLLV3_USB_VF610, 39 IMX_PLLV3_USB_VF610,
40 IMX_PLLV3_AV, 40 IMX_PLLV3_AV,
41 IMX_PLLV3_ENET, 41 IMX_PLLV3_ENET,
42 IMX_PLLV3_ENET_IMX7,
42}; 43};
43 44
44struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 45struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,