diff options
author | Lucas Stach <l.stach@pengutronix.de> | 2015-09-21 12:54:04 -0400 |
---|---|---|
committer | Shawn Guo <shawnguo@kernel.org> | 2015-09-26 00:59:06 -0400 |
commit | 1b9af68f325cb91ac9fc691f52d69dfb0826afd7 (patch) | |
tree | 9a85b30f63ebb0e7de37f61fe9fa3fb8ad01f6ad /drivers/clk/imx | |
parent | 0822f933735c1eee6adfc236c72f763f42ac0f3d (diff) |
clk: imx7d: retain early UART clocks during kernel init
Make sure to keep UART clocks enabled during kernel init if
earlyprintk or earlycon are active.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'drivers/clk/imx')
-rw-r--r-- | drivers/clk/imx/clk-imx7d.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 71f3a94b472c..f86b68049872 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c | |||
@@ -363,6 +363,17 @@ static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_ | |||
363 | 363 | ||
364 | static struct clk_onecell_data clk_data; | 364 | static struct clk_onecell_data clk_data; |
365 | 365 | ||
366 | static struct clk ** const uart_clks[] __initconst = { | ||
367 | &clks[IMX7D_UART1_ROOT_CLK], | ||
368 | &clks[IMX7D_UART2_ROOT_CLK], | ||
369 | &clks[IMX7D_UART3_ROOT_CLK], | ||
370 | &clks[IMX7D_UART4_ROOT_CLK], | ||
371 | &clks[IMX7D_UART5_ROOT_CLK], | ||
372 | &clks[IMX7D_UART6_ROOT_CLK], | ||
373 | &clks[IMX7D_UART7_ROOT_CLK], | ||
374 | NULL | ||
375 | }; | ||
376 | |||
366 | static void __init imx7d_clocks_init(struct device_node *ccm_node) | 377 | static void __init imx7d_clocks_init(struct device_node *ccm_node) |
367 | { | 378 | { |
368 | struct device_node *np; | 379 | struct device_node *np; |
@@ -856,5 +867,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) | |||
856 | /* set uart module clock's parent clock source that must be great then 80MHz */ | 867 | /* set uart module clock's parent clock source that must be great then 80MHz */ |
857 | clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]); | 868 | clk_set_parent(clks[IMX7D_UART1_ROOT_SRC], clks[IMX7D_OSC_24M_CLK]); |
858 | 869 | ||
870 | imx_register_uart_clocks(uart_clks); | ||
871 | |||
859 | } | 872 | } |
860 | CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init); | 873 | CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init); |