clk: bcm2835: add missing PLL clock dividers

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>

1 files changed, 32 insertions, 0 deletions

diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 156ce548ebf5..fa444d09c2d4 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1371,6 +1371,22 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
                 .load_mask = CM_PLLA_LOADPER,
                 .hold_mask = CM_PLLA_HOLDPER,
                 .fixed_divider = 1),
+        [BCM2835_PLLA_DSI0]     = REGISTER_PLL_DIV(
+                .name = "plla_dsi0",
+                .source_pll = "plla",
+                .cm_reg = CM_PLLA,
+                .a2w_reg = A2W_PLLA_DSI0,
+                .load_mask = CM_PLLA_LOADDSI0,
+                .hold_mask = CM_PLLA_HOLDDSI0,
+                .fixed_divider = 1),
+        [BCM2835_PLLA_CCP2]     = REGISTER_PLL_DIV(
+                .name = "plla_ccp2",
+                .source_pll = "plla",
+                .cm_reg = CM_PLLA,
+                .a2w_reg = A2W_PLLA_CCP2,
+                .load_mask = CM_PLLA_LOADCCP2,
+                .hold_mask = CM_PLLA_HOLDCCP2,
+                .fixed_divider = 1),
 
         /* PLLB is used for the ARM's clock. */
         [BCM2835_PLLB]          = REGISTER_PLL(
@@ -1485,6 +1501,22 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
                 .load_mask = CM_PLLD_LOADPER,
                 .hold_mask = CM_PLLD_HOLDPER,
                 .fixed_divider = 1),
+        [BCM2835_PLLD_DSI0]     = REGISTER_PLL_DIV(
+                .name = "plld_dsi0",
+                .source_pll = "plld",
+                .cm_reg = CM_PLLD,
+                .a2w_reg = A2W_PLLD_DSI0,
+                .load_mask = CM_PLLD_LOADDSI0,
+                .hold_mask = CM_PLLD_HOLDDSI0,
+                .fixed_divider = 1),
+        [BCM2835_PLLD_DSI1]     = REGISTER_PLL_DIV(
+                .name = "plld_dsi1",
+                .source_pll = "plld",
+                .cm_reg = CM_PLLD,
+                .a2w_reg = A2W_PLLD_DSI1,
+                .load_mask = CM_PLLD_LOADDSI1,
+                .hold_mask = CM_PLLD_HOLDDSI1,
+                .fixed_divider = 1),
 
         /*
          * PLLH is used to supply the pixel clock or the AUX clock for the