tile: updates to pci root complex from community feedback

Reviewed-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>

1 files changed, 1 insertions, 3 deletions

diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c
index 2b8b689e596d..6a649a4462d3 100644
--- a/arch/tile/kernel/setup.c
+++ b/arch/tile/kernel/setup.c
@@ -1536,8 +1536,7 @@ static struct resource code_resource = {
 
 /*
  * On Pro, we reserve all resources above 4GB so that PCI won't try to put
- * mappings above 4GB; the standard allows that for some devices but
- * the probing code trunates values to 32 bits.
+ * mappings above 4GB.
  */
 #if defined(CONFIG_PCI) && !defined(__tilegx__)
 static struct resource* __init
@@ -1584,7 +1583,6 @@ static int __init request_standard_resources(void)
         int i;
         enum { CODE_DELTA = MEM_SV_INTRPT - PAGE_OFFSET };
 
-        iomem_resource.end = -1LL;
 #if defined(CONFIG_PCI) && !defined(__tilegx__)
         insert_non_bus_resource();
 #endif