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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2016-07-05 01:03:47 -0400
committerMichael Ellerman <mpe@ellerman.id.au>2016-07-21 04:55:54 -0400
commitc40785ad305b32e9b0b5fbc888f1f5d57f29bf44 (patch)
tree29176dea27e7375311e8404d7137ed8b684fa110 /arch/powerpc/mm
parentde4cf3de594f96f5a27f0e2346dd211beb126f88 (diff)
powerpc/dart: Use a cachable DART
Instead of punching a hole in the linear mapping, just use normal cachable memory, and apply the flush sequence documented in the CPC625 (aka U3) user manual. This allows us to remove quite a bit of code related to the early allocation of the DART and the hole in the linear mapping. We can also get rid of the copy of the DART for suspend/resume as the original memory can just be saved/restored now, as long as we properly sync the caches. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [mpe: Integrate dart_init() fix to return ENODEV when DART disabled] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/mm')
-rw-r--r--arch/powerpc/mm/hash_utils_64.c32
1 files changed, 0 insertions, 32 deletions
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 7d0955e04f08..859ecaa928e9 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -87,10 +87,6 @@
87 * 87 *
88 */ 88 */
89 89
90#ifdef CONFIG_U3_DART
91extern unsigned long dart_tablebase;
92#endif /* CONFIG_U3_DART */
93
94static unsigned long _SDR1; 90static unsigned long _SDR1;
95struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; 91struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
96EXPORT_SYMBOL_GPL(mmu_psize_defs); 92EXPORT_SYMBOL_GPL(mmu_psize_defs);
@@ -846,34 +842,6 @@ static void __init htab_initialize(void)
846 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n", 842 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
847 base, size, prot); 843 base, size, prot);
848 844
849#ifdef CONFIG_U3_DART
850 /* Do not map the DART space. Fortunately, it will be aligned
851 * in such a way that it will not cross two memblock regions and
852 * will fit within a single 16Mb page.
853 * The DART space is assumed to be a full 16Mb region even if
854 * we only use 2Mb of that space. We will use more of it later
855 * for AGP GART. We have to use a full 16Mb large page.
856 */
857 DBG("DART base: %lx\n", dart_tablebase);
858
859 if (dart_tablebase != 0 && dart_tablebase >= base
860 && dart_tablebase < (base + size)) {
861 unsigned long dart_table_end = dart_tablebase + 16 * MB;
862 if (base != dart_tablebase)
863 BUG_ON(htab_bolt_mapping(base, dart_tablebase,
864 __pa(base), prot,
865 mmu_linear_psize,
866 mmu_kernel_ssize));
867 if ((base + size) > dart_table_end)
868 BUG_ON(htab_bolt_mapping(dart_tablebase+16*MB,
869 base + size,
870 __pa(dart_table_end),
871 prot,
872 mmu_linear_psize,
873 mmu_kernel_ssize));
874 continue;
875 }
876#endif /* CONFIG_U3_DART */
877 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base), 845 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
878 prot, mmu_linear_psize, mmu_kernel_ssize)); 846 prot, mmu_linear_psize, mmu_kernel_ssize));
879 } 847 }