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authorRabin Vincent <rabin@rab.in>2015-08-03 14:19:24 -0400
committerJesper Nilsson <jespern@axis.com>2015-11-02 14:03:05 -0500
commitab28e96fd1cf1db1579854931890e5613efc5021 (patch)
tree6884d63dc8b7199210a3e2f3ac38c6811cbcab15 /arch/cris/arch-v32
parent79b863c68eba8f7aa5b76c44db3b1df8412c977e (diff)
CRIS v32: remove old GPIO and LEDs code
Since we now have a gpiolib driver, remove this code: The gpio-etraxfs driver (along with things like gpio-keys-polled for polling support) replaces the GIO driver implementations in mach-a3 and mach-fs. The various generic external chip drivers replace the "virtual gpio" parts. The generic gpio-leds driver replaces the LED handling. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Jesper Nilsson <jespern@axis.com>
Diffstat (limited to 'arch/cris/arch-v32')
-rw-r--r--arch/cris/arch-v32/Kconfig89
-rw-r--r--arch/cris/arch-v32/drivers/Kconfig149
-rw-r--r--arch/cris/arch-v32/drivers/mach-a3/Makefile1
-rw-r--r--arch/cris/arch-v32/drivers/mach-a3/gpio.c999
-rw-r--r--arch/cris/arch-v32/drivers/mach-fs/Makefile1
-rw-r--r--arch/cris/arch-v32/drivers/mach-fs/gpio.c978
-rw-r--r--arch/cris/arch-v32/kernel/crisksyms.c3
-rw-r--r--arch/cris/arch-v32/mach-a3/Makefile2
-rw-r--r--arch/cris/arch-v32/mach-a3/io.c149
-rw-r--r--arch/cris/arch-v32/mach-fs/Makefile2
-rw-r--r--arch/cris/arch-v32/mach-fs/io.c191
11 files changed, 2 insertions, 2562 deletions
diff --git a/arch/cris/arch-v32/Kconfig b/arch/cris/arch-v32/Kconfig
index 21bbd93be34f..17dbe03af5f4 100644
--- a/arch/cris/arch-v32/Kconfig
+++ b/arch/cris/arch-v32/Kconfig
@@ -11,95 +11,6 @@ config ETRAX_DRAM_VIRTUAL_BASE
11 default "c0000000" 11 default "c0000000"
12 12
13choice 13choice
14 prompt "Nbr of Ethernet LED groups"
15 depends on ETRAX_ARCH_V32
16 default ETRAX_NBR_LED_GRP_ONE
17 help
18 Select how many Ethernet LED groups that can be used. Usually one per Ethernet
19 interface is a good choice.
20
21config ETRAX_NBR_LED_GRP_ZERO
22 bool "Use zero LED groups"
23 help
24 Select this if you do not want any Ethernet LEDs.
25
26config ETRAX_NBR_LED_GRP_ONE
27 bool "Use one LED group"
28 help
29 Select this if you want one Ethernet LED group. This LED group
30 can be used for one or more Ethernet interfaces. However, it is
31 recommended that each Ethernet interface use a dedicated LED group.
32
33config ETRAX_NBR_LED_GRP_TWO
34 bool "Use two LED groups"
35 help
36 Select this if you want two Ethernet LED groups. This is the
37 best choice if you have more than one Ethernet interface and
38 would like to have separate LEDs for the interfaces.
39
40endchoice
41
42config ETRAX_LED_G_NET0
43 string "Ethernet LED group 0 green LED bit"
44 depends on ETRAX_ARCH_V32 && (ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO)
45 default "PA3"
46 help
47 Bit to use for the green LED in Ethernet LED group 0.
48
49config ETRAX_LED_R_NET0
50 string "Ethernet LED group 0 red LED bit"
51 depends on ETRAX_ARCH_V32 && (ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO)
52 default "PA4"
53 help
54 Bit to use for the red LED in Ethernet LED group 0.
55
56config ETRAX_LED_G_NET1
57 string "Ethernet group 1 green LED bit"
58 depends on ETRAX_ARCH_V32 && ETRAX_NBR_LED_GRP_TWO
59 default ""
60 help
61 Bit to use for the green LED in Ethernet LED group 1.
62
63config ETRAX_LED_R_NET1
64 string "Ethernet group 1 red LED bit"
65 depends on ETRAX_ARCH_V32 && ETRAX_NBR_LED_GRP_TWO
66 default ""
67 help
68 Bit to use for the red LED in Ethernet LED group 1.
69
70config ETRAX_V32_LED2G
71 string "Second green LED bit"
72 depends on ETRAX_ARCH_V32
73 default "PA5"
74 help
75 Bit to use for the first green LED (status LED).
76 Most Axis products use bit A5 here.
77
78config ETRAX_V32_LED2R
79 string "Second red LED bit"
80 depends on ETRAX_ARCH_V32
81 default "PA6"
82 help
83 Bit to use for the first red LED (network LED).
84 Most Axis products use bit A6 here.
85
86config ETRAX_V32_LED3G
87 string "Third green LED bit"
88 depends on ETRAX_ARCH_V32
89 default "PA7"
90 help
91 Bit to use for the first green LED (drive/power LED).
92 Most Axis products use bit A7 here.
93
94config ETRAX_V32_LED3R
95 string "Third red LED bit"
96 depends on ETRAX_ARCH_V32
97 default "PA7"
98 help
99 Bit to use for the first red LED (drive/power LED).
100 Most Axis products use bit A7 here.
101
102choice
103 prompt "Kernel GDB port" 14 prompt "Kernel GDB port"
104 depends on ETRAX_KGDB 15 depends on ETRAX_KGDB
105 default ETRAX_KGDB_PORT0 16 default ETRAX_KGDB_PORT0
diff --git a/arch/cris/arch-v32/drivers/Kconfig b/arch/cris/arch-v32/drivers/Kconfig
index c5cbd2aac60e..2735eb7671a5 100644
--- a/arch/cris/arch-v32/drivers/Kconfig
+++ b/arch/cris/arch-v32/drivers/Kconfig
@@ -149,155 +149,6 @@ config ETRAX_NANDBOOT
149 Say Y if your boot code, kernel and root file system is in 149 Say Y if your boot code, kernel and root file system is in
150 NAND flash. Say N if they are in NOR flash. 150 NAND flash. Say N if they are in NOR flash.
151 151
152config ETRAX_GPIO
153 bool "GPIO support"
154 depends on ETRAX_ARCH_V32
155 ---help---
156 Enables the ETRAX general port device (major 120, minors 0-4).
157 You can use this driver to access the general port bits. It supports
158 these ioctl's:
159 #include <linux/etraxgpio.h>
160 fd = open("/dev/gpioa", O_RDWR); // or /dev/gpiob
161 ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_SETBITS), bits_to_set);
162 ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_CLRBITS), bits_to_clear);
163 err = ioctl(fd, _IO(ETRAXGPIO_IOCTYPE, IO_READ_INBITS), &val);
164 Remember that you need to setup the port directions appropriately in
165 the General configuration.
166
167config ETRAX_VIRTUAL_GPIO
168 bool "Virtual GPIO support"
169 depends on ETRAX_GPIO
170 help
171 Enables the virtual Etrax general port device (major 120, minor 6).
172 It uses an I/O expander for the I2C-bus.
173
174config ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN
175 int "Virtual GPIO interrupt pin on PA pin"
176 range 0 7
177 depends on ETRAX_VIRTUAL_GPIO
178 help
179 The pin to use on PA for virtual gpio interrupt.
180
181config ETRAX_PA_CHANGEABLE_DIR
182 hex "PA user changeable dir mask"
183 depends on ETRAX_GPIO
184 default "0x00" if ETRAXFS
185 default "0x00000000" if !ETRAXFS
186 help
187 This is a bitmask with information of what bits in PA that a
188 user can change direction on using ioctl's.
189 Bit set = changeable.
190 You probably want 0 here, but it depends on your hardware.
191
192config ETRAX_PA_CHANGEABLE_BITS
193 hex "PA user changeable bits mask"
194 depends on ETRAX_GPIO
195 default "0x00" if ETRAXFS
196 default "0x00000000" if !ETRAXFS
197 help
198 This is a bitmask with information of what bits in PA
199 that a user can change the value on using ioctl's.
200 Bit set = changeable.
201
202config ETRAX_PB_CHANGEABLE_DIR
203 hex "PB user changeable dir mask"
204 depends on ETRAX_GPIO
205 default "0x00000" if ETRAXFS
206 default "0x00000000" if !ETRAXFS
207 help
208 This is a bitmask with information of what bits in PB
209 that a user can change direction on using ioctl's.
210 Bit set = changeable.
211 You probably want 0 here, but it depends on your hardware.
212
213config ETRAX_PB_CHANGEABLE_BITS
214 hex "PB user changeable bits mask"
215 depends on ETRAX_GPIO
216 default "0x00000" if ETRAXFS
217 default "0x00000000" if !ETRAXFS
218 help
219 This is a bitmask with information of what bits in PB
220 that a user can change the value on using ioctl's.
221 Bit set = changeable.
222
223config ETRAX_PC_CHANGEABLE_DIR
224 hex "PC user changeable dir mask"
225 depends on ETRAX_GPIO
226 default "0x00000" if ETRAXFS
227 default "0x00000000" if !ETRAXFS
228 help
229 This is a bitmask with information of what bits in PC
230 that a user can change direction on using ioctl's.
231 Bit set = changeable.
232 You probably want 0 here, but it depends on your hardware.
233
234config ETRAX_PC_CHANGEABLE_BITS
235 hex "PC user changeable bits mask"
236 depends on ETRAX_GPIO
237 default "0x00000" if ETRAXFS
238 default "0x00000000" if !ETRAXFS
239 help
240 This is a bitmask with information of what bits in PC
241 that a user can change the value on using ioctl's.
242 Bit set = changeable.
243
244config ETRAX_PD_CHANGEABLE_DIR
245 hex "PD user changeable dir mask"
246 depends on ETRAX_GPIO && ETRAXFS
247 default "0x00000"
248 help
249 This is a bitmask with information of what bits in PD
250 that a user can change direction on using ioctl's.
251 Bit set = changeable.
252 You probably want 0x00000 here, but it depends on your hardware.
253
254config ETRAX_PD_CHANGEABLE_BITS
255 hex "PD user changeable bits mask"
256 depends on ETRAX_GPIO && ETRAXFS
257 default "0x00000"
258 help
259 This is a bitmask (18 bits) with information of what bits in PD
260 that a user can change the value on using ioctl's.
261 Bit set = changeable.
262
263config ETRAX_PE_CHANGEABLE_DIR
264 hex "PE user changeable dir mask"
265 depends on ETRAX_GPIO && ETRAXFS
266 default "0x00000"
267 help
268 This is a bitmask (18 bits) with information of what bits in PE
269 that a user can change direction on using ioctl's.
270 Bit set = changeable.
271 You probably want 0x00000 here, but it depends on your hardware.
272
273config ETRAX_PE_CHANGEABLE_BITS
274 hex "PE user changeable bits mask"
275 depends on ETRAX_GPIO && ETRAXFS
276 default "0x00000"
277 help
278 This is a bitmask (18 bits) with information of what bits in PE
279 that a user can change the value on using ioctl's.
280 Bit set = changeable.
281
282config ETRAX_PV_CHANGEABLE_DIR
283 hex "PV user changeable dir mask"
284 depends on ETRAX_VIRTUAL_GPIO
285 default "0x0000"
286 help
287 This is a bitmask (16 bits) with information of what bits in PV
288 that a user can change direction on using ioctl's.
289 Bit set = changeable.
290 You probably want 0x0000 here, but it depends on your hardware.
291
292config ETRAX_PV_CHANGEABLE_BITS
293 hex "PV user changeable bits mask"
294 depends on ETRAX_VIRTUAL_GPIO
295 default "0x0000"
296 help
297 This is a bitmask (16 bits) with information of what bits in PV
298 that a user can change the value on using ioctl's.
299 Bit set = changeable.
300
301config ETRAX_CARDBUS 152config ETRAX_CARDBUS
302 bool "Cardbus support" 153 bool "Cardbus support"
303 depends on ETRAX_ARCH_V32 154 depends on ETRAX_ARCH_V32
diff --git a/arch/cris/arch-v32/drivers/mach-a3/Makefile b/arch/cris/arch-v32/drivers/mach-a3/Makefile
index 5c6d2a2a080e..59028d0b981c 100644
--- a/arch/cris/arch-v32/drivers/mach-a3/Makefile
+++ b/arch/cris/arch-v32/drivers/mach-a3/Makefile
@@ -3,4 +3,3 @@
3# 3#
4 4
5obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o 5obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o
6obj-$(CONFIG_ETRAX_GPIO) += gpio.o
diff --git a/arch/cris/arch-v32/drivers/mach-a3/gpio.c b/arch/cris/arch-v32/drivers/mach-a3/gpio.c
deleted file mode 100644
index c92e1da3684d..000000000000
--- a/arch/cris/arch-v32/drivers/mach-a3/gpio.c
+++ /dev/null
@@ -1,999 +0,0 @@
1/*
2 * Artec-3 general port I/O device
3 *
4 * Copyright (c) 2007 Axis Communications AB
5 *
6 * Authors: Bjorn Wesen (initial version)
7 * Ola Knutsson (LED handling)
8 * Johan Adolfsson (read/set directions, write, port G,
9 * port to ETRAX FS.
10 * Ricard Wanderlof (PWM for Artpec-3)
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/sched.h>
16#include <linux/slab.h>
17#include <linux/ioport.h>
18#include <linux/errno.h>
19#include <linux/kernel.h>
20#include <linux/fs.h>
21#include <linux/string.h>
22#include <linux/poll.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/spinlock.h>
26#include <linux/mutex.h>
27
28#include <asm/etraxgpio.h>
29#include <hwregs/reg_map.h>
30#include <hwregs/reg_rdwr.h>
31#include <hwregs/gio_defs.h>
32#include <hwregs/intr_vect_defs.h>
33#include <asm/io.h>
34#include <asm/irq.h>
35#include <mach/pinmux.h>
36
37#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
38#include "../i2c.h"
39
40#define VIRT_I2C_ADDR 0x40
41#endif
42
43/* The following gio ports on ARTPEC-3 is available:
44 * pa 32 bits
45 * pb 32 bits
46 * pc 16 bits
47 * each port has a rw_px_dout, r_px_din and rw_px_oe register.
48 */
49
50#define GPIO_MAJOR 120 /* experimental MAJOR number */
51
52#define I2C_INTERRUPT_BITS 0x300 /* i2c0_done and i2c1_done bits */
53
54#define D(x)
55
56#if 0
57static int dp_cnt;
58#define DP(x) \
59 do { \
60 dp_cnt++; \
61 if (dp_cnt % 1000 == 0) \
62 x; \
63 } while (0)
64#else
65#define DP(x)
66#endif
67
68static DEFINE_MUTEX(gpio_mutex);
69static char gpio_name[] = "etrax gpio";
70
71#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
72static int virtual_gpio_ioctl(struct file *file, unsigned int cmd,
73 unsigned long arg);
74#endif
75static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
76static ssize_t gpio_write(struct file *file, const char __user *buf,
77 size_t count, loff_t *off);
78static int gpio_open(struct inode *inode, struct file *filp);
79static int gpio_release(struct inode *inode, struct file *filp);
80static unsigned int gpio_poll(struct file *filp,
81 struct poll_table_struct *wait);
82
83/* private data per open() of this driver */
84
85struct gpio_private {
86 struct gpio_private *next;
87 /* The IO_CFG_WRITE_MODE_VALUE only support 8 bits: */
88 unsigned char clk_mask;
89 unsigned char data_mask;
90 unsigned char write_msb;
91 unsigned char pad1;
92 /* These fields are generic */
93 unsigned long highalarm, lowalarm;
94 wait_queue_head_t alarm_wq;
95 int minor;
96};
97
98static void gpio_set_alarm(struct gpio_private *priv);
99static int gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
100static int gpio_pwm_ioctl(struct gpio_private *priv, unsigned int cmd,
101 unsigned long arg);
102
103
104/* linked list of alarms to check for */
105
106static struct gpio_private *alarmlist;
107
108static int wanted_interrupts;
109
110static DEFINE_SPINLOCK(gpio_lock);
111
112#define NUM_PORTS (GPIO_MINOR_LAST+1)
113#define GIO_REG_RD_ADDR(reg) \
114 (unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg)
115#define GIO_REG_WR_ADDR(reg) \
116 (unsigned long *)(regi_gio + REG_WR_ADDR_gio_##reg)
117static unsigned long led_dummy;
118static unsigned long port_d_dummy; /* Only input on Artpec-3 */
119#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
120static unsigned long port_e_dummy; /* Non existent on Artpec-3 */
121static unsigned long virtual_dummy;
122static unsigned long virtual_rw_pv_oe = CONFIG_ETRAX_DEF_GIO_PV_OE;
123static unsigned short cached_virtual_gpio_read;
124#endif
125
126static unsigned long *data_out[NUM_PORTS] = {
127 GIO_REG_WR_ADDR(rw_pa_dout),
128 GIO_REG_WR_ADDR(rw_pb_dout),
129 &led_dummy,
130 GIO_REG_WR_ADDR(rw_pc_dout),
131 &port_d_dummy,
132#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
133 &port_e_dummy,
134 &virtual_dummy,
135#endif
136};
137
138static unsigned long *data_in[NUM_PORTS] = {
139 GIO_REG_RD_ADDR(r_pa_din),
140 GIO_REG_RD_ADDR(r_pb_din),
141 &led_dummy,
142 GIO_REG_RD_ADDR(r_pc_din),
143 GIO_REG_RD_ADDR(r_pd_din),
144#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
145 &port_e_dummy,
146 &virtual_dummy,
147#endif
148};
149
150static unsigned long changeable_dir[NUM_PORTS] = {
151 CONFIG_ETRAX_PA_CHANGEABLE_DIR,
152 CONFIG_ETRAX_PB_CHANGEABLE_DIR,
153 0,
154 CONFIG_ETRAX_PC_CHANGEABLE_DIR,
155 0,
156#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
157 0,
158 CONFIG_ETRAX_PV_CHANGEABLE_DIR,
159#endif
160};
161
162static unsigned long changeable_bits[NUM_PORTS] = {
163 CONFIG_ETRAX_PA_CHANGEABLE_BITS,
164 CONFIG_ETRAX_PB_CHANGEABLE_BITS,
165 0,
166 CONFIG_ETRAX_PC_CHANGEABLE_BITS,
167 0,
168#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
169 0,
170 CONFIG_ETRAX_PV_CHANGEABLE_BITS,
171#endif
172};
173
174static unsigned long *dir_oe[NUM_PORTS] = {
175 GIO_REG_WR_ADDR(rw_pa_oe),
176 GIO_REG_WR_ADDR(rw_pb_oe),
177 &led_dummy,
178 GIO_REG_WR_ADDR(rw_pc_oe),
179 &port_d_dummy,
180#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
181 &port_e_dummy,
182 &virtual_rw_pv_oe,
183#endif
184};
185
186static void gpio_set_alarm(struct gpio_private *priv)
187{
188 int bit;
189 int intr_cfg;
190 int mask;
191 int pins;
192 unsigned long flags;
193
194 spin_lock_irqsave(&gpio_lock, flags);
195 intr_cfg = REG_RD_INT(gio, regi_gio, rw_intr_cfg);
196 pins = REG_RD_INT(gio, regi_gio, rw_intr_pins);
197 mask = REG_RD_INT(gio, regi_gio, rw_intr_mask) & I2C_INTERRUPT_BITS;
198
199 for (bit = 0; bit < 32; bit++) {
200 int intr = bit % 8;
201 int pin = bit / 8;
202 if (priv->minor < GPIO_MINOR_LEDS)
203 pin += priv->minor * 4;
204 else
205 pin += (priv->minor - 1) * 4;
206
207 if (priv->highalarm & (1<<bit)) {
208 intr_cfg |= (regk_gio_hi << (intr * 3));
209 mask |= 1 << intr;
210 wanted_interrupts = mask & 0xff;
211 pins |= pin << (intr * 4);
212 } else if (priv->lowalarm & (1<<bit)) {
213 intr_cfg |= (regk_gio_lo << (intr * 3));
214 mask |= 1 << intr;
215 wanted_interrupts = mask & 0xff;
216 pins |= pin << (intr * 4);
217 }
218 }
219
220 REG_WR_INT(gio, regi_gio, rw_intr_cfg, intr_cfg);
221 REG_WR_INT(gio, regi_gio, rw_intr_pins, pins);
222 REG_WR_INT(gio, regi_gio, rw_intr_mask, mask);
223
224 spin_unlock_irqrestore(&gpio_lock, flags);
225}
226
227static unsigned int gpio_poll(struct file *file, struct poll_table_struct *wait)
228{
229 unsigned int mask = 0;
230 struct gpio_private *priv = file->private_data;
231 unsigned long data;
232 unsigned long tmp;
233
234 if (priv->minor >= GPIO_MINOR_PWM0 &&
235 priv->minor <= GPIO_MINOR_LAST_PWM)
236 return 0;
237
238 poll_wait(file, &priv->alarm_wq, wait);
239 if (priv->minor <= GPIO_MINOR_D) {
240 data = readl(data_in[priv->minor]);
241 REG_WR_INT(gio, regi_gio, rw_ack_intr, wanted_interrupts);
242 tmp = REG_RD_INT(gio, regi_gio, rw_intr_mask);
243 tmp &= I2C_INTERRUPT_BITS;
244 tmp |= wanted_interrupts;
245 REG_WR_INT(gio, regi_gio, rw_intr_mask, tmp);
246 } else
247 return 0;
248
249 if ((data & priv->highalarm) || (~data & priv->lowalarm))
250 mask = POLLIN|POLLRDNORM;
251
252 DP(printk(KERN_DEBUG "gpio_poll ready: mask 0x%08X\n", mask));
253 return mask;
254}
255
256static irqreturn_t gpio_interrupt(int irq, void *dev_id)
257{
258 reg_gio_rw_intr_mask intr_mask;
259 reg_gio_r_masked_intr masked_intr;
260 reg_gio_rw_ack_intr ack_intr;
261 unsigned long flags;
262 unsigned long tmp;
263 unsigned long tmp2;
264#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
265 unsigned char enable_gpiov_ack = 0;
266#endif
267
268 /* Find what PA interrupts are active */
269 masked_intr = REG_RD(gio, regi_gio, r_masked_intr);
270 tmp = REG_TYPE_CONV(unsigned long, reg_gio_r_masked_intr, masked_intr);
271
272 /* Find those that we have enabled */
273 spin_lock_irqsave(&gpio_lock, flags);
274 tmp &= wanted_interrupts;
275 spin_unlock_irqrestore(&gpio_lock, flags);
276
277#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
278 /* Something changed on virtual GPIO. Interrupt is acked by
279 * reading the device.
280 */
281 if (tmp & (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN)) {
282 i2c_read(VIRT_I2C_ADDR, (void *)&cached_virtual_gpio_read,
283 sizeof(cached_virtual_gpio_read));
284 enable_gpiov_ack = 1;
285 }
286#endif
287
288 /* Ack them */
289 ack_intr = REG_TYPE_CONV(reg_gio_rw_ack_intr, unsigned long, tmp);
290 REG_WR(gio, regi_gio, rw_ack_intr, ack_intr);
291
292 /* Disable those interrupts.. */
293 intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
294 tmp2 = REG_TYPE_CONV(unsigned long, reg_gio_rw_intr_mask, intr_mask);
295 tmp2 &= ~tmp;
296#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
297 /* Do not disable interrupt on virtual GPIO. Changes on virtual
298 * pins are only noticed by an interrupt.
299 */
300 if (enable_gpiov_ack)
301 tmp2 |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
302#endif
303 intr_mask = REG_TYPE_CONV(reg_gio_rw_intr_mask, unsigned long, tmp2);
304 REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
305
306 return IRQ_RETVAL(tmp);
307}
308
309static void gpio_write_bit(unsigned long *port, unsigned char data, int bit,
310 unsigned char clk_mask, unsigned char data_mask)
311{
312 unsigned long shadow = readl(port) & ~clk_mask;
313 writel(shadow, port);
314 if (data & 1 << bit)
315 shadow |= data_mask;
316 else
317 shadow &= ~data_mask;
318 writel(shadow, port);
319 /* For FPGA: min 5.0ns (DCC) before CCLK high */
320 shadow |= clk_mask;
321 writel(shadow, port);
322}
323
324static void gpio_write_byte(struct gpio_private *priv, unsigned long *port,
325 unsigned char data)
326{
327 int i;
328
329 if (priv->write_msb)
330 for (i = 7; i >= 0; i--)
331 gpio_write_bit(port, data, i, priv->clk_mask,
332 priv->data_mask);
333 else
334 for (i = 0; i <= 7; i++)
335 gpio_write_bit(port, data, i, priv->clk_mask,
336 priv->data_mask);
337}
338
339
340static ssize_t gpio_write(struct file *file, const char __user *buf,
341 size_t count, loff_t *off)
342{
343 struct gpio_private *priv = file->private_data;
344 unsigned long flags;
345 ssize_t retval = count;
346 /* Only bits 0-7 may be used for write operations but allow all
347 devices except leds... */
348#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
349 if (priv->minor == GPIO_MINOR_V)
350 return -EFAULT;
351#endif
352 if (priv->minor == GPIO_MINOR_LEDS)
353 return -EFAULT;
354
355 if (priv->minor >= GPIO_MINOR_PWM0 &&
356 priv->minor <= GPIO_MINOR_LAST_PWM)
357 return -EFAULT;
358
359 if (!access_ok(VERIFY_READ, buf, count))
360 return -EFAULT;
361
362 /* It must have been configured using the IO_CFG_WRITE_MODE */
363 /* Perhaps a better error code? */
364 if (priv->clk_mask == 0 || priv->data_mask == 0)
365 return -EPERM;
366
367 D(printk(KERN_DEBUG "gpio_write: %lu to data 0x%02X clk 0x%02X "
368 "msb: %i\n",
369 count, priv->data_mask, priv->clk_mask, priv->write_msb));
370
371 spin_lock_irqsave(&gpio_lock, flags);
372
373 while (count--)
374 gpio_write_byte(priv, data_out[priv->minor], *buf++);
375
376 spin_unlock_irqrestore(&gpio_lock, flags);
377 return retval;
378}
379
380static int gpio_open(struct inode *inode, struct file *filp)
381{
382 struct gpio_private *priv;
383 int p = iminor(inode);
384
385 if (p > GPIO_MINOR_LAST_PWM ||
386 (p > GPIO_MINOR_LAST && p < GPIO_MINOR_PWM0))
387 return -EINVAL;
388
389 priv = kmalloc(sizeof(struct gpio_private), GFP_KERNEL);
390
391 if (!priv)
392 return -ENOMEM;
393
394 mutex_lock(&gpio_mutex);
395 memset(priv, 0, sizeof(*priv));
396
397 priv->minor = p;
398 filp->private_data = priv;
399
400 /* initialize the io/alarm struct, not for PWM ports though */
401 if (p <= GPIO_MINOR_LAST) {
402
403 priv->clk_mask = 0;
404 priv->data_mask = 0;
405 priv->highalarm = 0;
406 priv->lowalarm = 0;
407
408 init_waitqueue_head(&priv->alarm_wq);
409
410 /* link it into our alarmlist */
411 spin_lock_irq(&gpio_lock);
412 priv->next = alarmlist;
413 alarmlist = priv;
414 spin_unlock_irq(&gpio_lock);
415 }
416
417 mutex_unlock(&gpio_mutex);
418 return 0;
419}
420
421static int gpio_release(struct inode *inode, struct file *filp)
422{
423 struct gpio_private *p;
424 struct gpio_private *todel;
425 /* local copies while updating them: */
426 unsigned long a_high, a_low;
427
428 /* prepare to free private structure */
429 todel = filp->private_data;
430
431 /* unlink from alarmlist - only for non-PWM ports though */
432 if (todel->minor <= GPIO_MINOR_LAST) {
433 spin_lock_irq(&gpio_lock);
434 p = alarmlist;
435
436 if (p == todel)
437 alarmlist = todel->next;
438 else {
439 while (p->next != todel)
440 p = p->next;
441 p->next = todel->next;
442 }
443
444 /* Check if there are still any alarms set */
445 p = alarmlist;
446 a_high = 0;
447 a_low = 0;
448 while (p) {
449 if (p->minor == GPIO_MINOR_A) {
450#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
451 p->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
452#endif
453 a_high |= p->highalarm;
454 a_low |= p->lowalarm;
455 }
456
457 p = p->next;
458 }
459
460#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
461 /* Variable 'a_low' needs to be set here again
462 * to ensure that interrupt for virtual GPIO is handled.
463 */
464 a_low |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
465#endif
466
467 spin_unlock_irq(&gpio_lock);
468 }
469 kfree(todel);
470
471 return 0;
472}
473
474/* Main device API. ioctl's to read/set/clear bits, as well as to
475 * set alarms to wait for using a subsequent select().
476 */
477
478inline unsigned long setget_input(struct gpio_private *priv, unsigned long arg)
479{
480 /* Set direction 0=unchanged 1=input,
481 * return mask with 1=input
482 */
483 unsigned long flags;
484 unsigned long dir_shadow;
485
486 spin_lock_irqsave(&gpio_lock, flags);
487
488 dir_shadow = readl(dir_oe[priv->minor]) &
489 ~(arg & changeable_dir[priv->minor]);
490 writel(dir_shadow, dir_oe[priv->minor]);
491
492 spin_unlock_irqrestore(&gpio_lock, flags);
493
494 if (priv->minor == GPIO_MINOR_C)
495 dir_shadow ^= 0xFFFF; /* Only 16 bits */
496#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
497 else if (priv->minor == GPIO_MINOR_V)
498 dir_shadow ^= 0xFFFF; /* Only 16 bits */
499#endif
500 else
501 dir_shadow ^= 0xFFFFFFFF; /* PA, PB and PD 32 bits */
502
503 return dir_shadow;
504
505} /* setget_input */
506
507static inline unsigned long setget_output(struct gpio_private *priv,
508 unsigned long arg)
509{
510 unsigned long flags;
511 unsigned long dir_shadow;
512
513 spin_lock_irqsave(&gpio_lock, flags);
514
515 dir_shadow = readl(dir_oe[priv->minor]) |
516 (arg & changeable_dir[priv->minor]);
517 writel(dir_shadow, dir_oe[priv->minor]);
518
519 spin_unlock_irqrestore(&gpio_lock, flags);
520 return dir_shadow;
521} /* setget_output */
522
523static long gpio_ioctl_unlocked(struct file *file,
524 unsigned int cmd, unsigned long arg)
525{
526 unsigned long flags;
527 unsigned long val;
528 unsigned long shadow;
529 struct gpio_private *priv = file->private_data;
530
531 if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
532 return -ENOTTY;
533
534 /* Check for special ioctl handlers first */
535
536#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
537 if (priv->minor == GPIO_MINOR_V)
538 return virtual_gpio_ioctl(file, cmd, arg);
539#endif
540
541 if (priv->minor == GPIO_MINOR_LEDS)
542 return gpio_leds_ioctl(cmd, arg);
543
544 if (priv->minor >= GPIO_MINOR_PWM0 &&
545 priv->minor <= GPIO_MINOR_LAST_PWM)
546 return gpio_pwm_ioctl(priv, cmd, arg);
547
548 switch (_IOC_NR(cmd)) {
549 case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
550 /* Read the port. */
551 return readl(data_in[priv->minor]);
552 case IO_SETBITS:
553 spin_lock_irqsave(&gpio_lock, flags);
554 /* Set changeable bits with a 1 in arg. */
555 shadow = readl(data_out[priv->minor]) |
556 (arg & changeable_bits[priv->minor]);
557 writel(shadow, data_out[priv->minor]);
558 spin_unlock_irqrestore(&gpio_lock, flags);
559 break;
560 case IO_CLRBITS:
561 spin_lock_irqsave(&gpio_lock, flags);
562 /* Clear changeable bits with a 1 in arg. */
563 shadow = readl(data_out[priv->minor]) &
564 ~(arg & changeable_bits[priv->minor]);
565 writel(shadow, data_out[priv->minor]);
566 spin_unlock_irqrestore(&gpio_lock, flags);
567 break;
568 case IO_HIGHALARM:
569 /* Set alarm when bits with 1 in arg go high. */
570 priv->highalarm |= arg;
571 gpio_set_alarm(priv);
572 break;
573 case IO_LOWALARM:
574 /* Set alarm when bits with 1 in arg go low. */
575 priv->lowalarm |= arg;
576 gpio_set_alarm(priv);
577 break;
578 case IO_CLRALARM:
579 /* Clear alarm for bits with 1 in arg. */
580 priv->highalarm &= ~arg;
581 priv->lowalarm &= ~arg;
582 gpio_set_alarm(priv);
583 break;
584 case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
585 /* Read direction 0=input 1=output */
586 return readl(dir_oe[priv->minor]);
587
588 case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
589 /* Set direction 0=unchanged 1=input,
590 * return mask with 1=input
591 */
592 return setget_input(priv, arg);
593
594 case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
595 /* Set direction 0=unchanged 1=output,
596 * return mask with 1=output
597 */
598 return setget_output(priv, arg);
599
600 case IO_CFG_WRITE_MODE:
601 {
602 int res = -EPERM;
603 unsigned long dir_shadow, clk_mask, data_mask, write_msb;
604
605 clk_mask = arg & 0xFF;
606 data_mask = (arg >> 8) & 0xFF;
607 write_msb = (arg >> 16) & 0x01;
608
609 /* Check if we're allowed to change the bits and
610 * the direction is correct
611 */
612 spin_lock_irqsave(&gpio_lock, flags);
613 dir_shadow = readl(dir_oe[priv->minor]);
614 if ((clk_mask & changeable_bits[priv->minor]) &&
615 (data_mask & changeable_bits[priv->minor]) &&
616 (clk_mask & dir_shadow) &&
617 (data_mask & dir_shadow)) {
618 priv->clk_mask = clk_mask;
619 priv->data_mask = data_mask;
620 priv->write_msb = write_msb;
621 res = 0;
622 }
623 spin_unlock_irqrestore(&gpio_lock, flags);
624
625 return res;
626 }
627 case IO_READ_INBITS:
628 /* *arg is result of reading the input pins */
629 val = readl(data_in[priv->minor]);
630 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
631 return -EFAULT;
632 return 0;
633 case IO_READ_OUTBITS:
634 /* *arg is result of reading the output shadow */
635 val = *data_out[priv->minor];
636 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
637 return -EFAULT;
638 break;
639 case IO_SETGET_INPUT:
640 /* bits set in *arg is set to input,
641 * *arg updated with current input pins.
642 */
643 if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
644 return -EFAULT;
645 val = setget_input(priv, val);
646 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
647 return -EFAULT;
648 break;
649 case IO_SETGET_OUTPUT:
650 /* bits set in *arg is set to output,
651 * *arg updated with current output pins.
652 */
653 if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
654 return -EFAULT;
655 val = setget_output(priv, val);
656 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
657 return -EFAULT;
658 break;
659 default:
660 return -EINVAL;
661 } /* switch */
662
663 return 0;
664}
665
666static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
667{
668 long ret;
669
670 mutex_lock(&gpio_mutex);
671 ret = gpio_ioctl_unlocked(file, cmd, arg);
672 mutex_unlock(&gpio_mutex);
673
674 return ret;
675}
676
677#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
678static int virtual_gpio_ioctl(struct file *file, unsigned int cmd,
679 unsigned long arg)
680{
681 unsigned long flags;
682 unsigned short val;
683 unsigned short shadow;
684 struct gpio_private *priv = file->private_data;
685
686 switch (_IOC_NR(cmd)) {
687 case IO_SETBITS:
688 spin_lock_irqsave(&gpio_lock, flags);
689 /* Set changeable bits with a 1 in arg. */
690 i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
691 shadow |= ~readl(dir_oe[priv->minor]) |
692 (arg & changeable_bits[priv->minor]);
693 i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
694 spin_unlock_irqrestore(&gpio_lock, flags);
695 break;
696 case IO_CLRBITS:
697 spin_lock_irqsave(&gpio_lock, flags);
698 /* Clear changeable bits with a 1 in arg. */
699 i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
700 shadow |= ~readl(dir_oe[priv->minor]) &
701 ~(arg & changeable_bits[priv->minor]);
702 i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
703 spin_unlock_irqrestore(&gpio_lock, flags);
704 break;
705 case IO_HIGHALARM:
706 /* Set alarm when bits with 1 in arg go high. */
707 priv->highalarm |= arg;
708 break;
709 case IO_LOWALARM:
710 /* Set alarm when bits with 1 in arg go low. */
711 priv->lowalarm |= arg;
712 break;
713 case IO_CLRALARM:
714 /* Clear alarm for bits with 1 in arg. */
715 priv->highalarm &= ~arg;
716 priv->lowalarm &= ~arg;
717 break;
718 case IO_CFG_WRITE_MODE:
719 {
720 unsigned long dir_shadow;
721 dir_shadow = readl(dir_oe[priv->minor]);
722
723 priv->clk_mask = arg & 0xFF;
724 priv->data_mask = (arg >> 8) & 0xFF;
725 priv->write_msb = (arg >> 16) & 0x01;
726 /* Check if we're allowed to change the bits and
727 * the direction is correct
728 */
729 if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
730 (priv->data_mask & changeable_bits[priv->minor]) &&
731 (priv->clk_mask & dir_shadow) &&
732 (priv->data_mask & dir_shadow))) {
733 priv->clk_mask = 0;
734 priv->data_mask = 0;
735 return -EPERM;
736 }
737 break;
738 }
739 case IO_READ_INBITS:
740 /* *arg is result of reading the input pins */
741 val = cached_virtual_gpio_read & ~readl(dir_oe[priv->minor]);
742 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
743 return -EFAULT;
744 return 0;
745
746 case IO_READ_OUTBITS:
747 /* *arg is result of reading the output shadow */
748 i2c_read(VIRT_I2C_ADDR, (void *)&val, sizeof(val));
749 val &= readl(dir_oe[priv->minor]);
750 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
751 return -EFAULT;
752 break;
753 case IO_SETGET_INPUT:
754 {
755 /* bits set in *arg is set to input,
756 * *arg updated with current input pins.
757 */
758 unsigned short input_mask = ~readl(dir_oe[priv->minor]);
759 if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
760 return -EFAULT;
761 val = setget_input(priv, val);
762 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
763 return -EFAULT;
764 if ((input_mask & val) != input_mask) {
765 /* Input pins changed. All ports desired as input
766 * should be set to logic 1.
767 */
768 unsigned short change = input_mask ^ val;
769 i2c_read(VIRT_I2C_ADDR, (void *)&shadow,
770 sizeof(shadow));
771 shadow &= ~change;
772 shadow |= val;
773 i2c_write(VIRT_I2C_ADDR, (void *)&shadow,
774 sizeof(shadow));
775 }
776 break;
777 }
778 case IO_SETGET_OUTPUT:
779 /* bits set in *arg is set to output,
780 * *arg updated with current output pins.
781 */
782 if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
783 return -EFAULT;
784 val = setget_output(priv, val);
785 if (copy_to_user((void __user *)arg, &val, sizeof(val)))
786 return -EFAULT;
787 break;
788 default:
789 return -EINVAL;
790 } /* switch */
791 return 0;
792}
793#endif /* CONFIG_ETRAX_VIRTUAL_GPIO */
794
795static int gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
796{
797 unsigned char green;
798 unsigned char red;
799
800 switch (_IOC_NR(cmd)) {
801 case IO_LEDACTIVE_SET:
802 green = ((unsigned char) arg) & 1;
803 red = (((unsigned char) arg) >> 1) & 1;
804 CRIS_LED_ACTIVE_SET_G(green);
805 CRIS_LED_ACTIVE_SET_R(red);
806 break;
807
808 default:
809 return -EINVAL;
810 } /* switch */
811
812 return 0;
813}
814
815static int gpio_pwm_set_mode(unsigned long arg, int pwm_port)
816{
817 int pinmux_pwm = pinmux_pwm0 + pwm_port;
818 int mode;
819 reg_gio_rw_pwm0_ctrl rw_pwm_ctrl = {
820 .ccd_val = 0,
821 .ccd_override = regk_gio_no,
822 .mode = regk_gio_no
823 };
824 int allocstatus;
825
826 if (get_user(mode, &((struct io_pwm_set_mode *) arg)->mode))
827 return -EFAULT;
828 rw_pwm_ctrl.mode = mode;
829 if (mode != PWM_OFF)
830 allocstatus = crisv32_pinmux_alloc_fixed(pinmux_pwm);
831 else
832 allocstatus = crisv32_pinmux_dealloc_fixed(pinmux_pwm);
833 if (allocstatus)
834 return allocstatus;
835 REG_WRITE(reg_gio_rw_pwm0_ctrl, REG_ADDR(gio, regi_gio, rw_pwm0_ctrl) +
836 12 * pwm_port, rw_pwm_ctrl);
837 return 0;
838}
839
840static int gpio_pwm_set_period(unsigned long arg, int pwm_port)
841{
842 struct io_pwm_set_period periods;
843 reg_gio_rw_pwm0_var rw_pwm_widths;
844
845 if (copy_from_user(&periods, (void __user *)arg, sizeof(periods)))
846 return -EFAULT;
847 if (periods.lo > 8191 || periods.hi > 8191)
848 return -EINVAL;
849 rw_pwm_widths.lo = periods.lo;
850 rw_pwm_widths.hi = periods.hi;
851 REG_WRITE(reg_gio_rw_pwm0_var, REG_ADDR(gio, regi_gio, rw_pwm0_var) +
852 12 * pwm_port, rw_pwm_widths);
853 return 0;
854}
855
856static int gpio_pwm_set_duty(unsigned long arg, int pwm_port)
857{
858 unsigned int duty;
859 reg_gio_rw_pwm0_data rw_pwm_duty;
860
861 if (get_user(duty, &((struct io_pwm_set_duty *) arg)->duty))
862 return -EFAULT;
863 if (duty > 255)
864 return -EINVAL;
865 rw_pwm_duty.data = duty;
866 REG_WRITE(reg_gio_rw_pwm0_data, REG_ADDR(gio, regi_gio, rw_pwm0_data) +
867 12 * pwm_port, rw_pwm_duty);
868 return 0;
869}
870
871static int gpio_pwm_ioctl(struct gpio_private *priv, unsigned int cmd,
872 unsigned long arg)
873{
874 int pwm_port = priv->minor - GPIO_MINOR_PWM0;
875
876 switch (_IOC_NR(cmd)) {
877 case IO_PWM_SET_MODE:
878 return gpio_pwm_set_mode(arg, pwm_port);
879 case IO_PWM_SET_PERIOD:
880 return gpio_pwm_set_period(arg, pwm_port);
881 case IO_PWM_SET_DUTY:
882 return gpio_pwm_set_duty(arg, pwm_port);
883 default:
884 return -EINVAL;
885 }
886 return 0;
887}
888
889static const struct file_operations gpio_fops = {
890 .owner = THIS_MODULE,
891 .poll = gpio_poll,
892 .unlocked_ioctl = gpio_ioctl,
893 .write = gpio_write,
894 .open = gpio_open,
895 .release = gpio_release,
896 .llseek = noop_llseek,
897};
898
899#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
900static void __init virtual_gpio_init(void)
901{
902 reg_gio_rw_intr_cfg intr_cfg;
903 reg_gio_rw_intr_mask intr_mask;
904 unsigned short shadow;
905
906 shadow = ~virtual_rw_pv_oe; /* Input ports should be set to logic 1 */
907 shadow |= CONFIG_ETRAX_DEF_GIO_PV_OUT;
908 i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
909
910 /* Set interrupt mask and on what state the interrupt shall trigger.
911 * For virtual gpio the interrupt shall trigger on logic '0'.
912 */
913 intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
914 intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
915
916 switch (CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN) {
917 case 0:
918 intr_cfg.pa0 = regk_gio_lo;
919 intr_mask.pa0 = regk_gio_yes;
920 break;
921 case 1:
922 intr_cfg.pa1 = regk_gio_lo;
923 intr_mask.pa1 = regk_gio_yes;
924 break;
925 case 2:
926 intr_cfg.pa2 = regk_gio_lo;
927 intr_mask.pa2 = regk_gio_yes;
928 break;
929 case 3:
930 intr_cfg.pa3 = regk_gio_lo;
931 intr_mask.pa3 = regk_gio_yes;
932 break;
933 case 4:
934 intr_cfg.pa4 = regk_gio_lo;
935 intr_mask.pa4 = regk_gio_yes;
936 break;
937 case 5:
938 intr_cfg.pa5 = regk_gio_lo;
939 intr_mask.pa5 = regk_gio_yes;
940 break;
941 case 6:
942 intr_cfg.pa6 = regk_gio_lo;
943 intr_mask.pa6 = regk_gio_yes;
944 break;
945 case 7:
946 intr_cfg.pa7 = regk_gio_lo;
947 intr_mask.pa7 = regk_gio_yes;
948 break;
949 }
950
951 REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
952 REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
953}
954#endif
955
956/* main driver initialization routine, called from mem.c */
957
958static int __init gpio_init(void)
959{
960 int res, res2;
961
962 printk(KERN_INFO "ETRAX FS GPIO driver v2.7, (c) 2003-2008 "
963 "Axis Communications AB\n");
964
965 /* do the formalities */
966
967 res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
968 if (res < 0) {
969 printk(KERN_ERR "gpio: couldn't get a major number.\n");
970 return res;
971 }
972
973 /* Clear all leds */
974 CRIS_LED_NETWORK_GRP0_SET(0);
975 CRIS_LED_NETWORK_GRP1_SET(0);
976 CRIS_LED_ACTIVE_SET(0);
977 CRIS_LED_DISK_READ(0);
978 CRIS_LED_DISK_WRITE(0);
979
980 res2 = request_irq(GIO_INTR_VECT, gpio_interrupt,
981 IRQF_SHARED, "gpio", &alarmlist);
982 if (res2) {
983 printk(KERN_ERR "err: irq for gpio\n");
984 return res2;
985 }
986
987 /* No IRQs by default. */
988 REG_WR_INT(gio, regi_gio, rw_intr_pins, 0);
989
990#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
991 virtual_gpio_init();
992#endif
993
994 return res;
995}
996
997/* this makes sure that gpio_init is called during kernel boot */
998
999module_init(gpio_init);
diff --git a/arch/cris/arch-v32/drivers/mach-fs/Makefile b/arch/cris/arch-v32/drivers/mach-fs/Makefile
index 5c6d2a2a080e..59028d0b981c 100644
--- a/arch/cris/arch-v32/drivers/mach-fs/Makefile
+++ b/arch/cris/arch-v32/drivers/mach-fs/Makefile
@@ -3,4 +3,3 @@
3# 3#
4 4
5obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o 5obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o
6obj-$(CONFIG_ETRAX_GPIO) += gpio.o
diff --git a/arch/cris/arch-v32/drivers/mach-fs/gpio.c b/arch/cris/arch-v32/drivers/mach-fs/gpio.c
deleted file mode 100644
index 72968fbf814b..000000000000
--- a/arch/cris/arch-v32/drivers/mach-fs/gpio.c
+++ /dev/null
@@ -1,978 +0,0 @@
1/*
2 * ETRAX CRISv32 general port I/O device
3 *
4 * Copyright (c) 1999-2006 Axis Communications AB
5 *
6 * Authors: Bjorn Wesen (initial version)
7 * Ola Knutsson (LED handling)
8 * Johan Adolfsson (read/set directions, write, port G,
9 * port to ETRAX FS.
10 *
11 */
12
13#include <linux/module.h>
14#include <linux/sched.h>
15#include <linux/slab.h>
16#include <linux/ioport.h>
17#include <linux/errno.h>
18#include <linux/kernel.h>
19#include <linux/fs.h>
20#include <linux/string.h>
21#include <linux/poll.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/spinlock.h>
25#include <linux/mutex.h>
26
27#include <asm/etraxgpio.h>
28#include <hwregs/reg_map.h>
29#include <hwregs/reg_rdwr.h>
30#include <hwregs/gio_defs.h>
31#include <hwregs/intr_vect_defs.h>
32#include <asm/io.h>
33#include <asm/irq.h>
34
35#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
36#include "../i2c.h"
37
38#define VIRT_I2C_ADDR 0x40
39#endif
40
41/* The following gio ports on ETRAX FS is available:
42 * pa 8 bits, supports interrupts off, hi, low, set, posedge, negedge anyedge
43 * pb 18 bits
44 * pc 18 bits
45 * pd 18 bits
46 * pe 18 bits
47 * each port has a rw_px_dout, r_px_din and rw_px_oe register.
48 */
49
50#define GPIO_MAJOR 120 /* experimental MAJOR number */
51
52#define D(x)
53
54#if 0
55static int dp_cnt;
56#define DP(x) \
57 do { \
58 dp_cnt++; \
59 if (dp_cnt % 1000 == 0) \
60 x; \
61 } while (0)
62#else
63#define DP(x)
64#endif
65
66static DEFINE_MUTEX(gpio_mutex);
67static char gpio_name[] = "etrax gpio";
68
69#if 0
70static wait_queue_head_t *gpio_wq;
71#endif
72
73#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
74static int virtual_gpio_ioctl(struct file *file, unsigned int cmd,
75 unsigned long arg);
76#endif
77static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
78static ssize_t gpio_write(struct file *file, const char *buf, size_t count,
79 loff_t *off);
80static int gpio_open(struct inode *inode, struct file *filp);
81static int gpio_release(struct inode *inode, struct file *filp);
82static unsigned int gpio_poll(struct file *filp,
83 struct poll_table_struct *wait);
84
85/* private data per open() of this driver */
86
87struct gpio_private {
88 struct gpio_private *next;
89 /* The IO_CFG_WRITE_MODE_VALUE only support 8 bits: */
90 unsigned char clk_mask;
91 unsigned char data_mask;
92 unsigned char write_msb;
93 unsigned char pad1;
94 /* These fields are generic */
95 unsigned long highalarm, lowalarm;
96 wait_queue_head_t alarm_wq;
97 int minor;
98};
99
100/* linked list of alarms to check for */
101
102static struct gpio_private *alarmlist;
103
104static int gpio_some_alarms; /* Set if someone uses alarm */
105static unsigned long gpio_pa_high_alarms;
106static unsigned long gpio_pa_low_alarms;
107
108static DEFINE_SPINLOCK(alarm_lock);
109
110#define NUM_PORTS (GPIO_MINOR_LAST+1)
111#define GIO_REG_RD_ADDR(reg) \
112 (volatile unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg)
113#define GIO_REG_WR_ADDR(reg) \
114 (volatile unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg)
115unsigned long led_dummy;
116#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
117static unsigned long virtual_dummy;
118static unsigned long virtual_rw_pv_oe = CONFIG_ETRAX_DEF_GIO_PV_OE;
119static unsigned short cached_virtual_gpio_read;
120#endif
121
122static volatile unsigned long *data_out[NUM_PORTS] = {
123 GIO_REG_WR_ADDR(rw_pa_dout),
124 GIO_REG_WR_ADDR(rw_pb_dout),
125 &led_dummy,
126 GIO_REG_WR_ADDR(rw_pc_dout),
127 GIO_REG_WR_ADDR(rw_pd_dout),
128 GIO_REG_WR_ADDR(rw_pe_dout),
129#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
130 &virtual_dummy,
131#endif
132};
133
134static volatile unsigned long *data_in[NUM_PORTS] = {
135 GIO_REG_RD_ADDR(r_pa_din),
136 GIO_REG_RD_ADDR(r_pb_din),
137 &led_dummy,
138 GIO_REG_RD_ADDR(r_pc_din),
139 GIO_REG_RD_ADDR(r_pd_din),
140 GIO_REG_RD_ADDR(r_pe_din),
141#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
142 &virtual_dummy,
143#endif
144};
145
146static unsigned long changeable_dir[NUM_PORTS] = {
147 CONFIG_ETRAX_PA_CHANGEABLE_DIR,
148 CONFIG_ETRAX_PB_CHANGEABLE_DIR,
149 0,
150 CONFIG_ETRAX_PC_CHANGEABLE_DIR,
151 CONFIG_ETRAX_PD_CHANGEABLE_DIR,
152 CONFIG_ETRAX_PE_CHANGEABLE_DIR,
153#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
154 CONFIG_ETRAX_PV_CHANGEABLE_DIR,
155#endif
156};
157
158static unsigned long changeable_bits[NUM_PORTS] = {
159 CONFIG_ETRAX_PA_CHANGEABLE_BITS,
160 CONFIG_ETRAX_PB_CHANGEABLE_BITS,
161 0,
162 CONFIG_ETRAX_PC_CHANGEABLE_BITS,
163 CONFIG_ETRAX_PD_CHANGEABLE_BITS,
164 CONFIG_ETRAX_PE_CHANGEABLE_BITS,
165#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
166 CONFIG_ETRAX_PV_CHANGEABLE_BITS,
167#endif
168};
169
170static volatile unsigned long *dir_oe[NUM_PORTS] = {
171 GIO_REG_WR_ADDR(rw_pa_oe),
172 GIO_REG_WR_ADDR(rw_pb_oe),
173 &led_dummy,
174 GIO_REG_WR_ADDR(rw_pc_oe),
175 GIO_REG_WR_ADDR(rw_pd_oe),
176 GIO_REG_WR_ADDR(rw_pe_oe),
177#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
178 &virtual_rw_pv_oe,
179#endif
180};
181
182
183
184static unsigned int gpio_poll(struct file *file, struct poll_table_struct *wait)
185{
186 unsigned int mask = 0;
187 struct gpio_private *priv = file->private_data;
188 unsigned long data;
189 poll_wait(file, &priv->alarm_wq, wait);
190 if (priv->minor == GPIO_MINOR_A) {
191 reg_gio_rw_intr_cfg intr_cfg;
192 unsigned long tmp;
193 unsigned long flags;
194
195 local_irq_save(flags);
196 data = REG_TYPE_CONV(unsigned long, reg_gio_r_pa_din,
197 REG_RD(gio, regi_gio, r_pa_din));
198 /* PA has support for interrupt
199 * lets activate high for those low and with highalarm set
200 */
201 intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
202
203 tmp = ~data & priv->highalarm & 0xFF;
204 if (tmp & (1 << 0))
205 intr_cfg.pa0 = regk_gio_hi;
206 if (tmp & (1 << 1))
207 intr_cfg.pa1 = regk_gio_hi;
208 if (tmp & (1 << 2))
209 intr_cfg.pa2 = regk_gio_hi;
210 if (tmp & (1 << 3))
211 intr_cfg.pa3 = regk_gio_hi;
212 if (tmp & (1 << 4))
213 intr_cfg.pa4 = regk_gio_hi;
214 if (tmp & (1 << 5))
215 intr_cfg.pa5 = regk_gio_hi;
216 if (tmp & (1 << 6))
217 intr_cfg.pa6 = regk_gio_hi;
218 if (tmp & (1 << 7))
219 intr_cfg.pa7 = regk_gio_hi;
220 /*
221 * lets activate low for those high and with lowalarm set
222 */
223 tmp = data & priv->lowalarm & 0xFF;
224 if (tmp & (1 << 0))
225 intr_cfg.pa0 = regk_gio_lo;
226 if (tmp & (1 << 1))
227 intr_cfg.pa1 = regk_gio_lo;
228 if (tmp & (1 << 2))
229 intr_cfg.pa2 = regk_gio_lo;
230 if (tmp & (1 << 3))
231 intr_cfg.pa3 = regk_gio_lo;
232 if (tmp & (1 << 4))
233 intr_cfg.pa4 = regk_gio_lo;
234 if (tmp & (1 << 5))
235 intr_cfg.pa5 = regk_gio_lo;
236 if (tmp & (1 << 6))
237 intr_cfg.pa6 = regk_gio_lo;
238 if (tmp & (1 << 7))
239 intr_cfg.pa7 = regk_gio_lo;
240
241 REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
242 local_irq_restore(flags);
243 } else if (priv->minor <= GPIO_MINOR_E)
244 data = *data_in[priv->minor];
245 else
246 return 0;
247
248 if ((data & priv->highalarm) || (~data & priv->lowalarm))
249 mask = POLLIN|POLLRDNORM;
250
251 DP(printk(KERN_DEBUG "gpio_poll ready: mask 0x%08X\n", mask));
252 return mask;
253}
254
255int etrax_gpio_wake_up_check(void)
256{
257 struct gpio_private *priv;
258 unsigned long data = 0;
259 unsigned long flags;
260 int ret = 0;
261 spin_lock_irqsave(&alarm_lock, flags);
262 priv = alarmlist;
263 while (priv) {
264#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
265 if (priv->minor == GPIO_MINOR_V)
266 data = (unsigned long)cached_virtual_gpio_read;
267 else {
268 data = *data_in[priv->minor];
269 if (priv->minor == GPIO_MINOR_A)
270 priv->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
271 }
272#else
273 data = *data_in[priv->minor];
274#endif
275 if ((data & priv->highalarm) ||
276 (~data & priv->lowalarm)) {
277 DP(printk(KERN_DEBUG
278 "etrax_gpio_wake_up_check %i\n", priv->minor));
279 wake_up_interruptible(&priv->alarm_wq);
280 ret = 1;
281 }
282 priv = priv->next;
283 }
284 spin_unlock_irqrestore(&alarm_lock, flags);
285 return ret;
286}
287
288static irqreturn_t
289gpio_poll_timer_interrupt(int irq, void *dev_id)
290{
291 if (gpio_some_alarms)
292 return IRQ_RETVAL(etrax_gpio_wake_up_check());
293 return IRQ_NONE;
294}
295
296static irqreturn_t
297gpio_pa_interrupt(int irq, void *dev_id)
298{
299 reg_gio_rw_intr_mask intr_mask;
300 reg_gio_r_masked_intr masked_intr;
301 reg_gio_rw_ack_intr ack_intr;
302 unsigned long tmp;
303 unsigned long tmp2;
304#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
305 unsigned char enable_gpiov_ack = 0;
306#endif
307
308 /* Find what PA interrupts are active */
309 masked_intr = REG_RD(gio, regi_gio, r_masked_intr);
310 tmp = REG_TYPE_CONV(unsigned long, reg_gio_r_masked_intr, masked_intr);
311
312 /* Find those that we have enabled */
313 spin_lock(&alarm_lock);
314 tmp &= (gpio_pa_high_alarms | gpio_pa_low_alarms);
315 spin_unlock(&alarm_lock);
316
317#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
318 /* Something changed on virtual GPIO. Interrupt is acked by
319 * reading the device.
320 */
321 if (tmp & (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN)) {
322 i2c_read(VIRT_I2C_ADDR, (void *)&cached_virtual_gpio_read,
323 sizeof(cached_virtual_gpio_read));
324 enable_gpiov_ack = 1;
325 }
326#endif
327
328 /* Ack them */
329 ack_intr = REG_TYPE_CONV(reg_gio_rw_ack_intr, unsigned long, tmp);
330 REG_WR(gio, regi_gio, rw_ack_intr, ack_intr);
331
332 /* Disable those interrupts.. */
333 intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
334 tmp2 = REG_TYPE_CONV(unsigned long, reg_gio_rw_intr_mask, intr_mask);
335 tmp2 &= ~tmp;
336#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
337 /* Do not disable interrupt on virtual GPIO. Changes on virtual
338 * pins are only noticed by an interrupt.
339 */
340 if (enable_gpiov_ack)
341 tmp2 |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
342#endif
343 intr_mask = REG_TYPE_CONV(reg_gio_rw_intr_mask, unsigned long, tmp2);
344 REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
345
346 if (gpio_some_alarms)
347 return IRQ_RETVAL(etrax_gpio_wake_up_check());
348 return IRQ_NONE;
349}
350
351
352static ssize_t gpio_write(struct file *file, const char *buf, size_t count,
353 loff_t *off)
354{
355 struct gpio_private *priv = file->private_data;
356 unsigned char data, clk_mask, data_mask, write_msb;
357 unsigned long flags;
358 unsigned long shadow;
359 volatile unsigned long *port;
360 ssize_t retval = count;
361 /* Only bits 0-7 may be used for write operations but allow all
362 devices except leds... */
363#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
364 if (priv->minor == GPIO_MINOR_V)
365 return -EFAULT;
366#endif
367 if (priv->minor == GPIO_MINOR_LEDS)
368 return -EFAULT;
369
370 if (!access_ok(VERIFY_READ, buf, count))
371 return -EFAULT;
372 clk_mask = priv->clk_mask;
373 data_mask = priv->data_mask;
374 /* It must have been configured using the IO_CFG_WRITE_MODE */
375 /* Perhaps a better error code? */
376 if (clk_mask == 0 || data_mask == 0)
377 return -EPERM;
378 write_msb = priv->write_msb;
379 D(printk(KERN_DEBUG "gpio_write: %lu to data 0x%02X clk 0x%02X "
380 "msb: %i\n", count, data_mask, clk_mask, write_msb));
381 port = data_out[priv->minor];
382
383 while (count--) {
384 int i;
385 data = *buf++;
386 if (priv->write_msb) {
387 for (i = 7; i >= 0; i--) {
388 local_irq_save(flags);
389 shadow = *port;
390 *port = shadow &= ~clk_mask;
391 if (data & 1<<i)
392 *port = shadow |= data_mask;
393 else
394 *port = shadow &= ~data_mask;
395 /* For FPGA: min 5.0ns (DCC) before CCLK high */
396 *port = shadow |= clk_mask;
397 local_irq_restore(flags);
398 }
399 } else {
400 for (i = 0; i <= 7; i++) {
401 local_irq_save(flags);
402 shadow = *port;
403 *port = shadow &= ~clk_mask;
404 if (data & 1<<i)
405 *port = shadow |= data_mask;
406 else
407 *port = shadow &= ~data_mask;
408 /* For FPGA: min 5.0ns (DCC) before CCLK high */
409 *port = shadow |= clk_mask;
410 local_irq_restore(flags);
411 }
412 }
413 }
414 return retval;
415}
416
417
418
419static int
420gpio_open(struct inode *inode, struct file *filp)
421{
422 struct gpio_private *priv;
423 int p = iminor(inode);
424
425 if (p > GPIO_MINOR_LAST)
426 return -EINVAL;
427
428 priv = kzalloc(sizeof(struct gpio_private), GFP_KERNEL);
429 if (!priv)
430 return -ENOMEM;
431
432 mutex_lock(&gpio_mutex);
433
434 priv->minor = p;
435
436 /* initialize the io/alarm struct */
437
438 priv->clk_mask = 0;
439 priv->data_mask = 0;
440 priv->highalarm = 0;
441 priv->lowalarm = 0;
442 init_waitqueue_head(&priv->alarm_wq);
443
444 filp->private_data = (void *)priv;
445
446 /* link it into our alarmlist */
447 spin_lock_irq(&alarm_lock);
448 priv->next = alarmlist;
449 alarmlist = priv;
450 spin_unlock_irq(&alarm_lock);
451
452 mutex_unlock(&gpio_mutex);
453 return 0;
454}
455
456static int
457gpio_release(struct inode *inode, struct file *filp)
458{
459 struct gpio_private *p;
460 struct gpio_private *todel;
461 /* local copies while updating them: */
462 unsigned long a_high, a_low;
463 unsigned long some_alarms;
464
465 /* unlink from alarmlist and free the private structure */
466
467 spin_lock_irq(&alarm_lock);
468 p = alarmlist;
469 todel = filp->private_data;
470
471 if (p == todel) {
472 alarmlist = todel->next;
473 } else {
474 while (p->next != todel)
475 p = p->next;
476 p->next = todel->next;
477 }
478
479 kfree(todel);
480 /* Check if there are still any alarms set */
481 p = alarmlist;
482 some_alarms = 0;
483 a_high = 0;
484 a_low = 0;
485 while (p) {
486 if (p->minor == GPIO_MINOR_A) {
487#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
488 p->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
489#endif
490 a_high |= p->highalarm;
491 a_low |= p->lowalarm;
492 }
493
494 if (p->highalarm | p->lowalarm)
495 some_alarms = 1;
496 p = p->next;
497 }
498
499#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
500 /* Variables 'some_alarms' and 'a_low' needs to be set here again
501 * to ensure that interrupt for virtual GPIO is handled.
502 */
503 some_alarms = 1;
504 a_low |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
505#endif
506
507 gpio_some_alarms = some_alarms;
508 gpio_pa_high_alarms = a_high;
509 gpio_pa_low_alarms = a_low;
510 spin_unlock_irq(&alarm_lock);
511
512 return 0;
513}
514
515/* Main device API. ioctl's to read/set/clear bits, as well as to
516 * set alarms to wait for using a subsequent select().
517 */
518
519inline unsigned long setget_input(struct gpio_private *priv, unsigned long arg)
520{
521 /* Set direction 0=unchanged 1=input,
522 * return mask with 1=input
523 */
524 unsigned long flags;
525 unsigned long dir_shadow;
526
527 local_irq_save(flags);
528 dir_shadow = *dir_oe[priv->minor];
529 dir_shadow &= ~(arg & changeable_dir[priv->minor]);
530 *dir_oe[priv->minor] = dir_shadow;
531 local_irq_restore(flags);
532
533 if (priv->minor == GPIO_MINOR_A)
534 dir_shadow ^= 0xFF; /* Only 8 bits */
535#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
536 else if (priv->minor == GPIO_MINOR_V)
537 dir_shadow ^= 0xFFFF; /* Only 16 bits */
538#endif
539 else
540 dir_shadow ^= 0x3FFFF; /* Only 18 bits */
541 return dir_shadow;
542
543} /* setget_input */
544
545inline unsigned long setget_output(struct gpio_private *priv, unsigned long arg)
546{
547 unsigned long flags;
548 unsigned long dir_shadow;
549
550 local_irq_save(flags);
551 dir_shadow = *dir_oe[priv->minor];
552 dir_shadow |= (arg & changeable_dir[priv->minor]);
553 *dir_oe[priv->minor] = dir_shadow;
554 local_irq_restore(flags);
555 return dir_shadow;
556} /* setget_output */
557
558static int gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
559
560static int
561gpio_ioctl_unlocked(struct file *file, unsigned int cmd, unsigned long arg)
562{
563 unsigned long flags;
564 unsigned long val;
565 unsigned long shadow;
566 struct gpio_private *priv = file->private_data;
567 if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
568 return -EINVAL;
569
570#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
571 if (priv->minor == GPIO_MINOR_V)
572 return virtual_gpio_ioctl(file, cmd, arg);
573#endif
574
575 switch (_IOC_NR(cmd)) {
576 case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
577 /* Read the port. */
578 return *data_in[priv->minor];
579 break;
580 case IO_SETBITS:
581 local_irq_save(flags);
582 /* Set changeable bits with a 1 in arg. */
583 shadow = *data_out[priv->minor];
584 shadow |= (arg & changeable_bits[priv->minor]);
585 *data_out[priv->minor] = shadow;
586 local_irq_restore(flags);
587 break;
588 case IO_CLRBITS:
589 local_irq_save(flags);
590 /* Clear changeable bits with a 1 in arg. */
591 shadow = *data_out[priv->minor];
592 shadow &= ~(arg & changeable_bits[priv->minor]);
593 *data_out[priv->minor] = shadow;
594 local_irq_restore(flags);
595 break;
596 case IO_HIGHALARM:
597 /* Set alarm when bits with 1 in arg go high. */
598 priv->highalarm |= arg;
599 spin_lock_irqsave(&alarm_lock, flags);
600 gpio_some_alarms = 1;
601 if (priv->minor == GPIO_MINOR_A)
602 gpio_pa_high_alarms |= arg;
603 spin_unlock_irqrestore(&alarm_lock, flags);
604 break;
605 case IO_LOWALARM:
606 /* Set alarm when bits with 1 in arg go low. */
607 priv->lowalarm |= arg;
608 spin_lock_irqsave(&alarm_lock, flags);
609 gpio_some_alarms = 1;
610 if (priv->minor == GPIO_MINOR_A)
611 gpio_pa_low_alarms |= arg;
612 spin_unlock_irqrestore(&alarm_lock, flags);
613 break;
614 case IO_CLRALARM:
615 /* Clear alarm for bits with 1 in arg. */
616 priv->highalarm &= ~arg;
617 priv->lowalarm &= ~arg;
618 spin_lock_irqsave(&alarm_lock, flags);
619 if (priv->minor == GPIO_MINOR_A) {
620 if (gpio_pa_high_alarms & arg ||
621 gpio_pa_low_alarms & arg)
622 /* Must update the gpio_pa_*alarms masks */
623 ;
624 }
625 spin_unlock_irqrestore(&alarm_lock, flags);
626 break;
627 case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
628 /* Read direction 0=input 1=output */
629 return *dir_oe[priv->minor];
630 case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
631 /* Set direction 0=unchanged 1=input,
632 * return mask with 1=input
633 */
634 return setget_input(priv, arg);
635 break;
636 case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
637 /* Set direction 0=unchanged 1=output,
638 * return mask with 1=output
639 */
640 return setget_output(priv, arg);
641
642 case IO_CFG_WRITE_MODE:
643 {
644 unsigned long dir_shadow;
645 dir_shadow = *dir_oe[priv->minor];
646
647 priv->clk_mask = arg & 0xFF;
648 priv->data_mask = (arg >> 8) & 0xFF;
649 priv->write_msb = (arg >> 16) & 0x01;
650 /* Check if we're allowed to change the bits and
651 * the direction is correct
652 */
653 if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
654 (priv->data_mask & changeable_bits[priv->minor]) &&
655 (priv->clk_mask & dir_shadow) &&
656 (priv->data_mask & dir_shadow))) {
657 priv->clk_mask = 0;
658 priv->data_mask = 0;
659 return -EPERM;
660 }
661 break;
662 }
663 case IO_READ_INBITS:
664 /* *arg is result of reading the input pins */
665 val = *data_in[priv->minor];
666 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
667 return -EFAULT;
668 return 0;
669 break;
670 case IO_READ_OUTBITS:
671 /* *arg is result of reading the output shadow */
672 val = *data_out[priv->minor];
673 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
674 return -EFAULT;
675 break;
676 case IO_SETGET_INPUT:
677 /* bits set in *arg is set to input,
678 * *arg updated with current input pins.
679 */
680 if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
681 return -EFAULT;
682 val = setget_input(priv, val);
683 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
684 return -EFAULT;
685 break;
686 case IO_SETGET_OUTPUT:
687 /* bits set in *arg is set to output,
688 * *arg updated with current output pins.
689 */
690 if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
691 return -EFAULT;
692 val = setget_output(priv, val);
693 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
694 return -EFAULT;
695 break;
696 default:
697 if (priv->minor == GPIO_MINOR_LEDS)
698 return gpio_leds_ioctl(cmd, arg);
699 else
700 return -EINVAL;
701 } /* switch */
702
703 return 0;
704}
705
706static long gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
707{
708 long ret;
709
710 mutex_lock(&gpio_mutex);
711 ret = gpio_ioctl_unlocked(file, cmd, arg);
712 mutex_unlock(&gpio_mutex);
713
714 return ret;
715}
716
717#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
718static int
719virtual_gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
720{
721 unsigned long flags;
722 unsigned short val;
723 unsigned short shadow;
724 struct gpio_private *priv = file->private_data;
725
726 switch (_IOC_NR(cmd)) {
727 case IO_SETBITS:
728 local_irq_save(flags);
729 /* Set changeable bits with a 1 in arg. */
730 i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
731 shadow |= ~*dir_oe[priv->minor];
732 shadow |= (arg & changeable_bits[priv->minor]);
733 i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
734 local_irq_restore(flags);
735 break;
736 case IO_CLRBITS:
737 local_irq_save(flags);
738 /* Clear changeable bits with a 1 in arg. */
739 i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
740 shadow |= ~*dir_oe[priv->minor];
741 shadow &= ~(arg & changeable_bits[priv->minor]);
742 i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
743 local_irq_restore(flags);
744 break;
745 case IO_HIGHALARM:
746 /* Set alarm when bits with 1 in arg go high. */
747 priv->highalarm |= arg;
748 spin_lock(&alarm_lock);
749 gpio_some_alarms = 1;
750 spin_unlock(&alarm_lock);
751 break;
752 case IO_LOWALARM:
753 /* Set alarm when bits with 1 in arg go low. */
754 priv->lowalarm |= arg;
755 spin_lock(&alarm_lock);
756 gpio_some_alarms = 1;
757 spin_unlock(&alarm_lock);
758 break;
759 case IO_CLRALARM:
760 /* Clear alarm for bits with 1 in arg. */
761 priv->highalarm &= ~arg;
762 priv->lowalarm &= ~arg;
763 spin_lock(&alarm_lock);
764 spin_unlock(&alarm_lock);
765 break;
766 case IO_CFG_WRITE_MODE:
767 {
768 unsigned long dir_shadow;
769 dir_shadow = *dir_oe[priv->minor];
770
771 priv->clk_mask = arg & 0xFF;
772 priv->data_mask = (arg >> 8) & 0xFF;
773 priv->write_msb = (arg >> 16) & 0x01;
774 /* Check if we're allowed to change the bits and
775 * the direction is correct
776 */
777 if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
778 (priv->data_mask & changeable_bits[priv->minor]) &&
779 (priv->clk_mask & dir_shadow) &&
780 (priv->data_mask & dir_shadow))) {
781 priv->clk_mask = 0;
782 priv->data_mask = 0;
783 return -EPERM;
784 }
785 break;
786 }
787 case IO_READ_INBITS:
788 /* *arg is result of reading the input pins */
789 val = cached_virtual_gpio_read;
790 val &= ~*dir_oe[priv->minor];
791 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
792 return -EFAULT;
793 return 0;
794 break;
795 case IO_READ_OUTBITS:
796 /* *arg is result of reading the output shadow */
797 i2c_read(VIRT_I2C_ADDR, (void *)&val, sizeof(val));
798 val &= *dir_oe[priv->minor];
799 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
800 return -EFAULT;
801 break;
802 case IO_SETGET_INPUT:
803 {
804 /* bits set in *arg is set to input,
805 * *arg updated with current input pins.
806 */
807 unsigned short input_mask = ~*dir_oe[priv->minor];
808 if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
809 return -EFAULT;
810 val = setget_input(priv, val);
811 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
812 return -EFAULT;
813 if ((input_mask & val) != input_mask) {
814 /* Input pins changed. All ports desired as input
815 * should be set to logic 1.
816 */
817 unsigned short change = input_mask ^ val;
818 i2c_read(VIRT_I2C_ADDR, (void *)&shadow,
819 sizeof(shadow));
820 shadow &= ~change;
821 shadow |= val;
822 i2c_write(VIRT_I2C_ADDR, (void *)&shadow,
823 sizeof(shadow));
824 }
825 break;
826 }
827 case IO_SETGET_OUTPUT:
828 /* bits set in *arg is set to output,
829 * *arg updated with current output pins.
830 */
831 if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
832 return -EFAULT;
833 val = setget_output(priv, val);
834 if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
835 return -EFAULT;
836 break;
837 default:
838 return -EINVAL;
839 } /* switch */
840 return 0;
841}
842#endif /* CONFIG_ETRAX_VIRTUAL_GPIO */
843
844static int
845gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
846{
847 unsigned char green;
848 unsigned char red;
849
850 switch (_IOC_NR(cmd)) {
851 case IO_LEDACTIVE_SET:
852 green = ((unsigned char) arg) & 1;
853 red = (((unsigned char) arg) >> 1) & 1;
854 CRIS_LED_ACTIVE_SET_G(green);
855 CRIS_LED_ACTIVE_SET_R(red);
856 break;
857
858 default:
859 return -EINVAL;
860 } /* switch */
861
862 return 0;
863}
864
865static const struct file_operations gpio_fops = {
866 .owner = THIS_MODULE,
867 .poll = gpio_poll,
868 .unlocked_ioctl = gpio_ioctl,
869 .write = gpio_write,
870 .open = gpio_open,
871 .release = gpio_release,
872 .llseek = noop_llseek,
873};
874
875#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
876static void
877virtual_gpio_init(void)
878{
879 reg_gio_rw_intr_cfg intr_cfg;
880 reg_gio_rw_intr_mask intr_mask;
881 unsigned short shadow;
882
883 shadow = ~virtual_rw_pv_oe; /* Input ports should be set to logic 1 */
884 shadow |= CONFIG_ETRAX_DEF_GIO_PV_OUT;
885 i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
886
887 /* Set interrupt mask and on what state the interrupt shall trigger.
888 * For virtual gpio the interrupt shall trigger on logic '0'.
889 */
890 intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
891 intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
892
893 switch (CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN) {
894 case 0:
895 intr_cfg.pa0 = regk_gio_lo;
896 intr_mask.pa0 = regk_gio_yes;
897 break;
898 case 1:
899 intr_cfg.pa1 = regk_gio_lo;
900 intr_mask.pa1 = regk_gio_yes;
901 break;
902 case 2:
903 intr_cfg.pa2 = regk_gio_lo;
904 intr_mask.pa2 = regk_gio_yes;
905 break;
906 case 3:
907 intr_cfg.pa3 = regk_gio_lo;
908 intr_mask.pa3 = regk_gio_yes;
909 break;
910 case 4:
911 intr_cfg.pa4 = regk_gio_lo;
912 intr_mask.pa4 = regk_gio_yes;
913 break;
914 case 5:
915 intr_cfg.pa5 = regk_gio_lo;
916 intr_mask.pa5 = regk_gio_yes;
917 break;
918 case 6:
919 intr_cfg.pa6 = regk_gio_lo;
920 intr_mask.pa6 = regk_gio_yes;
921 break;
922 case 7:
923 intr_cfg.pa7 = regk_gio_lo;
924 intr_mask.pa7 = regk_gio_yes;
925 break;
926 }
927
928 REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
929 REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
930
931 gpio_pa_low_alarms |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
932 gpio_some_alarms = 1;
933}
934#endif
935
936/* main driver initialization routine, called from mem.c */
937
938static __init int
939gpio_init(void)
940{
941 int res;
942
943 /* do the formalities */
944
945 res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
946 if (res < 0) {
947 printk(KERN_ERR "gpio: couldn't get a major number.\n");
948 return res;
949 }
950
951 /* Clear all leds */
952 CRIS_LED_NETWORK_GRP0_SET(0);
953 CRIS_LED_NETWORK_GRP1_SET(0);
954 CRIS_LED_ACTIVE_SET(0);
955 CRIS_LED_DISK_READ(0);
956 CRIS_LED_DISK_WRITE(0);
957
958 printk(KERN_INFO "ETRAX FS GPIO driver v2.5, (c) 2003-2007 "
959 "Axis Communications AB\n");
960 /* We call etrax_gpio_wake_up_check() from timer interrupt */
961 if (request_irq(TIMER0_INTR_VECT, gpio_poll_timer_interrupt,
962 IRQF_SHARED, "gpio poll", &alarmlist))
963 printk(KERN_ERR "timer0 irq for gpio\n");
964
965 if (request_irq(GIO_INTR_VECT, gpio_pa_interrupt,
966 IRQF_SHARED, "gpio PA", &alarmlist))
967 printk(KERN_ERR "PA irq for gpio\n");
968
969#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
970 virtual_gpio_init();
971#endif
972
973 return res;
974}
975
976/* this makes sure that gpio_init is called during kernel boot */
977
978module_init(gpio_init);
diff --git a/arch/cris/arch-v32/kernel/crisksyms.c b/arch/cris/arch-v32/kernel/crisksyms.c
index bde8d1a10cad..b0566350a840 100644
--- a/arch/cris/arch-v32/kernel/crisksyms.c
+++ b/arch/cris/arch-v32/kernel/crisksyms.c
@@ -3,7 +3,6 @@
3#include <arch/dma.h> 3#include <arch/dma.h>
4#include <arch/intmem.h> 4#include <arch/intmem.h>
5#include <mach/pinmux.h> 5#include <mach/pinmux.h>
6#include <arch/io.h>
7 6
8/* Functions for allocating DMA channels */ 7/* Functions for allocating DMA channels */
9EXPORT_SYMBOL(crisv32_request_dma); 8EXPORT_SYMBOL(crisv32_request_dma);
@@ -20,8 +19,6 @@ EXPORT_SYMBOL(crisv32_pinmux_alloc);
20EXPORT_SYMBOL(crisv32_pinmux_alloc_fixed); 19EXPORT_SYMBOL(crisv32_pinmux_alloc_fixed);
21EXPORT_SYMBOL(crisv32_pinmux_dealloc); 20EXPORT_SYMBOL(crisv32_pinmux_dealloc);
22EXPORT_SYMBOL(crisv32_pinmux_dealloc_fixed); 21EXPORT_SYMBOL(crisv32_pinmux_dealloc_fixed);
23EXPORT_SYMBOL(crisv32_io_get_name);
24EXPORT_SYMBOL(crisv32_io_get);
25 22
26/* Functions masking/unmasking interrupts */ 23/* Functions masking/unmasking interrupts */
27EXPORT_SYMBOL(crisv32_mask_irq); 24EXPORT_SYMBOL(crisv32_mask_irq);
diff --git a/arch/cris/arch-v32/mach-a3/Makefile b/arch/cris/arch-v32/mach-a3/Makefile
index 18a227196a41..0cc6eebacbed 100644
--- a/arch/cris/arch-v32/mach-a3/Makefile
+++ b/arch/cris/arch-v32/mach-a3/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := dma.o pinmux.o io.o arbiter.o 5obj-y := dma.o pinmux.o arbiter.o
6 6
7clean: 7clean:
8 8
diff --git a/arch/cris/arch-v32/mach-a3/io.c b/arch/cris/arch-v32/mach-a3/io.c
deleted file mode 100644
index 090ceb99ef0b..000000000000
--- a/arch/cris/arch-v32/mach-a3/io.c
+++ /dev/null
@@ -1,149 +0,0 @@
1/*
2 * Helper functions for I/O pins.
3 *
4 * Copyright (c) 2005-2007 Axis Communications AB.
5 */
6
7#include <linux/types.h>
8#include <linux/errno.h>
9#include <linux/init.h>
10#include <linux/string.h>
11#include <linux/ctype.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <asm/io.h>
15#include <mach/pinmux.h>
16#include <hwregs/gio_defs.h>
17
18struct crisv32_ioport crisv32_ioports[] = {
19 {
20 (unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_oe),
21 (unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_dout),
22 (unsigned long *)REG_ADDR(gio, regi_gio, r_pa_din),
23 32
24 },
25 {
26 (unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_oe),
27 (unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_dout),
28 (unsigned long *)REG_ADDR(gio, regi_gio, r_pb_din),
29 32
30 },
31 {
32 (unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_oe),
33 (unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_dout),
34 (unsigned long *)REG_ADDR(gio, regi_gio, r_pc_din),
35 16
36 },
37};
38
39#define NBR_OF_PORTS ARRAY_SIZE(crisv32_ioports)
40
41struct crisv32_iopin crisv32_led_net0_green;
42struct crisv32_iopin crisv32_led_net0_red;
43struct crisv32_iopin crisv32_led2_green;
44struct crisv32_iopin crisv32_led2_red;
45struct crisv32_iopin crisv32_led3_green;
46struct crisv32_iopin crisv32_led3_red;
47
48/* Dummy port used when green LED and red LED is on the same bit */
49static unsigned long io_dummy;
50static struct crisv32_ioport dummy_port = {
51 &io_dummy,
52 &io_dummy,
53 &io_dummy,
54 32
55};
56static struct crisv32_iopin dummy_led = {
57 &dummy_port,
58 0
59};
60
61static int __init crisv32_io_init(void)
62{
63 int ret = 0;
64
65 u32 i;
66
67 /* Locks *should* be dynamically initialized. */
68 for (i = 0; i < ARRAY_SIZE(crisv32_ioports); i++)
69 spin_lock_init(&crisv32_ioports[i].lock);
70 spin_lock_init(&dummy_port.lock);
71
72 /* Initialize LEDs */
73#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO))
74 ret += crisv32_io_get_name(&crisv32_led_net0_green,
75 CONFIG_ETRAX_LED_G_NET0);
76 crisv32_io_set_dir(&crisv32_led_net0_green, crisv32_io_dir_out);
77 if (strcmp(CONFIG_ETRAX_LED_G_NET0, CONFIG_ETRAX_LED_R_NET0)) {
78 ret += crisv32_io_get_name(&crisv32_led_net0_red,
79 CONFIG_ETRAX_LED_R_NET0);
80 crisv32_io_set_dir(&crisv32_led_net0_red, crisv32_io_dir_out);
81 } else
82 crisv32_led_net0_red = dummy_led;
83#endif
84
85 ret += crisv32_io_get_name(&crisv32_led2_green, CONFIG_ETRAX_V32_LED2G);
86 ret += crisv32_io_get_name(&crisv32_led2_red, CONFIG_ETRAX_V32_LED2R);
87 ret += crisv32_io_get_name(&crisv32_led3_green, CONFIG_ETRAX_V32_LED3G);
88 ret += crisv32_io_get_name(&crisv32_led3_red, CONFIG_ETRAX_V32_LED3R);
89
90 crisv32_io_set_dir(&crisv32_led2_green, crisv32_io_dir_out);
91 crisv32_io_set_dir(&crisv32_led2_red, crisv32_io_dir_out);
92 crisv32_io_set_dir(&crisv32_led3_green, crisv32_io_dir_out);
93 crisv32_io_set_dir(&crisv32_led3_red, crisv32_io_dir_out);
94
95 return ret;
96}
97
98__initcall(crisv32_io_init);
99
100int crisv32_io_get(struct crisv32_iopin *iopin,
101 unsigned int port, unsigned int pin)
102{
103 if (port > NBR_OF_PORTS)
104 return -EINVAL;
105 if (port > crisv32_ioports[port].pin_count)
106 return -EINVAL;
107
108 iopin->bit = 1 << pin;
109 iopin->port = &crisv32_ioports[port];
110
111 if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio))
112 return -EIO;
113
114 return 0;
115}
116
117int crisv32_io_get_name(struct crisv32_iopin *iopin, const char *name)
118{
119 int port;
120 int pin;
121
122 if (toupper(*name) == 'P')
123 name++;
124
125 if (toupper(*name) < 'A' || toupper(*name) > 'E')
126 return -EINVAL;
127
128 port = toupper(*name) - 'A';
129 name++;
130 pin = simple_strtoul(name, NULL, 10);
131
132 if (pin < 0 || pin > crisv32_ioports[port].pin_count)
133 return -EINVAL;
134
135 iopin->bit = 1 << pin;
136 iopin->port = &crisv32_ioports[port];
137
138 if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio))
139 return -EIO;
140
141 return 0;
142}
143
144#ifdef CONFIG_PCI
145/* PCI I/O access stuff */
146struct cris_io_operations *cris_iops = NULL;
147EXPORT_SYMBOL(cris_iops);
148#endif
149
diff --git a/arch/cris/arch-v32/mach-fs/Makefile b/arch/cris/arch-v32/mach-fs/Makefile
index 18a227196a41..0cc6eebacbed 100644
--- a/arch/cris/arch-v32/mach-fs/Makefile
+++ b/arch/cris/arch-v32/mach-fs/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := dma.o pinmux.o io.o arbiter.o 5obj-y := dma.o pinmux.o arbiter.o
6 6
7clean: 7clean:
8 8
diff --git a/arch/cris/arch-v32/mach-fs/io.c b/arch/cris/arch-v32/mach-fs/io.c
deleted file mode 100644
index a6958661fa8e..000000000000
--- a/arch/cris/arch-v32/mach-fs/io.c
+++ /dev/null
@@ -1,191 +0,0 @@
1/*
2 * Helper functions for I/O pins.
3 *
4 * Copyright (c) 2004-2007 Axis Communications AB.
5 */
6
7#include <linux/types.h>
8#include <linux/errno.h>
9#include <linux/init.h>
10#include <linux/string.h>
11#include <linux/ctype.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <asm/io.h>
15#include <mach/pinmux.h>
16#include <hwregs/gio_defs.h>
17
18#ifndef DEBUG
19#define DEBUG(x)
20#endif
21
22struct crisv32_ioport crisv32_ioports[] = {
23 {
24 (unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_oe),
25 (unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_dout),
26 (unsigned long *)REG_ADDR(gio, regi_gio, r_pa_din),
27 8
28 },
29 {
30 (unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_oe),
31 (unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_dout),
32 (unsigned long *)REG_ADDR(gio, regi_gio, r_pb_din),
33 18
34 },
35 {
36 (unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_oe),
37 (unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_dout),
38 (unsigned long *)REG_ADDR(gio, regi_gio, r_pc_din),
39 18
40 },
41 {
42 (unsigned long *)REG_ADDR(gio, regi_gio, rw_pd_oe),
43 (unsigned long *)REG_ADDR(gio, regi_gio, rw_pd_dout),
44 (unsigned long *)REG_ADDR(gio, regi_gio, r_pd_din),
45 18
46 },
47 {
48 (unsigned long *)REG_ADDR(gio, regi_gio, rw_pe_oe),
49 (unsigned long *)REG_ADDR(gio, regi_gio, rw_pe_dout),
50 (unsigned long *)REG_ADDR(gio, regi_gio, r_pe_din),
51 18
52 }
53};
54
55#define NBR_OF_PORTS ARRAY_SIZE(crisv32_ioports)
56
57struct crisv32_iopin crisv32_led_net0_green;
58struct crisv32_iopin crisv32_led_net0_red;
59struct crisv32_iopin crisv32_led_net1_green;
60struct crisv32_iopin crisv32_led_net1_red;
61struct crisv32_iopin crisv32_led2_green;
62struct crisv32_iopin crisv32_led2_red;
63struct crisv32_iopin crisv32_led3_green;
64struct crisv32_iopin crisv32_led3_red;
65
66/* Dummy port used when green LED and red LED is on the same bit */
67static unsigned long io_dummy;
68static struct crisv32_ioport dummy_port = {
69 &io_dummy,
70 &io_dummy,
71 &io_dummy,
72 18
73};
74static struct crisv32_iopin dummy_led = {
75 &dummy_port,
76 0
77};
78
79static int __init crisv32_io_init(void)
80{
81 int ret = 0;
82
83 u32 i;
84
85 /* Locks *should* be dynamically initialized. */
86 for (i = 0; i < ARRAY_SIZE(crisv32_ioports); i++)
87 spin_lock_init(&crisv32_ioports[i].lock);
88 spin_lock_init(&dummy_port.lock);
89
90 /* Initialize LEDs */
91#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO))
92 ret +=
93 crisv32_io_get_name(&crisv32_led_net0_green,
94 CONFIG_ETRAX_LED_G_NET0);
95 crisv32_io_set_dir(&crisv32_led_net0_green, crisv32_io_dir_out);
96 if (strcmp(CONFIG_ETRAX_LED_G_NET0, CONFIG_ETRAX_LED_R_NET0)) {
97 ret +=
98 crisv32_io_get_name(&crisv32_led_net0_red,
99 CONFIG_ETRAX_LED_R_NET0);
100 crisv32_io_set_dir(&crisv32_led_net0_red, crisv32_io_dir_out);
101 } else
102 crisv32_led_net0_red = dummy_led;
103#endif
104
105#ifdef CONFIG_ETRAX_NBR_LED_GRP_TWO
106 ret +=
107 crisv32_io_get_name(&crisv32_led_net1_green,
108 CONFIG_ETRAX_LED_G_NET1);
109 crisv32_io_set_dir(&crisv32_led_net1_green, crisv32_io_dir_out);
110 if (strcmp(CONFIG_ETRAX_LED_G_NET1, CONFIG_ETRAX_LED_R_NET1)) {
111 crisv32_io_get_name(&crisv32_led_net1_red,
112 CONFIG_ETRAX_LED_R_NET1);
113 crisv32_io_set_dir(&crisv32_led_net1_red, crisv32_io_dir_out);
114 } else
115 crisv32_led_net1_red = dummy_led;
116#endif
117
118 ret += crisv32_io_get_name(&crisv32_led2_green, CONFIG_ETRAX_V32_LED2G);
119 ret += crisv32_io_get_name(&crisv32_led2_red, CONFIG_ETRAX_V32_LED2R);
120 ret += crisv32_io_get_name(&crisv32_led3_green, CONFIG_ETRAX_V32_LED3G);
121 ret += crisv32_io_get_name(&crisv32_led3_red, CONFIG_ETRAX_V32_LED3R);
122
123 crisv32_io_set_dir(&crisv32_led2_green, crisv32_io_dir_out);
124 crisv32_io_set_dir(&crisv32_led2_red, crisv32_io_dir_out);
125 crisv32_io_set_dir(&crisv32_led3_green, crisv32_io_dir_out);
126 crisv32_io_set_dir(&crisv32_led3_red, crisv32_io_dir_out);
127
128 return ret;
129}
130
131__initcall(crisv32_io_init);
132
133int crisv32_io_get(struct crisv32_iopin *iopin,
134 unsigned int port, unsigned int pin)
135{
136 if (port > NBR_OF_PORTS)
137 return -EINVAL;
138 if (port > crisv32_ioports[port].pin_count)
139 return -EINVAL;
140
141 iopin->bit = 1 << pin;
142 iopin->port = &crisv32_ioports[port];
143
144 /* Only allocate pinmux gpiopins if port != PORT_A (port 0) */
145 /* NOTE! crisv32_pinmux_alloc thinks PORT_B is port 0 */
146 if (port != 0 && crisv32_pinmux_alloc(port - 1, pin, pin, pinmux_gpio))
147 return -EIO;
148 DEBUG(printk(KERN_DEBUG "crisv32_io_get: Allocated pin %d on port %d\n",
149 pin, port));
150
151 return 0;
152}
153
154int crisv32_io_get_name(struct crisv32_iopin *iopin, const char *name)
155{
156 int port;
157 int pin;
158
159 if (toupper(*name) == 'P')
160 name++;
161
162 if (toupper(*name) < 'A' || toupper(*name) > 'E')
163 return -EINVAL;
164
165 port = toupper(*name) - 'A';
166 name++;
167 pin = simple_strtoul(name, NULL, 10);
168
169 if (pin < 0 || pin > crisv32_ioports[port].pin_count)
170 return -EINVAL;
171
172 iopin->bit = 1 << pin;
173 iopin->port = &crisv32_ioports[port];
174
175 /* Only allocate pinmux gpiopins if port != PORT_A (port 0) */
176 /* NOTE! crisv32_pinmux_alloc thinks PORT_B is port 0 */
177 if (port != 0 && crisv32_pinmux_alloc(port - 1, pin, pin, pinmux_gpio))
178 return -EIO;
179
180 DEBUG(printk(KERN_DEBUG
181 "crisv32_io_get_name: Allocated pin %d on port %d\n",
182 pin, port));
183
184 return 0;
185}
186
187#ifdef CONFIG_PCI
188/* PCI I/O access stuff */
189struct cris_io_operations *cris_iops = NULL;
190EXPORT_SYMBOL(cris_iops);
191#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-03 13:56:13 -0400