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authorRabin Vincent <rabin@rab.in>2015-02-19 11:35:28 -0500
committerJesper Nilsson <jespern@axis.com>2015-03-25 05:55:10 -0400
commit47a8f6fb349c977ff752f979b159aef96a0bb352 (patch)
tree53c52b00d97eb5b0e284b67d66f09ed7ab9a5744 /arch/cris/arch-v32
parent06aca92424c2a53a9e26cb81c1d6a829af9491b8 (diff)
CRIS: remove SMP code
The CRIS SMP code cannot be built since there is no (and appears to never have been) a CONFIG_SMP Kconfig option in arch/cris/. Remove it. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Jesper Nilsson <jespern@axis.com>
Diffstat (limited to 'arch/cris/arch-v32')
-rw-r--r--arch/cris/arch-v32/kernel/Makefile1
-rw-r--r--arch/cris/arch-v32/kernel/head.S32
-rw-r--r--arch/cris/arch-v32/kernel/irq.c3
-rw-r--r--arch/cris/arch-v32/kernel/setup.c5
-rw-r--r--arch/cris/arch-v32/kernel/smp.c358
-rw-r--r--arch/cris/arch-v32/kernel/time.c3
-rw-r--r--arch/cris/arch-v32/lib/Makefile2
-rw-r--r--arch/cris/arch-v32/lib/spinlock.S40
-rw-r--r--arch/cris/arch-v32/mm/init.c11
-rw-r--r--arch/cris/arch-v32/mm/mmu.S4
10 files changed, 1 insertions, 458 deletions
diff --git a/arch/cris/arch-v32/kernel/Makefile b/arch/cris/arch-v32/kernel/Makefile
index 40358355d0cb..d9fc617ea253 100644
--- a/arch/cris/arch-v32/kernel/Makefile
+++ b/arch/cris/arch-v32/kernel/Makefile
@@ -9,7 +9,6 @@ obj-y := entry.o traps.o irq.o debugport.o \
9 process.o ptrace.o setup.o signal.o traps.o time.o \ 9 process.o ptrace.o setup.o signal.o traps.o time.o \
10 cache.o cacheflush.o 10 cache.o cacheflush.o
11 11
12obj-$(CONFIG_SMP) += smp.o
13obj-$(CONFIG_ETRAX_KGDB) += kgdb.o kgdb_asm.o 12obj-$(CONFIG_ETRAX_KGDB) += kgdb.o kgdb_asm.o
14obj-$(CONFIG_ETRAX_FAST_TIMER) += fasttimer.o 13obj-$(CONFIG_ETRAX_FAST_TIMER) += fasttimer.o
15obj-$(CONFIG_MODULES) += crisksyms.o 14obj-$(CONFIG_MODULES) += crisksyms.o
diff --git a/arch/cris/arch-v32/kernel/head.S b/arch/cris/arch-v32/kernel/head.S
index 51e34165ece7..74a66e0e3777 100644
--- a/arch/cris/arch-v32/kernel/head.S
+++ b/arch/cris/arch-v32/kernel/head.S
@@ -52,11 +52,6 @@ tstart:
52 52
53 GIO_INIT 53 GIO_INIT
54 54
55#ifdef CONFIG_SMP
56secondary_cpu_entry: /* Entry point for secondary CPUs */
57 di
58#endif
59
60 ;; Setup and enable the MMU. Use same configuration for both the data 55 ;; Setup and enable the MMU. Use same configuration for both the data
61 ;; and the instruction MMU. 56 ;; and the instruction MMU.
62 ;; 57 ;;
@@ -164,33 +159,6 @@ secondary_cpu_entry: /* Entry point for secondary CPUs */
164 nop 159 nop
165 nop 160 nop
166 161
167#ifdef CONFIG_SMP
168 ;; Read CPU ID
169 move 0, $srs
170 nop
171 nop
172 nop
173 move $s12, $r0
174 cmpq 0, $r0
175 beq master_cpu
176 nop
177slave_cpu:
178 ; Time to boot-up. Get stack location provided by master CPU.
179 move.d smp_init_current_idle_thread, $r1
180 move.d [$r1], $sp
181 add.d 8192, $sp
182 move.d ebp_start, $r0 ; Defined in linker-script.
183 move $r0, $ebp
184 jsr smp_callin
185 nop
186master_cpu:
187 /* Set up entry point for secondary CPUs. The boot ROM has set up
188 * EBP at start of internal memory. The CPU will get there
189 * later when we issue an IPI to them... */
190 move.d MEM_INTMEM_START + IPI_INTR_VECT * 4, $r0
191 move.d secondary_cpu_entry, $r1
192 move.d $r1, [$r0]
193#endif
194 ; Check if starting from DRAM (network->RAM boot or unpacked 162 ; Check if starting from DRAM (network->RAM boot or unpacked
195 ; compressed kernel), or directly from flash. 163 ; compressed kernel), or directly from flash.
196 lapcq ., $r0 164 lapcq ., $r0
diff --git a/arch/cris/arch-v32/kernel/irq.c b/arch/cris/arch-v32/kernel/irq.c
index bc871d2c594a..6a881e0e92b4 100644
--- a/arch/cris/arch-v32/kernel/irq.c
+++ b/arch/cris/arch-v32/kernel/irq.c
@@ -58,9 +58,6 @@ struct cris_irq_allocation irq_allocations[NR_REAL_IRQS] =
58static unsigned long irq_regs[NR_CPUS] = 58static unsigned long irq_regs[NR_CPUS] =
59{ 59{
60 regi_irq, 60 regi_irq,
61#ifdef CONFIG_SMP
62 regi_irq2,
63#endif
64}; 61};
65 62
66#if NR_REAL_IRQS > 32 63#if NR_REAL_IRQS > 32
diff --git a/arch/cris/arch-v32/kernel/setup.c b/arch/cris/arch-v32/kernel/setup.c
index 61e10ae65296..231927bba7c2 100644
--- a/arch/cris/arch-v32/kernel/setup.c
+++ b/arch/cris/arch-v32/kernel/setup.c
@@ -63,11 +63,6 @@ int show_cpuinfo(struct seq_file *m, void *v)
63 63
64 info = &cpinfo[ARRAY_SIZE(cpinfo) - 1]; 64 info = &cpinfo[ARRAY_SIZE(cpinfo) - 1];
65 65
66#ifdef CONFIG_SMP
67 if (!cpu_online(cpu))
68 return 0;
69#endif
70
71 revision = rdvr(); 66 revision = rdvr();
72 67
73 for (i = 0; i < ARRAY_SIZE(cpinfo); i++) { 68 for (i = 0; i < ARRAY_SIZE(cpinfo); i++) {
diff --git a/arch/cris/arch-v32/kernel/smp.c b/arch/cris/arch-v32/kernel/smp.c
deleted file mode 100644
index 0698582467ca..000000000000
--- a/arch/cris/arch-v32/kernel/smp.c
+++ /dev/null
@@ -1,358 +0,0 @@
1#include <linux/types.h>
2#include <asm/delay.h>
3#include <irq.h>
4#include <hwregs/intr_vect.h>
5#include <hwregs/intr_vect_defs.h>
6#include <asm/tlbflush.h>
7#include <asm/mmu_context.h>
8#include <hwregs/asm/mmu_defs_asm.h>
9#include <hwregs/supp_reg.h>
10#include <linux/atomic.h>
11
12#include <linux/err.h>
13#include <linux/init.h>
14#include <linux/timex.h>
15#include <linux/sched.h>
16#include <linux/kernel.h>
17#include <linux/cpumask.h>
18#include <linux/interrupt.h>
19#include <linux/module.h>
20
21#define IPI_SCHEDULE 1
22#define IPI_CALL 2
23#define IPI_FLUSH_TLB 4
24#define IPI_BOOT 8
25
26#define FLUSH_ALL (void*)0xffffffff
27
28/* Vector of locks used for various atomic operations */
29spinlock_t cris_atomic_locks[] = {
30 [0 ... LOCK_COUNT - 1] = __SPIN_LOCK_UNLOCKED(cris_atomic_locks)
31};
32
33/* CPU masks */
34cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
35EXPORT_SYMBOL(phys_cpu_present_map);
36
37/* Variables used during SMP boot */
38volatile int cpu_now_booting = 0;
39volatile struct thread_info *smp_init_current_idle_thread;
40
41/* Variables used during IPI */
42static DEFINE_SPINLOCK(call_lock);
43static DEFINE_SPINLOCK(tlbstate_lock);
44
45struct call_data_struct {
46 void (*func) (void *info);
47 void *info;
48 int wait;
49};
50
51static struct call_data_struct * call_data;
52
53static struct mm_struct* flush_mm;
54static struct vm_area_struct* flush_vma;
55static unsigned long flush_addr;
56
57/* Mode registers */
58static unsigned long irq_regs[NR_CPUS] = {
59 regi_irq,
60 regi_irq2
61};
62
63static irqreturn_t crisv32_ipi_interrupt(int irq, void *dev_id);
64static int send_ipi(int vector, int wait, cpumask_t cpu_mask);
65static struct irqaction irq_ipi = {
66 .handler = crisv32_ipi_interrupt,
67 .flags = 0,
68 .name = "ipi",
69};
70
71extern void cris_mmu_init(void);
72extern void cris_timer_init(void);
73
74/* SMP initialization */
75void __init smp_prepare_cpus(unsigned int max_cpus)
76{
77 int i;
78
79 /* From now on we can expect IPIs so set them up */
80 setup_irq(IPI_INTR_VECT, &irq_ipi);
81
82 /* Mark all possible CPUs as present */
83 for (i = 0; i < max_cpus; i++)
84 cpumask_set_cpu(i, &phys_cpu_present_map);
85}
86
87void smp_prepare_boot_cpu(void)
88{
89 /* PGD pointer has moved after per_cpu initialization so
90 * update the MMU.
91 */
92 pgd_t **pgd;
93 pgd = (pgd_t**)&per_cpu(current_pgd, smp_processor_id());
94
95 SUPP_BANK_SEL(1);
96 SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
97 SUPP_BANK_SEL(2);
98 SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
99
100 set_cpu_online(0, true);
101 cpumask_set_cpu(0, &phys_cpu_present_map);
102 set_cpu_possible(0, true);
103}
104
105void __init smp_cpus_done(unsigned int max_cpus)
106{
107}
108
109/* Bring one cpu online.*/
110static int __init
111smp_boot_one_cpu(int cpuid, struct task_struct idle)
112{
113 unsigned timeout;
114 cpumask_t cpu_mask;
115
116 cpumask_clear(&cpu_mask);
117 task_thread_info(idle)->cpu = cpuid;
118
119 /* Information to the CPU that is about to boot */
120 smp_init_current_idle_thread = task_thread_info(idle);
121 cpu_now_booting = cpuid;
122
123 /* Kick it */
124 set_cpu_online(cpuid, true);
125 cpumask_set_cpu(cpuid, &cpu_mask);
126 send_ipi(IPI_BOOT, 0, cpu_mask);
127 set_cpu_online(cpuid, false);
128
129 /* Wait for CPU to come online */
130 for (timeout = 0; timeout < 10000; timeout++) {
131 if(cpu_online(cpuid)) {
132 cpu_now_booting = 0;
133 smp_init_current_idle_thread = NULL;
134 return 0; /* CPU online */
135 }
136 udelay(100);
137 barrier();
138 }
139
140 printk(KERN_CRIT "SMP: CPU:%d is stuck.\n", cpuid);
141 return -1;
142}
143
144/* Secondary CPUs starts using C here. Here we need to setup CPU
145 * specific stuff such as the local timer and the MMU. */
146void __init smp_callin(void)
147{
148 int cpu = cpu_now_booting;
149 reg_intr_vect_rw_mask vect_mask = {0};
150
151 /* Initialise the idle task for this CPU */
152 atomic_inc(&init_mm.mm_count);
153 current->active_mm = &init_mm;
154
155 /* Set up MMU */
156 cris_mmu_init();
157 __flush_tlb_all();
158
159 /* Setup local timer. */
160 cris_timer_init();
161
162 /* Enable IRQ and idle */
163 REG_WR(intr_vect, irq_regs[cpu], rw_mask, vect_mask);
164 crisv32_unmask_irq(IPI_INTR_VECT);
165 crisv32_unmask_irq(TIMER0_INTR_VECT);
166 preempt_disable();
167 notify_cpu_starting(cpu);
168 local_irq_enable();
169
170 set_cpu_online(cpu, true);
171 cpu_startup_entry(CPUHP_ONLINE);
172}
173
174/* Stop execution on this CPU.*/
175void stop_this_cpu(void* dummy)
176{
177 local_irq_disable();
178 asm volatile("halt");
179}
180
181/* Other calls */
182void smp_send_stop(void)
183{
184 smp_call_function(stop_this_cpu, NULL, 0);
185}
186
187int setup_profiling_timer(unsigned int multiplier)
188{
189 return -EINVAL;
190}
191
192
193/* cache_decay_ticks is used by the scheduler to decide if a process
194 * is "hot" on one CPU. A higher value means a higher penalty to move
195 * a process to another CPU. Our cache is rather small so we report
196 * 1 tick.
197 */
198unsigned long cache_decay_ticks = 1;
199
200int __cpu_up(unsigned int cpu, struct task_struct *tidle)
201{
202 smp_boot_one_cpu(cpu, tidle);
203 return cpu_online(cpu) ? 0 : -ENOSYS;
204}
205
206void smp_send_reschedule(int cpu)
207{
208 cpumask_t cpu_mask;
209 cpumask_clear(&cpu_mask);
210 cpumask_set_cpu(cpu, &cpu_mask);
211 send_ipi(IPI_SCHEDULE, 0, cpu_mask);
212}
213
214/* TLB flushing
215 *
216 * Flush needs to be done on the local CPU and on any other CPU that
217 * may have the same mapping. The mm->cpu_vm_mask is used to keep track
218 * of which CPUs that a specific process has been executed on.
219 */
220void flush_tlb_common(struct mm_struct* mm, struct vm_area_struct* vma, unsigned long addr)
221{
222 unsigned long flags;
223 cpumask_t cpu_mask;
224
225 spin_lock_irqsave(&tlbstate_lock, flags);
226 cpu_mask = (mm == FLUSH_ALL ? cpu_all_mask : *mm_cpumask(mm));
227 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
228 flush_mm = mm;
229 flush_vma = vma;
230 flush_addr = addr;
231 send_ipi(IPI_FLUSH_TLB, 1, cpu_mask);
232 spin_unlock_irqrestore(&tlbstate_lock, flags);
233}
234
235void flush_tlb_all(void)
236{
237 __flush_tlb_all();
238 flush_tlb_common(FLUSH_ALL, FLUSH_ALL, 0);
239}
240
241void flush_tlb_mm(struct mm_struct *mm)
242{
243 __flush_tlb_mm(mm);
244 flush_tlb_common(mm, FLUSH_ALL, 0);
245 /* No more mappings in other CPUs */
246 cpumask_clear(mm_cpumask(mm));
247 cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
248}
249
250void flush_tlb_page(struct vm_area_struct *vma,
251 unsigned long addr)
252{
253 __flush_tlb_page(vma, addr);
254 flush_tlb_common(vma->vm_mm, vma, addr);
255}
256
257/* Inter processor interrupts
258 *
259 * The IPIs are used for:
260 * * Force a schedule on a CPU
261 * * FLush TLB on other CPUs
262 * * Call a function on other CPUs
263 */
264
265int send_ipi(int vector, int wait, cpumask_t cpu_mask)
266{
267 int i = 0;
268 reg_intr_vect_rw_ipi ipi = REG_RD(intr_vect, irq_regs[i], rw_ipi);
269 int ret = 0;
270
271 /* Calculate CPUs to send to. */
272 cpumask_and(&cpu_mask, &cpu_mask, cpu_online_mask);
273
274 /* Send the IPI. */
275 for_each_cpu(i, &cpu_mask)
276 {
277 ipi.vector |= vector;
278 REG_WR(intr_vect, irq_regs[i], rw_ipi, ipi);
279 }
280
281 /* Wait for IPI to finish on other CPUS */
282 if (wait) {
283 for_each_cpu(i, &cpu_mask) {
284 int j;
285 for (j = 0 ; j < 1000; j++) {
286 ipi = REG_RD(intr_vect, irq_regs[i], rw_ipi);
287 if (!ipi.vector)
288 break;
289 udelay(100);
290 }
291
292 /* Timeout? */
293 if (ipi.vector) {
294 printk("SMP call timeout from %d to %d\n", smp_processor_id(), i);
295 ret = -ETIMEDOUT;
296 dump_stack();
297 }
298 }
299 }
300 return ret;
301}
302
303/*
304 * You must not call this function with disabled interrupts or from a
305 * hardware interrupt handler or from a bottom half handler.
306 */
307int smp_call_function(void (*func)(void *info), void *info, int wait)
308{
309 cpumask_t cpu_mask;
310 struct call_data_struct data;
311 int ret;
312
313 cpumask_setall(&cpu_mask);
314 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
315
316 WARN_ON(irqs_disabled());
317
318 data.func = func;
319 data.info = info;
320 data.wait = wait;
321
322 spin_lock(&call_lock);
323 call_data = &data;
324 ret = send_ipi(IPI_CALL, wait, cpu_mask);
325 spin_unlock(&call_lock);
326
327 return ret;
328}
329
330irqreturn_t crisv32_ipi_interrupt(int irq, void *dev_id)
331{
332 void (*func) (void *info) = call_data->func;
333 void *info = call_data->info;
334 reg_intr_vect_rw_ipi ipi;
335
336 ipi = REG_RD(intr_vect, irq_regs[smp_processor_id()], rw_ipi);
337
338 if (ipi.vector & IPI_SCHEDULE) {
339 scheduler_ipi();
340 }
341 if (ipi.vector & IPI_CALL) {
342 func(info);
343 }
344 if (ipi.vector & IPI_FLUSH_TLB) {
345 if (flush_mm == FLUSH_ALL)
346 __flush_tlb_all();
347 else if (flush_vma == FLUSH_ALL)
348 __flush_tlb_mm(flush_mm);
349 else
350 __flush_tlb_page(flush_vma, flush_addr);
351 }
352
353 ipi.vector = 0;
354 REG_WR(intr_vect, irq_regs[smp_processor_id()], rw_ipi, ipi);
355
356 return IRQ_HANDLED;
357}
358
diff --git a/arch/cris/arch-v32/kernel/time.c b/arch/cris/arch-v32/kernel/time.c
index c17b01abdc3b..aa2d94b7fb61 100644
--- a/arch/cris/arch-v32/kernel/time.c
+++ b/arch/cris/arch-v32/kernel/time.c
@@ -60,9 +60,6 @@ arch_initcall(etrax_init_cont_rotime);
60unsigned long timer_regs[NR_CPUS] = 60unsigned long timer_regs[NR_CPUS] =
61{ 61{
62 regi_timer0, 62 regi_timer0,
63#ifdef CONFIG_SMP
64 regi_timer2
65#endif
66}; 63};
67 64
68extern int set_rtc_mmss(unsigned long nowtime); 65extern int set_rtc_mmss(unsigned long nowtime);
diff --git a/arch/cris/arch-v32/lib/Makefile b/arch/cris/arch-v32/lib/Makefile
index dd296b9db034..e91cf02f625d 100644
--- a/arch/cris/arch-v32/lib/Makefile
+++ b/arch/cris/arch-v32/lib/Makefile
@@ -3,5 +3,5 @@
3# 3#
4 4
5lib-y = checksum.o checksumcopy.o string.o usercopy.o memset.o \ 5lib-y = checksum.o checksumcopy.o string.o usercopy.o memset.o \
6 csumcpfruser.o spinlock.o delay.o strcmp.o 6 csumcpfruser.o delay.o strcmp.o
7 7
diff --git a/arch/cris/arch-v32/lib/spinlock.S b/arch/cris/arch-v32/lib/spinlock.S
deleted file mode 100644
index fe610b9d775f..000000000000
--- a/arch/cris/arch-v32/lib/spinlock.S
+++ /dev/null
@@ -1,40 +0,0 @@
1;; Core of the spinlock implementation
2;;
3;; Copyright (C) 2004 Axis Communications AB.
4;;
5;; Author: Mikael Starvik
6
7
8 .global cris_spin_lock
9 .type cris_spin_lock,@function
10 .global cris_spin_trylock
11 .type cris_spin_trylock,@function
12
13 .text
14
15cris_spin_lock:
16 clearf p
171: test.b [$r10]
18 beq 1b
19 clearf p
20 ax
21 clear.b [$r10]
22 bcs 1b
23 clearf p
24 ret
25 nop
26
27 .size cris_spin_lock, . - cris_spin_lock
28
29cris_spin_trylock:
30 clearf p
311: move.b [$r10], $r11
32 ax
33 clear.b [$r10]
34 bcs 1b
35 clearf p
36 ret
37 movu.b $r11,$r10
38
39 .size cris_spin_trylock, . - cris_spin_trylock
40
diff --git a/arch/cris/arch-v32/mm/init.c b/arch/cris/arch-v32/mm/init.c
index 3deca5253d91..f5438ca8122d 100644
--- a/arch/cris/arch-v32/mm/init.c
+++ b/arch/cris/arch-v32/mm/init.c
@@ -40,17 +40,6 @@ void __init cris_mmu_init(void)
40 */ 40 */
41 per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd; 41 per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd;
42 42
43#ifdef CONFIG_SMP
44 {
45 pgd_t **pgd;
46 pgd = (pgd_t**)&per_cpu(current_pgd, smp_processor_id());
47 SUPP_BANK_SEL(1);
48 SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
49 SUPP_BANK_SEL(2);
50 SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
51 }
52#endif
53
54 /* Initialise the TLB. Function found in tlb.c. */ 43 /* Initialise the TLB. Function found in tlb.c. */
55 tlb_init(); 44 tlb_init();
56 45
diff --git a/arch/cris/arch-v32/mm/mmu.S b/arch/cris/arch-v32/mm/mmu.S
index 72727c1d8e60..c0981044eccb 100644
--- a/arch/cris/arch-v32/mm/mmu.S
+++ b/arch/cris/arch-v32/mm/mmu.S
@@ -115,11 +115,7 @@
115 move.d $r0, [$r1] ; last_refill_cause = rw_mm_cause 115 move.d $r0, [$r1] ; last_refill_cause = rw_mm_cause
116 116
1173: ; Probably not in a loop, continue normal processing 1173: ; Probably not in a loop, continue normal processing
118#ifdef CONFIG_SMP
119 move $s7, $acr ; PGD
120#else
121 move.d current_pgd, $acr ; PGD 118 move.d current_pgd, $acr ; PGD
122#endif
123 ; Look up PMD in PGD 119 ; Look up PMD in PGD
124 lsrq 24, $r0 ; Get PMD index into PGD (bit 24-31) 120 lsrq 24, $r0 ; Get PMD index into PGD (bit 24-31)
125 move.d [$acr], $acr ; PGD for the current process 121 move.d [$acr], $acr ; PGD for the current process