arm64: Provide read/write fault information in compat signal handlers

For AArch32, bit 11 (WnR) of the FSR/ESR register is set when the fault
was caused by a write access and applications like Qemu rely on such
information being provided in sigcontext. This patch introduces the
ESR_EL1 tracking for the arm64 kernel faults and sets bit 11 accordingly
in compat sigcontext.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

1 files changed, 5 insertions, 2 deletions

diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index 7ffadddb645d..c43cfa9b8304 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -251,10 +251,13 @@ void die(const char *str, struct pt_regs *regs, int err)
 void arm64_notify_die(const char *str, struct pt_regs *regs,
                       struct siginfo *info, int err)
 {
-        if (user_mode(regs))
+        if (user_mode(regs)) {
+                current->thread.fault_address = 0;
+                current->thread.fault_code = err;
                 force_sig_info(info->si_signo, info, current);
-        else
+        } else {
                 die(str, regs, err);
+        }
 }
 
 asmlinkage void __exception do_undefinstr(struct pt_regs *regs)