arm64: trap userspace "dc cvau" cache operation on errata-affected core

The ARM errata 819472, 826319, 827319 and 824069 for affected
Cortex-A53 cores demand to promote "dc cvau" instructions to
"dc civac". Since we allow userspace to also emit those instructions,
we should make sure that "dc cvau" gets promoted there too.
So lets grasp the nettle here and actually trap every userland cache
maintenance instruction once we detect at least one affected core in
the system.
We then emulate the instruction by executing it on behalf of userland,
promoting "dc cvau" to "dc civac" on the way and injecting access
fault back into userspace.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[catalin.marinas@arm.com: s/set_segfault/arm64_notify_segfault/]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

1 files changed, 11 insertions, 1 deletions

diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index eefffa81c6df..3eca5d34f7a6 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -451,7 +451,7 @@ el0_sync:
         cmp     x24, #ESR_ELx_EC_FP_EXC64       // FP/ASIMD exception
         b.eq    el0_fpsimd_exc
         cmp     x24, #ESR_ELx_EC_SYS64          // configurable trap
-        b.eq    el0_undef
+        b.eq    el0_sys
         cmp     x24, #ESR_ELx_EC_SP_ALIGN       // stack alignment exception
         b.eq    el0_sp_pc
         cmp     x24, #ESR_ELx_EC_PC_ALIGN       // pc alignment exception
@@ -579,6 +579,16 @@ el0_undef:
         mov     x0, sp
         bl      do_undefinstr
         b       ret_to_user
+el0_sys:
+        /*
+         * System instructions, for trapped cache maintenance instructions
+         */
+        enable_dbg_and_irq
+        ct_user_exit
+        mov     x0, x25
+        mov     x1, sp
+        bl      do_sysinstr
+        b       ret_to_user
 el0_dbg:
         /*
          * Debug exception handling