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authorKukjin Kim <kgene.kim@samsung.com>2010-12-29 20:43:56 -0500
committerKukjin Kim <kgene.kim@samsung.com>2010-12-29 20:43:56 -0500
commit57ca51514905b7aea532977e4e87e989d33bfcbb (patch)
tree93ffb69fb39c248f05ab6fcaa8063f3aa82fd8da /arch/arm/mach-s3c64xx
parente641d15869473d238d4beb0d79dd97a0f7d14e73 (diff)
parentd930596a3c093bf3f4fbf24f10ad0d8372d6ac21 (diff)
Merge branch 'next-samsung' into for-next-new
Diffstat (limited to 'arch/arm/mach-s3c64xx')
-rw-r--r--arch/arm/mach-s3c64xx/irq-eint.c37
1 files changed, 19 insertions, 18 deletions
diff --git a/arch/arm/mach-s3c64xx/irq-eint.c b/arch/arm/mach-s3c64xx/irq-eint.c
index 5682d6a7f4af..2ead8189da74 100644
--- a/arch/arm/mach-s3c64xx/irq-eint.c
+++ b/arch/arm/mach-s3c64xx/irq-eint.c
@@ -30,41 +30,41 @@
30#include <plat/pm.h> 30#include <plat/pm.h>
31 31
32#define eint_offset(irq) ((irq) - IRQ_EINT(0)) 32#define eint_offset(irq) ((irq) - IRQ_EINT(0))
33#define eint_irq_to_bit(irq) (1 << eint_offset(irq)) 33#define eint_irq_to_bit(irq) ((u32)(1 << eint_offset(irq)))
34 34
35static inline void s3c_irq_eint_mask(unsigned int irq) 35static inline void s3c_irq_eint_mask(struct irq_data *data)
36{ 36{
37 u32 mask; 37 u32 mask;
38 38
39 mask = __raw_readl(S3C64XX_EINT0MASK); 39 mask = __raw_readl(S3C64XX_EINT0MASK);
40 mask |= eint_irq_to_bit(irq); 40 mask |= (u32)data->chip_data;
41 __raw_writel(mask, S3C64XX_EINT0MASK); 41 __raw_writel(mask, S3C64XX_EINT0MASK);
42} 42}
43 43
44static void s3c_irq_eint_unmask(unsigned int irq) 44static void s3c_irq_eint_unmask(struct irq_data *data)
45{ 45{
46 u32 mask; 46 u32 mask;
47 47
48 mask = __raw_readl(S3C64XX_EINT0MASK); 48 mask = __raw_readl(S3C64XX_EINT0MASK);
49 mask &= ~eint_irq_to_bit(irq); 49 mask &= ~((u32)data->chip_data);
50 __raw_writel(mask, S3C64XX_EINT0MASK); 50 __raw_writel(mask, S3C64XX_EINT0MASK);
51} 51}
52 52
53static inline void s3c_irq_eint_ack(unsigned int irq) 53static inline void s3c_irq_eint_ack(struct irq_data *data)
54{ 54{
55 __raw_writel(eint_irq_to_bit(irq), S3C64XX_EINT0PEND); 55 __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
56} 56}
57 57
58static void s3c_irq_eint_maskack(unsigned int irq) 58static void s3c_irq_eint_maskack(struct irq_data *data)
59{ 59{
60 /* compiler should in-line these */ 60 /* compiler should in-line these */
61 s3c_irq_eint_mask(irq); 61 s3c_irq_eint_mask(data);
62 s3c_irq_eint_ack(irq); 62 s3c_irq_eint_ack(data);
63} 63}
64 64
65static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) 65static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
66{ 66{
67 int offs = eint_offset(irq); 67 int offs = eint_offset(data->irq);
68 int pin, pin_val; 68 int pin, pin_val;
69 int shift; 69 int shift;
70 u32 ctrl, mask; 70 u32 ctrl, mask;
@@ -140,12 +140,12 @@ static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
140 140
141static struct irq_chip s3c_irq_eint = { 141static struct irq_chip s3c_irq_eint = {
142 .name = "s3c-eint", 142 .name = "s3c-eint",
143 .mask = s3c_irq_eint_mask, 143 .irq_mask = s3c_irq_eint_mask,
144 .unmask = s3c_irq_eint_unmask, 144 .irq_unmask = s3c_irq_eint_unmask,
145 .mask_ack = s3c_irq_eint_maskack, 145 .irq_mask_ack = s3c_irq_eint_maskack,
146 .ack = s3c_irq_eint_ack, 146 .irq_ack = s3c_irq_eint_ack,
147 .set_type = s3c_irq_eint_set_type, 147 .irq_set_type = s3c_irq_eint_set_type,
148 .set_wake = s3c_irqext_wake, 148 .irq_set_wake = s3c_irqext_wake,
149}; 149};
150 150
151/* s3c_irq_demux_eint 151/* s3c_irq_demux_eint
@@ -198,6 +198,7 @@ static int __init s3c64xx_init_irq_eint(void)
198 198
199 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { 199 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
200 set_irq_chip(irq, &s3c_irq_eint); 200 set_irq_chip(irq, &s3c_irq_eint);
201 set_irq_chip_data(irq, (void *)eint_irq_to_bit(irq));
201 set_irq_handler(irq, handle_level_irq); 202 set_irq_handler(irq, handle_level_irq);
202 set_irq_flags(irq, IRQF_VALID); 203 set_irq_flags(irq, IRQF_VALID);
203 } 204 }