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authorTony Lindgren <tony@atomide.com>2013-01-03 14:04:21 -0500
committerTony Lindgren <tony@atomide.com>2013-01-03 14:04:21 -0500
commit2cd1f483b8c80b2f6b032edddb18f4946f94c4fc (patch)
tree8ae4a5803a08cd8049dd481cbd9d2d8cc3ac209b /arch/arm/mach-omap2/prm2xxx.c
parentd1c3ed669a2d452cacfb48c2d171a1f364dae2ed (diff)
parent7e7fff8254e318cede06a1a8c55b0d86dd4d8c5b (diff)
Merge tag 'omap-fixes-a2-for-v3.8-rc' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.8-rc2/fixes
Some OMAP PRCM and sparse fixes against v3.8-rc1. A basic set of test logs are available here: http://www.pwsan.com/omap/testlogs/prcm_fixes_b_3.8-rc/20130102120724/ The 3730 Beagle XM here has an intermittent failure mounting SD root, but the suspicion right now is that this is due to a failing SD card, rather than any change introduced by these patches. This second version includes a few changes requested by Tony Lindgren.
Diffstat (limited to 'arch/arm/mach-omap2/prm2xxx.c')
-rw-r--r--arch/arm/mach-omap2/prm2xxx.c88
1 files changed, 85 insertions, 3 deletions
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index cc0e71430af1..418de9c3b319 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -28,6 +28,14 @@
28#include "prm-regbits-24xx.h" 28#include "prm-regbits-24xx.h"
29 29
30/* 30/*
31 * OMAP24xx PM_PWSTCTRL_*.POWERSTATE and PM_PWSTST_*.LASTSTATEENTERED bits -
32 * these are reversed from the bits used on OMAP3+
33 */
34#define OMAP24XX_PWRDM_POWER_ON 0x0
35#define OMAP24XX_PWRDM_POWER_RET 0x1
36#define OMAP24XX_PWRDM_POWER_OFF 0x3
37
38/*
31 * omap2xxx_prm_reset_src_map - map from bits in the PRM_RSTST_WKUP 39 * omap2xxx_prm_reset_src_map - map from bits in the PRM_RSTST_WKUP
32 * hardware register (which are specific to the OMAP2xxx SoCs) to 40 * hardware register (which are specific to the OMAP2xxx SoCs) to
33 * reset source ID bit shifts (which is an OMAP SoC-independent 41 * reset source ID bit shifts (which is an OMAP SoC-independent
@@ -68,6 +76,34 @@ static u32 omap2xxx_prm_read_reset_sources(void)
68} 76}
69 77
70/** 78/**
79 * omap2xxx_pwrst_to_common_pwrst - convert OMAP2xxx pwrst to common pwrst
80 * @omap2xxx_pwrst: OMAP2xxx hardware power state to convert
81 *
82 * Return the common power state bits corresponding to the OMAP2xxx
83 * hardware power state bits @omap2xxx_pwrst, or -EINVAL upon error.
84 */
85static int omap2xxx_pwrst_to_common_pwrst(u8 omap2xxx_pwrst)
86{
87 u8 pwrst;
88
89 switch (omap2xxx_pwrst) {
90 case OMAP24XX_PWRDM_POWER_OFF:
91 pwrst = PWRDM_POWER_OFF;
92 break;
93 case OMAP24XX_PWRDM_POWER_RET:
94 pwrst = PWRDM_POWER_RET;
95 break;
96 case OMAP24XX_PWRDM_POWER_ON:
97 pwrst = PWRDM_POWER_ON;
98 break;
99 default:
100 return -EINVAL;
101 }
102
103 return pwrst;
104}
105
106/**
71 * omap2xxx_prm_dpll_reset - use DPLL reset to reboot the OMAP SoC 107 * omap2xxx_prm_dpll_reset - use DPLL reset to reboot the OMAP SoC
72 * 108 *
73 * Set the DPLL reset bit, which should reboot the SoC. This is the 109 * Set the DPLL reset bit, which should reboot the SoC. This is the
@@ -97,10 +133,56 @@ int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm)
97 return 0; 133 return 0;
98} 134}
99 135
136static int omap2xxx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
137{
138 u8 omap24xx_pwrst;
139
140 switch (pwrst) {
141 case PWRDM_POWER_OFF:
142 omap24xx_pwrst = OMAP24XX_PWRDM_POWER_OFF;
143 break;
144 case PWRDM_POWER_RET:
145 omap24xx_pwrst = OMAP24XX_PWRDM_POWER_RET;
146 break;
147 case PWRDM_POWER_ON:
148 omap24xx_pwrst = OMAP24XX_PWRDM_POWER_ON;
149 break;
150 default:
151 return -EINVAL;
152 }
153
154 omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
155 (omap24xx_pwrst << OMAP_POWERSTATE_SHIFT),
156 pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
157 return 0;
158}
159
160static int omap2xxx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
161{
162 u8 omap2xxx_pwrst;
163
164 omap2xxx_pwrst = omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
165 OMAP2_PM_PWSTCTRL,
166 OMAP_POWERSTATE_MASK);
167
168 return omap2xxx_pwrst_to_common_pwrst(omap2xxx_pwrst);
169}
170
171static int omap2xxx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
172{
173 u8 omap2xxx_pwrst;
174
175 omap2xxx_pwrst = omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
176 OMAP2_PM_PWSTST,
177 OMAP_POWERSTATEST_MASK);
178
179 return omap2xxx_pwrst_to_common_pwrst(omap2xxx_pwrst);
180}
181
100struct pwrdm_ops omap2_pwrdm_operations = { 182struct pwrdm_ops omap2_pwrdm_operations = {
101 .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst, 183 .pwrdm_set_next_pwrst = omap2xxx_pwrdm_set_next_pwrst,
102 .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst, 184 .pwrdm_read_next_pwrst = omap2xxx_pwrdm_read_next_pwrst,
103 .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst, 185 .pwrdm_read_pwrst = omap2xxx_pwrdm_read_pwrst,
104 .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst, 186 .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst,
105 .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst, 187 .pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst,
106 .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst, 188 .pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst,