diff options
author | Anson Huang <Anson.Huang@nxp.com> | 2016-08-29 11:41:12 -0400 |
---|---|---|
committer | Shawn Guo <shawnguo@kernel.org> | 2016-08-29 10:39:28 -0400 |
commit | 547e8f526959ded88b93dbdbbb6c8549138fefa8 (patch) | |
tree | 9b272a64fc144c92bac86382e418b8518d0bbcdf /arch/arm/mach-imx | |
parent | 6ae44aa651d0d82097cb5379be94e86beade9c7b (diff) |
ARM: imx: add cpuidle support for i.mx6ul
This patch enables cpuidle driver for i.MX6UL, it
reuses i.MX6SX's cpuidle driver, 3 levels of cpuidle
supported:
1. ARM WFI;
2. SOC in WAIT mode;
3. SOC in WAIT mode + ARM power off.
As i.MX6UL has cortex-A7 CORE with an internal L2
cache, so flushing it before powering down ARM platform
is necessary, flush_cache_all() in last step of cpu_suspend
has very small overhead, just call it to avoid cache
type check for different platforms.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/mach-imx')
-rw-r--r-- | arch/arm/mach-imx/cpuidle-imx6sx.c | 10 | ||||
-rw-r--r-- | arch/arm/mach-imx/mach-imx6ul.c | 3 |
2 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c b/arch/arm/mach-imx/cpuidle-imx6sx.c index 261aaa45ff33..c5a5c3a70ab1 100644 --- a/arch/arm/mach-imx/cpuidle-imx6sx.c +++ b/arch/arm/mach-imx/cpuidle-imx6sx.c | |||
@@ -9,6 +9,7 @@ | |||
9 | #include <linux/cpuidle.h> | 9 | #include <linux/cpuidle.h> |
10 | #include <linux/cpu_pm.h> | 10 | #include <linux/cpu_pm.h> |
11 | #include <linux/module.h> | 11 | #include <linux/module.h> |
12 | #include <asm/cacheflush.h> | ||
12 | #include <asm/cpuidle.h> | 13 | #include <asm/cpuidle.h> |
13 | #include <asm/suspend.h> | 14 | #include <asm/suspend.h> |
14 | 15 | ||
@@ -17,6 +18,15 @@ | |||
17 | 18 | ||
18 | static int imx6sx_idle_finish(unsigned long val) | 19 | static int imx6sx_idle_finish(unsigned long val) |
19 | { | 20 | { |
21 | /* | ||
22 | * for Cortex-A7 which has an internal L2 | ||
23 | * cache, need to flush it before powering | ||
24 | * down ARM platform, since flushing L1 cache | ||
25 | * here again has very small overhead, compared | ||
26 | * to adding conditional code for L2 cache type, | ||
27 | * just call flush_cache_all() is fine. | ||
28 | */ | ||
29 | flush_cache_all(); | ||
20 | cpu_do_idle(); | 30 | cpu_do_idle(); |
21 | 31 | ||
22 | return 0; | 32 | return 0; |
diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c index 5d9bfab279dd..08308a127ff7 100644 --- a/arch/arm/mach-imx/mach-imx6ul.c +++ b/arch/arm/mach-imx/mach-imx6ul.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <asm/mach/map.h> | 16 | #include <asm/mach/map.h> |
17 | 17 | ||
18 | #include "common.h" | 18 | #include "common.h" |
19 | #include "cpuidle.h" | ||
19 | 20 | ||
20 | static void __init imx6ul_enet_clk_init(void) | 21 | static void __init imx6ul_enet_clk_init(void) |
21 | { | 22 | { |
@@ -79,6 +80,8 @@ static void __init imx6ul_init_irq(void) | |||
79 | 80 | ||
80 | static void __init imx6ul_init_late(void) | 81 | static void __init imx6ul_init_late(void) |
81 | { | 82 | { |
83 | imx6sx_cpuidle_init(); | ||
84 | |||
82 | if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) | 85 | if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) |
83 | platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); | 86 | platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0); |
84 | } | 87 | } |