Documentation: devicetree: add qca8k binding

Add device-tree binding for ar8xxx switch families.

Cc: devicetree@vger.kernel.org
Signed-off-by: John Crispin <john@phrozen.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 89 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
new file mode 100644
index 000000000000..9c67ee4890d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
@@ -0,0 +1,89 @@
+* Qualcomm Atheros QCA8xxx switch family
+
+Required properties:
+
+- compatible: should be "qca,qca8337"
+- #size-cells: must be 0
+- #address-cells: must be 1
+
+Subnodes:
+
+The integrated switch subnode should be specified according to the binding
+described in dsa/dsa.txt. As the QCA8K switches do not have a N:N mapping of
+port and PHY id, each subnode describing a port needs to have a valid phandle
+referencing the internal PHY connected to it. The CPU port of this switch is
+always port 0.
+
+Example:
+
+
+        &mdio0 {
+                phy_port1: phy@0 {
+                        reg = <0>;
+                };
+
+                phy_port2: phy@1 {
+                        reg = <1>;
+                };
+
+                phy_port3: phy@2 {
+                        reg = <2>;
+                };
+
+                phy_port4: phy@3 {
+                        reg = <3>;
+                };
+
+                phy_port5: phy@4 {
+                        reg = <4>;
+                };
+
+                switch0@0 {
+                        compatible = "qca,qca8337";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        reg = <0>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                port@0 {
+                                        reg = <0>;
+                                        label = "cpu";
+                                        ethernet = <&gmac1>;
+                                        phy-mode = "rgmii";
+                                };
+
+                                port@1 {
+                                        reg = <1>;
+                                        label = "lan1";
+                                        phy-handle = <&phy_port1>;
+                                };
+
+                                port@2 {
+                                        reg = <2>;
+                                        label = "lan2";
+                                        phy-handle = <&phy_port2>;
+                                };
+
+                                port@3 {
+                                        reg = <3>;
+                                        label = "lan3";
+                                        phy-handle = <&phy_port3>;
+                                };
+
+                                port@4 {
+                                        reg = <4>;
+                                        label = "lan4";
+                                        phy-handle = <&phy_port4>;
+                                };
+
+                                port@5 {
+                                        reg = <5>;
+                                        label = "wan";
+                                        phy-handle = <&phy_port5>;
+                                };
+                        };
+                };
+        };