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authorJingoo Han <jg1.han@samsung.com>2013-10-16 12:28:15 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-10-16 16:48:09 -0400
commitf9b1e013f1c6723798b8f7f5b83297e2837aaef7 (patch)
tree9ecaaf588982d2a89ce6413653b8eeb9f4591bdb
parent74988e8b5718b561457fd035dc3ab9b9d8f45a5d (diff)
video: exynos_dp: remove non-DT support for Exynos Display Port
Exynos Display Port can be used only for Exynos SoCs. In addition, non-DT for EXYNOS SoCs is not supported from v3.11; thus, there is no need to support non-DT for Exynos Display Port. The 'include/video/exynos_dp.h' file has been used for non-DT support and the content of file include/video/exynos_dp.h is moved to drivers/video/exynos/exynos_dp_core.h. Thus, the 'exynos_dp.h' file is removed. Also, 'struct exynos_dp_platdata' is removed, because it is not used any more. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/video/exynos/Kconfig2
-rw-r--r--drivers/video/exynos/exynos_dp_core.c116
-rw-r--r--drivers/video/exynos/exynos_dp_core.h109
-rw-r--r--drivers/video/exynos/exynos_dp_reg.c2
-rw-r--r--include/video/exynos_dp.h131
5 files changed, 135 insertions, 225 deletions
diff --git a/drivers/video/exynos/Kconfig b/drivers/video/exynos/Kconfig
index 976594d578a9..1129d0e9e640 100644
--- a/drivers/video/exynos/Kconfig
+++ b/drivers/video/exynos/Kconfig
@@ -30,7 +30,7 @@ config EXYNOS_LCD_S6E8AX0
30 30
31config EXYNOS_DP 31config EXYNOS_DP
32 bool "EXYNOS DP driver support" 32 bool "EXYNOS DP driver support"
33 depends on ARCH_EXYNOS 33 depends on OF && ARCH_EXYNOS
34 default n 34 default n
35 help 35 help
36 This enables support for DP device. 36 This enables support for DP device.
diff --git a/drivers/video/exynos/exynos_dp_core.c b/drivers/video/exynos/exynos_dp_core.c
index 12bbede3b091..05fed7dc67da 100644
--- a/drivers/video/exynos/exynos_dp_core.c
+++ b/drivers/video/exynos/exynos_dp_core.c
@@ -20,8 +20,6 @@
20#include <linux/delay.h> 20#include <linux/delay.h>
21#include <linux/of.h> 21#include <linux/of.h>
22 22
23#include <video/exynos_dp.h>
24
25#include "exynos_dp_core.h" 23#include "exynos_dp_core.h"
26 24
27static int exynos_dp_init_dp(struct exynos_dp_device *dp) 25static int exynos_dp_init_dp(struct exynos_dp_device *dp)
@@ -894,26 +892,17 @@ static void exynos_dp_hotplug(struct work_struct *work)
894 dev_err(dp->dev, "unable to config video\n"); 892 dev_err(dp->dev, "unable to config video\n");
895} 893}
896 894
897#ifdef CONFIG_OF 895static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
898static struct exynos_dp_platdata *exynos_dp_dt_parse_pdata(struct device *dev)
899{ 896{
900 struct device_node *dp_node = dev->of_node; 897 struct device_node *dp_node = dev->of_node;
901 struct exynos_dp_platdata *pd;
902 struct video_info *dp_video_config; 898 struct video_info *dp_video_config;
903 899
904 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
905 if (!pd) {
906 dev_err(dev, "memory allocation for pdata failed\n");
907 return ERR_PTR(-ENOMEM);
908 }
909 dp_video_config = devm_kzalloc(dev, 900 dp_video_config = devm_kzalloc(dev,
910 sizeof(*dp_video_config), GFP_KERNEL); 901 sizeof(*dp_video_config), GFP_KERNEL);
911
912 if (!dp_video_config) { 902 if (!dp_video_config) {
913 dev_err(dev, "memory allocation for video config failed\n"); 903 dev_err(dev, "memory allocation for video config failed\n");
914 return ERR_PTR(-ENOMEM); 904 return ERR_PTR(-ENOMEM);
915 } 905 }
916 pd->video_info = dp_video_config;
917 906
918 dp_video_config->h_sync_polarity = 907 dp_video_config->h_sync_polarity =
919 of_property_read_bool(dp_node, "hsync-active-high"); 908 of_property_read_bool(dp_node, "hsync-active-high");
@@ -960,7 +949,7 @@ static struct exynos_dp_platdata *exynos_dp_dt_parse_pdata(struct device *dev)
960 return ERR_PTR(-EINVAL); 949 return ERR_PTR(-EINVAL);
961 } 950 }
962 951
963 return pd; 952 return dp_video_config;
964} 953}
965 954
966static int exynos_dp_dt_parse_phydata(struct exynos_dp_device *dp) 955static int exynos_dp_dt_parse_phydata(struct exynos_dp_device *dp)
@@ -1003,48 +992,30 @@ err:
1003 992
1004static void exynos_dp_phy_init(struct exynos_dp_device *dp) 993static void exynos_dp_phy_init(struct exynos_dp_device *dp)
1005{ 994{
1006 u32 reg; 995 if (dp->phy_addr) {
996 u32 reg;
1007 997
1008 reg = __raw_readl(dp->phy_addr); 998 reg = __raw_readl(dp->phy_addr);
1009 reg |= dp->enable_mask; 999 reg |= dp->enable_mask;
1010 __raw_writel(reg, dp->phy_addr); 1000 __raw_writel(reg, dp->phy_addr);
1001 }
1011} 1002}
1012 1003
1013static void exynos_dp_phy_exit(struct exynos_dp_device *dp) 1004static void exynos_dp_phy_exit(struct exynos_dp_device *dp)
1014{ 1005{
1015 u32 reg; 1006 if (dp->phy_addr) {
1016 1007 u32 reg;
1017 reg = __raw_readl(dp->phy_addr);
1018 reg &= ~(dp->enable_mask);
1019 __raw_writel(reg, dp->phy_addr);
1020}
1021#else
1022static struct exynos_dp_platdata *exynos_dp_dt_parse_pdata(struct device *dev)
1023{
1024 return NULL;
1025}
1026
1027static int exynos_dp_dt_parse_phydata(struct exynos_dp_device *dp)
1028{
1029 return -EINVAL;
1030}
1031
1032static void exynos_dp_phy_init(struct exynos_dp_device *dp)
1033{
1034 return;
1035}
1036 1008
1037static void exynos_dp_phy_exit(struct exynos_dp_device *dp) 1009 reg = __raw_readl(dp->phy_addr);
1038{ 1010 reg &= ~(dp->enable_mask);
1039 return; 1011 __raw_writel(reg, dp->phy_addr);
1012 }
1040} 1013}
1041#endif /* CONFIG_OF */
1042 1014
1043static int exynos_dp_probe(struct platform_device *pdev) 1015static int exynos_dp_probe(struct platform_device *pdev)
1044{ 1016{
1045 struct resource *res; 1017 struct resource *res;
1046 struct exynos_dp_device *dp; 1018 struct exynos_dp_device *dp;
1047 struct exynos_dp_platdata *pdata;
1048 1019
1049 int ret = 0; 1020 int ret = 0;
1050 1021
@@ -1057,21 +1028,13 @@ static int exynos_dp_probe(struct platform_device *pdev)
1057 1028
1058 dp->dev = &pdev->dev; 1029 dp->dev = &pdev->dev;
1059 1030
1060 if (pdev->dev.of_node) { 1031 dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev);
1061 pdata = exynos_dp_dt_parse_pdata(&pdev->dev); 1032 if (IS_ERR(dp->video_info))
1062 if (IS_ERR(pdata)) 1033 return PTR_ERR(dp->video_info);
1063 return PTR_ERR(pdata);
1064 1034
1065 ret = exynos_dp_dt_parse_phydata(dp); 1035 ret = exynos_dp_dt_parse_phydata(dp);
1066 if (ret) 1036 if (ret)
1067 return ret; 1037 return ret;
1068 } else {
1069 pdata = pdev->dev.platform_data;
1070 if (!pdata) {
1071 dev_err(&pdev->dev, "no platform data\n");
1072 return -EINVAL;
1073 }
1074 }
1075 1038
1076 dp->clock = devm_clk_get(&pdev->dev, "dp"); 1039 dp->clock = devm_clk_get(&pdev->dev, "dp");
1077 if (IS_ERR(dp->clock)) { 1040 if (IS_ERR(dp->clock)) {
@@ -1095,15 +1058,7 @@ static int exynos_dp_probe(struct platform_device *pdev)
1095 1058
1096 INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug); 1059 INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
1097 1060
1098 dp->video_info = pdata->video_info; 1061 exynos_dp_phy_init(dp);
1099
1100 if (pdev->dev.of_node) {
1101 if (dp->phy_addr)
1102 exynos_dp_phy_init(dp);
1103 } else {
1104 if (pdata->phy_init)
1105 pdata->phy_init();
1106 }
1107 1062
1108 exynos_dp_init_dp(dp); 1063 exynos_dp_init_dp(dp);
1109 1064
@@ -1121,18 +1076,11 @@ static int exynos_dp_probe(struct platform_device *pdev)
1121 1076
1122static int exynos_dp_remove(struct platform_device *pdev) 1077static int exynos_dp_remove(struct platform_device *pdev)
1123{ 1078{
1124 struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
1125 struct exynos_dp_device *dp = platform_get_drvdata(pdev); 1079 struct exynos_dp_device *dp = platform_get_drvdata(pdev);
1126 1080
1127 flush_work(&dp->hotplug_work); 1081 flush_work(&dp->hotplug_work);
1128 1082
1129 if (pdev->dev.of_node) { 1083 exynos_dp_phy_exit(dp);
1130 if (dp->phy_addr)
1131 exynos_dp_phy_exit(dp);
1132 } else {
1133 if (pdata->phy_exit)
1134 pdata->phy_exit();
1135 }
1136 1084
1137 clk_disable_unprepare(dp->clock); 1085 clk_disable_unprepare(dp->clock);
1138 1086
@@ -1143,20 +1091,13 @@ static int exynos_dp_remove(struct platform_device *pdev)
1143#ifdef CONFIG_PM_SLEEP 1091#ifdef CONFIG_PM_SLEEP
1144static int exynos_dp_suspend(struct device *dev) 1092static int exynos_dp_suspend(struct device *dev)
1145{ 1093{
1146 struct exynos_dp_platdata *pdata = dev->platform_data;
1147 struct exynos_dp_device *dp = dev_get_drvdata(dev); 1094 struct exynos_dp_device *dp = dev_get_drvdata(dev);
1148 1095
1149 disable_irq(dp->irq); 1096 disable_irq(dp->irq);
1150 1097
1151 flush_work(&dp->hotplug_work); 1098 flush_work(&dp->hotplug_work);
1152 1099
1153 if (dev->of_node) { 1100 exynos_dp_phy_exit(dp);
1154 if (dp->phy_addr)
1155 exynos_dp_phy_exit(dp);
1156 } else {
1157 if (pdata->phy_exit)
1158 pdata->phy_exit();
1159 }
1160 1101
1161 clk_disable_unprepare(dp->clock); 1102 clk_disable_unprepare(dp->clock);
1162 1103
@@ -1165,16 +1106,9 @@ static int exynos_dp_suspend(struct device *dev)
1165 1106
1166static int exynos_dp_resume(struct device *dev) 1107static int exynos_dp_resume(struct device *dev)
1167{ 1108{
1168 struct exynos_dp_platdata *pdata = dev->platform_data;
1169 struct exynos_dp_device *dp = dev_get_drvdata(dev); 1109 struct exynos_dp_device *dp = dev_get_drvdata(dev);
1170 1110
1171 if (dev->of_node) { 1111 exynos_dp_phy_init(dp);
1172 if (dp->phy_addr)
1173 exynos_dp_phy_init(dp);
1174 } else {
1175 if (pdata->phy_init)
1176 pdata->phy_init();
1177 }
1178 1112
1179 clk_prepare_enable(dp->clock); 1113 clk_prepare_enable(dp->clock);
1180 1114
@@ -1203,7 +1137,7 @@ static struct platform_driver exynos_dp_driver = {
1203 .name = "exynos-dp", 1137 .name = "exynos-dp",
1204 .owner = THIS_MODULE, 1138 .owner = THIS_MODULE,
1205 .pm = &exynos_dp_pm_ops, 1139 .pm = &exynos_dp_pm_ops,
1206 .of_match_table = of_match_ptr(exynos_dp_match), 1140 .of_match_table = exynos_dp_match,
1207 }, 1141 },
1208}; 1142};
1209 1143
diff --git a/drivers/video/exynos/exynos_dp_core.h b/drivers/video/exynos/exynos_dp_core.h
index 6c567bbf2fb8..56cfec890b46 100644
--- a/drivers/video/exynos/exynos_dp_core.h
+++ b/drivers/video/exynos/exynos_dp_core.h
@@ -13,6 +13,99 @@
13#ifndef _EXYNOS_DP_CORE_H 13#ifndef _EXYNOS_DP_CORE_H
14#define _EXYNOS_DP_CORE_H 14#define _EXYNOS_DP_CORE_H
15 15
16#define DP_TIMEOUT_LOOP_COUNT 100
17#define MAX_CR_LOOP 5
18#define MAX_EQ_LOOP 5
19
20enum link_rate_type {
21 LINK_RATE_1_62GBPS = 0x06,
22 LINK_RATE_2_70GBPS = 0x0a
23};
24
25enum link_lane_count_type {
26 LANE_COUNT1 = 1,
27 LANE_COUNT2 = 2,
28 LANE_COUNT4 = 4
29};
30
31enum link_training_state {
32 START,
33 CLOCK_RECOVERY,
34 EQUALIZER_TRAINING,
35 FINISHED,
36 FAILED
37};
38
39enum voltage_swing_level {
40 VOLTAGE_LEVEL_0,
41 VOLTAGE_LEVEL_1,
42 VOLTAGE_LEVEL_2,
43 VOLTAGE_LEVEL_3,
44};
45
46enum pre_emphasis_level {
47 PRE_EMPHASIS_LEVEL_0,
48 PRE_EMPHASIS_LEVEL_1,
49 PRE_EMPHASIS_LEVEL_2,
50 PRE_EMPHASIS_LEVEL_3,
51};
52
53enum pattern_set {
54 PRBS7,
55 D10_2,
56 TRAINING_PTN1,
57 TRAINING_PTN2,
58 DP_NONE
59};
60
61enum color_space {
62 COLOR_RGB,
63 COLOR_YCBCR422,
64 COLOR_YCBCR444
65};
66
67enum color_depth {
68 COLOR_6,
69 COLOR_8,
70 COLOR_10,
71 COLOR_12
72};
73
74enum color_coefficient {
75 COLOR_YCBCR601,
76 COLOR_YCBCR709
77};
78
79enum dynamic_range {
80 VESA,
81 CEA
82};
83
84enum pll_status {
85 PLL_UNLOCKED,
86 PLL_LOCKED
87};
88
89enum clock_recovery_m_value_type {
90 CALCULATED_M,
91 REGISTER_M
92};
93
94enum video_timing_recognition_type {
95 VIDEO_TIMING_FROM_CAPTURE,
96 VIDEO_TIMING_FROM_REGISTER
97};
98
99enum analog_power_block {
100 AUX_BLOCK,
101 CH0_BLOCK,
102 CH1_BLOCK,
103 CH2_BLOCK,
104 CH3_BLOCK,
105 ANALOG_TOTAL,
106 POWER_ALL
107};
108
16enum dp_irq_type { 109enum dp_irq_type {
17 DP_IRQ_TYPE_HP_CABLE_IN, 110 DP_IRQ_TYPE_HP_CABLE_IN,
18 DP_IRQ_TYPE_HP_CABLE_OUT, 111 DP_IRQ_TYPE_HP_CABLE_OUT,
@@ -20,6 +113,22 @@ enum dp_irq_type {
20 DP_IRQ_TYPE_UNKNOWN, 113 DP_IRQ_TYPE_UNKNOWN,
21}; 114};
22 115
116struct video_info {
117 char *name;
118
119 bool h_sync_polarity;
120 bool v_sync_polarity;
121 bool interlaced;
122
123 enum color_space color_space;
124 enum dynamic_range dynamic_range;
125 enum color_coefficient ycbcr_coeff;
126 enum color_depth color_depth;
127
128 enum link_rate_type link_rate;
129 enum link_lane_count_type lane_count;
130};
131
23struct link_train { 132struct link_train {
24 int eq_loop; 133 int eq_loop;
25 int cr_loop[4]; 134 int cr_loop[4];
diff --git a/drivers/video/exynos/exynos_dp_reg.c b/drivers/video/exynos/exynos_dp_reg.c
index 29d9d035c73a..b70da5052ff0 100644
--- a/drivers/video/exynos/exynos_dp_reg.c
+++ b/drivers/video/exynos/exynos_dp_reg.c
@@ -14,8 +14,6 @@
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/delay.h> 15#include <linux/delay.h>
16 16
17#include <video/exynos_dp.h>
18
19#include "exynos_dp_core.h" 17#include "exynos_dp_core.h"
20#include "exynos_dp_reg.h" 18#include "exynos_dp_reg.h"
21 19
diff --git a/include/video/exynos_dp.h b/include/video/exynos_dp.h
deleted file mode 100644
index bd8cabd344db..000000000000
--- a/include/video/exynos_dp.h
+++ /dev/null
@@ -1,131 +0,0 @@
1/*
2 * Samsung SoC DP device support
3 *
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef _EXYNOS_DP_H
13#define _EXYNOS_DP_H
14
15#define DP_TIMEOUT_LOOP_COUNT 100
16#define MAX_CR_LOOP 5
17#define MAX_EQ_LOOP 5
18
19enum link_rate_type {
20 LINK_RATE_1_62GBPS = 0x06,
21 LINK_RATE_2_70GBPS = 0x0a
22};
23
24enum link_lane_count_type {
25 LANE_COUNT1 = 1,
26 LANE_COUNT2 = 2,
27 LANE_COUNT4 = 4
28};
29
30enum link_training_state {
31 START,
32 CLOCK_RECOVERY,
33 EQUALIZER_TRAINING,
34 FINISHED,
35 FAILED
36};
37
38enum voltage_swing_level {
39 VOLTAGE_LEVEL_0,
40 VOLTAGE_LEVEL_1,
41 VOLTAGE_LEVEL_2,
42 VOLTAGE_LEVEL_3,
43};
44
45enum pre_emphasis_level {
46 PRE_EMPHASIS_LEVEL_0,
47 PRE_EMPHASIS_LEVEL_1,
48 PRE_EMPHASIS_LEVEL_2,
49 PRE_EMPHASIS_LEVEL_3,
50};
51
52enum pattern_set {
53 PRBS7,
54 D10_2,
55 TRAINING_PTN1,
56 TRAINING_PTN2,
57 DP_NONE
58};
59
60enum color_space {
61 COLOR_RGB,
62 COLOR_YCBCR422,
63 COLOR_YCBCR444
64};
65
66enum color_depth {
67 COLOR_6,
68 COLOR_8,
69 COLOR_10,
70 COLOR_12
71};
72
73enum color_coefficient {
74 COLOR_YCBCR601,
75 COLOR_YCBCR709
76};
77
78enum dynamic_range {
79 VESA,
80 CEA
81};
82
83enum pll_status {
84 PLL_UNLOCKED,
85 PLL_LOCKED
86};
87
88enum clock_recovery_m_value_type {
89 CALCULATED_M,
90 REGISTER_M
91};
92
93enum video_timing_recognition_type {
94 VIDEO_TIMING_FROM_CAPTURE,
95 VIDEO_TIMING_FROM_REGISTER
96};
97
98enum analog_power_block {
99 AUX_BLOCK,
100 CH0_BLOCK,
101 CH1_BLOCK,
102 CH2_BLOCK,
103 CH3_BLOCK,
104 ANALOG_TOTAL,
105 POWER_ALL
106};
107
108struct video_info {
109 char *name;
110
111 bool h_sync_polarity;
112 bool v_sync_polarity;
113 bool interlaced;
114
115 enum color_space color_space;
116 enum dynamic_range dynamic_range;
117 enum color_coefficient ycbcr_coeff;
118 enum color_depth color_depth;
119
120 enum link_rate_type link_rate;
121 enum link_lane_count_type lane_count;
122};
123
124struct exynos_dp_platdata {
125 struct video_info *video_info;
126
127 void (*phy_init)(void);
128 void (*phy_exit)(void);
129};
130
131#endif /* _EXYNOS_DP_H */