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path: root/drivers/char/drm/i810_dma.c
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/* i810_dma.c -- DMA support for the i810 -*- linux-c -*-
 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
 *
 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
 *	    Jeff Hartmann <jhartmann@valinux.com>
 *          Keith Whitwell <keith@tungstengraphics.com>
 *
 */

#include "drmP.h"
#include "drm.h"
#include "i810_drm.h"
#include "i810_drv.h"
#include <linux/interrupt.h>	/* For task queue support */
#include <linux/delay.h>
#include <linux/pagemap.h>

#define I810_BUF_FREE		2
#define I810_BUF_CLIENT		1
#define I810_BUF_HARDWARE      	0

#define I810_BUF_UNMAPPED 0
#define I810_BUF_MAPPED   1

static struct drm_buf *i810_freelist_get(struct drm_device * dev)
{
	struct drm_device_dma *dma = dev->dma;
	int i;
	int used;

	/* Linear search might not be the best solution */

	for (i = 0; i < dma->buf_count; i++) {
		struct drm_buf *buf = dma->buflist[i];
		drm_i810_buf_priv_t *buf_priv = buf->dev_private;
		/* In use is already a pointer */
		used = cmpxchg(buf_priv->in_use, I810_BUF_FREE,
			       I810_BUF_CLIENT);
		if (used == I810_BUF_FREE) {
			return buf;
		}
	}
	return NULL;
}

/* This should only be called if the buffer is not sent to the hardware
 * yet, the hardware updates in use for us once its on the ring buffer.
 */

static int i810_freelist_put(struct drm_device * dev, struct drm_buf * buf)
{
	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
	int used;

	/* In use is already a pointer */
	used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_FREE);
	if (used != I810_BUF_CLIENT) {
		DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
		return -EINVAL;
	}

	return 0;
}

static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
{
	struct drm_file *priv = filp->private_data;
	struct drm_device *dev;
	drm_i810_private_t *dev_priv;
	struct drm_buf *buf;
	drm_i810_buf_priv_t *buf_priv;

	lock_kernel();
	dev = priv->head->dev;
	dev_priv = dev->dev_private;
	buf = dev_priv->mmap_buffer;
	buf_priv = buf->dev_private;

	vma->vm_flags |= (VM_IO | VM_DONTCOPY);
	vma->vm_file = filp;

	buf_priv->currently_mapped = I810_BUF_MAPPED;
	unlock_kernel();

	if (io_remap_pfn_range(vma, vma->vm_start,
			       vma->vm_pgoff,
			       vma->vm_end - vma->vm_start, vma->vm_page_prot))
		return -EAGAIN;
	return 0;
}

static const struct file_operations i810_buffer_fops = {
	.open = drm_open,
	.release = drm_release,
	.ioctl = drm_ioctl,
	.mmap = i810_mmap_buffers,
	.fasync = drm_fasync,
};

static int i810_map_buffer(struct drm_buf * buf, struct drm_file *file_priv)
{
	struct drm_device *dev = file_priv->head->dev;
	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
	drm_i810_private_t *dev_priv = dev->dev_private;
	const struct file_operations *old_fops;
	int retcode = 0;

	if (buf_priv->currently_mapped == I810_BUF_MAPPED)
		return -EINVAL;

	down_write(&current->mm->mmap_sem);
	old_fops = file_priv->filp->f_op;
	file_priv->filp->f_op = &i810_buffer_fops;
	dev_priv->mmap_buffer = buf;
	buf_priv->virtual = (void *)do_mmap(file_priv->filp, 0, buf->total,
					    PROT_READ | PROT_WRITE,
					    MAP_SHARED, buf->bus_address);
	dev_priv->mmap_buffer = NULL;
	file_priv->filp->f_op = old_fops;
	if (IS_ERR(buf_priv->virtual)) {
		/* Real error */
		DRM_ERROR("mmap error\n");
		retcode = PTR_ERR(buf_priv->virtual);
		buf_priv->virtual = NULL;
	}
	up_write(&current->mm->mmap_sem);

	return retcode;
}

static int i810_unmap_buffer(struct drm_buf * buf)
{
	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
	int retcode = 0;

	if (buf_priv->currently_mapped != I810_BUF_MAPPED)
		return -EINVAL;

	down_write(&current->mm->mmap_sem);
	retcode = do_munmap(current->mm,
			    (unsigned long)buf_priv->virtual,
			    (size_t) buf->total);
	up_write(&current->mm->mmap_sem);

	buf_priv->currently_mapped = I810_BUF_UNMAPPED;
	buf_priv->virtual = NULL;

	return retcode;
}

static int i810_dma_get_buffer(struct drm_device * dev, drm_i810_dma_t * d,
			       struct drm_file *file_priv)
{
	struct drm_buf *buf;
	drm_i810_buf_priv_t *buf_priv;
	int retcode = 0;

	buf = i810_freelist_get(dev);
	if (!buf) {
		retcode = -ENOMEM;
		DRM_DEBUG("retcode=%d\n", retcode);
		return retcode;
	}

	retcode = i810_map_buffer(buf, file_priv);
	if (retcode) {
		i810_freelist_put(dev, buf);
		DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
		return retcode;
	}
	buf->file_priv = file_priv;
	buf_priv = buf->dev_private;
	d->granted = 1;
	d->request_idx = buf->idx;
	d->request_size = buf->total;
	d->virtual = buf_priv->virtual;

	return retcode;
}

static int i810_dma_cleanup(struct drm_device * dev)
{
	struct drm_device_dma *dma = dev->dma;

	/* Make sure interrupts are disabled here because the uninstall ioctl
	 * may not have been called from userspace and after dev_private
	 * is freed, it's too late.
	 */
	if (drm_core_check_feature(dev, DRIVER_HAVE_IRQ) && dev->irq_enabled)
		drm_irq_uninstall(dev);

	if (dev->dev_private) {
		int i;
		drm_i810_private_t *dev_priv =
		    (drm_i810_private_t *) dev->dev_private;

		if (dev_priv->ring.virtual_start) {
			drm_core_ioremapfree(&dev_priv->ring.map, dev);
		}
		if (dev_priv->hw_status_page) {
			pci_free_consistent(dev->pdev, PAGE_SIZE,
					    dev_priv->hw_status_page,
					    dev_priv->dma_status_page);
			/* Need to rewrite hardware status page */
			I810_WRITE(0x02080, 0x1ffff000);
		}
		drm_free(dev->dev_private, sizeof(drm_i810_private_t),
			 DRM_MEM_DRIVER);
		dev->dev_private = NULL;

		for (i = 0; i < dma->buf_count; i++) {
			struct drm_buf *buf = dma->buflist[i];
			drm_i810_buf_priv_t *buf_priv = buf->dev_private;

			if (buf_priv->kernel_virtual && buf->total)
				drm_core_ioremapfree(&buf_priv->map, dev);
		}
	}
	return 0;
}

static int i810_wait_ring(struct drm_device * dev, int n)
{
	drm_i810_private_t *dev_priv = dev->dev_private;
	drm_i810_ring_buffer_t *ring = &(dev_priv->ring);
	int iters = 0;
	unsigned long end;
	unsigned int last_head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;

	end = jiffies + (HZ * 3);
	while (ring->space < n) {
		ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
		ring->space = ring->head - (ring->tail + 8);
		if (ring->space < 0)
			ring->space += ring->Size;

		if (ring->head != last_head) {
			end = jiffies + (HZ * 3);
			last_head = ring->head;
		}

		iters++;
		if (time_before(end, jiffies)) {
			DRM_ERROR("space: %d wanted %d\n", ring->space, n);
			DRM_ERROR("lockup\n");
			goto out_wait_ring;
		}
		udelay(1);
	}

      out_wait_ring:
	return iters;
}

static void i810_kernel_lost_context(struct drm_device * dev)
{
	drm_i810_private_t *dev_priv = dev->dev_private;
	drm_i810_ring_buffer_t *ring = &(dev_priv->ring);

	ring->head = I810_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
	ring->tail = I810_READ(LP_RING + RING_TAIL);
	ring->space = ring->head - (ring->tail + 8);
	if (ring->space < 0)
		ring->space += ring->Size;
}

static int i810_freelist_init(struct drm_device * dev, drm_i810_private_t * dev_priv)
{
	struct drm_device_dma *dma = dev->dma;
	int my_idx = 24;
	u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
	int i;

	if (dma->buf_count > 1019) {
		/* Not enough space in the status page for the freelist */
		return -EINVAL;
	}

	for (i = 0; i < dma->buf_count; i++) {
		struct drm_buf *buf = dma->buflist[i];
		drm_i810_buf_priv_t *buf_priv = buf->dev_private;

		buf_priv->in_use = hw_status++;
		buf_priv->my_use_idx = my_idx;
		my_idx += 4;

		*buf_priv->in_use = I810_BUF_FREE;

		buf_priv->map.offset = buf->bus_address;
		buf_priv->map.size = buf->total;
		buf_priv->map.type = _DRM_AGP;
		buf_priv->map.flags = 0;
		buf_priv->map.mtrr = 0;

		drm_core_ioremap(&buf_priv->map, dev);
		buf_priv->kernel_virtual = buf_priv->map.handle;

	}
	return 0;
}

static int i810_dma_initialize(struct drm_device * dev,
			       drm_i810_private_t * dev_priv,
			       drm_i810_init_t * init)
{
	struct drm_map_list *r_list;
	memset(dev_priv, 0, sizeof(drm_i810_private_t));

	list_for_each_entry(r_list, &dev->maplist, head) {
		if (r_list->map &&
		    r_list->map->type == _DRM_SHM &&
		    r_list->map->flags & _DRM_CONTAINS_LOCK) {
			dev_priv->sarea_map = r_list->map;
			break;
		}
	}
	if (!dev_priv->sarea_map) {
		dev->dev_private = (void *)dev_priv;
		i810_dma_cleanup(dev);
		DRM_ERROR("can not find sarea!\n");
		return -EINVAL;
	}
	dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
	if (!dev_priv->mmio_map) {
		dev->dev_private = (void *)dev_priv;
		i810_dma_cleanup(dev);
		DRM_ERROR("can not find mmio map!\n");
		return -EINVAL;
	}
	dev->agp_buffer_token = init->buffers_offset;
	dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
	if (!dev->agp_buffer_map) {
		dev->dev_private = (void *)dev_priv;
		i810_dma_cleanup(dev);
		DRM_ERROR("can not find dma buffer map!\n");
		return -EINVAL;
	}

	dev_priv->sarea_priv = (drm_i810_sarea_t *)
	    ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);

	dev_priv->ring.Start = init->ring_start;
	dev_priv->ring.End = init->ring_end;
	dev_priv->ring.Size = init->ring_size;

	dev_priv->ring.map.offset = dev->agp->base + init->ring_start;
	dev_priv->ring.map.size = init->ring_size;
	dev_priv->ring.map.type = _DRM_AGP;
	dev_priv->ring.map.flags = 0;
	dev_priv->ring.map.mtrr = 0;

	drm_core_ioremap(&dev_priv->ring.map, dev);

	if (dev_priv->ring.map.handle == NULL) {
		dev->dev_private = (void *)dev_priv;
		i810_dma_cleanup(dev);
		DRM_ERROR("can not ioremap virtual address for"
			  " ring buffer\n");
		return -ENOMEM;
	}

	dev_priv->ring.virtual_start = dev_priv->ring.map.handle;

	dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;

	dev_priv->w = init->w;
	dev_priv->h = init->h;
	dev_priv->pitch = init->pitch;
	dev_priv->back_offset = init->back_offset;
	dev_priv->depth_offset = init->depth_offset;
	dev_priv->front_offset = init->front_offset;

	dev_priv->overlay_offset = init->overlay_offset;
	dev_priv->overlay_physical = init->overlay_physical;

	dev_priv->front_di1 = init->front_offset | init->pitch_bits;
	dev_priv->back_di1 = init->back_offset | init->pitch_bits;
	dev_priv->zi1 = init->depth_offset | init->pitch_bits;

	/* Program Hardware Status Page */
	dev_priv->hw_status_page =
	    pci_alloc_consistent(dev->pdev, PAGE_SIZE,
				 &dev_priv->dma_status_page);
	if (!dev_priv->hw_status_page) {
		dev->dev_private = (void *)dev_priv;
		i810_dma_cleanup(dev);
		DRM_ERROR("Can not allocate hardware status page\n");
		return -ENOMEM;
	}
	memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
	DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);

	I810_WRITE(0x02080, dev_priv->dma_status_page);
	DRM_DEBUG("Enabled hardware status page\n");

	/* Now we need to init our freelist */
	if (i810_freelist_init(dev, dev_priv) != 0) {
		dev->dev_private = (void *)dev_priv;
		i810_dma_cleanup(dev);
		DRM_ERROR("Not enough space in the status page for"
			  " the freelist\n");
		return -ENOMEM;
	}
	dev->dev_private = (void *)dev_priv;

	return 0;
}

static int i810_dma_init(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	drm_i810_private_t *dev_priv;
	drm_i810_init_t *init = data;
	int retcode = 0;

	switch (init->func) {
	case I810_INIT_DMA_1_4:
		DRM_INFO("Using v1.4 init.\n");
		dev_priv = drm_alloc(sizeof(drm_i810_private_t),
				     DRM_MEM_DRIVER);
		if (dev_priv == NULL)
			return -ENOMEM;
		retcode = i810_dma_initialize(dev, dev_priv, init);
		break;

	case I810_CLEANUP_DMA:
		DRM_INFO("DMA Cleanup\n");
		retcode = i810_dma_cleanup(dev);
		break;
	default:
		return -EINVAL;
	}

	return retcode;
}

/* Most efficient way to verify state for the i810 is as it is
 * emitted.  Non-conformant state is silently dropped.
 *
 * Use 'volatile' & local var tmp to force the emitted values to be
 * identical to the verified ones.
 */
static void i810EmitContextVerified(struct drm_device * dev,
				    volatile unsigned int *code)
{
	drm_i810_private_t *dev_priv = dev->dev_private;
	int i, j = 0;
	unsigned int tmp;
	RING_LOCALS;

	BEGIN_LP_RING(I810_CTX_SETUP_SIZE);

	OUT_RING(GFX_OP_COLOR_FACTOR);
	OUT_RING(code[I810_CTXREG_CF1]);

	OUT_RING(GFX_OP_STIPPLE);
	OUT_RING(code[I810_CTXREG_ST1]);

	for (i = 4; i < I810_CTX_SETUP_SIZE; i++) {
		tmp = code[i];

		if ((tmp & (7 << 29)) == (3 << 29) &&
		    (tmp & (0x1f << 24)) < (0x1d << 24)) {
			OUT_RING(tmp);
			j++;
		} else
			printk("constext state dropped!!!\n");
	}

	if (j & 1)
		OUT_RING(0);

	ADVANCE_LP_RING();
}

static void i810EmitTexVerified(struct drm_device * dev, volatile unsigned int *code)
{
	drm_i810_private_t *dev_priv = dev->dev_private;
	int i, j = 0;
	unsigned int tmp;
	RING_LOCALS;

	BEGIN_LP_RING(I810_TEX_SETUP_SIZE);

	OUT_RING(GFX_OP_MAP_INFO);
	OUT_RING(code[I810_TEXREG_MI1]);
	OUT_RING(code[I810_TEXREG_MI2]);
	OUT_RING(code[I810_TEXREG_MI3]);

	for (i = 4; i < I810_TEX_SETUP_SIZE; i++) {
		tmp = code[i];

		if ((tmp & (7 << 29)) == (3 << 29) &&
		    (tmp & (0x1f << 24)) < (0x1d << 24)) {
			OUT_RING(tmp);
			j++;
		} else
			printk("texture state dropped!!!\n");
	}

	if (j & 1)
		OUT_RING(0);

	ADVANCE_LP_RING();
}

/* Need to do some additional checking when setting the dest buffer.
 */
static void i810EmitDestVerified(struct drm_device * dev,
				 volatile unsigned int *code)
{
	drm_i810_private_t *dev_priv = dev->dev_private;
	unsigned int tmp;
	RING_LOCALS;

	BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);

	tmp = code[I810_DESTREG_DI1];
	if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
		OUT_RING(CMD_OP_DESTBUFFER_INFO);
		OUT_RING(tmp);
	} else
		DRM_DEBUG("bad di1 %x (allow %x or %x)\n",
			  tmp, dev_priv->front_di1, dev_priv->back_di1);

	/* invarient:
	 */
	OUT_RING(CMD_OP_Z_BUFFER_INFO);
	OUT_RING(dev_priv->zi1);

	OUT_RING(GFX_OP_DESTBUFFER_VARS);
	OUT_RING(code[I810_DESTREG_DV1]);

	OUT_RING(GFX_OP_DRAWRECT_INFO);
	OUT_RING(code[I810_DESTREG_DR1]);
	OUT_RING(code[I810_DESTREG_DR2]);
	OUT_RING(code[I810_DESTREG_DR3]);
	OUT_RING(code[I810_DESTREG_DR4]);
	OUT_RING(0);

	ADVANCE_LP_RING();
}

static void i810EmitState(struct drm_device * dev)
{
	drm_i810_private_t *dev_priv = dev->dev_private;
	drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
	unsigned int dirty = sarea_priv->dirty;

	DRM_DEBUG("%s %x\n", __FUNCTION__, dirty);

	if (dirty & I810_UPLOAD_BUFFERS) {
		i810EmitDestVerified(dev, sarea_priv->BufferState);
		sarea_priv->dirty &= ~I810_UPLOAD_BUFFERS;
	}

	if (dirty & I810_UPLOAD_CTX) {
		i810EmitContextVerified(dev, sarea_priv->ContextState);
		sarea_priv->dirty &= ~I810_UPLOAD_CTX;
	}

	if (dirty & I810_UPLOAD_TEX0) {
		i810EmitTexVerified(dev, sarea_priv->TexState[0]);
		sarea_priv->dirty &= ~I810_UPLOAD_TEX0;
	}

	if (dirty & I810_UPLOAD_TEX1) {
		i810EmitTexVerified(dev, sarea_priv->TexState[1]);
		sarea_priv->dirty &= ~I810_UPLOAD_TEX1;
	}
}

/* need to verify
 */
static void i810_dma_dispatch_clear(struct drm_device * dev, int flags,
				    unsigned int clear_color,
				    unsigned int clear_zval)
{
	drm_i810_private_t *dev_priv = dev->dev_private;
	drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
	int nbox = sarea_priv->nbox;
	struct drm_clip_rect *pbox = sarea_priv->boxes;
	int pitch = dev_priv->pitch;
	int cpp = 2;
	int i;
	RING_LOCALS;

	if (dev_priv->current_page == 1) {
		unsigned int tmp = flags;

		flags &= ~(I810_FRONT | I810_BACK);
		if (tmp & I810_FRONT)
			flags |= I810_BACK;
		if (tmp & I810_BACK)
			flags |= I810_FRONT;
	}

	i810_kernel_lost_context(dev);

	if (nbox > I810_NR_SAREA_CLIPRECTS)
		nbox = I810_NR_SAREA_CLIPRECTS;

	for (i = 0; i < nbox; i++, pbox++) {
		unsigned int x = pbox->x1;
		unsigned int y = pbox->y1;
		unsigned int width = (pbox->x2 - x) * cpp;
		unsigned int height = pbox->y2 - y;
		unsigned int start = y * pitch + x * cpp;

		if (pbox->x1 > pbox->x2 ||
		    pbox->y1 > pbox->y2 ||
		    pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
			continue;

		if (flags & I810_FRONT) {
			BEGIN_LP_RING(6);
			OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
			OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
			OUT_RING((height << 16) | width);
			OUT_RING(start);
			OUT_RING(clear_color);
			OUT_RING(0);
			ADVANCE_LP_RING();
		}

		if (flags & I810_BACK) {
			BEGIN_LP_RING(6);
			OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
			OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
			OUT_RING((height << 16) | width);
			OUT_RING(dev_priv->back_offset + start);
			OUT_RING(clear_color);
			OUT_RING(0);
			ADVANCE_LP_RING();
		}

		if (flags & I810_DEPTH) {
			BEGIN_LP_RING(6);
			OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_COLOR_BLT | 0x3);
			OUT_RING(BR13_SOLID_PATTERN | (0xF0 << 16) | pitch);
			OUT_RING((height << 16) | width);
			OUT_RING(dev_priv->depth_offset + start);
			OUT_RING(clear_zval);
			OUT_RING(0);
			ADVANCE_LP_RING();
		}
	}
}

static void i810_dma_dispatch_swap(struct drm_device * dev)
{
	drm_i810_private_t *dev_priv = dev->dev_private;
	drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
	int nbox = sarea_priv->nbox;
	struct drm_clip_rect *pbox = sarea_priv->boxes;
	int pitch = dev_priv->pitch;
	int cpp = 2;
	int i;
	RING_LOCALS;

	DRM_DEBUG("swapbuffers\n");

	i810_kernel_lost_context(dev);

	if (nbox > I810_NR_SAREA_CLIPRECTS)
		nbox = I810_NR_SAREA_CLIPRECTS;

	for (i = 0; i < nbox; i++, pbox++) {
		unsigned int w = pbox->x2 - pbox->x1;
		unsigned int h = pbox->y2 - pbox->y1;
		unsigned int dst = pbox->x1 * cpp + pbox->y1 * pitch;
		unsigned int start = dst;

		if (pbox->x1 > pbox->x2 ||
		    pbox->y1 > pbox->y2 ||
		    pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
			continue;

		BEGIN_LP_RING(6);
		OUT_RING(BR00_BITBLT_CLIENT | BR00_OP_SRC_COPY_BLT | 0x4);
		OUT_RING(pitch | (0xCC << 16));
		OUT_RING((h << 16) | (w * cpp));
		if (dev_priv->current_page == 0)
			OUT_RING(dev_priv->front_offset + start);
		else
			OUT_RING(dev_priv->back_offset + start);
		OUT_RING(pitch);
		if (dev_priv->current_page == 0)
			OUT_RING(dev_priv->back_offset + start);
		else
			OUT_RING(dev_priv->front_offset + start);
		ADVANCE_LP_RING();
	}
}

static void i810_dma_dispatch_vertex(struct drm_device * dev,
				     struct drm_buf * buf, int discard, int used)
{
	drm_i810_private_t *dev_priv = dev->dev_private;
	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
	drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
	struct drm_clip_rect *box = sarea_priv->boxes;
	int nbox = sarea_priv->nbox;
	unsigned long address = (unsigned long)buf->bus_address;
	unsigned long start = address - dev->agp->base;
	int i = 0;
	RING_LOCALS;

	i810_kernel_lost_context(dev);

	if (nbox > I810_NR_SAREA_CLIPRECTS)
		nbox = I810_NR_SAREA_CLIPRECTS;

	if (used > 4 * 1024)
		used = 0;

	if (sarea_priv->dirty)
		i810EmitState(dev);

	if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
		unsigned int prim = (sarea_priv->vertex_prim & PR_MASK);

		*(u32 *) buf_priv->kernel_virtual =
		    ((GFX_OP_PRIMITIVE | prim | ((used / 4) - 2)));

		if (used & 4) {
			*(u32 *) ((char *) buf_priv->kernel_virtual + used) = 0;
			used += 4;
		}

		i810_unmap_buffer(buf);
	}

	if (used) {
		do {
			if (i < nbox) {
				BEGIN_LP_RING(4);
				OUT_RING(GFX_OP_SCISSOR | SC_UPDATE_SCISSOR |
					 SC_ENABLE);
				OUT_RING(GFX_OP_SCISSOR_INFO);
				OUT_RING(box[i].x1 | (box[i].y1 << 16));
				OUT_RING((box[i].x2 -
					  1) | ((box[i].y2 - 1) << 16));
				ADVANCE_LP_RING();
			}

			BEGIN_LP_RING(4);
			OUT_RING(CMD_OP_BATCH_BUFFER);
			OUT_RING(start | BB1_PROTECTED);
			OUT_RING(start + used - 4);
			OUT_RING(0);
			ADVANCE_LP_RING();

		} while (++i < nbox);
	}

	if (discard) {
		dev_priv->counter++;

		(void)cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
			      I810_BUF_HARDWARE);

		BEGIN_LP_RING(8);
		OUT_RING(CMD_STORE_DWORD_IDX);
		OUT_RING(20);
		OUT_RING(dev_priv->counter);
		OUT_RING(CMD_STORE_DWORD_IDX);
		OUT_RING(buf_priv->my_use_idx);
		OUT_RING(I810_BUF_FREE);
		OUT_RING(CMD_REPORT_HEAD);
		OUT_RING(0);
		ADVANCE_LP_RING();
	}
}

static void i810_dma_dispatch_flip(struct drm_device * dev)
{
	drm_i810_private_t *dev_priv = dev->dev_private;
	int pitch = dev_priv->pitch;
	RING_LOCALS;

	DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
		  __FUNCTION__,
		  dev_priv->current_page,
		  dev_priv->sarea_priv->pf_current_page);

	i810_kernel_lost_context(dev);

	BEGIN_LP_RING(2);
	OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
	OUT_RING(0);
	ADVANCE_LP_RING();

	BEGIN_LP_RING(I810_DEST_SETUP_SIZE + 2);
	/* On i815 at least ASYNC is buggy */
	/* pitch<<5 is from 11.2.8 p158,
	   its the pitch / 8 then left shifted 8,
	   so (pitch >> 3) << 8 */
	OUT_RING(CMD_OP_FRONTBUFFER_INFO | (pitch << 5) /*| ASYNC_FLIP */ );
	if (dev_priv->current_page == 0) {
		OUT_RING(dev_priv->back_offset);
		dev_priv->current_page = 1;
	} else {
		OUT_RING(dev_priv->front_offset);
		dev_priv->current_page = 0;
	}
	OUT_RING(0);
	ADVANCE_LP_RING();

	BEGIN_LP_RING(2);
	OUT_RING(CMD_OP_WAIT_FOR_EVENT | WAIT_FOR_PLANE_A_FLIP);
	OUT_RING(0);
	ADVANCE_LP_RING();

	/* Increment the frame counter.  The client-side 3D driver must
	 * throttle the framerate by waiting for this value before
	 * performing the swapbuffer ioctl.
	 */
	dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;

}

static void i810_dma_quiescent(struct drm_device * dev)
{
	drm_i810_private_t *dev_priv = dev->dev_private;
	RING_LOCALS;

/*  	printk("%s\n", __FUNCTION__); */

	i810_kernel_lost_context(dev);

	BEGIN_LP_RING(4);
	OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
	OUT_RING(CMD_REPORT_HEAD);
	OUT_RING(0);
	OUT_RING(0);
	ADVANCE_LP_RING();

	i810_wait_ring(dev, dev_priv->ring.Size - 8);
}

static int i810_flush_queue(struct drm_device * dev)
{
	drm_i810_private_t *dev_priv = dev->dev_private;
	struct drm_device_dma *dma = dev->dma;
	int i, ret = 0;
	RING_LOCALS;

/*  	printk("%s\n", __FUNCTION__); */

	i810_kernel_lost_context(dev);

	BEGIN_LP_RING(2);
	OUT_RING(CMD_REPORT_HEAD);
	OUT_RING(0);
	ADVANCE_LP_RING();

	i810_wait_ring(dev, dev_priv->ring.Size - 8);

	for (i = 0; i < dma->buf_count; i++) {
		struct drm_buf *buf = dma->buflist[i];
		drm_i810_buf_priv_t *buf_priv = buf->dev_private;

		int used = cmpxchg(buf_priv->in_use, I810_BUF_HARDWARE,
				   I810_BUF_FREE);

		if (used == I810_BUF_HARDWARE)
			DRM_DEBUG("reclaimed from HARDWARE\n");
		if (used == I810_BUF_CLIENT)
			DRM_DEBUG("still on client\n");
	}

	return ret;
}

/* Must be called with the lock held */
static void i810_reclaim_buffers(struct drm_device * dev,
				 struct drm_file *file_priv)
{
	struct drm_device_dma *dma = dev->dma;
	int i;

	if (!dma)
		return;
	if (!dev->dev_private)
		return;
	if (!dma->buflist)
		return;

	i810_flush_queue(dev);

	for (i = 0; i < dma->buf_count; i++) {
		struct drm_buf *buf = dma->buflist[i];
		drm_i810_buf_priv_t *buf_priv = buf->dev_private;

		if (buf->file_priv == file_priv && buf_priv) {
			int used = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT,
					   I810_BUF_FREE);

			if (used == I810_BUF_CLIENT)
				DRM_DEBUG("reclaimed from client\n");
			if (buf_priv->currently_mapped == I810_BUF_MAPPED)
				buf_priv->currently_mapped = I810_BUF_UNMAPPED;
		}
	}
}

static int i810_flush_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv)
{
	LOCK_TEST_WITH_RETURN(dev, file_priv);

	i810_flush_queue(dev);
	return 0;
}

static int i810_dma_vertex(struct drm_device *dev, void *data,
			   struct drm_file *file_priv)
{
	struct drm_device_dma *dma = dev->dma;
	drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
	u32 *hw_status = dev_priv->hw_status_page;
	drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
	    dev_priv->sarea_priv;
	drm_i810_vertex_t *vertex = data;

	LOCK_TEST_WITH_RETURN(dev, file_priv);

	DRM_DEBUG("i810 dma vertex, idx %d used %d discard %d\n",
		  vertex->idx, vertex->used, vertex->discard);

	if (vertex->idx < 0 || vertex->idx > dma->buf_count)
		return -EINVAL;

	i810_dma_dispatch_vertex(dev,
				 dma->buflist[vertex->idx],
				 vertex->discard, vertex->used);

	atomic_add(vertex->used, &dev->counts[_DRM_STAT_SECONDARY]);
	atomic_inc(&dev->counts[_DRM_STAT_DMA]);
	sarea_priv->last_enqueue = dev_priv->counter - 1;
	sarea_priv->last_dispatch = (int)hw_status[5];

	return 0;
}

static int i810_clear_bufs(struct drm_device *dev, void *data,
			   struct drm_file *file_priv)
{
	drm_i810_clear_t *clear = data;

	LOCK_TEST_WITH_RETURN(dev, file_priv);

	/* GH: Someone's doing nasty things... */
	if (!dev->dev_private) {
		return -EINVAL;
	}

	i810_dma_dispatch_clear(dev, clear->flags,
				clear->clear_color, clear->clear_depth);
	return 0;
}

static int i810_swap_bufs(struct drm_device *dev, void *data,
			  struct drm_file *file_priv)
{
	DRM_DEBUG("i810_swap_bufs\n");

	LOCK_TEST_WITH_RETURN(dev, file_priv);

	i810_dma_dispatch_swap(dev);
	return 0;
}

static int i810_getage(struct drm_device *dev, void *data,
		       struct drm_file *file_priv)
{
	drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
	u32 *hw_status = dev_priv->hw_status_page;
	drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
	    dev_priv->sarea_priv;

	sarea_priv->last_dispatch = (int)hw_status[5];
	return 0;
}

static int i810_getbuf(struct drm_device *dev, void *data,
		       struct drm_file *file_priv)
{
	int retcode = 0;
	drm_i810_dma_t *d = data;
	drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
	u32 *hw_status = dev_priv->hw_status_page;
	drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
	    dev_priv->sarea_priv;

	LOCK_TEST_WITH_RETURN(dev, file_priv);

	d->granted = 0;

	retcode = i810_dma_get_buffer(dev, d, file_priv);

	DRM_DEBUG("i810_dma: %d returning %d, granted = %d\n",
		  task_pid_nr(current), retcode, d->granted);

	sarea_priv->last_dispatch = (int)hw_status[5];

	return retcode;
}

static int i810_copybuf(struct drm_device *dev, void *data,
			struct drm_file *file_priv)
{
	/* Never copy - 2.4.x doesn't need it */
	return 0;
}

static int i810_docopy(struct drm_device *dev, void *data,
			struct drm_file *file_priv)
{
	/* Never copy - 2.4.x doesn't need it */
	return 0;
}

static void i810_dma_dispatch_mc(struct drm_device * dev, struct drm_buf * buf, int used,
				 unsigned int last_render)
{
	drm_i810_private_t *dev_priv = dev->dev_private;
	drm_i810_buf_priv_t *buf_priv = buf->dev_private;
	drm_i810_sarea_t *sarea_priv = dev_priv->sarea_priv;
	unsigned long address = (unsigned long)buf->bus_address;
	unsigned long start = address - dev->agp->base;
	int u;
	RING_LOCALS;

	i810_kernel_lost_context(dev);

	u = cmpxchg(buf_priv->in_use, I810_BUF_CLIENT, I810_BUF_HARDWARE);
	if (u != I810_BUF_CLIENT) {
		DRM_DEBUG("MC found buffer that isn't mine!\n");
	}

	if (used > 4 * 1024)
		used = 0;

	sarea_priv->dirty = 0x7f;

	DRM_DEBUG("dispatch mc addr 0x%lx, used 0x%x\n", address, used);

	dev_priv->counter++;
	DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
	DRM_DEBUG("i810_dma_dispatch_mc\n");
	DRM_DEBUG("start : %lx\n", start);
	DRM_DEBUG("used : %d\n", used);
	DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);

	if (buf_priv->currently_mapped == I810_BUF_MAPPED) {
		if (used & 4) {
			*(u32 *) ((char *) buf_priv->virtual + used) = 0;
			used += 4;
		}

		i810_unmap_buffer(buf);
	}
	BEGIN_LP_RING(4);
	OUT_RING(CMD_OP_BATCH_BUFFER);
	OUT_RING(start | BB1_PROTECTED);
	OUT_RING(start + used - 4);
	OUT_RING(0);
	ADVANCE_LP_RING();

	BEGIN_LP_RING(8);
	OUT_RING(CMD_STORE_DWORD_IDX);
	OUT_RING(buf_priv->my_use_idx);
	OUT_RING(I810_BUF_FREE);
	OUT_RING(0);

	OUT_RING(CMD_STORE_DWORD_IDX);
	OUT_RING(16);
	OUT_RING(last_render);
	OUT_RING(0);
	ADVANCE_LP_RING();
}

static int i810_dma_mc(struct drm_device *dev, void *data,
		       struct drm_file *file_priv)
{
	struct drm_device_dma *dma = dev->dma;
	drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
	u32 *hw_status = dev_priv->hw_status_page;
	drm_i810_sarea_t *sarea_priv = (drm_i810_sarea_t *)
	    dev_priv->sarea_priv;
	drm_i810_mc_t *mc = data;

	LOCK_TEST_WITH_RETURN(dev, file_priv);

	if (mc->idx >= dma->buf_count || mc->idx < 0)
		return -EINVAL;

	i810_dma_dispatch_mc(dev, dma->buflist[mc->idx], mc->used,
			     mc->last_render);

	atomic_add(mc->used, &dev->counts[_DRM_STAT_SECONDARY]);
	atomic_inc(&dev->counts[_DRM_STAT_DMA]);
	sarea_priv->last_enqueue = dev_priv->counter - 1;
	sarea_priv->last_dispatch = (int)hw_status[5];

	return 0;
}

static int i810_rstatus(struct drm_device *dev, void *data,
			struct drm_file *file_priv)
{
	drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;

	return (int)(((u32 *) (dev_priv->hw_status_page))[4]);
}

static int i810_ov0_info(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;
	drm_i810_overlay_t *ov = data;

	ov->offset = dev_priv->overlay_offset;
	ov->physical = dev_priv->overlay_physical;

	return 0;
}

static int i810_fstatus(struct drm_device *dev, void *data,
			struct drm_file *file_priv)
{
	drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;

	LOCK_TEST_WITH_RETURN(dev, file_priv);
	return I810_READ(0x30008);
}

static int i810_ov0_flip(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
{
	drm_i810_private_t *dev_priv = (drm_i810_private_t *) dev->dev_private;

	LOCK_TEST_WITH_RETURN(dev, file_priv);

	//Tell the overlay to update
	I810_WRITE(0x30000, dev_priv->overlay_physical | 0x80000000);

	return 0;
}

/* Not sure why this isn't set all the time:
 */
static void i810_do_init_pageflip(struct drm_device * dev)
{
	drm_i810_private_t *dev_priv = dev->dev_private;

	DRM_DEBUG("%s\n", __FUNCTION__);
	dev_priv->page_flipping = 1;
	dev_priv->current_page = 0;
	dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
}

static int i810_do_cleanup_pageflip(struct drm_device * dev)
{
	drm_i810_private_t *dev_priv = dev->dev_private;

	DRM_DEBUG("%s\n", __FUNCTION__);
	if (dev_priv->current_page != 0)
		i810_dma_dispatch_flip(dev);

	dev_priv->page_flipping = 0;
	return 0;
}

static int i810_flip_bufs(struct drm_device *dev, void *data,
			  struct drm_file *file_priv)
{
	drm_i810_private_t *dev_priv = dev->dev_private;

	DRM_DEBUG("%s\n", __FUNCTION__);

	LOCK_TEST_WITH_RETURN(dev, file_priv);

	if (!dev_priv->page_flipping)
		i810_do_init_pageflip(dev);

	i810_dma_dispatch_flip(dev);
	return 0;
}

int i810_driver_load(struct drm_device *dev, unsigned long flags)
{
	/* i810 has 4 more counters */
	dev->counters += 4;
	dev->types[6] = _DRM_STAT_IRQ;
	dev->types[7] = _DRM_STAT_PRIMARY;
	dev->types[8] = _DRM_STAT_SECONDARY;
	dev->types[9] = _DRM_STAT_DMA;

	return 0;
}

void i810_driver_lastclose(struct drm_device * dev)
{
	i810_dma_cleanup(dev);
}

void i810_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
{
	if (dev->dev_private) {
		drm_i810_private_t *dev_priv = dev->dev_private;
		if (dev_priv->page_flipping) {
			i810_do_cleanup_pageflip(dev);
		}
	}
}

void i810_driver_reclaim_buffers_locked(struct drm_device * dev,
					struct drm_file *file_priv)
{
	i810_reclaim_buffers(dev, file_priv);
}

int i810_driver_dma_quiescent(struct drm_device * dev)
{
	i810_dma_quiescent(dev);
	return 0;
}

struct drm_ioctl_desc i810_ioctls[] = {
	DRM_IOCTL_DEF(DRM_I810_INIT, i810_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF(DRM_I810_VERTEX, i810_dma_vertex, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_I810_CLEAR, i810_clear_bufs, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_I810_FLUSH, i810_flush_ioctl, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_I810_GETAGE, i810_getage, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_I810_GETBUF, i810_getbuf, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_I810_SWAP, i810_swap_bufs, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_I810_COPY, i810_copybuf, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_I810_DOCOPY, i810_docopy, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_I810_OV0INFO, i810_ov0_info, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_I810_FSTATUS, i810_fstatus, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_I810_OV0FLIP, i810_ov0_flip, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_I810_MC, i810_dma_mc, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF(DRM_I810_RSTATUS, i810_rstatus, DRM_AUTH),
	DRM_IOCTL_DEF(DRM_I810_FLIP, i810_flip_bufs, DRM_AUTH)
};

int i810_max_ioctl = DRM_ARRAY_SIZE(i810_ioctls);

/**
 * Determine if the device really is AGP or not.
 *
 * All Intel graphics chipsets are treated as AGP, even if they are really
 * PCI-e.
 *
 * \param dev   The device to be tested.
 *
 * \returns
 * A value of 1 is always retured to indictate every i810 is AGP.
 */
int i810_driver_device_is_agp(struct drm_device * dev)
{
	return 1;
}
n class="hl opt">(5); for (address = 0; address < LANAI_EEPROM_SIZE; address++) { data = (address << 1) | 1; /* Command=read + address */ /* send start bit */ data_l(); udelay(5); clock_l(); udelay(5); for (i = 128; i != 0; i >>= 1) { /* write command out */ tmp = (lanai->conf1 & ~CONFIG1_PROMDATA) | (data & i) ? CONFIG1_PROMDATA : 0; if (lanai->conf1 != tmp) { set_config1(tmp); udelay(5); /* Let new data settle */ } clock_h(); udelay(5); clock_l(); udelay(5); } /* look for ack */ data_h(); clock_h(); udelay(5); if (read_pin() != 0) goto error; /* No ack seen */ clock_l(); udelay(5); /* read back result */ for (data = 0, i = 7; i >= 0; i--) { data_h(); clock_h(); udelay(5); data = (data << 1) | !!read_pin(); clock_l(); udelay(5); } /* look again for ack */ data_h(); clock_h(); udelay(5); if (read_pin() == 0) goto error; /* Spurious ack */ clock_l(); udelay(5); send_stop(); lanai->eeprom[address] = data; DPRINTK("EEPROM 0x%04X %02X\n", (unsigned int) address, (unsigned int) data); } return 0; error: clock_l(); udelay(5); /* finish read */ send_stop(); printk(KERN_ERR DEV_LABEL "(itf %d): error reading EEPROM byte %d\n", lanai->number, address); return -EIO; #undef set_config1 #undef clock_h #undef clock_l #undef data_h #undef data_l #undef pre_read #undef read_pin #undef send_stop } /* read a big-endian 4-byte value out of eeprom */ static inline u32 eeprom_be4(const struct lanai_dev *lanai, int address) { return be32_to_cpup((const u32 *) &lanai->eeprom[address]); } /* Checksum/validate EEPROM contents */ static int __devinit eeprom_validate(struct lanai_dev *lanai) { int i, s; u32 v; const u8 *e = lanai->eeprom; #ifdef DEBUG /* First, see if we can get an ASCIIZ string out of the copyright */ for (i = EEPROM_COPYRIGHT; i < (EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN); i++) if (e[i] < 0x20 || e[i] > 0x7E) break; if ( i != EEPROM_COPYRIGHT && i != EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN && e[i] == '\0') DPRINTK("eeprom: copyright = \"%s\"\n", (char *) &e[EEPROM_COPYRIGHT]); else DPRINTK("eeprom: copyright not found\n"); #endif /* Validate checksum */ for (i = s = 0; i < EEPROM_CHECKSUM; i++) s += e[i]; s &= 0xFF; if (s != e[EEPROM_CHECKSUM]) { printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM checksum bad " "(wanted 0x%02X, got 0x%02X)\n", lanai->number, (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM]); return -EIO; } s ^= 0xFF; if (s != e[EEPROM_CHECKSUM_REV]) { printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM inverse checksum " "bad (wanted 0x%02X, got 0x%02X)\n", lanai->number, (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM_REV]); return -EIO; } /* Verify MAC address */ for (i = 0; i < 6; i++) if ((e[EEPROM_MAC + i] ^ e[EEPROM_MAC_REV + i]) != 0xFF) { printk(KERN_ERR DEV_LABEL "(itf %d) : EEPROM MAC addresses don't match " "(0x%02X, inverse 0x%02X)\n", lanai->number, (unsigned int) e[EEPROM_MAC + i], (unsigned int) e[EEPROM_MAC_REV + i]); return -EIO; } DPRINTK("eeprom: MAC address = %02X:%02X:%02X:%02X:%02X:%02X\n", e[EEPROM_MAC + 0], e[EEPROM_MAC + 1], e[EEPROM_MAC + 2], e[EEPROM_MAC + 3], e[EEPROM_MAC + 4], e[EEPROM_MAC + 5]); /* Verify serial number */ lanai->serialno = eeprom_be4(lanai, EEPROM_SERIAL); v = eeprom_be4(lanai, EEPROM_SERIAL_REV); if ((lanai->serialno ^ v) != 0xFFFFFFFF) { printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM serial numbers " "don't match (0x%08X, inverse 0x%08X)\n", lanai->number, (unsigned int) lanai->serialno, (unsigned int) v); return -EIO; } DPRINTK("eeprom: Serial number = %d\n", (unsigned int) lanai->serialno); /* Verify magic number */ lanai->magicno = eeprom_be4(lanai, EEPROM_MAGIC); v = eeprom_be4(lanai, EEPROM_MAGIC_REV); if ((lanai->magicno ^ v) != 0xFFFFFFFF) { printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM magic numbers " "don't match (0x%08X, inverse 0x%08X)\n", lanai->number, lanai->magicno, v); return -EIO; } DPRINTK("eeprom: Magic number = 0x%08X\n", lanai->magicno); if (lanai->magicno != EEPROM_MAGIC_VALUE) printk(KERN_WARNING DEV_LABEL "(itf %d): warning - EEPROM " "magic not what expected (got 0x%08X, not 0x%08X)\n", lanai->number, (unsigned int) lanai->magicno, (unsigned int) EEPROM_MAGIC_VALUE); return 0; } #endif /* READ_EEPROM */ static inline const u8 *eeprom_mac(const struct lanai_dev *lanai) { return &lanai->eeprom[EEPROM_MAC]; } /* -------------------- INTERRUPT HANDLING UTILITIES: */ /* Interrupt types */ #define INT_STATS (0x00000002) /* Statistics counter overflow */ #define INT_SOOL (0x00000004) /* SOOL changed state */ #define INT_LOCD (0x00000008) /* LOCD changed state */ #define INT_LED (0x00000010) /* LED (HAPPI) changed state */ #define INT_GPIN (0x00000020) /* GPIN changed state */ #define INT_PING (0x00000040) /* PING_COUNT fulfilled */ #define INT_WAKE (0x00000080) /* Lanai wants bus */ #define INT_CBR0 (0x00000100) /* CBR sched hit VCI 0 */ #define INT_LOCK (0x00000200) /* Service list overflow */ #define INT_MISMATCH (0x00000400) /* TX magic list mismatch */ #define INT_AAL0_STR (0x00000800) /* Non-AAL5 buffer half filled */ #define INT_AAL0 (0x00001000) /* Non-AAL5 data available */ #define INT_SERVICE (0x00002000) /* Service list entries available */ #define INT_TABORTSENT (0x00004000) /* Target abort sent by lanai */ #define INT_TABORTBM (0x00008000) /* Abort rcv'd as bus master */ #define INT_TIMEOUTBM (0x00010000) /* No response to bus master */ #define INT_PCIPARITY (0x00020000) /* Parity error on PCI */ /* Sets of the above */ #define INT_ALL (0x0003FFFE) /* All interrupts */ #define INT_STATUS (0x0000003C) /* Some status pin changed */ #define INT_DMASHUT (0x00038000) /* DMA engine got shut down */ #define INT_SEGSHUT (0x00000700) /* Segmentation got shut down */ static inline u32 intr_pending(const struct lanai_dev *lanai) { return reg_read(lanai, IntStatusMasked_Reg); } static inline void intr_enable(const struct lanai_dev *lanai, u32 i) { reg_write(lanai, i, IntControlEna_Reg); } static inline void intr_disable(const struct lanai_dev *lanai, u32 i) { reg_write(lanai, i, IntControlDis_Reg); } /* -------------------- CARD/PCI STATUS: */ static void status_message(int itf, const char *name, int status) { static const char *onoff[2] = { "off to on", "on to off" }; printk(KERN_INFO DEV_LABEL "(itf %d): %s changed from %s\n", itf, name, onoff[!status]); } static void lanai_check_status(struct lanai_dev *lanai) { u32 new = reg_read(lanai, Status_Reg); u32 changes = new ^ lanai->status; lanai->status = new; #define e(flag, name) \ if (changes & flag) \ status_message(lanai->number, name, new & flag) e(STATUS_SOOL, "SOOL"); e(STATUS_LOCD, "LOCD"); e(STATUS_LED, "LED"); e(STATUS_GPIN, "GPIN"); #undef e } static void pcistatus_got(int itf, const char *name) { printk(KERN_INFO DEV_LABEL "(itf %d): PCI got %s error\n", itf, name); } static void pcistatus_check(struct lanai_dev *lanai, int clearonly) { u16 s; int result; result = pci_read_config_word(lanai->pci, PCI_STATUS, &s); if (result != PCIBIOS_SUCCESSFUL) { printk(KERN_ERR DEV_LABEL "(itf %d): can't read PCI_STATUS: " "%d\n", lanai->number, result); return; } s &= PCI_STATUS_DETECTED_PARITY | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT | PCI_STATUS_PARITY; if (s == 0) return; result = pci_write_config_word(lanai->pci, PCI_STATUS, s); if (result != PCIBIOS_SUCCESSFUL) printk(KERN_ERR DEV_LABEL "(itf %d): can't write PCI_STATUS: " "%d\n", lanai->number, result); if (clearonly) return; #define e(flag, name, stat) \ if (s & flag) { \ pcistatus_got(lanai->number, name); \ ++lanai->stats.pcierr_##stat; \ } e(PCI_STATUS_DETECTED_PARITY, "parity", parity_detect); e(PCI_STATUS_SIG_SYSTEM_ERROR, "signalled system", serr_set); e(PCI_STATUS_REC_MASTER_ABORT, "master", master_abort); e(PCI_STATUS_REC_TARGET_ABORT, "master target", m_target_abort); e(PCI_STATUS_SIG_TARGET_ABORT, "slave", s_target_abort); e(PCI_STATUS_PARITY, "master parity", master_parity); #undef e } /* -------------------- VCC TX BUFFER UTILITIES: */ /* space left in tx buffer in bytes */ static inline int vcc_tx_space(const struct lanai_vcc *lvcc, int endptr) { int r; r = endptr * 16; r -= ((unsigned long) lvcc->tx.buf.ptr) - ((unsigned long) lvcc->tx.buf.start); r -= 16; /* Leave "bubble" - if start==end it looks empty */ if (r < 0) r += lanai_buf_size(&lvcc->tx.buf); return r; } /* test if VCC is currently backlogged */ static inline int vcc_is_backlogged(const struct lanai_vcc *lvcc) { return !skb_queue_empty(&lvcc->tx.backlog); } /* Bit fields in the segmentation buffer descriptor */ #define DESCRIPTOR_MAGIC (0xD0000000) #define DESCRIPTOR_AAL5 (0x00008000) #define DESCRIPTOR_AAL5_STREAM (0x00004000) #define DESCRIPTOR_CLP (0x00002000) /* Add 32-bit descriptor with its padding */ static inline void vcc_tx_add_aal5_descriptor(struct lanai_vcc *lvcc, u32 flags, int len) { int pos; APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 0, "vcc_tx_add_aal5_descriptor: bad ptr=%p\n", lvcc->tx.buf.ptr); lvcc->tx.buf.ptr += 4; /* Hope the values REALLY don't matter */ pos = ((unsigned char *) lvcc->tx.buf.ptr) - (unsigned char *) lvcc->tx.buf.start; APRINTK((pos & ~0x0001FFF0) == 0, "vcc_tx_add_aal5_descriptor: bad pos (%d) before, vci=%d, " "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci, lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end); pos = (pos + len) & (lanai_buf_size(&lvcc->tx.buf) - 1); APRINTK((pos & ~0x0001FFF0) == 0, "vcc_tx_add_aal5_descriptor: bad pos (%d) after, vci=%d, " "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci, lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end); lvcc->tx.buf.ptr[-1] = cpu_to_le32(DESCRIPTOR_MAGIC | DESCRIPTOR_AAL5 | ((lvcc->tx.atmvcc->atm_options & ATM_ATMOPT_CLP) ? DESCRIPTOR_CLP : 0) | flags | pos >> 4); if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end) lvcc->tx.buf.ptr = lvcc->tx.buf.start; } /* Add 32-bit AAL5 trailer and leave room for its CRC */ static inline void vcc_tx_add_aal5_trailer(struct lanai_vcc *lvcc, int len, int cpi, int uu) { APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 8, "vcc_tx_add_aal5_trailer: bad ptr=%p\n", lvcc->tx.buf.ptr); lvcc->tx.buf.ptr += 2; lvcc->tx.buf.ptr[-2] = cpu_to_be32((uu << 24) | (cpi << 16) | len); if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end) lvcc->tx.buf.ptr = lvcc->tx.buf.start; } static inline void vcc_tx_memcpy(struct lanai_vcc *lvcc, const unsigned char *src, int n) { unsigned char *e; int m; e = ((unsigned char *) lvcc->tx.buf.ptr) + n; m = e - (unsigned char *) lvcc->tx.buf.end; if (m < 0) m = 0; memcpy(lvcc->tx.buf.ptr, src, n - m); if (m != 0) { memcpy(lvcc->tx.buf.start, src + n - m, m); e = ((unsigned char *) lvcc->tx.buf.start) + m; } lvcc->tx.buf.ptr = (u32 *) e; } static inline void vcc_tx_memzero(struct lanai_vcc *lvcc, int n) { unsigned char *e; int m; if (n == 0) return; e = ((unsigned char *) lvcc->tx.buf.ptr) + n; m = e - (unsigned char *) lvcc->tx.buf.end; if (m < 0) m = 0; memset(lvcc->tx.buf.ptr, 0, n - m); if (m != 0) { memset(lvcc->tx.buf.start, 0, m); e = ((unsigned char *) lvcc->tx.buf.start) + m; } lvcc->tx.buf.ptr = (u32 *) e; } /* Update "butt" register to specify new WritePtr */ static inline void lanai_endtx(struct lanai_dev *lanai, const struct lanai_vcc *lvcc) { int i, ptr = ((unsigned char *) lvcc->tx.buf.ptr) - (unsigned char *) lvcc->tx.buf.start; APRINTK((ptr & ~0x0001FFF0) == 0, "lanai_endtx: bad ptr (%d), vci=%d, start,ptr,end=%p,%p,%p\n", ptr, lvcc->vci, lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end); /* * Since the "butt register" is a shared resounce on the card we * serialize all accesses to it through this spinlock. This is * mostly just paranoia sicne the register is rarely "busy" anyway * but is needed for correctness. */ spin_lock(&lanai->endtxlock); /* * We need to check if the "butt busy" bit is set before * updating the butt register. In theory this should * never happen because the ATM card is plenty fast at * updating the register. Still, we should make sure */ for (i = 0; reg_read(lanai, Status_Reg) & STATUS_BUTTBUSY; i++) { if (unlikely(i > 50)) { printk(KERN_ERR DEV_LABEL "(itf %d): butt register " "always busy!\n", lanai->number); break; } udelay(5); } /* * Before we tall the card to start work we need to be sure 100% of * the info in the service buffer has been written before we tell * the card about it */ wmb(); reg_write(lanai, (ptr << 12) | lvcc->vci, Butt_Reg); spin_unlock(&lanai->endtxlock); } /* * Add one AAL5 PDU to lvcc's transmit buffer. Caller garauntees there's * space available. "pdusize" is the number of bytes the PDU will take */ static void lanai_send_one_aal5(struct lanai_dev *lanai, struct lanai_vcc *lvcc, struct sk_buff *skb, int pdusize) { int pad; APRINTK(pdusize == aal5_size(skb->len), "lanai_send_one_aal5: wrong size packet (%d != %d)\n", pdusize, aal5_size(skb->len)); vcc_tx_add_aal5_descriptor(lvcc, 0, pdusize); pad = pdusize - skb->len - 8; APRINTK(pad >= 0, "pad is negative (%d)\n", pad); APRINTK(pad < 48, "pad is too big (%d)\n", pad); vcc_tx_memcpy(lvcc, skb->data, skb->len); vcc_tx_memzero(lvcc, pad); vcc_tx_add_aal5_trailer(lvcc, skb->len, 0, 0); lanai_endtx(lanai, lvcc); lanai_free_skb(lvcc->tx.atmvcc, skb); atomic_inc(&lvcc->tx.atmvcc->stats->tx); } /* Try to fill the buffer - don't call unless there is backlog */ static void vcc_tx_unqueue_aal5(struct lanai_dev *lanai, struct lanai_vcc *lvcc, int endptr) { int n; struct sk_buff *skb; int space = vcc_tx_space(lvcc, endptr); APRINTK(vcc_is_backlogged(lvcc), "vcc_tx_unqueue() called with empty backlog (vci=%d)\n", lvcc->vci); while (space >= 64) { skb = skb_dequeue(&lvcc->tx.backlog); if (skb == NULL) goto no_backlog; n = aal5_size(skb->len); if (n + 16 > space) { /* No room for this packet - put it back on queue */ skb_queue_head(&lvcc->tx.backlog, skb); return; } lanai_send_one_aal5(lanai, lvcc, skb, n); space -= n + 16; } if (!vcc_is_backlogged(lvcc)) { no_backlog: __clear_bit(lvcc->vci, lanai->backlog_vccs); } } /* Given an skb that we want to transmit either send it now or queue */ static void vcc_tx_aal5(struct lanai_dev *lanai, struct lanai_vcc *lvcc, struct sk_buff *skb) { int space, n; if (vcc_is_backlogged(lvcc)) /* Already backlogged */ goto queue_it; space = vcc_tx_space(lvcc, TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr))); n = aal5_size(skb->len); APRINTK(n + 16 >= 64, "vcc_tx_aal5: n too small (%d)\n", n); if (space < n + 16) { /* No space for this PDU */ __set_bit(lvcc->vci, lanai->backlog_vccs); queue_it: skb_queue_tail(&lvcc->tx.backlog, skb); return; } lanai_send_one_aal5(lanai, lvcc, skb, n); } static void vcc_tx_unqueue_aal0(struct lanai_dev *lanai, struct lanai_vcc *lvcc, int endptr) { printk(KERN_INFO DEV_LABEL ": vcc_tx_unqueue_aal0: not implemented\n"); } static void vcc_tx_aal0(struct lanai_dev *lanai, struct lanai_vcc *lvcc, struct sk_buff *skb) { printk(KERN_INFO DEV_LABEL ": vcc_tx_aal0: not implemented\n"); /* Remember to increment lvcc->tx.atmvcc->stats->tx */ lanai_free_skb(lvcc->tx.atmvcc, skb); } /* -------------------- VCC RX BUFFER UTILITIES: */ /* unlike the _tx_ cousins, this doesn't update ptr */ static inline void vcc_rx_memcpy(unsigned char *dest, const struct lanai_vcc *lvcc, int n) { int m = ((const unsigned char *) lvcc->rx.buf.ptr) + n - ((const unsigned char *) (lvcc->rx.buf.end)); if (m < 0) m = 0; memcpy(dest, lvcc->rx.buf.ptr, n - m); memcpy(dest + n - m, lvcc->rx.buf.start, m); /* Make sure that these copies don't get reordered */ barrier(); } /* Receive AAL5 data on a VCC with a particular endptr */ static void vcc_rx_aal5(struct lanai_vcc *lvcc, int endptr) { int size; struct sk_buff *skb; const u32 *x; u32 *end = &lvcc->rx.buf.start[endptr * 4]; int n = ((unsigned long) end) - ((unsigned long) lvcc->rx.buf.ptr); if (n < 0) n += lanai_buf_size(&lvcc->rx.buf); APRINTK(n >= 0 && n < lanai_buf_size(&lvcc->rx.buf) && !(n & 15), "vcc_rx_aal5: n out of range (%d/%Zu)\n", n, lanai_buf_size(&lvcc->rx.buf)); /* Recover the second-to-last word to get true pdu length */ if ((x = &end[-2]) < lvcc->rx.buf.start) x = &lvcc->rx.buf.end[-2]; /* * Before we actually read from the buffer, make sure the memory * changes have arrived */ rmb(); size = be32_to_cpup(x) & 0xffff; if (unlikely(n != aal5_size(size))) { /* Make sure size matches padding */ printk(KERN_INFO DEV_LABEL "(itf %d): Got bad AAL5 length " "on vci=%d - size=%d n=%d\n", lvcc->rx.atmvcc->dev->number, lvcc->vci, size, n); lvcc->stats.x.aal5.rx_badlen++; goto out; } skb = atm_alloc_charge(lvcc->rx.atmvcc, size, GFP_ATOMIC); if (unlikely(skb == NULL)) { lvcc->stats.rx_nomem++; goto out; } skb_put(skb, size); vcc_rx_memcpy(skb->data, lvcc, size); ATM_SKB(skb)->vcc = lvcc->rx.atmvcc; __net_timestamp(skb); lvcc->rx.atmvcc->push(lvcc->rx.atmvcc, skb); atomic_inc(&lvcc->rx.atmvcc->stats->rx); out: lvcc->rx.buf.ptr = end; cardvcc_write(lvcc, endptr, vcc_rxreadptr); } static void vcc_rx_aal0(struct lanai_dev *lanai) { printk(KERN_INFO DEV_LABEL ": vcc_rx_aal0: not implemented\n"); /* Remember to get read_lock(&vcc_sklist_lock) while looking up VC */ /* Remember to increment lvcc->rx.atmvcc->stats->rx */ } /* -------------------- MANAGING HOST-BASED VCC TABLE: */ /* Decide whether to use vmalloc or get_zeroed_page for VCC table */ #if (NUM_VCI * BITS_PER_LONG) <= PAGE_SIZE #define VCCTABLE_GETFREEPAGE #else #include <linux/vmalloc.h> #endif static int __devinit vcc_table_allocate(struct lanai_dev *lanai) { #ifdef VCCTABLE_GETFREEPAGE APRINTK((lanai->num_vci) * sizeof(struct lanai_vcc *) <= PAGE_SIZE, "vcc table > PAGE_SIZE!"); lanai->vccs = (struct lanai_vcc **) get_zeroed_page(GFP_KERNEL); return (lanai->vccs == NULL) ? -ENOMEM : 0; #else int bytes = (lanai->num_vci) * sizeof(struct lanai_vcc *); lanai->vccs = (struct lanai_vcc **) vmalloc(bytes); if (unlikely(lanai->vccs == NULL)) return -ENOMEM; memset(lanai->vccs, 0, bytes); return 0; #endif } static inline void vcc_table_deallocate(const struct lanai_dev *lanai) { #ifdef VCCTABLE_GETFREEPAGE free_page((unsigned long) lanai->vccs); #else vfree(lanai->vccs); #endif } /* Allocate a fresh lanai_vcc, with the appropriate things cleared */ static inline struct lanai_vcc *new_lanai_vcc(void) { struct lanai_vcc *lvcc; lvcc = kzalloc(sizeof(*lvcc), GFP_KERNEL); if (likely(lvcc != NULL)) { skb_queue_head_init(&lvcc->tx.backlog); #ifdef DEBUG lvcc->vci = -1; #endif } return lvcc; } static int lanai_get_sized_buffer(struct lanai_dev *lanai, struct lanai_buffer *buf, int max_sdu, int multiplier, const char *name) { int size; if (unlikely(max_sdu < 1)) max_sdu = 1; max_sdu = aal5_size(max_sdu); size = (max_sdu + 16) * multiplier + 16; lanai_buf_allocate(buf, size, max_sdu + 32, lanai->pci); if (unlikely(buf->start == NULL)) return -ENOMEM; if (unlikely(lanai_buf_size(buf) < size)) printk(KERN_WARNING DEV_LABEL "(itf %d): wanted %d bytes " "for %s buffer, got only %Zu\n", lanai->number, size, name, lanai_buf_size(buf)); DPRINTK("Allocated %Zu byte %s buffer\n", lanai_buf_size(buf), name); return 0; } /* Setup a RX buffer for a currently unbound AAL5 vci */ static inline int lanai_setup_rx_vci_aal5(struct lanai_dev *lanai, struct lanai_vcc *lvcc, const struct atm_qos *qos) { return lanai_get_sized_buffer(lanai, &lvcc->rx.buf, qos->rxtp.max_sdu, AAL5_RX_MULTIPLIER, "RX"); } /* Setup a TX buffer for a currently unbound AAL5 vci */ static int lanai_setup_tx_vci(struct lanai_dev *lanai, struct lanai_vcc *lvcc, const struct atm_qos *qos) { int max_sdu, multiplier; if (qos->aal == ATM_AAL0) { lvcc->tx.unqueue = vcc_tx_unqueue_aal0; max_sdu = ATM_CELL_SIZE - 1; multiplier = AAL0_TX_MULTIPLIER; } else { lvcc->tx.unqueue = vcc_tx_unqueue_aal5; max_sdu = qos->txtp.max_sdu; multiplier = AAL5_TX_MULTIPLIER; } return lanai_get_sized_buffer(lanai, &lvcc->tx.buf, max_sdu, multiplier, "TX"); } static inline void host_vcc_bind(struct lanai_dev *lanai, struct lanai_vcc *lvcc, vci_t vci) { if (lvcc->vbase != NULL) return; /* We already were bound in the other direction */ DPRINTK("Binding vci %d\n", vci); #ifdef USE_POWERDOWN if (lanai->nbound++ == 0) { DPRINTK("Coming out of powerdown\n"); lanai->conf1 &= ~CONFIG1_POWERDOWN; conf1_write(lanai); conf2_write(lanai); } #endif lvcc->vbase = cardvcc_addr(lanai, vci); lanai->vccs[lvcc->vci = vci] = lvcc; } static inline void host_vcc_unbind(struct lanai_dev *lanai, struct lanai_vcc *lvcc) { if (lvcc->vbase == NULL) return; /* This vcc was never bound */ DPRINTK("Unbinding vci %d\n", lvcc->vci); lvcc->vbase = NULL; lanai->vccs[lvcc->vci] = NULL; #ifdef USE_POWERDOWN if (--lanai->nbound == 0) { DPRINTK("Going into powerdown\n"); lanai->conf1 |= CONFIG1_POWERDOWN; conf1_write(lanai); } #endif } /* -------------------- RESET CARD: */ static void lanai_reset(struct lanai_dev *lanai) { printk(KERN_CRIT DEV_LABEL "(itf %d): *NOT* reseting - not " "implemented\n", lanai->number); /* TODO */ /* The following is just a hack until we write the real * resetter - at least ack whatever interrupt sent us * here */ reg_write(lanai, INT_ALL, IntAck_Reg); lanai->stats.card_reset++; } /* -------------------- SERVICE LIST UTILITIES: */ /* * Allocate service buffer and tell card about it */ static int __devinit service_buffer_allocate(struct lanai_dev *lanai) { lanai_buf_allocate(&lanai->service, SERVICE_ENTRIES * 4, 8, lanai->pci); if (unlikely(lanai->service.start == NULL)) return -ENOMEM; DPRINTK("allocated service buffer at 0x%08lX, size %Zu(%d)\n", (unsigned long) lanai->service.start, lanai_buf_size(&lanai->service), lanai_buf_size_cardorder(&lanai->service)); /* Clear ServWrite register to be safe */ reg_write(lanai, 0, ServWrite_Reg); /* ServiceStuff register contains size and address of buffer */ reg_write(lanai, SSTUFF_SET_SIZE(lanai_buf_size_cardorder(&lanai->service)) | SSTUFF_SET_ADDR(lanai->service.dmaaddr), ServiceStuff_Reg); return 0; } static inline void service_buffer_deallocate(struct lanai_dev *lanai) { lanai_buf_deallocate(&lanai->service, lanai->pci); } /* Bitfields in service list */ #define SERVICE_TX (0x80000000) /* Was from transmission */ #define SERVICE_TRASH (0x40000000) /* RXed PDU was trashed */ #define SERVICE_CRCERR (0x20000000) /* RXed PDU had CRC error */ #define SERVICE_CI (0x10000000) /* RXed PDU had CI set */ #define SERVICE_CLP (0x08000000) /* RXed PDU had CLP set */ #define SERVICE_STREAM (0x04000000) /* RX Stream mode */ #define SERVICE_GET_VCI(x) (((x)>>16)&0x3FF) #define SERVICE_GET_END(x) ((x)&0x1FFF) /* Handle one thing from the service list - returns true if it marked a * VCC ready for xmit */ static int handle_service(struct lanai_dev *lanai, u32 s) { vci_t vci = SERVICE_GET_VCI(s); struct lanai_vcc *lvcc; read_lock(&vcc_sklist_lock); lvcc = lanai->vccs[vci]; if (unlikely(lvcc == NULL)) { read_unlock(&vcc_sklist_lock); DPRINTK("(itf %d) got service entry 0x%X for nonexistent " "vcc %d\n", lanai->number, (unsigned int) s, vci); if (s & SERVICE_TX) lanai->stats.service_notx++; else lanai->stats.service_norx++; return 0; } if (s & SERVICE_TX) { /* segmentation interrupt */ if (unlikely(lvcc->tx.atmvcc == NULL)) { read_unlock(&vcc_sklist_lock); DPRINTK("(itf %d) got service entry 0x%X for non-TX " "vcc %d\n", lanai->number, (unsigned int) s, vci); lanai->stats.service_notx++; return 0; } __set_bit(vci, lanai->transmit_ready); lvcc->tx.endptr = SERVICE_GET_END(s); read_unlock(&vcc_sklist_lock); return 1; } if (unlikely(lvcc->rx.atmvcc == NULL)) { read_unlock(&vcc_sklist_lock); DPRINTK("(itf %d) got service entry 0x%X for non-RX " "vcc %d\n", lanai->number, (unsigned int) s, vci); lanai->stats.service_norx++; return 0; } if (unlikely(lvcc->rx.atmvcc->qos.aal != ATM_AAL5)) { read_unlock(&vcc_sklist_lock); DPRINTK("(itf %d) got RX service entry 0x%X for non-AAL5 " "vcc %d\n", lanai->number, (unsigned int) s, vci); lanai->stats.service_rxnotaal5++; atomic_inc(&lvcc->rx.atmvcc->stats->rx_err); return 0; } if (likely(!(s & (SERVICE_TRASH | SERVICE_STREAM | SERVICE_CRCERR)))) { vcc_rx_aal5(lvcc, SERVICE_GET_END(s)); read_unlock(&vcc_sklist_lock); return 0; } if (s & SERVICE_TRASH) { int bytes; read_unlock(&vcc_sklist_lock); DPRINTK("got trashed rx pdu on vci %d\n", vci); atomic_inc(&lvcc->rx.atmvcc->stats->rx_err); lvcc->stats.x.aal5.service_trash++; bytes = (SERVICE_GET_END(s) * 16) - (((unsigned long) lvcc->rx.buf.ptr) - ((unsigned long) lvcc->rx.buf.start)) + 47; if (bytes < 0) bytes += lanai_buf_size(&lvcc->rx.buf); lanai->stats.ovfl_trash += (bytes / 48); return 0; } if (s & SERVICE_STREAM) { read_unlock(&vcc_sklist_lock); atomic_inc(&lvcc->rx.atmvcc->stats->rx_err); lvcc->stats.x.aal5.service_stream++; printk(KERN_ERR DEV_LABEL "(itf %d): Got AAL5 stream " "PDU on VCI %d!\n", lanai->number, vci); lanai_reset(lanai); return 0; } DPRINTK("got rx crc error on vci %d\n", vci); atomic_inc(&lvcc->rx.atmvcc->stats->rx_err); lvcc->stats.x.aal5.service_rxcrc++; lvcc->rx.buf.ptr = &lvcc->rx.buf.start[SERVICE_GET_END(s) * 4]; cardvcc_write(lvcc, SERVICE_GET_END(s), vcc_rxreadptr); read_unlock(&vcc_sklist_lock); return 0; } /* Try transmitting on all VCIs that we marked ready to serve */ static void iter_transmit(struct lanai_dev *lanai, vci_t vci) { struct lanai_vcc *lvcc = lanai->vccs[vci]; if (vcc_is_backlogged(lvcc)) lvcc->tx.unqueue(lanai, lvcc, lvcc->tx.endptr); } /* Run service queue -- called from interrupt context or with * interrupts otherwise disabled and with the lanai->servicelock * lock held */ static void run_service(struct lanai_dev *lanai) { int ntx = 0; u32 wreg = reg_read(lanai, ServWrite_Reg); const u32 *end = lanai->service.start + wreg; while (lanai->service.ptr != end) { ntx += handle_service(lanai, le32_to_cpup(lanai->service.ptr++)); if (lanai->service.ptr >= lanai->service.end) lanai->service.ptr = lanai->service.start; } reg_write(lanai, wreg, ServRead_Reg); if (ntx != 0) { read_lock(&vcc_sklist_lock); vci_bitfield_iterate(lanai, lanai->transmit_ready, iter_transmit); bitmap_zero(lanai->transmit_ready, NUM_VCI); read_unlock(&vcc_sklist_lock); } } /* -------------------- GATHER STATISTICS: */ static void get_statistics(struct lanai_dev *lanai) { u32 statreg = reg_read(lanai, Statistics_Reg); lanai->stats.atm_ovfl += STATS_GET_FIFO_OVFL(statreg); lanai->stats.hec_err += STATS_GET_HEC_ERR(statreg); lanai->stats.vci_trash += STATS_GET_BAD_VCI(statreg); lanai->stats.ovfl_trash += STATS_GET_BUF_OVFL(statreg); } /* -------------------- POLLING TIMER: */ #ifndef DEBUG_RW /* Try to undequeue 1 backlogged vcc */ static void iter_dequeue(struct lanai_dev *lanai, vci_t vci) { struct lanai_vcc *lvcc = lanai->vccs[vci]; int endptr; if (lvcc == NULL || lvcc->tx.atmvcc == NULL || !vcc_is_backlogged(lvcc)) { __clear_bit(vci, lanai->backlog_vccs); return; } endptr = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr)); lvcc->tx.unqueue(lanai, lvcc, endptr); } #endif /* !DEBUG_RW */ static void lanai_timed_poll(unsigned long arg) { struct lanai_dev *lanai = (struct lanai_dev *) arg; #ifndef DEBUG_RW unsigned long flags; #ifdef USE_POWERDOWN if (lanai->conf1 & CONFIG1_POWERDOWN) return; #endif /* USE_POWERDOWN */ local_irq_save(flags); /* If we can grab the spinlock, check if any services need to be run */ if (spin_trylock(&lanai->servicelock)) { run_service(lanai); spin_unlock(&lanai->servicelock); } /* ...and see if any backlogged VCs can make progress */ /* unfortunately linux has no read_trylock() currently */ read_lock(&vcc_sklist_lock); vci_bitfield_iterate(lanai, lanai->backlog_vccs, iter_dequeue); read_unlock(&vcc_sklist_lock); local_irq_restore(flags); get_statistics(lanai); #endif /* !DEBUG_RW */ mod_timer(&lanai->timer, jiffies + LANAI_POLL_PERIOD); } static inline void lanai_timed_poll_start(struct lanai_dev *lanai) { init_timer(&lanai->timer); lanai->timer.expires = jiffies + LANAI_POLL_PERIOD; lanai->timer.data = (unsigned long) lanai; lanai->timer.function = lanai_timed_poll; add_timer(&lanai->timer); } static inline void lanai_timed_poll_stop(struct lanai_dev *lanai) { del_timer_sync(&lanai->timer); } /* -------------------- INTERRUPT SERVICE: */ static inline void lanai_int_1(struct lanai_dev *lanai, u32 reason) { u32 ack = 0; if (reason & INT_SERVICE) { ack = INT_SERVICE; spin_lock(&lanai->servicelock); run_service(lanai); spin_unlock(&lanai->servicelock); } if (reason & (INT_AAL0_STR | INT_AAL0)) { ack |= reason & (INT_AAL0_STR | INT_AAL0); vcc_rx_aal0(lanai); } /* The rest of the interrupts are pretty rare */ if (ack == reason) goto done; if (reason & INT_STATS) { reason &= ~INT_STATS; /* No need to ack */ get_statistics(lanai); } if (reason & INT_STATUS) { ack |= reason & INT_STATUS; lanai_check_status(lanai); } if (unlikely(reason & INT_DMASHUT)) { printk(KERN_ERR DEV_LABEL "(itf %d): driver error - DMA " "shutdown, reason=0x%08X, address=0x%08X\n", lanai->number, (unsigned int) (reason & INT_DMASHUT), (unsigned int) reg_read(lanai, DMA_Addr_Reg)); if (reason & INT_TABORTBM) { lanai_reset(lanai); return; } ack |= (reason & INT_DMASHUT); printk(KERN_ERR DEV_LABEL "(itf %d): re-enabling DMA\n", lanai->number); conf1_write(lanai); lanai->stats.dma_reenable++; pcistatus_check(lanai, 0); } if (unlikely(reason & INT_TABORTSENT)) { ack |= (reason & INT_TABORTSENT); printk(KERN_ERR DEV_LABEL "(itf %d): sent PCI target abort\n", lanai->number); pcistatus_check(lanai, 0); } if (unlikely(reason & INT_SEGSHUT)) { printk(KERN_ERR DEV_LABEL "(itf %d): driver error - " "segmentation shutdown, reason=0x%08X\n", lanai->number, (unsigned int) (reason & INT_SEGSHUT)); lanai_reset(lanai); return; } if (unlikely(reason & (INT_PING | INT_WAKE))) { printk(KERN_ERR DEV_LABEL "(itf %d): driver error - " "unexpected interrupt 0x%08X, resetting\n", lanai->number, (unsigned int) (reason & (INT_PING | INT_WAKE))); lanai_reset(lanai); return; } #ifdef DEBUG if (unlikely(ack != reason)) { DPRINTK("unacked ints: 0x%08X\n", (unsigned int) (reason & ~ack)); ack = reason; } #endif done: if (ack != 0) reg_write(lanai, ack, IntAck_Reg); } static irqreturn_t lanai_int(int irq, void *devid) { struct lanai_dev *lanai = devid; u32 reason; #ifdef USE_POWERDOWN /* * If we're powered down we shouldn't be generating any interrupts - * so assume that this is a shared interrupt line and it's for someone * else */ if (unlikely(lanai->conf1 & CONFIG1_POWERDOWN)) return IRQ_NONE; #endif reason = intr_pending(lanai); if (reason == 0) return IRQ_NONE; /* Must be for someone else */ do { if (unlikely(reason == 0xFFFFFFFF)) break; /* Maybe we've been unplugged? */ lanai_int_1(lanai, reason); reason = intr_pending(lanai); } while (reason != 0); return IRQ_HANDLED; } /* TODO - it would be nice if we could use the "delayed interrupt" system * to some advantage */ /* -------------------- CHECK BOARD ID/REV: */ /* * The board id and revision are stored both in the reset register and * in the PCI configuration space - the documentation says to check * each of them. If revp!=NULL we store the revision there */ static int check_board_id_and_rev(const char *name, u32 val, int *revp) { DPRINTK("%s says board_id=%d, board_rev=%d\n", name, (int) RESET_GET_BOARD_ID(val), (int) RESET_GET_BOARD_REV(val)); if (RESET_GET_BOARD_ID(val) != BOARD_ID_LANAI256) { printk(KERN_ERR DEV_LABEL ": Found %s board-id %d -- not a " "Lanai 25.6\n", name, (int) RESET_GET_BOARD_ID(val)); return -ENODEV; } if (revp != NULL) *revp = RESET_GET_BOARD_REV(val); return 0; } /* -------------------- PCI INITIALIZATION/SHUTDOWN: */ static int __devinit lanai_pci_start(struct lanai_dev *lanai) { struct pci_dev *pci = lanai->pci; int result; u16 w; if (pci_enable_device(pci) != 0) { printk(KERN_ERR DEV_LABEL "(itf %d): can't enable " "PCI device", lanai->number); return -ENXIO; } pci_set_master(pci); if (pci_set_dma_mask(pci, DMA_32BIT_MASK) != 0) { printk(KERN_WARNING DEV_LABEL "(itf %d): No suitable DMA available.\n", lanai->number); return -EBUSY; } if (pci_set_consistent_dma_mask(pci, DMA_32BIT_MASK) != 0) { printk(KERN_WARNING DEV_LABEL "(itf %d): No suitable DMA available.\n", lanai->number); return -EBUSY; } /* Get the pci revision byte */ result = pci_read_config_byte(pci, PCI_REVISION_ID, &lanai->pci_revision); if (result != PCIBIOS_SUCCESSFUL) { printk(KERN_ERR DEV_LABEL "(itf %d): can't read " "PCI_REVISION_ID: %d\n", lanai->number, result); return -EINVAL; } result = pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &w); if (result != PCIBIOS_SUCCESSFUL) { printk(KERN_ERR DEV_LABEL "(itf %d): can't read " "PCI_SUBSYSTEM_ID: %d\n", lanai->number, result); return -EINVAL; } result = check_board_id_and_rev("PCI", w, NULL); if (result != 0) return result; /* Set latency timer to zero as per lanai docs */ result = pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0); if (result != PCIBIOS_SUCCESSFUL) { printk(KERN_ERR DEV_LABEL "(itf %d): can't write " "PCI_LATENCY_TIMER: %d\n", lanai->number, result); return -EINVAL; } pcistatus_check(lanai, 1); pcistatus_check(lanai, 0); return 0; } /* -------------------- VPI/VCI ALLOCATION: */ /* * We _can_ use VCI==0 for normal traffic, but only for UBR (or we'll * get a CBRZERO interrupt), and we can use it only if noone is receiving * AAL0 traffic (since they will use the same queue) - according to the * docs we shouldn't even use it for AAL0 traffic */ static inline int vci0_is_ok(struct lanai_dev *lanai, const struct atm_qos *qos) { if (qos->txtp.traffic_class == ATM_CBR || qos->aal == ATM_AAL0) return 0; if (qos->rxtp.traffic_class != ATM_NONE) { if (lanai->naal0 != 0) return 0; lanai->conf2 |= CONFIG2_VCI0_NORMAL; conf2_write_if_powerup(lanai); } return 1; } /* return true if vci is currently unused, or if requested qos is * compatible */ static int vci_is_ok(struct lanai_dev *lanai, vci_t vci, const struct atm_vcc *atmvcc) { const struct atm_qos *qos = &atmvcc->qos; const struct lanai_vcc *lvcc = lanai->vccs[vci]; if (vci == 0 && !vci0_is_ok(lanai, qos)) return 0; if (unlikely(lvcc != NULL)) { if (qos->rxtp.traffic_class != ATM_NONE && lvcc->rx.atmvcc != NULL && lvcc->rx.atmvcc != atmvcc) return 0; if (qos->txtp.traffic_class != ATM_NONE && lvcc->tx.atmvcc != NULL && lvcc->tx.atmvcc != atmvcc) return 0; if (qos->txtp.traffic_class == ATM_CBR && lanai->cbrvcc != NULL && lanai->cbrvcc != atmvcc) return 0; } if (qos->aal == ATM_AAL0 && lanai->naal0 == 0 && qos->rxtp.traffic_class != ATM_NONE) { const struct lanai_vcc *vci0 = lanai->vccs[0]; if (vci0 != NULL && vci0->rx.atmvcc != NULL) return 0; lanai->conf2 &= ~CONFIG2_VCI0_NORMAL; conf2_write_if_powerup(lanai); } return 1; } static int lanai_normalize_ci(struct lanai_dev *lanai, const struct atm_vcc *atmvcc, short *vpip, vci_t *vcip) { switch (*vpip) { case ATM_VPI_ANY: *vpip = 0; /* FALLTHROUGH */ case 0: break; default: return -EADDRINUSE; } switch (*vcip) { case ATM_VCI_ANY: for (*vcip = ATM_NOT_RSV_VCI; *vcip < lanai->num_vci; (*vcip)++) if (vci_is_ok(lanai, *vcip, atmvcc)) return 0; return -EADDRINUSE; default: if (*vcip >= lanai->num_vci || *vcip < 0 || !vci_is_ok(lanai, *vcip, atmvcc)) return -EADDRINUSE; } return 0; } /* -------------------- MANAGE CBR: */ /* * CBR ICG is stored as a fixed-point number with 4 fractional bits. * Note that storing a number greater than 2046.0 will result in * incorrect shaping */ #define CBRICG_FRAC_BITS (4) #define CBRICG_MAX (2046 << CBRICG_FRAC_BITS) /* * ICG is related to PCR with the formula PCR = MAXPCR / (ICG + 1) * where MAXPCR is (according to the docs) 25600000/(54*8), * which is equal to (3125<<9)/27. * * Solving for ICG, we get: * ICG = MAXPCR/PCR - 1 * ICG = (3125<<9)/(27*PCR) - 1 * ICG = ((3125<<9) - (27*PCR)) / (27*PCR) * * The end result is supposed to be a fixed-point number with FRAC_BITS * bits of a fractional part, so we keep everything in the numerator * shifted by that much as we compute * */ static int pcr_to_cbricg(const struct atm_qos *qos) { int rounddown = 0; /* 1 = Round PCR down, i.e. round ICG _up_ */ int x, icg, pcr = atm_pcr_goal(&qos->txtp); if (pcr == 0) /* Use maximum bandwidth */ return 0; if (pcr < 0) { rounddown = 1; pcr = -pcr; } x = pcr * 27; icg = (3125 << (9 + CBRICG_FRAC_BITS)) - (x << CBRICG_FRAC_BITS); if (rounddown) icg += x - 1; icg /= x; if (icg > CBRICG_MAX) icg = CBRICG_MAX; DPRINTK("pcr_to_cbricg: pcr=%d rounddown=%c icg=%d\n", pcr, rounddown ? 'Y' : 'N', icg); return icg; } static inline void lanai_cbr_setup(struct lanai_dev *lanai) { reg_write(lanai, pcr_to_cbricg(&lanai->cbrvcc->qos), CBR_ICG_Reg); reg_write(lanai, lanai->cbrvcc->vci, CBR_PTR_Reg); lanai->conf2 |= CONFIG2_CBR_ENABLE; conf2_write(lanai); } static inline void lanai_cbr_shutdown(struct lanai_dev *lanai) { lanai->conf2 &= ~CONFIG2_CBR_ENABLE; conf2_write(lanai); } /* -------------------- OPERATIONS: */ /* setup a newly detected device */ static int __devinit lanai_dev_open(struct atm_dev *atmdev) { struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data; unsigned long raw_base; int result; DPRINTK("In lanai_dev_open()\n"); /* Basic device fields */ lanai->number = atmdev->number; lanai->num_vci = NUM_VCI; bitmap_zero(lanai->backlog_vccs, NUM_VCI); bitmap_zero(lanai->transmit_ready, NUM_VCI); lanai->naal0 = 0; #ifdef USE_POWERDOWN lanai->nbound = 0; #endif lanai->cbrvcc = NULL; memset(&lanai->stats, 0, sizeof lanai->stats); spin_lock_init(&lanai->endtxlock); spin_lock_init(&lanai->servicelock); atmdev->ci_range.vpi_bits = 0; atmdev->ci_range.vci_bits = 0; while (1 << atmdev->ci_range.vci_bits < lanai->num_vci) atmdev->ci_range.vci_bits++; atmdev->link_rate = ATM_25_PCR; /* 3.2: PCI initialization */ if ((result = lanai_pci_start(lanai)) != 0) goto error; raw_base = lanai->pci->resource[0].start; lanai->base = (bus_addr_t) ioremap(raw_base, LANAI_MAPPING_SIZE); if (lanai->base == NULL) { printk(KERN_ERR DEV_LABEL ": couldn't remap I/O space\n"); goto error_pci; } /* 3.3: Reset lanai and PHY */ reset_board(lanai); lanai->conf1 = reg_read(lanai, Config1_Reg); lanai->conf1 &= ~(CONFIG1_GPOUT1 | CONFIG1_POWERDOWN | CONFIG1_MASK_LEDMODE); lanai->conf1 |= CONFIG1_SET_LEDMODE(LEDMODE_NOT_SOOL); reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg); udelay(1000); conf1_write(lanai); /* * 3.4: Turn on endian mode for big-endian hardware * We don't actually want to do this - the actual bit fields * in the endian register are not documented anywhere. * Instead we do the bit-flipping ourselves on big-endian * hardware. * * 3.5: get the board ID/rev by reading the reset register */ result = check_board_id_and_rev("register", reg_read(lanai, Reset_Reg), &lanai->board_rev); if (result != 0) goto error_unmap; /* 3.6: read EEPROM */ if ((result = eeprom_read(lanai)) != 0) goto error_unmap; if ((result = eeprom_validate(lanai)) != 0) goto error_unmap; /* 3.7: re-reset PHY, do loopback tests, setup PHY */ reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg); udelay(1000); conf1_write(lanai); /* TODO - loopback tests */ lanai->conf1 |= (CONFIG1_GPOUT2 | CONFIG1_GPOUT3 | CONFIG1_DMA_ENABLE); conf1_write(lanai); /* 3.8/3.9: test and initialize card SRAM */ if ((result = sram_test_and_clear(lanai)) != 0) goto error_unmap; /* 3.10: initialize lanai registers */ lanai->conf1 |= CONFIG1_DMA_ENABLE; conf1_write(lanai); if ((result = service_buffer_allocate(lanai)) != 0) goto error_unmap; if ((result = vcc_table_allocate(lanai)) != 0) goto error_service; lanai->conf2 = (lanai->num_vci >= 512 ? CONFIG2_HOWMANY : 0) | CONFIG2_HEC_DROP | /* ??? */ CONFIG2_PTI7_MODE; conf2_write(lanai); reg_write(lanai, TX_FIFO_DEPTH, TxDepth_Reg); reg_write(lanai, 0, CBR_ICG_Reg); /* CBR defaults to no limit */ if ((result = request_irq(lanai->pci->irq, lanai_int, IRQF_SHARED, DEV_LABEL, lanai)) != 0) { printk(KERN_ERR DEV_LABEL ": can't allocate interrupt\n"); goto error_vcctable; } mb(); /* Make sure that all that made it */ intr_enable(lanai, INT_ALL & ~(INT_PING | INT_WAKE)); /* 3.11: initialize loop mode (i.e. turn looping off) */ lanai->conf1 = (lanai->conf1 & ~CONFIG1_MASK_LOOPMODE) | CONFIG1_SET_LOOPMODE(LOOPMODE_NORMAL) | CONFIG1_GPOUT2 | CONFIG1_GPOUT3; conf1_write(lanai); lanai->status = reg_read(lanai, Status_Reg); /* We're now done initializing this card */ #ifdef USE_POWERDOWN lanai->conf1 |= CONFIG1_POWERDOWN; conf1_write(lanai); #endif memcpy(atmdev->esi, eeprom_mac(lanai), ESI_LEN); lanai_timed_poll_start(lanai); printk(KERN_NOTICE DEV_LABEL "(itf %d): rev.%d, base=0x%lx, irq=%u "