/*********************************************************************** ;* File Name : TMSCSIM.H * ;* TEKRAM DC-390(T) PCI SCSI Bus Master Host Adapter * ;* Device Driver * ;***********************************************************************/ /* $Id: tmscsim.h,v 2.15.2.3 2000/11/17 20:52:27 garloff Exp $ */ #ifndef _TMSCSIM_H #define _TMSCSIM_H #include #define SCSI_IRQ_NONE 255 #define MAX_ADAPTER_NUM 4 #define MAX_SG_LIST_BUF 16 /* Not used */ #define MAX_SCSI_ID 8 #define MAX_SRB_CNT 50 /* Max number of started commands */ #define SEL_TIMEOUT 153 /* 250 ms selection timeout (@ 40 MHz) */ /* ;----------------------------------------------------------------------- ; SCSI Request Block ;----------------------------------------------------------------------- */ struct dc390_srb { //u8 CmdBlock[12]; struct dc390_srb *pNextSRB; struct dc390_dcb *pSRBDCB; struct scsi_cmnd *pcmd; struct scatterlist *pSegmentList; struct scatterlist Segmentx; /* make a one entry of S/G list table */ unsigned long SGBusAddr; /*;a segment starting address as seen by AM53C974A in CPU endianness. We're only getting 32-bit bus addresses by default */ unsigned long SGToBeXferLen; /*; to be xfer length */ unsigned long TotalXferredLen; unsigned long SavedTotXLen; unsigned long Saved_Ptr; u32 SRBState; u8 SRBStatus; u8 SRBFlag; /*; b0-AutoReqSense,b6-Read,b7-write */ /*; b4-settimeout,b5-Residual valid */ u8 AdaptStatus; u8 TargetStatus; u8 ScsiPhase; s8 TagNumber; u8 SGIndex; u8 SGcount; u8 MsgCnt; u8 EndMessage; u8 MsgInBuf[6]; u8 MsgOutBuf[6]; //u8 IORBFlag; /*;81h-Reset, 2-retry */ }; /* ;----------------------------------------------------------------------- ; Device Control Block ;----------------------------------------------------------------------- */ struct dc390_dcb { struct dc390_dcb *pNextDCB; struct dc390_acb *pDCBACB; /* Queued SRBs */ struct dc390_srb *pGoingSRB; struct dc390_srb *pGoingLast; struct dc390_srb *pActiveSRB; u8 GoingSRBCnt; u32 TagMask; u8 TargetID; /*; SCSI Target ID (SCSI Only) */ u8 TargetLUN; /*; SCSI Log. Unit (SCSI Only) */ u8 DevMode; u8 DCBFlag; u8 CtrlR1; u8 CtrlR3; u8 CtrlR4; u8 SyncMode; /*; 0:async mode */ u8 NegoPeriod; /*;for nego. */ u8 SyncPeriod; /*;for reg. Linux kernel release 2.6.xx <http://kernel.org/> These are the release notes for Linux version 2.6. Read them carefully, as they tell you what this is all about, explain how to install the kernel, and what to do if something goes wrong. WHAT IS LINUX? Linux is a clone of the operating system Unix, written from scratch by Linus Torvalds with assistance from a loosely-knit team of hackers across the Net. It aims towards POSIX and Single UNIX Specification compliance. It has all the features you would expect in a modern fully-fledged Unix, including true multitasking, virtual memory, shared libraries, demand loading, shared copy-on-write executables, proper memory management, and multistack networking including IPv4 and IPv6. It is distributed under the GNU General Public License - see the accompanying COPYING file for more details. ON WHAT HARDWARE DOES IT RUN? Although originally developed first for 32-bit x86-based PCs (386 or higher), today Linux also runs on (at least) the Compaq Alpha AXP, Sun SPARC and UltraSPARC, Motorola 68000, PowerPC, PowerPC64, ARM, Hitachi SuperH, Cell, IBM S/390, MIPS, HP PA-RISC, Intel IA-64, DEC VAX, AMD x86-64, AXIS CRIS, Xtensa, AVR32 and Renesas M32R architectures. Linux is easily portable to most general-purpose 32- or 64-bit architectures as long as they have a paged memory management unit (PMMU) and a port of the GNU C compiler (gcc) (part of The GNU Compiler Collection, GCC). Linux has also been ported to a number of architectures without a PMMU, although functionality is then obviously somewhat limited. Linux has also been ported to itself. You can now run the kernel as a userspace application - this is called UserMode Linux (UML). DOCUMENTATION: - There is a lot of documentation available both in electronic form on the Internet and in books, both Linux-specific and pertaining to general UNIX questions. I'd recommend looking into the documentation subdirectories on any Linux FTP site for the LDP (Linux Documentation Project) books. This README is not meant to be documentation on the system: there are much better sources available. - There are various README files in the Documentation/ subdirectory: these typically contain kernel-specific installation notes for some drivers for example. See Documentation/00-INDEX for a list of what is contained in each file. Please read the Changes file, as it contains information about the problems, which may result by upgrading your kernel. - The Documentation/DocBook/ subdirectory contains several guides for kernel developers and users. These guides can be rendered in a number of formats: PostScript (.ps), PDF, and HTML, among others. After installation, "make psdocs", "make pdfdocs", or "make htmldocs" will render the documentation in the requested format. INSTALLING the kernel: - If you install the full sources, put the kernel tarball in a directory where you have permissions (eg. your home directory) and unpack it: gzip -cd linux-2.6.XX.tar.gz | tar xvf - or bzip2 -dc linux-2.6.XX.tar.bz2 | tar xvf - Replace "XX" with the version number of the latest kernel. Do NOT use the /usr/src/linux area! This area has a (usually incomplete) set of kernel headers that are used by the library header files. They should match the library, and not get messed up by whatever the kernel-du-jour happens to be. - You can also upgrade between 2.6.xx releases by patching. Patches are distributed in the traditional gzip and the newer bzip2 format. To install by patching, get all the newer patch files, enter the top level directory of the kernel source (linux-2.6.xx) and execute: gzip -cd ../patch-2.6.xx.gz | patch -p1 or bzip2 -dc ../patch-2.6.xx.bz2 | patch -p1 (repeat xx for all versions bigger than the version of your current source tree, _in_order_) and you should be ok. You may want to remove the backup files (xxx~ or xxx.orig), and make ) #define SET_RES_TARGET_LNX(who, tgt) do { who &= ~RES_TARGET_LNX; who |= (int)(tgt) << 1; } while (0) #define SET_RES_MSG(who, msg) do { who &= ~RES_ENDMSG; who |= (int)(msg) << 8; } while (0) #define SET_RES_DID(who, did) do { who &= ~RES_DID; who |= (int)(did) << 16; } while (0) #define SET_RES_DRV(who, drv) do { who &= ~RES_DRV; who |= (int)(drv) << 24; } while (0) /*;---Sync_Mode */ #define SYNC_DISABLE 0 #define SYNC_ENABLE BIT0 #define SYNC_NEGO_DONE BIT1 #define WIDE_ENABLE BIT2 /* Not used ;-) */ #define WIDE_NEGO_DONE BIT3 /* Not used ;-) */ #define EN_TAG_QUEUEING BIT4 #define EN_ATN_STOP BIT5 #define SYNC_NEGO_OFFSET 15 /*;---SCSI bus phase*/ #define SCSI_DATA_OUT 0 #define SCSI_DATA_IN 1 #define SCSI_COMMAND 2 #define SCSI_STATUS_ 3 #define SCSI_NOP0 4 #define SCSI_NOP1 5 #define SCSI_MSG_OUT 6 #define SCSI_MSG_IN 7 /*;----SCSI MSG BYTE*/ /* see scsi/scsi.h */ /* One is missing ! */ #define ABORT_TAG 0x0d /* * SISC query queue */ typedef struct { dma_addr_t saved_dma_handle; } dc390_cmd_scp_t; /* ;========================================================== ; EEPROM byte offset ;========================================================== */ typedef struct _EEprom { u8 EE_MODE1; u8 EE_SPEED; u8 xx1; u8 xx2; } EEprom, *PEEprom; #define REAL_EE_ADAPT_SCSI_ID 64 #define REAL_EE_MODE2 65 #define REAL_EE_DELAY 66 #define REAL_EE_TAG_CMD_NUM 67 #define EE_ADAPT_SCSI_ID 32 #define EE_MODE2 33 #define EE_DELAY 34 #define EE_TAG_CMD_NUM 35 #define EE_LEN 40 /*; EE_MODE1 bits definition*/ #define PARITY_CHK_ BIT0 #define SYNC_NEGO_ BIT1 #define EN_DISCONNECT_ BIT2 #define SEND_START_ BIT3 #define TAG_QUEUEING_ BIT4 /*; EE_MODE2 bits definition*/ #define MORE2_DRV BIT0 #define GREATER_1G BIT1 #define RST_SCSI_BUS BIT2 #define ACTIVE_NEGATION BIT3 #define NO_SEEK BIT4 #define LUN_CHECK BIT5 #define ENABLE_CE 1 #define DISABLE_CE 0 #define EEPROM_READ 0x80 /* ;========================================================== ; AMD 53C974 Registers bit Definition ;========================================================== */ /* ;==================== ; SCSI Register ;==================== */ /*; Command Reg.(+0CH) (rw) */ #define DMA_COMMAND BIT7 #define NOP_CMD 0 #define CLEAR_FIFO_CMD 1 #define RST_DEVICE_CMD 2 #define RST_SCSI_BUS_CMD 3 #define INFO_XFER_CMD 0x10 #define INITIATOR_CMD_CMPLTE 0x11 #define MSG_ACCEPTED_CMD 0x12 #define XFER_PAD_BYTE 0x18 #define SET_ATN_CMD 0x1A #define RESET_ATN_CMD 0x1B #define SEL_WO_ATN 0x41 /* currently not used */ #define SEL_W_ATN 0x42 #define SEL_W_ATN_STOP 0x43 #define SEL_W_ATN3 0x46 #define EN_SEL_RESEL 0x44 #define DIS_SEL_RESEL 0x45 /* currently not used */ #define RESEL 0x40 /* " */ #define RESEL_ATN3 0x47 /* " */ #define DATA_XFER_CMD INFO_XFER_CMD /*; SCSI Status Reg.(+10H) (r) */ #define INTERRUPT BIT7 #define ILLEGAL_OP_ERR BIT6 #define PARITY_ERR BIT5 #define COUNT_2_ZERO BIT4 #define GROUP_CODE_VALID BIT3 #define SCSI_PHASE_MASK (BIT2+BIT1+BIT0) /* BIT2: MSG phase; BIT1: C/D physe; BIT0: I/O phase */ /*; Interrupt Status Reg.(+14H) (r) */ #define SCSI_RESET BIT7 #define INVALID_CMD BIT6 #define DISCONNECTED BIT5 #define SERVICE_REQUEST BIT4 #define SUCCESSFUL_OP BIT3 #define RESELECTED BIT2 #define SEL_ATTENTION BIT1 #define SELECTED BIT0 /*; Internal State Reg.(+18H) (r) */ #define SYNC_OFFSET_FLAG BIT3 #define INTRN_STATE_MASK (BIT2+BIT1+BIT0) /* 0x04: Sel. successful (w/o stop), 0x01: Sel. successful (w/ stop) */ /*; Clock Factor Reg.(+24H) (w) */ #define CLK_FREQ_40MHZ 0 #define CLK_FREQ_35MHZ (BIT2+BIT1+BIT0) #define CLK_FREQ_30MHZ (BIT2+BIT1) #define CLK_FREQ_25MHZ (BIT2+BIT0) #define CLK_FREQ_20MHZ BIT2 #define CLK_FREQ_15MHZ (BIT1+BIT0) #define CLK_FREQ_10MHZ BIT1 /*; Control Reg. 1(+20H) (rw) */ #define EXTENDED_TIMING BIT7 #define DIS_INT_ON_SCSI_RST BIT6 #define PARITY_ERR_REPO BIT4 #define SCSI_ID_ON_BUS (BIT2+BIT1+BIT0) /* host adapter ID */ /*; Control Reg. 2(+2CH) (rw) */ #define EN_FEATURE BIT6 #define EN_SCSI2_CMD BIT3 /*; Control Reg. 3(+30H) (rw) */ #define ID_MSG_CHECK BIT7 #define EN_QTAG_MSG BIT6 #define EN_GRP2_CMD BIT5 #define FAST_SCSI BIT4 /* ;10MB/SEC */ #define FAST_CLK BIT3 /* ;25 - 40 MHZ */ /*; Control Reg. 4(+34H) (rw) */ #define EATER_12NS 0 #define EATER_25NS BIT7 #define EATER_35NS BIT6 #define EATER_0NS (BIT7+BIT6) #define REDUCED_POWER BIT5 #define CTRL4_RESERVED BIT4 /* must be 1 acc. to AM53C974.c */ #define NEGATE_REQACKDATA BIT2 #define NEGATE_REQACK BIT3 #define GLITCH_TO_NS(x) (((~x>>6 & 2) >> 1) | ((x>>6 & 1) << 1 ^ (x>>6 & 2))) #define NS_TO_GLITCH(y) (((~y<<7) | ~((y<<6) ^ ((y<<5 & 1<<6) | ~0x40))) & 0xc0) /* ;==================== ; DMA Register ;==================== */ /*; DMA Command Reg.(+40H) (rw) */ #define READ_DIRECTION BIT7 #define WRITE_DIRECTION 0 #define EN_DMA_INT BIT6 #define EN_PAGE_INT BIT5 /* page transfer interrupt enable */ #define MAP_TO_MDL BIT4 #define DIAGNOSTIC BIT2 #define DMA_IDLE_CMD 0 #define DMA_BLAST_CMD BIT0 #define DMA_ABORT_CMD BIT1 #define DMA_START_CMD (BIT1+BIT0) /*; DMA Status Reg.(+54H) (r) */ #define PCI_MS_ABORT BIT6 #define BLAST_COMPLETE BIT5 #define SCSI_INTERRUPT BIT4 #define DMA_XFER_DONE BIT3 #define DMA_XFER_ABORT BIT2 #define DMA_XFER_ERROR BIT1 #define POWER_DOWN BIT0 /*; DMA SCSI Bus and Ctrl.(+70H) */ #define EN_INT_ON_PCI_ABORT BIT25 #define WRT_ERASE_DMA_STAT BIT24 #define PW_DOWN_CTRL BIT21 #define SCSI_BUSY BIT20 #define SCLK BIT19 #define SCAM BIT18 #define SCSI_LINES 0x0003ffff /* ;========================================================== ; SCSI Chip register address offset ;========================================================== ;Registers are rw unless declared otherwise */ #define CtcReg_Low 0x00 /* r curr. transfer count */ #define CtcReg_Mid 0x04 /* r */ #define CtcReg_High 0x38 /* r */ #define ScsiFifo 0x08 #define ScsiCmd 0x0C #define Scsi_Status 0x10 /* r */ #define INT_Status 0x14 /* r */ #define Sync_Period 0x18 /* w */ #define Sync_Offset 0x1C /* w */ #define Clk_Factor 0x24 /* w */ #define CtrlReg1 0x20 #define CtrlReg2 0x2C #define CtrlReg3 0x30 #define CtrlReg4 0x34 #define DMA_Cmd 0x40 #define DMA_XferCnt 0x44 /* rw starting transfer count (32 bit) */ #define DMA_XferAddr 0x48 /* rw starting physical address (32 bit) */ #define DMA_Wk_ByteCntr 0x4C /* r working byte counter */ #define DMA_Wk_AddrCntr 0x50 /* r working address counter */ #define DMA_Status 0x54 /* r */ #define DMA_MDL_Addr 0x58 /* rw starting MDL address */ #define DMA_Wk_MDL_Cntr 0x5C /* r working MDL counter */ #define DMA_ScsiBusCtrl 0x70 /* rw SCSI Bus, PCI/DMA Ctrl */ #define StcReg_Low CtcReg_Low /* w start transfer count */ #define StcReg_Mid CtcReg_Mid /* w */ #define StcReg_High CtcReg_High /* w */ #define Scsi_Dest_ID Scsi_Status /* w */ #define Scsi_TimeOut INT_Status /* w */ #define Intern_State Sync_Period /* r */ #define Current_Fifo Sync_Offset /* r Curr. FIFO / int. state */ #define DC390_read8(address) \ (inb (pACB->IOPortBase + (address))) #define DC390_read8_(address, base) \ (inb ((u16)(base) + (address))) #define DC390_read16(address) \ (inw (pACB->IOPortBase + (address))) #define DC390_read32(address) \ (inl (pACB->IOPortBase + (address))) #define DC390_write8(address,value) \ outb ((value), pACB->IOPortBase + (address)) #define DC390_write8_(address,value,base) \ outb ((value), (u16)(base) + (address)) #define DC390_write16(address,value) \ outw ((value), pACB->IOPortBase + (address)) #define DC390_write32(address,value) \ outl ((value), pACB->IOPortBase + (address)) #endif /* _TMSCSIM_H */