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-rw-r--r--sound/soc/mediatek/Kconfig19
-rw-r--r--sound/soc/mediatek/Makefile1
-rw-r--r--sound/soc/mediatek/common/Makefile2
-rw-r--r--sound/soc/mediatek/common/mtk-btcvsd.c1364
-rw-r--r--sound/soc/mediatek/mt8183/Makefile13
-rw-r--r--sound/soc/mediatek/mt8183/mt8183-afe-clk.c611
-rw-r--r--sound/soc/mediatek/mt8183/mt8183-afe-clk.h38
-rw-r--r--sound/soc/mediatek/mt8183/mt8183-afe-common.h108
-rw-r--r--sound/soc/mediatek/mt8183/mt8183-afe-pcm.c1237
-rw-r--r--sound/soc/mediatek/mt8183/mt8183-dai-adda.c501
-rw-r--r--sound/soc/mediatek/mt8183/mt8183-dai-hostless.c118
-rw-r--r--sound/soc/mediatek/mt8183/mt8183-dai-i2s.c1040
-rw-r--r--sound/soc/mediatek/mt8183/mt8183-dai-pcm.c318
-rw-r--r--sound/soc/mediatek/mt8183/mt8183-dai-tdm.c639
-rw-r--r--sound/soc/mediatek/mt8183/mt8183-interconnection.h33
-rw-r--r--sound/soc/mediatek/mt8183/mt8183-reg.h1666
16 files changed, 7708 insertions, 0 deletions
diff --git a/sound/soc/mediatek/Kconfig b/sound/soc/mediatek/Kconfig
index e731d40afcce..b35410e4020e 100644
--- a/sound/soc/mediatek/Kconfig
+++ b/sound/soc/mediatek/Kconfig
@@ -105,3 +105,22 @@ config SND_SOC_MT8173_RT5650_RT5676
105 with the RT5650 and RT5676 codecs. 105 with the RT5650 and RT5676 codecs.
106 Select Y if you have such device. 106 Select Y if you have such device.
107 If unsure select "N". 107 If unsure select "N".
108
109config SND_SOC_MT8183
110 tristate "ASoC support for Mediatek MT8183 chip"
111 depends on ARCH_MEDIATEK
112 select SND_SOC_MEDIATEK
113 help
114 This adds ASoC platform driver support for Mediatek MT8183 chip
115 that can be used with other codecs.
116 Select Y if you have such device.
117 If unsure select "N".
118
119config SND_SOC_MTK_BTCVSD
120 tristate "ALSA BT SCO CVSD/MSBC Driver"
121 help
122 This is for software BTCVSD. This enable
123 the function for transferring/receiving
124 BT encoded data to/from BT firmware.
125 Select Y if you have such device.
126 If unsure select "N".
diff --git a/sound/soc/mediatek/Makefile b/sound/soc/mediatek/Makefile
index 3bb2c47532f4..76032cae6d51 100644
--- a/sound/soc/mediatek/Makefile
+++ b/sound/soc/mediatek/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_SND_SOC_MEDIATEK) += common/
3obj-$(CONFIG_SND_SOC_MT2701) += mt2701/ 3obj-$(CONFIG_SND_SOC_MT2701) += mt2701/
4obj-$(CONFIG_SND_SOC_MT6797) += mt6797/ 4obj-$(CONFIG_SND_SOC_MT6797) += mt6797/
5obj-$(CONFIG_SND_SOC_MT8173) += mt8173/ 5obj-$(CONFIG_SND_SOC_MT8173) += mt8173/
6obj-$(CONFIG_SND_SOC_MT8183) += mt8183/
diff --git a/sound/soc/mediatek/common/Makefile b/sound/soc/mediatek/common/Makefile
index cdadabc5fd16..9ab90433a8d7 100644
--- a/sound/soc/mediatek/common/Makefile
+++ b/sound/soc/mediatek/common/Makefile
@@ -2,3 +2,5 @@
2# platform driver 2# platform driver
3snd-soc-mtk-common-objs := mtk-afe-platform-driver.o mtk-afe-fe-dai.o 3snd-soc-mtk-common-objs := mtk-afe-platform-driver.o mtk-afe-fe-dai.o
4obj-$(CONFIG_SND_SOC_MEDIATEK) += snd-soc-mtk-common.o 4obj-$(CONFIG_SND_SOC_MEDIATEK) += snd-soc-mtk-common.o
5
6obj-$(CONFIG_SND_SOC_MTK_BTCVSD) += mtk-btcvsd.o \ No newline at end of file
diff --git a/sound/soc/mediatek/common/mtk-btcvsd.c b/sound/soc/mediatek/common/mtk-btcvsd.c
new file mode 100644
index 000000000000..e408c1b270ab
--- /dev/null
+++ b/sound/soc/mediatek/common/mtk-btcvsd.c
@@ -0,0 +1,1364 @@
1// SPDX-License-Identifier: GPL-2.0
2//
3// Mediatek ALSA BT SCO CVSD/MSBC Driver
4//
5// Copyright (c) 2019 MediaTek Inc.
6// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7
8#include <linux/mfd/syscon.h>
9#include <linux/module.h>
10#include <linux/of_address.h>
11#include <linux/sched/clock.h>
12
13#include <sound/soc.h>
14
15#define BTCVSD_SND_NAME "mtk-btcvsd-snd"
16
17#define BT_CVSD_TX_NREADY BIT(21)
18#define BT_CVSD_RX_READY BIT(22)
19#define BT_CVSD_TX_UNDERFLOW BIT(23)
20#define BT_CVSD_RX_OVERFLOW BIT(24)
21#define BT_CVSD_INTERRUPT BIT(31)
22
23#define BT_CVSD_CLEAR \
24 (BT_CVSD_TX_NREADY | BT_CVSD_RX_READY | BT_CVSD_TX_UNDERFLOW |\
25 BT_CVSD_RX_OVERFLOW | BT_CVSD_INTERRUPT)
26
27/* TX */
28#define SCO_TX_ENCODE_SIZE (60)
29/* 18 = 6 * 180 / SCO_TX_ENCODE_SIZE */
30#define SCO_TX_PACKER_BUF_NUM (18)
31
32/* RX */
33#define SCO_RX_PLC_SIZE (30)
34#define SCO_RX_PACKER_BUF_NUM (64)
35#define SCO_RX_PACKET_MASK (0x3F)
36
37#define SCO_CVSD_PACKET_VALID_SIZE 2
38
39#define SCO_PACKET_120 120
40#define SCO_PACKET_180 180
41
42#define BTCVSD_RX_PACKET_SIZE (SCO_RX_PLC_SIZE + SCO_CVSD_PACKET_VALID_SIZE)
43#define BTCVSD_TX_PACKET_SIZE (SCO_TX_ENCODE_SIZE)
44
45#define BTCVSD_RX_BUF_SIZE (BTCVSD_RX_PACKET_SIZE * SCO_RX_PACKER_BUF_NUM)
46#define BTCVSD_TX_BUF_SIZE (BTCVSD_TX_PACKET_SIZE * SCO_TX_PACKER_BUF_NUM)
47
48enum bt_sco_state {
49 BT_SCO_STATE_IDLE,
50 BT_SCO_STATE_RUNNING,
51 BT_SCO_STATE_ENDING,
52};
53
54enum bt_sco_direct {
55 BT_SCO_DIRECT_BT2ARM,
56 BT_SCO_DIRECT_ARM2BT,
57};
58
59enum bt_sco_packet_len {
60 BT_SCO_CVSD_30 = 0,
61 BT_SCO_CVSD_60,
62 BT_SCO_CVSD_90,
63 BT_SCO_CVSD_120,
64 BT_SCO_CVSD_10,
65 BT_SCO_CVSD_20,
66 BT_SCO_CVSD_MAX,
67};
68
69enum BT_SCO_BAND {
70 BT_SCO_NB,
71 BT_SCO_WB,
72};
73
74struct mtk_btcvsd_snd_hw_info {
75 unsigned int num_valid_addr;
76 unsigned long bt_sram_addr[20];
77 unsigned int packet_length;
78 unsigned int packet_num;
79};
80
81struct mtk_btcvsd_snd_stream {
82 struct snd_pcm_substream *substream;
83 int stream;
84
85 enum bt_sco_state state;
86
87 unsigned int packet_size;
88 unsigned int buf_size;
89 u8 temp_packet_buf[SCO_PACKET_180];
90
91 int packet_w;
92 int packet_r;
93 snd_pcm_uframes_t prev_frame;
94 int prev_packet_idx;
95
96 unsigned int xrun:1;
97 unsigned int timeout:1;
98 unsigned int mute:1;
99 unsigned int trigger_start:1;
100 unsigned int wait_flag:1;
101 unsigned int rw_cnt;
102
103 unsigned long long time_stamp;
104 unsigned long long buf_data_equivalent_time;
105
106 struct mtk_btcvsd_snd_hw_info buffer_info;
107};
108
109struct mtk_btcvsd_snd {
110 struct device *dev;
111 int irq_id;
112
113 struct regmap *infra;
114 void __iomem *bt_pkv_base;
115 void __iomem *bt_sram_bank2_base;
116
117 unsigned int infra_misc_offset;
118 unsigned int conn_bt_cvsd_mask;
119 unsigned int cvsd_mcu_read_offset;
120 unsigned int cvsd_mcu_write_offset;
121 unsigned int cvsd_packet_indicator;
122
123 u32 *bt_reg_pkt_r;
124 u32 *bt_reg_pkt_w;
125 u32 *bt_reg_ctl;
126
127 unsigned int irq_disabled:1;
128
129 spinlock_t tx_lock; /* spinlock for bt tx stream control */
130 spinlock_t rx_lock; /* spinlock for bt rx stream control */
131 wait_queue_head_t tx_wait;
132 wait_queue_head_t rx_wait;
133
134 struct mtk_btcvsd_snd_stream *tx;
135 struct mtk_btcvsd_snd_stream *rx;
136 u8 tx_packet_buf[BTCVSD_TX_BUF_SIZE];
137 u8 rx_packet_buf[BTCVSD_RX_BUF_SIZE];
138
139 enum BT_SCO_BAND band;
140};
141
142struct mtk_btcvsd_snd_time_buffer_info {
143 unsigned long long data_count_equi_time;
144 unsigned long long time_stamp_us;
145};
146
147static const unsigned int btsco_packet_valid_mask[BT_SCO_CVSD_MAX][6] = {
148 {0x1, 0x1 << 1, 0x1 << 2, 0x1 << 3, 0x1 << 4, 0x1 << 5},
149 {0x1, 0x1, 0x2, 0x2, 0x4, 0x4},
150 {0x1, 0x1, 0x1, 0x2, 0x2, 0x2},
151 {0x1, 0x1, 0x1, 0x1, 0x0, 0x0},
152 {0x7, 0x7 << 3, 0x7 << 6, 0x7 << 9, 0x7 << 12, 0x7 << 15},
153 {0x3, 0x3 << 1, 0x3 << 3, 0x3 << 4, 0x3 << 6, 0x3 << 7},
154};
155
156static const unsigned int btsco_packet_info[BT_SCO_CVSD_MAX][4] = {
157 {30, 6, SCO_PACKET_180 / SCO_TX_ENCODE_SIZE,
158 SCO_PACKET_180 / SCO_RX_PLC_SIZE},
159 {60, 3, SCO_PACKET_180 / SCO_TX_ENCODE_SIZE,
160 SCO_PACKET_180 / SCO_RX_PLC_SIZE},
161 {90, 2, SCO_PACKET_180 / SCO_TX_ENCODE_SIZE,
162 SCO_PACKET_180 / SCO_RX_PLC_SIZE},
163 {120, 1, SCO_PACKET_120 / SCO_TX_ENCODE_SIZE,
164 SCO_PACKET_120 / SCO_RX_PLC_SIZE},
165 {10, 18, SCO_PACKET_180 / SCO_TX_ENCODE_SIZE,
166 SCO_PACKET_180 / SCO_RX_PLC_SIZE},
167 {20, 9, SCO_PACKET_180 / SCO_TX_ENCODE_SIZE,
168 SCO_PACKET_180 / SCO_RX_PLC_SIZE},
169};
170
171static const u8 table_msbc_silence[SCO_PACKET_180] = {
172 0x01, 0x38, 0xad, 0x00, 0x00, 0xc5, 0x00, 0x00, 0x00, 0x00,
173 0x77, 0x6d, 0xb6, 0xdd, 0xdb, 0x6d, 0xb7, 0x76, 0xdb, 0x6d,
174 0xdd, 0xb6, 0xdb, 0x77, 0x6d, 0xb6, 0xdd, 0xdb, 0x6d, 0xb7,
175 0x76, 0xdb, 0x6d, 0xdd, 0xb6, 0xdb, 0x77, 0x6d, 0xb6, 0xdd,
176 0xdb, 0x6d, 0xb7, 0x76, 0xdb, 0x6d, 0xdd, 0xb6, 0xdb, 0x77,
177 0x6d, 0xb6, 0xdd, 0xdb, 0x6d, 0xb7, 0x76, 0xdb, 0x6c, 0x00,
178 0x01, 0xc8, 0xad, 0x00, 0x00, 0xc5, 0x00, 0x00, 0x00, 0x00,
179 0x77, 0x6d, 0xb6, 0xdd, 0xdb, 0x6d, 0xb7, 0x76, 0xdb, 0x6d,
180 0xdd, 0xb6, 0xdb, 0x77, 0x6d, 0xb6, 0xdd, 0xdb, 0x6d, 0xb7,
181 0x76, 0xdb, 0x6d, 0xdd, 0xb6, 0xdb, 0x77, 0x6d, 0xb6, 0xdd,
182 0xdb, 0x6d, 0xb7, 0x76, 0xdb, 0x6d, 0xdd, 0xb6, 0xdb, 0x77,
183 0x6d, 0xb6, 0xdd, 0xdb, 0x6d, 0xb7, 0x76, 0xdb, 0x6c, 0x00,
184 0x01, 0xf8, 0xad, 0x00, 0x00, 0xc5, 0x00, 0x00, 0x00, 0x00,
185 0x77, 0x6d, 0xb6, 0xdd, 0xdb, 0x6d, 0xb7, 0x76, 0xdb, 0x6d,
186 0xdd, 0xb6, 0xdb, 0x77, 0x6d, 0xb6, 0xdd, 0xdb, 0x6d, 0xb7,
187 0x76, 0xdb, 0x6d, 0xdd, 0xb6, 0xdb, 0x77, 0x6d, 0xb6, 0xdd,
188 0xdb, 0x6d, 0xb7, 0x76, 0xdb, 0x6d, 0xdd, 0xb6, 0xdb, 0x77,
189 0x6d, 0xb6, 0xdd, 0xdb, 0x6d, 0xb7, 0x76, 0xdb, 0x6c, 0x00
190};
191
192static void mtk_btcvsd_snd_irq_enable(struct mtk_btcvsd_snd *bt)
193{
194 regmap_update_bits(bt->infra, bt->infra_misc_offset,
195 bt->conn_bt_cvsd_mask, bt->conn_bt_cvsd_mask);
196}
197
198static void mtk_btcvsd_snd_irq_disable(struct mtk_btcvsd_snd *bt)
199{
200 regmap_update_bits(bt->infra, bt->infra_misc_offset,
201 bt->conn_bt_cvsd_mask, 0);
202}
203
204static void mtk_btcvsd_snd_set_state(struct mtk_btcvsd_snd *bt,
205 struct mtk_btcvsd_snd_stream *bt_stream,
206 int state)
207{
208 dev_dbg(bt->dev, "%s(), stream %d, state %d, tx->state %d, rx->state %d, irq_disabled %d\n",
209 __func__,
210 bt_stream->stream, state,
211 bt->tx->state, bt->rx->state, bt->irq_disabled);
212
213 bt_stream->state = state;
214
215 if (bt->tx->state == BT_SCO_STATE_IDLE &&
216 bt->rx->state == BT_SCO_STATE_IDLE) {
217 if (!bt->irq_disabled) {
218 disable_irq(bt->irq_id);
219 mtk_btcvsd_snd_irq_disable(bt);
220 bt->irq_disabled = 1;
221 }
222 } else {
223 if (bt->irq_disabled) {
224 enable_irq(bt->irq_id);
225 mtk_btcvsd_snd_irq_enable(bt);
226 bt->irq_disabled = 0;
227 }
228 }
229}
230
231static int mtk_btcvsd_snd_tx_init(struct mtk_btcvsd_snd *bt)
232{
233 memset(bt->tx, 0, sizeof(*bt->tx));
234 memset(bt->tx_packet_buf, 0, sizeof(bt->tx_packet_buf));
235
236 bt->tx->packet_size = BTCVSD_TX_PACKET_SIZE;
237 bt->tx->buf_size = BTCVSD_TX_BUF_SIZE;
238 bt->tx->timeout = 0;
239 bt->tx->rw_cnt = 0;
240 bt->tx->stream = SNDRV_PCM_STREAM_PLAYBACK;
241 return 0;
242}
243
244static int mtk_btcvsd_snd_rx_init(struct mtk_btcvsd_snd *bt)
245{
246 memset(bt->rx, 0, sizeof(*bt->rx));
247 memset(bt->rx_packet_buf, 0, sizeof(bt->rx_packet_buf));
248
249 bt->rx->packet_size = BTCVSD_RX_PACKET_SIZE;
250 bt->rx->buf_size = BTCVSD_RX_BUF_SIZE;
251 bt->rx->timeout = 0;
252 bt->rx->rw_cnt = 0;
253 bt->tx->stream = SNDRV_PCM_STREAM_CAPTURE;
254 return 0;
255}
256
257static void get_tx_time_stamp(struct mtk_btcvsd_snd *bt,
258 struct mtk_btcvsd_snd_time_buffer_info *ts)
259{
260 ts->time_stamp_us = bt->tx->time_stamp;
261 ts->data_count_equi_time = bt->tx->buf_data_equivalent_time;
262}
263
264static void get_rx_time_stamp(struct mtk_btcvsd_snd *bt,
265 struct mtk_btcvsd_snd_time_buffer_info *ts)
266{
267 ts->time_stamp_us = bt->rx->time_stamp;
268 ts->data_count_equi_time = bt->rx->buf_data_equivalent_time;
269}
270
271static int btcvsd_bytes_to_frame(struct snd_pcm_substream *substream,
272 int bytes)
273{
274 int count = bytes;
275 struct snd_pcm_runtime *runtime = substream->runtime;
276
277 if (runtime->format == SNDRV_PCM_FORMAT_S32_LE ||
278 runtime->format == SNDRV_PCM_FORMAT_U32_LE)
279 count = count >> 2;
280 else
281 count = count >> 1;
282
283 count = count / runtime->channels;
284 return count;
285}
286
287static void mtk_btcvsd_snd_data_transfer(enum bt_sco_direct dir,
288 u8 *src, u8 *dst,
289 unsigned int blk_size,
290 unsigned int blk_num)
291{
292 unsigned int i, j;
293
294 if (blk_size == 60 || blk_size == 120 || blk_size == 20) {
295 u32 *src_32 = (u32 *)src;
296 u32 *dst_32 = (u32 *)dst;
297
298 for (i = 0; i < (blk_size * blk_num / 4); i++)
299 *dst_32++ = *src_32++;
300 } else {
301 u16 *src_16 = (u16 *)src;
302 u16 *dst_16 = (u16 *)dst;
303
304 for (j = 0; j < blk_num; j++) {
305 for (i = 0; i < (blk_size / 2); i++)
306 *dst_16++ = *src_16++;
307
308 if (dir == BT_SCO_DIRECT_BT2ARM)
309 src_16++;
310 else
311 dst_16++;
312 }
313 }
314}
315
316/* write encoded mute data to bt sram */
317static int btcvsd_tx_clean_buffer(struct mtk_btcvsd_snd *bt)
318{
319 unsigned int i;
320 unsigned int num_valid_addr;
321 unsigned long flags;
322 enum BT_SCO_BAND band = bt->band;
323
324 /* prepare encoded mute data */
325 if (band == BT_SCO_NB)
326 memset(bt->tx->temp_packet_buf, 170, SCO_PACKET_180);
327 else
328 memcpy(bt->tx->temp_packet_buf,
329 table_msbc_silence, SCO_PACKET_180);
330
331 /* write mute data to bt tx sram buffer */
332 spin_lock_irqsave(&bt->tx_lock, flags);
333 num_valid_addr = bt->tx->buffer_info.num_valid_addr;
334
335 dev_info(bt->dev, "%s(), band %d, num_valid_addr %u\n",
336 __func__, band, num_valid_addr);
337
338 for (i = 0; i < num_valid_addr; i++) {
339 void *dst;
340
341 dev_info(bt->dev, "%s(), clean addr 0x%lx\n", __func__,
342 bt->tx->buffer_info.bt_sram_addr[i]);
343
344 dst = (void *)bt->tx->buffer_info.bt_sram_addr[i];
345
346 mtk_btcvsd_snd_data_transfer(BT_SCO_DIRECT_ARM2BT,
347 bt->tx->temp_packet_buf, dst,
348 bt->tx->buffer_info.packet_length,
349 bt->tx->buffer_info.packet_num);
350 }
351 spin_unlock_irqrestore(&bt->tx_lock, flags);
352
353 return 0;
354}
355
356static int mtk_btcvsd_read_from_bt(struct mtk_btcvsd_snd *bt,
357 enum bt_sco_packet_len packet_type,
358 unsigned int packet_length,
359 unsigned int packet_num,
360 unsigned int blk_size,
361 unsigned int control)
362{
363 unsigned int i;
364 int pv;
365 u8 *src;
366 unsigned int packet_buf_ofs;
367 unsigned long flags;
368 unsigned long connsys_addr_rx, ap_addr_rx;
369
370 connsys_addr_rx = *bt->bt_reg_pkt_r;
371 ap_addr_rx = (unsigned long)bt->bt_sram_bank2_base +
372 (connsys_addr_rx & 0xFFFF);
373
374 if (connsys_addr_rx == 0xdeadfeed) {
375 /* bt return 0xdeadfeed if read register during bt sleep */
376 dev_warn(bt->dev, "%s(), connsys_addr_rx == 0xdeadfeed",
377 __func__);
378 return -EIO;
379 }
380
381 src = (u8 *)ap_addr_rx;
382
383 mtk_btcvsd_snd_data_transfer(BT_SCO_DIRECT_BT2ARM, src,
384 bt->rx->temp_packet_buf, packet_length,
385 packet_num);
386
387 spin_lock_irqsave(&bt->rx_lock, flags);
388 for (i = 0; i < blk_size; i++) {
389 packet_buf_ofs = (bt->rx->packet_w & SCO_RX_PACKET_MASK) *
390 bt->rx->packet_size;
391 memcpy(bt->rx_packet_buf + packet_buf_ofs,
392 bt->rx->temp_packet_buf + (SCO_RX_PLC_SIZE * i),
393 SCO_RX_PLC_SIZE);
394 if ((control & btsco_packet_valid_mask[packet_type][i]) ==
395 btsco_packet_valid_mask[packet_type][i])
396 pv = 1;
397 else
398 pv = 0;
399
400 packet_buf_ofs += SCO_RX_PLC_SIZE;
401 memcpy(bt->rx_packet_buf + packet_buf_ofs, (void *)&pv,
402 SCO_CVSD_PACKET_VALID_SIZE);
403 bt->rx->packet_w++;
404 }
405 spin_unlock_irqrestore(&bt->rx_lock, flags);
406 return 0;
407}
408
409int mtk_btcvsd_write_to_bt(struct mtk_btcvsd_snd *bt,
410 enum bt_sco_packet_len packet_type,
411 unsigned int packet_length,
412 unsigned int packet_num,
413 unsigned int blk_size)
414{
415 unsigned int i;
416 unsigned long flags;
417 u8 *dst;
418 unsigned long connsys_addr_tx, ap_addr_tx;
419 bool new_ap_addr_tx = true;
420
421 connsys_addr_tx = *bt->bt_reg_pkt_w;
422 ap_addr_tx = (unsigned long)bt->bt_sram_bank2_base +
423 (connsys_addr_tx & 0xFFFF);
424
425 if (connsys_addr_tx == 0xdeadfeed) {
426 /* bt return 0xdeadfeed if read register during bt sleep */
427 dev_warn(bt->dev, "%s(), connsys_addr_tx == 0xdeadfeed\n",
428 __func__);
429 return -EIO;
430 }
431
432 spin_lock_irqsave(&bt->tx_lock, flags);
433 for (i = 0; i < blk_size; i++) {
434 memcpy(bt->tx->temp_packet_buf + (bt->tx->packet_size * i),
435 (bt->tx_packet_buf +
436 (bt->tx->packet_r % SCO_TX_PACKER_BUF_NUM) *
437 bt->tx->packet_size),
438 bt->tx->packet_size);
439
440 bt->tx->packet_r++;
441 }
442 spin_unlock_irqrestore(&bt->tx_lock, flags);
443
444 dst = (u8 *)ap_addr_tx;
445
446 if (!bt->tx->mute) {
447 mtk_btcvsd_snd_data_transfer(BT_SCO_DIRECT_ARM2BT,
448 bt->tx->temp_packet_buf, dst,
449 packet_length, packet_num);
450 }
451
452 /* store bt tx buffer sram info */
453 bt->tx->buffer_info.packet_length = packet_length;
454 bt->tx->buffer_info.packet_num = packet_num;
455 for (i = 0; i < bt->tx->buffer_info.num_valid_addr; i++) {
456 if (bt->tx->buffer_info.bt_sram_addr[i] == ap_addr_tx) {
457 new_ap_addr_tx = false;
458 break;
459 }
460 }
461 if (new_ap_addr_tx) {
462 unsigned int next_idx;
463
464 spin_lock_irqsave(&bt->tx_lock, flags);
465 bt->tx->buffer_info.num_valid_addr++;
466 next_idx = bt->tx->buffer_info.num_valid_addr - 1;
467 bt->tx->buffer_info.bt_sram_addr[next_idx] = ap_addr_tx;
468 spin_unlock_irqrestore(&bt->tx_lock, flags);
469 dev_info(bt->dev, "%s(), new ap_addr_tx = 0x%lx, num_valid_addr %d\n",
470 __func__, ap_addr_tx,
471 bt->tx->buffer_info.num_valid_addr);
472 }
473
474 if (bt->tx->mute)
475 btcvsd_tx_clean_buffer(bt);
476
477 return 0;
478}
479
480static irqreturn_t mtk_btcvsd_snd_irq_handler(int irq_id, void *dev)
481{
482 struct mtk_btcvsd_snd *bt = dev;
483 unsigned int packet_type, packet_num, packet_length;
484 unsigned int buf_cnt_tx, buf_cnt_rx, control;
485
486 if (bt->rx->state != BT_SCO_STATE_RUNNING &&
487 bt->rx->state != BT_SCO_STATE_ENDING &&
488 bt->tx->state != BT_SCO_STATE_RUNNING &&
489 bt->tx->state != BT_SCO_STATE_ENDING) {
490 dev_warn(bt->dev, "%s(), in idle state: rx->state: %d, tx->state: %d\n",
491 __func__, bt->rx->state, bt->tx->state);
492 goto irq_handler_exit;
493 }
494
495 control = *bt->bt_reg_ctl;
496 packet_type = (control >> 18) & 0x7;
497
498 if (((control >> 31) & 1) == 0) {
499 dev_warn(bt->dev, "%s(), ((control >> 31) & 1) == 0, control 0x%x\n",
500 __func__, control);
501 goto irq_handler_exit;
502 }
503
504 if (packet_type >= BT_SCO_CVSD_MAX) {
505 dev_warn(bt->dev, "%s(), invalid packet_type %u, exit\n",
506 __func__, packet_type);
507 goto irq_handler_exit;
508 }
509
510 packet_length = btsco_packet_info[packet_type][0];
511 packet_num = btsco_packet_info[packet_type][1];
512 buf_cnt_tx = btsco_packet_info[packet_type][2];
513 buf_cnt_rx = btsco_packet_info[packet_type][3];
514
515 if (bt->rx->state == BT_SCO_STATE_RUNNING ||
516 bt->rx->state == BT_SCO_STATE_ENDING) {
517 if (bt->rx->xrun) {
518 if (bt->rx->packet_w - bt->rx->packet_r <=
519 SCO_RX_PACKER_BUF_NUM - 2 * buf_cnt_rx) {
520 /*
521 * free space is larger then
522 * twice interrupt rx data size
523 */
524 bt->rx->xrun = 0;
525 dev_warn(bt->dev, "%s(), rx->xrun 0!\n",
526 __func__);
527 }
528 }
529
530 if (!bt->rx->xrun &&
531 (bt->rx->packet_w - bt->rx->packet_r <=
532 SCO_RX_PACKER_BUF_NUM - buf_cnt_rx)) {
533 mtk_btcvsd_read_from_bt(bt,
534 packet_type,
535 packet_length,
536 packet_num,
537 buf_cnt_rx,
538 control);
539 bt->rx->rw_cnt++;
540 } else {
541 bt->rx->xrun = 1;
542 dev_warn(bt->dev, "%s(), rx->xrun 1\n", __func__);
543 }
544 }
545
546 /* tx */
547 bt->tx->timeout = 0;
548 if ((bt->tx->state == BT_SCO_STATE_RUNNING ||
549 bt->tx->state == BT_SCO_STATE_ENDING) &&
550 bt->tx->trigger_start) {
551 if (bt->tx->xrun) {
552 /* prepared data is larger then twice
553 * interrupt tx data size
554 */
555 if (bt->tx->packet_w - bt->tx->packet_r >=
556 2 * buf_cnt_tx) {
557 bt->tx->xrun = 0;
558 dev_warn(bt->dev, "%s(), tx->xrun 0\n",
559 __func__);
560 }
561 }
562
563 if ((!bt->tx->xrun &&
564 (bt->tx->packet_w - bt->tx->packet_r >= buf_cnt_tx)) ||
565 bt->tx->state == BT_SCO_STATE_ENDING) {
566 mtk_btcvsd_write_to_bt(bt,
567 packet_type,
568 packet_length,
569 packet_num,
570 buf_cnt_tx);
571 bt->tx->rw_cnt++;
572 } else {
573 bt->tx->xrun = 1;
574 dev_warn(bt->dev, "%s(), tx->xrun 1\n", __func__);
575 }
576 }
577
578 *bt->bt_reg_ctl &= ~BT_CVSD_CLEAR;
579
580 if (bt->rx->state == BT_SCO_STATE_RUNNING ||
581 bt->rx->state == BT_SCO_STATE_ENDING) {
582 bt->rx->wait_flag = 1;
583 wake_up_interruptible(&bt->rx_wait);
584 snd_pcm_period_elapsed(bt->rx->substream);
585 }
586 if (bt->tx->state == BT_SCO_STATE_RUNNING ||
587 bt->tx->state == BT_SCO_STATE_ENDING) {
588 bt->tx->wait_flag = 1;
589 wake_up_interruptible(&bt->tx_wait);
590 snd_pcm_period_elapsed(bt->tx->substream);
591 }
592
593 return IRQ_HANDLED;
594irq_handler_exit:
595 *bt->bt_reg_ctl &= ~BT_CVSD_CLEAR;
596 return IRQ_HANDLED;
597}
598
599static int wait_for_bt_irq(struct mtk_btcvsd_snd *bt,
600 struct mtk_btcvsd_snd_stream *bt_stream)
601{
602 unsigned long long t1, t2;
603 /* one interrupt period = 22.5ms */
604 unsigned long long timeout_limit = 22500000;
605 int max_timeout_trial = 2;
606 int ret;
607
608 bt_stream->wait_flag = 0;
609
610 while (max_timeout_trial && !bt_stream->wait_flag) {
611 t1 = sched_clock();
612 if (bt_stream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
613 ret = wait_event_interruptible_timeout(bt->tx_wait,
614 bt_stream->wait_flag,
615 nsecs_to_jiffies(timeout_limit));
616 } else {
617 ret = wait_event_interruptible_timeout(bt->rx_wait,
618 bt_stream->wait_flag,
619 nsecs_to_jiffies(timeout_limit));
620 }
621
622 t2 = sched_clock();
623 t2 = t2 - t1; /* in ns (10^9) */
624
625 if (t2 > timeout_limit) {
626 dev_warn(bt->dev, "%s(), stream %d, timeout %llu, limit %llu, ret %d, flag %d\n",
627 __func__, bt_stream->stream,
628 t2, timeout_limit, ret,
629 bt_stream->wait_flag);
630 }
631
632 if (ret < 0) {
633 /*
634 * error, -ERESTARTSYS if it was interrupted by
635 * a signal
636 */
637 dev_warn(bt->dev, "%s(), stream %d, error, trial left %d\n",
638 __func__,
639 bt_stream->stream, max_timeout_trial);
640
641 bt_stream->timeout = 1;
642 return ret;
643 } else if (ret == 0) {
644 /* conidtion is false after timeout */
645 max_timeout_trial--;
646 dev_warn(bt->dev, "%s(), stream %d, error, timeout, condition is false, trial left %d\n",
647 __func__,
648 bt_stream->stream, max_timeout_trial);
649
650 if (max_timeout_trial <= 0) {
651 bt_stream->timeout = 1;
652 return -ETIME;
653 }
654 }
655 }
656
657 return 0;
658}
659
660ssize_t mtk_btcvsd_snd_read(struct mtk_btcvsd_snd *bt,
661 char __user *buf,
662 size_t count)
663{
664 ssize_t read_size = 0, read_count = 0, cur_read_idx, cont;
665 unsigned int cur_buf_ofs = 0;
666 unsigned long avail;
667 unsigned long flags;
668 unsigned int packet_size = bt->rx->packet_size;
669
670 while (count) {
671 spin_lock_irqsave(&bt->rx_lock, flags);
672 /* available data in RX packet buffer */
673 avail = (bt->rx->packet_w - bt->rx->packet_r) * packet_size;
674
675 cur_read_idx = (bt->rx->packet_r & SCO_RX_PACKET_MASK) *
676 packet_size;
677 spin_unlock_irqrestore(&bt->rx_lock, flags);
678
679 if (!avail) {
680 int ret = wait_for_bt_irq(bt, bt->rx);
681
682 if (ret)
683 return read_count;
684
685 continue;
686 }
687
688 /* count must be multiple of packet_size */
689 if (count % packet_size != 0 ||
690 avail % packet_size != 0) {
691 dev_warn(bt->dev, "%s(), count %zu or d %lu is not multiple of packet_size %dd\n",
692 __func__, count, avail, packet_size);
693
694 count -= count % packet_size;
695 avail -= avail % packet_size;
696 }
697
698 if (count > avail)
699 read_size = avail;
700 else
701 read_size = count;
702
703 /* calculate continue space */
704 cont = bt->rx->buf_size - cur_read_idx;
705 if (read_size > cont)
706 read_size = cont;
707
708 if (copy_to_user(buf + cur_buf_ofs,
709 bt->rx_packet_buf + cur_read_idx,
710 read_size)) {
711 dev_warn(bt->dev, "%s(), copy_to_user fail\n",
712 __func__);
713 return -EFAULT;
714 }
715
716 spin_lock_irqsave(&bt->rx_lock, flags);
717 bt->rx->packet_r += read_size / packet_size;
718 spin_unlock_irqrestore(&bt->rx_lock, flags);
719
720 read_count += read_size;
721 cur_buf_ofs += read_size;
722 count -= read_size;
723 }
724
725 /*
726 * save current timestamp & buffer time in times_tamp and
727 * buf_data_equivalent_time
728 */
729 bt->rx->time_stamp = sched_clock();
730 bt->rx->buf_data_equivalent_time =
731 (unsigned long long)(bt->rx->packet_w - bt->rx->packet_r) *
732 SCO_RX_PLC_SIZE * 16 * 1000 / 2 / 64;
733 bt->rx->buf_data_equivalent_time += read_count * SCO_RX_PLC_SIZE *
734 16 * 1000 / packet_size / 2 / 64;
735 /* return equivalent time(us) to data count */
736 bt->rx->buf_data_equivalent_time *= 1000;
737
738 return read_count;
739}
740
741ssize_t mtk_btcvsd_snd_write(struct mtk_btcvsd_snd *bt,
742 char __user *buf,
743 size_t count)
744{
745 int written_size = count, avail = 0, cur_write_idx, write_size, cont;
746 unsigned int cur_buf_ofs = 0;
747 unsigned long flags;
748 unsigned int packet_size = bt->tx->packet_size;
749
750 /*
751 * save current timestamp & buffer time in time_stamp and
752 * buf_data_equivalent_time
753 */
754 bt->tx->time_stamp = sched_clock();
755 bt->tx->buf_data_equivalent_time =
756 (unsigned long long)(bt->tx->packet_w - bt->tx->packet_r) *
757 packet_size * 16 * 1000 / 2 / 64;
758
759 /* return equivalent time(us) to data count */
760 bt->tx->buf_data_equivalent_time *= 1000;
761
762 while (count) {
763 spin_lock_irqsave(&bt->tx_lock, flags);
764 /* free space of TX packet buffer */
765 avail = bt->tx->buf_size -
766 (bt->tx->packet_w - bt->tx->packet_r) * packet_size;
767
768 cur_write_idx = (bt->tx->packet_w % SCO_TX_PACKER_BUF_NUM) *
769 packet_size;
770 spin_unlock_irqrestore(&bt->tx_lock, flags);
771
772 if (!avail) {
773 int ret = wait_for_bt_irq(bt, bt->rx);
774
775 if (ret)
776 return written_size;
777
778 continue;
779 }
780
781 /* count must be multiple of bt->tx->packet_size */
782 if (count % packet_size != 0 ||
783 avail % packet_size != 0) {
784 dev_warn(bt->dev, "%s(), count %zu or avail %d is not multiple of packet_size %d\n",
785 __func__, count, avail, packet_size);
786 count -= count % packet_size;
787 avail -= avail % packet_size;
788 }
789
790 if (count > avail)
791 write_size = avail;
792 else
793 write_size = count;
794
795 /* calculate continue space */
796 cont = bt->tx->buf_size - cur_write_idx;
797 if (write_size > cont)
798 write_size = cont;
799
800 if (copy_from_user(bt->tx_packet_buf +
801 cur_write_idx,
802 buf + cur_buf_ofs,
803 write_size)) {
804 dev_warn(bt->dev, "%s(), copy_from_user fail\n",
805 __func__);
806 return -EFAULT;
807 }
808
809 spin_lock_irqsave(&bt->tx_lock, flags);
810 bt->tx->packet_w += write_size / packet_size;
811 spin_unlock_irqrestore(&bt->tx_lock, flags);
812 cur_buf_ofs += write_size;
813 count -= write_size;
814 }
815
816 return written_size;
817}
818
819static struct mtk_btcvsd_snd_stream *get_bt_stream
820 (struct mtk_btcvsd_snd *bt, struct snd_pcm_substream *substream)
821{
822 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
823 return bt->tx;
824 else
825 return bt->rx;
826}
827
828/* pcm ops */
829static const struct snd_pcm_hardware mtk_btcvsd_hardware = {
830 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
831 SNDRV_PCM_INFO_RESUME),
832 .formats = SNDRV_PCM_FMTBIT_S16_LE,
833 .buffer_bytes_max = 24 * 1024,
834 .period_bytes_max = 24 * 1024,
835 .periods_min = 2,
836 .periods_max = 16,
837 .fifo_size = 0,
838};
839
840static int mtk_pcm_btcvsd_open(struct snd_pcm_substream *substream)
841{
842 struct snd_soc_pcm_runtime *rtd = substream->private_data;
843 struct snd_soc_component *component =
844 snd_soc_rtdcom_lookup(rtd, BTCVSD_SND_NAME);
845 struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(component);
846 int ret;
847
848 dev_dbg(bt->dev, "%s(), stream %d, substream %p\n",
849 __func__, substream->stream, substream);
850
851 snd_soc_set_runtime_hwparams(substream, &mtk_btcvsd_hardware);
852
853 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
854 ret = mtk_btcvsd_snd_tx_init(bt);
855 bt->tx->substream = substream;
856 } else {
857 ret = mtk_btcvsd_snd_rx_init(bt);
858 bt->rx->substream = substream;
859 }
860
861 return ret;
862}
863
864static int mtk_pcm_btcvsd_close(struct snd_pcm_substream *substream)
865{
866 struct snd_soc_pcm_runtime *rtd = substream->private_data;
867 struct snd_soc_component *component =
868 snd_soc_rtdcom_lookup(rtd, BTCVSD_SND_NAME);
869 struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(component);
870 struct mtk_btcvsd_snd_stream *bt_stream = get_bt_stream(bt, substream);
871
872 dev_dbg(bt->dev, "%s(), stream %d\n", __func__, substream->stream);
873
874 mtk_btcvsd_snd_set_state(bt, bt_stream, BT_SCO_STATE_IDLE);
875 bt_stream->substream = NULL;
876 return 0;
877}
878
879static int mtk_pcm_btcvsd_hw_params(struct snd_pcm_substream *substream,
880 struct snd_pcm_hw_params *hw_params)
881{
882 struct snd_soc_pcm_runtime *rtd = substream->private_data;
883 struct snd_soc_component *component =
884 snd_soc_rtdcom_lookup(rtd, BTCVSD_SND_NAME);
885 struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(component);
886
887 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK &&
888 params_buffer_bytes(hw_params) % bt->tx->packet_size != 0) {
889 dev_warn(bt->dev, "%s(), error, buffer size %d not valid\n",
890 __func__,
891 params_buffer_bytes(hw_params));
892 return -EINVAL;
893 }
894
895 substream->runtime->dma_bytes = params_buffer_bytes(hw_params);
896 return 0;
897}
898
899static int mtk_pcm_btcvsd_hw_free(struct snd_pcm_substream *substream)
900{
901 struct snd_soc_pcm_runtime *rtd = substream->private_data;
902 struct snd_soc_component *component =
903 snd_soc_rtdcom_lookup(rtd, BTCVSD_SND_NAME);
904 struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(component);
905
906 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
907 btcvsd_tx_clean_buffer(bt);
908
909 return 0;
910}
911
912static int mtk_pcm_btcvsd_prepare(struct snd_pcm_substream *substream)
913{
914 struct snd_soc_pcm_runtime *rtd = substream->private_data;
915 struct snd_soc_component *component =
916 snd_soc_rtdcom_lookup(rtd, BTCVSD_SND_NAME);
917 struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(component);
918 struct mtk_btcvsd_snd_stream *bt_stream = get_bt_stream(bt, substream);
919
920 dev_dbg(bt->dev, "%s(), stream %d\n", __func__, substream->stream);
921
922 mtk_btcvsd_snd_set_state(bt, bt_stream, BT_SCO_STATE_RUNNING);
923 return 0;
924}
925
926static int mtk_pcm_btcvsd_trigger(struct snd_pcm_substream *substream, int cmd)
927{
928 struct snd_soc_pcm_runtime *rtd = substream->private_data;
929 struct snd_soc_component *component =
930 snd_soc_rtdcom_lookup(rtd, BTCVSD_SND_NAME);
931 struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(component);
932 struct mtk_btcvsd_snd_stream *bt_stream = get_bt_stream(bt, substream);
933 int stream = substream->stream;
934 int hw_packet_ptr;
935
936 dev_dbg(bt->dev, "%s(), stream %d, cmd %d\n",
937 __func__, substream->stream, cmd);
938
939 switch (cmd) {
940 case SNDRV_PCM_TRIGGER_START:
941 case SNDRV_PCM_TRIGGER_RESUME:
942 hw_packet_ptr = stream == SNDRV_PCM_STREAM_PLAYBACK ?
943 bt_stream->packet_r : bt_stream->packet_w;
944 bt_stream->prev_packet_idx = hw_packet_ptr;
945 bt_stream->prev_frame = 0;
946 bt_stream->trigger_start = 1;
947 return 0;
948 case SNDRV_PCM_TRIGGER_STOP:
949 case SNDRV_PCM_TRIGGER_SUSPEND:
950 bt_stream->trigger_start = 0;
951 mtk_btcvsd_snd_set_state(bt, bt_stream, BT_SCO_STATE_ENDING);
952 return 0;
953 default:
954 return -EINVAL;
955 }
956}
957
958static snd_pcm_uframes_t mtk_pcm_btcvsd_pointer
959 (struct snd_pcm_substream *substream)
960{
961 struct snd_soc_pcm_runtime *rtd = substream->private_data;
962 struct snd_soc_component *component =
963 snd_soc_rtdcom_lookup(rtd, BTCVSD_SND_NAME);
964 struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(component);
965 struct mtk_btcvsd_snd_stream *bt_stream;
966 snd_pcm_uframes_t frame = 0;
967 int byte = 0;
968 int hw_packet_ptr;
969 int packet_diff;
970 spinlock_t *lock; /* spinlock for bt stream control */
971 unsigned long flags;
972
973 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
974 lock = &bt->tx_lock;
975 bt_stream = bt->tx;
976 } else {
977 lock = &bt->rx_lock;
978 bt_stream = bt->rx;
979 }
980
981 spin_lock_irqsave(lock, flags);
982 hw_packet_ptr = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
983 bt->tx->packet_r : bt->rx->packet_w;
984
985 /* get packet diff from last time */
986 if (hw_packet_ptr >= bt_stream->prev_packet_idx) {
987 packet_diff = hw_packet_ptr - bt_stream->prev_packet_idx;
988 } else {
989 /* integer overflow */
990 packet_diff = (INT_MAX - bt_stream->prev_packet_idx) +
991 (hw_packet_ptr - INT_MIN) + 1;
992 }
993 bt_stream->prev_packet_idx = hw_packet_ptr;
994
995 /* increased bytes */
996 byte = packet_diff * bt_stream->packet_size;
997
998 frame = btcvsd_bytes_to_frame(substream, byte);
999 frame += bt_stream->prev_frame;
1000 frame %= substream->runtime->buffer_size;
1001
1002 bt_stream->prev_frame = frame;
1003
1004 spin_unlock_irqrestore(lock, flags);
1005
1006 return frame;
1007}
1008
1009static int mtk_pcm_btcvsd_copy(struct snd_pcm_substream *substream,
1010 int channel, unsigned long pos,
1011 void __user *buf, unsigned long count)
1012{
1013 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1014 struct snd_soc_component *component =
1015 snd_soc_rtdcom_lookup(rtd, BTCVSD_SND_NAME);
1016 struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(component);
1017
1018 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1019 mtk_btcvsd_snd_write(bt, buf, count);
1020 else
1021 mtk_btcvsd_snd_read(bt, buf, count);
1022
1023 return 0;
1024}
1025
1026static struct snd_pcm_ops mtk_btcvsd_ops = {
1027 .open = mtk_pcm_btcvsd_open,
1028 .close = mtk_pcm_btcvsd_close,
1029 .ioctl = snd_pcm_lib_ioctl,
1030 .hw_params = mtk_pcm_btcvsd_hw_params,
1031 .hw_free = mtk_pcm_btcvsd_hw_free,
1032 .prepare = mtk_pcm_btcvsd_prepare,
1033 .trigger = mtk_pcm_btcvsd_trigger,
1034 .pointer = mtk_pcm_btcvsd_pointer,
1035 .copy_user = mtk_pcm_btcvsd_copy,
1036};
1037
1038/* kcontrol */
1039static const char *const btsco_band_str[] = {"NB", "WB"};
1040
1041static const struct soc_enum btcvsd_enum[] = {
1042 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(btsco_band_str), btsco_band_str),
1043};
1044
1045static int btcvsd_band_get(struct snd_kcontrol *kcontrol,
1046 struct snd_ctl_elem_value *ucontrol)
1047{
1048 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
1049 struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
1050
1051 ucontrol->value.integer.value[0] = bt->band;
1052 return 0;
1053}
1054
1055static int btcvsd_band_set(struct snd_kcontrol *kcontrol,
1056 struct snd_ctl_elem_value *ucontrol)
1057{
1058 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
1059 struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
1060 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1061
1062 if (ucontrol->value.enumerated.item[0] >= e->items)
1063 return -EINVAL;
1064
1065 bt->band = ucontrol->value.integer.value[0];
1066 dev_dbg(bt->dev, "%s(), band %d\n", __func__, bt->band);
1067 return 0;
1068}
1069
1070static int btcvsd_tx_mute_get(struct snd_kcontrol *kcontrol,
1071 struct snd_ctl_elem_value *ucontrol)
1072{
1073 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
1074 struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
1075
1076 if (!bt->tx) {
1077 ucontrol->value.integer.value[0] = 0;
1078 return 0;
1079 }
1080
1081 ucontrol->value.integer.value[0] = bt->tx->mute;
1082 return 0;
1083}
1084
1085static int btcvsd_tx_mute_set(struct snd_kcontrol *kcontrol,
1086 struct snd_ctl_elem_value *ucontrol)
1087{
1088 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
1089 struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
1090
1091 if (!bt->tx)
1092 return 0;
1093
1094 bt->tx->mute = ucontrol->value.integer.value[0];
1095 return 0;
1096}
1097
1098static int btcvsd_rx_irq_received_get(struct snd_kcontrol *kcontrol,
1099 struct snd_ctl_elem_value *ucontrol)
1100{
1101 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
1102 struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
1103
1104 if (!bt->rx)
1105 return 0;
1106
1107 ucontrol->value.integer.value[0] = bt->rx->rw_cnt ? 1 : 0;
1108 return 0;
1109}
1110
1111static int btcvsd_rx_timeout_get(struct snd_kcontrol *kcontrol,
1112 struct snd_ctl_elem_value *ucontrol)
1113{
1114 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
1115 struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
1116
1117 if (!bt->rx)
1118 return 0;
1119
1120 ucontrol->value.integer.value[0] = bt->rx->timeout;
1121 bt->rx->timeout = 0;
1122 return 0;
1123}
1124
1125static int btcvsd_rx_timestamp_get(struct snd_kcontrol *kcontrol,
1126 unsigned int __user *data, unsigned int size)
1127{
1128 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
1129 struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
1130 int ret = 0;
1131 struct mtk_btcvsd_snd_time_buffer_info time_buffer_info_rx;
1132
1133 if (size > sizeof(struct mtk_btcvsd_snd_time_buffer_info))
1134 return -EINVAL;
1135
1136 get_rx_time_stamp(bt, &time_buffer_info_rx);
1137
1138 dev_dbg(bt->dev, "%s(), time_stamp_us %llu, data_count_equi_time %llu",
1139 __func__,
1140 time_buffer_info_rx.time_stamp_us,
1141 time_buffer_info_rx.data_count_equi_time);
1142
1143 if (copy_to_user(data, &time_buffer_info_rx,
1144 sizeof(struct mtk_btcvsd_snd_time_buffer_info))) {
1145 dev_warn(bt->dev, "%s(), copy_to_user fail", __func__);
1146 ret = -EFAULT;
1147 }
1148
1149 return ret;
1150}
1151
1152static int btcvsd_tx_irq_received_get(struct snd_kcontrol *kcontrol,
1153 struct snd_ctl_elem_value *ucontrol)
1154{
1155 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
1156 struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
1157
1158 if (!bt->tx)
1159 return 0;
1160
1161 ucontrol->value.integer.value[0] = bt->tx->rw_cnt ? 1 : 0;
1162 return 0;
1163}
1164
1165static int btcvsd_tx_timeout_get(struct snd_kcontrol *kcontrol,
1166 struct snd_ctl_elem_value *ucontrol)
1167{
1168 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
1169 struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
1170
1171 ucontrol->value.integer.value[0] = bt->tx->timeout;
1172 return 0;
1173}
1174
1175static int btcvsd_tx_timestamp_get(struct snd_kcontrol *kcontrol,
1176 unsigned int __user *data, unsigned int size)
1177{
1178 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
1179 struct mtk_btcvsd_snd *bt = snd_soc_component_get_drvdata(cmpnt);
1180 int ret = 0;
1181 struct mtk_btcvsd_snd_time_buffer_info time_buffer_info_tx;
1182
1183 if (size > sizeof(struct mtk_btcvsd_snd_time_buffer_info))
1184 return -EINVAL;
1185
1186 get_tx_time_stamp(bt, &time_buffer_info_tx);
1187
1188 dev_dbg(bt->dev, "%s(), time_stamp_us %llu, data_count_equi_time %llu",
1189 __func__,
1190 time_buffer_info_tx.time_stamp_us,
1191 time_buffer_info_tx.data_count_equi_time);
1192
1193 if (copy_to_user(data, &time_buffer_info_tx,
1194 sizeof(struct mtk_btcvsd_snd_time_buffer_info))) {
1195 dev_warn(bt->dev, "%s(), copy_to_user fail", __func__);
1196 ret = -EFAULT;
1197 }
1198
1199 return ret;
1200}
1201
1202static const struct snd_kcontrol_new mtk_btcvsd_snd_controls[] = {
1203 SOC_ENUM_EXT("BTCVSD Band", btcvsd_enum[0],
1204 btcvsd_band_get, btcvsd_band_set),
1205 SOC_SINGLE_BOOL_EXT("BTCVSD Tx Mute Switch", 0,
1206 btcvsd_tx_mute_get, btcvsd_tx_mute_set),
1207 SOC_SINGLE_BOOL_EXT("BTCVSD Tx Irq Received Switch", 0,
1208 btcvsd_tx_irq_received_get, NULL),
1209 SOC_SINGLE_BOOL_EXT("BTCVSD Tx Timeout Switch", 0,
1210 btcvsd_tx_timeout_get, NULL),
1211 SOC_SINGLE_BOOL_EXT("BTCVSD Rx Irq Received Switch", 0,
1212 btcvsd_rx_irq_received_get, NULL),
1213 SOC_SINGLE_BOOL_EXT("BTCVSD Rx Timeout Switch", 0,
1214 btcvsd_rx_timeout_get, NULL),
1215 SND_SOC_BYTES_TLV("BTCVSD Rx Timestamp",
1216 sizeof(struct mtk_btcvsd_snd_time_buffer_info),
1217 btcvsd_rx_timestamp_get, NULL),
1218 SND_SOC_BYTES_TLV("BTCVSD Tx Timestamp",
1219 sizeof(struct mtk_btcvsd_snd_time_buffer_info),
1220 btcvsd_tx_timestamp_get, NULL),
1221};
1222
1223static int mtk_btcvsd_snd_component_probe(struct snd_soc_component *component)
1224{
1225 return snd_soc_add_component_controls(component,
1226 mtk_btcvsd_snd_controls,
1227 ARRAY_SIZE(mtk_btcvsd_snd_controls));
1228}
1229
1230static const struct snd_soc_component_driver mtk_btcvsd_snd_platform = {
1231 .name = BTCVSD_SND_NAME,
1232 .ops = &mtk_btcvsd_ops,
1233 .probe = mtk_btcvsd_snd_component_probe,
1234};
1235
1236static int mtk_btcvsd_snd_probe(struct platform_device *pdev)
1237{
1238 int ret = 0;
1239 int irq_id;
1240 u32 offset[5] = {0, 0, 0, 0, 0};
1241 struct mtk_btcvsd_snd *btcvsd;
1242 struct device *dev = &pdev->dev;
1243
1244 /* init btcvsd private data */
1245 btcvsd = devm_kzalloc(dev, sizeof(*btcvsd), GFP_KERNEL);
1246 if (!btcvsd)
1247 return -ENOMEM;
1248 platform_set_drvdata(pdev, btcvsd);
1249 btcvsd->dev = dev;
1250
1251 /* init tx/rx */
1252 btcvsd->rx = devm_kzalloc(btcvsd->dev, sizeof(*btcvsd->rx), GFP_KERNEL);
1253 if (!btcvsd->rx)
1254 return -ENOMEM;
1255
1256 btcvsd->tx = devm_kzalloc(btcvsd->dev, sizeof(*btcvsd->tx), GFP_KERNEL);
1257 if (!btcvsd->tx)
1258 return -ENOMEM;
1259
1260 spin_lock_init(&btcvsd->tx_lock);
1261 spin_lock_init(&btcvsd->rx_lock);
1262
1263 init_waitqueue_head(&btcvsd->tx_wait);
1264 init_waitqueue_head(&btcvsd->rx_wait);
1265
1266 mtk_btcvsd_snd_tx_init(btcvsd);
1267 mtk_btcvsd_snd_rx_init(btcvsd);
1268
1269 /* irq */
1270 irq_id = platform_get_irq(pdev, 0);
1271 if (irq_id <= 0) {
1272 dev_err(dev, "%s no irq found\n", dev->of_node->name);
1273 return irq_id < 0 ? irq_id : -ENXIO;
1274 }
1275
1276 ret = devm_request_irq(dev, irq_id, mtk_btcvsd_snd_irq_handler,
1277 IRQF_TRIGGER_LOW, "BTCVSD_ISR_Handle",
1278 (void *)btcvsd);
1279 if (ret) {
1280 dev_err(dev, "could not request_irq for BTCVSD_ISR_Handle\n");
1281 return ret;
1282 }
1283
1284 btcvsd->irq_id = irq_id;
1285
1286 /* iomap */
1287 btcvsd->bt_pkv_base = of_iomap(dev->of_node, 0);
1288 if (!btcvsd->bt_pkv_base) {
1289 dev_err(dev, "iomap bt_pkv_base fail\n");
1290 return -EIO;
1291 }
1292
1293 btcvsd->bt_sram_bank2_base = of_iomap(dev->of_node, 1);
1294 if (!btcvsd->bt_sram_bank2_base) {
1295 dev_err(dev, "iomap bt_sram_bank2_base fail\n");
1296 return -EIO;
1297 }
1298
1299 btcvsd->infra = syscon_regmap_lookup_by_phandle(dev->of_node,
1300 "mediatek,infracfg");
1301 if (IS_ERR(btcvsd->infra)) {
1302 dev_err(dev, "cannot find infra controller: %ld\n",
1303 PTR_ERR(btcvsd->infra));
1304 return PTR_ERR(btcvsd->infra);
1305 }
1306
1307 /* get offset */
1308 ret = of_property_read_u32_array(dev->of_node, "mediatek,offset",
1309 offset,
1310 ARRAY_SIZE(offset));
1311 if (ret) {
1312 dev_warn(dev, "%s(), get offset fail, ret %d\n", __func__, ret);
1313 return ret;
1314 }
1315 btcvsd->infra_misc_offset = offset[0];
1316 btcvsd->conn_bt_cvsd_mask = offset[1];
1317 btcvsd->cvsd_mcu_read_offset = offset[2];
1318 btcvsd->cvsd_mcu_write_offset = offset[3];
1319 btcvsd->cvsd_packet_indicator = offset[4];
1320
1321 btcvsd->bt_reg_pkt_r = btcvsd->bt_pkv_base +
1322 btcvsd->cvsd_mcu_read_offset;
1323 btcvsd->bt_reg_pkt_w = btcvsd->bt_pkv_base +
1324 btcvsd->cvsd_mcu_write_offset;
1325 btcvsd->bt_reg_ctl = btcvsd->bt_pkv_base +
1326 btcvsd->cvsd_packet_indicator;
1327
1328 /* init state */
1329 mtk_btcvsd_snd_set_state(btcvsd, btcvsd->tx, BT_SCO_STATE_IDLE);
1330 mtk_btcvsd_snd_set_state(btcvsd, btcvsd->rx, BT_SCO_STATE_IDLE);
1331
1332 return devm_snd_soc_register_component(dev, &mtk_btcvsd_snd_platform,
1333 NULL, 0);
1334}
1335
1336static int mtk_btcvsd_snd_remove(struct platform_device *pdev)
1337{
1338 struct mtk_btcvsd_snd *btcvsd = dev_get_drvdata(&pdev->dev);
1339
1340 iounmap(btcvsd->bt_pkv_base);
1341 iounmap(btcvsd->bt_sram_bank2_base);
1342 return 0;
1343}
1344
1345static const struct of_device_id mtk_btcvsd_snd_dt_match[] = {
1346 { .compatible = "mediatek,mtk-btcvsd-snd", },
1347 {},
1348};
1349MODULE_DEVICE_TABLE(of, mtk_btcvsd_snd_dt_match);
1350
1351static struct platform_driver mtk_btcvsd_snd_driver = {
1352 .driver = {
1353 .name = "mtk-btcvsd-snd",
1354 .of_match_table = mtk_btcvsd_snd_dt_match,
1355 },
1356 .probe = mtk_btcvsd_snd_probe,
1357 .remove = mtk_btcvsd_snd_remove,
1358};
1359
1360module_platform_driver(mtk_btcvsd_snd_driver);
1361
1362MODULE_DESCRIPTION("Mediatek ALSA BT SCO CVSD/MSBC Driver");
1363MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
1364MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/mediatek/mt8183/Makefile b/sound/soc/mediatek/mt8183/Makefile
new file mode 100644
index 000000000000..f3ee6ac98fe8
--- /dev/null
+++ b/sound/soc/mediatek/mt8183/Makefile
@@ -0,0 +1,13 @@
1# SPDX-License-Identifier: GPL-2.0
2
3# platform driver
4snd-soc-mt8183-afe-objs := \
5 mt8183-afe-pcm.o \
6 mt8183-afe-clk.o \
7 mt8183-dai-i2s.o \
8 mt8183-dai-tdm.o \
9 mt8183-dai-pcm.o \
10 mt8183-dai-hostless.o \
11 mt8183-dai-adda.o
12
13obj-$(CONFIG_SND_SOC_MT8183) += snd-soc-mt8183-afe.o
diff --git a/sound/soc/mediatek/mt8183/mt8183-afe-clk.c b/sound/soc/mediatek/mt8183/mt8183-afe-clk.c
new file mode 100644
index 000000000000..f523ad103acc
--- /dev/null
+++ b/sound/soc/mediatek/mt8183/mt8183-afe-clk.c
@@ -0,0 +1,611 @@
1// SPDX-License-Identifier: GPL-2.0
2//
3// mt8183-afe-clk.c -- Mediatek 8183 afe clock ctrl
4//
5// Copyright (c) 2018 MediaTek Inc.
6// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7
8#include <linux/clk.h>
9
10#include "mt8183-afe-common.h"
11#include "mt8183-afe-clk.h"
12#include "mt8183-reg.h"
13
14enum {
15 CLK_AFE = 0,
16 CLK_TML,
17 CLK_APLL22M,
18 CLK_APLL24M,
19 CLK_APLL1_TUNER,
20 CLK_APLL2_TUNER,
21 CLK_I2S1_BCLK_SW,
22 CLK_I2S2_BCLK_SW,
23 CLK_I2S3_BCLK_SW,
24 CLK_I2S4_BCLK_SW,
25 CLK_INFRA_SYS_AUDIO,
26 CLK_MUX_AUDIO,
27 CLK_MUX_AUDIOINTBUS,
28 CLK_TOP_SYSPLL_D2_D4,
29 /* apll related mux */
30 CLK_TOP_MUX_AUD_1,
31 CLK_TOP_APLL1_CK,
32 CLK_TOP_MUX_AUD_2,
33 CLK_TOP_APLL2_CK,
34 CLK_TOP_MUX_AUD_ENG1,
35 CLK_TOP_APLL1_D8,
36 CLK_TOP_MUX_AUD_ENG2,
37 CLK_TOP_APLL2_D8,
38 CLK_TOP_I2S0_M_SEL,
39 CLK_TOP_I2S1_M_SEL,
40 CLK_TOP_I2S2_M_SEL,
41 CLK_TOP_I2S3_M_SEL,
42 CLK_TOP_I2S4_M_SEL,
43 CLK_TOP_I2S5_M_SEL,
44 CLK_TOP_APLL12_DIV0,
45 CLK_TOP_APLL12_DIV1,
46 CLK_TOP_APLL12_DIV2,
47 CLK_TOP_APLL12_DIV3,
48 CLK_TOP_APLL12_DIV4,
49 CLK_TOP_APLL12_DIVB,
50 CLK_CLK26M,
51 CLK_NUM
52};
53
54static const char *aud_clks[CLK_NUM] = {
55 [CLK_AFE] = "aud_afe_clk",
56 [CLK_TML] = "aud_tml_clk",
57 [CLK_APLL22M] = "aud_apll22m_clk",
58 [CLK_APLL24M] = "aud_apll24m_clk",
59 [CLK_APLL1_TUNER] = "aud_apll1_tuner_clk",
60 [CLK_APLL2_TUNER] = "aud_apll2_tuner_clk",
61 [CLK_I2S1_BCLK_SW] = "aud_i2s1_bclk_sw",
62 [CLK_I2S2_BCLK_SW] = "aud_i2s2_bclk_sw",
63 [CLK_I2S3_BCLK_SW] = "aud_i2s3_bclk_sw",
64 [CLK_I2S4_BCLK_SW] = "aud_i2s4_bclk_sw",
65 [CLK_INFRA_SYS_AUDIO] = "aud_infra_clk",
66 [CLK_MUX_AUDIO] = "top_mux_audio",
67 [CLK_MUX_AUDIOINTBUS] = "top_mux_aud_intbus",
68 [CLK_TOP_SYSPLL_D2_D4] = "top_syspll_d2_d4",
69 [CLK_TOP_MUX_AUD_1] = "top_mux_aud_1",
70 [CLK_TOP_APLL1_CK] = "top_apll1_ck",
71 [CLK_TOP_MUX_AUD_2] = "top_mux_aud_2",
72 [CLK_TOP_APLL2_CK] = "top_apll2_ck",
73 [CLK_TOP_MUX_AUD_ENG1] = "top_mux_aud_eng1",
74 [CLK_TOP_APLL1_D8] = "top_apll1_d8",
75 [CLK_TOP_MUX_AUD_ENG2] = "top_mux_aud_eng2",
76 [CLK_TOP_APLL2_D8] = "top_apll2_d8",
77 [CLK_TOP_I2S0_M_SEL] = "top_i2s0_m_sel",
78 [CLK_TOP_I2S1_M_SEL] = "top_i2s1_m_sel",
79 [CLK_TOP_I2S2_M_SEL] = "top_i2s2_m_sel",
80 [CLK_TOP_I2S3_M_SEL] = "top_i2s3_m_sel",
81 [CLK_TOP_I2S4_M_SEL] = "top_i2s4_m_sel",
82 [CLK_TOP_I2S5_M_SEL] = "top_i2s5_m_sel",
83 [CLK_TOP_APLL12_DIV0] = "top_apll12_div0",
84 [CLK_TOP_APLL12_DIV1] = "top_apll12_div1",
85 [CLK_TOP_APLL12_DIV2] = "top_apll12_div2",
86 [CLK_TOP_APLL12_DIV3] = "top_apll12_div3",
87 [CLK_TOP_APLL12_DIV4] = "top_apll12_div4",
88 [CLK_TOP_APLL12_DIVB] = "top_apll12_divb",
89 [CLK_CLK26M] = "top_clk26m_clk",
90};
91
92int mt8183_init_clock(struct mtk_base_afe *afe)
93{
94 struct mt8183_afe_private *afe_priv = afe->platform_priv;
95 int i;
96
97 afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
98 GFP_KERNEL);
99 if (!afe_priv->clk)
100 return -ENOMEM;
101
102 for (i = 0; i < CLK_NUM; i++) {
103 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
104 if (IS_ERR(afe_priv->clk[i])) {
105 dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n",
106 __func__, aud_clks[i],
107 PTR_ERR(afe_priv->clk[i]));
108 return PTR_ERR(afe_priv->clk[i]);
109 }
110 }
111
112 return 0;
113}
114
115int mt8183_afe_enable_clock(struct mtk_base_afe *afe)
116{
117 struct mt8183_afe_private *afe_priv = afe->platform_priv;
118 int ret;
119
120 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
121 if (ret) {
122 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
123 __func__, aud_clks[CLK_INFRA_SYS_AUDIO], ret);
124 goto CLK_INFRA_SYS_AUDIO_ERR;
125 }
126
127 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]);
128 if (ret) {
129 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
130 __func__, aud_clks[CLK_MUX_AUDIO], ret);
131 goto CLK_MUX_AUDIO_ERR;
132 }
133
134 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO],
135 afe_priv->clk[CLK_CLK26M]);
136 if (ret) {
137 dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
138 __func__, aud_clks[CLK_MUX_AUDIO],
139 aud_clks[CLK_CLK26M], ret);
140 goto CLK_MUX_AUDIO_ERR;
141 }
142
143 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
144 if (ret) {
145 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
146 __func__, aud_clks[CLK_MUX_AUDIOINTBUS], ret);
147 goto CLK_MUX_AUDIO_INTBUS_ERR;
148 }
149
150 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS],
151 afe_priv->clk[CLK_TOP_SYSPLL_D2_D4]);
152 if (ret) {
153 dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
154 __func__, aud_clks[CLK_MUX_AUDIOINTBUS],
155 aud_clks[CLK_TOP_SYSPLL_D2_D4], ret);
156 goto CLK_MUX_AUDIO_INTBUS_ERR;
157 }
158
159 ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]);
160 if (ret) {
161 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
162 __func__, aud_clks[CLK_AFE], ret);
163 goto CLK_AFE_ERR;
164 }
165
166 ret = clk_prepare_enable(afe_priv->clk[CLK_I2S1_BCLK_SW]);
167 if (ret) {
168 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
169 __func__, aud_clks[CLK_I2S1_BCLK_SW], ret);
170 goto CLK_I2S1_BCLK_SW_ERR;
171 }
172
173 ret = clk_prepare_enable(afe_priv->clk[CLK_I2S2_BCLK_SW]);
174 if (ret) {
175 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
176 __func__, aud_clks[CLK_I2S2_BCLK_SW], ret);
177 goto CLK_I2S2_BCLK_SW_ERR;
178 }
179
180 ret = clk_prepare_enable(afe_priv->clk[CLK_I2S3_BCLK_SW]);
181 if (ret) {
182 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
183 __func__, aud_clks[CLK_I2S3_BCLK_SW], ret);
184 goto CLK_I2S3_BCLK_SW_ERR;
185 }
186
187 ret = clk_prepare_enable(afe_priv->clk[CLK_I2S4_BCLK_SW]);
188 if (ret) {
189 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
190 __func__, aud_clks[CLK_I2S4_BCLK_SW], ret);
191 goto CLK_I2S4_BCLK_SW_ERR;
192 }
193
194 return 0;
195
196CLK_I2S4_BCLK_SW_ERR:
197 clk_disable_unprepare(afe_priv->clk[CLK_I2S3_BCLK_SW]);
198CLK_I2S3_BCLK_SW_ERR:
199 clk_disable_unprepare(afe_priv->clk[CLK_I2S2_BCLK_SW]);
200CLK_I2S2_BCLK_SW_ERR:
201 clk_disable_unprepare(afe_priv->clk[CLK_I2S1_BCLK_SW]);
202CLK_I2S1_BCLK_SW_ERR:
203 clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
204CLK_AFE_ERR:
205 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
206CLK_MUX_AUDIO_INTBUS_ERR:
207 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
208CLK_MUX_AUDIO_ERR:
209 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
210CLK_INFRA_SYS_AUDIO_ERR:
211 return ret;
212}
213
214int mt8183_afe_disable_clock(struct mtk_base_afe *afe)
215{
216 struct mt8183_afe_private *afe_priv = afe->platform_priv;
217
218 clk_disable_unprepare(afe_priv->clk[CLK_I2S4_BCLK_SW]);
219 clk_disable_unprepare(afe_priv->clk[CLK_I2S3_BCLK_SW]);
220 clk_disable_unprepare(afe_priv->clk[CLK_I2S2_BCLK_SW]);
221 clk_disable_unprepare(afe_priv->clk[CLK_I2S1_BCLK_SW]);
222 clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
223 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
224 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
225 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
226
227 return 0;
228}
229
230/* apll */
231static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
232{
233 struct mt8183_afe_private *afe_priv = afe->platform_priv;
234 int ret;
235
236 if (enable) {
237 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
238 if (ret) {
239 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
240 __func__, aud_clks[CLK_TOP_MUX_AUD_1], ret);
241 goto ERR_ENABLE_CLK_TOP_MUX_AUD_1;
242 }
243 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
244 afe_priv->clk[CLK_TOP_APLL1_CK]);
245 if (ret) {
246 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
247 __func__, aud_clks[CLK_TOP_MUX_AUD_1],
248 aud_clks[CLK_TOP_APLL1_CK], ret);
249 goto ERR_SELECT_CLK_TOP_MUX_AUD_1;
250 }
251
252 /* 180.6336 / 8 = 22.5792MHz */
253 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
254 if (ret) {
255 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
256 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1], ret);
257 goto ERR_ENABLE_CLK_TOP_MUX_AUD_ENG1;
258 }
259 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
260 afe_priv->clk[CLK_TOP_APLL1_D8]);
261 if (ret) {
262 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
263 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
264 aud_clks[CLK_TOP_APLL1_D8], ret);
265 goto ERR_SELECT_CLK_TOP_MUX_AUD_ENG1;
266 }
267 } else {
268 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
269 afe_priv->clk[CLK_CLK26M]);
270 if (ret) {
271 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
272 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG1],
273 aud_clks[CLK_CLK26M], ret);
274 goto EXIT;
275 }
276 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
277
278 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
279 afe_priv->clk[CLK_CLK26M]);
280 if (ret) {
281 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
282 __func__, aud_clks[CLK_TOP_MUX_AUD_1],
283 aud_clks[CLK_CLK26M], ret);
284 goto EXIT;
285 }
286 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
287 }
288
289 return 0;
290
291ERR_SELECT_CLK_TOP_MUX_AUD_ENG1:
292 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
293 afe_priv->clk[CLK_CLK26M]);
294 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
295ERR_ENABLE_CLK_TOP_MUX_AUD_ENG1:
296ERR_SELECT_CLK_TOP_MUX_AUD_1:
297 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
298 afe_priv->clk[CLK_CLK26M]);
299 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
300ERR_ENABLE_CLK_TOP_MUX_AUD_1:
301EXIT:
302 return ret;
303}
304
305static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
306{
307 struct mt8183_afe_private *afe_priv = afe->platform_priv;
308 int ret;
309
310 if (enable) {
311 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
312 if (ret) {
313 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
314 __func__, aud_clks[CLK_TOP_MUX_AUD_2], ret);
315 goto ERR_ENABLE_CLK_TOP_MUX_AUD_2;
316 }
317 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
318 afe_priv->clk[CLK_TOP_APLL2_CK]);
319 if (ret) {
320 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
321 __func__, aud_clks[CLK_TOP_MUX_AUD_2],
322 aud_clks[CLK_TOP_APLL2_CK], ret);
323 goto ERR_SELECT_CLK_TOP_MUX_AUD_2;
324 }
325
326 /* 196.608 / 8 = 24.576MHz */
327 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
328 if (ret) {
329 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
330 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2], ret);
331 goto ERR_ENABLE_CLK_TOP_MUX_AUD_ENG2;
332 }
333 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
334 afe_priv->clk[CLK_TOP_APLL2_D8]);
335 if (ret) {
336 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
337 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
338 aud_clks[CLK_TOP_APLL2_D8], ret);
339 goto ERR_SELECT_CLK_TOP_MUX_AUD_ENG2;
340 }
341 } else {
342 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
343 afe_priv->clk[CLK_CLK26M]);
344 if (ret) {
345 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
346 __func__, aud_clks[CLK_TOP_MUX_AUD_ENG2],
347 aud_clks[CLK_CLK26M], ret);
348 goto EXIT;
349 }
350 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
351
352 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
353 afe_priv->clk[CLK_CLK26M]);
354 if (ret) {
355 dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",
356 __func__, aud_clks[CLK_TOP_MUX_AUD_2],
357 aud_clks[CLK_CLK26M], ret);
358 goto EXIT;
359 }
360 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
361 }
362
363 return 0;
364
365ERR_SELECT_CLK_TOP_MUX_AUD_ENG2:
366 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
367 afe_priv->clk[CLK_CLK26M]);
368 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
369ERR_ENABLE_CLK_TOP_MUX_AUD_ENG2:
370ERR_SELECT_CLK_TOP_MUX_AUD_2:
371 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
372 afe_priv->clk[CLK_CLK26M]);
373 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
374ERR_ENABLE_CLK_TOP_MUX_AUD_2:
375EXIT:
376 return ret;
377}
378
379int mt8183_apll1_enable(struct mtk_base_afe *afe)
380{
381 struct mt8183_afe_private *afe_priv = afe->platform_priv;
382 int ret;
383
384 /* setting for APLL */
385 apll1_mux_setting(afe, true);
386
387 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]);
388 if (ret) {
389 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
390 __func__, aud_clks[CLK_APLL22M], ret);
391 goto ERR_CLK_APLL22M;
392 }
393
394 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]);
395 if (ret) {
396 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
397 __func__, aud_clks[CLK_APLL1_TUNER], ret);
398 goto ERR_CLK_APLL1_TUNER;
399 }
400
401 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG,
402 0x0000FFF7, 0x00000832);
403 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1);
404
405 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
406 AFE_22M_ON_MASK_SFT,
407 0x1 << AFE_22M_ON_SFT);
408
409 return 0;
410
411ERR_CLK_APLL1_TUNER:
412 clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
413ERR_CLK_APLL22M:
414 return ret;
415}
416
417void mt8183_apll1_disable(struct mtk_base_afe *afe)
418{
419 struct mt8183_afe_private *afe_priv = afe->platform_priv;
420
421 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
422 AFE_22M_ON_MASK_SFT,
423 0x0 << AFE_22M_ON_SFT);
424
425 regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x0);
426
427 clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);
428 clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
429
430 apll1_mux_setting(afe, false);
431}
432
433int mt8183_apll2_enable(struct mtk_base_afe *afe)
434{
435 struct mt8183_afe_private *afe_priv = afe->platform_priv;
436 int ret;
437
438 /* setting for APLL */
439 apll2_mux_setting(afe, true);
440
441 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]);
442 if (ret) {
443 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
444 __func__, aud_clks[CLK_APLL24M], ret);
445 goto ERR_CLK_APLL24M;
446 }
447
448 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]);
449 if (ret) {
450 dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",
451 __func__, aud_clks[CLK_APLL2_TUNER], ret);
452 goto ERR_CLK_APLL2_TUNER;
453 }
454
455 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG,
456 0x0000FFF7, 0x00000634);
457 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1);
458
459 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
460 AFE_24M_ON_MASK_SFT,
461 0x1 << AFE_24M_ON_SFT);
462
463 return 0;
464
465ERR_CLK_APLL2_TUNER:
466 clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
467ERR_CLK_APLL24M:
468 return ret;
469}
470
471void mt8183_apll2_disable(struct mtk_base_afe *afe)
472{
473 struct mt8183_afe_private *afe_priv = afe->platform_priv;
474
475 regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,
476 AFE_24M_ON_MASK_SFT,
477 0x0 << AFE_24M_ON_SFT);
478
479 regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x0);
480
481 clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);
482 clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
483
484 apll2_mux_setting(afe, false);
485}
486
487int mt8183_get_apll_rate(struct mtk_base_afe *afe, int apll)
488{
489 return (apll == MT8183_APLL1) ? 180633600 : 196608000;
490}
491
492int mt8183_get_apll_by_rate(struct mtk_base_afe *afe, int rate)
493{
494 return ((rate % 8000) == 0) ? MT8183_APLL2 : MT8183_APLL1;
495}
496
497int mt8183_get_apll_by_name(struct mtk_base_afe *afe, const char *name)
498{
499 if (strcmp(name, APLL1_W_NAME) == 0)
500 return MT8183_APLL1;
501 else
502 return MT8183_APLL2;
503}
504
505/* mck */
506struct mt8183_mck_div {
507 int m_sel_id;
508 int div_clk_id;
509};
510
511static const struct mt8183_mck_div mck_div[MT8183_MCK_NUM] = {
512 [MT8183_I2S0_MCK] = {
513 .m_sel_id = CLK_TOP_I2S0_M_SEL,
514 .div_clk_id = CLK_TOP_APLL12_DIV0,
515 },
516 [MT8183_I2S1_MCK] = {
517 .m_sel_id = CLK_TOP_I2S1_M_SEL,
518 .div_clk_id = CLK_TOP_APLL12_DIV1,
519 },
520 [MT8183_I2S2_MCK] = {
521 .m_sel_id = CLK_TOP_I2S2_M_SEL,
522 .div_clk_id = CLK_TOP_APLL12_DIV2,
523 },
524 [MT8183_I2S3_MCK] = {
525 .m_sel_id = CLK_TOP_I2S3_M_SEL,
526 .div_clk_id = CLK_TOP_APLL12_DIV3,
527 },
528 [MT8183_I2S4_MCK] = {
529 .m_sel_id = CLK_TOP_I2S4_M_SEL,
530 .div_clk_id = CLK_TOP_APLL12_DIV4,
531 },
532 [MT8183_I2S4_BCK] = {
533 .m_sel_id = -1,
534 .div_clk_id = CLK_TOP_APLL12_DIVB,
535 },
536 [MT8183_I2S5_MCK] = {
537 .m_sel_id = -1,
538 .div_clk_id = -1,
539 },
540};
541
542int mt8183_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)
543{
544 struct mt8183_afe_private *afe_priv = afe->platform_priv;
545 int apll = mt8183_get_apll_by_rate(afe, rate);
546 int apll_clk_id = apll == MT8183_APLL1 ?
547 CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2;
548 int m_sel_id = mck_div[mck_id].m_sel_id;
549 int div_clk_id = mck_div[mck_id].div_clk_id;
550 int ret;
551
552 /* i2s5 mck not support */
553 if (mck_id == MT8183_I2S5_MCK)
554 return 0;
555
556 /* select apll */
557 if (m_sel_id >= 0) {
558 ret = clk_prepare_enable(afe_priv->clk[m_sel_id]);
559 if (ret) {
560 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
561 __func__, aud_clks[m_sel_id], ret);
562 goto ERR_ENABLE_MCLK;
563 }
564 ret = clk_set_parent(afe_priv->clk[m_sel_id],
565 afe_priv->clk[apll_clk_id]);
566 if (ret) {
567 dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",
568 __func__, aud_clks[m_sel_id],
569 aud_clks[apll_clk_id], ret);
570 goto ERR_SELECT_MCLK;
571 }
572 }
573
574 /* enable div, set rate */
575 ret = clk_prepare_enable(afe_priv->clk[div_clk_id]);
576 if (ret) {
577 dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",
578 __func__, aud_clks[div_clk_id], ret);
579 goto ERR_ENABLE_MCLK_DIV;
580 }
581 ret = clk_set_rate(afe_priv->clk[div_clk_id], rate);
582 if (ret) {
583 dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n",
584 __func__, aud_clks[div_clk_id],
585 rate, ret);
586 goto ERR_SET_MCLK_RATE;
587 return ret;
588 }
589
590 return 0;
591
592ERR_SET_MCLK_RATE:
593 clk_disable_unprepare(afe_priv->clk[div_clk_id]);
594ERR_ENABLE_MCLK_DIV:
595ERR_SELECT_MCLK:
596 if (m_sel_id >= 0)
597 clk_disable_unprepare(afe_priv->clk[m_sel_id]);
598ERR_ENABLE_MCLK:
599 return ret;
600}
601
602void mt8183_mck_disable(struct mtk_base_afe *afe, int mck_id)
603{
604 struct mt8183_afe_private *afe_priv = afe->platform_priv;
605 int m_sel_id = mck_div[mck_id].m_sel_id;
606 int div_clk_id = mck_div[mck_id].div_clk_id;
607
608 clk_disable_unprepare(afe_priv->clk[div_clk_id]);
609 if (m_sel_id >= 0)
610 clk_disable_unprepare(afe_priv->clk[m_sel_id]);
611}
diff --git a/sound/soc/mediatek/mt8183/mt8183-afe-clk.h b/sound/soc/mediatek/mt8183/mt8183-afe-clk.h
new file mode 100644
index 000000000000..2c510aa80fc7
--- /dev/null
+++ b/sound/soc/mediatek/mt8183/mt8183-afe-clk.h
@@ -0,0 +1,38 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * mt8183-afe-clk.h -- Mediatek 8183 afe clock ctrl definition
4 *
5 * Copyright (c) 2018 MediaTek Inc.
6 * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7 */
8
9#ifndef _MT8183_AFE_CLK_H_
10#define _MT8183_AFE_CLK_H_
11
12/* APLL */
13#define APLL1_W_NAME "APLL1"
14#define APLL2_W_NAME "APLL2"
15enum {
16 MT8183_APLL1 = 0,
17 MT8183_APLL2,
18};
19
20struct mtk_base_afe;
21
22int mt8183_init_clock(struct mtk_base_afe *afe);
23int mt8183_afe_enable_clock(struct mtk_base_afe *afe);
24int mt8183_afe_disable_clock(struct mtk_base_afe *afe);
25
26int mt8183_apll1_enable(struct mtk_base_afe *afe);
27void mt8183_apll1_disable(struct mtk_base_afe *afe);
28
29int mt8183_apll2_enable(struct mtk_base_afe *afe);
30void mt8183_apll2_disable(struct mtk_base_afe *afe);
31
32int mt8183_get_apll_rate(struct mtk_base_afe *afe, int apll);
33int mt8183_get_apll_by_rate(struct mtk_base_afe *afe, int rate);
34int mt8183_get_apll_by_name(struct mtk_base_afe *afe, const char *name);
35
36int mt8183_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate);
37void mt8183_mck_disable(struct mtk_base_afe *afe, int mck_id);
38#endif
diff --git a/sound/soc/mediatek/mt8183/mt8183-afe-common.h b/sound/soc/mediatek/mt8183/mt8183-afe-common.h
new file mode 100644
index 000000000000..b220e7a7db7e
--- /dev/null
+++ b/sound/soc/mediatek/mt8183/mt8183-afe-common.h
@@ -0,0 +1,108 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * mt8183-afe-common.h -- Mediatek 8183 audio driver definitions
4 *
5 * Copyright (c) 2018 MediaTek Inc.
6 * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7 */
8
9#ifndef _MT_8183_AFE_COMMON_H_
10#define _MT_8183_AFE_COMMON_H_
11
12#include <sound/soc.h>
13#include <linux/list.h>
14#include <linux/regmap.h>
15#include "../common/mtk-base-afe.h"
16
17enum {
18 MT8183_MEMIF_DL1,
19 MT8183_MEMIF_DL2,
20 MT8183_MEMIF_DL3,
21 MT8183_MEMIF_VUL12,
22 MT8183_MEMIF_VUL2,
23 MT8183_MEMIF_AWB,
24 MT8183_MEMIF_AWB2,
25 MT8183_MEMIF_MOD_DAI,
26 MT8183_MEMIF_HDMI,
27 MT8183_MEMIF_NUM,
28 MT8183_DAI_ADDA = MT8183_MEMIF_NUM,
29 MT8183_DAI_PCM_1,
30 MT8183_DAI_PCM_2,
31 MT8183_DAI_I2S_0,
32 MT8183_DAI_I2S_1,
33 MT8183_DAI_I2S_2,
34 MT8183_DAI_I2S_3,
35 MT8183_DAI_I2S_5,
36 MT8183_DAI_TDM,
37 MT8183_DAI_HOSTLESS_LPBK,
38 MT8183_DAI_HOSTLESS_SPEECH,
39 MT8183_DAI_NUM,
40};
41
42enum {
43 MT8183_IRQ_0,
44 MT8183_IRQ_1,
45 MT8183_IRQ_2,
46 MT8183_IRQ_3,
47 MT8183_IRQ_4,
48 MT8183_IRQ_5,
49 MT8183_IRQ_6,
50 MT8183_IRQ_7,
51 MT8183_IRQ_8, /* hw bundle to TDM */
52 MT8183_IRQ_11,
53 MT8183_IRQ_12,
54 MT8183_IRQ_NUM,
55};
56
57enum {
58 MT8183_MTKAIF_PROTOCOL_1 = 0,
59 MT8183_MTKAIF_PROTOCOL_2,
60 MT8183_MTKAIF_PROTOCOL_2_CLK_P2,
61};
62
63/* MCLK */
64enum {
65 MT8183_I2S0_MCK = 0,
66 MT8183_I2S1_MCK,
67 MT8183_I2S2_MCK,
68 MT8183_I2S3_MCK,
69 MT8183_I2S4_MCK,
70 MT8183_I2S4_BCK,
71 MT8183_I2S5_MCK,
72 MT8183_MCK_NUM,
73};
74
75struct clk;
76
77struct mt8183_afe_private {
78 struct clk **clk;
79
80 int pm_runtime_bypass_reg_ctl;
81
82 /* dai */
83 void *dai_priv[MT8183_DAI_NUM];
84
85 /* adda */
86 int mtkaif_protocol;
87 int mtkaif_calibration_ok;
88 int mtkaif_chosen_phase[4];
89 int mtkaif_phase_cycle[4];
90 int mtkaif_calibration_num_phase;
91 int mtkaif_dmic;
92
93 /* mck */
94 int mck_rate[MT8183_MCK_NUM];
95};
96
97unsigned int mt8183_general_rate_transform(struct device *dev,
98 unsigned int rate);
99unsigned int mt8183_rate_transform(struct device *dev,
100 unsigned int rate, int aud_blk);
101
102/* dai register */
103int mt8183_dai_adda_register(struct mtk_base_afe *afe);
104int mt8183_dai_pcm_register(struct mtk_base_afe *afe);
105int mt8183_dai_i2s_register(struct mtk_base_afe *afe);
106int mt8183_dai_tdm_register(struct mtk_base_afe *afe);
107int mt8183_dai_hostless_register(struct mtk_base_afe *afe);
108#endif
diff --git a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
new file mode 100644
index 000000000000..ff3111ec876c
--- /dev/null
+++ b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
@@ -0,0 +1,1237 @@
1// SPDX-License-Identifier: GPL-2.0
2//
3// Mediatek ALSA SoC AFE platform driver for 8183
4//
5// Copyright (c) 2018 MediaTek Inc.
6// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7
8#include <linux/delay.h>
9#include <linux/module.h>
10#include <linux/mfd/syscon.h>
11#include <linux/of.h>
12#include <linux/of_address.h>
13#include <linux/pm_runtime.h>
14
15#include "mt8183-afe-common.h"
16#include "mt8183-afe-clk.h"
17#include "mt8183-interconnection.h"
18#include "mt8183-reg.h"
19#include "../common/mtk-afe-platform-driver.h"
20#include "../common/mtk-afe-fe-dai.h"
21
22enum {
23 MTK_AFE_RATE_8K = 0,
24 MTK_AFE_RATE_11K = 1,
25 MTK_AFE_RATE_12K = 2,
26 MTK_AFE_RATE_384K = 3,
27 MTK_AFE_RATE_16K = 4,
28 MTK_AFE_RATE_22K = 5,
29 MTK_AFE_RATE_24K = 6,
30 MTK_AFE_RATE_130K = 7,
31 MTK_AFE_RATE_32K = 8,
32 MTK_AFE_RATE_44K = 9,
33 MTK_AFE_RATE_48K = 10,
34 MTK_AFE_RATE_88K = 11,
35 MTK_AFE_RATE_96K = 12,
36 MTK_AFE_RATE_176K = 13,
37 MTK_AFE_RATE_192K = 14,
38 MTK_AFE_RATE_260K = 15,
39};
40
41enum {
42 MTK_AFE_DAI_MEMIF_RATE_8K = 0,
43 MTK_AFE_DAI_MEMIF_RATE_16K = 1,
44 MTK_AFE_DAI_MEMIF_RATE_32K = 2,
45 MTK_AFE_DAI_MEMIF_RATE_48K = 3,
46};
47
48enum {
49 MTK_AFE_PCM_RATE_8K = 0,
50 MTK_AFE_PCM_RATE_16K = 1,
51 MTK_AFE_PCM_RATE_32K = 2,
52 MTK_AFE_PCM_RATE_48K = 3,
53};
54
55unsigned int mt8183_general_rate_transform(struct device *dev,
56 unsigned int rate)
57{
58 switch (rate) {
59 case 8000:
60 return MTK_AFE_RATE_8K;
61 case 11025:
62 return MTK_AFE_RATE_11K;
63 case 12000:
64 return MTK_AFE_RATE_12K;
65 case 16000:
66 return MTK_AFE_RATE_16K;
67 case 22050:
68 return MTK_AFE_RATE_22K;
69 case 24000:
70 return MTK_AFE_RATE_24K;
71 case 32000:
72 return MTK_AFE_RATE_32K;
73 case 44100:
74 return MTK_AFE_RATE_44K;
75 case 48000:
76 return MTK_AFE_RATE_48K;
77 case 88200:
78 return MTK_AFE_RATE_88K;
79 case 96000:
80 return MTK_AFE_RATE_96K;
81 case 130000:
82 return MTK_AFE_RATE_130K;
83 case 176400:
84 return MTK_AFE_RATE_176K;
85 case 192000:
86 return MTK_AFE_RATE_192K;
87 case 260000:
88 return MTK_AFE_RATE_260K;
89 default:
90 dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
91 __func__, rate, MTK_AFE_RATE_48K);
92 return MTK_AFE_RATE_48K;
93 }
94}
95
96static unsigned int dai_memif_rate_transform(struct device *dev,
97 unsigned int rate)
98{
99 switch (rate) {
100 case 8000:
101 return MTK_AFE_DAI_MEMIF_RATE_8K;
102 case 16000:
103 return MTK_AFE_DAI_MEMIF_RATE_16K;
104 case 32000:
105 return MTK_AFE_DAI_MEMIF_RATE_32K;
106 case 48000:
107 return MTK_AFE_DAI_MEMIF_RATE_48K;
108 default:
109 dev_warn(dev, "%s(), rate %u invalid, use %d!!!\n",
110 __func__, rate, MTK_AFE_DAI_MEMIF_RATE_16K);
111 return MTK_AFE_DAI_MEMIF_RATE_16K;
112 }
113}
114
115unsigned int mt8183_rate_transform(struct device *dev,
116 unsigned int rate, int aud_blk)
117{
118 switch (aud_blk) {
119 case MT8183_MEMIF_MOD_DAI:
120 return dai_memif_rate_transform(dev, rate);
121 default:
122 return mt8183_general_rate_transform(dev, rate);
123 }
124}
125
126static const struct snd_pcm_hardware mt8183_afe_hardware = {
127 .info = SNDRV_PCM_INFO_MMAP |
128 SNDRV_PCM_INFO_INTERLEAVED |
129 SNDRV_PCM_INFO_MMAP_VALID,
130 .formats = SNDRV_PCM_FMTBIT_S16_LE |
131 SNDRV_PCM_FMTBIT_S24_LE |
132 SNDRV_PCM_FMTBIT_S32_LE,
133 .period_bytes_min = 256,
134 .period_bytes_max = 4 * 48 * 1024,
135 .periods_min = 2,
136 .periods_max = 256,
137 .buffer_bytes_max = 8 * 48 * 1024,
138 .fifo_size = 0,
139};
140
141static int mt8183_memif_fs(struct snd_pcm_substream *substream,
142 unsigned int rate)
143{
144 struct snd_soc_pcm_runtime *rtd = substream->private_data;
145 struct snd_soc_component *component =
146 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
147 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
148 int id = rtd->cpu_dai->id;
149
150 return mt8183_rate_transform(afe->dev, rate, id);
151}
152
153static int mt8183_irq_fs(struct snd_pcm_substream *substream, unsigned int rate)
154{
155 struct snd_soc_pcm_runtime *rtd = substream->private_data;
156 struct snd_soc_component *component =
157 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME);
158 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);
159
160 return mt8183_general_rate_transform(afe->dev, rate);
161}
162
163#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\
164 SNDRV_PCM_RATE_88200 |\
165 SNDRV_PCM_RATE_96000 |\
166 SNDRV_PCM_RATE_176400 |\
167 SNDRV_PCM_RATE_192000)
168
169#define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\
170 SNDRV_PCM_RATE_16000 |\
171 SNDRV_PCM_RATE_32000 |\
172 SNDRV_PCM_RATE_48000)
173
174#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
175 SNDRV_PCM_FMTBIT_S24_LE |\
176 SNDRV_PCM_FMTBIT_S32_LE)
177
178static struct snd_soc_dai_driver mt8183_memif_dai_driver[] = {
179 /* FE DAIs: memory intefaces to CPU */
180 {
181 .name = "DL1",
182 .id = MT8183_MEMIF_DL1,
183 .playback = {
184 .stream_name = "DL1",
185 .channels_min = 1,
186 .channels_max = 2,
187 .rates = MTK_PCM_RATES,
188 .formats = MTK_PCM_FORMATS,
189 },
190 .ops = &mtk_afe_fe_ops,
191 },
192 {
193 .name = "DL2",
194 .id = MT8183_MEMIF_DL2,
195 .playback = {
196 .stream_name = "DL2",
197 .channels_min = 1,
198 .channels_max = 2,
199 .rates = MTK_PCM_RATES,
200 .formats = MTK_PCM_FORMATS,
201 },
202 .ops = &mtk_afe_fe_ops,
203 },
204 {
205 .name = "DL3",
206 .id = MT8183_MEMIF_DL3,
207 .playback = {
208 .stream_name = "DL3",
209 .channels_min = 1,
210 .channels_max = 2,
211 .rates = MTK_PCM_RATES,
212 .formats = MTK_PCM_FORMATS,
213 },
214 .ops = &mtk_afe_fe_ops,
215 },
216 {
217 .name = "UL1",
218 .id = MT8183_MEMIF_VUL12,
219 .capture = {
220 .stream_name = "UL1",
221 .channels_min = 1,
222 .channels_max = 2,
223 .rates = MTK_PCM_RATES,
224 .formats = MTK_PCM_FORMATS,
225 },
226 .ops = &mtk_afe_fe_ops,
227 },
228 {
229 .name = "UL2",
230 .id = MT8183_MEMIF_AWB,
231 .capture = {
232 .stream_name = "UL2",
233 .channels_min = 1,
234 .channels_max = 2,
235 .rates = MTK_PCM_RATES,
236 .formats = MTK_PCM_FORMATS,
237 },
238 .ops = &mtk_afe_fe_ops,
239 },
240 {
241 .name = "UL3",
242 .id = MT8183_MEMIF_VUL2,
243 .capture = {
244 .stream_name = "UL3",
245 .channels_min = 1,
246 .channels_max = 2,
247 .rates = MTK_PCM_RATES,
248 .formats = MTK_PCM_FORMATS,
249 },
250 .ops = &mtk_afe_fe_ops,
251 },
252 {
253 .name = "UL4",
254 .id = MT8183_MEMIF_AWB2,
255 .capture = {
256 .stream_name = "UL4",
257 .channels_min = 1,
258 .channels_max = 2,
259 .rates = MTK_PCM_RATES,
260 .formats = MTK_PCM_FORMATS,
261 },
262 .ops = &mtk_afe_fe_ops,
263 },
264 {
265 .name = "UL_MONO_1",
266 .id = MT8183_MEMIF_MOD_DAI,
267 .capture = {
268 .stream_name = "UL_MONO_1",
269 .channels_min = 1,
270 .channels_max = 1,
271 .rates = MTK_PCM_DAI_RATES,
272 .formats = MTK_PCM_FORMATS,
273 },
274 .ops = &mtk_afe_fe_ops,
275 },
276 {
277 .name = "HDMI",
278 .id = MT8183_MEMIF_HDMI,
279 .playback = {
280 .stream_name = "HDMI",
281 .channels_min = 2,
282 .channels_max = 8,
283 .rates = MTK_PCM_RATES,
284 .formats = MTK_PCM_FORMATS,
285 },
286 .ops = &mtk_afe_fe_ops,
287 },
288};
289
290/* dma widget & routes*/
291static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = {
292 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN21,
293 I_ADDA_UL_CH1, 1, 0),
294};
295
296static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = {
297 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN22,
298 I_ADDA_UL_CH2, 1, 0),
299};
300
301static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = {
302 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN5,
303 I_ADDA_UL_CH1, 1, 0),
304 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN5,
305 I_DL1_CH1, 1, 0),
306 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN5,
307 I_DL2_CH1, 1, 0),
308 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN5,
309 I_DL3_CH1, 1, 0),
310};
311
312static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = {
313 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN6,
314 I_ADDA_UL_CH2, 1, 0),
315 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN6,
316 I_DL1_CH2, 1, 0),
317 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN6,
318 I_DL2_CH2, 1, 0),
319 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN6,
320 I_DL3_CH2, 1, 0),
321};
322
323static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = {
324 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN32,
325 I_ADDA_UL_CH1, 1, 0),
326};
327
328static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = {
329 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN33,
330 I_ADDA_UL_CH2, 1, 0),
331};
332
333static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = {
334 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN38,
335 I_ADDA_UL_CH1, 1, 0),
336};
337
338static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = {
339 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN39,
340 I_ADDA_UL_CH2, 1, 0),
341};
342
343static const struct snd_kcontrol_new memif_ul_mono_1_mix[] = {
344 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN12,
345 I_ADDA_UL_CH1, 1, 0),
346 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN12,
347 I_ADDA_UL_CH2, 1, 0),
348};
349
350static const struct snd_soc_dapm_widget mt8183_memif_widgets[] = {
351 /* memif */
352 SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0,
353 memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)),
354 SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0,
355 memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)),
356
357 SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0,
358 memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)),
359 SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0,
360 memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)),
361
362 SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0,
363 memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)),
364 SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0,
365 memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)),
366
367 SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0,
368 memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)),
369 SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0,
370 memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)),
371
372 SND_SOC_DAPM_MIXER("UL_MONO_1_CH1", SND_SOC_NOPM, 0, 0,
373 memif_ul_mono_1_mix,
374 ARRAY_SIZE(memif_ul_mono_1_mix)),
375};
376
377static const struct snd_soc_dapm_route mt8183_memif_routes[] = {
378 /* capture */
379 {"UL1", NULL, "UL1_CH1"},
380 {"UL1", NULL, "UL1_CH2"},
381 {"UL1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
382 {"UL1_CH2", "ADDA_UL_CH2", "ADDA Capture"},
383
384 {"UL2", NULL, "UL2_CH1"},
385 {"UL2", NULL, "UL2_CH2"},
386 {"UL2_CH1", "ADDA_UL_CH1", "ADDA Capture"},
387 {"UL2_CH2", "ADDA_UL_CH2", "ADDA Capture"},
388
389 {"UL3", NULL, "UL3_CH1"},
390 {"UL3", NULL, "UL3_CH2"},
391 {"UL3_CH1", "ADDA_UL_CH1", "ADDA Capture"},
392 {"UL3_CH2", "ADDA_UL_CH2", "ADDA Capture"},
393
394 {"UL4", NULL, "UL4_CH1"},
395 {"UL4", NULL, "UL4_CH2"},
396 {"UL4_CH1", "ADDA_UL_CH1", "ADDA Capture"},
397 {"UL4_CH2", "ADDA_UL_CH2", "ADDA Capture"},
398
399 {"UL_MONO_1", NULL, "UL_MONO_1_CH1"},
400 {"UL_MONO_1_CH1", "ADDA_UL_CH1", "ADDA Capture"},
401 {"UL_MONO_1_CH1", "ADDA_UL_CH2", "ADDA Capture"},
402};
403
404static const struct snd_soc_component_driver mt8183_afe_pcm_dai_component = {
405 .name = "mt8183-afe-pcm-dai",
406};
407
408static const struct mtk_base_memif_data memif_data[MT8183_MEMIF_NUM] = {
409 [MT8183_MEMIF_DL1] = {
410 .name = "DL1",
411 .id = MT8183_MEMIF_DL1,
412 .reg_ofs_base = AFE_DL1_BASE,
413 .reg_ofs_cur = AFE_DL1_CUR,
414 .fs_reg = AFE_DAC_CON1,
415 .fs_shift = DL1_MODE_SFT,
416 .fs_maskbit = DL1_MODE_MASK,
417 .mono_reg = AFE_DAC_CON1,
418 .mono_shift = DL1_DATA_SFT,
419 .enable_reg = AFE_DAC_CON0,
420 .enable_shift = DL1_ON_SFT,
421 .hd_reg = AFE_MEMIF_HD_MODE,
422 .hd_shift = DL1_HD_SFT,
423 .agent_disable_reg = -1,
424 .agent_disable_shift = -1,
425 .msb_reg = -1,
426 .msb_shift = -1,
427 },
428 [MT8183_MEMIF_DL2] = {
429 .name = "DL2",
430 .id = MT8183_MEMIF_DL2,
431 .reg_ofs_base = AFE_DL2_BASE,
432 .reg_ofs_cur = AFE_DL2_CUR,
433 .fs_reg = AFE_DAC_CON1,
434 .fs_shift = DL2_MODE_SFT,
435 .fs_maskbit = DL2_MODE_MASK,
436 .mono_reg = AFE_DAC_CON1,
437 .mono_shift = DL2_DATA_SFT,
438 .enable_reg = AFE_DAC_CON0,
439 .enable_shift = DL2_ON_SFT,
440 .hd_reg = AFE_MEMIF_HD_MODE,
441 .hd_shift = DL2_HD_SFT,
442 .agent_disable_reg = -1,
443 .agent_disable_shift = -1,
444 .msb_reg = -1,
445 .msb_shift = -1,
446 },
447 [MT8183_MEMIF_DL3] = {
448 .name = "DL3",
449 .id = MT8183_MEMIF_DL3,
450 .reg_ofs_base = AFE_DL3_BASE,
451 .reg_ofs_cur = AFE_DL3_CUR,
452 .fs_reg = AFE_DAC_CON2,
453 .fs_shift = DL3_MODE_SFT,
454 .fs_maskbit = DL3_MODE_MASK,
455 .mono_reg = AFE_DAC_CON1,
456 .mono_shift = DL3_DATA_SFT,
457 .enable_reg = AFE_DAC_CON0,
458 .enable_shift = DL3_ON_SFT,
459 .hd_reg = AFE_MEMIF_HD_MODE,
460 .hd_shift = DL3_HD_SFT,
461 .agent_disable_reg = -1,
462 .agent_disable_shift = -1,
463 .msb_reg = -1,
464 .msb_shift = -1,
465 },
466 [MT8183_MEMIF_VUL2] = {
467 .name = "VUL2",
468 .id = MT8183_MEMIF_VUL2,
469 .reg_ofs_base = AFE_VUL2_BASE,
470 .reg_ofs_cur = AFE_VUL2_CUR,
471 .fs_reg = AFE_DAC_CON2,
472 .fs_shift = VUL2_MODE_SFT,
473 .fs_maskbit = VUL2_MODE_MASK,
474 .mono_reg = AFE_DAC_CON2,
475 .mono_shift = VUL2_DATA_SFT,
476 .enable_reg = AFE_DAC_CON0,
477 .enable_shift = VUL2_ON_SFT,
478 .hd_reg = AFE_MEMIF_HD_MODE,
479 .hd_shift = VUL2_HD_SFT,
480 .agent_disable_reg = -1,
481 .agent_disable_shift = -1,
482 .msb_reg = -1,
483 .msb_shift = -1,
484 },
485 [MT8183_MEMIF_AWB] = {
486 .name = "AWB",
487 .id = MT8183_MEMIF_AWB,
488 .reg_ofs_base = AFE_AWB_BASE,
489 .reg_ofs_cur = AFE_AWB_CUR,
490 .fs_reg = AFE_DAC_CON1,
491 .fs_shift = AWB_MODE_SFT,
492 .fs_maskbit = AWB_MODE_MASK,
493 .mono_reg = AFE_DAC_CON1,
494 .mono_shift = AWB_DATA_SFT,
495 .enable_reg = AFE_DAC_CON0,
496 .enable_shift = AWB_ON_SFT,
497 .hd_reg = AFE_MEMIF_HD_MODE,
498 .hd_shift = AWB_HD_SFT,
499 .agent_disable_reg = -1,
500 .agent_disable_shift = -1,
501 .msb_reg = -1,
502 .msb_shift = -1,
503 },
504 [MT8183_MEMIF_AWB2] = {
505 .name = "AWB2",
506 .id = MT8183_MEMIF_AWB2,
507 .reg_ofs_base = AFE_AWB2_BASE,
508 .reg_ofs_cur = AFE_AWB2_CUR,
509 .fs_reg = AFE_DAC_CON2,
510 .fs_shift = AWB2_MODE_SFT,
511 .fs_maskbit = AWB2_MODE_MASK,
512 .mono_reg = AFE_DAC_CON2,
513 .mono_shift = AWB2_DATA_SFT,
514 .enable_reg = AFE_DAC_CON0,
515 .enable_shift = AWB2_ON_SFT,
516 .hd_reg = AFE_MEMIF_HD_MODE,
517 .hd_shift = AWB2_HD_SFT,
518 .agent_disable_reg = -1,
519 .agent_disable_shift = -1,
520 .msb_reg = -1,
521 .msb_shift = -1,
522 },
523 [MT8183_MEMIF_VUL12] = {
524 .name = "VUL12",
525 .id = MT8183_MEMIF_VUL12,
526 .reg_ofs_base = AFE_VUL_D2_BASE,
527 .reg_ofs_cur = AFE_VUL_D2_CUR,
528 .fs_reg = AFE_DAC_CON0,
529 .fs_shift = VUL12_MODE_SFT,
530 .fs_maskbit = VUL12_MODE_MASK,
531 .mono_reg = AFE_DAC_CON0,
532 .mono_shift = VUL12_MONO_SFT,
533 .enable_reg = AFE_DAC_CON0,
534 .enable_shift = VUL12_ON_SFT,
535 .hd_reg = AFE_MEMIF_HD_MODE,
536 .hd_shift = VUL12_HD_SFT,
537 .agent_disable_reg = -1,
538 .agent_disable_shift = -1,
539 .msb_reg = -1,
540 .msb_shift = -1,
541 },
542 [MT8183_MEMIF_MOD_DAI] = {
543 .name = "MOD_DAI",
544 .id = MT8183_MEMIF_MOD_DAI,
545 .reg_ofs_base = AFE_MOD_DAI_BASE,
546 .reg_ofs_cur = AFE_MOD_DAI_CUR,
547 .fs_reg = AFE_DAC_CON1,
548 .fs_shift = MOD_DAI_MODE_SFT,
549 .fs_maskbit = MOD_DAI_MODE_MASK,
550 .mono_reg = -1,
551 .mono_shift = 0,
552 .enable_reg = AFE_DAC_CON0,
553 .enable_shift = MOD_DAI_ON_SFT,
554 .hd_reg = AFE_MEMIF_HD_MODE,
555 .hd_shift = MOD_DAI_HD_SFT,
556 .agent_disable_reg = -1,
557 .agent_disable_shift = -1,
558 .msb_reg = -1,
559 .msb_shift = -1,
560 },
561 [MT8183_MEMIF_HDMI] = {
562 .name = "HDMI",
563 .id = MT8183_MEMIF_HDMI,
564 .reg_ofs_base = AFE_HDMI_OUT_BASE,
565 .reg_ofs_cur = AFE_HDMI_OUT_CUR,
566 .fs_reg = -1,
567 .fs_shift = -1,
568 .fs_maskbit = -1,
569 .mono_reg = -1,
570 .mono_shift = -1,
571 .enable_reg = -1, /* control in tdm for sync start */
572 .enable_shift = -1,
573 .hd_reg = AFE_MEMIF_HD_MODE,
574 .hd_shift = HDMI_HD_SFT,
575 .agent_disable_reg = -1,
576 .agent_disable_shift = -1,
577 .msb_reg = -1,
578 .msb_shift = -1,
579 },
580};
581
582static const struct mtk_base_irq_data irq_data[MT8183_IRQ_NUM] = {
583 [MT8183_IRQ_0] = {
584 .id = MT8183_IRQ_0,
585 .irq_cnt_reg = AFE_IRQ_MCU_CNT0,
586 .irq_cnt_shift = 0,
587 .irq_cnt_maskbit = 0x3ffff,
588 .irq_fs_reg = AFE_IRQ_MCU_CON1,
589 .irq_fs_shift = IRQ0_MCU_MODE_SFT,
590 .irq_fs_maskbit = IRQ0_MCU_MODE_MASK,
591 .irq_en_reg = AFE_IRQ_MCU_CON0,
592 .irq_en_shift = IRQ0_MCU_ON_SFT,
593 .irq_clr_reg = AFE_IRQ_MCU_CLR,
594 .irq_clr_shift = IRQ0_MCU_CLR_SFT,
595 },
596 [MT8183_IRQ_1] = {
597 .id = MT8183_IRQ_1,
598 .irq_cnt_reg = AFE_IRQ_MCU_CNT1,
599 .irq_cnt_shift = 0,
600 .irq_cnt_maskbit = 0x3ffff,
601 .irq_fs_reg = AFE_IRQ_MCU_CON1,
602 .irq_fs_shift = IRQ1_MCU_MODE_SFT,
603 .irq_fs_maskbit = IRQ1_MCU_MODE_MASK,
604 .irq_en_reg = AFE_IRQ_MCU_CON0,
605 .irq_en_shift = IRQ1_MCU_ON_SFT,
606 .irq_clr_reg = AFE_IRQ_MCU_CLR,
607 .irq_clr_shift = IRQ1_MCU_CLR_SFT,
608 },
609 [MT8183_IRQ_2] = {
610 .id = MT8183_IRQ_2,
611 .irq_cnt_reg = AFE_IRQ_MCU_CNT2,
612 .irq_cnt_shift = 0,
613 .irq_cnt_maskbit = 0x3ffff,
614 .irq_fs_reg = AFE_IRQ_MCU_CON1,
615 .irq_fs_shift = IRQ2_MCU_MODE_SFT,
616 .irq_fs_maskbit = IRQ2_MCU_MODE_MASK,
617 .irq_en_reg = AFE_IRQ_MCU_CON0,
618 .irq_en_shift = IRQ2_MCU_ON_SFT,
619 .irq_clr_reg = AFE_IRQ_MCU_CLR,
620 .irq_clr_shift = IRQ2_MCU_CLR_SFT,
621 },
622 [MT8183_IRQ_3] = {
623 .id = MT8183_IRQ_3,
624 .irq_cnt_reg = AFE_IRQ_MCU_CNT3,
625 .irq_cnt_shift = 0,
626 .irq_cnt_maskbit = 0x3ffff,
627 .irq_fs_reg = AFE_IRQ_MCU_CON1,
628 .irq_fs_shift = IRQ3_MCU_MODE_SFT,
629 .irq_fs_maskbit = IRQ3_MCU_MODE_MASK,
630 .irq_en_reg = AFE_IRQ_MCU_CON0,
631 .irq_en_shift = IRQ3_MCU_ON_SFT,
632 .irq_clr_reg = AFE_IRQ_MCU_CLR,
633 .irq_clr_shift = IRQ3_MCU_CLR_SFT,
634 },
635 [MT8183_IRQ_4] = {
636 .id = MT8183_IRQ_4,
637 .irq_cnt_reg = AFE_IRQ_MCU_CNT4,
638 .irq_cnt_shift = 0,
639 .irq_cnt_maskbit = 0x3ffff,
640 .irq_fs_reg = AFE_IRQ_MCU_CON1,
641 .irq_fs_shift = IRQ4_MCU_MODE_SFT,
642 .irq_fs_maskbit = IRQ4_MCU_MODE_MASK,
643 .irq_en_reg = AFE_IRQ_MCU_CON0,
644 .irq_en_shift = IRQ4_MCU_ON_SFT,
645 .irq_clr_reg = AFE_IRQ_MCU_CLR,
646 .irq_clr_shift = IRQ4_MCU_CLR_SFT,
647 },
648 [MT8183_IRQ_5] = {
649 .id = MT8183_IRQ_5,
650 .irq_cnt_reg = AFE_IRQ_MCU_CNT5,
651 .irq_cnt_shift = 0,
652 .irq_cnt_maskbit = 0x3ffff,
653 .irq_fs_reg = AFE_IRQ_MCU_CON1,
654 .irq_fs_shift = IRQ5_MCU_MODE_SFT,
655 .irq_fs_maskbit = IRQ5_MCU_MODE_MASK,
656 .irq_en_reg = AFE_IRQ_MCU_CON0,
657 .irq_en_shift = IRQ5_MCU_ON_SFT,
658 .irq_clr_reg = AFE_IRQ_MCU_CLR,
659 .irq_clr_shift = IRQ5_MCU_CLR_SFT,
660 },
661 [MT8183_IRQ_6] = {
662 .id = MT8183_IRQ_6,
663 .irq_cnt_reg = AFE_IRQ_MCU_CNT6,
664 .irq_cnt_shift = 0,
665 .irq_cnt_maskbit = 0x3ffff,
666 .irq_fs_reg = AFE_IRQ_MCU_CON1,
667 .irq_fs_shift = IRQ6_MCU_MODE_SFT,
668 .irq_fs_maskbit = IRQ6_MCU_MODE_MASK,
669 .irq_en_reg = AFE_IRQ_MCU_CON0,
670 .irq_en_shift = IRQ6_MCU_ON_SFT,
671 .irq_clr_reg = AFE_IRQ_MCU_CLR,
672 .irq_clr_shift = IRQ6_MCU_CLR_SFT,
673 },
674 [MT8183_IRQ_7] = {
675 .id = MT8183_IRQ_7,
676 .irq_cnt_reg = AFE_IRQ_MCU_CNT7,
677 .irq_cnt_shift = 0,
678 .irq_cnt_maskbit = 0x3ffff,
679 .irq_fs_reg = AFE_IRQ_MCU_CON1,
680 .irq_fs_shift = IRQ7_MCU_MODE_SFT,
681 .irq_fs_maskbit = IRQ7_MCU_MODE_MASK,
682 .irq_en_reg = AFE_IRQ_MCU_CON0,
683 .irq_en_shift = IRQ7_MCU_ON_SFT,
684 .irq_clr_reg = AFE_IRQ_MCU_CLR,
685 .irq_clr_shift = IRQ7_MCU_CLR_SFT,
686 },
687 [MT8183_IRQ_8] = {
688 .id = MT8183_IRQ_8,
689 .irq_cnt_reg = AFE_IRQ_MCU_CNT8,
690 .irq_cnt_shift = 0,
691 .irq_cnt_maskbit = 0x3ffff,
692 .irq_fs_reg = -1,
693 .irq_fs_shift = -1,
694 .irq_fs_maskbit = -1,
695 .irq_en_reg = AFE_IRQ_MCU_CON0,
696 .irq_en_shift = IRQ8_MCU_ON_SFT,
697 .irq_clr_reg = AFE_IRQ_MCU_CLR,
698 .irq_clr_shift = IRQ8_MCU_CLR_SFT,
699 },
700 [MT8183_IRQ_11] = {
701 .id = MT8183_IRQ_11,
702 .irq_cnt_reg = AFE_IRQ_MCU_CNT11,
703 .irq_cnt_shift = 0,
704 .irq_cnt_maskbit = 0x3ffff,
705 .irq_fs_reg = AFE_IRQ_MCU_CON2,
706 .irq_fs_shift = IRQ11_MCU_MODE_SFT,
707 .irq_fs_maskbit = IRQ11_MCU_MODE_MASK,
708 .irq_en_reg = AFE_IRQ_MCU_CON0,
709 .irq_en_shift = IRQ11_MCU_ON_SFT,
710 .irq_clr_reg = AFE_IRQ_MCU_CLR,
711 .irq_clr_shift = IRQ11_MCU_CLR_SFT,
712 },
713 [MT8183_IRQ_12] = {
714 .id = MT8183_IRQ_12,
715 .irq_cnt_reg = AFE_IRQ_MCU_CNT12,
716 .irq_cnt_shift = 0,
717 .irq_cnt_maskbit = 0x3ffff,
718 .irq_fs_reg = AFE_IRQ_MCU_CON2,
719 .irq_fs_shift = IRQ12_MCU_MODE_SFT,
720 .irq_fs_maskbit = IRQ12_MCU_MODE_MASK,
721 .irq_en_reg = AFE_IRQ_MCU_CON0,
722 .irq_en_shift = IRQ12_MCU_ON_SFT,
723 .irq_clr_reg = AFE_IRQ_MCU_CLR,
724 .irq_clr_shift = IRQ12_MCU_CLR_SFT,
725 },
726};
727
728static bool mt8183_is_volatile_reg(struct device *dev, unsigned int reg)
729{
730 /* these auto-gen reg has read-only bit, so put it as volatile */
731 /* volatile reg cannot be cached, so cannot be set when power off */
732 switch (reg) {
733 case AUDIO_TOP_CON0: /* reg bit controlled by CCF */
734 case AUDIO_TOP_CON1: /* reg bit controlled by CCF */
735 case AUDIO_TOP_CON3:
736 case AFE_DL1_CUR:
737 case AFE_DL1_END:
738 case AFE_DL2_CUR:
739 case AFE_DL2_END:
740 case AFE_AWB_END:
741 case AFE_AWB_CUR:
742 case AFE_VUL_END:
743 case AFE_VUL_CUR:
744 case AFE_MEMIF_MON0:
745 case AFE_MEMIF_MON1:
746 case AFE_MEMIF_MON2:
747 case AFE_MEMIF_MON3:
748 case AFE_MEMIF_MON4:
749 case AFE_MEMIF_MON5:
750 case AFE_MEMIF_MON6:
751 case AFE_MEMIF_MON7:
752 case AFE_MEMIF_MON8:
753 case AFE_MEMIF_MON9:
754 case AFE_ADDA_SRC_DEBUG_MON0:
755 case AFE_ADDA_SRC_DEBUG_MON1:
756 case AFE_ADDA_UL_SRC_MON0:
757 case AFE_ADDA_UL_SRC_MON1:
758 case AFE_SIDETONE_MON:
759 case AFE_SIDETONE_CON0:
760 case AFE_SIDETONE_COEFF:
761 case AFE_BUS_MON0:
762 case AFE_MRGIF_MON0:
763 case AFE_MRGIF_MON1:
764 case AFE_MRGIF_MON2:
765 case AFE_I2S_MON:
766 case AFE_DAC_MON:
767 case AFE_VUL2_END:
768 case AFE_VUL2_CUR:
769 case AFE_IRQ0_MCU_CNT_MON:
770 case AFE_IRQ6_MCU_CNT_MON:
771 case AFE_MOD_DAI_END:
772 case AFE_MOD_DAI_CUR:
773 case AFE_VUL_D2_END:
774 case AFE_VUL_D2_CUR:
775 case AFE_DL3_CUR:
776 case AFE_DL3_END:
777 case AFE_HDMI_OUT_CON0:
778 case AFE_HDMI_OUT_CUR:
779 case AFE_HDMI_OUT_END:
780 case AFE_IRQ3_MCU_CNT_MON:
781 case AFE_IRQ4_MCU_CNT_MON:
782 case AFE_IRQ_MCU_STATUS:
783 case AFE_IRQ_MCU_CLR:
784 case AFE_IRQ_MCU_MON2:
785 case AFE_IRQ1_MCU_CNT_MON:
786 case AFE_IRQ2_MCU_CNT_MON:
787 case AFE_IRQ1_MCU_EN_CNT_MON:
788 case AFE_IRQ5_MCU_CNT_MON:
789 case AFE_IRQ7_MCU_CNT_MON:
790 case AFE_GAIN1_CUR:
791 case AFE_GAIN2_CUR:
792 case AFE_SRAM_DELSEL_CON0:
793 case AFE_SRAM_DELSEL_CON2:
794 case AFE_SRAM_DELSEL_CON3:
795 case AFE_ASRC_2CH_CON12:
796 case AFE_ASRC_2CH_CON13:
797 case PCM_INTF_CON2:
798 case FPGA_CFG0:
799 case FPGA_CFG1:
800 case FPGA_CFG2:
801 case FPGA_CFG3:
802 case AUDIO_TOP_DBG_MON0:
803 case AUDIO_TOP_DBG_MON1:
804 case AFE_IRQ8_MCU_CNT_MON:
805 case AFE_IRQ11_MCU_CNT_MON:
806 case AFE_IRQ12_MCU_CNT_MON:
807 case AFE_CBIP_MON0:
808 case AFE_CBIP_SLV_MUX_MON0:
809 case AFE_CBIP_SLV_DECODER_MON0:
810 case AFE_ADDA6_SRC_DEBUG_MON0:
811 case AFE_ADD6A_UL_SRC_MON0:
812 case AFE_ADDA6_UL_SRC_MON1:
813 case AFE_DL1_CUR_MSB:
814 case AFE_DL2_CUR_MSB:
815 case AFE_AWB_CUR_MSB:
816 case AFE_VUL_CUR_MSB:
817 case AFE_VUL2_CUR_MSB:
818 case AFE_MOD_DAI_CUR_MSB:
819 case AFE_VUL_D2_CUR_MSB:
820 case AFE_DL3_CUR_MSB:
821 case AFE_HDMI_OUT_CUR_MSB:
822 case AFE_AWB2_END:
823 case AFE_AWB2_CUR:
824 case AFE_AWB2_CUR_MSB:
825 case AFE_ADDA_DL_SDM_FIFO_MON:
826 case AFE_ADDA_DL_SRC_LCH_MON:
827 case AFE_ADDA_DL_SRC_RCH_MON:
828 case AFE_ADDA_DL_SDM_OUT_MON:
829 case AFE_CONNSYS_I2S_MON:
830 case AFE_ASRC_2CH_CON0:
831 case AFE_ASRC_2CH_CON2:
832 case AFE_ASRC_2CH_CON3:
833 case AFE_ASRC_2CH_CON4:
834 case AFE_ASRC_2CH_CON5:
835 case AFE_ASRC_2CH_CON7:
836 case AFE_ASRC_2CH_CON8:
837 case AFE_MEMIF_MON12:
838 case AFE_MEMIF_MON13:
839 case AFE_MEMIF_MON14:
840 case AFE_MEMIF_MON15:
841 case AFE_MEMIF_MON16:
842 case AFE_MEMIF_MON17:
843 case AFE_MEMIF_MON18:
844 case AFE_MEMIF_MON19:
845 case AFE_MEMIF_MON20:
846 case AFE_MEMIF_MON21:
847 case AFE_MEMIF_MON22:
848 case AFE_MEMIF_MON23:
849 case AFE_MEMIF_MON24:
850 case AFE_ADDA_MTKAIF_MON0:
851 case AFE_ADDA_MTKAIF_MON1:
852 case AFE_AUD_PAD_TOP:
853 case AFE_GENERAL1_ASRC_2CH_CON0:
854 case AFE_GENERAL1_ASRC_2CH_CON2:
855 case AFE_GENERAL1_ASRC_2CH_CON3:
856 case AFE_GENERAL1_ASRC_2CH_CON4:
857 case AFE_GENERAL1_ASRC_2CH_CON5:
858 case AFE_GENERAL1_ASRC_2CH_CON7:
859 case AFE_GENERAL1_ASRC_2CH_CON8:
860 case AFE_GENERAL1_ASRC_2CH_CON12:
861 case AFE_GENERAL1_ASRC_2CH_CON13:
862 case AFE_GENERAL2_ASRC_2CH_CON0:
863 case AFE_GENERAL2_ASRC_2CH_CON2:
864 case AFE_GENERAL2_ASRC_2CH_CON3:
865 case AFE_GENERAL2_ASRC_2CH_CON4:
866 case AFE_GENERAL2_ASRC_2CH_CON5:
867 case AFE_GENERAL2_ASRC_2CH_CON7:
868 case AFE_GENERAL2_ASRC_2CH_CON8:
869 case AFE_GENERAL2_ASRC_2CH_CON12:
870 case AFE_GENERAL2_ASRC_2CH_CON13:
871 return true;
872 default:
873 return false;
874 };
875}
876
877static const struct regmap_config mt8183_afe_regmap_config = {
878 .reg_bits = 32,
879 .reg_stride = 4,
880 .val_bits = 32,
881
882 .volatile_reg = mt8183_is_volatile_reg,
883
884 .max_register = AFE_MAX_REGISTER,
885 .num_reg_defaults_raw = AFE_MAX_REGISTER,
886
887 .cache_type = REGCACHE_FLAT,
888};
889
890static irqreturn_t mt8183_afe_irq_handler(int irq_id, void *dev)
891{
892 struct mtk_base_afe *afe = dev;
893 struct mtk_base_afe_irq *irq;
894 unsigned int status;
895 unsigned int status_mcu;
896 unsigned int mcu_en;
897 int ret;
898 int i;
899 irqreturn_t irq_ret = IRQ_HANDLED;
900
901 /* get irq that is sent to MCU */
902 regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en);
903
904 ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status);
905 /* only care IRQ which is sent to MCU */
906 status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS;
907
908 if (ret || status_mcu == 0) {
909 dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n",
910 __func__, ret, status, mcu_en);
911
912 irq_ret = IRQ_NONE;
913 goto err_irq;
914 }
915
916 for (i = 0; i < MT8183_MEMIF_NUM; i++) {
917 struct mtk_base_afe_memif *memif = &afe->memif[i];
918
919 if (!memif->substream)
920 continue;
921
922 if (memif->irq_usage < 0)
923 continue;
924
925 irq = &afe->irqs[memif->irq_usage];
926
927 if (status_mcu & (1 << irq->irq_data->irq_en_shift))
928 snd_pcm_period_elapsed(memif->substream);
929 }
930
931err_irq:
932 /* clear irq */
933 regmap_write(afe->regmap,
934 AFE_IRQ_MCU_CLR,
935 status_mcu);
936
937 return irq_ret;
938}
939
940static int mt8183_afe_runtime_suspend(struct device *dev)
941{
942 struct mtk_base_afe *afe = dev_get_drvdata(dev);
943 struct mt8183_afe_private *afe_priv = afe->platform_priv;
944 unsigned int value;
945 int ret;
946
947 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
948 goto skip_regmap;
949
950 /* disable AFE */
951 regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x0);
952
953 ret = regmap_read_poll_timeout(afe->regmap,
954 AFE_DAC_MON,
955 value,
956 (value & AFE_ON_RETM_MASK_SFT) == 0,
957 20,
958 1 * 1000 * 1000);
959 if (ret)
960 dev_warn(afe->dev, "%s(), ret %d\n", __func__, ret);
961
962 /* make sure all irq status are cleared, twice intended */
963 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
964 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_CLR, 0xffff, 0xffff);
965
966 /* cache only */
967 regcache_cache_only(afe->regmap, true);
968 regcache_mark_dirty(afe->regmap);
969
970skip_regmap:
971 return mt8183_afe_disable_clock(afe);
972}
973
974static int mt8183_afe_runtime_resume(struct device *dev)
975{
976 struct mtk_base_afe *afe = dev_get_drvdata(dev);
977 struct mt8183_afe_private *afe_priv = afe->platform_priv;
978 int ret;
979
980 ret = mt8183_afe_enable_clock(afe);
981 if (ret)
982 return ret;
983
984 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)
985 goto skip_regmap;
986
987 regcache_cache_only(afe->regmap, false);
988 regcache_sync(afe->regmap);
989
990 /* enable audio sys DCM for power saving */
991 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 0x1 << 29, 0x1 << 29);
992
993 /* force cpu use 8_24 format when writing 32bit data */
994 regmap_update_bits(afe->regmap, AFE_MEMIF_MSB,
995 CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT);
996
997 /* set all output port to 24bit */
998 regmap_write(afe->regmap, AFE_CONN_24BIT, 0xffffffff);
999 regmap_write(afe->regmap, AFE_CONN_24BIT_1, 0xffffffff);
1000
1001 /* enable AFE */
1002 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1);
1003
1004skip_regmap:
1005 return 0;
1006}
1007
1008static int mt8183_afe_component_probe(struct snd_soc_component *component)
1009{
1010 return mtk_afe_add_sub_dai_control(component);
1011}
1012
1013static const struct snd_soc_component_driver mt8183_afe_component = {
1014 .name = AFE_PCM_NAME,
1015 .ops = &mtk_afe_pcm_ops,
1016 .pcm_new = mtk_afe_pcm_new,
1017 .pcm_free = mtk_afe_pcm_free,
1018 .probe = mt8183_afe_component_probe,
1019};
1020
1021static int mt8183_dai_memif_register(struct mtk_base_afe *afe)
1022{
1023 struct mtk_base_afe_dai *dai;
1024
1025 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
1026 if (!dai)
1027 return -ENOMEM;
1028
1029 list_add(&dai->list, &afe->sub_dais);
1030
1031 dai->dai_drivers = mt8183_memif_dai_driver;
1032 dai->num_dai_drivers = ARRAY_SIZE(mt8183_memif_dai_driver);
1033
1034 dai->dapm_widgets = mt8183_memif_widgets;
1035 dai->num_dapm_widgets = ARRAY_SIZE(mt8183_memif_widgets);
1036 dai->dapm_routes = mt8183_memif_routes;
1037 dai->num_dapm_routes = ARRAY_SIZE(mt8183_memif_routes);
1038 return 0;
1039}
1040
1041typedef int (*dai_register_cb)(struct mtk_base_afe *);
1042static const dai_register_cb dai_register_cbs[] = {
1043 mt8183_dai_adda_register,
1044 mt8183_dai_i2s_register,
1045 mt8183_dai_pcm_register,
1046 mt8183_dai_tdm_register,
1047 mt8183_dai_hostless_register,
1048 mt8183_dai_memif_register,
1049};
1050
1051static int mt8183_afe_pcm_dev_probe(struct platform_device *pdev)
1052{
1053 struct mtk_base_afe *afe;
1054 struct mt8183_afe_private *afe_priv;
1055 struct device *dev;
1056 int i, irq_id, ret;
1057
1058 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
1059 if (!afe)
1060 return -ENOMEM;
1061 platform_set_drvdata(pdev, afe);
1062
1063 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv),
1064 GFP_KERNEL);
1065 if (!afe->platform_priv)
1066 return -ENOMEM;
1067
1068 afe_priv = afe->platform_priv;
1069 afe->dev = &pdev->dev;
1070 dev = afe->dev;
1071
1072 /* initial audio related clock */
1073 ret = mt8183_init_clock(afe);
1074 if (ret) {
1075 dev_err(dev, "init clock error\n");
1076 return ret;
1077 }
1078
1079 pm_runtime_enable(dev);
1080
1081 /* regmap init */
1082 afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
1083 if (IS_ERR(afe->regmap)) {
1084 dev_err(dev, "could not get regmap from parent\n");
1085 return PTR_ERR(afe->regmap);
1086 }
1087 ret = regmap_attach_dev(dev, afe->regmap, &mt8183_afe_regmap_config);
1088 if (ret) {
1089 dev_warn(dev, "regmap_attach_dev fail, ret %d\n", ret);
1090 return ret;
1091 }
1092
1093 /* enable clock for regcache get default value from hw */
1094 afe_priv->pm_runtime_bypass_reg_ctl = true;
1095 pm_runtime_get_sync(&pdev->dev);
1096
1097 ret = regmap_reinit_cache(afe->regmap, &mt8183_afe_regmap_config);
1098 if (ret) {
1099 dev_err(dev, "regmap_reinit_cache fail, ret %d\n", ret);
1100 return ret;
1101 }
1102
1103 pm_runtime_put_sync(&pdev->dev);
1104 afe_priv->pm_runtime_bypass_reg_ctl = false;
1105
1106 regcache_cache_only(afe->regmap, true);
1107 regcache_mark_dirty(afe->regmap);
1108
1109 pm_runtime_get_sync(&pdev->dev);
1110
1111 /* init memif */
1112 afe->memif_size = MT8183_MEMIF_NUM;
1113 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif),
1114 GFP_KERNEL);
1115 if (!afe->memif)
1116 return -ENOMEM;
1117
1118 for (i = 0; i < afe->memif_size; i++) {
1119 afe->memif[i].data = &memif_data[i];
1120 afe->memif[i].irq_usage = -1;
1121 }
1122
1123 afe->memif[MT8183_MEMIF_HDMI].irq_usage = MT8183_IRQ_8;
1124 afe->memif[MT8183_MEMIF_HDMI].const_irq = 1;
1125
1126 mutex_init(&afe->irq_alloc_lock);
1127
1128 /* init memif */
1129 /* irq initialize */
1130 afe->irqs_size = MT8183_IRQ_NUM;
1131 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs),
1132 GFP_KERNEL);
1133 if (!afe->irqs)
1134 return -ENOMEM;
1135
1136 for (i = 0; i < afe->irqs_size; i++)
1137 afe->irqs[i].irq_data = &irq_data[i];
1138
1139 /* request irq */
1140 irq_id = platform_get_irq(pdev, 0);
1141 if (!irq_id) {
1142 dev_err(dev, "%s no irq found\n", dev->of_node->name);
1143 return -ENXIO;
1144 }
1145 ret = devm_request_irq(dev, irq_id, mt8183_afe_irq_handler,
1146 IRQF_TRIGGER_NONE, "asys-isr", (void *)afe);
1147 if (ret) {
1148 dev_err(dev, "could not request_irq for asys-isr\n");
1149 return ret;
1150 }
1151
1152 /* init sub_dais */
1153 INIT_LIST_HEAD(&afe->sub_dais);
1154
1155 for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) {
1156 ret = dai_register_cbs[i](afe);
1157 if (ret) {
1158 dev_warn(afe->dev, "dai register i %d fail, ret %d\n",
1159 i, ret);
1160 return ret;
1161 }
1162 }
1163
1164 /* init dai_driver and component_driver */
1165 ret = mtk_afe_combine_sub_dai(afe);
1166 if (ret) {
1167 dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n",
1168 ret);
1169 return ret;
1170 }
1171
1172 afe->mtk_afe_hardware = &mt8183_afe_hardware;
1173 afe->memif_fs = mt8183_memif_fs;
1174 afe->irq_fs = mt8183_irq_fs;
1175
1176 afe->runtime_resume = mt8183_afe_runtime_resume;
1177 afe->runtime_suspend = mt8183_afe_runtime_suspend;
1178
1179 /* register component */
1180 ret = devm_snd_soc_register_component(&pdev->dev,
1181 &mt8183_afe_component,
1182 NULL, 0);
1183 if (ret) {
1184 dev_warn(dev, "err_platform\n");
1185 return ret;
1186 }
1187
1188 ret = devm_snd_soc_register_component(afe->dev,
1189 &mt8183_afe_pcm_dai_component,
1190 afe->dai_drivers,
1191 afe->num_dai_drivers);
1192 if (ret) {
1193 dev_warn(dev, "err_dai_component\n");
1194 return ret;
1195 }
1196
1197 return ret;
1198}
1199
1200static int mt8183_afe_pcm_dev_remove(struct platform_device *pdev)
1201{
1202 pm_runtime_put_sync(&pdev->dev);
1203
1204 pm_runtime_disable(&pdev->dev);
1205 if (!pm_runtime_status_suspended(&pdev->dev))
1206 mt8183_afe_runtime_suspend(&pdev->dev);
1207 return 0;
1208}
1209
1210static const struct of_device_id mt8183_afe_pcm_dt_match[] = {
1211 { .compatible = "mediatek,mt8183-audio", },
1212 {},
1213};
1214MODULE_DEVICE_TABLE(of, mt8183_afe_pcm_dt_match);
1215
1216static const struct dev_pm_ops mt8183_afe_pm_ops = {
1217 SET_RUNTIME_PM_OPS(mt8183_afe_runtime_suspend,
1218 mt8183_afe_runtime_resume, NULL)
1219};
1220
1221static struct platform_driver mt8183_afe_pcm_driver = {
1222 .driver = {
1223 .name = "mt8183-audio",
1224 .of_match_table = mt8183_afe_pcm_dt_match,
1225#ifdef CONFIG_PM
1226 .pm = &mt8183_afe_pm_ops,
1227#endif
1228 },
1229 .probe = mt8183_afe_pcm_dev_probe,
1230 .remove = mt8183_afe_pcm_dev_remove,
1231};
1232
1233module_platform_driver(mt8183_afe_pcm_driver);
1234
1235MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8183");
1236MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>");
1237MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/mediatek/mt8183/mt8183-dai-adda.c b/sound/soc/mediatek/mt8183/mt8183-dai-adda.c
new file mode 100644
index 000000000000..017d7d1d9148
--- /dev/null
+++ b/sound/soc/mediatek/mt8183/mt8183-dai-adda.c
@@ -0,0 +1,501 @@
1// SPDX-License-Identifier: GPL-2.0
2//
3// MediaTek ALSA SoC Audio DAI ADDA Control
4//
5// Copyright (c) 2018 MediaTek Inc.
6// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7
8#include <linux/regmap.h>
9#include <linux/delay.h>
10#include "mt8183-afe-common.h"
11#include "mt8183-interconnection.h"
12#include "mt8183-reg.h"
13
14enum {
15 AUDIO_SDM_LEVEL_MUTE = 0,
16 AUDIO_SDM_LEVEL_NORMAL = 0x1d,
17 /* if you change level normal */
18 /* you need to change formula of hp impedance and dc trim too */
19};
20
21enum {
22 DELAY_DATA_MISO1 = 0,
23 DELAY_DATA_MISO2,
24};
25
26enum {
27 MTK_AFE_ADDA_DL_RATE_8K = 0,
28 MTK_AFE_ADDA_DL_RATE_11K = 1,
29 MTK_AFE_ADDA_DL_RATE_12K = 2,
30 MTK_AFE_ADDA_DL_RATE_16K = 3,
31 MTK_AFE_ADDA_DL_RATE_22K = 4,
32 MTK_AFE_ADDA_DL_RATE_24K = 5,
33 MTK_AFE_ADDA_DL_RATE_32K = 6,
34 MTK_AFE_ADDA_DL_RATE_44K = 7,
35 MTK_AFE_ADDA_DL_RATE_48K = 8,
36 MTK_AFE_ADDA_DL_RATE_96K = 9,
37 MTK_AFE_ADDA_DL_RATE_192K = 10,
38};
39
40enum {
41 MTK_AFE_ADDA_UL_RATE_8K = 0,
42 MTK_AFE_ADDA_UL_RATE_16K = 1,
43 MTK_AFE_ADDA_UL_RATE_32K = 2,
44 MTK_AFE_ADDA_UL_RATE_48K = 3,
45 MTK_AFE_ADDA_UL_RATE_96K = 4,
46 MTK_AFE_ADDA_UL_RATE_192K = 5,
47 MTK_AFE_ADDA_UL_RATE_48K_HD = 6,
48};
49
50static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe,
51 unsigned int rate)
52{
53 switch (rate) {
54 case 8000:
55 return MTK_AFE_ADDA_DL_RATE_8K;
56 case 11025:
57 return MTK_AFE_ADDA_DL_RATE_11K;
58 case 12000:
59 return MTK_AFE_ADDA_DL_RATE_12K;
60 case 16000:
61 return MTK_AFE_ADDA_DL_RATE_16K;
62 case 22050:
63 return MTK_AFE_ADDA_DL_RATE_22K;
64 case 24000:
65 return MTK_AFE_ADDA_DL_RATE_24K;
66 case 32000:
67 return MTK_AFE_ADDA_DL_RATE_32K;
68 case 44100:
69 return MTK_AFE_ADDA_DL_RATE_44K;
70 case 48000:
71 return MTK_AFE_ADDA_DL_RATE_48K;
72 case 96000:
73 return MTK_AFE_ADDA_DL_RATE_96K;
74 case 192000:
75 return MTK_AFE_ADDA_DL_RATE_192K;
76 default:
77 dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
78 __func__, rate);
79 return MTK_AFE_ADDA_DL_RATE_48K;
80 }
81}
82
83static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe,
84 unsigned int rate)
85{
86 switch (rate) {
87 case 8000:
88 return MTK_AFE_ADDA_UL_RATE_8K;
89 case 16000:
90 return MTK_AFE_ADDA_UL_RATE_16K;
91 case 32000:
92 return MTK_AFE_ADDA_UL_RATE_32K;
93 case 48000:
94 return MTK_AFE_ADDA_UL_RATE_48K;
95 case 96000:
96 return MTK_AFE_ADDA_UL_RATE_96K;
97 case 192000:
98 return MTK_AFE_ADDA_UL_RATE_192K;
99 default:
100 dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n",
101 __func__, rate);
102 return MTK_AFE_ADDA_UL_RATE_48K;
103 }
104}
105
106/* dai component */
107static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = {
108 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0),
109 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0),
110 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0),
111 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN3,
112 I_ADDA_UL_CH2, 1, 0),
113 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN3,
114 I_ADDA_UL_CH1, 1, 0),
115 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN3,
116 I_PCM_1_CAP_CH1, 1, 0),
117 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN3,
118 I_PCM_2_CAP_CH1, 1, 0),
119};
120
121static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = {
122 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0),
123 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN4, I_DL1_CH2, 1, 0),
124 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN4, I_DL2_CH1, 1, 0),
125 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN4, I_DL2_CH2, 1, 0),
126 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN4, I_DL3_CH1, 1, 0),
127 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN4, I_DL3_CH2, 1, 0),
128 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN4,
129 I_ADDA_UL_CH2, 1, 0),
130 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN4,
131 I_ADDA_UL_CH1, 1, 0),
132 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN4,
133 I_PCM_1_CAP_CH1, 1, 0),
134 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN4,
135 I_PCM_2_CAP_CH1, 1, 0),
136 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN4,
137 I_PCM_1_CAP_CH2, 1, 0),
138 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN4,
139 I_PCM_2_CAP_CH2, 1, 0),
140};
141
142static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w,
143 struct snd_kcontrol *kcontrol,
144 int event)
145{
146 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
147 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
148 struct mt8183_afe_private *afe_priv = afe->platform_priv;
149
150 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n",
151 __func__, w->name, event);
152
153 switch (event) {
154 case SND_SOC_DAPM_PRE_PMU:
155 /* update setting to dmic */
156 if (afe_priv->mtkaif_dmic) {
157 /* mtkaif_rxif_data_mode = 1, dmic */
158 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
159 0x1, 0x1);
160
161 /* dmic mode, 3.25M*/
162 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0,
163 0x0, 0xf << 20);
164 regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
165 0x0, 0x1 << 5);
166 regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
167 0x0, 0x3 << 14);
168
169 /* turn on dmic, ch1, ch2 */
170 regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
171 0x1 << 1, 0x1 << 1);
172 regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0,
173 0x3 << 21, 0x3 << 21);
174 }
175 break;
176 case SND_SOC_DAPM_POST_PMD:
177 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */
178 usleep_range(125, 135);
179
180 /* reset dmic */
181 afe_priv->mtkaif_dmic = 0;
182 break;
183 default:
184 break;
185 }
186
187 return 0;
188}
189
190/* mtkaif dmic */
191static const char * const mt8183_adda_off_on_str[] = {
192 "Off", "On"
193};
194
195static const struct soc_enum mt8183_adda_enum[] = {
196 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8183_adda_off_on_str),
197 mt8183_adda_off_on_str),
198};
199
200static int mt8183_adda_dmic_get(struct snd_kcontrol *kcontrol,
201 struct snd_ctl_elem_value *ucontrol)
202{
203 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
204 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
205 struct mt8183_afe_private *afe_priv = afe->platform_priv;
206
207 ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic;
208
209 return 0;
210}
211
212static int mt8183_adda_dmic_set(struct snd_kcontrol *kcontrol,
213 struct snd_ctl_elem_value *ucontrol)
214{
215 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
216 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
217 struct mt8183_afe_private *afe_priv = afe->platform_priv;
218 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
219
220 if (ucontrol->value.enumerated.item[0] >= e->items)
221 return -EINVAL;
222
223 afe_priv->mtkaif_dmic = ucontrol->value.integer.value[0];
224
225 dev_info(afe->dev, "%s(), kcontrol name %s, mtkaif_dmic %d\n",
226 __func__, kcontrol->id.name, afe_priv->mtkaif_dmic);
227
228 return 0;
229}
230
231static const struct snd_kcontrol_new mtk_adda_controls[] = {
232 SOC_ENUM_EXT("MTKAIF_DMIC", mt8183_adda_enum[0],
233 mt8183_adda_dmic_get, mt8183_adda_dmic_set),
234};
235
236enum {
237 SUPPLY_SEQ_ADDA_AFE_ON,
238 SUPPLY_SEQ_ADDA_DL_ON,
239 SUPPLY_SEQ_ADDA_UL_ON,
240};
241
242static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = {
243 /* adda */
244 SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0,
245 mtk_adda_dl_ch1_mix,
246 ARRAY_SIZE(mtk_adda_dl_ch1_mix)),
247 SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0,
248 mtk_adda_dl_ch2_mix,
249 ARRAY_SIZE(mtk_adda_dl_ch2_mix)),
250
251 SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON,
252 AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0,
253 NULL, 0),
254
255 SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON,
256 AFE_ADDA_DL_SRC2_CON0,
257 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0,
258 NULL, 0),
259
260 SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON,
261 AFE_ADDA_UL_SRC_CON0,
262 UL_SRC_ON_TMP_CTL_SFT, 0,
263 mtk_adda_ul_event,
264 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
265
266 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"),
267 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"),
268 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"),
269 SND_SOC_DAPM_CLOCK_SUPPLY("mtkaif_26m_clk"),
270};
271
272static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = {
273 /* playback */
274 {"ADDA_DL_CH1", "DL1_CH1", "DL1"},
275 {"ADDA_DL_CH2", "DL1_CH1", "DL1"},
276 {"ADDA_DL_CH2", "DL1_CH2", "DL1"},
277
278 {"ADDA_DL_CH1", "DL2_CH1", "DL2"},
279 {"ADDA_DL_CH2", "DL2_CH1", "DL2"},
280 {"ADDA_DL_CH2", "DL2_CH2", "DL2"},
281
282 {"ADDA_DL_CH1", "DL3_CH1", "DL3"},
283 {"ADDA_DL_CH2", "DL3_CH1", "DL3"},
284 {"ADDA_DL_CH2", "DL3_CH2", "DL3"},
285
286 {"ADDA Playback", NULL, "ADDA_DL_CH1"},
287 {"ADDA Playback", NULL, "ADDA_DL_CH2"},
288
289 /* adda enable */
290 {"ADDA Playback", NULL, "ADDA Enable"},
291 {"ADDA Playback", NULL, "ADDA Playback Enable"},
292 {"ADDA Capture", NULL, "ADDA Enable"},
293 {"ADDA Capture", NULL, "ADDA Capture Enable"},
294
295 /* clk */
296 {"ADDA Playback", NULL, "mtkaif_26m_clk"},
297 {"ADDA Playback", NULL, "aud_dac_clk"},
298 {"ADDA Playback", NULL, "aud_dac_predis_clk"},
299
300 {"ADDA Capture", NULL, "mtkaif_26m_clk"},
301 {"ADDA Capture", NULL, "aud_adc_clk"},
302};
303
304static int set_mtkaif_rx(struct mtk_base_afe *afe)
305{
306 struct mt8183_afe_private *afe_priv = afe->platform_priv;
307 int delay_data;
308 int delay_cycle;
309
310 switch (afe_priv->mtkaif_protocol) {
311 case MT8183_MTKAIF_PROTOCOL_2_CLK_P2:
312 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x38);
313 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x39);
314 /* mtkaif_rxif_clkinv_adc inverse for calibration */
315 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
316 0x80010000);
317
318 if (afe_priv->mtkaif_phase_cycle[0] >=
319 afe_priv->mtkaif_phase_cycle[1]) {
320 delay_data = DELAY_DATA_MISO1;
321 delay_cycle = afe_priv->mtkaif_phase_cycle[0] -
322 afe_priv->mtkaif_phase_cycle[1];
323 } else {
324 delay_data = DELAY_DATA_MISO2;
325 delay_cycle = afe_priv->mtkaif_phase_cycle[1] -
326 afe_priv->mtkaif_phase_cycle[0];
327 }
328
329 regmap_update_bits(afe->regmap,
330 AFE_ADDA_MTKAIF_RX_CFG2,
331 MTKAIF_RXIF_DELAY_DATA_MASK_SFT,
332 delay_data << MTKAIF_RXIF_DELAY_DATA_SFT);
333
334 regmap_update_bits(afe->regmap,
335 AFE_ADDA_MTKAIF_RX_CFG2,
336 MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT,
337 delay_cycle << MTKAIF_RXIF_DELAY_CYCLE_SFT);
338 break;
339 case MT8183_MTKAIF_PROTOCOL_2:
340 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31);
341 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0,
342 0x00010000);
343 break;
344 case MT8183_MTKAIF_PROTOCOL_1:
345 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31);
346 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x0);
347 default:
348 break;
349 }
350
351 return 0;
352}
353
354/* dai ops */
355static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream,
356 struct snd_pcm_hw_params *params,
357 struct snd_soc_dai *dai)
358{
359 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
360 unsigned int rate = params_rate(params);
361
362 dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n",
363 __func__, dai->id, substream->stream, rate);
364
365 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
366 unsigned int dl_src2_con0 = 0;
367 unsigned int dl_src2_con1 = 0;
368
369 /* clean predistortion */
370 regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0);
371 regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0);
372
373 /* set sampling rate */
374 dl_src2_con0 = adda_dl_rate_transform(afe, rate) << 28;
375
376 /* set output mode */
377 switch (rate) {
378 case 192000:
379 dl_src2_con0 |= (0x1 << 24); /* UP_SAMPLING_RATE_X2 */
380 dl_src2_con0 |= 1 << 14;
381 break;
382 case 96000:
383 dl_src2_con0 |= (0x2 << 24); /* UP_SAMPLING_RATE_X4 */
384 dl_src2_con0 |= 1 << 14;
385 break;
386 default:
387 dl_src2_con0 |= (0x3 << 24); /* UP_SAMPLING_RATE_X8 */
388 break;
389 }
390
391 /* turn off mute function */
392 dl_src2_con0 |= (0x03 << 11);
393
394 /* set voice input data if input sample rate is 8k or 16k */
395 if (rate == 8000 || rate == 16000)
396 dl_src2_con0 |= 0x01 << 5;
397
398 /* SA suggest apply -0.3db to audio/speech path */
399 dl_src2_con1 = 0xf74f0000;
400
401 /* turn on down-link gain */
402 dl_src2_con0 = dl_src2_con0 | (0x01 << 1);
403
404 regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON0, dl_src2_con0);
405 regmap_write(afe->regmap, AFE_ADDA_DL_SRC2_CON1, dl_src2_con1);
406
407 /* set sdm gain */
408 regmap_update_bits(afe->regmap,
409 AFE_ADDA_DL_SDM_DCCOMP_CON,
410 ATTGAIN_CTL_MASK_SFT,
411 AUDIO_SDM_LEVEL_NORMAL << ATTGAIN_CTL_SFT);
412 } else {
413 unsigned int voice_mode = 0;
414 unsigned int ul_src_con0 = 0; /* default value */
415
416 /* set mtkaif protocol */
417 set_mtkaif_rx(afe);
418
419 /* Using Internal ADC */
420 regmap_update_bits(afe->regmap,
421 AFE_ADDA_TOP_CON0,
422 0x1 << 0,
423 0x0 << 0);
424
425 voice_mode = adda_ul_rate_transform(afe, rate);
426
427 ul_src_con0 |= (voice_mode << 17) & (0x7 << 17);
428
429 regmap_write(afe->regmap, AFE_ADDA_UL_SRC_CON0, ul_src_con0);
430
431 /* mtkaif_rxif_data_mode = 0, amic */
432 regmap_update_bits(afe->regmap,
433 AFE_ADDA_MTKAIF_RX_CFG0,
434 0x1 << 0,
435 0x0 << 0);
436 }
437
438 return 0;
439}
440
441static const struct snd_soc_dai_ops mtk_dai_adda_ops = {
442 .hw_params = mtk_dai_adda_hw_params,
443};
444
445/* dai driver */
446#define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\
447 SNDRV_PCM_RATE_96000 |\
448 SNDRV_PCM_RATE_192000)
449
450#define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
451 SNDRV_PCM_RATE_16000 |\
452 SNDRV_PCM_RATE_32000 |\
453 SNDRV_PCM_RATE_48000)
454
455#define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
456 SNDRV_PCM_FMTBIT_S24_LE |\
457 SNDRV_PCM_FMTBIT_S32_LE)
458
459static struct snd_soc_dai_driver mtk_dai_adda_driver[] = {
460 {
461 .name = "ADDA",
462 .id = MT8183_DAI_ADDA,
463 .playback = {
464 .stream_name = "ADDA Playback",
465 .channels_min = 1,
466 .channels_max = 2,
467 .rates = MTK_ADDA_PLAYBACK_RATES,
468 .formats = MTK_ADDA_FORMATS,
469 },
470 .capture = {
471 .stream_name = "ADDA Capture",
472 .channels_min = 1,
473 .channels_max = 2,
474 .rates = MTK_ADDA_CAPTURE_RATES,
475 .formats = MTK_ADDA_FORMATS,
476 },
477 .ops = &mtk_dai_adda_ops,
478 },
479};
480
481int mt8183_dai_adda_register(struct mtk_base_afe *afe)
482{
483 struct mtk_base_afe_dai *dai;
484
485 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
486 if (!dai)
487 return -ENOMEM;
488
489 list_add(&dai->list, &afe->sub_dais);
490
491 dai->dai_drivers = mtk_dai_adda_driver;
492 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver);
493
494 dai->controls = mtk_adda_controls;
495 dai->num_controls = ARRAY_SIZE(mtk_adda_controls);
496 dai->dapm_widgets = mtk_dai_adda_widgets;
497 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets);
498 dai->dapm_routes = mtk_dai_adda_routes;
499 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes);
500 return 0;
501}
diff --git a/sound/soc/mediatek/mt8183/mt8183-dai-hostless.c b/sound/soc/mediatek/mt8183/mt8183-dai-hostless.c
new file mode 100644
index 000000000000..1667ad352d34
--- /dev/null
+++ b/sound/soc/mediatek/mt8183/mt8183-dai-hostless.c
@@ -0,0 +1,118 @@
1// SPDX-License-Identifier: GPL-2.0
2//
3// MediaTek ALSA SoC Audio DAI Hostless Control
4//
5// Copyright (c) 2018 MediaTek Inc.
6// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7
8#include "mt8183-afe-common.h"
9
10/* dai component */
11static const struct snd_soc_dapm_route mtk_dai_hostless_routes[] = {
12 /* Hostless ADDA Loopback */
13 {"ADDA_DL_CH1", "ADDA_UL_CH1", "Hostless LPBK DL"},
14 {"ADDA_DL_CH1", "ADDA_UL_CH2", "Hostless LPBK DL"},
15 {"ADDA_DL_CH2", "ADDA_UL_CH1", "Hostless LPBK DL"},
16 {"ADDA_DL_CH2", "ADDA_UL_CH2", "Hostless LPBK DL"},
17 {"Hostless LPBK UL", NULL, "ADDA Capture"},
18
19 /* Hostless Speech */
20 {"ADDA_DL_CH1", "PCM_1_CAP_CH1", "Hostless Speech DL"},
21 {"ADDA_DL_CH2", "PCM_1_CAP_CH1", "Hostless Speech DL"},
22 {"ADDA_DL_CH2", "PCM_1_CAP_CH2", "Hostless Speech DL"},
23 {"ADDA_DL_CH1", "PCM_2_CAP_CH1", "Hostless Speech DL"},
24 {"ADDA_DL_CH2", "PCM_2_CAP_CH1", "Hostless Speech DL"},
25 {"ADDA_DL_CH2", "PCM_2_CAP_CH2", "Hostless Speech DL"},
26 {"PCM_1_PB_CH1", "ADDA_UL_CH1", "Hostless Speech DL"},
27 {"PCM_1_PB_CH2", "ADDA_UL_CH2", "Hostless Speech DL"},
28 {"PCM_2_PB_CH1", "ADDA_UL_CH1", "Hostless Speech DL"},
29 {"PCM_2_PB_CH2", "ADDA_UL_CH2", "Hostless Speech DL"},
30
31 {"Hostless Speech UL", NULL, "PCM 1 Capture"},
32 {"Hostless Speech UL", NULL, "PCM 2 Capture"},
33 {"Hostless Speech UL", NULL, "ADDA Capture"},
34};
35
36/* dai ops */
37static int mtk_dai_hostless_startup(struct snd_pcm_substream *substream,
38 struct snd_soc_dai *dai)
39{
40 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
41
42 return snd_soc_set_runtime_hwparams(substream, afe->mtk_afe_hardware);
43}
44
45static const struct snd_soc_dai_ops mtk_dai_hostless_ops = {
46 .startup = mtk_dai_hostless_startup,
47};
48
49/* dai driver */
50#define MTK_HOSTLESS_RATES (SNDRV_PCM_RATE_8000_48000 |\
51 SNDRV_PCM_RATE_88200 |\
52 SNDRV_PCM_RATE_96000 |\
53 SNDRV_PCM_RATE_176400 |\
54 SNDRV_PCM_RATE_192000)
55
56#define MTK_HOSTLESS_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
57 SNDRV_PCM_FMTBIT_S24_LE |\
58 SNDRV_PCM_FMTBIT_S32_LE)
59
60static struct snd_soc_dai_driver mtk_dai_hostless_driver[] = {
61 {
62 .name = "Hostless LPBK DAI",
63 .id = MT8183_DAI_HOSTLESS_LPBK,
64 .playback = {
65 .stream_name = "Hostless LPBK DL",
66 .channels_min = 1,
67 .channels_max = 2,
68 .rates = MTK_HOSTLESS_RATES,
69 .formats = MTK_HOSTLESS_FORMATS,
70 },
71 .capture = {
72 .stream_name = "Hostless LPBK UL",
73 .channels_min = 1,
74 .channels_max = 2,
75 .rates = MTK_HOSTLESS_RATES,
76 .formats = MTK_HOSTLESS_FORMATS,
77 },
78 .ops = &mtk_dai_hostless_ops,
79 },
80 {
81 .name = "Hostless Speech DAI",
82 .id = MT8183_DAI_HOSTLESS_SPEECH,
83 .playback = {
84 .stream_name = "Hostless Speech DL",
85 .channels_min = 1,
86 .channels_max = 2,
87 .rates = MTK_HOSTLESS_RATES,
88 .formats = MTK_HOSTLESS_FORMATS,
89 },
90 .capture = {
91 .stream_name = "Hostless Speech UL",
92 .channels_min = 1,
93 .channels_max = 2,
94 .rates = MTK_HOSTLESS_RATES,
95 .formats = MTK_HOSTLESS_FORMATS,
96 },
97 .ops = &mtk_dai_hostless_ops,
98 },
99};
100
101int mt8183_dai_hostless_register(struct mtk_base_afe *afe)
102{
103 struct mtk_base_afe_dai *dai;
104
105 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
106 if (!dai)
107 return -ENOMEM;
108
109 list_add(&dai->list, &afe->sub_dais);
110
111 dai->dai_drivers = mtk_dai_hostless_driver;
112 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_hostless_driver);
113
114 dai->dapm_routes = mtk_dai_hostless_routes;
115 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_hostless_routes);
116
117 return 0;
118}
diff --git a/sound/soc/mediatek/mt8183/mt8183-dai-i2s.c b/sound/soc/mediatek/mt8183/mt8183-dai-i2s.c
new file mode 100644
index 000000000000..c25024f72e72
--- /dev/null
+++ b/sound/soc/mediatek/mt8183/mt8183-dai-i2s.c
@@ -0,0 +1,1040 @@
1// SPDX-License-Identifier: GPL-2.0
2//
3// MediaTek ALSA SoC Audio DAI I2S Control
4//
5// Copyright (c) 2018 MediaTek Inc.
6// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7
8#include <linux/bitops.h>
9#include <linux/regmap.h>
10#include <sound/pcm_params.h>
11#include "mt8183-afe-clk.h"
12#include "mt8183-afe-common.h"
13#include "mt8183-interconnection.h"
14#include "mt8183-reg.h"
15
16enum {
17 I2S_FMT_EIAJ = 0,
18 I2S_FMT_I2S = 1,
19};
20
21enum {
22 I2S_WLEN_16_BIT = 0,
23 I2S_WLEN_32_BIT = 1,
24};
25
26enum {
27 I2S_HD_NORMAL = 0,
28 I2S_HD_LOW_JITTER = 1,
29};
30
31enum {
32 I2S1_SEL_O28_O29 = 0,
33 I2S1_SEL_O03_O04 = 1,
34};
35
36enum {
37 I2S_IN_PAD_CONNSYS = 0,
38 I2S_IN_PAD_IO_MUX = 1,
39};
40
41struct mtk_afe_i2s_priv {
42 int id;
43 int rate; /* for determine which apll to use */
44 int low_jitter_en;
45
46 const char *share_property_name;
47 int share_i2s_id;
48
49 int mclk_id;
50 int mclk_rate;
51 int mclk_apll;
52};
53
54static unsigned int get_i2s_wlen(snd_pcm_format_t format)
55{
56 return snd_pcm_format_physical_width(format) <= 16 ?
57 I2S_WLEN_16_BIT : I2S_WLEN_32_BIT;
58}
59
60#define MTK_AFE_I2S0_KCONTROL_NAME "I2S0_HD_Mux"
61#define MTK_AFE_I2S1_KCONTROL_NAME "I2S1_HD_Mux"
62#define MTK_AFE_I2S2_KCONTROL_NAME "I2S2_HD_Mux"
63#define MTK_AFE_I2S3_KCONTROL_NAME "I2S3_HD_Mux"
64#define MTK_AFE_I2S5_KCONTROL_NAME "I2S5_HD_Mux"
65
66#define I2S0_HD_EN_W_NAME "I2S0_HD_EN"
67#define I2S1_HD_EN_W_NAME "I2S1_HD_EN"
68#define I2S2_HD_EN_W_NAME "I2S2_HD_EN"
69#define I2S3_HD_EN_W_NAME "I2S3_HD_EN"
70#define I2S5_HD_EN_W_NAME "I2S5_HD_EN"
71
72#define I2S0_MCLK_EN_W_NAME "I2S0_MCLK_EN"
73#define I2S1_MCLK_EN_W_NAME "I2S1_MCLK_EN"
74#define I2S2_MCLK_EN_W_NAME "I2S2_MCLK_EN"
75#define I2S3_MCLK_EN_W_NAME "I2S3_MCLK_EN"
76#define I2S5_MCLK_EN_W_NAME "I2S5_MCLK_EN"
77
78static int get_i2s_id_by_name(struct mtk_base_afe *afe,
79 const char *name)
80{
81 if (strncmp(name, "I2S0", 4) == 0)
82 return MT8183_DAI_I2S_0;
83 else if (strncmp(name, "I2S1", 4) == 0)
84 return MT8183_DAI_I2S_1;
85 else if (strncmp(name, "I2S2", 4) == 0)
86 return MT8183_DAI_I2S_2;
87 else if (strncmp(name, "I2S3", 4) == 0)
88 return MT8183_DAI_I2S_3;
89 else if (strncmp(name, "I2S5", 4) == 0)
90 return MT8183_DAI_I2S_5;
91 else
92 return -EINVAL;
93}
94
95static struct mtk_afe_i2s_priv *get_i2s_priv_by_name(struct mtk_base_afe *afe,
96 const char *name)
97{
98 struct mt8183_afe_private *afe_priv = afe->platform_priv;
99 int dai_id = get_i2s_id_by_name(afe, name);
100
101 if (dai_id < 0)
102 return NULL;
103
104 return afe_priv->dai_priv[dai_id];
105}
106
107/* low jitter control */
108static const char * const mt8183_i2s_hd_str[] = {
109 "Normal", "Low_Jitter"
110};
111
112static const struct soc_enum mt8183_i2s_enum[] = {
113 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mt8183_i2s_hd_str),
114 mt8183_i2s_hd_str),
115};
116
117static int mt8183_i2s_hd_get(struct snd_kcontrol *kcontrol,
118 struct snd_ctl_elem_value *ucontrol)
119{
120 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
121 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
122 struct mtk_afe_i2s_priv *i2s_priv;
123
124 i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name);
125
126 if (!i2s_priv) {
127 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
128 return -EINVAL;
129 }
130
131 ucontrol->value.integer.value[0] = i2s_priv->low_jitter_en;
132
133 return 0;
134}
135
136static int mt8183_i2s_hd_set(struct snd_kcontrol *kcontrol,
137 struct snd_ctl_elem_value *ucontrol)
138{
139 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
140 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
141 struct mtk_afe_i2s_priv *i2s_priv;
142 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
143 int hd_en;
144
145 if (ucontrol->value.enumerated.item[0] >= e->items)
146 return -EINVAL;
147
148 hd_en = ucontrol->value.integer.value[0];
149
150 dev_info(afe->dev, "%s(), kcontrol name %s, hd_en %d\n",
151 __func__, kcontrol->id.name, hd_en);
152
153 i2s_priv = get_i2s_priv_by_name(afe, kcontrol->id.name);
154
155 if (!i2s_priv) {
156 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
157 return -EINVAL;
158 }
159
160 i2s_priv->low_jitter_en = hd_en;
161
162 return 0;
163}
164
165static const struct snd_kcontrol_new mtk_dai_i2s_controls[] = {
166 SOC_ENUM_EXT(MTK_AFE_I2S0_KCONTROL_NAME, mt8183_i2s_enum[0],
167 mt8183_i2s_hd_get, mt8183_i2s_hd_set),
168 SOC_ENUM_EXT(MTK_AFE_I2S1_KCONTROL_NAME, mt8183_i2s_enum[0],
169 mt8183_i2s_hd_get, mt8183_i2s_hd_set),
170 SOC_ENUM_EXT(MTK_AFE_I2S2_KCONTROL_NAME, mt8183_i2s_enum[0],
171 mt8183_i2s_hd_get, mt8183_i2s_hd_set),
172 SOC_ENUM_EXT(MTK_AFE_I2S3_KCONTROL_NAME, mt8183_i2s_enum[0],
173 mt8183_i2s_hd_get, mt8183_i2s_hd_set),
174 SOC_ENUM_EXT(MTK_AFE_I2S5_KCONTROL_NAME, mt8183_i2s_enum[0],
175 mt8183_i2s_hd_get, mt8183_i2s_hd_set),
176};
177
178/* dai component */
179/* interconnection */
180static const struct snd_kcontrol_new mtk_i2s3_ch1_mix[] = {
181 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN0, I_DL1_CH1, 1, 0),
182 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN0, I_DL2_CH1, 1, 0),
183 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN0, I_DL3_CH1, 1, 0),
184 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN0,
185 I_ADDA_UL_CH1, 1, 0),
186 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN0,
187 I_PCM_1_CAP_CH1, 1, 0),
188 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN0,
189 I_PCM_2_CAP_CH1, 1, 0),
190};
191
192static const struct snd_kcontrol_new mtk_i2s3_ch2_mix[] = {
193 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN1, I_DL1_CH2, 1, 0),
194 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN1, I_DL2_CH2, 1, 0),
195 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN1, I_DL3_CH2, 1, 0),
196 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN1,
197 I_ADDA_UL_CH2, 1, 0),
198 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN1,
199 I_PCM_1_CAP_CH1, 1, 0),
200 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN1,
201 I_PCM_2_CAP_CH1, 1, 0),
202 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN1,
203 I_PCM_1_CAP_CH2, 1, 0),
204 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN1,
205 I_PCM_2_CAP_CH2, 1, 0),
206};
207
208static const struct snd_kcontrol_new mtk_i2s1_ch1_mix[] = {
209 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN28, I_DL1_CH1, 1, 0),
210 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN28, I_DL2_CH1, 1, 0),
211 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN28, I_DL3_CH1, 1, 0),
212 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN28,
213 I_ADDA_UL_CH1, 1, 0),
214 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN28,
215 I_PCM_1_CAP_CH1, 1, 0),
216 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN28,
217 I_PCM_2_CAP_CH1, 1, 0),
218};
219
220static const struct snd_kcontrol_new mtk_i2s1_ch2_mix[] = {
221 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN29, I_DL1_CH2, 1, 0),
222 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN29, I_DL2_CH2, 1, 0),
223 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN29, I_DL3_CH2, 1, 0),
224 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN29,
225 I_ADDA_UL_CH2, 1, 0),
226 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN29,
227 I_PCM_1_CAP_CH1, 1, 0),
228 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN29,
229 I_PCM_2_CAP_CH1, 1, 0),
230 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN29,
231 I_PCM_1_CAP_CH2, 1, 0),
232 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN29,
233 I_PCM_2_CAP_CH2, 1, 0),
234};
235
236static const struct snd_kcontrol_new mtk_i2s5_ch1_mix[] = {
237 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN30, I_DL1_CH1, 1, 0),
238 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN30, I_DL2_CH1, 1, 0),
239 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN30, I_DL3_CH1, 1, 0),
240 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN30,
241 I_ADDA_UL_CH1, 1, 0),
242 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN30,
243 I_PCM_1_CAP_CH1, 1, 0),
244 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN30,
245 I_PCM_2_CAP_CH1, 1, 0),
246};
247
248static const struct snd_kcontrol_new mtk_i2s5_ch2_mix[] = {
249 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN31, I_DL1_CH2, 1, 0),
250 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN31, I_DL2_CH2, 1, 0),
251 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN31, I_DL3_CH2, 1, 0),
252 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN31,
253 I_ADDA_UL_CH2, 1, 0),
254 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN31,
255 I_PCM_1_CAP_CH1, 1, 0),
256 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN31,
257 I_PCM_2_CAP_CH1, 1, 0),
258 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN31,
259 I_PCM_1_CAP_CH2, 1, 0),
260 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN31,
261 I_PCM_2_CAP_CH2, 1, 0),
262};
263
264enum {
265 SUPPLY_SEQ_APLL,
266 SUPPLY_SEQ_I2S_MCLK_EN,
267 SUPPLY_SEQ_I2S_HD_EN,
268 SUPPLY_SEQ_I2S_EN,
269};
270
271static int mtk_apll_event(struct snd_soc_dapm_widget *w,
272 struct snd_kcontrol *kcontrol,
273 int event)
274{
275 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
276 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
277
278 dev_info(cmpnt->dev, "%s(), name %s, event 0x%x\n",
279 __func__, w->name, event);
280
281 switch (event) {
282 case SND_SOC_DAPM_PRE_PMU:
283 if (strcmp(w->name, APLL1_W_NAME) == 0)
284 mt8183_apll1_enable(afe);
285 else
286 mt8183_apll2_enable(afe);
287 break;
288 case SND_SOC_DAPM_POST_PMD:
289 if (strcmp(w->name, APLL1_W_NAME) == 0)
290 mt8183_apll1_disable(afe);
291 else
292 mt8183_apll2_disable(afe);
293 break;
294 default:
295 break;
296 }
297
298 return 0;
299}
300
301static int mtk_mclk_en_event(struct snd_soc_dapm_widget *w,
302 struct snd_kcontrol *kcontrol,
303 int event)
304{
305 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
306 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
307 struct mtk_afe_i2s_priv *i2s_priv;
308
309 dev_info(cmpnt->dev, "%s(), name %s, event 0x%x\n",
310 __func__, w->name, event);
311
312 i2s_priv = get_i2s_priv_by_name(afe, w->name);
313
314 if (!i2s_priv) {
315 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
316 return -EINVAL;
317 }
318
319 switch (event) {
320 case SND_SOC_DAPM_PRE_PMU:
321 mt8183_mck_enable(afe, i2s_priv->mclk_id, i2s_priv->mclk_rate);
322 break;
323 case SND_SOC_DAPM_POST_PMD:
324 i2s_priv->mclk_rate = 0;
325 mt8183_mck_disable(afe, i2s_priv->mclk_id);
326 break;
327 default:
328 break;
329 }
330
331 return 0;
332}
333
334static const struct snd_soc_dapm_widget mtk_dai_i2s_widgets[] = {
335 SND_SOC_DAPM_MIXER("I2S1_CH1", SND_SOC_NOPM, 0, 0,
336 mtk_i2s1_ch1_mix,
337 ARRAY_SIZE(mtk_i2s1_ch1_mix)),
338 SND_SOC_DAPM_MIXER("I2S1_CH2", SND_SOC_NOPM, 0, 0,
339 mtk_i2s1_ch2_mix,
340 ARRAY_SIZE(mtk_i2s1_ch2_mix)),
341
342 SND_SOC_DAPM_MIXER("I2S3_CH1", SND_SOC_NOPM, 0, 0,
343 mtk_i2s3_ch1_mix,
344 ARRAY_SIZE(mtk_i2s3_ch1_mix)),
345 SND_SOC_DAPM_MIXER("I2S3_CH2", SND_SOC_NOPM, 0, 0,
346 mtk_i2s3_ch2_mix,
347 ARRAY_SIZE(mtk_i2s3_ch2_mix)),
348
349 SND_SOC_DAPM_MIXER("I2S5_CH1", SND_SOC_NOPM, 0, 0,
350 mtk_i2s5_ch1_mix,
351 ARRAY_SIZE(mtk_i2s5_ch1_mix)),
352 SND_SOC_DAPM_MIXER("I2S5_CH2", SND_SOC_NOPM, 0, 0,
353 mtk_i2s5_ch2_mix,
354 ARRAY_SIZE(mtk_i2s5_ch2_mix)),
355
356 /* i2s en*/
357 SND_SOC_DAPM_SUPPLY_S("I2S0_EN", SUPPLY_SEQ_I2S_EN,
358 AFE_I2S_CON, I2S_EN_SFT, 0,
359 NULL, 0),
360 SND_SOC_DAPM_SUPPLY_S("I2S1_EN", SUPPLY_SEQ_I2S_EN,
361 AFE_I2S_CON1, I2S_EN_SFT, 0,
362 NULL, 0),
363 SND_SOC_DAPM_SUPPLY_S("I2S2_EN", SUPPLY_SEQ_I2S_EN,
364 AFE_I2S_CON2, I2S_EN_SFT, 0,
365 NULL, 0),
366 SND_SOC_DAPM_SUPPLY_S("I2S3_EN", SUPPLY_SEQ_I2S_EN,
367 AFE_I2S_CON3, I2S_EN_SFT, 0,
368 NULL, 0),
369 SND_SOC_DAPM_SUPPLY_S("I2S5_EN", SUPPLY_SEQ_I2S_EN,
370 AFE_I2S_CON4, I2S5_EN_SFT, 0,
371 NULL, 0),
372 /* i2s hd en */
373 SND_SOC_DAPM_SUPPLY_S(I2S0_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
374 AFE_I2S_CON, I2S1_HD_EN_SFT, 0,
375 NULL, 0),
376 SND_SOC_DAPM_SUPPLY_S(I2S1_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
377 AFE_I2S_CON1, I2S2_HD_EN_SFT, 0,
378 NULL, 0),
379 SND_SOC_DAPM_SUPPLY_S(I2S2_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
380 AFE_I2S_CON2, I2S3_HD_EN_SFT, 0,
381 NULL, 0),
382 SND_SOC_DAPM_SUPPLY_S(I2S3_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
383 AFE_I2S_CON3, I2S4_HD_EN_SFT, 0,
384 NULL, 0),
385 SND_SOC_DAPM_SUPPLY_S(I2S5_HD_EN_W_NAME, SUPPLY_SEQ_I2S_HD_EN,
386 AFE_I2S_CON4, I2S5_HD_EN_SFT, 0,
387 NULL, 0),
388
389 /* i2s mclk en */
390 SND_SOC_DAPM_SUPPLY_S(I2S0_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
391 SND_SOC_NOPM, 0, 0,
392 mtk_mclk_en_event,
393 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
394 SND_SOC_DAPM_SUPPLY_S(I2S1_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
395 SND_SOC_NOPM, 0, 0,
396 mtk_mclk_en_event,
397 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
398 SND_SOC_DAPM_SUPPLY_S(I2S2_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
399 SND_SOC_NOPM, 0, 0,
400 mtk_mclk_en_event,
401 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
402 SND_SOC_DAPM_SUPPLY_S(I2S3_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
403 SND_SOC_NOPM, 0, 0,
404 mtk_mclk_en_event,
405 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
406 SND_SOC_DAPM_SUPPLY_S(I2S5_MCLK_EN_W_NAME, SUPPLY_SEQ_I2S_MCLK_EN,
407 SND_SOC_NOPM, 0, 0,
408 mtk_mclk_en_event,
409 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
410
411 /* apll */
412 SND_SOC_DAPM_SUPPLY_S(APLL1_W_NAME, SUPPLY_SEQ_APLL,
413 SND_SOC_NOPM, 0, 0,
414 mtk_apll_event,
415 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
416 SND_SOC_DAPM_SUPPLY_S(APLL2_W_NAME, SUPPLY_SEQ_APLL,
417 SND_SOC_NOPM, 0, 0,
418 mtk_apll_event,
419 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
420};
421
422static int mtk_afe_i2s_share_connect(struct snd_soc_dapm_widget *source,
423 struct snd_soc_dapm_widget *sink)
424{
425 struct snd_soc_dapm_widget *w = sink;
426 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
427 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
428 struct mtk_afe_i2s_priv *i2s_priv;
429
430 i2s_priv = get_i2s_priv_by_name(afe, sink->name);
431
432 if (!i2s_priv) {
433 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
434 return 0;
435 }
436
437 if (i2s_priv->share_i2s_id < 0)
438 return 0;
439
440 return i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name);
441}
442
443static int mtk_afe_i2s_hd_connect(struct snd_soc_dapm_widget *source,
444 struct snd_soc_dapm_widget *sink)
445{
446 struct snd_soc_dapm_widget *w = sink;
447 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
448 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
449 struct mtk_afe_i2s_priv *i2s_priv;
450
451 i2s_priv = get_i2s_priv_by_name(afe, sink->name);
452
453 if (!i2s_priv) {
454 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
455 return 0;
456 }
457
458 if (get_i2s_id_by_name(afe, sink->name) ==
459 get_i2s_id_by_name(afe, source->name))
460 return i2s_priv->low_jitter_en;
461
462 /* check if share i2s need hd en */
463 if (i2s_priv->share_i2s_id < 0)
464 return 0;
465
466 if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name))
467 return i2s_priv->low_jitter_en;
468
469 return 0;
470}
471
472static int mtk_afe_i2s_apll_connect(struct snd_soc_dapm_widget *source,
473 struct snd_soc_dapm_widget *sink)
474{
475 struct snd_soc_dapm_widget *w = sink;
476 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
477 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
478 struct mtk_afe_i2s_priv *i2s_priv;
479 int cur_apll;
480 int i2s_need_apll;
481
482 i2s_priv = get_i2s_priv_by_name(afe, w->name);
483
484 if (!i2s_priv) {
485 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
486 return 0;
487 }
488
489 /* which apll */
490 cur_apll = mt8183_get_apll_by_name(afe, source->name);
491
492 /* choose APLL from i2s rate */
493 i2s_need_apll = mt8183_get_apll_by_rate(afe, i2s_priv->rate);
494
495 return (i2s_need_apll == cur_apll) ? 1 : 0;
496}
497
498static int mtk_afe_i2s_mclk_connect(struct snd_soc_dapm_widget *source,
499 struct snd_soc_dapm_widget *sink)
500{
501 struct snd_soc_dapm_widget *w = sink;
502 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
503 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
504 struct mtk_afe_i2s_priv *i2s_priv;
505
506 i2s_priv = get_i2s_priv_by_name(afe, sink->name);
507
508 if (!i2s_priv) {
509 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
510 return 0;
511 }
512
513 if (get_i2s_id_by_name(afe, sink->name) ==
514 get_i2s_id_by_name(afe, source->name))
515 return (i2s_priv->mclk_rate > 0) ? 1 : 0;
516
517 /* check if share i2s need mclk */
518 if (i2s_priv->share_i2s_id < 0)
519 return 0;
520
521 if (i2s_priv->share_i2s_id == get_i2s_id_by_name(afe, source->name))
522 return (i2s_priv->mclk_rate > 0) ? 1 : 0;
523
524 return 0;
525}
526
527static int mtk_afe_mclk_apll_connect(struct snd_soc_dapm_widget *source,
528 struct snd_soc_dapm_widget *sink)
529{
530 struct snd_soc_dapm_widget *w = sink;
531 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
532 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
533 struct mtk_afe_i2s_priv *i2s_priv;
534 int cur_apll;
535
536 i2s_priv = get_i2s_priv_by_name(afe, w->name);
537
538 if (!i2s_priv) {
539 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
540 return 0;
541 }
542
543 /* which apll */
544 cur_apll = mt8183_get_apll_by_name(afe, source->name);
545
546 return (i2s_priv->mclk_apll == cur_apll) ? 1 : 0;
547}
548
549static const struct snd_soc_dapm_route mtk_dai_i2s_routes[] = {
550 /* i2s0 */
551 {"I2S0", NULL, "I2S0_EN"},
552 {"I2S0", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
553 {"I2S0", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
554 {"I2S0", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
555 {"I2S0", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
556
557 {"I2S0", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
558 {"I2S0", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
559 {"I2S0", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
560 {"I2S0", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
561 {"I2S0", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
562 {I2S0_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
563 {I2S0_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
564
565 {"I2S0", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
566 {"I2S0", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
567 {"I2S0", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
568 {"I2S0", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
569 {"I2S0", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
570 {I2S0_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
571 {I2S0_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
572
573 /* i2s1 */
574 {"I2S1_CH1", "DL1_CH1", "DL1"},
575 {"I2S1_CH2", "DL1_CH2", "DL1"},
576
577 {"I2S1_CH1", "DL2_CH1", "DL2"},
578 {"I2S1_CH2", "DL2_CH2", "DL2"},
579
580 {"I2S1_CH1", "DL3_CH1", "DL3"},
581 {"I2S1_CH2", "DL3_CH2", "DL3"},
582
583 {"I2S1", NULL, "I2S1_CH1"},
584 {"I2S1", NULL, "I2S1_CH2"},
585
586 {"I2S1", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
587 {"I2S1", NULL, "I2S1_EN"},
588 {"I2S1", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
589 {"I2S1", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
590 {"I2S1", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
591
592 {"I2S1", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
593 {"I2S1", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
594 {"I2S1", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
595 {"I2S1", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
596 {"I2S1", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
597 {I2S1_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
598 {I2S1_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
599
600 {"I2S1", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
601 {"I2S1", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
602 {"I2S1", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
603 {"I2S1", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
604 {"I2S1", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
605 {I2S1_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
606 {I2S1_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
607
608 /* i2s2 */
609 {"I2S2", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
610 {"I2S2", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
611 {"I2S2", NULL, "I2S2_EN"},
612 {"I2S2", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
613 {"I2S2", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
614
615 {"I2S2", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
616 {"I2S2", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
617 {"I2S2", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
618 {"I2S2", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
619 {"I2S2", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
620 {I2S2_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
621 {I2S2_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
622
623 {"I2S2", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
624 {"I2S2", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
625 {"I2S2", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
626 {"I2S2", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
627 {"I2S2", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
628 {I2S2_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
629 {I2S2_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
630
631 /* i2s3 */
632 {"I2S3_CH1", "DL1_CH1", "DL1"},
633 {"I2S3_CH2", "DL1_CH2", "DL1"},
634
635 {"I2S3_CH1", "DL2_CH1", "DL2"},
636 {"I2S3_CH2", "DL2_CH2", "DL2"},
637
638 {"I2S3_CH1", "DL3_CH1", "DL3"},
639 {"I2S3_CH2", "DL3_CH2", "DL3"},
640
641 {"I2S3", NULL, "I2S3_CH1"},
642 {"I2S3", NULL, "I2S3_CH2"},
643
644 {"I2S3", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
645 {"I2S3", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
646 {"I2S3", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
647 {"I2S3", NULL, "I2S3_EN"},
648 {"I2S3", NULL, "I2S5_EN", mtk_afe_i2s_share_connect},
649
650 {"I2S3", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
651 {"I2S3", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
652 {"I2S3", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
653 {"I2S3", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
654 {"I2S3", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
655 {I2S3_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
656 {I2S3_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
657
658 {"I2S3", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
659 {"I2S3", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
660 {"I2S3", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
661 {"I2S3", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
662 {"I2S3", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
663 {I2S3_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
664 {I2S3_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
665
666 /* i2s5 */
667 {"I2S5_CH1", "DL1_CH1", "DL1"},
668 {"I2S5_CH2", "DL1_CH2", "DL1"},
669
670 {"I2S5_CH1", "DL2_CH1", "DL2"},
671 {"I2S5_CH2", "DL2_CH2", "DL2"},
672
673 {"I2S5_CH1", "DL3_CH1", "DL3"},
674 {"I2S5_CH2", "DL3_CH2", "DL3"},
675
676 {"I2S5", NULL, "I2S5_CH1"},
677 {"I2S5", NULL, "I2S5_CH2"},
678
679 {"I2S5", NULL, "I2S0_EN", mtk_afe_i2s_share_connect},
680 {"I2S5", NULL, "I2S1_EN", mtk_afe_i2s_share_connect},
681 {"I2S5", NULL, "I2S2_EN", mtk_afe_i2s_share_connect},
682 {"I2S5", NULL, "I2S3_EN", mtk_afe_i2s_share_connect},
683 {"I2S5", NULL, "I2S5_EN"},
684
685 {"I2S5", NULL, I2S0_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
686 {"I2S5", NULL, I2S1_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
687 {"I2S5", NULL, I2S2_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
688 {"I2S5", NULL, I2S3_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
689 {"I2S5", NULL, I2S5_HD_EN_W_NAME, mtk_afe_i2s_hd_connect},
690 {I2S5_HD_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_i2s_apll_connect},
691 {I2S5_HD_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_i2s_apll_connect},
692
693 {"I2S5", NULL, I2S0_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
694 {"I2S5", NULL, I2S1_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
695 {"I2S5", NULL, I2S2_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
696 {"I2S5", NULL, I2S3_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
697 {"I2S5", NULL, I2S5_MCLK_EN_W_NAME, mtk_afe_i2s_mclk_connect},
698 {I2S5_MCLK_EN_W_NAME, NULL, APLL1_W_NAME, mtk_afe_mclk_apll_connect},
699 {I2S5_MCLK_EN_W_NAME, NULL, APLL2_W_NAME, mtk_afe_mclk_apll_connect},
700};
701
702/* dai ops */
703static int mtk_dai_i2s_config(struct mtk_base_afe *afe,
704 struct snd_pcm_hw_params *params,
705 int i2s_id)
706{
707 struct mt8183_afe_private *afe_priv = afe->platform_priv;
708 struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[i2s_id];
709
710 unsigned int rate = params_rate(params);
711 unsigned int rate_reg = mt8183_rate_transform(afe->dev,
712 rate, i2s_id);
713 snd_pcm_format_t format = params_format(params);
714 unsigned int i2s_con = 0;
715 int ret = 0;
716
717 dev_info(afe->dev, "%s(), id %d, rate %d, format %d\n",
718 __func__,
719 i2s_id,
720 rate, format);
721
722 if (i2s_priv)
723 i2s_priv->rate = rate;
724 else
725 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
726
727 switch (i2s_id) {
728 case MT8183_DAI_I2S_0:
729 regmap_update_bits(afe->regmap, AFE_DAC_CON1,
730 I2S_MODE_MASK_SFT, rate_reg << I2S_MODE_SFT);
731 i2s_con = I2S_IN_PAD_IO_MUX << I2SIN_PAD_SEL_SFT;
732 i2s_con |= I2S_FMT_I2S << I2S_FMT_SFT;
733 i2s_con |= get_i2s_wlen(format) << I2S_WLEN_SFT;
734 regmap_update_bits(afe->regmap, AFE_I2S_CON,
735 0xffffeffe, i2s_con);
736 break;
737 case MT8183_DAI_I2S_1:
738 i2s_con = I2S1_SEL_O28_O29 << I2S2_SEL_O03_O04_SFT;
739 i2s_con |= rate_reg << I2S2_OUT_MODE_SFT;
740 i2s_con |= I2S_FMT_I2S << I2S2_FMT_SFT;
741 i2s_con |= get_i2s_wlen(format) << I2S2_WLEN_SFT;
742 regmap_update_bits(afe->regmap, AFE_I2S_CON1,
743 0xffffeffe, i2s_con);
744 break;
745 case MT8183_DAI_I2S_2:
746 i2s_con = 8 << I2S3_UPDATE_WORD_SFT;
747 i2s_con |= rate_reg << I2S3_OUT_MODE_SFT;
748 i2s_con |= I2S_FMT_I2S << I2S3_FMT_SFT;
749 i2s_con |= get_i2s_wlen(format) << I2S3_WLEN_SFT;
750 regmap_update_bits(afe->regmap, AFE_I2S_CON2,
751 0xffffeffe, i2s_con);
752 break;
753 case MT8183_DAI_I2S_3:
754 i2s_con = rate_reg << I2S4_OUT_MODE_SFT;
755 i2s_con |= I2S_FMT_I2S << I2S4_FMT_SFT;
756 i2s_con |= get_i2s_wlen(format) << I2S4_WLEN_SFT;
757 regmap_update_bits(afe->regmap, AFE_I2S_CON3,
758 0xffffeffe, i2s_con);
759 break;
760 case MT8183_DAI_I2S_5:
761 i2s_con = rate_reg << I2S5_OUT_MODE_SFT;
762 i2s_con |= I2S_FMT_I2S << I2S5_FMT_SFT;
763 i2s_con |= get_i2s_wlen(format) << I2S5_WLEN_SFT;
764 regmap_update_bits(afe->regmap, AFE_I2S_CON4,
765 0xffffeffe, i2s_con);
766 break;
767 default:
768 dev_warn(afe->dev, "%s(), id %d not support\n",
769 __func__, i2s_id);
770 return -EINVAL;
771 }
772
773 /* set share i2s */
774 if (i2s_priv && i2s_priv->share_i2s_id >= 0)
775 ret = mtk_dai_i2s_config(afe, params, i2s_priv->share_i2s_id);
776
777 return ret;
778}
779
780static int mtk_dai_i2s_hw_params(struct snd_pcm_substream *substream,
781 struct snd_pcm_hw_params *params,
782 struct snd_soc_dai *dai)
783{
784 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
785
786 return mtk_dai_i2s_config(afe, params, dai->id);
787}
788
789static int mtk_dai_i2s_set_sysclk(struct snd_soc_dai *dai,
790 int clk_id, unsigned int freq, int dir)
791{
792 struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
793 struct mt8183_afe_private *afe_priv = afe->platform_priv;
794 struct mtk_afe_i2s_priv *i2s_priv = afe_priv->dai_priv[dai->id];
795 int apll;
796 int apll_rate;
797
798 if (!i2s_priv) {
799 dev_warn(afe->dev, "%s(), i2s_priv == NULL", __func__);
800 return -EINVAL;
801 }
802
803 if (dir != SND_SOC_CLOCK_OUT) {
804 dev_warn(afe->dev, "%s(), dir != SND_SOC_CLOCK_OUT", __func__);
805 return -EINVAL;
806 }
807
808 dev_info(afe->dev, "%s(), freq %d\n", __func__, freq);
809
810 apll = mt8183_get_apll_by_rate(afe, freq);
811 apll_rate = mt8183_get_apll_rate(afe, apll);
812
813 if (freq > apll_rate) {
814 dev_warn(afe->dev, "%s(), freq > apll rate", __func__);
815 return -EINVAL;
816 }
817
818 if (apll_rate % freq != 0) {
819 dev_warn(afe->dev, "%s(), APLL cannot generate freq Hz",
820 __func__);
821 return -EINVAL;
822 }
823
824 i2s_priv->mclk_rate = freq;
825 i2s_priv->mclk_apll = apll;
826
827 if (i2s_priv->share_i2s_id > 0) {
828 struct mtk_afe_i2s_priv *share_i2s_priv;
829
830 share_i2s_priv = afe_priv->dai_priv[i2s_priv->share_i2s_id];
831 if (!share_i2s_priv) {
832 dev_warn(afe->dev, "%s(), share_i2s_priv == NULL",
833 __func__);
834 return -EINVAL;
835 }
836
837 share_i2s_priv->mclk_rate = i2s_priv->mclk_rate;
838 share_i2s_priv->mclk_apll = i2s_priv->mclk_apll;
839 }
840
841 return 0;
842}
843
844static const struct snd_soc_dai_ops mtk_dai_i2s_ops = {
845 .hw_params = mtk_dai_i2s_hw_params,
846 .set_sysclk = mtk_dai_i2s_set_sysclk,
847};
848
849/* dai driver */
850#define MTK_I2S_RATES (SNDRV_PCM_RATE_8000_48000 |\
851 SNDRV_PCM_RATE_88200 |\
852 SNDRV_PCM_RATE_96000 |\
853 SNDRV_PCM_RATE_176400 |\
854 SNDRV_PCM_RATE_192000)
855
856#define MTK_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
857 SNDRV_PCM_FMTBIT_S24_LE |\
858 SNDRV_PCM_FMTBIT_S32_LE)
859
860static struct snd_soc_dai_driver mtk_dai_i2s_driver[] = {
861 {
862 .name = "I2S0",
863 .id = MT8183_DAI_I2S_0,
864 .capture = {
865 .stream_name = "I2S0",
866 .channels_min = 1,
867 .channels_max = 2,
868 .rates = MTK_I2S_RATES,
869 .formats = MTK_I2S_FORMATS,
870 },
871 .ops = &mtk_dai_i2s_ops,
872 },
873 {
874 .name = "I2S1",
875 .id = MT8183_DAI_I2S_1,
876 .playback = {
877 .stream_name = "I2S1",
878 .channels_min = 1,
879 .channels_max = 2,
880 .rates = MTK_I2S_RATES,
881 .formats = MTK_I2S_FORMATS,
882 },
883 .ops = &mtk_dai_i2s_ops,
884 },
885 {
886 .name = "I2S2",
887 .id = MT8183_DAI_I2S_2,
888 .capture = {
889 .stream_name = "I2S2",
890 .channels_min = 1,
891 .channels_max = 2,
892 .rates = MTK_I2S_RATES,
893 .formats = MTK_I2S_FORMATS,
894 },
895 .ops = &mtk_dai_i2s_ops,
896 },
897 {
898 .name = "I2S3",
899 .id = MT8183_DAI_I2S_3,
900 .playback = {
901 .stream_name = "I2S3",
902 .channels_min = 1,
903 .channels_max = 2,
904 .rates = MTK_I2S_RATES,
905 .formats = MTK_I2S_FORMATS,
906 },
907 .ops = &mtk_dai_i2s_ops,
908 },
909 {
910 .name = "I2S5",
911 .id = MT8183_DAI_I2S_5,
912 .playback = {
913 .stream_name = "I2S5",
914 .channels_min = 1,
915 .channels_max = 2,
916 .rates = MTK_I2S_RATES,
917 .formats = MTK_I2S_FORMATS,
918 },
919 .ops = &mtk_dai_i2s_ops,
920 },
921};
922
923/* this enum is merely for mtk_afe_i2s_priv declare */
924enum {
925 DAI_I2S0 = 0,
926 DAI_I2S1,
927 DAI_I2S2,
928 DAI_I2S3,
929 DAI_I2S5,
930 DAI_I2S_NUM,
931};
932
933static const struct mtk_afe_i2s_priv mt8183_i2s_priv[DAI_I2S_NUM] = {
934 [DAI_I2S0] = {
935 .id = MT8183_DAI_I2S_0,
936 .mclk_id = MT8183_I2S0_MCK,
937 .share_property_name = "i2s0-share",
938 .share_i2s_id = -1,
939 },
940 [DAI_I2S1] = {
941 .id = MT8183_DAI_I2S_1,
942 .mclk_id = MT8183_I2S1_MCK,
943 .share_property_name = "i2s1-share",
944 .share_i2s_id = -1,
945 },
946 [DAI_I2S2] = {
947 .id = MT8183_DAI_I2S_2,
948 .mclk_id = MT8183_I2S2_MCK,
949 .share_property_name = "i2s2-share",
950 .share_i2s_id = -1,
951 },
952 [DAI_I2S3] = {
953 .id = MT8183_DAI_I2S_3,
954 .mclk_id = MT8183_I2S3_MCK,
955 .share_property_name = "i2s3-share",
956 .share_i2s_id = -1,
957 },
958 [DAI_I2S5] = {
959 .id = MT8183_DAI_I2S_5,
960 .mclk_id = MT8183_I2S5_MCK,
961 .share_property_name = "i2s5-share",
962 .share_i2s_id = -1,
963 },
964};
965
966int mt8183_dai_i2s_get_share(struct mtk_base_afe *afe)
967{
968 struct mt8183_afe_private *afe_priv = afe->platform_priv;
969 const struct device_node *of_node = afe->dev->of_node;
970 const char *of_str;
971 const char *property_name;
972 struct mtk_afe_i2s_priv *i2s_priv;
973 int i;
974
975 for (i = 0; i < DAI_I2S_NUM; i++) {
976 i2s_priv = afe_priv->dai_priv[mt8183_i2s_priv[i].id];
977 property_name = mt8183_i2s_priv[i].share_property_name;
978 if (of_property_read_string(of_node, property_name, &of_str))
979 continue;
980 i2s_priv->share_i2s_id = get_i2s_id_by_name(afe, of_str);
981 }
982
983 return 0;
984}
985
986int mt8183_dai_i2s_set_priv(struct mtk_base_afe *afe)
987{
988 struct mt8183_afe_private *afe_priv = afe->platform_priv;
989 struct mtk_afe_i2s_priv *i2s_priv;
990 int i;
991
992 for (i = 0; i < DAI_I2S_NUM; i++) {
993 i2s_priv = devm_kzalloc(afe->dev,
994 sizeof(struct mtk_afe_i2s_priv),
995 GFP_KERNEL);
996 if (!i2s_priv)
997 return -ENOMEM;
998
999 memcpy(i2s_priv, &mt8183_i2s_priv[i],
1000 sizeof(struct mtk_afe_i2s_priv));
1001
1002 afe_priv->dai_priv[mt8183_i2s_priv[i].id] = i2s_priv;
1003 }
1004
1005 return 0;
1006}
1007
1008int mt8183_dai_i2s_register(struct mtk_base_afe *afe)
1009{
1010 struct mtk_base_afe_dai *dai;
1011 int ret;
1012
1013 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
1014 if (!dai)
1015 return -ENOMEM;
1016
1017 list_add(&dai->list, &afe->sub_dais);
1018
1019 dai->dai_drivers = mtk_dai_i2s_driver;
1020 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_i2s_driver);
1021
1022 dai->controls = mtk_dai_i2s_controls;
1023 dai->num_controls = ARRAY_SIZE(mtk_dai_i2s_controls);
1024 dai->dapm_widgets = mtk_dai_i2s_widgets;
1025 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_i2s_widgets);
1026 dai->dapm_routes = mtk_dai_i2s_routes;
1027 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_i2s_routes);
1028
1029 /* set all dai i2s private data */
1030 ret = mt8183_dai_i2s_set_priv(afe);
1031 if (ret)
1032 return ret;
1033
1034 /* parse share i2s */
1035 ret = mt8183_dai_i2s_get_share(afe);
1036 if (ret)
1037 return ret;
1038
1039 return 0;
1040}
diff --git a/sound/soc/mediatek/mt8183/mt8183-dai-pcm.c b/sound/soc/mediatek/mt8183/mt8183-dai-pcm.c
new file mode 100644
index 000000000000..bc3ba3228f08
--- /dev/null
+++ b/sound/soc/mediatek/mt8183/mt8183-dai-pcm.c
@@ -0,0 +1,318 @@
1// SPDX-License-Identifier: GPL-2.0
2//
3// MediaTek ALSA SoC Audio DAI I2S Control
4//
5// Copyright (c) 2018 MediaTek Inc.
6// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7
8#include <linux/regmap.h>
9#include <sound/pcm_params.h>
10#include "mt8183-afe-common.h"
11#include "mt8183-interconnection.h"
12#include "mt8183-reg.h"
13
14enum AUD_TX_LCH_RPT {
15 AUD_TX_LCH_RPT_NO_REPEAT = 0,
16 AUD_TX_LCH_RPT_REPEAT = 1
17};
18
19enum AUD_VBT_16K_MODE {
20 AUD_VBT_16K_MODE_DISABLE = 0,
21 AUD_VBT_16K_MODE_ENABLE = 1
22};
23
24enum AUD_EXT_MODEM {
25 AUD_EXT_MODEM_SELECT_INTERNAL = 0,
26 AUD_EXT_MODEM_SELECT_EXTERNAL = 1
27};
28
29enum AUD_PCM_SYNC_TYPE {
30 /* bck sync length = 1 */
31 AUD_PCM_ONE_BCK_CYCLE_SYNC = 0,
32 /* bck sync length = PCM_INTF_CON1[9:13] */
33 AUD_PCM_EXTENDED_BCK_CYCLE_SYNC = 1
34};
35
36enum AUD_BT_MODE {
37 AUD_BT_MODE_DUAL_MIC_ON_TX = 0,
38 AUD_BT_MODE_SINGLE_MIC_ON_TX = 1
39};
40
41enum AUD_PCM_AFIFO_SRC {
42 /* slave mode & external modem uses different crystal */
43 AUD_PCM_AFIFO_ASRC = 0,
44 /* slave mode & external modem uses the same crystal */
45 AUD_PCM_AFIFO_AFIFO = 1
46};
47
48enum AUD_PCM_CLOCK_SOURCE {
49 AUD_PCM_CLOCK_MASTER_MODE = 0,
50 AUD_PCM_CLOCK_SLAVE_MODE = 1
51};
52
53enum AUD_PCM_WLEN {
54 AUD_PCM_WLEN_PCM_32_BCK_CYCLES = 0,
55 AUD_PCM_WLEN_PCM_64_BCK_CYCLES = 1
56};
57
58enum AUD_PCM_MODE {
59 AUD_PCM_MODE_PCM_MODE_8K = 0,
60 AUD_PCM_MODE_PCM_MODE_16K = 1,
61 AUD_PCM_MODE_PCM_MODE_32K = 2,
62 AUD_PCM_MODE_PCM_MODE_48K = 3,
63};
64
65enum AUD_PCM_FMT {
66 AUD_PCM_FMT_I2S = 0,
67 AUD_PCM_FMT_EIAJ = 1,
68 AUD_PCM_FMT_PCM_MODE_A = 2,
69 AUD_PCM_FMT_PCM_MODE_B = 3
70};
71
72enum AUD_BCLK_OUT_INV {
73 AUD_BCLK_OUT_INV_NO_INVERSE = 0,
74 AUD_BCLK_OUT_INV_INVERSE = 1
75};
76
77enum AUD_PCM_EN {
78 AUD_PCM_EN_DISABLE = 0,
79 AUD_PCM_EN_ENABLE = 1
80};
81
82/* dai component */
83static const struct snd_kcontrol_new mtk_pcm_1_playback_ch1_mix[] = {
84 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN7,
85 I_ADDA_UL_CH1, 1, 0),
86 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN7,
87 I_DL2_CH1, 1, 0),
88};
89
90static const struct snd_kcontrol_new mtk_pcm_1_playback_ch2_mix[] = {
91 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN8,
92 I_ADDA_UL_CH2, 1, 0),
93 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN8,
94 I_DL2_CH2, 1, 0),
95};
96
97static const struct snd_kcontrol_new mtk_pcm_1_playback_ch4_mix[] = {
98 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN27,
99 I_DL1_CH1, 1, 0),
100};
101
102static const struct snd_kcontrol_new mtk_pcm_2_playback_ch1_mix[] = {
103 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN17,
104 I_ADDA_UL_CH1, 1, 0),
105 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN17,
106 I_DL2_CH1, 1, 0),
107};
108
109static const struct snd_kcontrol_new mtk_pcm_2_playback_ch2_mix[] = {
110 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN18,
111 I_ADDA_UL_CH2, 1, 0),
112 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN18,
113 I_DL2_CH2, 1, 0),
114};
115
116static const struct snd_kcontrol_new mtk_pcm_2_playback_ch4_mix[] = {
117 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN24,
118 I_DL1_CH1, 1, 0),
119};
120
121static const struct snd_soc_dapm_widget mtk_dai_pcm_widgets[] = {
122 /* inter-connections */
123 SND_SOC_DAPM_MIXER("PCM_1_PB_CH1", SND_SOC_NOPM, 0, 0,
124 mtk_pcm_1_playback_ch1_mix,
125 ARRAY_SIZE(mtk_pcm_1_playback_ch1_mix)),
126 SND_SOC_DAPM_MIXER("PCM_1_PB_CH2", SND_SOC_NOPM, 0, 0,
127 mtk_pcm_1_playback_ch2_mix,
128 ARRAY_SIZE(mtk_pcm_1_playback_ch2_mix)),
129 SND_SOC_DAPM_MIXER("PCM_1_PB_CH4", SND_SOC_NOPM, 0, 0,
130 mtk_pcm_1_playback_ch4_mix,
131 ARRAY_SIZE(mtk_pcm_1_playback_ch4_mix)),
132 SND_SOC_DAPM_MIXER("PCM_2_PB_CH1", SND_SOC_NOPM, 0, 0,
133 mtk_pcm_2_playback_ch1_mix,
134 ARRAY_SIZE(mtk_pcm_2_playback_ch1_mix)),
135 SND_SOC_DAPM_MIXER("PCM_2_PB_CH2", SND_SOC_NOPM, 0, 0,
136 mtk_pcm_2_playback_ch2_mix,
137 ARRAY_SIZE(mtk_pcm_2_playback_ch2_mix)),
138 SND_SOC_DAPM_MIXER("PCM_2_PB_CH4", SND_SOC_NOPM, 0, 0,
139 mtk_pcm_2_playback_ch4_mix,
140 ARRAY_SIZE(mtk_pcm_2_playback_ch4_mix)),
141
142 SND_SOC_DAPM_SUPPLY("PCM_1_EN", PCM_INTF_CON1, PCM_EN_SFT, 0,
143 NULL, 0),
144
145 SND_SOC_DAPM_SUPPLY("PCM_2_EN", PCM2_INTF_CON, PCM2_EN_SFT, 0,
146 NULL, 0),
147
148 SND_SOC_DAPM_INPUT("MD1_TO_AFE"),
149 SND_SOC_DAPM_INPUT("MD2_TO_AFE"),
150 SND_SOC_DAPM_OUTPUT("AFE_TO_MD1"),
151 SND_SOC_DAPM_OUTPUT("AFE_TO_MD2"),
152};
153
154static const struct snd_soc_dapm_route mtk_dai_pcm_routes[] = {
155 {"PCM 1 Playback", NULL, "PCM_1_PB_CH1"},
156 {"PCM 1 Playback", NULL, "PCM_1_PB_CH2"},
157 {"PCM 1 Playback", NULL, "PCM_1_PB_CH4"},
158 {"PCM 2 Playback", NULL, "PCM_2_PB_CH1"},
159 {"PCM 2 Playback", NULL, "PCM_2_PB_CH2"},
160 {"PCM 2 Playback", NULL, "PCM_2_PB_CH4"},
161
162 {"PCM 1 Playback", NULL, "PCM_1_EN"},
163 {"PCM 2 Playback", NULL, "PCM_2_EN"},
164 {"PCM 1 Capture", NULL, "PCM_1_EN"},
165 {"PCM 2 Capture", NULL, "PCM_2_EN"},
166
167 {"AFE_TO_MD1", NULL, "PCM 2 Playback"},
168 {"AFE_TO_MD2", NULL, "PCM 1 Playback"},
169 {"PCM 2 Capture", NULL, "MD1_TO_AFE"},
170 {"PCM 1 Capture", NULL, "MD2_TO_AFE"},
171
172 {"PCM_1_PB_CH1", "DL2_CH1", "DL2"},
173 {"PCM_1_PB_CH2", "DL2_CH2", "DL2"},
174 {"PCM_1_PB_CH4", "DL1_CH1", "DL1"},
175 {"PCM_2_PB_CH1", "DL2_CH1", "DL2"},
176 {"PCM_2_PB_CH2", "DL2_CH2", "DL2"},
177 {"PCM_2_PB_CH4", "DL1_CH1", "DL1"},
178};
179
180/* dai ops */
181static int mtk_dai_pcm_hw_params(struct snd_pcm_substream *substream,
182 struct snd_pcm_hw_params *params,
183 struct snd_soc_dai *dai)
184{
185 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
186 unsigned int rate = params_rate(params);
187 unsigned int rate_reg = mt8183_rate_transform(afe->dev, rate, dai->id);
188 unsigned int pcm_con = 0;
189
190 dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d, rate_reg %d, widget active p %d, c %d\n",
191 __func__,
192 dai->id,
193 substream->stream,
194 rate,
195 rate_reg,
196 dai->playback_widget->active,
197 dai->capture_widget->active);
198
199 if (dai->playback_widget->active || dai->capture_widget->active)
200 return 0;
201
202 switch (dai->id) {
203 case MT8183_DAI_PCM_1:
204 pcm_con |= AUD_BCLK_OUT_INV_NO_INVERSE << PCM_BCLK_OUT_INV_SFT;
205 pcm_con |= AUD_TX_LCH_RPT_NO_REPEAT << PCM_TX_LCH_RPT_SFT;
206 pcm_con |= AUD_VBT_16K_MODE_DISABLE << PCM_VBT_16K_MODE_SFT;
207 pcm_con |= AUD_EXT_MODEM_SELECT_INTERNAL << PCM_EXT_MODEM_SFT;
208 pcm_con |= 0 << PCM_SYNC_LENGTH_SFT;
209 pcm_con |= AUD_PCM_ONE_BCK_CYCLE_SYNC << PCM_SYNC_TYPE_SFT;
210 pcm_con |= AUD_BT_MODE_DUAL_MIC_ON_TX << PCM_BT_MODE_SFT;
211 pcm_con |= AUD_PCM_AFIFO_AFIFO << PCM_BYP_ASRC_SFT;
212 pcm_con |= AUD_PCM_CLOCK_SLAVE_MODE << PCM_SLAVE_SFT;
213 pcm_con |= rate_reg << PCM_MODE_SFT;
214 pcm_con |= AUD_PCM_FMT_PCM_MODE_B << PCM_FMT_SFT;
215
216 regmap_update_bits(afe->regmap, PCM_INTF_CON1,
217 0xfffffffe, pcm_con);
218 break;
219 case MT8183_DAI_PCM_2:
220 pcm_con |= AUD_TX_LCH_RPT_NO_REPEAT << PCM2_TX_LCH_RPT_SFT;
221 pcm_con |= AUD_VBT_16K_MODE_DISABLE << PCM2_VBT_16K_MODE_SFT;
222 pcm_con |= AUD_BT_MODE_DUAL_MIC_ON_TX << PCM2_BT_MODE_SFT;
223 pcm_con |= AUD_PCM_AFIFO_AFIFO << PCM2_AFIFO_SFT;
224 pcm_con |= AUD_PCM_WLEN_PCM_32_BCK_CYCLES << PCM2_WLEN_SFT;
225 pcm_con |= rate_reg << PCM2_MODE_SFT;
226 pcm_con |= AUD_PCM_FMT_PCM_MODE_B << PCM2_FMT_SFT;
227
228 regmap_update_bits(afe->regmap, PCM2_INTF_CON,
229 0xfffffffe, pcm_con);
230 break;
231 default:
232 dev_warn(afe->dev, "%s(), id %d not support\n",
233 __func__, dai->id);
234 return -EINVAL;
235 }
236
237 return 0;
238}
239
240static const struct snd_soc_dai_ops mtk_dai_pcm_ops = {
241 .hw_params = mtk_dai_pcm_hw_params,
242};
243
244/* dai driver */
245#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000 |\
246 SNDRV_PCM_RATE_16000 |\
247 SNDRV_PCM_RATE_32000 |\
248 SNDRV_PCM_RATE_48000)
249
250#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
251 SNDRV_PCM_FMTBIT_S24_LE |\
252 SNDRV_PCM_FMTBIT_S32_LE)
253
254static struct snd_soc_dai_driver mtk_dai_pcm_driver[] = {
255 {
256 .name = "PCM 1",
257 .id = MT8183_DAI_PCM_1,
258 .playback = {
259 .stream_name = "PCM 1 Playback",
260 .channels_min = 1,
261 .channels_max = 2,
262 .rates = MTK_PCM_RATES,
263 .formats = MTK_PCM_FORMATS,
264 },
265 .capture = {
266 .stream_name = "PCM 1 Capture",
267 .channels_min = 1,
268 .channels_max = 2,
269 .rates = MTK_PCM_RATES,
270 .formats = MTK_PCM_FORMATS,
271 },
272 .ops = &mtk_dai_pcm_ops,
273 .symmetric_rates = 1,
274 .symmetric_samplebits = 1,
275 },
276 {
277 .name = "PCM 2",
278 .id = MT8183_DAI_PCM_2,
279 .playback = {
280 .stream_name = "PCM 2 Playback",
281 .channels_min = 1,
282 .channels_max = 2,
283 .rates = MTK_PCM_RATES,
284 .formats = MTK_PCM_FORMATS,
285 },
286 .capture = {
287 .stream_name = "PCM 2 Capture",
288 .channels_min = 1,
289 .channels_max = 2,
290 .rates = MTK_PCM_RATES,
291 .formats = MTK_PCM_FORMATS,
292 },
293 .ops = &mtk_dai_pcm_ops,
294 .symmetric_rates = 1,
295 .symmetric_samplebits = 1,
296 },
297};
298
299int mt8183_dai_pcm_register(struct mtk_base_afe *afe)
300{
301 struct mtk_base_afe_dai *dai;
302
303 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
304 if (!dai)
305 return -ENOMEM;
306
307 list_add(&dai->list, &afe->sub_dais);
308
309 dai->dai_drivers = mtk_dai_pcm_driver;
310 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_pcm_driver);
311
312 dai->dapm_widgets = mtk_dai_pcm_widgets;
313 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_pcm_widgets);
314 dai->dapm_routes = mtk_dai_pcm_routes;
315 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_pcm_routes);
316
317 return 0;
318}
diff --git a/sound/soc/mediatek/mt8183/mt8183-dai-tdm.c b/sound/soc/mediatek/mt8183/mt8183-dai-tdm.c
new file mode 100644
index 000000000000..8983d54a9b67
--- /dev/null
+++ b/sound/soc/mediatek/mt8183/mt8183-dai-tdm.c
@@ -0,0 +1,639 @@
1// SPDX-License-Identifier: GPL-2.0
2//
3// MediaTek ALSA SoC Audio DAI TDM Control
4//
5// Copyright (c) 2018 MediaTek Inc.
6// Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7
8#include <linux/regmap.h>
9#include <sound/pcm_params.h>
10#include "mt8183-afe-clk.h"
11#include "mt8183-afe-common.h"
12#include "mt8183-interconnection.h"
13#include "mt8183-reg.h"
14
15struct mtk_afe_tdm_priv {
16 int bck_id;
17 int bck_rate;
18
19 int mclk_id;
20 int mclk_multiple; /* according to sample rate */
21 int mclk_rate;
22 int mclk_apll;
23};
24
25enum {
26 TDM_WLEN_16_BIT = 1,
27 TDM_WLEN_32_BIT = 2,
28};
29
30enum {
31 TDM_CHANNEL_BCK_16 = 0,
32 TDM_CHANNEL_BCK_24 = 1,
33 TDM_CHANNEL_BCK_32 = 2,
34};
35
36enum {
37 TDM_CHANNEL_NUM_2 = 0,
38 TDM_CHANNEL_NUM_4 = 1,
39 TDM_CHANNEL_NUM_8 = 2,
40};
41
42enum {
43 TDM_CH_START_O30_O31 = 0,
44 TDM_CH_START_O32_O33,
45 TDM_CH_START_O34_O35,
46 TDM_CH_START_O36_O37,
47 TDM_CH_ZERO,
48};
49
50enum {
51 HDMI_BIT_WIDTH_16_BIT = 0,
52 HDMI_BIT_WIDTH_32_BIT = 1,
53};
54
55static unsigned int get_hdmi_wlen(snd_pcm_format_t format)
56{
57 return snd_pcm_format_physical_width(format) <= 16 ?
58 HDMI_BIT_WIDTH_16_BIT : HDMI_BIT_WIDTH_32_BIT;
59}
60
61static unsigned int get_tdm_wlen(snd_pcm_format_t format)
62{
63 return snd_pcm_format_physical_width(format) <= 16 ?
64 TDM_WLEN_16_BIT : TDM_WLEN_32_BIT;
65}
66
67static unsigned int get_tdm_channel_bck(snd_pcm_format_t format)
68{
69 return snd_pcm_format_physical_width(format) <= 16 ?
70 TDM_CHANNEL_BCK_16 : TDM_CHANNEL_BCK_32;
71}
72
73static unsigned int get_tdm_lrck_width(snd_pcm_format_t format)
74{
75 return snd_pcm_format_physical_width(format) - 1;
76}
77
78static unsigned int get_tdm_ch(unsigned int ch)
79{
80 switch (ch) {
81 case 1:
82 case 2:
83 return TDM_CHANNEL_NUM_2;
84 case 3:
85 case 4:
86 return TDM_CHANNEL_NUM_4;
87 case 5:
88 case 6:
89 case 7:
90 case 8:
91 default:
92 return TDM_CHANNEL_NUM_8;
93 }
94}
95
96/* interconnection */
97enum {
98 HDMI_CONN_CH0 = 0,
99 HDMI_CONN_CH1,
100 HDMI_CONN_CH2,
101 HDMI_CONN_CH3,
102 HDMI_CONN_CH4,
103 HDMI_CONN_CH5,
104 HDMI_CONN_CH6,
105 HDMI_CONN_CH7,
106};
107
108static const char *const hdmi_conn_mux_map[] = {
109 "CH0", "CH1", "CH2", "CH3",
110 "CH4", "CH5", "CH6", "CH7",
111};
112
113static int hdmi_conn_mux_map_value[] = {
114 HDMI_CONN_CH0,
115 HDMI_CONN_CH1,
116 HDMI_CONN_CH2,
117 HDMI_CONN_CH3,
118 HDMI_CONN_CH4,
119 HDMI_CONN_CH5,
120 HDMI_CONN_CH6,
121 HDMI_CONN_CH7,
122};
123
124static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum,
125 AFE_HDMI_CONN0,
126 HDMI_O_0_SFT,
127 HDMI_O_0_MASK,
128 hdmi_conn_mux_map,
129 hdmi_conn_mux_map_value);
130
131static const struct snd_kcontrol_new hdmi_ch0_mux_control =
132 SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum);
133
134static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum,
135 AFE_HDMI_CONN0,
136 HDMI_O_1_SFT,
137 HDMI_O_1_MASK,
138 hdmi_conn_mux_map,
139 hdmi_conn_mux_map_value);
140
141static const struct snd_kcontrol_new hdmi_ch1_mux_control =
142 SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum);
143
144static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum,
145 AFE_HDMI_CONN0,
146 HDMI_O_2_SFT,
147 HDMI_O_2_MASK,
148 hdmi_conn_mux_map,
149 hdmi_conn_mux_map_value);
150
151static const struct snd_kcontrol_new hdmi_ch2_mux_control =
152 SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum);
153
154static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum,
155 AFE_HDMI_CONN0,
156 HDMI_O_3_SFT,
157 HDMI_O_3_MASK,
158 hdmi_conn_mux_map,
159 hdmi_conn_mux_map_value);
160
161static const struct snd_kcontrol_new hdmi_ch3_mux_control =
162 SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum);
163
164static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum,
165 AFE_HDMI_CONN0,
166 HDMI_O_4_SFT,
167 HDMI_O_4_MASK,
168 hdmi_conn_mux_map,
169 hdmi_conn_mux_map_value);
170
171static const struct snd_kcontrol_new hdmi_ch4_mux_control =
172 SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum);
173
174static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum,
175 AFE_HDMI_CONN0,
176 HDMI_O_5_SFT,
177 HDMI_O_5_MASK,
178 hdmi_conn_mux_map,
179 hdmi_conn_mux_map_value);
180
181static const struct snd_kcontrol_new hdmi_ch5_mux_control =
182 SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum);
183
184static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum,
185 AFE_HDMI_CONN0,
186 HDMI_O_6_SFT,
187 HDMI_O_6_MASK,
188 hdmi_conn_mux_map,
189 hdmi_conn_mux_map_value);
190
191static const struct snd_kcontrol_new hdmi_ch6_mux_control =
192 SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum);
193
194static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum,
195 AFE_HDMI_CONN0,
196 HDMI_O_7_SFT,
197 HDMI_O_7_MASK,
198 hdmi_conn_mux_map,
199 hdmi_conn_mux_map_value);
200
201static const struct snd_kcontrol_new hdmi_ch7_mux_control =
202 SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum);
203
204enum {
205 SUPPLY_SEQ_APLL,
206 SUPPLY_SEQ_TDM_MCK_EN,
207 SUPPLY_SEQ_TDM_BCK_EN,
208};
209
210static int mtk_tdm_bck_en_event(struct snd_soc_dapm_widget *w,
211 struct snd_kcontrol *kcontrol,
212 int event)
213{
214 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
215 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
216 struct mt8183_afe_private *afe_priv = afe->platform_priv;
217 struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[MT8183_DAI_TDM];
218
219 dev_info(cmpnt->dev, "%s(), name %s, event 0x%x\n",
220 __func__, w->name, event);
221
222 switch (event) {
223 case SND_SOC_DAPM_PRE_PMU:
224 mt8183_mck_enable(afe, tdm_priv->bck_id, tdm_priv->bck_rate);
225 break;
226 case SND_SOC_DAPM_POST_PMD:
227 mt8183_mck_disable(afe, tdm_priv->bck_id);
228 break;
229 default:
230 break;
231 }
232
233 return 0;
234}
235
236static int mtk_tdm_mck_en_event(struct snd_soc_dapm_widget *w,
237 struct snd_kcontrol *kcontrol,
238 int event)
239{
240 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
241 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
242 struct mt8183_afe_private *afe_priv = afe->platform_priv;
243 struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[MT8183_DAI_TDM];
244
245 dev_info(cmpnt->dev, "%s(), name %s, event 0x%x\n",
246 __func__, w->name, event);
247
248 switch (event) {
249 case SND_SOC_DAPM_PRE_PMU:
250 mt8183_mck_enable(afe, tdm_priv->mclk_id, tdm_priv->mclk_rate);
251 break;
252 case SND_SOC_DAPM_POST_PMD:
253 tdm_priv->mclk_rate = 0;
254 mt8183_mck_disable(afe, tdm_priv->mclk_id);
255 break;
256 default:
257 break;
258 }
259
260 return 0;
261}
262
263static const struct snd_soc_dapm_widget mtk_dai_tdm_widgets[] = {
264 SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0,
265 &hdmi_ch0_mux_control),
266 SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0,
267 &hdmi_ch1_mux_control),
268 SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0,
269 &hdmi_ch2_mux_control),
270 SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0,
271 &hdmi_ch3_mux_control),
272 SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0,
273 &hdmi_ch4_mux_control),
274 SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0,
275 &hdmi_ch5_mux_control),
276 SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0,
277 &hdmi_ch6_mux_control),
278 SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0,
279 &hdmi_ch7_mux_control),
280
281 SND_SOC_DAPM_CLOCK_SUPPLY("aud_tdm_clk"),
282
283 SND_SOC_DAPM_SUPPLY_S("TDM_BCK", SUPPLY_SEQ_TDM_BCK_EN,
284 SND_SOC_NOPM, 0, 0,
285 mtk_tdm_bck_en_event,
286 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
287
288 SND_SOC_DAPM_SUPPLY_S("TDM_MCK", SUPPLY_SEQ_TDM_MCK_EN,
289 SND_SOC_NOPM, 0, 0,
290 mtk_tdm_mck_en_event,
291 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
292};
293
294static int mtk_afe_tdm_apll_connect(struct snd_soc_dapm_widget *source,
295 struct snd_soc_dapm_widget *sink)
296{
297 struct snd_soc_dapm_widget *w = sink;
298 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
299 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt);
300 struct mt8183_afe_private *afe_priv = afe->platform_priv;
301 struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[MT8183_DAI_TDM];
302 int cur_apll;
303
304 /* which apll */
305 cur_apll = mt8183_get_apll_by_name(afe, source->name);
306
307 return (tdm_priv->mclk_apll == cur_apll) ? 1 : 0;
308}
309
310static const struct snd_soc_dapm_route mtk_dai_tdm_routes[] = {
311 {"HDMI_CH0_MUX", "CH0", "HDMI"},
312 {"HDMI_CH0_MUX", "CH1", "HDMI"},
313 {"HDMI_CH0_MUX", "CH2", "HDMI"},
314 {"HDMI_CH0_MUX", "CH3", "HDMI"},
315 {"HDMI_CH0_MUX", "CH4", "HDMI"},
316 {"HDMI_CH0_MUX", "CH5", "HDMI"},
317 {"HDMI_CH0_MUX", "CH6", "HDMI"},
318 {"HDMI_CH0_MUX", "CH7", "HDMI"},
319
320 {"HDMI_CH1_MUX", "CH0", "HDMI"},
321 {"HDMI_CH1_MUX", "CH1", "HDMI"},
322 {"HDMI_CH1_MUX", "CH2", "HDMI"},
323 {"HDMI_CH1_MUX", "CH3", "HDMI"},
324 {"HDMI_CH1_MUX", "CH4", "HDMI"},
325 {"HDMI_CH1_MUX", "CH5", "HDMI"},
326 {"HDMI_CH1_MUX", "CH6", "HDMI"},
327 {"HDMI_CH1_MUX", "CH7", "HDMI"},
328
329 {"HDMI_CH2_MUX", "CH0", "HDMI"},
330 {"HDMI_CH2_MUX", "CH1", "HDMI"},
331 {"HDMI_CH2_MUX", "CH2", "HDMI"},
332 {"HDMI_CH2_MUX", "CH3", "HDMI"},
333 {"HDMI_CH2_MUX", "CH4", "HDMI"},
334 {"HDMI_CH2_MUX", "CH5", "HDMI"},
335 {"HDMI_CH2_MUX", "CH6", "HDMI"},
336 {"HDMI_CH2_MUX", "CH7", "HDMI"},
337
338 {"HDMI_CH3_MUX", "CH0", "HDMI"},
339 {"HDMI_CH3_MUX", "CH1", "HDMI"},
340 {"HDMI_CH3_MUX", "CH2", "HDMI"},
341 {"HDMI_CH3_MUX", "CH3", "HDMI"},
342 {"HDMI_CH3_MUX", "CH4", "HDMI"},
343 {"HDMI_CH3_MUX", "CH5", "HDMI"},
344 {"HDMI_CH3_MUX", "CH6", "HDMI"},
345 {"HDMI_CH3_MUX", "CH7", "HDMI"},
346
347 {"HDMI_CH4_MUX", "CH0", "HDMI"},
348 {"HDMI_CH4_MUX", "CH1", "HDMI"},
349 {"HDMI_CH4_MUX", "CH2", "HDMI"},
350 {"HDMI_CH4_MUX", "CH3", "HDMI"},
351 {"HDMI_CH4_MUX", "CH4", "HDMI"},
352 {"HDMI_CH4_MUX", "CH5", "HDMI"},
353 {"HDMI_CH4_MUX", "CH6", "HDMI"},
354 {"HDMI_CH4_MUX", "CH7", "HDMI"},
355
356 {"HDMI_CH5_MUX", "CH0", "HDMI"},
357 {"HDMI_CH5_MUX", "CH1", "HDMI"},
358 {"HDMI_CH5_MUX", "CH2", "HDMI"},
359 {"HDMI_CH5_MUX", "CH3", "HDMI"},
360 {"HDMI_CH5_MUX", "CH4", "HDMI"},
361 {"HDMI_CH5_MUX", "CH5", "HDMI"},
362 {"HDMI_CH5_MUX", "CH6", "HDMI"},
363 {"HDMI_CH5_MUX", "CH7", "HDMI"},
364
365 {"HDMI_CH6_MUX", "CH0", "HDMI"},
366 {"HDMI_CH6_MUX", "CH1", "HDMI"},
367 {"HDMI_CH6_MUX", "CH2", "HDMI"},
368 {"HDMI_CH6_MUX", "CH3", "HDMI"},
369 {"HDMI_CH6_MUX", "CH4", "HDMI"},
370 {"HDMI_CH6_MUX", "CH5", "HDMI"},
371 {"HDMI_CH6_MUX", "CH6", "HDMI"},
372 {"HDMI_CH6_MUX", "CH7", "HDMI"},
373
374 {"HDMI_CH7_MUX", "CH0", "HDMI"},
375 {"HDMI_CH7_MUX", "CH1", "HDMI"},
376 {"HDMI_CH7_MUX", "CH2", "HDMI"},
377 {"HDMI_CH7_MUX", "CH3", "HDMI"},
378 {"HDMI_CH7_MUX", "CH4", "HDMI"},
379 {"HDMI_CH7_MUX", "CH5", "HDMI"},
380 {"HDMI_CH7_MUX", "CH6", "HDMI"},
381 {"HDMI_CH7_MUX", "CH7", "HDMI"},
382
383 {"TDM", NULL, "HDMI_CH0_MUX"},
384 {"TDM", NULL, "HDMI_CH1_MUX"},
385 {"TDM", NULL, "HDMI_CH2_MUX"},
386 {"TDM", NULL, "HDMI_CH3_MUX"},
387 {"TDM", NULL, "HDMI_CH4_MUX"},
388 {"TDM", NULL, "HDMI_CH5_MUX"},
389 {"TDM", NULL, "HDMI_CH6_MUX"},
390 {"TDM", NULL, "HDMI_CH7_MUX"},
391
392 {"TDM", NULL, "aud_tdm_clk"},
393 {"TDM", NULL, "TDM_BCK"},
394 {"TDM_BCK", NULL, "TDM_MCK"},
395 {"TDM_MCK", NULL, APLL1_W_NAME, mtk_afe_tdm_apll_connect},
396 {"TDM_MCK", NULL, APLL2_W_NAME, mtk_afe_tdm_apll_connect},
397};
398
399/* dai ops */
400static int mtk_dai_tdm_cal_mclk(struct mtk_base_afe *afe,
401 struct mtk_afe_tdm_priv *tdm_priv,
402 int freq)
403{
404 int apll;
405 int apll_rate;
406
407 apll = mt8183_get_apll_by_rate(afe, freq);
408 apll_rate = mt8183_get_apll_rate(afe, apll);
409
410 if (!freq || freq > apll_rate) {
411 dev_warn(afe->dev,
412 "%s(), freq(%d Hz) invalid\n", __func__, freq);
413 return -EINVAL;
414 }
415
416 if (apll_rate % freq != 0) {
417 dev_warn(afe->dev,
418 "%s(), APLL cannot generate %d Hz", __func__, freq);
419 return -EINVAL;
420 }
421
422 tdm_priv->mclk_rate = freq;
423 tdm_priv->mclk_apll = apll;
424
425 return 0;
426}
427
428static int mtk_dai_tdm_hw_params(struct snd_pcm_substream *substream,
429 struct snd_pcm_hw_params *params,
430 struct snd_soc_dai *dai)
431{
432 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
433 struct mt8183_afe_private *afe_priv = afe->platform_priv;
434 int tdm_id = dai->id;
435 struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[tdm_id];
436 unsigned int rate = params_rate(params);
437 unsigned int channels = params_channels(params);
438 snd_pcm_format_t format = params_format(params);
439 unsigned int tdm_con = 0;
440
441 /* calculate mclk_rate, if not set explicitly */
442 if (!tdm_priv->mclk_rate) {
443 tdm_priv->mclk_rate = rate * tdm_priv->mclk_multiple;
444 mtk_dai_tdm_cal_mclk(afe,
445 tdm_priv,
446 tdm_priv->mclk_rate);
447 }
448
449 /* calculate bck */
450 tdm_priv->bck_rate = rate *
451 channels *
452 snd_pcm_format_physical_width(format);
453
454 if (tdm_priv->bck_rate > tdm_priv->mclk_rate)
455 dev_warn(afe->dev, "%s(), bck_rate > mclk_rate rate", __func__);
456
457 if (tdm_priv->mclk_rate % tdm_priv->bck_rate != 0)
458 dev_warn(afe->dev, "%s(), bck cannot generate", __func__);
459
460 dev_info(afe->dev, "%s(), id %d, rate %d, channels %d, format %d, mclk_rate %d, bck_rate %d\n",
461 __func__,
462 tdm_id, rate, channels, format,
463 tdm_priv->mclk_rate, tdm_priv->bck_rate);
464
465 /* set tdm */
466 tdm_con = 1 << BCK_INVERSE_SFT;
467 tdm_con |= 1 << LRCK_INVERSE_SFT;
468 tdm_con |= 1 << DELAY_DATA_SFT;
469 tdm_con |= 1 << LEFT_ALIGN_SFT;
470 tdm_con |= get_tdm_wlen(format) << WLEN_SFT;
471 tdm_con |= get_tdm_ch(channels) << CHANNEL_NUM_SFT;
472 tdm_con |= get_tdm_channel_bck(format) << CHANNEL_BCK_CYCLES_SFT;
473 tdm_con |= get_tdm_lrck_width(format) << LRCK_TDM_WIDTH_SFT;
474 regmap_write(afe->regmap, AFE_TDM_CON1, tdm_con);
475
476 switch (channels) {
477 case 1:
478 case 2:
479 tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
480 tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT1_SFT;
481 tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT;
482 tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
483 break;
484 case 3:
485 case 4:
486 tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
487 tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
488 tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT2_SFT;
489 tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
490 break;
491 case 5:
492 case 6:
493 tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
494 tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
495 tdm_con |= TDM_CH_START_O34_O35 << ST_CH_PAIR_SOUT2_SFT;
496 tdm_con |= TDM_CH_ZERO << ST_CH_PAIR_SOUT3_SFT;
497 break;
498 case 7:
499 case 8:
500 tdm_con = TDM_CH_START_O30_O31 << ST_CH_PAIR_SOUT0_SFT;
501 tdm_con |= TDM_CH_START_O32_O33 << ST_CH_PAIR_SOUT1_SFT;
502 tdm_con |= TDM_CH_START_O34_O35 << ST_CH_PAIR_SOUT2_SFT;
503 tdm_con |= TDM_CH_START_O36_O37 << ST_CH_PAIR_SOUT3_SFT;
504 break;
505 default:
506 tdm_con = 0;
507 }
508 regmap_write(afe->regmap, AFE_TDM_CON2, tdm_con);
509
510 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
511 AFE_HDMI_OUT_CH_NUM_MASK_SFT,
512 channels << AFE_HDMI_OUT_CH_NUM_SFT);
513
514 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
515 AFE_HDMI_OUT_BIT_WIDTH_MASK_SFT,
516 get_hdmi_wlen(format) << AFE_HDMI_OUT_BIT_WIDTH_SFT);
517 return 0;
518}
519
520static int mtk_dai_tdm_trigger(struct snd_pcm_substream *substream,
521 int cmd,
522 struct snd_soc_dai *dai)
523{
524 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
525
526 switch (cmd) {
527 case SNDRV_PCM_TRIGGER_START:
528 case SNDRV_PCM_TRIGGER_RESUME:
529 /* enable Out control */
530 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
531 AFE_HDMI_OUT_ON_MASK_SFT,
532 0x1 << AFE_HDMI_OUT_ON_SFT);
533 /* enable tdm */
534 regmap_update_bits(afe->regmap, AFE_TDM_CON1,
535 TDM_EN_MASK_SFT, 0x1 << TDM_EN_SFT);
536 break;
537 case SNDRV_PCM_TRIGGER_STOP:
538 case SNDRV_PCM_TRIGGER_SUSPEND:
539 /* disable tdm */
540 regmap_update_bits(afe->regmap, AFE_TDM_CON1,
541 TDM_EN_MASK_SFT, 0);
542 /* disable Out control */
543 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0,
544 AFE_HDMI_OUT_ON_MASK_SFT,
545 0);
546 break;
547 default:
548 return -EINVAL;
549 }
550
551 return 0;
552}
553
554static int mtk_dai_tdm_set_sysclk(struct snd_soc_dai *dai,
555 int clk_id, unsigned int freq, int dir)
556{
557 struct mtk_base_afe *afe = dev_get_drvdata(dai->dev);
558 struct mt8183_afe_private *afe_priv = afe->platform_priv;
559 struct mtk_afe_tdm_priv *tdm_priv = afe_priv->dai_priv[dai->id];
560
561 if (!tdm_priv) {
562 dev_warn(afe->dev, "%s(), tdm_priv == NULL", __func__);
563 return -EINVAL;
564 }
565
566 if (dir != SND_SOC_CLOCK_OUT) {
567 dev_warn(afe->dev, "%s(), dir != SND_SOC_CLOCK_OUT", __func__);
568 return -EINVAL;
569 }
570
571 dev_info(afe->dev, "%s(), freq %d\n", __func__, freq);
572
573 return mtk_dai_tdm_cal_mclk(afe, tdm_priv, freq);
574}
575
576static const struct snd_soc_dai_ops mtk_dai_tdm_ops = {
577 .hw_params = mtk_dai_tdm_hw_params,
578 .trigger = mtk_dai_tdm_trigger,
579 .set_sysclk = mtk_dai_tdm_set_sysclk,
580};
581
582/* dai driver */
583#define MTK_TDM_RATES (SNDRV_PCM_RATE_8000_48000 |\
584 SNDRV_PCM_RATE_88200 |\
585 SNDRV_PCM_RATE_96000 |\
586 SNDRV_PCM_RATE_176400 |\
587 SNDRV_PCM_RATE_192000)
588
589#define MTK_TDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
590 SNDRV_PCM_FMTBIT_S24_LE |\
591 SNDRV_PCM_FMTBIT_S32_LE)
592
593static struct snd_soc_dai_driver mtk_dai_tdm_driver[] = {
594 {
595 .name = "TDM",
596 .id = MT8183_DAI_TDM,
597 .playback = {
598 .stream_name = "TDM",
599 .channels_min = 2,
600 .channels_max = 8,
601 .rates = MTK_TDM_RATES,
602 .formats = MTK_TDM_FORMATS,
603 },
604 .ops = &mtk_dai_tdm_ops,
605 },
606};
607
608int mt8183_dai_tdm_register(struct mtk_base_afe *afe)
609{
610 struct mt8183_afe_private *afe_priv = afe->platform_priv;
611 struct mtk_afe_tdm_priv *tdm_priv;
612 struct mtk_base_afe_dai *dai;
613
614 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL);
615 if (!dai)
616 return -ENOMEM;
617
618 list_add(&dai->list, &afe->sub_dais);
619
620 dai->dai_drivers = mtk_dai_tdm_driver;
621 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_tdm_driver);
622
623 dai->dapm_widgets = mtk_dai_tdm_widgets;
624 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_tdm_widgets);
625 dai->dapm_routes = mtk_dai_tdm_routes;
626 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_tdm_routes);
627
628 tdm_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_afe_tdm_priv),
629 GFP_KERNEL);
630 if (!tdm_priv)
631 return -ENOMEM;
632
633 tdm_priv->mclk_multiple = 128;
634 tdm_priv->bck_id = MT8183_I2S4_BCK;
635 tdm_priv->mclk_id = MT8183_I2S4_MCK;
636
637 afe_priv->dai_priv[MT8183_DAI_TDM] = tdm_priv;
638 return 0;
639}
diff --git a/sound/soc/mediatek/mt8183/mt8183-interconnection.h b/sound/soc/mediatek/mt8183/mt8183-interconnection.h
new file mode 100644
index 000000000000..6332f5f3e987
--- /dev/null
+++ b/sound/soc/mediatek/mt8183/mt8183-interconnection.h
@@ -0,0 +1,33 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Mediatek MT8183 audio driver interconnection definition
4 *
5 * Copyright (c) 2018 MediaTek Inc.
6 * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7 */
8
9#ifndef _MT8183_INTERCONNECTION_H_
10#define _MT8183_INTERCONNECTION_H_
11
12#define I_I2S0_CH1 0
13#define I_I2S0_CH2 1
14#define I_ADDA_UL_CH1 3
15#define I_ADDA_UL_CH2 4
16#define I_DL1_CH1 5
17#define I_DL1_CH2 6
18#define I_DL2_CH1 7
19#define I_DL2_CH2 8
20#define I_PCM_1_CAP_CH1 9
21#define I_GAIN1_OUT_CH1 10
22#define I_GAIN1_OUT_CH2 11
23#define I_GAIN2_OUT_CH1 12
24#define I_GAIN2_OUT_CH2 13
25#define I_PCM_2_CAP_CH1 14
26#define I_PCM_2_CAP_CH2 21
27#define I_PCM_1_CAP_CH2 22
28#define I_DL3_CH1 23
29#define I_DL3_CH2 24
30#define I_I2S2_CH1 25
31#define I_I2S2_CH2 26
32
33#endif
diff --git a/sound/soc/mediatek/mt8183/mt8183-reg.h b/sound/soc/mediatek/mt8183/mt8183-reg.h
new file mode 100644
index 000000000000..e0482f2826da
--- /dev/null
+++ b/sound/soc/mediatek/mt8183/mt8183-reg.h
@@ -0,0 +1,1666 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * mt8183-reg.h -- Mediatek 8183 audio driver reg definition
4 *
5 * Copyright (c) 2018 MediaTek Inc.
6 * Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com>
7 */
8
9#ifndef _MT8183_REG_H_
10#define _MT8183_REG_H_
11
12#define AUDIO_TOP_CON0 0x0000
13#define AUDIO_TOP_CON1 0x0004
14#define AUDIO_TOP_CON3 0x000c
15#define AFE_DAC_CON0 0x0010
16#define AFE_DAC_CON1 0x0014
17#define AFE_I2S_CON 0x0018
18#define AFE_DAIBT_CON0 0x001c
19#define AFE_CONN0 0x0020
20#define AFE_CONN1 0x0024
21#define AFE_CONN2 0x0028
22#define AFE_CONN3 0x002c
23#define AFE_CONN4 0x0030
24#define AFE_I2S_CON1 0x0034
25#define AFE_I2S_CON2 0x0038
26#define AFE_MRGIF_CON 0x003c
27#define AFE_DL1_BASE 0x0040
28#define AFE_DL1_CUR 0x0044
29#define AFE_DL1_END 0x0048
30#define AFE_I2S_CON3 0x004c
31#define AFE_DL2_BASE 0x0050
32#define AFE_DL2_CUR 0x0054
33#define AFE_DL2_END 0x0058
34#define AFE_CONN5 0x005c
35#define AFE_CONN_24BIT 0x006c
36#define AFE_AWB_BASE 0x0070
37#define AFE_AWB_END 0x0078
38#define AFE_AWB_CUR 0x007c
39#define AFE_VUL_BASE 0x0080
40#define AFE_VUL_END 0x0088
41#define AFE_VUL_CUR 0x008c
42#define AFE_CONN6 0x00bc
43#define AFE_MEMIF_MSB 0x00cc
44#define AFE_MEMIF_MON0 0x00d0
45#define AFE_MEMIF_MON1 0x00d4
46#define AFE_MEMIF_MON2 0x00d8
47#define AFE_MEMIF_MON3 0x00dc
48#define AFE_MEMIF_MON4 0x00e0
49#define AFE_MEMIF_MON5 0x00e4
50#define AFE_MEMIF_MON6 0x00e8
51#define AFE_MEMIF_MON7 0x00ec
52#define AFE_MEMIF_MON8 0x00f0
53#define AFE_MEMIF_MON9 0x00f4
54#define AFE_ADDA_DL_SRC2_CON0 0x0108
55#define AFE_ADDA_DL_SRC2_CON1 0x010c
56#define AFE_ADDA_UL_SRC_CON0 0x0114
57#define AFE_ADDA_UL_SRC_CON1 0x0118
58#define AFE_ADDA_TOP_CON0 0x0120
59#define AFE_ADDA_UL_DL_CON0 0x0124
60#define AFE_ADDA_SRC_DEBUG 0x012c
61#define AFE_ADDA_SRC_DEBUG_MON0 0x0130
62#define AFE_ADDA_SRC_DEBUG_MON1 0x0134
63#define AFE_ADDA_UL_SRC_MON0 0x0148
64#define AFE_ADDA_UL_SRC_MON1 0x014c
65#define AFE_SIDETONE_DEBUG 0x01d0
66#define AFE_SIDETONE_MON 0x01d4
67#define AFE_SINEGEN_CON2 0x01dc
68#define AFE_SIDETONE_CON0 0x01e0
69#define AFE_SIDETONE_COEFF 0x01e4
70#define AFE_SIDETONE_CON1 0x01e8
71#define AFE_SIDETONE_GAIN 0x01ec
72#define AFE_SINEGEN_CON0 0x01f0
73#define AFE_TOP_CON0 0x0200
74#define AFE_BUS_CFG 0x0240
75#define AFE_BUS_MON0 0x0244
76#define AFE_ADDA_PREDIS_CON0 0x0260
77#define AFE_ADDA_PREDIS_CON1 0x0264
78#define AFE_MRGIF_MON0 0x0270
79#define AFE_MRGIF_MON1 0x0274
80#define AFE_MRGIF_MON2 0x0278
81#define AFE_I2S_MON 0x027c
82#define AFE_ADDA_IIR_COEF_02_01 0x0290
83#define AFE_ADDA_IIR_COEF_04_03 0x0294
84#define AFE_ADDA_IIR_COEF_06_05 0x0298
85#define AFE_ADDA_IIR_COEF_08_07 0x029c
86#define AFE_ADDA_IIR_COEF_10_09 0x02a0
87#define AFE_DAC_CON2 0x02e0
88#define AFE_IRQ_MCU_CON1 0x02e4
89#define AFE_IRQ_MCU_CON2 0x02e8
90#define AFE_DAC_MON 0x02ec
91#define AFE_VUL2_BASE 0x02f0
92#define AFE_VUL2_END 0x02f8
93#define AFE_VUL2_CUR 0x02fc
94#define AFE_IRQ_MCU_CNT0 0x0300
95#define AFE_IRQ_MCU_CNT6 0x0304
96#define AFE_IRQ_MCU_CNT8 0x0308
97#define AFE_IRQ_MCU_EN1 0x030c
98#define AFE_IRQ0_MCU_CNT_MON 0x0310
99#define AFE_IRQ6_MCU_CNT_MON 0x0314
100#define AFE_MOD_DAI_BASE 0x0330
101#define AFE_MOD_DAI_END 0x0338
102#define AFE_MOD_DAI_CUR 0x033c
103#define AFE_VUL_D2_BASE 0x0350
104#define AFE_VUL_D2_END 0x0358
105#define AFE_VUL_D2_CUR 0x035c
106#define AFE_DL3_BASE 0x0360
107#define AFE_DL3_CUR 0x0364
108#define AFE_DL3_END 0x0368
109#define AFE_HDMI_OUT_CON0 0x0370
110#define AFE_HDMI_OUT_BASE 0x0374
111#define AFE_HDMI_OUT_CUR 0x0378
112#define AFE_HDMI_OUT_END 0x037c
113#define AFE_HDMI_CONN0 0x0390
114#define AFE_IRQ3_MCU_CNT_MON 0x0398
115#define AFE_IRQ4_MCU_CNT_MON 0x039c
116#define AFE_IRQ_MCU_CON0 0x03a0
117#define AFE_IRQ_MCU_STATUS 0x03a4
118#define AFE_IRQ_MCU_CLR 0x03a8
119#define AFE_IRQ_MCU_CNT1 0x03ac
120#define AFE_IRQ_MCU_CNT2 0x03b0
121#define AFE_IRQ_MCU_EN 0x03b4
122#define AFE_IRQ_MCU_MON2 0x03b8
123#define AFE_IRQ_MCU_CNT5 0x03bc
124#define AFE_IRQ1_MCU_CNT_MON 0x03c0
125#define AFE_IRQ2_MCU_CNT_MON 0x03c4
126#define AFE_IRQ1_MCU_EN_CNT_MON 0x03c8
127#define AFE_IRQ5_MCU_CNT_MON 0x03cc
128#define AFE_MEMIF_MINLEN 0x03d0
129#define AFE_MEMIF_MAXLEN 0x03d4
130#define AFE_MEMIF_PBUF_SIZE 0x03d8
131#define AFE_IRQ_MCU_CNT7 0x03dc
132#define AFE_IRQ7_MCU_CNT_MON 0x03e0
133#define AFE_IRQ_MCU_CNT3 0x03e4
134#define AFE_IRQ_MCU_CNT4 0x03e8
135#define AFE_IRQ_MCU_CNT11 0x03ec
136#define AFE_APLL1_TUNER_CFG 0x03f0
137#define AFE_APLL2_TUNER_CFG 0x03f4
138#define AFE_MEMIF_HD_MODE 0x03f8
139#define AFE_MEMIF_HDALIGN 0x03fc
140#define AFE_CONN33 0x0408
141#define AFE_IRQ_MCU_CNT12 0x040c
142#define AFE_GAIN1_CON0 0x0410
143#define AFE_GAIN1_CON1 0x0414
144#define AFE_GAIN1_CON2 0x0418
145#define AFE_GAIN1_CON3 0x041c
146#define AFE_CONN7 0x0420
147#define AFE_GAIN1_CUR 0x0424
148#define AFE_GAIN2_CON0 0x0428
149#define AFE_GAIN2_CON1 0x042c
150#define AFE_GAIN2_CON2 0x0430
151#define AFE_GAIN2_CON3 0x0434
152#define AFE_CONN8 0x0438
153#define AFE_GAIN2_CUR 0x043c
154#define AFE_CONN9 0x0440
155#define AFE_CONN10 0x0444
156#define AFE_CONN11 0x0448
157#define AFE_CONN12 0x044c
158#define AFE_CONN13 0x0450
159#define AFE_CONN14 0x0454
160#define AFE_CONN15 0x0458
161#define AFE_CONN16 0x045c
162#define AFE_CONN17 0x0460
163#define AFE_CONN18 0x0464
164#define AFE_CONN19 0x0468
165#define AFE_CONN20 0x046c
166#define AFE_CONN21 0x0470
167#define AFE_CONN22 0x0474
168#define AFE_CONN23 0x0478
169#define AFE_CONN24 0x047c
170#define AFE_CONN_RS 0x0494
171#define AFE_CONN_DI 0x0498
172#define AFE_CONN25 0x04b0
173#define AFE_CONN26 0x04b4
174#define AFE_CONN27 0x04b8
175#define AFE_CONN28 0x04bc
176#define AFE_CONN29 0x04c0
177#define AFE_CONN30 0x04c4
178#define AFE_CONN31 0x04c8
179#define AFE_CONN32 0x04cc
180#define AFE_SRAM_DELSEL_CON0 0x04f0
181#define AFE_SRAM_DELSEL_CON2 0x04f8
182#define AFE_SRAM_DELSEL_CON3 0x04fc
183#define AFE_ASRC_2CH_CON12 0x0528
184#define AFE_ASRC_2CH_CON13 0x052c
185#define PCM_INTF_CON1 0x0530
186#define PCM_INTF_CON2 0x0538
187#define PCM2_INTF_CON 0x053c
188#define AFE_TDM_CON1 0x0548
189#define AFE_TDM_CON2 0x054c
190#define AFE_CONN34 0x0580
191#define FPGA_CFG0 0x05b0
192#define FPGA_CFG1 0x05b4
193#define FPGA_CFG2 0x05c0
194#define FPGA_CFG3 0x05c4
195#define AUDIO_TOP_DBG_CON 0x05c8
196#define AUDIO_TOP_DBG_MON0 0x05cc
197#define AUDIO_TOP_DBG_MON1 0x05d0
198#define AFE_IRQ8_MCU_CNT_MON 0x05e4
199#define AFE_IRQ11_MCU_CNT_MON 0x05e8
200#define AFE_IRQ12_MCU_CNT_MON 0x05ec
201#define AFE_GENERAL_REG0 0x0800
202#define AFE_GENERAL_REG1 0x0804
203#define AFE_GENERAL_REG2 0x0808
204#define AFE_GENERAL_REG3 0x080c
205#define AFE_GENERAL_REG4 0x0810
206#define AFE_GENERAL_REG5 0x0814
207#define AFE_GENERAL_REG6 0x0818
208#define AFE_GENERAL_REG7 0x081c
209#define AFE_GENERAL_REG8 0x0820
210#define AFE_GENERAL_REG9 0x0824
211#define AFE_GENERAL_REG10 0x0828
212#define AFE_GENERAL_REG11 0x082c
213#define AFE_GENERAL_REG12 0x0830
214#define AFE_GENERAL_REG13 0x0834
215#define AFE_GENERAL_REG14 0x0838
216#define AFE_GENERAL_REG15 0x083c
217#define AFE_CBIP_CFG0 0x0840
218#define AFE_CBIP_MON0 0x0844
219#define AFE_CBIP_SLV_MUX_MON0 0x0848
220#define AFE_CBIP_SLV_DECODER_MON0 0x084c
221#define AFE_CONN0_1 0x0900
222#define AFE_CONN1_1 0x0904
223#define AFE_CONN2_1 0x0908
224#define AFE_CONN3_1 0x090c
225#define AFE_CONN4_1 0x0910
226#define AFE_CONN5_1 0x0914
227#define AFE_CONN6_1 0x0918
228#define AFE_CONN7_1 0x091c
229#define AFE_CONN8_1 0x0920
230#define AFE_CONN9_1 0x0924
231#define AFE_CONN10_1 0x0928
232#define AFE_CONN11_1 0x092c
233#define AFE_CONN12_1 0x0930
234#define AFE_CONN13_1 0x0934
235#define AFE_CONN14_1 0x0938
236#define AFE_CONN15_1 0x093c
237#define AFE_CONN16_1 0x0940
238#define AFE_CONN17_1 0x0944
239#define AFE_CONN18_1 0x0948
240#define AFE_CONN19_1 0x094c
241#define AFE_CONN20_1 0x0950
242#define AFE_CONN21_1 0x0954
243#define AFE_CONN22_1 0x0958
244#define AFE_CONN23_1 0x095c
245#define AFE_CONN24_1 0x0960
246#define AFE_CONN25_1 0x0964
247#define AFE_CONN26_1 0x0968
248#define AFE_CONN27_1 0x096c
249#define AFE_CONN28_1 0x0970
250#define AFE_CONN29_1 0x0974
251#define AFE_CONN30_1 0x0978
252#define AFE_CONN31_1 0x097c
253#define AFE_CONN32_1 0x0980
254#define AFE_CONN33_1 0x0984
255#define AFE_CONN34_1 0x0988
256#define AFE_CONN_RS_1 0x098c
257#define AFE_CONN_DI_1 0x0990
258#define AFE_CONN_24BIT_1 0x0994
259#define AFE_CONN_REG 0x0998
260#define AFE_CONN35 0x09a0
261#define AFE_CONN36 0x09a4
262#define AFE_CONN37 0x09a8
263#define AFE_CONN38 0x09ac
264#define AFE_CONN35_1 0x09b0
265#define AFE_CONN36_1 0x09b4
266#define AFE_CONN37_1 0x09b8
267#define AFE_CONN38_1 0x09bc
268#define AFE_CONN39 0x09c0
269#define AFE_CONN40 0x09c4
270#define AFE_CONN41 0x09c8
271#define AFE_CONN42 0x09cc
272#define AFE_CONN39_1 0x09e0
273#define AFE_CONN40_1 0x09e4
274#define AFE_CONN41_1 0x09e8
275#define AFE_CONN42_1 0x09ec
276#define AFE_I2S_CON4 0x09f8
277#define AFE_ADDA6_TOP_CON0 0x0a80
278#define AFE_ADDA6_UL_SRC_CON0 0x0a84
279#define AFE_ADD6_UL_SRC_CON1 0x0a88
280#define AFE_ADDA6_SRC_DEBUG 0x0a8c
281#define AFE_ADDA6_SRC_DEBUG_MON0 0x0a90
282#define AFE_ADDA6_ULCF_CFG_02_01 0x0aa0
283#define AFE_ADDA6_ULCF_CFG_04_03 0x0aa4
284#define AFE_ADDA6_ULCF_CFG_06_05 0x0aa8
285#define AFE_ADDA6_ULCF_CFG_08_07 0x0aac
286#define AFE_ADDA6_ULCF_CFG_10_09 0x0ab0
287#define AFE_ADDA6_ULCF_CFG_12_11 0x0ab4
288#define AFE_ADDA6_ULCF_CFG_14_13 0x0ab8
289#define AFE_ADDA6_ULCF_CFG_16_15 0x0abc
290#define AFE_ADDA6_ULCF_CFG_18_17 0x0ac0
291#define AFE_ADDA6_ULCF_CFG_20_19 0x0ac4
292#define AFE_ADDA6_ULCF_CFG_22_21 0x0ac8
293#define AFE_ADDA6_ULCF_CFG_24_23 0x0acc
294#define AFE_ADDA6_ULCF_CFG_26_25 0x0ad0
295#define AFE_ADDA6_ULCF_CFG_28_27 0x0ad4
296#define AFE_ADDA6_ULCF_CFG_30_29 0x0ad8
297#define AFE_ADD6A_UL_SRC_MON0 0x0ae4
298#define AFE_ADDA6_UL_SRC_MON1 0x0ae8
299#define AFE_CONN43 0x0af8
300#define AFE_CONN43_1 0x0afc
301#define AFE_DL1_BASE_MSB 0x0b00
302#define AFE_DL1_CUR_MSB 0x0b04
303#define AFE_DL1_END_MSB 0x0b08
304#define AFE_DL2_BASE_MSB 0x0b10
305#define AFE_DL2_CUR_MSB 0x0b14
306#define AFE_DL2_END_MSB 0x0b18
307#define AFE_AWB_BASE_MSB 0x0b20
308#define AFE_AWB_END_MSB 0x0b28
309#define AFE_AWB_CUR_MSB 0x0b2c
310#define AFE_VUL_BASE_MSB 0x0b30
311#define AFE_VUL_END_MSB 0x0b38
312#define AFE_VUL_CUR_MSB 0x0b3c
313#define AFE_VUL2_BASE_MSB 0x0b50
314#define AFE_VUL2_END_MSB 0x0b58
315#define AFE_VUL2_CUR_MSB 0x0b5c
316#define AFE_MOD_DAI_BASE_MSB 0x0b60
317#define AFE_MOD_DAI_END_MSB 0x0b68
318#define AFE_MOD_DAI_CUR_MSB 0x0b6c
319#define AFE_VUL_D2_BASE_MSB 0x0b80
320#define AFE_VUL_D2_END_MSB 0x0b88
321#define AFE_VUL_D2_CUR_MSB 0x0b8c
322#define AFE_DL3_BASE_MSB 0x0b90
323#define AFE_DL3_CUR_MSB 0x0b94
324#define AFE_DL3_END_MSB 0x0b98
325#define AFE_HDMI_OUT_BASE_MSB 0x0ba4
326#define AFE_HDMI_OUT_CUR_MSB 0x0ba8
327#define AFE_HDMI_OUT_END_MSB 0x0bac
328#define AFE_AWB2_BASE 0x0bd0
329#define AFE_AWB2_END 0x0bd8
330#define AFE_AWB2_CUR 0x0bdc
331#define AFE_AWB2_BASE_MSB 0x0be0
332#define AFE_AWB2_END_MSB 0x0be8
333#define AFE_AWB2_CUR_MSB 0x0bec
334#define AFE_ADDA_DL_SDM_DCCOMP_CON 0x0c50
335#define AFE_ADDA_DL_SDM_TEST 0x0c54
336#define AFE_ADDA_DL_DC_COMP_CFG0 0x0c58
337#define AFE_ADDA_DL_DC_COMP_CFG1 0x0c5c
338#define AFE_ADDA_DL_SDM_FIFO_MON 0x0c60
339#define AFE_ADDA_DL_SRC_LCH_MON 0x0c64
340#define AFE_ADDA_DL_SRC_RCH_MON 0x0c68
341#define AFE_ADDA_DL_SDM_OUT_MON 0x0c6c
342#define AFE_CONNSYS_I2S_CON 0x0c78
343#define AFE_CONNSYS_I2S_MON 0x0c7c
344#define AFE_ASRC_2CH_CON0 0x0c80
345#define AFE_ASRC_2CH_CON1 0x0c84
346#define AFE_ASRC_2CH_CON2 0x0c88
347#define AFE_ASRC_2CH_CON3 0x0c8c
348#define AFE_ASRC_2CH_CON4 0x0c90
349#define AFE_ASRC_2CH_CON5 0x0c94
350#define AFE_ASRC_2CH_CON6 0x0c98
351#define AFE_ASRC_2CH_CON7 0x0c9c
352#define AFE_ASRC_2CH_CON8 0x0ca0
353#define AFE_ASRC_2CH_CON9 0x0ca4
354#define AFE_ASRC_2CH_CON10 0x0ca8
355#define AFE_ADDA6_IIR_COEF_02_01 0x0ce0
356#define AFE_ADDA6_IIR_COEF_04_03 0x0ce4
357#define AFE_ADDA6_IIR_COEF_06_05 0x0ce8
358#define AFE_ADDA6_IIR_COEF_08_07 0x0cec
359#define AFE_ADDA6_IIR_COEF_10_09 0x0cf0
360#define AFE_ADDA_PREDIS_CON2 0x0d40
361#define AFE_ADDA_PREDIS_CON3 0x0d44
362#define AFE_MEMIF_MON12 0x0d70
363#define AFE_MEMIF_MON13 0x0d74
364#define AFE_MEMIF_MON14 0x0d78
365#define AFE_MEMIF_MON15 0x0d7c
366#define AFE_MEMIF_MON16 0x0d80
367#define AFE_MEMIF_MON17 0x0d84
368#define AFE_MEMIF_MON18 0x0d88
369#define AFE_MEMIF_MON19 0x0d8c
370#define AFE_MEMIF_MON20 0x0d90
371#define AFE_MEMIF_MON21 0x0d94
372#define AFE_MEMIF_MON22 0x0d98
373#define AFE_MEMIF_MON23 0x0d9c
374#define AFE_MEMIF_MON24 0x0da0
375#define AFE_HD_ENGEN_ENABLE 0x0dd0
376#define AFE_ADDA_MTKAIF_CFG0 0x0e00
377#define AFE_ADDA_MTKAIF_TX_CFG1 0x0e14
378#define AFE_ADDA_MTKAIF_RX_CFG0 0x0e20
379#define AFE_ADDA_MTKAIF_RX_CFG1 0x0e24
380#define AFE_ADDA_MTKAIF_RX_CFG2 0x0e28
381#define AFE_ADDA_MTKAIF_MON0 0x0e34
382#define AFE_ADDA_MTKAIF_MON1 0x0e38
383#define AFE_AUD_PAD_TOP 0x0e40
384#define AFE_GENERAL1_ASRC_2CH_CON0 0x0e80
385#define AFE_GENERAL1_ASRC_2CH_CON1 0x0e84
386#define AFE_GENERAL1_ASRC_2CH_CON2 0x0e88
387#define AFE_GENERAL1_ASRC_2CH_CON3 0x0e8c
388#define AFE_GENERAL1_ASRC_2CH_CON4 0x0e90
389#define AFE_GENERAL1_ASRC_2CH_CON5 0x0e94
390#define AFE_GENERAL1_ASRC_2CH_CON6 0x0e98
391#define AFE_GENERAL1_ASRC_2CH_CON7 0x0e9c
392#define AFE_GENERAL1_ASRC_2CH_CON8 0x0ea0
393#define AFE_GENERAL1_ASRC_2CH_CON9 0x0ea4
394#define AFE_GENERAL1_ASRC_2CH_CON10 0x0ea8
395#define AFE_GENERAL1_ASRC_2CH_CON12 0x0eb0
396#define AFE_GENERAL1_ASRC_2CH_CON13 0x0eb4
397#define GENERAL_ASRC_MODE 0x0eb8
398#define GENERAL_ASRC_EN_ON 0x0ebc
399#define AFE_GENERAL2_ASRC_2CH_CON0 0x0f00
400#define AFE_GENERAL2_ASRC_2CH_CON1 0x0f04
401#define AFE_GENERAL2_ASRC_2CH_CON2 0x0f08
402#define AFE_GENERAL2_ASRC_2CH_CON3 0x0f0c
403#define AFE_GENERAL2_ASRC_2CH_CON4 0x0f10
404#define AFE_GENERAL2_ASRC_2CH_CON5 0x0f14
405#define AFE_GENERAL2_ASRC_2CH_CON6 0x0f18
406#define AFE_GENERAL2_ASRC_2CH_CON7 0x0f1c
407#define AFE_GENERAL2_ASRC_2CH_CON8 0x0f20
408#define AFE_GENERAL2_ASRC_2CH_CON9 0x0f24
409#define AFE_GENERAL2_ASRC_2CH_CON10 0x0f28
410#define AFE_GENERAL2_ASRC_2CH_CON12 0x0f30
411#define AFE_GENERAL2_ASRC_2CH_CON13 0x0f34
412
413#define AFE_MAX_REGISTER AFE_GENERAL2_ASRC_2CH_CON13
414#define AFE_IRQ_STATUS_BITS 0x1fff
415
416/* AFE_DAC_CON0 */
417#define AWB2_ON_SFT 29
418#define AWB2_ON_MASK 0x1
419#define AWB2_ON_MASK_SFT (0x1 << 29)
420#define VUL2_ON_SFT 27
421#define VUL2_ON_MASK 0x1
422#define VUL2_ON_MASK_SFT (0x1 << 27)
423#define MOD_DAI_DUP_WR_SFT 26
424#define MOD_DAI_DUP_WR_MASK 0x1
425#define MOD_DAI_DUP_WR_MASK_SFT (0x1 << 26)
426#define VUL12_MODE_SFT 20
427#define VUL12_MODE_MASK 0xf
428#define VUL12_MODE_MASK_SFT (0xf << 20)
429#define VUL12_R_MONO_SFT 11
430#define VUL12_R_MONO_MASK 0x1
431#define VUL12_R_MONO_MASK_SFT (0x1 << 11)
432#define VUL12_MONO_SFT 10
433#define VUL12_MONO_MASK 0x1
434#define VUL12_MONO_MASK_SFT (0x1 << 10)
435#define VUL12_ON_SFT 9
436#define VUL12_ON_MASK 0x1
437#define VUL12_ON_MASK_SFT (0x1 << 9)
438#define MOD_DAI_ON_SFT 7
439#define MOD_DAI_ON_MASK 0x1
440#define MOD_DAI_ON_MASK_SFT (0x1 << 7)
441#define AWB_ON_SFT 6
442#define AWB_ON_MASK 0x1
443#define AWB_ON_MASK_SFT (0x1 << 6)
444#define DL3_ON_SFT 5
445#define DL3_ON_MASK 0x1
446#define DL3_ON_MASK_SFT (0x1 << 5)
447#define VUL_ON_SFT 3
448#define VUL_ON_MASK 0x1
449#define VUL_ON_MASK_SFT (0x1 << 3)
450#define DL2_ON_SFT 2
451#define DL2_ON_MASK 0x1
452#define DL2_ON_MASK_SFT (0x1 << 2)
453#define DL1_ON_SFT 1
454#define DL1_ON_MASK 0x1
455#define DL1_ON_MASK_SFT (0x1 << 1)
456#define AFE_ON_SFT 0
457#define AFE_ON_MASK 0x1
458#define AFE_ON_MASK_SFT (0x1 << 0)
459
460/* AFE_DAC_CON1 */
461#define MOD_DAI_MODE_SFT 30
462#define MOD_DAI_MODE_MASK 0x3
463#define MOD_DAI_MODE_MASK_SFT (0x3 << 30)
464#define VUL_R_MONO_SFT 28
465#define VUL_R_MONO_MASK 0x1
466#define VUL_R_MONO_MASK_SFT (0x1 << 28)
467#define VUL_DATA_SFT 27
468#define VUL_DATA_MASK 0x1
469#define VUL_DATA_MASK_SFT (0x1 << 27)
470#define AWB_R_MONO_SFT 25
471#define AWB_R_MONO_MASK 0x1
472#define AWB_R_MONO_MASK_SFT (0x1 << 25)
473#define AWB_DATA_SFT 24
474#define AWB_DATA_MASK 0x1
475#define AWB_DATA_MASK_SFT (0x1 << 24)
476#define DL3_DATA_SFT 23
477#define DL3_DATA_MASK 0x1
478#define DL3_DATA_MASK_SFT (0x1 << 23)
479#define DL2_DATA_SFT 22
480#define DL2_DATA_MASK 0x1
481#define DL2_DATA_MASK_SFT (0x1 << 22)
482#define DL1_DATA_SFT 21
483#define DL1_DATA_MASK 0x1
484#define DL1_DATA_MASK_SFT (0x1 << 21)
485#define VUL_MODE_SFT 16
486#define VUL_MODE_MASK 0xf
487#define VUL_MODE_MASK_SFT (0xf << 16)
488#define AWB_MODE_SFT 12
489#define AWB_MODE_MASK 0xf
490#define AWB_MODE_MASK_SFT (0xf << 12)
491#define I2S_MODE_SFT 8
492#define I2S_MODE_MASK 0xf
493#define I2S_MODE_MASK_SFT (0xf << 8)
494#define DL2_MODE_SFT 4
495#define DL2_MODE_MASK 0xf
496#define DL2_MODE_MASK_SFT (0xf << 4)
497#define DL1_MODE_SFT 0
498#define DL1_MODE_MASK 0xf
499#define DL1_MODE_MASK_SFT (0xf << 0)
500
501/* AFE_DAC_CON2 */
502#define AWB2_R_MONO_SFT 21
503#define AWB2_R_MONO_MASK 0x1
504#define AWB2_R_MONO_MASK_SFT (0x1 << 21)
505#define AWB2_DATA_SFT 20
506#define AWB2_DATA_MASK 0x1
507#define AWB2_DATA_MASK_SFT (0x1 << 20)
508#define AWB2_MODE_SFT 16
509#define AWB2_MODE_MASK 0xf
510#define AWB2_MODE_MASK_SFT (0xf << 16)
511#define DL3_MODE_SFT 8
512#define DL3_MODE_MASK 0xf
513#define DL3_MODE_MASK_SFT (0xf << 8)
514#define VUL2_MODE_SFT 4
515#define VUL2_MODE_MASK 0xf
516#define VUL2_MODE_MASK_SFT (0xf << 4)
517#define VUL2_R_MONO_SFT 1
518#define VUL2_R_MONO_MASK 0x1
519#define VUL2_R_MONO_MASK_SFT (0x1 << 1)
520#define VUL2_DATA_SFT 0
521#define VUL2_DATA_MASK 0x1
522#define VUL2_DATA_MASK_SFT (0x1 << 0)
523
524/* AFE_DAC_MON */
525#define AFE_ON_RETM_SFT 0
526#define AFE_ON_RETM_MASK 0x1
527#define AFE_ON_RETM_MASK_SFT (0x1 << 0)
528
529/* AFE_I2S_CON */
530#define BCK_NEG_EG_LATCH_SFT 30
531#define BCK_NEG_EG_LATCH_MASK 0x1
532#define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)
533#define BCK_INV_SFT 29
534#define BCK_INV_MASK 0x1
535#define BCK_INV_MASK_SFT (0x1 << 29)
536#define I2SIN_PAD_SEL_SFT 28
537#define I2SIN_PAD_SEL_MASK 0x1
538#define I2SIN_PAD_SEL_MASK_SFT (0x1 << 28)
539#define I2S_LOOPBACK_SFT 20
540#define I2S_LOOPBACK_MASK 0x1
541#define I2S_LOOPBACK_MASK_SFT (0x1 << 20)
542#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17
543#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
544#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
545#define I2S1_HD_EN_SFT 12
546#define I2S1_HD_EN_MASK 0x1
547#define I2S1_HD_EN_MASK_SFT (0x1 << 12)
548#define INV_PAD_CTRL_SFT 7
549#define INV_PAD_CTRL_MASK 0x1
550#define INV_PAD_CTRL_MASK_SFT (0x1 << 7)
551#define I2S_BYPSRC_SFT 6
552#define I2S_BYPSRC_MASK 0x1
553#define I2S_BYPSRC_MASK_SFT (0x1 << 6)
554#define INV_LRCK_SFT 5
555#define INV_LRCK_MASK 0x1
556#define INV_LRCK_MASK_SFT (0x1 << 5)
557#define I2S_FMT_SFT 3
558#define I2S_FMT_MASK 0x1
559#define I2S_FMT_MASK_SFT (0x1 << 3)
560#define I2S_SRC_SFT 2
561#define I2S_SRC_MASK 0x1
562#define I2S_SRC_MASK_SFT (0x1 << 2)
563#define I2S_WLEN_SFT 1
564#define I2S_WLEN_MASK 0x1
565#define I2S_WLEN_MASK_SFT (0x1 << 1)
566#define I2S_EN_SFT 0
567#define I2S_EN_MASK 0x1
568#define I2S_EN_MASK_SFT (0x1 << 0)
569
570/* AFE_I2S_CON1 */
571#define I2S2_LR_SWAP_SFT 31
572#define I2S2_LR_SWAP_MASK 0x1
573#define I2S2_LR_SWAP_MASK_SFT (0x1 << 31)
574#define I2S2_SEL_O19_O20_SFT 18
575#define I2S2_SEL_O19_O20_MASK 0x1
576#define I2S2_SEL_O19_O20_MASK_SFT (0x1 << 18)
577#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17
578#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
579#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
580#define I2S2_SEL_O03_O04_SFT 16
581#define I2S2_SEL_O03_O04_MASK 0x1
582#define I2S2_SEL_O03_O04_MASK_SFT (0x1 << 16)
583#define I2S2_32BIT_EN_SFT 13
584#define I2S2_32BIT_EN_MASK 0x1
585#define I2S2_32BIT_EN_MASK_SFT (0x1 << 13)
586#define I2S2_HD_EN_SFT 12
587#define I2S2_HD_EN_MASK 0x1
588#define I2S2_HD_EN_MASK_SFT (0x1 << 12)
589#define I2S2_OUT_MODE_SFT 8
590#define I2S2_OUT_MODE_MASK 0xf
591#define I2S2_OUT_MODE_MASK_SFT (0xf << 8)
592#define INV_LRCK_SFT 5
593#define INV_LRCK_MASK 0x1
594#define INV_LRCK_MASK_SFT (0x1 << 5)
595#define I2S2_FMT_SFT 3
596#define I2S2_FMT_MASK 0x1
597#define I2S2_FMT_MASK_SFT (0x1 << 3)
598#define I2S2_WLEN_SFT 1
599#define I2S2_WLEN_MASK 0x1
600#define I2S2_WLEN_MASK_SFT (0x1 << 1)
601#define I2S2_EN_SFT 0
602#define I2S2_EN_MASK 0x1
603#define I2S2_EN_MASK_SFT (0x1 << 0)
604
605/* AFE_I2S_CON2 */
606#define I2S3_LR_SWAP_SFT 31
607#define I2S3_LR_SWAP_MASK 0x1
608#define I2S3_LR_SWAP_MASK_SFT (0x1 << 31)
609#define I2S3_UPDATE_WORD_SFT 24
610#define I2S3_UPDATE_WORD_MASK 0x1f
611#define I2S3_UPDATE_WORD_MASK_SFT (0x1f << 24)
612#define I2S3_BCK_INV_SFT 23
613#define I2S3_BCK_INV_MASK 0x1
614#define I2S3_BCK_INV_MASK_SFT (0x1 << 23)
615#define I2S3_FPGA_BIT_TEST_SFT 22
616#define I2S3_FPGA_BIT_TEST_MASK 0x1
617#define I2S3_FPGA_BIT_TEST_MASK_SFT (0x1 << 22)
618#define I2S3_FPGA_BIT_SFT 21
619#define I2S3_FPGA_BIT_MASK 0x1
620#define I2S3_FPGA_BIT_MASK_SFT (0x1 << 21)
621#define I2S3_LOOPBACK_SFT 20
622#define I2S3_LOOPBACK_MASK 0x1
623#define I2S3_LOOPBACK_MASK_SFT (0x1 << 20)
624#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17
625#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
626#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
627#define I2S3_HD_EN_SFT 12
628#define I2S3_HD_EN_MASK 0x1
629#define I2S3_HD_EN_MASK_SFT (0x1 << 12)
630#define I2S3_OUT_MODE_SFT 8
631#define I2S3_OUT_MODE_MASK 0xf
632#define I2S3_OUT_MODE_MASK_SFT (0xf << 8)
633#define I2S3_FMT_SFT 3
634#define I2S3_FMT_MASK 0x1
635#define I2S3_FMT_MASK_SFT (0x1 << 3)
636#define I2S3_WLEN_SFT 1
637#define I2S3_WLEN_MASK 0x1
638#define I2S3_WLEN_MASK_SFT (0x1 << 1)
639#define I2S3_EN_SFT 0
640#define I2S3_EN_MASK 0x1
641#define I2S3_EN_MASK_SFT (0x1 << 0)
642
643/* AFE_I2S_CON3 */
644#define I2S4_LR_SWAP_SFT 31
645#define I2S4_LR_SWAP_MASK 0x1
646#define I2S4_LR_SWAP_MASK_SFT (0x1 << 31)
647#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17
648#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
649#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
650#define I2S4_32BIT_EN_SFT 13
651#define I2S4_32BIT_EN_MASK 0x1
652#define I2S4_32BIT_EN_MASK_SFT (0x1 << 13)
653#define I2S4_HD_EN_SFT 12
654#define I2S4_HD_EN_MASK 0x1
655#define I2S4_HD_EN_MASK_SFT (0x1 << 12)
656#define I2S4_OUT_MODE_SFT 8
657#define I2S4_OUT_MODE_MASK 0xf
658#define I2S4_OUT_MODE_MASK_SFT (0xf << 8)
659#define INV_LRCK_SFT 5
660#define INV_LRCK_MASK 0x1
661#define INV_LRCK_MASK_SFT (0x1 << 5)
662#define I2S4_FMT_SFT 3
663#define I2S4_FMT_MASK 0x1
664#define I2S4_FMT_MASK_SFT (0x1 << 3)
665#define I2S4_WLEN_SFT 1
666#define I2S4_WLEN_MASK 0x1
667#define I2S4_WLEN_MASK_SFT (0x1 << 1)
668#define I2S4_EN_SFT 0
669#define I2S4_EN_MASK 0x1
670#define I2S4_EN_MASK_SFT (0x1 << 0)
671
672/* AFE_I2S_CON4 */
673#define I2S5_LR_SWAP_SFT 31
674#define I2S5_LR_SWAP_MASK 0x1
675#define I2S5_LR_SWAP_MASK_SFT (0x1 << 31)
676#define I2S_LOOPBACK_SFT 20
677#define I2S_LOOPBACK_MASK 0x1
678#define I2S_LOOPBACK_MASK_SFT (0x1 << 20)
679#define I2S_ONOFF_NOT_RESET_CK_ENABLE_SFT 17
680#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
681#define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
682#define I2S5_32BIT_EN_SFT 13
683#define I2S5_32BIT_EN_MASK 0x1
684#define I2S5_32BIT_EN_MASK_SFT (0x1 << 13)
685#define I2S5_HD_EN_SFT 12
686#define I2S5_HD_EN_MASK 0x1
687#define I2S5_HD_EN_MASK_SFT (0x1 << 12)
688#define I2S5_OUT_MODE_SFT 8
689#define I2S5_OUT_MODE_MASK 0xf
690#define I2S5_OUT_MODE_MASK_SFT (0xf << 8)
691#define INV_LRCK_SFT 5
692#define INV_LRCK_MASK 0x1
693#define INV_LRCK_MASK_SFT (0x1 << 5)
694#define I2S5_FMT_SFT 3
695#define I2S5_FMT_MASK 0x1
696#define I2S5_FMT_MASK_SFT (0x1 << 3)
697#define I2S5_WLEN_SFT 1
698#define I2S5_WLEN_MASK 0x1
699#define I2S5_WLEN_MASK_SFT (0x1 << 1)
700#define I2S5_EN_SFT 0
701#define I2S5_EN_MASK 0x1
702#define I2S5_EN_MASK_SFT (0x1 << 0)
703
704/* AFE_GAIN1_CON0 */
705#define GAIN1_SAMPLE_PER_STEP_SFT 8
706#define GAIN1_SAMPLE_PER_STEP_MASK 0xff
707#define GAIN1_SAMPLE_PER_STEP_MASK_SFT (0xff << 8)
708#define GAIN1_MODE_SFT 4
709#define GAIN1_MODE_MASK 0xf
710#define GAIN1_MODE_MASK_SFT (0xf << 4)
711#define GAIN1_ON_SFT 0
712#define GAIN1_ON_MASK 0x1
713#define GAIN1_ON_MASK_SFT (0x1 << 0)
714
715/* AFE_GAIN1_CON1 */
716#define GAIN1_TARGET_SFT 0
717#define GAIN1_TARGET_MASK 0xfffff
718#define GAIN1_TARGET_MASK_SFT (0xfffff << 0)
719
720/* AFE_GAIN2_CON0 */
721#define GAIN2_SAMPLE_PER_STEP_SFT 8
722#define GAIN2_SAMPLE_PER_STEP_MASK 0xff
723#define GAIN2_SAMPLE_PER_STEP_MASK_SFT (0xff << 8)
724#define GAIN2_MODE_SFT 4
725#define GAIN2_MODE_MASK 0xf
726#define GAIN2_MODE_MASK_SFT (0xf << 4)
727#define GAIN2_ON_SFT 0
728#define GAIN2_ON_MASK 0x1
729#define GAIN2_ON_MASK_SFT (0x1 << 0)
730
731/* AFE_GAIN2_CON1 */
732#define GAIN2_TARGET_SFT 0
733#define GAIN2_TARGET_MASK 0xfffff
734#define GAIN2_TARGET_MASK_SFT (0xfffff << 0)
735
736/* AFE_GAIN1_CUR */
737#define AFE_GAIN1_CUR_SFT 0
738#define AFE_GAIN1_CUR_MASK 0xfffff
739#define AFE_GAIN1_CUR_MASK_SFT (0xfffff << 0)
740
741/* AFE_GAIN2_CUR */
742#define AFE_GAIN2_CUR_SFT 0
743#define AFE_GAIN2_CUR_MASK 0xfffff
744#define AFE_GAIN2_CUR_MASK_SFT (0xfffff << 0)
745
746/* AFE_MEMIF_HD_MODE */
747#define AWB2_HD_SFT 28
748#define AWB2_HD_MASK 0x3
749#define AWB2_HD_MASK_SFT (0x3 << 28)
750#define HDMI_HD_SFT 20
751#define HDMI_HD_MASK 0x3
752#define HDMI_HD_MASK_SFT (0x3 << 20)
753#define MOD_DAI_HD_SFT 18
754#define MOD_DAI_HD_MASK 0x3
755#define MOD_DAI_HD_MASK_SFT (0x3 << 18)
756#define DAI_HD_SFT 16
757#define DAI_HD_MASK 0x3
758#define DAI_HD_MASK_SFT (0x3 << 16)
759#define VUL2_HD_SFT 14
760#define VUL2_HD_MASK 0x3
761#define VUL2_HD_MASK_SFT (0x3 << 14)
762#define VUL12_HD_SFT 12
763#define VUL12_HD_MASK 0x3
764#define VUL12_HD_MASK_SFT (0x3 << 12)
765#define VUL_HD_SFT 10
766#define VUL_HD_MASK 0x3
767#define VUL_HD_MASK_SFT (0x3 << 10)
768#define AWB_HD_SFT 8
769#define AWB_HD_MASK 0x3
770#define AWB_HD_MASK_SFT (0x3 << 8)
771#define DL3_HD_SFT 6
772#define DL3_HD_MASK 0x3
773#define DL3_HD_MASK_SFT (0x3 << 6)
774#define DL2_HD_SFT 4
775#define DL2_HD_MASK 0x3
776#define DL2_HD_MASK_SFT (0x3 << 4)
777#define DL1_HD_SFT 0
778#define DL1_HD_MASK 0x3
779#define DL1_HD_MASK_SFT (0x3 << 0)
780
781/* AFE_MEMIF_HDALIGN */
782#define AWB2_NORMAL_MODE_SFT 30
783#define AWB2_NORMAL_MODE_MASK 0x1
784#define AWB2_NORMAL_MODE_MASK_SFT (0x1 << 30)
785#define HDMI_NORMAL_MODE_SFT 26
786#define HDMI_NORMAL_MODE_MASK 0x1
787#define HDMI_NORMAL_MODE_MASK_SFT (0x1 << 26)
788#define MOD_DAI_NORMAL_MODE_SFT 25
789#define MOD_DAI_NORMAL_MODE_MASK 0x1
790#define MOD_DAI_NORMAL_MODE_MASK_SFT (0x1 << 25)
791#define DAI_NORMAL_MODE_SFT 24
792#define DAI_NORMAL_MODE_MASK 0x1
793#define DAI_NORMAL_MODE_MASK_SFT (0x1 << 24)
794#define VUL2_NORMAL_MODE_SFT 23
795#define VUL2_NORMAL_MODE_MASK 0x1
796#define VUL2_NORMAL_MODE_MASK_SFT (0x1 << 23)
797#define VUL12_NORMAL_MODE_SFT 22
798#define VUL12_NORMAL_MODE_MASK 0x1
799#define VUL12_NORMAL_MODE_MASK_SFT (0x1 << 22)
800#define VUL_NORMAL_MODE_SFT 21
801#define VUL_NORMAL_MODE_MASK 0x1
802#define VUL_NORMAL_MODE_MASK_SFT (0x1 << 21)
803#define AWB_NORMAL_MODE_SFT 20
804#define AWB_NORMAL_MODE_MASK 0x1
805#define AWB_NORMAL_MODE_MASK_SFT (0x1 << 20)
806#define DL3_NORMAL_MODE_SFT 19
807#define DL3_NORMAL_MODE_MASK 0x1
808#define DL3_NORMAL_MODE_MASK_SFT (0x1 << 19)
809#define DL2_NORMAL_MODE_SFT 18
810#define DL2_NORMAL_MODE_MASK 0x1
811#define DL2_NORMAL_MODE_MASK_SFT (0x1 << 18)
812#define DL1_NORMAL_MODE_SFT 16
813#define DL1_NORMAL_MODE_MASK 0x1
814#define DL1_NORMAL_MODE_MASK_SFT (0x1 << 16)
815#define RESERVED1_SFT 15
816#define RESERVED1_MASK 0x1
817#define RESERVED1_MASK_SFT (0x1 << 15)
818#define AWB2_ALIGN_SFT 14
819#define AWB2_ALIGN_MASK 0x1
820#define AWB2_ALIGN_MASK_SFT (0x1 << 14)
821#define HDMI_HD_ALIGN_SFT 10
822#define HDMI_HD_ALIGN_MASK 0x1
823#define HDMI_HD_ALIGN_MASK_SFT (0x1 << 10)
824#define MOD_DAI_HD_ALIGN_SFT 9
825#define MOD_DAI_HD_ALIGN_MASK 0x1
826#define MOD_DAI_HD_ALIGN_MASK_SFT (0x1 << 9)
827#define VUL2_HD_ALIGN_SFT 7
828#define VUL2_HD_ALIGN_MASK 0x1
829#define VUL2_HD_ALIGN_MASK_SFT (0x1 << 7)
830#define VUL12_HD_ALIGN_SFT 6
831#define VUL12_HD_ALIGN_MASK 0x1
832#define VUL12_HD_ALIGN_MASK_SFT (0x1 << 6)
833#define VUL_HD_ALIGN_SFT 5
834#define VUL_HD_ALIGN_MASK 0x1
835#define VUL_HD_ALIGN_MASK_SFT (0x1 << 5)
836#define AWB_HD_ALIGN_SFT 4
837#define AWB_HD_ALIGN_MASK 0x1
838#define AWB_HD_ALIGN_MASK_SFT (0x1 << 4)
839#define DL3_HD_ALIGN_SFT 3
840#define DL3_HD_ALIGN_MASK 0x1
841#define DL3_HD_ALIGN_MASK_SFT (0x1 << 3)
842#define DL2_HD_ALIGN_SFT 2
843#define DL2_HD_ALIGN_MASK 0x1
844#define DL2_HD_ALIGN_MASK_SFT (0x1 << 2)
845#define DL1_HD_ALIGN_SFT 0
846#define DL1_HD_ALIGN_MASK 0x1
847#define DL1_HD_ALIGN_MASK_SFT (0x1 << 0)
848
849/* PCM_INTF_CON1 */
850#define PCM_FIX_VALUE_SEL_SFT 31
851#define PCM_FIX_VALUE_SEL_MASK 0x1
852#define PCM_FIX_VALUE_SEL_MASK_SFT (0x1 << 31)
853#define PCM_BUFFER_LOOPBACK_SFT 30
854#define PCM_BUFFER_LOOPBACK_MASK 0x1
855#define PCM_BUFFER_LOOPBACK_MASK_SFT (0x1 << 30)
856#define PCM_PARALLEL_LOOPBACK_SFT 29
857#define PCM_PARALLEL_LOOPBACK_MASK 0x1
858#define PCM_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 29)
859#define PCM_SERIAL_LOOPBACK_SFT 28
860#define PCM_SERIAL_LOOPBACK_MASK 0x1
861#define PCM_SERIAL_LOOPBACK_MASK_SFT (0x1 << 28)
862#define PCM_DAI_PCM_LOOPBACK_SFT 27
863#define PCM_DAI_PCM_LOOPBACK_MASK 0x1
864#define PCM_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 27)
865#define PCM_I2S_PCM_LOOPBACK_SFT 26
866#define PCM_I2S_PCM_LOOPBACK_MASK 0x1
867#define PCM_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 26)
868#define PCM_SYNC_DELSEL_SFT 25
869#define PCM_SYNC_DELSEL_MASK 0x1
870#define PCM_SYNC_DELSEL_MASK_SFT (0x1 << 25)
871#define PCM_TX_LR_SWAP_SFT 24
872#define PCM_TX_LR_SWAP_MASK 0x1
873#define PCM_TX_LR_SWAP_MASK_SFT (0x1 << 24)
874#define PCM_SYNC_OUT_INV_SFT 23
875#define PCM_SYNC_OUT_INV_MASK 0x1
876#define PCM_SYNC_OUT_INV_MASK_SFT (0x1 << 23)
877#define PCM_BCLK_OUT_INV_SFT 22
878#define PCM_BCLK_OUT_INV_MASK 0x1
879#define PCM_BCLK_OUT_INV_MASK_SFT (0x1 << 22)
880#define PCM_SYNC_IN_INV_SFT 21
881#define PCM_SYNC_IN_INV_MASK 0x1
882#define PCM_SYNC_IN_INV_MASK_SFT (0x1 << 21)
883#define PCM_BCLK_IN_INV_SFT 20
884#define PCM_BCLK_IN_INV_MASK 0x1
885#define PCM_BCLK_IN_INV_MASK_SFT (0x1 << 20)
886#define PCM_TX_LCH_RPT_SFT 19
887#define PCM_TX_LCH_RPT_MASK 0x1
888#define PCM_TX_LCH_RPT_MASK_SFT (0x1 << 19)
889#define PCM_VBT_16K_MODE_SFT 18
890#define PCM_VBT_16K_MODE_MASK 0x1
891#define PCM_VBT_16K_MODE_MASK_SFT (0x1 << 18)
892#define PCM_EXT_MODEM_SFT 17
893#define PCM_EXT_MODEM_MASK 0x1
894#define PCM_EXT_MODEM_MASK_SFT (0x1 << 17)
895#define PCM_24BIT_SFT 16
896#define PCM_24BIT_MASK 0x1
897#define PCM_24BIT_MASK_SFT (0x1 << 16)
898#define PCM_WLEN_SFT 14
899#define PCM_WLEN_MASK 0x3
900#define PCM_WLEN_MASK_SFT (0x3 << 14)
901#define PCM_SYNC_LENGTH_SFT 9
902#define PCM_SYNC_LENGTH_MASK 0x1f
903#define PCM_SYNC_LENGTH_MASK_SFT (0x1f << 9)
904#define PCM_SYNC_TYPE_SFT 8
905#define PCM_SYNC_TYPE_MASK 0x1
906#define PCM_SYNC_TYPE_MASK_SFT (0x1 << 8)
907#define PCM_BT_MODE_SFT 7
908#define PCM_BT_MODE_MASK 0x1
909#define PCM_BT_MODE_MASK_SFT (0x1 << 7)
910#define PCM_BYP_ASRC_SFT 6
911#define PCM_BYP_ASRC_MASK 0x1
912#define PCM_BYP_ASRC_MASK_SFT (0x1 << 6)
913#define PCM_SLAVE_SFT 5
914#define PCM_SLAVE_MASK 0x1
915#define PCM_SLAVE_MASK_SFT (0x1 << 5)
916#define PCM_MODE_SFT 3
917#define PCM_MODE_MASK 0x3
918#define PCM_MODE_MASK_SFT (0x3 << 3)
919#define PCM_FMT_SFT 1
920#define PCM_FMT_MASK 0x3
921#define PCM_FMT_MASK_SFT (0x3 << 1)
922#define PCM_EN_SFT 0
923#define PCM_EN_MASK 0x1
924#define PCM_EN_MASK_SFT (0x1 << 0)
925
926/* PCM_INTF_CON2 */
927#define PCM1_TX_FIFO_OV_SFT 31
928#define PCM1_TX_FIFO_OV_MASK 0x1
929#define PCM1_TX_FIFO_OV_MASK_SFT (0x1 << 31)
930#define PCM1_RX_FIFO_OV_SFT 30
931#define PCM1_RX_FIFO_OV_MASK 0x1
932#define PCM1_RX_FIFO_OV_MASK_SFT (0x1 << 30)
933#define PCM2_TX_FIFO_OV_SFT 29
934#define PCM2_TX_FIFO_OV_MASK 0x1
935#define PCM2_TX_FIFO_OV_MASK_SFT (0x1 << 29)
936#define PCM2_RX_FIFO_OV_SFT 28
937#define PCM2_RX_FIFO_OV_MASK 0x1
938#define PCM2_RX_FIFO_OV_MASK_SFT (0x1 << 28)
939#define PCM1_SYNC_GLITCH_SFT 27
940#define PCM1_SYNC_GLITCH_MASK 0x1
941#define PCM1_SYNC_GLITCH_MASK_SFT (0x1 << 27)
942#define PCM2_SYNC_GLITCH_SFT 26
943#define PCM2_SYNC_GLITCH_MASK 0x1
944#define PCM2_SYNC_GLITCH_MASK_SFT (0x1 << 26)
945#define TX3_RCH_DBG_MODE_SFT 17
946#define TX3_RCH_DBG_MODE_MASK 0x1
947#define TX3_RCH_DBG_MODE_MASK_SFT (0x1 << 17)
948#define PCM1_PCM2_LOOPBACK_SFT 16
949#define PCM1_PCM2_LOOPBACK_MASK 0x1
950#define PCM1_PCM2_LOOPBACK_MASK_SFT (0x1 << 16)
951#define DAI_PCM_LOOPBACK_CH_SFT 14
952#define DAI_PCM_LOOPBACK_CH_MASK 0x3
953#define DAI_PCM_LOOPBACK_CH_MASK_SFT (0x3 << 14)
954#define I2S_PCM_LOOPBACK_CH_SFT 12
955#define I2S_PCM_LOOPBACK_CH_MASK 0x3
956#define I2S_PCM_LOOPBACK_CH_MASK_SFT (0x3 << 12)
957#define TX_FIX_VALUE_SFT 0
958#define TX_FIX_VALUE_MASK 0xff
959#define TX_FIX_VALUE_MASK_SFT (0xff << 0)
960
961/* PCM2_INTF_CON */
962#define PCM2_TX_FIX_VALUE_SFT 24
963#define PCM2_TX_FIX_VALUE_MASK 0xff
964#define PCM2_TX_FIX_VALUE_MASK_SFT (0xff << 24)
965#define PCM2_FIX_VALUE_SEL_SFT 23
966#define PCM2_FIX_VALUE_SEL_MASK 0x1
967#define PCM2_FIX_VALUE_SEL_MASK_SFT (0x1 << 23)
968#define PCM2_BUFFER_LOOPBACK_SFT 22
969#define PCM2_BUFFER_LOOPBACK_MASK 0x1
970#define PCM2_BUFFER_LOOPBACK_MASK_SFT (0x1 << 22)
971#define PCM2_PARALLEL_LOOPBACK_SFT 21
972#define PCM2_PARALLEL_LOOPBACK_MASK 0x1
973#define PCM2_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 21)
974#define PCM2_SERIAL_LOOPBACK_SFT 20
975#define PCM2_SERIAL_LOOPBACK_MASK 0x1
976#define PCM2_SERIAL_LOOPBACK_MASK_SFT (0x1 << 20)
977#define PCM2_DAI_PCM_LOOPBACK_SFT 19
978#define PCM2_DAI_PCM_LOOPBACK_MASK 0x1
979#define PCM2_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 19)
980#define PCM2_I2S_PCM_LOOPBACK_SFT 18
981#define PCM2_I2S_PCM_LOOPBACK_MASK 0x1
982#define PCM2_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 18)
983#define PCM2_SYNC_DELSEL_SFT 17
984#define PCM2_SYNC_DELSEL_MASK 0x1
985#define PCM2_SYNC_DELSEL_MASK_SFT (0x1 << 17)
986#define PCM2_TX_LR_SWAP_SFT 16
987#define PCM2_TX_LR_SWAP_MASK 0x1
988#define PCM2_TX_LR_SWAP_MASK_SFT (0x1 << 16)
989#define PCM2_SYNC_IN_INV_SFT 15
990#define PCM2_SYNC_IN_INV_MASK 0x1
991#define PCM2_SYNC_IN_INV_MASK_SFT (0x1 << 15)
992#define PCM2_BCLK_IN_INV_SFT 14
993#define PCM2_BCLK_IN_INV_MASK 0x1
994#define PCM2_BCLK_IN_INV_MASK_SFT (0x1 << 14)
995#define PCM2_TX_LCH_RPT_SFT 13
996#define PCM2_TX_LCH_RPT_MASK 0x1
997#define PCM2_TX_LCH_RPT_MASK_SFT (0x1 << 13)
998#define PCM2_VBT_16K_MODE_SFT 12
999#define PCM2_VBT_16K_MODE_MASK 0x1
1000#define PCM2_VBT_16K_MODE_MASK_SFT (0x1 << 12)
1001#define PCM2_LOOPBACK_CH_SEL_SFT 10
1002#define PCM2_LOOPBACK_CH_SEL_MASK 0x3
1003#define PCM2_LOOPBACK_CH_SEL_MASK_SFT (0x3 << 10)
1004#define PCM2_TX2_BT_MODE_SFT 8
1005#define PCM2_TX2_BT_MODE_MASK 0x1
1006#define PCM2_TX2_BT_MODE_MASK_SFT (0x1 << 8)
1007#define PCM2_BT_MODE_SFT 7
1008#define PCM2_BT_MODE_MASK 0x1
1009#define PCM2_BT_MODE_MASK_SFT (0x1 << 7)
1010#define PCM2_AFIFO_SFT 6
1011#define PCM2_AFIFO_MASK 0x1
1012#define PCM2_AFIFO_MASK_SFT (0x1 << 6)
1013#define PCM2_WLEN_SFT 5
1014#define PCM2_WLEN_MASK 0x1
1015#define PCM2_WLEN_MASK_SFT (0x1 << 5)
1016#define PCM2_MODE_SFT 3
1017#define PCM2_MODE_MASK 0x3
1018#define PCM2_MODE_MASK_SFT (0x3 << 3)
1019#define PCM2_FMT_SFT 1
1020#define PCM2_FMT_MASK 0x3
1021#define PCM2_FMT_MASK_SFT (0x3 << 1)
1022#define PCM2_EN_SFT 0
1023#define PCM2_EN_MASK 0x1
1024#define PCM2_EN_MASK_SFT (0x1 << 0)
1025
1026/* AFE_ADDA_MTKAIF_CFG0 */
1027#define MTKAIF_RXIF_CLKINV_ADC_SFT 31
1028#define MTKAIF_RXIF_CLKINV_ADC_MASK 0x1
1029#define MTKAIF_RXIF_CLKINV_ADC_MASK_SFT (0x1 << 31)
1030#define MTKAIF_RXIF_BYPASS_SRC_SFT 17
1031#define MTKAIF_RXIF_BYPASS_SRC_MASK 0x1
1032#define MTKAIF_RXIF_BYPASS_SRC_MASK_SFT (0x1 << 17)
1033#define MTKAIF_RXIF_PROTOCOL2_SFT 16
1034#define MTKAIF_RXIF_PROTOCOL2_MASK 0x1
1035#define MTKAIF_RXIF_PROTOCOL2_MASK_SFT (0x1 << 16)
1036#define MTKAIF_TXIF_BYPASS_SRC_SFT 5
1037#define MTKAIF_TXIF_BYPASS_SRC_MASK 0x1
1038#define MTKAIF_TXIF_BYPASS_SRC_MASK_SFT (0x1 << 5)
1039#define MTKAIF_TXIF_PROTOCOL2_SFT 4
1040#define MTKAIF_TXIF_PROTOCOL2_MASK 0x1
1041#define MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4)
1042#define MTKAIF_TXIF_8TO5_SFT 2
1043#define MTKAIF_TXIF_8TO5_MASK 0x1
1044#define MTKAIF_TXIF_8TO5_MASK_SFT (0x1 << 2)
1045#define MTKAIF_RXIF_8TO5_SFT 1
1046#define MTKAIF_RXIF_8TO5_MASK 0x1
1047#define MTKAIF_RXIF_8TO5_MASK_SFT (0x1 << 1)
1048#define MTKAIF_IF_LOOPBACK1_SFT 0
1049#define MTKAIF_IF_LOOPBACK1_MASK 0x1
1050#define MTKAIF_IF_LOOPBACK1_MASK_SFT (0x1 << 0)
1051
1052/* AFE_ADDA_MTKAIF_RX_CFG2 */
1053#define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT 16
1054#define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK 0x1
1055#define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 16)
1056#define MTKAIF_RXIF_DELAY_CYCLE_SFT 12
1057#define MTKAIF_RXIF_DELAY_CYCLE_MASK 0xf
1058#define MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT (0xf << 12)
1059#define MTKAIF_RXIF_DELAY_DATA_SFT 8
1060#define MTKAIF_RXIF_DELAY_DATA_MASK 0x1
1061#define MTKAIF_RXIF_DELAY_DATA_MASK_SFT (0x1 << 8)
1062#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SFT 4
1063#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK 0x7
1064#define MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT (0x7 << 4)
1065
1066/* AFE_ADDA_DL_SRC2_CON0 */
1067#define DL_2_INPUT_MODE_CTL_SFT 28
1068#define DL_2_INPUT_MODE_CTL_MASK 0xf
1069#define DL_2_INPUT_MODE_CTL_MASK_SFT (0xf << 28)
1070#define DL_2_CH1_SATURATION_EN_CTL_SFT 27
1071#define DL_2_CH1_SATURATION_EN_CTL_MASK 0x1
1072#define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT (0x1 << 27)
1073#define DL_2_CH2_SATURATION_EN_CTL_SFT 26
1074#define DL_2_CH2_SATURATION_EN_CTL_MASK 0x1
1075#define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT (0x1 << 26)
1076#define DL_2_OUTPUT_SEL_CTL_SFT 24
1077#define DL_2_OUTPUT_SEL_CTL_MASK 0x3
1078#define DL_2_OUTPUT_SEL_CTL_MASK_SFT (0x3 << 24)
1079#define DL_2_FADEIN_0START_EN_SFT 16
1080#define DL_2_FADEIN_0START_EN_MASK 0x3
1081#define DL_2_FADEIN_0START_EN_MASK_SFT (0x3 << 16)
1082#define DL_DISABLE_HW_CG_CTL_SFT 15
1083#define DL_DISABLE_HW_CG_CTL_MASK 0x1
1084#define DL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 15)
1085#define C_DATA_EN_SEL_CTL_PRE_SFT 14
1086#define C_DATA_EN_SEL_CTL_PRE_MASK 0x1
1087#define C_DATA_EN_SEL_CTL_PRE_MASK_SFT (0x1 << 14)
1088#define DL_2_SIDE_TONE_ON_CTL_PRE_SFT 13
1089#define DL_2_SIDE_TONE_ON_CTL_PRE_MASK 0x1
1090#define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT (0x1 << 13)
1091#define DL_2_MUTE_CH1_OFF_CTL_PRE_SFT 12
1092#define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK 0x1
1093#define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT (0x1 << 12)
1094#define DL_2_MUTE_CH2_OFF_CTL_PRE_SFT 11
1095#define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK 0x1
1096#define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT (0x1 << 11)
1097#define DL2_ARAMPSP_CTL_PRE_SFT 9
1098#define DL2_ARAMPSP_CTL_PRE_MASK 0x3
1099#define DL2_ARAMPSP_CTL_PRE_MASK_SFT (0x3 << 9)
1100#define DL_2_IIRMODE_CTL_PRE_SFT 6
1101#define DL_2_IIRMODE_CTL_PRE_MASK 0x7
1102#define DL_2_IIRMODE_CTL_PRE_MASK_SFT (0x7 << 6)
1103#define DL_2_VOICE_MODE_CTL_PRE_SFT 5
1104#define DL_2_VOICE_MODE_CTL_PRE_MASK 0x1
1105#define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT (0x1 << 5)
1106#define D2_2_MUTE_CH1_ON_CTL_PRE_SFT 4
1107#define D2_2_MUTE_CH1_ON_CTL_PRE_MASK 0x1
1108#define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT (0x1 << 4)
1109#define D2_2_MUTE_CH2_ON_CTL_PRE_SFT 3
1110#define D2_2_MUTE_CH2_ON_CTL_PRE_MASK 0x1
1111#define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT (0x1 << 3)
1112#define DL_2_IIR_ON_CTL_PRE_SFT 2
1113#define DL_2_IIR_ON_CTL_PRE_MASK 0x1
1114#define DL_2_IIR_ON_CTL_PRE_MASK_SFT (0x1 << 2)
1115#define DL_2_GAIN_ON_CTL_PRE_SFT 1
1116#define DL_2_GAIN_ON_CTL_PRE_MASK 0x1
1117#define DL_2_GAIN_ON_CTL_PRE_MASK_SFT (0x1 << 1)
1118#define DL_2_SRC_ON_TMP_CTL_PRE_SFT 0
1119#define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1
1120#define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)
1121
1122/* AFE_ADDA_DL_SRC2_CON1 */
1123#define DL_2_GAIN_CTL_PRE_SFT 16
1124#define DL_2_GAIN_CTL_PRE_MASK 0xffff
1125#define DL_2_GAIN_CTL_PRE_MASK_SFT (0xffff << 16)
1126#define DL_2_GAIN_MODE_CTL_SFT 0
1127#define DL_2_GAIN_MODE_CTL_MASK 0x1
1128#define DL_2_GAIN_MODE_CTL_MASK_SFT (0x1 << 0)
1129
1130/* AFE_ADDA_UL_SRC_CON0 */
1131#define ULCF_CFG_EN_CTL_SFT 31
1132#define ULCF_CFG_EN_CTL_MASK 0x1
1133#define ULCF_CFG_EN_CTL_MASK_SFT (0x1 << 31)
1134#define UL_MODE_3P25M_CH2_CTL_SFT 22
1135#define UL_MODE_3P25M_CH2_CTL_MASK 0x1
1136#define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22)
1137#define UL_MODE_3P25M_CH1_CTL_SFT 21
1138#define UL_MODE_3P25M_CH1_CTL_MASK 0x1
1139#define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21)
1140#define UL_VOICE_MODE_CH1_CH2_CTL_SFT 17
1141#define UL_VOICE_MODE_CH1_CH2_CTL_MASK 0x7
1142#define UL_VOICE_MODE_CH1_CH2_CTL_MASK_SFT (0x7 << 17)
1143#define DMIC_LOW_POWER_MODE_CTL_SFT 14
1144#define DMIC_LOW_POWER_MODE_CTL_MASK 0x3
1145#define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
1146#define UL_DISABLE_HW_CG_CTL_SFT 12
1147#define UL_DISABLE_HW_CG_CTL_MASK 0x1
1148#define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12)
1149#define UL_IIR_ON_TMP_CTL_SFT 10
1150#define UL_IIR_ON_TMP_CTL_MASK 0x1
1151#define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10)
1152#define UL_IIRMODE_CTL_SFT 7
1153#define UL_IIRMODE_CTL_MASK 0x7
1154#define UL_IIRMODE_CTL_MASK_SFT (0x7 << 7)
1155#define DIGMIC_3P25M_1P625M_SEL_CTL_SFT 5
1156#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
1157#define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
1158#define UL_LOOP_BACK_MODE_CTL_SFT 2
1159#define UL_LOOP_BACK_MODE_CTL_MASK 0x1
1160#define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
1161#define UL_SDM_3_LEVEL_CTL_SFT 1
1162#define UL_SDM_3_LEVEL_CTL_MASK 0x1
1163#define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
1164#define UL_SRC_ON_TMP_CTL_SFT 0
1165#define UL_SRC_ON_TMP_CTL_MASK 0x1
1166#define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
1167
1168/* AFE_ADDA_UL_SRC_CON1 */
1169#define C_DAC_EN_CTL_SFT 27
1170#define C_DAC_EN_CTL_MASK 0x1
1171#define C_DAC_EN_CTL_MASK_SFT (0x1 << 27)
1172#define C_MUTE_SW_CTL_SFT 26
1173#define C_MUTE_SW_CTL_MASK 0x1
1174#define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26)
1175#define ASDM_SRC_SEL_CTL_SFT 25
1176#define ASDM_SRC_SEL_CTL_MASK 0x1
1177#define ASDM_SRC_SEL_CTL_MASK_SFT (0x1 << 25)
1178#define C_AMP_DIV_CH2_CTL_SFT 21
1179#define C_AMP_DIV_CH2_CTL_MASK 0x7
1180#define C_AMP_DIV_CH2_CTL_MASK_SFT (0x7 << 21)
1181#define C_FREQ_DIV_CH2_CTL_SFT 16
1182#define C_FREQ_DIV_CH2_CTL_MASK 0x1f
1183#define C_FREQ_DIV_CH2_CTL_MASK_SFT (0x1f << 16)
1184#define C_SINE_MODE_CH2_CTL_SFT 12
1185#define C_SINE_MODE_CH2_CTL_MASK 0xf
1186#define C_SINE_MODE_CH2_CTL_MASK_SFT (0xf << 12)
1187#define C_AMP_DIV_CH1_CTL_SFT 9
1188#define C_AMP_DIV_CH1_CTL_MASK 0x7
1189#define C_AMP_DIV_CH1_CTL_MASK_SFT (0x7 << 9)
1190#define C_FREQ_DIV_CH1_CTL_SFT 4
1191#define C_FREQ_DIV_CH1_CTL_MASK 0x1f
1192#define C_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 4)
1193#define C_SINE_MODE_CH1_CTL_SFT 0
1194#define C_SINE_MODE_CH1_CTL_MASK 0xf
1195#define C_SINE_MODE_CH1_CTL_MASK_SFT (0xf << 0)
1196
1197/* AFE_ADDA_TOP_CON0 */
1198#define C_LOOP_BACK_MODE_CTL_SFT 12
1199#define C_LOOP_BACK_MODE_CTL_MASK 0xf
1200#define C_LOOP_BACK_MODE_CTL_MASK_SFT (0xf << 12)
1201#define C_EXT_ADC_CTL_SFT 0
1202#define C_EXT_ADC_CTL_MASK 0x1
1203#define C_EXT_ADC_CTL_MASK_SFT (0x1 << 0)
1204
1205/* AFE_ADDA_UL_DL_CON0 */
1206#define AFE_ADDA6_UL_LR_SWAP_SFT 15
1207#define AFE_ADDA6_UL_LR_SWAP_MASK 0x1
1208#define AFE_ADDA6_UL_LR_SWAP_MASK_SFT (0x1 << 15)
1209#define AFE_ADDA6_CKDIV_RST_SFT 14
1210#define AFE_ADDA6_CKDIV_RST_MASK 0x1
1211#define AFE_ADDA6_CKDIV_RST_MASK_SFT (0x1 << 14)
1212#define AFE_ADDA6_FIFO_AUTO_RST_SFT 13
1213#define AFE_ADDA6_FIFO_AUTO_RST_MASK 0x1
1214#define AFE_ADDA6_FIFO_AUTO_RST_MASK_SFT (0x1 << 13)
1215#define UL_FIFO_DIGMIC_TESTIN_SFT 5
1216#define UL_FIFO_DIGMIC_TESTIN_MASK 0x3
1217#define UL_FIFO_DIGMIC_TESTIN_MASK_SFT (0x3 << 5)
1218#define UL_FIFO_DIGMIC_WDATA_TESTEN_SFT 4
1219#define UL_FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1
1220#define UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 4)
1221#define ADDA_AFE_ON_SFT 0
1222#define ADDA_AFE_ON_MASK 0x1
1223#define ADDA_AFE_ON_MASK_SFT (0x1 << 0)
1224
1225/* AFE_SIDETONE_CON0 */
1226#define R_RDY_SFT 30
1227#define R_RDY_MASK 0x1
1228#define R_RDY_MASK_SFT (0x1 << 30)
1229#define W_RDY_SFT 29
1230#define W_RDY_MASK 0x1
1231#define W_RDY_MASK_SFT (0x1 << 29)
1232#define R_W_EN_SFT 25
1233#define R_W_EN_MASK 0x1
1234#define R_W_EN_MASK_SFT (0x1 << 25)
1235#define R_W_SEL_SFT 24
1236#define R_W_SEL_MASK 0x1
1237#define R_W_SEL_MASK_SFT (0x1 << 24)
1238#define SEL_CH2_SFT 23
1239#define SEL_CH2_MASK 0x1
1240#define SEL_CH2_MASK_SFT (0x1 << 23)
1241#define SIDE_TONE_COEFFICIENT_ADDR_SFT 16
1242#define SIDE_TONE_COEFFICIENT_ADDR_MASK 0x1f
1243#define SIDE_TONE_COEFFICIENT_ADDR_MASK_SFT (0x1f << 16)
1244#define SIDE_TONE_COEFFICIENT_SFT 0
1245#define SIDE_TONE_COEFFICIENT_MASK 0xffff
1246#define SIDE_TONE_COEFFICIENT_MASK_SFT (0xffff << 0)
1247
1248/* AFE_SIDETONE_COEFF */
1249#define SIDE_TONE_COEFF_SFT 0
1250#define SIDE_TONE_COEFF_MASK 0xffff
1251#define SIDE_TONE_COEFF_MASK_SFT (0xffff << 0)
1252
1253/* AFE_SIDETONE_CON1 */
1254#define STF_BYPASS_MODE_SFT 31
1255#define STF_BYPASS_MODE_MASK 0x1
1256#define STF_BYPASS_MODE_MASK_SFT (0x1 << 31)
1257#define STF_BYPASS_MODE_O28_O29_SFT 30
1258#define STF_BYPASS_MODE_O28_O29_MASK 0x1
1259#define STF_BYPASS_MODE_O28_O29_MASK_SFT (0x1 << 30)
1260#define STF_BYPASS_MODE_I2S4_SFT 29
1261#define STF_BYPASS_MODE_I2S4_MASK 0x1
1262#define STF_BYPASS_MODE_I2S4_MASK_SFT (0x1 << 29)
1263#define STF_BYPASS_MODE_I2S5_SFT 28
1264#define STF_BYPASS_MODE_I2S5_MASK 0x1
1265#define STF_BYPASS_MODE_I2S5_MASK_SFT (0x1 << 28)
1266#define STF_INPUT_EN_SEL_SFT 13
1267#define STF_INPUT_EN_SEL_MASK 0x1
1268#define STF_INPUT_EN_SEL_MASK_SFT (0x1 << 13)
1269#define STF_SOURCE_FROM_O19O20_SFT 12
1270#define STF_SOURCE_FROM_O19O20_MASK 0x1
1271#define STF_SOURCE_FROM_O19O20_MASK_SFT (0x1 << 12)
1272#define SIDE_TONE_ON_SFT 8
1273#define SIDE_TONE_ON_MASK 0x1
1274#define SIDE_TONE_ON_MASK_SFT (0x1 << 8)
1275#define SIDE_TONE_HALF_TAP_NUM_SFT 0
1276#define SIDE_TONE_HALF_TAP_NUM_MASK 0x3f
1277#define SIDE_TONE_HALF_TAP_NUM_MASK_SFT (0x3f << 0)
1278
1279/* AFE_SIDETONE_GAIN */
1280#define POSITIVE_GAIN_SFT 16
1281#define POSITIVE_GAIN_MASK 0x7
1282#define POSITIVE_GAIN_MASK_SFT (0x7 << 16)
1283#define SIDE_TONE_GAIN_SFT 0
1284#define SIDE_TONE_GAIN_MASK 0xffff
1285#define SIDE_TONE_GAIN_MASK_SFT (0xffff << 0)
1286
1287/* AFE_ADDA_DL_SDM_DCCOMP_CON */
1288#define AUD_DC_COMP_EN_SFT 8
1289#define AUD_DC_COMP_EN_MASK 0x1
1290#define AUD_DC_COMP_EN_MASK_SFT (0x1 << 8)
1291#define ATTGAIN_CTL_SFT 0
1292#define ATTGAIN_CTL_MASK 0x3f
1293#define ATTGAIN_CTL_MASK_SFT (0x3f << 0)
1294
1295/* AFE_SINEGEN_CON0 */
1296#define DAC_EN_SFT 26
1297#define DAC_EN_MASK 0x1
1298#define DAC_EN_MASK_SFT (0x1 << 26)
1299#define MUTE_SW_CH2_SFT 25
1300#define MUTE_SW_CH2_MASK 0x1
1301#define MUTE_SW_CH2_MASK_SFT (0x1 << 25)
1302#define MUTE_SW_CH1_SFT 24
1303#define MUTE_SW_CH1_MASK 0x1
1304#define MUTE_SW_CH1_MASK_SFT (0x1 << 24)
1305#define SINE_MODE_CH2_SFT 20
1306#define SINE_MODE_CH2_MASK 0xf
1307#define SINE_MODE_CH2_MASK_SFT (0xf << 20)
1308#define AMP_DIV_CH2_SFT 17
1309#define AMP_DIV_CH2_MASK 0x7
1310#define AMP_DIV_CH2_MASK_SFT (0x7 << 17)
1311#define FREQ_DIV_CH2_SFT 12
1312#define FREQ_DIV_CH2_MASK 0x1f
1313#define FREQ_DIV_CH2_MASK_SFT (0x1f << 12)
1314#define SINE_MODE_CH1_SFT 8
1315#define SINE_MODE_CH1_MASK 0xf
1316#define SINE_MODE_CH1_MASK_SFT (0xf << 8)
1317#define AMP_DIV_CH1_SFT 5
1318#define AMP_DIV_CH1_MASK 0x7
1319#define AMP_DIV_CH1_MASK_SFT (0x7 << 5)
1320#define FREQ_DIV_CH1_SFT 0
1321#define FREQ_DIV_CH1_MASK 0x1f
1322#define FREQ_DIV_CH1_MASK_SFT (0x1f << 0)
1323
1324/* AFE_SINEGEN_CON2 */
1325#define INNER_LOOP_BACK_MODE_SFT 0
1326#define INNER_LOOP_BACK_MODE_MASK 0x3f
1327#define INNER_LOOP_BACK_MODE_MASK_SFT (0x3f << 0)
1328
1329/* AFE_MEMIF_MINLEN */
1330#define HDMI_MINLEN_SFT 24
1331#define HDMI_MINLEN_MASK 0xf
1332#define HDMI_MINLEN_MASK_SFT (0xf << 24)
1333#define DL3_MINLEN_SFT 12
1334#define DL3_MINLEN_MASK 0xf
1335#define DL3_MINLEN_MASK_SFT (0xf << 12)
1336#define DL2_MINLEN_SFT 8
1337#define DL2_MINLEN_MASK 0xf
1338#define DL2_MINLEN_MASK_SFT (0xf << 8)
1339#define DL1_DATA2_MINLEN_SFT 4
1340#define DL1_DATA2_MINLEN_MASK 0xf
1341#define DL1_DATA2_MINLEN_MASK_SFT (0xf << 4)
1342#define DL1_MINLEN_SFT 0
1343#define DL1_MINLEN_MASK 0xf
1344#define DL1_MINLEN_MASK_SFT (0xf << 0)
1345
1346/* AFE_MEMIF_MAXLEN */
1347#define HDMI_MAXLEN_SFT 24
1348#define HDMI_MAXLEN_MASK 0xf
1349#define HDMI_MAXLEN_MASK_SFT (0xf << 24)
1350#define DL3_MAXLEN_SFT 8
1351#define DL3_MAXLEN_MASK 0xf
1352#define DL3_MAXLEN_MASK_SFT (0xf << 8)
1353#define DL2_MAXLEN_SFT 4
1354#define DL2_MAXLEN_MASK 0xf
1355#define DL2_MAXLEN_MASK_SFT (0xf << 4)
1356#define DL1_MAXLEN_SFT 0
1357#define DL1_MAXLEN_MASK 0x3
1358#define DL1_MAXLEN_MASK_SFT (0x3 << 0)
1359
1360/* AFE_MEMIF_PBUF_SIZE */
1361#define VUL12_4CH_SFT 17
1362#define VUL12_4CH_MASK 0x1
1363#define VUL12_4CH_MASK_SFT (0x1 << 17)
1364#define DL3_PBUF_SIZE_SFT 10
1365#define DL3_PBUF_SIZE_MASK 0x3
1366#define DL3_PBUF_SIZE_MASK_SFT (0x3 << 10)
1367#define HDMI_PBUF_SIZE_SFT 4
1368#define HDMI_PBUF_SIZE_MASK 0x3
1369#define HDMI_PBUF_SIZE_MASK_SFT (0x3 << 4)
1370#define DL2_PBUF_SIZE_SFT 2
1371#define DL2_PBUF_SIZE_MASK 0x3
1372#define DL2_PBUF_SIZE_MASK_SFT (0x3 << 2)
1373#define DL1_PBUF_SIZE_SFT 0
1374#define DL1_PBUF_SIZE_MASK 0x3
1375#define DL1_PBUF_SIZE_MASK_SFT (0x3 << 0)
1376
1377/* AFE_HD_ENGEN_ENABLE */
1378#define AFE_24M_ON_SFT 1
1379#define AFE_24M_ON_MASK 0x1
1380#define AFE_24M_ON_MASK_SFT (0x1 << 1)
1381#define AFE_22M_ON_SFT 0
1382#define AFE_22M_ON_MASK 0x1
1383#define AFE_22M_ON_MASK_SFT (0x1 << 0)
1384
1385/* AFE_IRQ_MCU_CON0 */
1386#define IRQ12_MCU_ON_SFT 12
1387#define IRQ12_MCU_ON_MASK 0x1
1388#define IRQ12_MCU_ON_MASK_SFT (0x1 << 12)
1389#define IRQ11_MCU_ON_SFT 11
1390#define IRQ11_MCU_ON_MASK 0x1
1391#define IRQ11_MCU_ON_MASK_SFT (0x1 << 11)
1392#define IRQ10_MCU_ON_SFT 10
1393#define IRQ10_MCU_ON_MASK 0x1
1394#define IRQ10_MCU_ON_MASK_SFT (0x1 << 10)
1395#define IRQ9_MCU_ON_SFT 9
1396#define IRQ9_MCU_ON_MASK 0x1
1397#define IRQ9_MCU_ON_MASK_SFT (0x1 << 9)
1398#define IRQ8_MCU_ON_SFT 8
1399#define IRQ8_MCU_ON_MASK 0x1
1400#define IRQ8_MCU_ON_MASK_SFT (0x1 << 8)
1401#define IRQ7_MCU_ON_SFT 7
1402#define IRQ7_MCU_ON_MASK 0x1
1403#define IRQ7_MCU_ON_MASK_SFT (0x1 << 7)
1404#define IRQ6_MCU_ON_SFT 6
1405#define IRQ6_MCU_ON_MASK 0x1
1406#define IRQ6_MCU_ON_MASK_SFT (0x1 << 6)
1407#define IRQ5_MCU_ON_SFT 5
1408#define IRQ5_MCU_ON_MASK 0x1
1409#define IRQ5_MCU_ON_MASK_SFT (0x1 << 5)
1410#define IRQ4_MCU_ON_SFT 4
1411#define IRQ4_MCU_ON_MASK 0x1
1412#define IRQ4_MCU_ON_MASK_SFT (0x1 << 4)
1413#define IRQ3_MCU_ON_SFT 3
1414#define IRQ3_MCU_ON_MASK 0x1
1415#define IRQ3_MCU_ON_MASK_SFT (0x1 << 3)
1416#define IRQ2_MCU_ON_SFT 2
1417#define IRQ2_MCU_ON_MASK 0x1
1418#define IRQ2_MCU_ON_MASK_SFT (0x1 << 2)
1419#define IRQ1_MCU_ON_SFT 1
1420#define IRQ1_MCU_ON_MASK 0x1
1421#define IRQ1_MCU_ON_MASK_SFT (0x1 << 1)
1422#define IRQ0_MCU_ON_SFT 0
1423#define IRQ0_MCU_ON_MASK 0x1
1424#define IRQ0_MCU_ON_MASK_SFT (0x1 << 0)
1425
1426/* AFE_IRQ_MCU_CON1 */
1427#define IRQ7_MCU_MODE_SFT 28
1428#define IRQ7_MCU_MODE_MASK 0xf
1429#define IRQ7_MCU_MODE_MASK_SFT (0xf << 28)
1430#define IRQ6_MCU_MODE_SFT 24
1431#define IRQ6_MCU_MODE_MASK 0xf
1432#define IRQ6_MCU_MODE_MASK_SFT (0xf << 24)
1433#define IRQ5_MCU_MODE_SFT 20
1434#define IRQ5_MCU_MODE_MASK 0xf
1435#define IRQ5_MCU_MODE_MASK_SFT (0xf << 20)
1436#define IRQ4_MCU_MODE_SFT 16
1437#define IRQ4_MCU_MODE_MASK 0xf
1438#define IRQ4_MCU_MODE_MASK_SFT (0xf << 16)
1439#define IRQ3_MCU_MODE_SFT 12
1440#define IRQ3_MCU_MODE_MASK 0xf
1441#define IRQ3_MCU_MODE_MASK_SFT (0xf << 12)
1442#define IRQ2_MCU_MODE_SFT 8
1443#define IRQ2_MCU_MODE_MASK 0xf
1444#define IRQ2_MCU_MODE_MASK_SFT (0xf << 8)
1445#define IRQ1_MCU_MODE_SFT 4
1446#define IRQ1_MCU_MODE_MASK 0xf
1447#define IRQ1_MCU_MODE_MASK_SFT (0xf << 4)
1448#define IRQ0_MCU_MODE_SFT 0
1449#define IRQ0_MCU_MODE_MASK 0xf
1450#define IRQ0_MCU_MODE_MASK_SFT (0xf << 0)
1451
1452/* AFE_IRQ_MCU_CON2 */
1453#define IRQ12_MCU_MODE_SFT 4
1454#define IRQ12_MCU_MODE_MASK 0xf
1455#define IRQ12_MCU_MODE_MASK_SFT (0xf << 4)
1456#define IRQ11_MCU_MODE_SFT 0
1457#define IRQ11_MCU_MODE_MASK 0xf
1458#define IRQ11_MCU_MODE_MASK_SFT (0xf << 0)
1459
1460/* AFE_IRQ_MCU_CLR */
1461#define IRQ12_MCU_MISS_CNT_CLR_SFT 28
1462#define IRQ12_MCU_MISS_CNT_CLR_MASK 0x1
1463#define IRQ12_MCU_MISS_CNT_CLR_MASK_SFT (0x1 << 28)
1464#define IRQ11_MCU_MISS_CNT_CLR_SFT 27
1465#define IRQ11_MCU_MISS_CNT_CLR_MASK 0x1
1466#define IRQ11_MCU_MISS_CNT_CLR_MASK_SFT (0x1 << 27)
1467#define IRQ10_MCU_MISS_CLR_SFT 26
1468#define IRQ10_MCU_MISS_CLR_MASK 0x1
1469#define IRQ10_MCU_MISS_CLR_MASK_SFT (0x1 << 26)
1470#define IRQ9_MCU_MISS_CLR_SFT 25
1471#define IRQ9_MCU_MISS_CLR_MASK 0x1
1472#define IRQ9_MCU_MISS_CLR_MASK_SFT (0x1 << 25)
1473#define IRQ8_MCU_MISS_CLR_SFT 24
1474#define IRQ8_MCU_MISS_CLR_MASK 0x1
1475#define IRQ8_MCU_MISS_CLR_MASK_SFT (0x1 << 24)
1476#define IRQ7_MCU_MISS_CLR_SFT 23
1477#define IRQ7_MCU_MISS_CLR_MASK 0x1
1478#define IRQ7_MCU_MISS_CLR_MASK_SFT (0x1 << 23)
1479#define IRQ6_MCU_MISS_CLR_SFT 22
1480#define IRQ6_MCU_MISS_CLR_MASK 0x1
1481#define IRQ6_MCU_MISS_CLR_MASK_SFT (0x1 << 22)
1482#define IRQ5_MCU_MISS_CLR_SFT 21
1483#define IRQ5_MCU_MISS_CLR_MASK 0x1
1484#define IRQ5_MCU_MISS_CLR_MASK_SFT (0x1 << 21)
1485#define IRQ4_MCU_MISS_CLR_SFT 20
1486#define IRQ4_MCU_MISS_CLR_MASK 0x1
1487#define IRQ4_MCU_MISS_CLR_MASK_SFT (0x1 << 20)
1488#define IRQ3_MCU_MISS_CLR_SFT 19
1489#define IRQ3_MCU_MISS_CLR_MASK 0x1
1490#define IRQ3_MCU_MISS_CLR_MASK_SFT (0x1 << 19)
1491#define IRQ2_MCU_MISS_CLR_SFT 18
1492#define IRQ2_MCU_MISS_CLR_MASK 0x1
1493#define IRQ2_MCU_MISS_CLR_MASK_SFT (0x1 << 18)
1494#define IRQ1_MCU_MISS_CLR_SFT 17
1495#define IRQ1_MCU_MISS_CLR_MASK 0x1
1496#define IRQ1_MCU_MISS_CLR_MASK_SFT (0x1 << 17)
1497#define IRQ0_MCU_MISS_CLR_SFT 16
1498#define IRQ0_MCU_MISS_CLR_MASK 0x1
1499#define IRQ0_MCU_MISS_CLR_MASK_SFT (0x1 << 16)
1500#define IRQ12_MCU_CLR_SFT 12
1501#define IRQ12_MCU_CLR_MASK 0x1
1502#define IRQ12_MCU_CLR_MASK_SFT (0x1 << 12)
1503#define IRQ11_MCU_CLR_SFT 11
1504#define IRQ11_MCU_CLR_MASK 0x1
1505#define IRQ11_MCU_CLR_MASK_SFT (0x1 << 11)
1506#define IRQ10_MCU_CLR_SFT 10
1507#define IRQ10_MCU_CLR_MASK 0x1
1508#define IRQ10_MCU_CLR_MASK_SFT (0x1 << 10)
1509#define IRQ9_MCU_CLR_SFT 9
1510#define IRQ9_MCU_CLR_MASK 0x1
1511#define IRQ9_MCU_CLR_MASK_SFT (0x1 << 9)
1512#define IRQ8_MCU_CLR_SFT 8
1513#define IRQ8_MCU_CLR_MASK 0x1
1514#define IRQ8_MCU_CLR_MASK_SFT (0x1 << 8)
1515#define IRQ7_MCU_CLR_SFT 7
1516#define IRQ7_MCU_CLR_MASK 0x1
1517#define IRQ7_MCU_CLR_MASK_SFT (0x1 << 7)
1518#define IRQ6_MCU_CLR_SFT 6
1519#define IRQ6_MCU_CLR_MASK 0x1
1520#define IRQ6_MCU_CLR_MASK_SFT (0x1 << 6)
1521#define IRQ5_MCU_CLR_SFT 5
1522#define IRQ5_MCU_CLR_MASK 0x1
1523#define IRQ5_MCU_CLR_MASK_SFT (0x1 << 5)
1524#define IRQ4_MCU_CLR_SFT 4
1525#define IRQ4_MCU_CLR_MASK 0x1
1526#define IRQ4_MCU_CLR_MASK_SFT (0x1 << 4)
1527#define IRQ3_MCU_CLR_SFT 3
1528#define IRQ3_MCU_CLR_MASK 0x1
1529#define IRQ3_MCU_CLR_MASK_SFT (0x1 << 3)
1530#define IRQ2_MCU_CLR_SFT 2
1531#define IRQ2_MCU_CLR_MASK 0x1
1532#define IRQ2_MCU_CLR_MASK_SFT (0x1 << 2)
1533#define IRQ1_MCU_CLR_SFT 1
1534#define IRQ1_MCU_CLR_MASK 0x1
1535#define IRQ1_MCU_CLR_MASK_SFT (0x1 << 1)
1536#define IRQ0_MCU_CLR_SFT 0
1537#define IRQ0_MCU_CLR_MASK 0x1
1538#define IRQ0_MCU_CLR_MASK_SFT (0x1 << 0)
1539
1540/* AFE_MEMIF_MSB */
1541#define CPU_COMPACT_MODE_SFT 29
1542#define CPU_COMPACT_MODE_MASK 0x1
1543#define CPU_COMPACT_MODE_MASK_SFT (0x1 << 29)
1544#define CPU_HD_ALIGN_SFT 28
1545#define CPU_HD_ALIGN_MASK 0x1
1546#define CPU_HD_ALIGN_MASK_SFT (0x1 << 28)
1547#define AWB2_AXI_WR_SIGN_SFT 24
1548#define AWB2_AXI_WR_SIGN_MASK 0x1
1549#define AWB2_AXI_WR_SIGN_MASK_SFT (0x1 << 24)
1550#define VUL2_AXI_WR_SIGN_SFT 22
1551#define VUL2_AXI_WR_SIGN_MASK 0x1
1552#define VUL2_AXI_WR_SIGN_MASK_SFT (0x1 << 22)
1553#define VUL12_AXI_WR_SIGN_SFT 21
1554#define VUL12_AXI_WR_SIGN_MASK 0x1
1555#define VUL12_AXI_WR_SIGN_MASK_SFT (0x1 << 21)
1556#define VUL_AXI_WR_SIGN_SFT 20
1557#define VUL_AXI_WR_SIGN_MASK 0x1
1558#define VUL_AXI_WR_SIGN_MASK_SFT (0x1 << 20)
1559#define MOD_DAI_AXI_WR_SIGN_SFT 18
1560#define MOD_DAI_AXI_WR_SIGN_MASK 0x1
1561#define MOD_DAI_AXI_WR_SIGN_MASK_SFT (0x1 << 18)
1562#define AWB_MSTR_SIGN_SFT 17
1563#define AWB_MSTR_SIGN_MASK 0x1
1564#define AWB_MSTR_SIGN_MASK_SFT (0x1 << 17)
1565#define SYSRAM_SIGN_SFT 16
1566#define SYSRAM_SIGN_MASK 0x1
1567#define SYSRAM_SIGN_MASK_SFT (0x1 << 16)
1568
1569/* AFE_HDMI_CONN0 */
1570#define HDMI_O_7_SFT 21
1571#define HDMI_O_7_MASK 0x7
1572#define HDMI_O_7_MASK_SFT (0x7 << 21)
1573#define HDMI_O_6_SFT 18
1574#define HDMI_O_6_MASK 0x7
1575#define HDMI_O_6_MASK_SFT (0x7 << 18)
1576#define HDMI_O_5_SFT 15
1577#define HDMI_O_5_MASK 0x7
1578#define HDMI_O_5_MASK_SFT (0x7 << 15)
1579#define HDMI_O_4_SFT 12
1580#define HDMI_O_4_MASK 0x7
1581#define HDMI_O_4_MASK_SFT (0x7 << 12)
1582#define HDMI_O_3_SFT 9
1583#define HDMI_O_3_MASK 0x7
1584#define HDMI_O_3_MASK_SFT (0x7 << 9)
1585#define HDMI_O_2_SFT 6
1586#define HDMI_O_2_MASK 0x7
1587#define HDMI_O_2_MASK_SFT (0x7 << 6)
1588#define HDMI_O_1_SFT 3
1589#define HDMI_O_1_MASK 0x7
1590#define HDMI_O_1_MASK_SFT (0x7 << 3)
1591#define HDMI_O_0_SFT 0
1592#define HDMI_O_0_MASK 0x7
1593#define HDMI_O_0_MASK_SFT (0x7 << 0)
1594
1595/* AFE_TDM_CON1 */
1596#define TDM_EN_SFT 0
1597#define TDM_EN_MASK 0x1
1598#define TDM_EN_MASK_SFT (0x1 << 0)
1599#define BCK_INVERSE_SFT 1
1600#define BCK_INVERSE_MASK 0x1
1601#define BCK_INVERSE_MASK_SFT (0x1 << 1)
1602#define LRCK_INVERSE_SFT 2
1603#define LRCK_INVERSE_MASK 0x1
1604#define LRCK_INVERSE_MASK_SFT (0x1 << 2)
1605#define DELAY_DATA_SFT 3
1606#define DELAY_DATA_MASK 0x1
1607#define DELAY_DATA_MASK_SFT (0x1 << 3)
1608#define LEFT_ALIGN_SFT 4
1609#define LEFT_ALIGN_MASK 0x1
1610#define LEFT_ALIGN_MASK_SFT (0x1 << 4)
1611#define WLEN_SFT 8
1612#define WLEN_MASK 0x3
1613#define WLEN_MASK_SFT (0x3 << 8)
1614#define CHANNEL_NUM_SFT 10
1615#define CHANNEL_NUM_MASK 0x3
1616#define CHANNEL_NUM_MASK_SFT (0x3 << 10)
1617#define CHANNEL_BCK_CYCLES_SFT 12
1618#define CHANNEL_BCK_CYCLES_MASK 0x3
1619#define CHANNEL_BCK_CYCLES_MASK_SFT (0x3 << 12)
1620#define DAC_BIT_NUM_SFT 16
1621#define DAC_BIT_NUM_MASK 0x1f
1622#define DAC_BIT_NUM_MASK_SFT (0x1f << 16)
1623#define LRCK_TDM_WIDTH_SFT 24
1624#define LRCK_TDM_WIDTH_MASK 0xff
1625#define LRCK_TDM_WIDTH_MASK_SFT (0xff << 24)
1626
1627/* AFE_TDM_CON2 */
1628#define ST_CH_PAIR_SOUT0_SFT 0
1629#define ST_CH_PAIR_SOUT0_MASK 0x7
1630#define ST_CH_PAIR_SOUT0_MASK_SFT (0x7 << 0)
1631#define ST_CH_PAIR_SOUT1_SFT 4
1632#define ST_CH_PAIR_SOUT1_MASK 0x7
1633#define ST_CH_PAIR_SOUT1_MASK_SFT (0x7 << 4)
1634#define ST_CH_PAIR_SOUT2_SFT 8
1635#define ST_CH_PAIR_SOUT2_MASK 0x7
1636#define ST_CH_PAIR_SOUT2_MASK_SFT (0x7 << 8)
1637#define ST_CH_PAIR_SOUT3_SFT 12
1638#define ST_CH_PAIR_SOUT3_MASK 0x7
1639#define ST_CH_PAIR_SOUT3_MASK_SFT (0x7 << 12)
1640#define TDM_FIX_VALUE_SEL_SFT 16
1641#define TDM_FIX_VALUE_SEL_MASK 0x1
1642#define TDM_FIX_VALUE_SEL_MASK_SFT (0x1 << 16)
1643#define TDM_I2S_LOOPBACK_SFT 20
1644#define TDM_I2S_LOOPBACK_MASK 0x1
1645#define TDM_I2S_LOOPBACK_MASK_SFT (0x1 << 20)
1646#define TDM_I2S_LOOPBACK_CH_SFT 21
1647#define TDM_I2S_LOOPBACK_CH_MASK 0x3
1648#define TDM_I2S_LOOPBACK_CH_MASK_SFT (0x3 << 21)
1649#define TDM_FIX_VALUE_SFT 24
1650#define TDM_FIX_VALUE_MASK 0xff
1651#define TDM_FIX_VALUE_MASK_SFT (0xff << 24)
1652
1653/* AFE_HDMI_OUT_CON0 */
1654#define AFE_HDMI_OUT_ON_RETM_SFT 8
1655#define AFE_HDMI_OUT_ON_RETM_MASK 0x1
1656#define AFE_HDMI_OUT_ON_RETM_MASK_SFT (0x1 << 8)
1657#define AFE_HDMI_OUT_CH_NUM_SFT 4
1658#define AFE_HDMI_OUT_CH_NUM_MASK 0xf
1659#define AFE_HDMI_OUT_CH_NUM_MASK_SFT (0xf << 4)
1660#define AFE_HDMI_OUT_BIT_WIDTH_SFT 1
1661#define AFE_HDMI_OUT_BIT_WIDTH_MASK 0x1
1662#define AFE_HDMI_OUT_BIT_WIDTH_MASK_SFT (0x1 << 1)
1663#define AFE_HDMI_OUT_ON_SFT 0
1664#define AFE_HDMI_OUT_ON_MASK 0x1
1665#define AFE_HDMI_OUT_ON_MASK_SFT (0x1 << 0)
1666#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-17 02:15:54 -0400