7 files changed, 88 insertions, 224 deletions

diff --git a/include/linux/memremap.h b/include/linux/memremap.h
index f8a5b2a19945..b459518ce475 100644
--- a/include/linux/memremap.h
+++ b/include/linux/memremap.h
@@ -112,7 +112,6 @@ struct dev_pagemap {
         struct device *dev;
         enum memory_type type;
         unsigned int flags;
-        u64 pci_p2pdma_bus_offset;
         const struct dev_pagemap_ops *ops;
 };
 
diff --git a/include/linux/pci-aspm.h b/include/linux/pci-aspm.h
deleted file mode 100644
index 67064145d76e..000000000000
--- a/include/linux/pci-aspm.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- *      aspm.h
- *
- *      PCI Express ASPM defines and function prototypes
- *
- *      Copyright (C) 2007 Intel Corp.
- *              Zhang Yanmin (yanmin.zhang@intel.com)
- *              Shaohua Li (shaohua.li@intel.com)
- *
- *      For more information, please consult the following manuals (look at
- *      http://www.pcisig.com/ for how to get them):
- *
- *      PCI Express Specification
- */
-
-#ifndef LINUX_ASPM_H
-#define LINUX_ASPM_H
-
-#include <linux/pci.h>
-
-#define PCIE_LINK_STATE_L0S     1
-#define PCIE_LINK_STATE_L1      2
-#define PCIE_LINK_STATE_CLKPM   4
-
-#ifdef CONFIG_PCIEASPM
-int pci_disable_link_state(struct pci_dev *pdev, int state);
-int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
-void pcie_no_aspm(void);
-#else
-static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
-{ return 0; }
-static inline void pcie_no_aspm(void) { }
-#endif
-
-#endif /* LINUX_ASPM_H */
diff --git a/include/linux/pci-p2pdma.h b/include/linux/pci-p2pdma.h
index bca9bc3e5be7..8318a97c9c61 100644
--- a/include/linux/pci-p2pdma.h
+++ b/include/linux/pci-p2pdma.h
@@ -30,8 +30,10 @@ struct scatterlist *pci_p2pmem_alloc_sgl(struct pci_dev *pdev,
                                          unsigned int *nents, u32 length);
 void pci_p2pmem_free_sgl(struct pci_dev *pdev, struct scatterlist *sgl);
 void pci_p2pmem_publish(struct pci_dev *pdev, bool publish);
-int pci_p2pdma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-                      enum dma_data_direction dir);
+int pci_p2pdma_map_sg_attrs(struct device *dev, struct scatterlist *sg,
+                int nents, enum dma_data_direction dir, unsigned long attrs);
+void pci_p2pdma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg,
+                int nents, enum dma_data_direction dir, unsigned long attrs);
 int pci_p2pdma_enable_store(const char *page, struct pci_dev **p2p_dev,
                             bool *use_p2pdma);
 ssize_t pci_p2pdma_enable_show(char *page, struct pci_dev *p2p_dev,
@@ -81,11 +83,17 @@ static inline void pci_p2pmem_free_sgl(struct pci_dev *pdev,
 static inline void pci_p2pmem_publish(struct pci_dev *pdev, bool publish)
 {
 }
-static inline int pci_p2pdma_map_sg(struct device *dev,
-                struct scatterlist *sg, int nents, enum dma_data_direction dir)
+static inline int pci_p2pdma_map_sg_attrs(struct device *dev,
+                struct scatterlist *sg, int nents, enum dma_data_direction dir,
+                unsigned long attrs)
 {
         return 0;
 }
+static inline void pci_p2pdma_unmap_sg_attrs(struct device *dev,
+                struct scatterlist *sg, int nents, enum dma_data_direction dir,
+                unsigned long attrs)
+{
+}
 static inline int pci_p2pdma_enable_store(const char *page,
                 struct pci_dev **p2p_dev, bool *use_p2pdma)
 {
@@ -111,4 +119,16 @@ static inline struct pci_dev *pci_p2pmem_find(struct device *client)
         return pci_p2pmem_find_many(&client, 1);
 }
 
+static inline int pci_p2pdma_map_sg(struct device *dev, struct scatterlist *sg,
+                                    int nents, enum dma_data_direction dir)
+{
+        return pci_p2pdma_map_sg_attrs(dev, sg, nents, dir, 0);
+}
+
+static inline void pci_p2pdma_unmap_sg(struct device *dev,
+                struct scatterlist *sg, int nents, enum dma_data_direction dir)
+{
+        pci_p2pdma_unmap_sg_attrs(dev, sg, nents, dir, 0);
+}
+
 #endif /* _LINUX_PCI_P2P_H */
diff --git a/include/linux/pci.h b/include/linux/pci.h
index c133579c01fa..deecf3cc17b1 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -6,12 +6,18 @@
  *      Copyright 1994, Drew Eckhardt
  *      Copyright 1997--1999 Martin Mares <mj@ucw.cz>
  *
+ *      PCI Express ASPM defines and function prototypes
+ *      Copyright (c) 2007 Intel Corp.
+ *              Zhang Yanmin (yanmin.zhang@intel.com)
+ *              Shaohua Li (shaohua.li@intel.com)
+ *
  *      For more information, please consult the following manuals (look at
  *      http://www.pcisig.com/ for how to get them):
  *
  *      PCI BIOS Specification
  *      PCI Local Bus Specification
  *      PCI to PCI Bridge Specification
+ *      PCI Express Specification
  *      PCI System Design Guide
  */
 #ifndef LINUX_PCI_H
@@ -145,11 +151,6 @@ static inline const char *pci_power_name(pci_power_t state)
         return pci_power_names[1 + (__force int) state];
 }
 
-#define PCI_PM_D2_DELAY         200
-#define PCI_PM_D3_WAIT          10
-#define PCI_PM_D3COLD_WAIT      100
-#define PCI_PM_BUS_WAIT         50
-
 /**
  * typedef pci_channel_state_t
  *
@@ -418,7 +419,6 @@ struct pci_dev {
         unsigned int    broken_intx_masking:1;  /* INTx masking can't be used */
         unsigned int    io_window_1k:1;         /* Intel bridge 1K I/O windows */
         unsigned int    irq_managed:1;
-        unsigned int    has_secondary_link:1;
         unsigned int    non_compliant_bars:1;   /* Broken BARs; ignore them */
         unsigned int    is_probed:1;            /* Device probing in progress */
         unsigned int    link_active_reporting:1;/* Device capable of reporting link active */
@@ -649,9 +649,6 @@ static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
         return dev->bus->self;
 }
 
-struct device *pci_get_host_bridge_device(struct pci_dev *dev);
-void pci_put_host_bridge_device(struct device *dev);
-
 #ifdef CONFIG_PCI_MSI
 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
 {
@@ -925,6 +922,11 @@ enum {
         PCI_SCAN_ALL_PCIE_DEVS  = 0x00000040,   /* Scan all, not just dev 0 */
 };
 
+#define PCI_IRQ_LEGACY          (1 << 0) /* Allow legacy interrupts */
+#define PCI_IRQ_MSI             (1 << 1) /* Allow MSI interrupts */
+#define PCI_IRQ_MSIX            (1 << 2) /* Allow MSI-X interrupts */
+#define PCI_IRQ_AFFINITY        (1 << 3) /* Auto-assign affinity */
+
 /* These external functions are only available when PCI support is enabled */
 #ifdef CONFIG_PCI
 
@@ -995,7 +997,6 @@ struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
                                 int busnr);
-void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
                                  const char *name,
                                  struct hotplug_slot *hotplug);
@@ -1241,19 +1242,12 @@ int pci_wake_from_d3(struct pci_dev *dev, bool enable);
 int pci_prepare_to_sleep(struct pci_dev *dev);
 int pci_back_from_sleep(struct pci_dev *dev);
 bool pci_dev_run_wake(struct pci_dev *dev);
-bool pci_check_pme_status(struct pci_dev *dev);
-void pci_pme_wakeup_bus(struct pci_bus *bus);
 void pci_d3cold_enable(struct pci_dev *dev);
 void pci_d3cold_disable(struct pci_dev *dev);
 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
 void pci_wakeup_bus(struct pci_bus *bus);
 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
 
-/* PCI Virtual Channel */
-int pci_save_vc_state(struct pci_dev *dev);
-void pci_restore_vc_state(struct pci_dev *dev);
-void pci_allocate_vc_save_buffers(struct pci_dev *dev);
-
 /* For use by arch with custom probe code */
 void set_pcie_port_type(struct pci_dev *pdev);
 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
@@ -1297,8 +1291,6 @@ int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
 void pci_release_selected_regions(struct pci_dev *, int);
 
 /* drivers/pci/bus.c */
-struct pci_bus *pci_bus_get(struct pci_bus *bus);
-void pci_bus_put(struct pci_bus *bus);
 void pci_add_resource(struct list_head *resources, struct resource *res);
 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
                              resource_size_t offset);
@@ -1408,11 +1400,6 @@ resource_size_t pcibios_window_alignment(struct pci_bus *bus,
 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
                       unsigned int command_bits, u32 flags);
 
-#define PCI_IRQ_LEGACY          (1 << 0) /* Allow legacy interrupts */
-#define PCI_IRQ_MSI             (1 << 1) /* Allow MSI interrupts */
-#define PCI_IRQ_MSIX            (1 << 2) /* Allow MSI-X interrupts */
-#define PCI_IRQ_AFFINITY        (1 << 3) /* Auto-assign affinity */
-
 /*
  * Virtual interrupts allow for more interrupts to be allocated
  * than the device has interrupts for. These are not programmed
@@ -1517,14 +1504,6 @@ static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
 }
 #endif
 
-static inline int
-pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
-                      unsigned int max_vecs, unsigned int flags)
-{
-        return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
-                                              NULL);
-}
-
 /**
  * pci_irqd_intx_xlate() - Translate PCI INTx value to an IRQ domain hwirq
  * @d: the INTx IRQ domain
@@ -1565,9 +1544,21 @@ extern bool pcie_ports_native;
 #define pcie_ports_native       false
 #endif
 
+#define PCIE_LINK_STATE_L0S     1
+#define PCIE_LINK_STATE_L1      2
+#define PCIE_LINK_STATE_CLKPM   4
+
 #ifdef CONFIG_PCIEASPM
+int pci_disable_link_state(struct pci_dev *pdev, int state);
+int pci_disable_link_state_locked(struct pci_dev *pdev, int state);
+void pcie_no_aspm(void);
 bool pcie_aspm_support_enabled(void);
 #else
+static inline int pci_disable_link_state(struct pci_dev *pdev, int state)
+{ return 0; }
+static inline int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
+{ return 0; }
+static inline void pcie_no_aspm(void) { }
 static inline bool pcie_aspm_support_enabled(void) { return false; }
 #endif
 
@@ -1577,23 +1568,8 @@ bool pci_aer_available(void);
 static inline bool pci_aer_available(void) { return false; }
 #endif
 
-#ifdef CONFIG_PCIE_ECRC
-void pcie_set_ecrc_checking(struct pci_dev *dev);
-void pcie_ecrc_get_policy(char *str);
-#else
-static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
-static inline void pcie_ecrc_get_policy(char *str) { }
-#endif
-
 bool pci_ats_disabled(void);
 
-#ifdef CONFIG_PCIE_PTM
-int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
-#else
-static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
-{ return -EINVAL; }
-#endif
-
 void pci_cfg_access_lock(struct pci_dev *dev);
 bool pci_cfg_access_trylock(struct pci_dev *dev);
 void pci_cfg_access_unlock(struct pci_dev *dev);
@@ -1747,11 +1723,6 @@ static inline void pci_release_regions(struct pci_dev *dev) { }
 
 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
 
-static inline void pci_block_cfg_access(struct pci_dev *dev) { }
-static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
-{ return 0; }
-static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
-
 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
 { return NULL; }
 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
@@ -1780,17 +1751,36 @@ static inline const struct pci_device_id *pci_match_id(const struct pci_device_i
                                                          struct pci_dev *dev)
 { return NULL; }
 static inline bool pci_ats_disabled(void) { return true; }
+
+static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
+{
+        return -EINVAL;
+}
+
+static inline int
+pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
+                               unsigned int max_vecs, unsigned int flags,
+                               struct irq_affinity *aff_desc)
+{
+        return -ENOSPC;
+}
 #endif /* CONFIG_PCI */
 
+static inline int
+pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
+                      unsigned int max_vecs, unsigned int flags)
+{
+        return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
+                                              NULL);
+}
+
 #ifdef CONFIG_PCI_ATS
 /* Address Translation Service */
-void pci_ats_init(struct pci_dev *dev);
 int pci_enable_ats(struct pci_dev *dev, int ps);
 void pci_disable_ats(struct pci_dev *dev);
 int pci_ats_queue_depth(struct pci_dev *dev);
 int pci_ats_page_aligned(struct pci_dev *dev);
 #else
-static inline void pci_ats_init(struct pci_dev *d) { }
 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
 static inline void pci_disable_ats(struct pci_dev *d) { }
 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
@@ -1870,25 +1860,9 @@ static inline const char *pci_name(const struct pci_dev *pdev)
         return dev_name(&pdev->dev);
 }
 
-
-/*
- * Some archs don't want to expose struct resource to userland as-is
- * in sysfs and /proc
- */
-#ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
 void pci_resource_to_user(const struct pci_dev *dev, int bar,
                           const struct resource *rsrc,
                           resource_size_t *start, resource_size_t *end);
-#else
-static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
-                const struct resource *rsrc, resource_size_t *start,
-                resource_size_t *end)
-{
-        *start = rsrc->start;
-        *end = rsrc->end;
-}
-#endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
-
 
 /*
  * The world is not perfect and supplies us with broken PCI devices.
@@ -2030,10 +2004,6 @@ extern unsigned long pci_cardbus_mem_size;
 extern u8 pci_dfl_cache_line_size;
 extern u8 pci_cache_line_size;
 
-extern unsigned long pci_hotplug_io_size;
-extern unsigned long pci_hotplug_mem_size;
-extern unsigned long pci_hotplug_bus_size;
-
 /* Architecture-specific versions may override these (weak) */
 void pcibios_disable_device(struct pci_dev *dev);
 void pcibios_set_master(struct pci_dev *dev);
@@ -2303,10 +2273,6 @@ int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
 #ifdef CONFIG_OF
 struct device_node;
 struct irq_domain;
-void pci_set_of_node(struct pci_dev *dev);
-void pci_release_of_node(struct pci_dev *dev);
-void pci_set_bus_of_node(struct pci_bus *bus);
-void pci_release_bus_of_node(struct pci_bus *bus);
 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
 int pci_parse_request_of_pci_ranges(struct device *dev,
                                     struct list_head *resources,
@@ -2316,10 +2282,6 @@ int pci_parse_request_of_pci_ranges(struct device *dev,
 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
 
 #else   /* CONFIG_OF */
-static inline void pci_set_of_node(struct pci_dev *dev) { }
-static inline void pci_release_of_node(struct pci_dev *dev) { }
-static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
-static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
 static inline struct irq_domain *
 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
 static inline int pci_parse_request_of_pci_ranges(struct device *dev,
@@ -2433,4 +2395,7 @@ void pci_uevent_ers(struct pci_dev *pdev, enum  pci_ers_result err_type);
 #define pci_notice_ratelimited(pdev, fmt, arg...) \
         dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
 
+#define pci_info_ratelimited(pdev, fmt, arg...) \
+        dev_info_ratelimited(&(pdev)->dev, fmt, ##arg)
+
 #endif /* LINUX_PCI_H */
diff --git a/include/linux/pci_hotplug.h b/include/linux/pci_hotplug.h
index f694eb2ca978..b482e42d7153 100644
--- a/include/linux/pci_hotplug.h
+++ b/include/linux/pci_hotplug.h
@@ -86,114 +86,14 @@ void pci_hp_deregister(struct hotplug_slot *slot);
 #define pci_hp_initialize(slot, bus, nr, name) \
         __pci_hp_initialize(slot, bus, nr, name, THIS_MODULE, KBUILD_MODNAME)
 
-/* PCI Setting Record (Type 0) */
-struct hpp_type0 {
-        u32 revision;
-        u8  cache_line_size;
-        u8  latency_timer;
-        u8  enable_serr;
-        u8  enable_perr;
-};
-
-/* PCI-X Setting Record (Type 1) */
-struct hpp_type1 {
-        u32 revision;
-        u8  max_mem_read;
-        u8  avg_max_split;
-        u16 tot_max_split;
-};
-
-/* PCI Express Setting Record (Type 2) */
-struct hpp_type2 {
-        u32 revision;
-        u32 unc_err_mask_and;
-        u32 unc_err_mask_or;
-        u32 unc_err_sever_and;
-        u32 unc_err_sever_or;
-        u32 cor_err_mask_and;
-        u32 cor_err_mask_or;
-        u32 adv_err_cap_and;
-        u32 adv_err_cap_or;
-        u16 pci_exp_devctl_and;
-        u16 pci_exp_devctl_or;
-        u16 pci_exp_lnkctl_and;
-        u16 pci_exp_lnkctl_or;
-        u32 sec_unc_err_sever_and;
-        u32 sec_unc_err_sever_or;
-        u32 sec_unc_err_mask_and;
-        u32 sec_unc_err_mask_or;
-};
-
-/*
- * _HPX PCI Express Setting Record (Type 3)
- */
-struct hpx_type3 {
-        u16 device_type;
-        u16 function_type;
-        u16 config_space_location;
-        u16 pci_exp_cap_id;
-        u16 pci_exp_cap_ver;
-        u16 pci_exp_vendor_id;
-        u16 dvsec_id;
-        u16 dvsec_rev;
-        u16 match_offset;
-        u32 match_mask_and;
-        u32 match_value;
-        u16 reg_offset;
-        u32 reg_mask_and;
-        u32 reg_mask_or;
-};
-
-struct hotplug_program_ops {
-        void (*program_type0)(struct pci_dev *dev, struct hpp_type0 *hpp);
-        void (*program_type1)(struct pci_dev *dev, struct hpp_type1 *hpp);
-        void (*program_type2)(struct pci_dev *dev, struct hpp_type2 *hpp);
-        void (*program_type3)(struct pci_dev *dev, struct hpx_type3 *hpp);
-};
-
-enum hpx_type3_dev_type {
-        HPX_TYPE_ENDPOINT       = BIT(0),
-        HPX_TYPE_LEG_END        = BIT(1),
-        HPX_TYPE_RC_END         = BIT(2),
-        HPX_TYPE_RC_EC          = BIT(3),
-        HPX_TYPE_ROOT_PORT      = BIT(4),
-        HPX_TYPE_UPSTREAM       = BIT(5),
-        HPX_TYPE_DOWNSTREAM     = BIT(6),
-        HPX_TYPE_PCI_BRIDGE     = BIT(7),
-        HPX_TYPE_PCIE_BRIDGE    = BIT(8),
-};
-
-enum hpx_type3_fn_type {
-        HPX_FN_NORMAL           = BIT(0),
-        HPX_FN_SRIOV_PHYS       = BIT(1),
-        HPX_FN_SRIOV_VIRT       = BIT(2),
-};
-
-enum hpx_type3_cfg_loc {
-        HPX_CFG_PCICFG          = 0,
-        HPX_CFG_PCIE_CAP        = 1,
-        HPX_CFG_PCIE_CAP_EXT    = 2,
-        HPX_CFG_VEND_CAP        = 3,
-        HPX_CFG_DVSEC           = 4,
-        HPX_CFG_MAX,
-};
-
 #ifdef CONFIG_ACPI
 #include <linux/acpi.h>
-int pci_acpi_program_hp_params(struct pci_dev *dev,
-                               const struct hotplug_program_ops *hp_ops);
 bool pciehp_is_native(struct pci_dev *bridge);
 int acpi_get_hp_hw_control_from_firmware(struct pci_dev *bridge);
 bool shpchp_is_native(struct pci_dev *bridge);
 int acpi_pci_check_ejectable(struct pci_bus *pbus, acpi_handle handle);
 int acpi_pci_detect_ejectable(acpi_handle handle);
 #else
-static inline int pci_acpi_program_hp_params(struct pci_dev *dev,
-                                    const struct hotplug_program_ops *hp_ops)
-{
-        return -ENODEV;
-}
-
 static inline int acpi_get_hp_hw_control_from_firmware(struct pci_dev *bridge)
 {
         return 0;
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index c842735a4f45..f3130542c752 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2132,6 +2132,7 @@
 #define PCI_VENDOR_ID_MYRICOM           0x14c1
 
 #define PCI_VENDOR_ID_MEDIATEK          0x14c3
+#define PCI_DEVICE_ID_MEDIATEK_7629     0x7629
 
 #define PCI_VENDOR_ID_TITAN             0x14D2
 #define PCI_DEVICE_ID_TITAN_010L        0x8001
@@ -2570,6 +2571,8 @@
 
 #define PCI_VENDOR_ID_ASMEDIA           0x1b21
 
+#define PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS     0x1c36
+
 #define PCI_VENDOR_ID_CIRCUITCO         0x1cc8
 #define PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD  0x0001
 
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index f28e562d7ca8..29d6e93fd15e 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -591,6 +591,7 @@
 #define  PCI_EXP_SLTCTL_CCIE    0x0010  /* Command Completed Interrupt Enable */
 #define  PCI_EXP_SLTCTL_HPIE    0x0020  /* Hot-Plug Interrupt Enable */
 #define  PCI_EXP_SLTCTL_AIC     0x00c0  /* Attention Indicator Control */
+#define  PCI_EXP_SLTCTL_ATTN_IND_SHIFT 6      /* Attention Indicator shift */
 #define  PCI_EXP_SLTCTL_ATTN_IND_ON    0x0040 /* Attention Indicator on */
 #define  PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 /* Attention Indicator blinking */
 #define  PCI_EXP_SLTCTL_ATTN_IND_OFF   0x00c0 /* Attention Indicator off */
@@ -713,7 +714,9 @@
 #define PCI_EXT_CAP_ID_DPC      0x1D    /* Downstream Port Containment */
 #define PCI_EXT_CAP_ID_L1SS     0x1E    /* L1 PM Substates */
 #define PCI_EXT_CAP_ID_PTM      0x1F    /* Precision Time Measurement */
-#define PCI_EXT_CAP_ID_MAX      PCI_EXT_CAP_ID_PTM
+#define PCI_EXT_CAP_ID_DLF      0x25    /* Data Link Feature */
+#define PCI_EXT_CAP_ID_PL_16GT  0x26    /* Physical Layer 16.0 GT/s */
+#define PCI_EXT_CAP_ID_MAX      PCI_EXT_CAP_ID_PL_16GT
 
 #define PCI_EXT_CAP_DSN_SIZEOF  12
 #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
@@ -1053,4 +1056,14 @@
 #define  PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000  /* LTR_L1.2_THRESHOLD_Scale */
 #define PCI_L1SS_CTL2           0x0c    /* Control 2 Register */
 
+/* Data Link Feature */
+#define PCI_DLF_CAP             0x04    /* Capabilities Register */
+#define  PCI_DLF_EXCHANGE_ENABLE        0x80000000  /* Data Link Feature Exchange Enable */
+
+/* Physical Layer 16.0 GT/s */
+#define PCI_PL_16GT_LE_CTRL     0x20    /* Lane Equalization Control Register */
+#define  PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK         0x0000000F
+#define  PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK         0x000000F0
+#define  PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT        4
+
 #endif /* LINUX_PCI_REGS_H */