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-rw-r--r--include/asm-generic/pci_iomap.h6
-rw-r--r--include/linux/of_pci.h8
-rw-r--r--include/linux/pci-aspm.h35
-rw-r--r--include/linux/pci-dma-compat.h27
-rw-r--r--include/linux/pci-ecam.h13
-rw-r--r--include/linux/pci-ep-cfs.h5
-rw-r--r--include/linux/pci-epc.h48
-rw-r--r--include/linux/pci-epf.h5
-rw-r--r--include/linux/pci.h441
-rw-r--r--include/linux/pci_hotplug.h16
-rw-r--r--include/linux/pci_ids.h2
-rw-r--r--include/linux/switchtec.h3
-rw-r--r--include/uapi/linux/pci_regs.h30
-rw-r--r--include/uapi/linux/switchtec_ioctl.h3
14 files changed, 298 insertions, 344 deletions
diff --git a/include/asm-generic/pci_iomap.h b/include/asm-generic/pci_iomap.h
index b1e17fcee2d0..854f96ad5ccb 100644
--- a/include/asm-generic/pci_iomap.h
+++ b/include/asm-generic/pci_iomap.h
@@ -1,12 +1,8 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
1/* Generic I/O port emulation, based on MN10300 code 2/* Generic I/O port emulation, based on MN10300 code
2 * 3 *
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved. 4 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com) 5 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
10 */ 6 */
11#ifndef __ASM_GENERIC_PCI_IOMAP_H 7#ifndef __ASM_GENERIC_PCI_IOMAP_H
12#define __ASM_GENERIC_PCI_IOMAP_H 8#define __ASM_GENERIC_PCI_IOMAP_H
diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h
index bf588a05d0d0..88865e0ebf4d 100644
--- a/include/linux/of_pci.h
+++ b/include/linux/of_pci.h
@@ -9,8 +9,7 @@ struct pci_dev;
9struct of_phandle_args; 9struct of_phandle_args;
10struct device_node; 10struct device_node;
11 11
12#ifdef CONFIG_OF_PCI 12#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_PCI)
13int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *out_irq);
14struct device_node *of_pci_find_child_device(struct device_node *parent, 13struct device_node *of_pci_find_child_device(struct device_node *parent,
15 unsigned int devfn); 14 unsigned int devfn);
16int of_pci_get_devfn(struct device_node *np); 15int of_pci_get_devfn(struct device_node *np);
@@ -23,11 +22,6 @@ int of_pci_map_rid(struct device_node *np, u32 rid,
23 const char *map_name, const char *map_mask_name, 22 const char *map_name, const char *map_mask_name,
24 struct device_node **target, u32 *id_out); 23 struct device_node **target, u32 *id_out);
25#else 24#else
26static inline int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *out_irq)
27{
28 return 0;
29}
30
31static inline struct device_node *of_pci_find_child_device(struct device_node *parent, 25static inline struct device_node *of_pci_find_child_device(struct device_node *parent,
32 unsigned int devfn) 26 unsigned int devfn)
33{ 27{
diff --git a/include/linux/pci-aspm.h b/include/linux/pci-aspm.h
index 3cc06b059017..df28af5cef21 100644
--- a/include/linux/pci-aspm.h
+++ b/include/linux/pci-aspm.h
@@ -24,43 +24,12 @@
24#define PCIE_LINK_STATE_CLKPM 4 24#define PCIE_LINK_STATE_CLKPM 4
25 25
26#ifdef CONFIG_PCIEASPM 26#ifdef CONFIG_PCIEASPM
27void pcie_aspm_init_link_state(struct pci_dev *pdev);
28void pcie_aspm_exit_link_state(struct pci_dev *pdev);
29void pcie_aspm_pm_state_change(struct pci_dev *pdev);
30void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
31void pci_disable_link_state(struct pci_dev *pdev, int state); 27void pci_disable_link_state(struct pci_dev *pdev, int state);
32void pci_disable_link_state_locked(struct pci_dev *pdev, int state); 28void pci_disable_link_state_locked(struct pci_dev *pdev, int state);
33void pcie_no_aspm(void); 29void pcie_no_aspm(void);
34#else 30#else
35static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) 31static inline void pci_disable_link_state(struct pci_dev *pdev, int state) { }
36{ 32static inline void pcie_no_aspm(void) { }
37}
38static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev)
39{
40}
41static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev)
42{
43}
44static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
45{
46}
47static inline void pci_disable_link_state(struct pci_dev *pdev, int state)
48{
49}
50static inline void pcie_no_aspm(void)
51{
52}
53#endif 33#endif
54 34
55#ifdef CONFIG_PCIEASPM_DEBUG /* this depends on CONFIG_PCIEASPM */
56void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
57void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
58#else
59static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
60{
61}
62static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
63{
64}
65#endif
66#endif /* LINUX_ASPM_H */ 35#endif /* LINUX_ASPM_H */
diff --git a/include/linux/pci-dma-compat.h b/include/linux/pci-dma-compat.h
index d1f9fdade1e0..0dd1a3f7b309 100644
--- a/include/linux/pci-dma-compat.h
+++ b/include/linux/pci-dma-compat.h
@@ -17,91 +17,90 @@ static inline void *
17pci_alloc_consistent(struct pci_dev *hwdev, size_t size, 17pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
18 dma_addr_t *dma_handle) 18 dma_addr_t *dma_handle)
19{ 19{
20 return dma_alloc_coherent(hwdev == NULL ? NULL : &hwdev->dev, size, dma_handle, GFP_ATOMIC); 20 return dma_alloc_coherent(&hwdev->dev, size, dma_handle, GFP_ATOMIC);
21} 21}
22 22
23static inline void * 23static inline void *
24pci_zalloc_consistent(struct pci_dev *hwdev, size_t size, 24pci_zalloc_consistent(struct pci_dev *hwdev, size_t size,
25 dma_addr_t *dma_handle) 25 dma_addr_t *dma_handle)
26{ 26{
27 return dma_zalloc_coherent(hwdev == NULL ? NULL : &hwdev->dev, 27 return dma_zalloc_coherent(&hwdev->dev, size, dma_handle, GFP_ATOMIC);
28 size, dma_handle, GFP_ATOMIC);
29} 28}
30 29
31static inline void 30static inline void
32pci_free_consistent(struct pci_dev *hwdev, size_t size, 31pci_free_consistent(struct pci_dev *hwdev, size_t size,
33 void *vaddr, dma_addr_t dma_handle) 32 void *vaddr, dma_addr_t dma_handle)
34{ 33{
35 dma_free_coherent(hwdev == NULL ? NULL : &hwdev->dev, size, vaddr, dma_handle); 34 dma_free_coherent(&hwdev->dev, size, vaddr, dma_handle);
36} 35}
37 36
38static inline dma_addr_t 37static inline dma_addr_t
39pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction) 38pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction)
40{ 39{
41 return dma_map_single(hwdev == NULL ? NULL : &hwdev->dev, ptr, size, (enum dma_data_direction)direction); 40 return dma_map_single(&hwdev->dev, ptr, size, (enum dma_data_direction)direction);
42} 41}
43 42
44static inline void 43static inline void
45pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, 44pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
46 size_t size, int direction) 45 size_t size, int direction)
47{ 46{
48 dma_unmap_single(hwdev == NULL ? NULL : &hwdev->dev, dma_addr, size, (enum dma_data_direction)direction); 47 dma_unmap_single(&hwdev->dev, dma_addr, size, (enum dma_data_direction)direction);
49} 48}
50 49
51static inline dma_addr_t 50static inline dma_addr_t
52pci_map_page(struct pci_dev *hwdev, struct page *page, 51pci_map_page(struct pci_dev *hwdev, struct page *page,
53 unsigned long offset, size_t size, int direction) 52 unsigned long offset, size_t size, int direction)
54{ 53{
55 return dma_map_page(hwdev == NULL ? NULL : &hwdev->dev, page, offset, size, (enum dma_data_direction)direction); 54 return dma_map_page(&hwdev->dev, page, offset, size, (enum dma_data_direction)direction);
56} 55}
57 56
58static inline void 57static inline void
59pci_unmap_page(struct pci_dev *hwdev, dma_addr_t dma_address, 58pci_unmap_page(struct pci_dev *hwdev, dma_addr_t dma_address,
60 size_t size, int direction) 59 size_t size, int direction)
61{ 60{
62 dma_unmap_page(hwdev == NULL ? NULL : &hwdev->dev, dma_address, size, (enum dma_data_direction)direction); 61 dma_unmap_page(&hwdev->dev, dma_address, size, (enum dma_data_direction)direction);
63} 62}
64 63
65static inline int 64static inline int
66pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, 65pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
67 int nents, int direction) 66 int nents, int direction)
68{ 67{
69 return dma_map_sg(hwdev == NULL ? NULL : &hwdev->dev, sg, nents, (enum dma_data_direction)direction); 68 return dma_map_sg(&hwdev->dev, sg, nents, (enum dma_data_direction)direction);
70} 69}
71 70
72static inline void 71static inline void
73pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, 72pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
74 int nents, int direction) 73 int nents, int direction)
75{ 74{
76 dma_unmap_sg(hwdev == NULL ? NULL : &hwdev->dev, sg, nents, (enum dma_data_direction)direction); 75 dma_unmap_sg(&hwdev->dev, sg, nents, (enum dma_data_direction)direction);
77} 76}
78 77
79static inline void 78static inline void
80pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t dma_handle, 79pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t dma_handle,
81 size_t size, int direction) 80 size_t size, int direction)
82{ 81{
83 dma_sync_single_for_cpu(hwdev == NULL ? NULL : &hwdev->dev, dma_handle, size, (enum dma_data_direction)direction); 82 dma_sync_single_for_cpu(&hwdev->dev, dma_handle, size, (enum dma_data_direction)direction);
84} 83}
85 84
86static inline void 85static inline void
87pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t dma_handle, 86pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t dma_handle,
88 size_t size, int direction) 87 size_t size, int direction)
89{ 88{
90 dma_sync_single_for_device(hwdev == NULL ? NULL : &hwdev->dev, dma_handle, size, (enum dma_data_direction)direction); 89 dma_sync_single_for_device(&hwdev->dev, dma_handle, size, (enum dma_data_direction)direction);
91} 90}
92 91
93static inline void 92static inline void
94pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sg, 93pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sg,
95 int nelems, int direction) 94 int nelems, int direction)
96{ 95{
97 dma_sync_sg_for_cpu(hwdev == NULL ? NULL : &hwdev->dev, sg, nelems, (enum dma_data_direction)direction); 96 dma_sync_sg_for_cpu(&hwdev->dev, sg, nelems, (enum dma_data_direction)direction);
98} 97}
99 98
100static inline void 99static inline void
101pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sg, 100pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sg,
102 int nelems, int direction) 101 int nelems, int direction)
103{ 102{
104 dma_sync_sg_for_device(hwdev == NULL ? NULL : &hwdev->dev, sg, nelems, (enum dma_data_direction)direction); 103 dma_sync_sg_for_device(&hwdev->dev, sg, nelems, (enum dma_data_direction)direction);
105} 104}
106 105
107static inline int 106static inline int
diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h
index 809c2f1873ac..baadad1aabbc 100644
--- a/include/linux/pci-ecam.h
+++ b/include/linux/pci-ecam.h
@@ -1,17 +1,6 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Copyright 2016 Broadcom 3 * Copyright 2016 Broadcom
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License, version 2, as
6 * published by the Free Software Foundation (the "GPL").
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License version 2 (GPLv2) for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * version 2 (GPLv2) along with this source code.
15 */ 4 */
16#ifndef DRIVERS_PCI_ECAM_H 5#ifndef DRIVERS_PCI_ECAM_H
17#define DRIVERS_PCI_ECAM_H 6#define DRIVERS_PCI_ECAM_H
diff --git a/include/linux/pci-ep-cfs.h b/include/linux/pci-ep-cfs.h
index 263b89ea5705..f42b0fd4b4bc 100644
--- a/include/linux/pci-ep-cfs.h
+++ b/include/linux/pci-ep-cfs.h
@@ -1,12 +1,9 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
1/** 2/**
2 * PCI Endpoint ConfigFS header file 3 * PCI Endpoint ConfigFS header file
3 * 4 *
4 * Copyright (C) 2017 Texas Instruments 5 * Copyright (C) 2017 Texas Instruments
5 * Author: Kishon Vijay Abraham I <kishon@ti.com> 6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
10 */ 7 */
11 8
12#ifndef __LINUX_PCI_EP_CFS_H 9#ifndef __LINUX_PCI_EP_CFS_H
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index f7a04e1af112..a1a5e5df0f66 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -1,12 +1,9 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/** 2/**
2 * PCI Endpoint *Controller* (EPC) header file 3 * PCI Endpoint *Controller* (EPC) header file
3 * 4 *
4 * Copyright (C) 2017 Texas Instruments 5 * Copyright (C) 2017 Texas Instruments
5 * Author: Kishon Vijay Abraham I <kishon@ti.com> 6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
10 */ 7 */
11 8
12#ifndef __LINUX_PCI_EPC_H 9#ifndef __LINUX_PCI_EPC_H
@@ -39,17 +36,20 @@ enum pci_epc_irq_type {
39 * @owner: the module owner containing the ops 36 * @owner: the module owner containing the ops
40 */ 37 */
41struct pci_epc_ops { 38struct pci_epc_ops {
42 int (*write_header)(struct pci_epc *pci_epc, 39 int (*write_header)(struct pci_epc *epc, u8 func_no,
43 struct pci_epf_header *hdr); 40 struct pci_epf_header *hdr);
44 int (*set_bar)(struct pci_epc *epc, enum pci_barno bar, 41 int (*set_bar)(struct pci_epc *epc, u8 func_no,
42 enum pci_barno bar,
45 dma_addr_t bar_phys, size_t size, int flags); 43 dma_addr_t bar_phys, size_t size, int flags);
46 void (*clear_bar)(struct pci_epc *epc, enum pci_barno bar); 44 void (*clear_bar)(struct pci_epc *epc, u8 func_no,
47 int (*map_addr)(struct pci_epc *epc, phys_addr_t addr, 45 enum pci_barno bar);
48 u64 pci_addr, size_t size); 46 int (*map_addr)(struct pci_epc *epc, u8 func_no,
49 void (*unmap_addr)(struct pci_epc *epc, phys_addr_t addr); 47 phys_addr_t addr, u64 pci_addr, size_t size);
50 int (*set_msi)(struct pci_epc *epc, u8 interrupts); 48 void (*unmap_addr)(struct pci_epc *epc, u8 func_no,
51 int (*get_msi)(struct pci_epc *epc); 49 phys_addr_t addr);
52 int (*raise_irq)(struct pci_epc *pci_epc, 50 int (*set_msi)(struct pci_epc *epc, u8 func_no, u8 interrupts);
51 int (*get_msi)(struct pci_epc *epc, u8 func_no);
52 int (*raise_irq)(struct pci_epc *epc, u8 func_no,
53 enum pci_epc_irq_type type, u8 interrupt_num); 53 enum pci_epc_irq_type type, u8 interrupt_num);
54 int (*start)(struct pci_epc *epc); 54 int (*start)(struct pci_epc *epc);
55 void (*stop)(struct pci_epc *epc); 55 void (*stop)(struct pci_epc *epc);
@@ -124,17 +124,21 @@ void pci_epc_destroy(struct pci_epc *epc);
124int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf); 124int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf);
125void pci_epc_linkup(struct pci_epc *epc); 125void pci_epc_linkup(struct pci_epc *epc);
126void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf); 126void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf);
127int pci_epc_write_header(struct pci_epc *epc, struct pci_epf_header *hdr); 127int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
128int pci_epc_set_bar(struct pci_epc *epc, enum pci_barno bar, 128 struct pci_epf_header *hdr);
129int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
130 enum pci_barno bar,
129 dma_addr_t bar_phys, size_t size, int flags); 131 dma_addr_t bar_phys, size_t size, int flags);
130void pci_epc_clear_bar(struct pci_epc *epc, int bar); 132void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, int bar);
131int pci_epc_map_addr(struct pci_epc *epc, phys_addr_t phys_addr, 133int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
134 phys_addr_t phys_addr,
132 u64 pci_addr, size_t size); 135 u64 pci_addr, size_t size);
133void pci_epc_unmap_addr(struct pci_epc *epc, phys_addr_t phys_addr); 136void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
134int pci_epc_set_msi(struct pci_epc *epc, u8 interrupts); 137 phys_addr_t phys_addr);
135int pci_epc_get_msi(struct pci_epc *epc); 138int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts);
136int pci_epc_raise_irq(struct pci_epc *epc, enum pci_epc_irq_type type, 139int pci_epc_get_msi(struct pci_epc *epc, u8 func_no);
137 u8 interrupt_num); 140int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
141 enum pci_epc_irq_type type, u8 interrupt_num);
138int pci_epc_start(struct pci_epc *epc); 142int pci_epc_start(struct pci_epc *epc);
139void pci_epc_stop(struct pci_epc *epc); 143void pci_epc_stop(struct pci_epc *epc);
140struct pci_epc *pci_epc_get(const char *epc_name); 144struct pci_epc *pci_epc_get(const char *epc_name);
diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h
index 60d551a9a1ba..e897bf076701 100644
--- a/include/linux/pci-epf.h
+++ b/include/linux/pci-epf.h
@@ -1,12 +1,9 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/** 2/**
2 * PCI Endpoint *Function* (EPF) header file 3 * PCI Endpoint *Function* (EPF) header file
3 * 4 *
4 * Copyright (C) 2017 Texas Instruments 5 * Copyright (C) 2017 Texas Instruments
5 * Author: Kishon Vijay Abraham I <kishon@ti.com> 6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 of
9 * the License as published by the Free Software Foundation.
10 */ 7 */
11 8
12#ifndef __LINUX_PCI_EPF_H 9#ifndef __LINUX_PCI_EPF_H
diff --git a/include/linux/pci.h b/include/linux/pci.h
index ad35aac87971..024a1beda008 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -48,17 +48,17 @@
48 * In the interest of not exposing interfaces to user-space unnecessarily, 48 * In the interest of not exposing interfaces to user-space unnecessarily,
49 * the following kernel-only defines are being added here. 49 * the following kernel-only defines are being added here.
50 */ 50 */
51#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn)) 51#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
52/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */ 52/* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
53#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff) 53#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
54 54
55/* pci_slot represents a physical slot */ 55/* pci_slot represents a physical slot */
56struct pci_slot { 56struct pci_slot {
57 struct pci_bus *bus; /* The bus this slot is on */ 57 struct pci_bus *bus; /* Bus this slot is on */
58 struct list_head list; /* node in list of slots on this bus */ 58 struct list_head list; /* Node in list of slots */
59 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */ 59 struct hotplug_slot *hotplug; /* Hotplug info (move here) */
60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */ 60 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
61 struct kobject kobj; 61 struct kobject kobj;
62}; 62};
63 63
64static inline const char *pci_slot_name(const struct pci_slot *slot) 64static inline const char *pci_slot_name(const struct pci_slot *slot)
@@ -72,9 +72,7 @@ enum pci_mmap_state {
72 pci_mmap_mem 72 pci_mmap_mem
73}; 73};
74 74
75/* 75/* For PCI devices, the region numbers are assigned this way: */
76 * For PCI devices, the region numbers are assigned this way:
77 */
78enum { 76enum {
79 /* #0-5: standard PCI resources */ 77 /* #0-5: standard PCI resources */
80 PCI_STD_RESOURCES, 78 PCI_STD_RESOURCES,
@@ -83,23 +81,23 @@ enum {
83 /* #6: expansion ROM resource */ 81 /* #6: expansion ROM resource */
84 PCI_ROM_RESOURCE, 82 PCI_ROM_RESOURCE,
85 83
86 /* device specific resources */ 84 /* Device-specific resources */
87#ifdef CONFIG_PCI_IOV 85#ifdef CONFIG_PCI_IOV
88 PCI_IOV_RESOURCES, 86 PCI_IOV_RESOURCES,
89 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1, 87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
90#endif 88#endif
91 89
92 /* resources assigned to buses behind the bridge */ 90 /* Resources assigned to buses behind the bridge */
93#define PCI_BRIDGE_RESOURCE_NUM 4 91#define PCI_BRIDGE_RESOURCE_NUM 4
94 92
95 PCI_BRIDGE_RESOURCES, 93 PCI_BRIDGE_RESOURCES,
96 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES + 94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
97 PCI_BRIDGE_RESOURCE_NUM - 1, 95 PCI_BRIDGE_RESOURCE_NUM - 1,
98 96
99 /* total resources associated with a PCI device */ 97 /* Total resources associated with a PCI device */
100 PCI_NUM_RESOURCES, 98 PCI_NUM_RESOURCES,
101 99
102 /* preserve this for compatibility */ 100 /* Preserve this for compatibility */
103 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES, 101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
104}; 102};
105 103
@@ -152,9 +150,10 @@ static inline const char *pci_power_name(pci_power_t state)
152#define PCI_PM_D3COLD_WAIT 100 150#define PCI_PM_D3COLD_WAIT 100
153#define PCI_PM_BUS_WAIT 50 151#define PCI_PM_BUS_WAIT 50
154 152
155/** The pci_channel state describes connectivity between the CPU and 153/**
156 * the pci device. If some PCI bus between here and the pci device 154 * The pci_channel state describes connectivity between the CPU and
157 * has crashed or locked up, this info is reflected here. 155 * the PCI device. If some PCI bus between here and the PCI device
156 * has crashed or locked up, this info is reflected here.
158 */ 157 */
159typedef unsigned int __bitwise pci_channel_state_t; 158typedef unsigned int __bitwise pci_channel_state_t;
160 159
@@ -184,9 +183,7 @@ enum pcie_reset_state {
184 183
185typedef unsigned short __bitwise pci_dev_flags_t; 184typedef unsigned short __bitwise pci_dev_flags_t;
186enum pci_dev_flags { 185enum pci_dev_flags {
187 /* INTX_DISABLE in PCI_COMMAND register disables MSI 186 /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
188 * generation too.
189 */
190 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0), 187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
191 /* Device configuration is irrevocably lost if disabled into D3 */ 188 /* Device configuration is irrevocably lost if disabled into D3 */
192 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1), 189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
@@ -202,7 +199,7 @@ enum pci_dev_flags {
202 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7), 199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
203 /* Get VPD from function 0 VPD */ 200 /* Get VPD from function 0 VPD */
204 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8), 201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
205 /* a non-root bridge where translation occurs, stop alias search here */ 202 /* A non-root bridge where translation occurs, stop alias search here */
206 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), 203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
207 /* Do not use FLR even if device advertises PCI_AF_CAP */ 204 /* Do not use FLR even if device advertises PCI_AF_CAP */
208 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), 205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
@@ -222,17 +219,17 @@ enum pci_bus_flags {
222 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4, 219 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
223}; 220};
224 221
225/* These values come from the PCI Express Spec */ 222/* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
226enum pcie_link_width { 223enum pcie_link_width {
227 PCIE_LNK_WIDTH_RESRV = 0x00, 224 PCIE_LNK_WIDTH_RESRV = 0x00,
228 PCIE_LNK_X1 = 0x01, 225 PCIE_LNK_X1 = 0x01,
229 PCIE_LNK_X2 = 0x02, 226 PCIE_LNK_X2 = 0x02,
230 PCIE_LNK_X4 = 0x04, 227 PCIE_LNK_X4 = 0x04,
231 PCIE_LNK_X8 = 0x08, 228 PCIE_LNK_X8 = 0x08,
232 PCIE_LNK_X12 = 0x0C, 229 PCIE_LNK_X12 = 0x0c,
233 PCIE_LNK_X16 = 0x10, 230 PCIE_LNK_X16 = 0x10,
234 PCIE_LNK_X32 = 0x20, 231 PCIE_LNK_X32 = 0x20,
235 PCIE_LNK_WIDTH_UNKNOWN = 0xFF, 232 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
236}; 233};
237 234
238/* Based on the PCI Hotplug Spec, but some values are made up by us */ 235/* Based on the PCI Hotplug Spec, but some values are made up by us */
@@ -263,15 +260,15 @@ enum pci_bus_speed {
263}; 260};
264 261
265struct pci_cap_saved_data { 262struct pci_cap_saved_data {
266 u16 cap_nr; 263 u16 cap_nr;
267 bool cap_extended; 264 bool cap_extended;
268 unsigned int size; 265 unsigned int size;
269 u32 data[0]; 266 u32 data[0];
270}; 267};
271 268
272struct pci_cap_saved_state { 269struct pci_cap_saved_state {
273 struct hlist_node next; 270 struct hlist_node next;
274 struct pci_cap_saved_data cap; 271 struct pci_cap_saved_data cap;
275}; 272};
276 273
277struct irq_affinity; 274struct irq_affinity;
@@ -280,19 +277,17 @@ struct pci_vpd;
280struct pci_sriov; 277struct pci_sriov;
281struct pci_ats; 278struct pci_ats;
282 279
283/* 280/* The pci_dev structure describes PCI devices */
284 * The pci_dev structure is used to describe PCI devices.
285 */
286struct pci_dev { 281struct pci_dev {
287 struct list_head bus_list; /* node in per-bus list */ 282 struct list_head bus_list; /* Node in per-bus list */
288 struct pci_bus *bus; /* bus this device is on */ 283 struct pci_bus *bus; /* Bus this device is on */
289 struct pci_bus *subordinate; /* bus this device bridges to */ 284 struct pci_bus *subordinate; /* Bus this device bridges to */
290 285
291 void *sysdata; /* hook for sys-specific extension */ 286 void *sysdata; /* Hook for sys-specific extension */
292 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */ 287 struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
293 struct pci_slot *slot; /* Physical slot this device is in */ 288 struct pci_slot *slot; /* Physical slot this device is in */
294 289
295 unsigned int devfn; /* encoded device & function index */ 290 unsigned int devfn; /* Encoded device & function index */
296 unsigned short vendor; 291 unsigned short vendor;
297 unsigned short device; 292 unsigned short device;
298 unsigned short subsystem_vendor; 293 unsigned short subsystem_vendor;
@@ -307,12 +302,12 @@ struct pci_dev {
307 u8 msi_cap; /* MSI capability offset */ 302 u8 msi_cap; /* MSI capability offset */
308 u8 msix_cap; /* MSI-X capability offset */ 303 u8 msix_cap; /* MSI-X capability offset */
309 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */ 304 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
310 u8 rom_base_reg; /* which config register controls the ROM */ 305 u8 rom_base_reg; /* Config register controlling ROM */
311 u8 pin; /* which interrupt pin this device uses */ 306 u8 pin; /* Interrupt pin this device uses */
312 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */ 307 u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
313 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */ 308 unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
314 309
315 struct pci_driver *driver; /* which driver has allocated this device */ 310 struct pci_driver *driver; /* Driver bound to this device */
316 u64 dma_mask; /* Mask of the bits of bus address this 311 u64 dma_mask; /* Mask of the bits of bus address this
317 device implements. Normally this is 312 device implements. Normally this is
318 0xffffffff. You only need to change 313 0xffffffff. You only need to change
@@ -321,9 +316,9 @@ struct pci_dev {
321 316
322 struct device_dma_parameters dma_parms; 317 struct device_dma_parameters dma_parms;
323 318
324 pci_power_t current_state; /* Current operating state. In ACPI-speak, 319 pci_power_t current_state; /* Current operating state. In ACPI,
325 this is D0-D3, D0 being fully functional, 320 this is D0-D3, D0 being fully
326 and D3 being off. */ 321 functional, and D3 being off. */
327 u8 pm_cap; /* PM capability offset */ 322 u8 pm_cap; /* PM capability offset */
328 unsigned int pme_support:5; /* Bitmask of states from which PME# 323 unsigned int pme_support:5; /* Bitmask of states from which PME#
329 can be generated */ 324 can be generated */
@@ -334,10 +329,10 @@ struct pci_dev {
334 unsigned int no_d3cold:1; /* D3cold is forbidden */ 329 unsigned int no_d3cold:1; /* D3cold is forbidden */
335 unsigned int bridge_d3:1; /* Allow D3 for bridge */ 330 unsigned int bridge_d3:1; /* Allow D3 for bridge */
336 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */ 331 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
337 unsigned int mmio_always_on:1; /* disallow turning off io/mem 332 unsigned int mmio_always_on:1; /* Disallow turning off io/mem
338 decoding during bar sizing */ 333 decoding during BAR sizing */
339 unsigned int wakeup_prepared:1; 334 unsigned int wakeup_prepared:1;
340 unsigned int runtime_d3cold:1; /* whether go through runtime 335 unsigned int runtime_d3cold:1; /* Whether go through runtime
341 D3cold, not set for devices 336 D3cold, not set for devices
342 powered on/off by the 337 powered on/off by the
343 corresponding bridge */ 338 corresponding bridge */
@@ -350,12 +345,14 @@ struct pci_dev {
350 345
351#ifdef CONFIG_PCIEASPM 346#ifdef CONFIG_PCIEASPM
352 struct pcie_link_state *link_state; /* ASPM link state */ 347 struct pcie_link_state *link_state; /* ASPM link state */
348 unsigned int ltr_path:1; /* Latency Tolerance Reporting
349 supported from root to here */
353#endif 350#endif
354 351
355 pci_channel_state_t error_state; /* current connectivity state */ 352 pci_channel_state_t error_state; /* Current connectivity state */
356 struct device dev; /* Generic device interface */ 353 struct device dev; /* Generic device interface */
357 354
358 int cfg_size; /* Size of configuration space */ 355 int cfg_size; /* Size of config space */
359 356
360 /* 357 /*
361 * Instead of touching interrupt line and base address registers 358 * Instead of touching interrupt line and base address registers
@@ -364,47 +361,47 @@ struct pci_dev {
364 unsigned int irq; 361 unsigned int irq;
365 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */ 362 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
366 363
367 bool match_driver; /* Skip attaching driver */ 364 bool match_driver; /* Skip attaching driver */
368 /* These fields are used by common fixups */ 365
369 unsigned int transparent:1; /* Subtractive decode PCI bridge */ 366 unsigned int transparent:1; /* Subtractive decode bridge */
370 unsigned int multifunction:1;/* Part of multi-function device */ 367 unsigned int multifunction:1; /* Multi-function device */
371 /* keep track of device state */ 368
372 unsigned int is_added:1; 369 unsigned int is_added:1;
373 unsigned int is_busmaster:1; /* device is busmaster */ 370 unsigned int is_busmaster:1; /* Is busmaster */
374 unsigned int no_msi:1; /* device may not use msi */ 371 unsigned int no_msi:1; /* May not use MSI */
375 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */ 372 unsigned int no_64bit_msi:1; /* May only use 32-bit MSIs */
376 unsigned int block_cfg_access:1; /* config space access is blocked */ 373 unsigned int block_cfg_access:1; /* Config space access blocked */
377 unsigned int broken_parity_status:1; /* Device generates false positive parity */ 374 unsigned int broken_parity_status:1; /* Generates false positive parity */
378 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */ 375 unsigned int irq_reroute_variant:2; /* Needs IRQ rerouting variant */
379 unsigned int msi_enabled:1; 376 unsigned int msi_enabled:1;
380 unsigned int msix_enabled:1; 377 unsigned int msix_enabled:1;
381 unsigned int ari_enabled:1; /* ARI forwarding */ 378 unsigned int ari_enabled:1; /* ARI forwarding */
382 unsigned int ats_enabled:1; /* Address Translation Service */ 379 unsigned int ats_enabled:1; /* Address Translation Svc */
383 unsigned int pasid_enabled:1; /* Process Address Space ID */ 380 unsigned int pasid_enabled:1; /* Process Address Space ID */
384 unsigned int pri_enabled:1; /* Page Request Interface */ 381 unsigned int pri_enabled:1; /* Page Request Interface */
385 unsigned int is_managed:1; 382 unsigned int is_managed:1;
386 unsigned int needs_freset:1; /* Dev requires fundamental reset */ 383 unsigned int needs_freset:1; /* Requires fundamental reset */
387 unsigned int state_saved:1; 384 unsigned int state_saved:1;
388 unsigned int is_physfn:1; 385 unsigned int is_physfn:1;
389 unsigned int is_virtfn:1; 386 unsigned int is_virtfn:1;
390 unsigned int reset_fn:1; 387 unsigned int reset_fn:1;
391 unsigned int is_hotplug_bridge:1; 388 unsigned int is_hotplug_bridge:1;
392 unsigned int is_thunderbolt:1; /* Thunderbolt controller */ 389 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
393 unsigned int __aer_firmware_first_valid:1; 390 unsigned int __aer_firmware_first_valid:1;
394 unsigned int __aer_firmware_first:1; 391 unsigned int __aer_firmware_first:1;
395 unsigned int broken_intx_masking:1; /* INTx masking can't be used */ 392 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
396 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */ 393 unsigned int io_window_1k:1; /* Intel bridge 1K I/O windows */
397 unsigned int irq_managed:1; 394 unsigned int irq_managed:1;
398 unsigned int has_secondary_link:1; 395 unsigned int has_secondary_link:1;
399 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */ 396 unsigned int non_compliant_bars:1; /* Broken BARs; ignore them */
400 unsigned int is_probed:1; /* device probing in progress */ 397 unsigned int is_probed:1; /* Device probing in progress */
401 pci_dev_flags_t dev_flags; 398 pci_dev_flags_t dev_flags;
402 atomic_t enable_cnt; /* pci_enable_device has been called */ 399 atomic_t enable_cnt; /* pci_enable_device has been called */
403 400
404 u32 saved_config_space[16]; /* config space saved at suspend time */ 401 u32 saved_config_space[16]; /* Config space saved at suspend time */
405 struct hlist_head saved_cap_space; 402 struct hlist_head saved_cap_space;
406 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */ 403 struct bin_attribute *rom_attr; /* Attribute descriptor for sysfs ROM entry */
407 int rom_attr_enabled; /* has display of the rom attribute been enabled? */ 404 int rom_attr_enabled; /* Display of ROM attribute enabled? */
408 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */ 405 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
409 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */ 406 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
410 407
@@ -419,12 +416,12 @@ struct pci_dev {
419 struct pci_vpd *vpd; 416 struct pci_vpd *vpd;
420#ifdef CONFIG_PCI_ATS 417#ifdef CONFIG_PCI_ATS
421 union { 418 union {
422 struct pci_sriov *sriov; /* SR-IOV capability related */ 419 struct pci_sriov *sriov; /* PF: SR-IOV info */
423 struct pci_dev *physfn; /* the PF this VF is associated with */ 420 struct pci_dev *physfn; /* VF: related PF */
424 }; 421 };
425 u16 ats_cap; /* ATS Capability offset */ 422 u16 ats_cap; /* ATS Capability offset */
426 u8 ats_stu; /* ATS Smallest Translation Unit */ 423 u8 ats_stu; /* ATS Smallest Translation Unit */
427 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */ 424 atomic_t ats_ref_cnt; /* Number of VFs with ATS enabled */
428#endif 425#endif
429#ifdef CONFIG_PCI_PRI 426#ifdef CONFIG_PCI_PRI
430 u32 pri_reqs_alloc; /* Number of PRI requests allocated */ 427 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
@@ -432,11 +429,11 @@ struct pci_dev {
432#ifdef CONFIG_PCI_PASID 429#ifdef CONFIG_PCI_PASID
433 u16 pasid_features; 430 u16 pasid_features;
434#endif 431#endif
435 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */ 432 phys_addr_t rom; /* Physical address if not from BAR */
436 size_t romlen; /* Length of ROM if it's not from the BAR */ 433 size_t romlen; /* Length if not from BAR */
437 char *driver_override; /* Driver name to force a match */ 434 char *driver_override; /* Driver name to force a match */
438 435
439 unsigned long priv_flags; /* Private flags for the pci driver */ 436 unsigned long priv_flags; /* Private flags for the PCI driver */
440}; 437};
441 438
442static inline struct pci_dev *pci_physfn(struct pci_dev *dev) 439static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
@@ -459,26 +456,26 @@ static inline int pci_channel_offline(struct pci_dev *pdev)
459} 456}
460 457
461struct pci_host_bridge { 458struct pci_host_bridge {
462 struct device dev; 459 struct device dev;
463 struct pci_bus *bus; /* root bus */ 460 struct pci_bus *bus; /* Root bus */
464 struct pci_ops *ops; 461 struct pci_ops *ops;
465 void *sysdata; 462 void *sysdata;
466 int busnr; 463 int busnr;
467 struct list_head windows; /* resource_entry */ 464 struct list_head windows; /* resource_entry */
468 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* platform IRQ swizzler */ 465 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
469 int (*map_irq)(const struct pci_dev *, u8, u8); 466 int (*map_irq)(const struct pci_dev *, u8, u8);
470 void (*release_fn)(struct pci_host_bridge *); 467 void (*release_fn)(struct pci_host_bridge *);
471 void *release_data; 468 void *release_data;
472 struct msi_controller *msi; 469 struct msi_controller *msi;
473 unsigned int ignore_reset_delay:1; /* for entire hierarchy */ 470 unsigned int ignore_reset_delay:1; /* For entire hierarchy */
474 unsigned int no_ext_tags:1; /* no Extended Tags */ 471 unsigned int no_ext_tags:1; /* No Extended Tags */
475 /* Resource alignment requirements */ 472 /* Resource alignment requirements */
476 resource_size_t (*align_resource)(struct pci_dev *dev, 473 resource_size_t (*align_resource)(struct pci_dev *dev,
477 const struct resource *res, 474 const struct resource *res,
478 resource_size_t start, 475 resource_size_t start,
479 resource_size_t size, 476 resource_size_t size,
480 resource_size_t align); 477 resource_size_t align);
481 unsigned long private[0] ____cacheline_aligned; 478 unsigned long private[0] ____cacheline_aligned;
482}; 479};
483 480
484#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev) 481#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
@@ -500,8 +497,8 @@ void pci_free_host_bridge(struct pci_host_bridge *bridge);
500struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus); 497struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
501 498
502void pci_set_host_bridge_release(struct pci_host_bridge *bridge, 499void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
503 void (*release_fn)(struct pci_host_bridge *), 500 void (*release_fn)(struct pci_host_bridge *),
504 void *release_data); 501 void *release_data);
505 502
506int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge); 503int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
507 504
@@ -521,32 +518,32 @@ int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
521#define PCI_SUBTRACTIVE_DECODE 0x1 518#define PCI_SUBTRACTIVE_DECODE 0x1
522 519
523struct pci_bus_resource { 520struct pci_bus_resource {
524 struct list_head list; 521 struct list_head list;
525 struct resource *res; 522 struct resource *res;
526 unsigned int flags; 523 unsigned int flags;
527}; 524};
528 525
529#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */ 526#define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
530 527
531struct pci_bus { 528struct pci_bus {
532 struct list_head node; /* node in list of buses */ 529 struct list_head node; /* Node in list of buses */
533 struct pci_bus *parent; /* parent bus this bridge is on */ 530 struct pci_bus *parent; /* Parent bus this bridge is on */
534 struct list_head children; /* list of child buses */ 531 struct list_head children; /* List of child buses */
535 struct list_head devices; /* list of devices on this bus */ 532 struct list_head devices; /* List of devices on this bus */
536 struct pci_dev *self; /* bridge device as seen by parent */ 533 struct pci_dev *self; /* Bridge device as seen by parent */
537 struct list_head slots; /* list of slots on this bus; 534 struct list_head slots; /* List of slots on this bus;
538 protected by pci_slot_mutex */ 535 protected by pci_slot_mutex */
539 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM]; 536 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
540 struct list_head resources; /* address space routed to this bus */ 537 struct list_head resources; /* Address space routed to this bus */
541 struct resource busn_res; /* bus numbers routed to this bus */ 538 struct resource busn_res; /* Bus numbers routed to this bus */
542 539
543 struct pci_ops *ops; /* configuration access functions */ 540 struct pci_ops *ops; /* Configuration access functions */
544 struct msi_controller *msi; /* MSI controller */ 541 struct msi_controller *msi; /* MSI controller */
545 void *sysdata; /* hook for sys-specific extension */ 542 void *sysdata; /* Hook for sys-specific extension */
546 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */ 543 struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
547 544
548 unsigned char number; /* bus number */ 545 unsigned char number; /* Bus number */
549 unsigned char primary; /* number of primary bridge */ 546 unsigned char primary; /* Number of primary bridge */
550 unsigned char max_bus_speed; /* enum pci_bus_speed */ 547 unsigned char max_bus_speed; /* enum pci_bus_speed */
551 unsigned char cur_bus_speed; /* enum pci_bus_speed */ 548 unsigned char cur_bus_speed; /* enum pci_bus_speed */
552#ifdef CONFIG_PCI_DOMAINS_GENERIC 549#ifdef CONFIG_PCI_DOMAINS_GENERIC
@@ -555,12 +552,12 @@ struct pci_bus {
555 552
556 char name[48]; 553 char name[48];
557 554
558 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */ 555 unsigned short bridge_ctl; /* Manage NO_ISA/FBB/et al behaviors */
559 pci_bus_flags_t bus_flags; /* inherited by child buses */ 556 pci_bus_flags_t bus_flags; /* Inherited by child buses */
560 struct device *bridge; 557 struct device *bridge;
561 struct device dev; 558 struct device dev;
562 struct bin_attribute *legacy_io; /* legacy I/O for this bus */ 559 struct bin_attribute *legacy_io; /* Legacy I/O for this bus */
563 struct bin_attribute *legacy_mem; /* legacy mem */ 560 struct bin_attribute *legacy_mem; /* Legacy mem */
564 unsigned int is_added:1; 561 unsigned int is_added:1;
565}; 562};
566 563
@@ -617,9 +614,7 @@ static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
617static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; } 614static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
618#endif 615#endif
619 616
620/* 617/* Error values that may be returned by PCI functions */
621 * Error values that may be returned by PCI functions.
622 */
623#define PCIBIOS_SUCCESSFUL 0x00 618#define PCIBIOS_SUCCESSFUL 0x00
624#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81 619#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
625#define PCIBIOS_BAD_VENDOR_ID 0x83 620#define PCIBIOS_BAD_VENDOR_ID 0x83
@@ -628,9 +623,7 @@ static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false;
628#define PCIBIOS_SET_FAILED 0x88 623#define PCIBIOS_SET_FAILED 0x88
629#define PCIBIOS_BUFFER_TOO_SMALL 0x89 624#define PCIBIOS_BUFFER_TOO_SMALL 0x89
630 625
631/* 626/* Translate above to generic errno for passing back through non-PCI code */
632 * Translate above to generic errno for passing back through non-PCI code.
633 */
634static inline int pcibios_err_to_errno(int err) 627static inline int pcibios_err_to_errno(int err)
635{ 628{
636 if (err <= PCIBIOS_SUCCESSFUL) 629 if (err <= PCIBIOS_SUCCESSFUL)
@@ -680,13 +673,13 @@ typedef u32 pci_bus_addr_t;
680#endif 673#endif
681 674
682struct pci_bus_region { 675struct pci_bus_region {
683 pci_bus_addr_t start; 676 pci_bus_addr_t start;
684 pci_bus_addr_t end; 677 pci_bus_addr_t end;
685}; 678};
686 679
687struct pci_dynids { 680struct pci_dynids {
688 spinlock_t lock; /* protects list, index */ 681 spinlock_t lock; /* Protects list, index */
689 struct list_head list; /* for IDs added at runtime */ 682 struct list_head list; /* For IDs added at runtime */
690}; 683};
691 684
692 685
@@ -700,13 +693,13 @@ struct pci_dynids {
700typedef unsigned int __bitwise pci_ers_result_t; 693typedef unsigned int __bitwise pci_ers_result_t;
701 694
702enum pci_ers_result { 695enum pci_ers_result {
703 /* no result/none/not supported in device driver */ 696 /* No result/none/not supported in device driver */
704 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1, 697 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
705 698
706 /* Device driver can recover without slot reset */ 699 /* Device driver can recover without slot reset */
707 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2, 700 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
708 701
709 /* Device driver wants slot to be reset. */ 702 /* Device driver wants slot to be reset */
710 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3, 703 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
711 704
712 /* Device has completely failed, is unrecoverable */ 705 /* Device has completely failed, is unrecoverable */
@@ -742,27 +735,27 @@ struct pci_error_handlers {
742 735
743struct module; 736struct module;
744struct pci_driver { 737struct pci_driver {
745 struct list_head node; 738 struct list_head node;
746 const char *name; 739 const char *name;
747 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */ 740 const struct pci_device_id *id_table; /* Must be non-NULL for probe to be called */
748 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */ 741 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
749 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */ 742 void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
750 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */ 743 int (*suspend)(struct pci_dev *dev, pm_message_t state); /* Device suspended */
751 int (*suspend_late) (struct pci_dev *dev, pm_message_t state); 744 int (*suspend_late)(struct pci_dev *dev, pm_message_t state);
752 int (*resume_early) (struct pci_dev *dev); 745 int (*resume_early)(struct pci_dev *dev);
753 int (*resume) (struct pci_dev *dev); /* Device woken up */ 746 int (*resume) (struct pci_dev *dev); /* Device woken up */
754 void (*shutdown) (struct pci_dev *dev); 747 void (*shutdown) (struct pci_dev *dev);
755 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */ 748 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* On PF */
756 const struct pci_error_handlers *err_handler; 749 const struct pci_error_handlers *err_handler;
757 const struct attribute_group **groups; 750 const struct attribute_group **groups;
758 struct device_driver driver; 751 struct device_driver driver;
759 struct pci_dynids dynids; 752 struct pci_dynids dynids;
760}; 753};
761 754
762#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver) 755#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
763 756
764/** 757/**
765 * PCI_DEVICE - macro used to describe a specific pci device 758 * PCI_DEVICE - macro used to describe a specific PCI device
766 * @vend: the 16 bit PCI Vendor ID 759 * @vend: the 16 bit PCI Vendor ID
767 * @dev: the 16 bit PCI Device ID 760 * @dev: the 16 bit PCI Device ID
768 * 761 *
@@ -775,7 +768,7 @@ struct pci_driver {
775 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 768 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
776 769
777/** 770/**
778 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 771 * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
779 * @vend: the 16 bit PCI Vendor ID 772 * @vend: the 16 bit PCI Vendor ID
780 * @dev: the 16 bit PCI Device ID 773 * @dev: the 16 bit PCI Device ID
781 * @subvend: the 16 bit PCI Subvendor ID 774 * @subvend: the 16 bit PCI Subvendor ID
@@ -789,7 +782,7 @@ struct pci_driver {
789 .subvendor = (subvend), .subdevice = (subdev) 782 .subvendor = (subvend), .subdevice = (subdev)
790 783
791/** 784/**
792 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 785 * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
793 * @dev_class: the class, subclass, prog-if triple for this device 786 * @dev_class: the class, subclass, prog-if triple for this device
794 * @dev_class_mask: the class mask for this device 787 * @dev_class_mask: the class mask for this device
795 * 788 *
@@ -803,7 +796,7 @@ struct pci_driver {
803 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 796 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
804 797
805/** 798/**
806 * PCI_VDEVICE - macro used to describe a specific pci device in short form 799 * PCI_VDEVICE - macro used to describe a specific PCI device in short form
807 * @vend: the vendor name 800 * @vend: the vendor name
808 * @dev: the 16 bit PCI Device ID 801 * @dev: the 16 bit PCI Device ID
809 * 802 *
@@ -812,22 +805,21 @@ struct pci_driver {
812 * to PCI_ANY_ID. The macro allows the next field to follow as the device 805 * to PCI_ANY_ID. The macro allows the next field to follow as the device
813 * private data. 806 * private data.
814 */ 807 */
815
816#define PCI_VDEVICE(vend, dev) \ 808#define PCI_VDEVICE(vend, dev) \
817 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 809 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
818 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 810 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
819 811
820enum { 812enum {
821 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */ 813 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* Ignore firmware setup */
822 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */ 814 PCI_REASSIGN_ALL_BUS = 0x00000002, /* Reassign all bus numbers */
823 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */ 815 PCI_PROBE_ONLY = 0x00000004, /* Use existing setup */
824 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */ 816 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* Don't do ISA alignment */
825 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */ 817 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* Enable domains in /proc */
826 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */ 818 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
827 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */ 819 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* Scan all, not just dev 0 */
828}; 820};
829 821
830/* these external functions are only available when PCI support is enabled */ 822/* These external functions are only available when PCI support is enabled */
831#ifdef CONFIG_PCI 823#ifdef CONFIG_PCI
832 824
833extern unsigned int pci_flags; 825extern unsigned int pci_flags;
@@ -840,11 +832,11 @@ static inline int pci_has_flag(int flag) { return pci_flags & flag; }
840void pcie_bus_configure_settings(struct pci_bus *bus); 832void pcie_bus_configure_settings(struct pci_bus *bus);
841 833
842enum pcie_bus_config_types { 834enum pcie_bus_config_types {
843 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */ 835 PCIE_BUS_TUNE_OFF, /* Don't touch MPS at all */
844 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */ 836 PCIE_BUS_DEFAULT, /* Ensure MPS matches upstream bridge */
845 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */ 837 PCIE_BUS_SAFE, /* Use largest MPS boot-time devices support */
846 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */ 838 PCIE_BUS_PERFORMANCE, /* Use MPS and MRRS for best performance */
847 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */ 839 PCIE_BUS_PEER2PEER, /* Set MPS = 128 for all devices */
848}; 840};
849 841
850extern enum pcie_bus_config_types pcie_bus_config; 842extern enum pcie_bus_config_types pcie_bus_config;
@@ -853,7 +845,7 @@ extern struct bus_type pci_bus_type;
853 845
854/* Do NOT directly access these two variables, unless you are arch-specific PCI 846/* Do NOT directly access these two variables, unless you are arch-specific PCI
855 * code, or PCI core code. */ 847 * code, or PCI core code. */
856extern struct list_head pci_root_buses; /* list of all known PCI buses */ 848extern struct list_head pci_root_buses; /* List of all known PCI buses */
857/* Some device drivers need know if PCI is initiated */ 849/* Some device drivers need know if PCI is initiated */
858int no_pci_devices(void); 850int no_pci_devices(void);
859 851
@@ -887,12 +879,13 @@ struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
887struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 879struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
888 struct pci_ops *ops, void *sysdata, 880 struct pci_ops *ops, void *sysdata,
889 struct list_head *resources); 881 struct list_head *resources);
882int pci_host_probe(struct pci_host_bridge *bridge);
890int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax); 883int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
891int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax); 884int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
892void pci_bus_release_busn_res(struct pci_bus *b); 885void pci_bus_release_busn_res(struct pci_bus *b);
893struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 886struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
894 struct pci_ops *ops, void *sysdata, 887 struct pci_ops *ops, void *sysdata,
895 struct list_head *resources); 888 struct list_head *resources);
896int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge); 889int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
897struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 890struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
898 int busnr); 891 int busnr);
@@ -949,10 +942,10 @@ int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
949struct pci_bus *pci_find_next_bus(const struct pci_bus *from); 942struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
950 943
951struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device, 944struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
952 struct pci_dev *from); 945 struct pci_dev *from);
953struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device, 946struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
954 unsigned int ss_vendor, unsigned int ss_device, 947 unsigned int ss_vendor, unsigned int ss_device,
955 struct pci_dev *from); 948 struct pci_dev *from);
956struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn); 949struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
957struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus, 950struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
958 unsigned int devfn); 951 unsigned int devfn);
@@ -1028,7 +1021,7 @@ static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1028 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0); 1021 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1029} 1022}
1030 1023
1031/* user-space driven config access */ 1024/* User-space driven config access */
1032int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 1025int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1033int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 1026int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1034int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val); 1027int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
@@ -1171,7 +1164,7 @@ unsigned int pci_rescan_bus(struct pci_bus *bus);
1171void pci_lock_rescan_remove(void); 1164void pci_lock_rescan_remove(void);
1172void pci_unlock_rescan_remove(void); 1165void pci_unlock_rescan_remove(void);
1173 1166
1174/* Vital product data routines */ 1167/* Vital Product Data routines */
1175ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf); 1168ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1176ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf); 1169ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1177int pci_set_vpd_size(struct pci_dev *dev, size_t len); 1170int pci_set_vpd_size(struct pci_dev *dev, size_t len);
@@ -1256,9 +1249,7 @@ static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1256int __must_check __pci_register_driver(struct pci_driver *, struct module *, 1249int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1257 const char *mod_name); 1250 const char *mod_name);
1258 1251
1259/* 1252/* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
1260 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1261 */
1262#define pci_register_driver(driver) \ 1253#define pci_register_driver(driver) \
1263 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) 1254 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1264 1255
@@ -1273,8 +1264,7 @@ void pci_unregister_driver(struct pci_driver *dev);
1273 * use this macro once, and calling it replaces module_init() and module_exit() 1264 * use this macro once, and calling it replaces module_init() and module_exit()
1274 */ 1265 */
1275#define module_pci_driver(__pci_driver) \ 1266#define module_pci_driver(__pci_driver) \
1276 module_driver(__pci_driver, pci_register_driver, \ 1267 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1277 pci_unregister_driver)
1278 1268
1279/** 1269/**
1280 * builtin_pci_driver() - Helper macro for registering a PCI driver 1270 * builtin_pci_driver() - Helper macro for registering a PCI driver
@@ -1313,10 +1303,10 @@ resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1313int pci_set_vga_state(struct pci_dev *pdev, bool decode, 1303int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1314 unsigned int command_bits, u32 flags); 1304 unsigned int command_bits, u32 flags);
1315 1305
1316#define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */ 1306#define PCI_IRQ_LEGACY (1 << 0) /* Allow legacy interrupts */
1317#define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */ 1307#define PCI_IRQ_MSI (1 << 1) /* Allow MSI interrupts */
1318#define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */ 1308#define PCI_IRQ_MSIX (1 << 2) /* Allow MSI-X interrupts */
1319#define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */ 1309#define PCI_IRQ_AFFINITY (1 << 3) /* Auto-assign affinity */
1320#define PCI_IRQ_ALL_TYPES \ 1310#define PCI_IRQ_ALL_TYPES \
1321 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX) 1311 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1322 1312
@@ -1335,8 +1325,8 @@ int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1335#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr) 1325#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1336 1326
1337struct msix_entry { 1327struct msix_entry {
1338 u32 vector; /* kernel uses to write allocated vector */ 1328 u32 vector; /* Kernel uses to write allocated vector */
1339 u16 entry; /* driver uses to specify entry, OS writes */ 1329 u16 entry; /* Driver uses to specify entry, OS writes */
1340}; 1330};
1341 1331
1342#ifdef CONFIG_PCI_MSI 1332#ifdef CONFIG_PCI_MSI
@@ -1376,10 +1366,10 @@ static inline int pci_msi_enabled(void) { return 0; }
1376static inline int pci_enable_msi(struct pci_dev *dev) 1366static inline int pci_enable_msi(struct pci_dev *dev)
1377{ return -ENOSYS; } 1367{ return -ENOSYS; }
1378static inline int pci_enable_msix_range(struct pci_dev *dev, 1368static inline int pci_enable_msix_range(struct pci_dev *dev,
1379 struct msix_entry *entries, int minvec, int maxvec) 1369 struct msix_entry *entries, int minvec, int maxvec)
1380{ return -ENOSYS; } 1370{ return -ENOSYS; }
1381static inline int pci_enable_msix_exact(struct pci_dev *dev, 1371static inline int pci_enable_msix_exact(struct pci_dev *dev,
1382 struct msix_entry *entries, int nvec) 1372 struct msix_entry *entries, int nvec)
1383{ return -ENOSYS; } 1373{ return -ENOSYS; }
1384 1374
1385static inline int 1375static inline int
@@ -1544,9 +1534,9 @@ static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1544int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent); 1534int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1545#endif 1535#endif
1546 1536
1547/* some architectures require additional setup to direct VGA traffic */ 1537/* Some architectures require additional setup to direct VGA traffic */
1548typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, 1538typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1549 unsigned int command_bits, u32 flags); 1539 unsigned int command_bits, u32 flags);
1550void pci_register_set_vga_state(arch_set_vga_state_t func); 1540void pci_register_set_vga_state(arch_set_vga_state_t func);
1551 1541
1552static inline int 1542static inline int
@@ -1585,10 +1575,9 @@ static inline void pci_clear_flags(int flags) { }
1585static inline int pci_has_flag(int flag) { return 0; } 1575static inline int pci_has_flag(int flag) { return 0; }
1586 1576
1587/* 1577/*
1588 * If the system does not have PCI, clearly these return errors. Define 1578 * If the system does not have PCI, clearly these return errors. Define
1589 * these as simple inline functions to avoid hair in drivers. 1579 * these as simple inline functions to avoid hair in drivers.
1590 */ 1580 */
1591
1592#define _PCI_NOP(o, s, t) \ 1581#define _PCI_NOP(o, s, t) \
1593 static inline int pci_##o##_config_##s(struct pci_dev *dev, \ 1582 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1594 int where, t val) \ 1583 int where, t val) \
@@ -1687,6 +1676,13 @@ static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1687#define dev_is_pf(d) (false) 1676#define dev_is_pf(d) (false)
1688static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags) 1677static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1689{ return false; } 1678{ return false; }
1679static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1680 struct device_node *node,
1681 const u32 *intspec,
1682 unsigned int intsize,
1683 unsigned long *out_hwirq,
1684 unsigned int *out_type)
1685{ return -EINVAL; }
1690#endif /* CONFIG_PCI */ 1686#endif /* CONFIG_PCI */
1691 1687
1692/* Include architecture-dependent settings and functions */ 1688/* Include architecture-dependent settings and functions */
@@ -1727,8 +1723,10 @@ int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1727#define pci_root_bus_fwnode(bus) NULL 1723#define pci_root_bus_fwnode(bus) NULL
1728#endif 1724#endif
1729 1725
1730/* these helpers provide future and backwards compatibility 1726/*
1731 * for accessing popular PCI BAR info */ 1727 * These helpers provide future and backwards compatibility
1728 * for accessing popular PCI BAR info
1729 */
1732#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start) 1730#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1733#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end) 1731#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1734#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags) 1732#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
@@ -1740,7 +1738,8 @@ int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1740 (pci_resource_end((dev), (bar)) - \ 1738 (pci_resource_end((dev), (bar)) - \
1741 pci_resource_start((dev), (bar)) + 1)) 1739 pci_resource_start((dev), (bar)) + 1))
1742 1740
1743/* Similar to the helpers above, these manipulate per-pci_dev 1741/*
1742 * Similar to the helpers above, these manipulate per-pci_dev
1744 * driver-specific data. They are really just a wrapper around 1743 * driver-specific data. They are really just a wrapper around
1745 * the generic device structure functions of these calls. 1744 * the generic device structure functions of these calls.
1746 */ 1745 */
@@ -1754,16 +1753,14 @@ static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1754 dev_set_drvdata(&pdev->dev, data); 1753 dev_set_drvdata(&pdev->dev, data);
1755} 1754}
1756 1755
1757/* If you want to know what to call your pci_dev, ask this function.
1758 * Again, it's a wrapper around the generic device.
1759 */
1760static inline const char *pci_name(const struct pci_dev *pdev) 1756static inline const char *pci_name(const struct pci_dev *pdev)
1761{ 1757{
1762 return dev_name(&pdev->dev); 1758 return dev_name(&pdev->dev);
1763} 1759}
1764 1760
1765 1761
1766/* Some archs don't want to expose struct resource to userland as-is 1762/*
1763 * Some archs don't want to expose struct resource to userland as-is
1767 * in sysfs and /proc 1764 * in sysfs and /proc
1768 */ 1765 */
1769#ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER 1766#ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
@@ -1782,16 +1779,16 @@ static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1782 1779
1783 1780
1784/* 1781/*
1785 * The world is not perfect and supplies us with broken PCI devices. 1782 * The world is not perfect and supplies us with broken PCI devices.
1786 * For at least a part of these bugs we need a work-around, so both 1783 * For at least a part of these bugs we need a work-around, so both
1787 * generic (drivers/pci/quirks.c) and per-architecture code can define 1784 * generic (drivers/pci/quirks.c) and per-architecture code can define
1788 * fixup hooks to be called for particular buggy devices. 1785 * fixup hooks to be called for particular buggy devices.
1789 */ 1786 */
1790 1787
1791struct pci_fixup { 1788struct pci_fixup {
1792 u16 vendor; /* You can use PCI_ANY_ID here of course */ 1789 u16 vendor; /* Or PCI_ANY_ID */
1793 u16 device; /* You can use PCI_ANY_ID here of course */ 1790 u16 device; /* Or PCI_ANY_ID */
1794 u32 class; /* You can use PCI_ANY_ID here too */ 1791 u32 class; /* Or PCI_ANY_ID */
1795 unsigned int class_shift; /* should be 0, 8, 16 */ 1792 unsigned int class_shift; /* should be 0, 8, 16 */
1796 void (*hook)(struct pci_dev *dev); 1793 void (*hook)(struct pci_dev *dev);
1797}; 1794};
@@ -1833,23 +1830,19 @@ enum pci_fixup_pass {
1833#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \ 1830#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1834 class_shift, hook) \ 1831 class_shift, hook) \
1835 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1832 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1836 resume##hook, vendor, device, class, \ 1833 resume##hook, vendor, device, class, class_shift, hook)
1837 class_shift, hook)
1838#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \ 1834#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1839 class_shift, hook) \ 1835 class_shift, hook) \
1840 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1836 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1841 resume_early##hook, vendor, device, \ 1837 resume_early##hook, vendor, device, class, class_shift, hook)
1842 class, class_shift, hook)
1843#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \ 1838#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1844 class_shift, hook) \ 1839 class_shift, hook) \
1845 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1840 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1846 suspend##hook, vendor, device, class, \ 1841 suspend##hook, vendor, device, class, class_shift, hook)
1847 class_shift, hook)
1848#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \ 1842#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1849 class_shift, hook) \ 1843 class_shift, hook) \
1850 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1844 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1851 suspend_late##hook, vendor, device, \ 1845 suspend_late##hook, vendor, device, class, class_shift, hook)
1852 class, class_shift, hook)
1853 1846
1854#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \ 1847#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1855 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \ 1848 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
@@ -1865,20 +1858,16 @@ enum pci_fixup_pass {
1865 hook, vendor, device, PCI_ANY_ID, 0, hook) 1858 hook, vendor, device, PCI_ANY_ID, 0, hook)
1866#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \ 1859#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1867 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \ 1860 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1868 resume##hook, vendor, device, \ 1861 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1869 PCI_ANY_ID, 0, hook)
1870#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \ 1862#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1871 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \ 1863 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1872 resume_early##hook, vendor, device, \ 1864 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1873 PCI_ANY_ID, 0, hook)
1874#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \ 1865#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1875 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \ 1866 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1876 suspend##hook, vendor, device, \ 1867 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1877 PCI_ANY_ID, 0, hook)
1878#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \ 1868#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1879 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \ 1869 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1880 suspend_late##hook, vendor, device, \ 1870 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1881 PCI_ANY_ID, 0, hook)
1882 1871
1883#ifdef CONFIG_PCI_QUIRKS 1872#ifdef CONFIG_PCI_QUIRKS
1884void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev); 1873void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
@@ -2064,6 +2053,7 @@ void pci_request_acs(void);
2064bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags); 2053bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2065bool pci_acs_path_enabled(struct pci_dev *start, 2054bool pci_acs_path_enabled(struct pci_dev *start,
2066 struct pci_dev *end, u16 acs_flags); 2055 struct pci_dev *end, u16 acs_flags);
2056int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2067 2057
2068#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */ 2058#define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2069#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT) 2059#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
@@ -2115,7 +2105,7 @@ static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2115 */ 2105 */
2116static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt) 2106static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2117{ 2107{
2118 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK); 2108 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2119} 2109}
2120 2110
2121/** 2111/**
@@ -2185,6 +2175,9 @@ void pci_release_of_node(struct pci_dev *dev);
2185void pci_set_bus_of_node(struct pci_bus *bus); 2175void pci_set_bus_of_node(struct pci_bus *bus);
2186void pci_release_bus_of_node(struct pci_bus *bus); 2176void pci_release_bus_of_node(struct pci_bus *bus);
2187struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus); 2177struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2178int pci_parse_request_of_pci_ranges(struct device *dev,
2179 struct list_head *resources,
2180 struct resource **bus_range);
2188 2181
2189/* Arch may override this (weak) */ 2182/* Arch may override this (weak) */
2190struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus); 2183struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
@@ -2200,7 +2193,7 @@ static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2200 return bus ? bus->dev.of_node : NULL; 2193 return bus ? bus->dev.of_node : NULL;
2201} 2194}
2202 2195
2203#else /* CONFIG_OF */ 2196#else /* CONFIG_OF */
2204static inline void pci_set_of_node(struct pci_dev *dev) { } 2197static inline void pci_set_of_node(struct pci_dev *dev) { }
2205static inline void pci_release_of_node(struct pci_dev *dev) { } 2198static inline void pci_release_of_node(struct pci_dev *dev) { }
2206static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 2199static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
@@ -2209,6 +2202,12 @@ static inline struct device_node *
2209pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; } 2202pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
2210static inline struct irq_domain * 2203static inline struct irq_domain *
2211pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; } 2204pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2205static inline int pci_parse_request_of_pci_ranges(struct device *dev,
2206 struct list_head *resources,
2207 struct resource **bus_range)
2208{
2209 return -EINVAL;
2210}
2212#endif /* CONFIG_OF */ 2211#endif /* CONFIG_OF */
2213 2212
2214#ifdef CONFIG_ACPI 2213#ifdef CONFIG_ACPI
@@ -2234,7 +2233,7 @@ int pci_for_each_dma_alias(struct pci_dev *pdev,
2234 int (*fn)(struct pci_dev *pdev, 2233 int (*fn)(struct pci_dev *pdev,
2235 u16 alias, void *data), void *data); 2234 u16 alias, void *data), void *data);
2236 2235
2237/* helper functions for operation of device flag */ 2236/* Helper functions for operation of device flag */
2238static inline void pci_set_dev_assigned(struct pci_dev *pdev) 2237static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2239{ 2238{
2240 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED; 2239 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
@@ -2317,7 +2316,19 @@ static inline void pci_uevent_ers(struct pci_dev *pdev,
2317 } 2316 }
2318} 2317}
2319 2318
2320/* provide the legacy pci_dma_* API */ 2319/* Provide the legacy pci_dma_* API */
2321#include <linux/pci-dma-compat.h> 2320#include <linux/pci-dma-compat.h>
2322 2321
2322#define pci_printk(level, pdev, fmt, arg...) \
2323 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2324
2325#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2326#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2327#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2328#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2329#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2330#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2331#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2332#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2333
2323#endif /* LINUX_PCI_H */ 2334#endif /* LINUX_PCI_H */
diff --git a/include/linux/pci_hotplug.h b/include/linux/pci_hotplug.h
index 2e855afa0212..26213024e81b 100644
--- a/include/linux/pci_hotplug.h
+++ b/include/linux/pci_hotplug.h
@@ -1,3 +1,4 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
1/* 2/*
2 * PCI HotPlug Core Functions 3 * PCI HotPlug Core Functions
3 * 4 *
@@ -7,21 +8,6 @@
7 * 8 *
8 * All rights reserved. 9 * All rights reserved.
9 * 10 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
18 * NON INFRINGEMENT. See the GNU General Public License for more
19 * details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * Send feedback to <kristen.c.accardi@intel.com> 11 * Send feedback to <kristen.c.accardi@intel.com>
26 * 12 *
27 */ 13 */
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index ab20dc5db423..eb13e84e1fef 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2381,6 +2381,8 @@
2381 2381
2382#define PCI_VENDOR_ID_LENOVO 0x17aa 2382#define PCI_VENDOR_ID_LENOVO 0x17aa
2383 2383
2384#define PCI_VENDOR_ID_CDNS 0x17cd
2385
2384#define PCI_VENDOR_ID_ARECA 0x17d3 2386#define PCI_VENDOR_ID_ARECA 0x17d3
2385#define PCI_DEVICE_ID_ARECA_1110 0x1110 2387#define PCI_DEVICE_ID_ARECA_1110 0x1110
2386#define PCI_DEVICE_ID_ARECA_1120 0x1120 2388#define PCI_DEVICE_ID_ARECA_1120 0x1120
diff --git a/include/linux/switchtec.h b/include/linux/switchtec.h
index 6d325a7a0c19..ec93e93371fa 100644
--- a/include/linux/switchtec.h
+++ b/include/linux/switchtec.h
@@ -100,6 +100,9 @@ struct sw_event_regs {
100 u32 gpio_interrupt_hdr; 100 u32 gpio_interrupt_hdr;
101 u32 gpio_interrupt_data; 101 u32 gpio_interrupt_data;
102 u32 reserved16[4]; 102 u32 reserved16[4];
103 u32 gfms_event_hdr;
104 u32 gfms_event_data;
105 u32 reserved17[4];
103} __packed; 106} __packed;
104 107
105enum { 108enum {
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 70c2b2ade048..0c79eac5e9b8 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -622,15 +622,19 @@
622 * safely. 622 * safely.
623 */ 623 */
624#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ 624#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
625#define PCI_EXP_DEVCAP2_COMP_TMOUT_DIS 0x00000010 /* Completion Timeout Disable supported */
625#define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */ 626#define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */
626#define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 /* Atomic Op routing */ 627#define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 /* Atomic Op routing */
627#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* Atomic 64-bit compare */ 628#define PCI_EXP_DEVCAP2_ATOMIC_COMP32 0x00000080 /* 32b AtomicOp completion */
629#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* 64b AtomicOp completion */
630#define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200 /* 128b AtomicOp completion */
628#define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */ 631#define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */
629#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ 632#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */
630#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ 633#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */
631#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */ 634#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
632#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ 635#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
633#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */ 636#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */
637#define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disable */
634#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ 638#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
635#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */ 639#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */
636#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */ 640#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */
@@ -966,26 +970,28 @@
966 970
967/* Downstream Port Containment */ 971/* Downstream Port Containment */
968#define PCI_EXP_DPC_CAP 4 /* DPC Capability */ 972#define PCI_EXP_DPC_CAP 4 /* DPC Capability */
969#define PCI_EXP_DPC_IRQ 0x1f /* DPC Interrupt Message Number */ 973#define PCI_EXP_DPC_IRQ 0x001F /* Interrupt Message Number */
970#define PCI_EXP_DPC_CAP_RP_EXT 0x20 /* Root Port Extensions for DPC */ 974#define PCI_EXP_DPC_CAP_RP_EXT 0x0020 /* Root Port Extensions */
971#define PCI_EXP_DPC_CAP_POISONED_TLP 0x40 /* Poisoned TLP Egress Blocking Supported */ 975#define PCI_EXP_DPC_CAP_POISONED_TLP 0x0040 /* Poisoned TLP Egress Blocking Supported */
972#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80 /* Software Triggering Supported */ 976#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x0080 /* Software Triggering Supported */
973#define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0xF00 /* RP PIO log size */ 977#define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0x0F00 /* RP PIO Log Size */
974#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */ 978#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */
975 979
976#define PCI_EXP_DPC_CTL 6 /* DPC control */ 980#define PCI_EXP_DPC_CTL 6 /* DPC control */
977#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x02 /* Enable trigger on ERR_NONFATAL message */ 981#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */
978#define PCI_EXP_DPC_CTL_INT_EN 0x08 /* DPC Interrupt Enable */ 982#define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */
979 983
980#define PCI_EXP_DPC_STATUS 8 /* DPC Status */ 984#define PCI_EXP_DPC_STATUS 8 /* DPC Status */
981#define PCI_EXP_DPC_STATUS_TRIGGER 0x01 /* Trigger Status */ 985#define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */
982#define PCI_EXP_DPC_STATUS_INTERRUPT 0x08 /* Interrupt Status */ 986#define PCI_EXP_DPC_STATUS_TRIGGER_RSN 0x0006 /* Trigger Reason */
983#define PCI_EXP_DPC_RP_BUSY 0x10 /* Root Port Busy */ 987#define PCI_EXP_DPC_STATUS_INTERRUPT 0x0008 /* Interrupt Status */
988#define PCI_EXP_DPC_RP_BUSY 0x0010 /* Root Port Busy */
989#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */
984 990
985#define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */ 991#define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */
986 992
987#define PCI_EXP_DPC_RP_PIO_STATUS 0x0C /* RP PIO Status */ 993#define PCI_EXP_DPC_RP_PIO_STATUS 0x0C /* RP PIO Status */
988#define PCI_EXP_DPC_RP_PIO_MASK 0x10 /* RP PIO MASK */ 994#define PCI_EXP_DPC_RP_PIO_MASK 0x10 /* RP PIO Mask */
989#define PCI_EXP_DPC_RP_PIO_SEVERITY 0x14 /* RP PIO Severity */ 995#define PCI_EXP_DPC_RP_PIO_SEVERITY 0x14 /* RP PIO Severity */
990#define PCI_EXP_DPC_RP_PIO_SYSERROR 0x18 /* RP PIO SysError */ 996#define PCI_EXP_DPC_RP_PIO_SYSERROR 0x18 /* RP PIO SysError */
991#define PCI_EXP_DPC_RP_PIO_EXCEPTION 0x1C /* RP PIO Exception */ 997#define PCI_EXP_DPC_RP_PIO_EXCEPTION 0x1C /* RP PIO Exception */
diff --git a/include/uapi/linux/switchtec_ioctl.h b/include/uapi/linux/switchtec_ioctl.h
index 75df44373034..4f4daf8db954 100644
--- a/include/uapi/linux/switchtec_ioctl.h
+++ b/include/uapi/linux/switchtec_ioctl.h
@@ -88,7 +88,8 @@ struct switchtec_ioctl_event_summary {
88#define SWITCHTEC_IOCTL_EVENT_FORCE_SPEED 26 88#define SWITCHTEC_IOCTL_EVENT_FORCE_SPEED 26
89#define SWITCHTEC_IOCTL_EVENT_CREDIT_TIMEOUT 27 89#define SWITCHTEC_IOCTL_EVENT_CREDIT_TIMEOUT 27
90#define SWITCHTEC_IOCTL_EVENT_LINK_STATE 28 90#define SWITCHTEC_IOCTL_EVENT_LINK_STATE 28
91#define SWITCHTEC_IOCTL_MAX_EVENTS 29 91#define SWITCHTEC_IOCTL_EVENT_GFMS 29
92#define SWITCHTEC_IOCTL_MAX_EVENTS 30
92 93
93#define SWITCHTEC_IOCTL_EVENT_LOCAL_PART_IDX -1 94#define SWITCHTEC_IOCTL_EVENT_LOCAL_PART_IDX -1
94#define SWITCHTEC_IOCTL_EVENT_IDX_ALL -2 95#define SWITCHTEC_IOCTL_EVENT_IDX_ALL -2
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-30 22:31:17 -0400