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-rw-r--r--drivers/clk/socfpga/clk-gate.c22
1 files changed, 13 insertions, 9 deletions
diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c
index aa7a6e6a15b6..73e03328d5c5 100644
--- a/drivers/clk/socfpga/clk-gate.c
+++ b/drivers/clk/socfpga/clk-gate.c
@@ -176,8 +176,7 @@ static struct clk_ops gateclk_ops = {
176 .set_parent = socfpga_clk_set_parent, 176 .set_parent = socfpga_clk_set_parent,
177}; 177};
178 178
179static void __init __socfpga_gate_init(struct device_node *node, 179void __init socfpga_gate_init(struct device_node *node)
180 const struct clk_ops *ops)
181{ 180{
182 u32 clk_gate[2]; 181 u32 clk_gate[2];
183 u32 div_reg[3]; 182 u32 div_reg[3];
@@ -188,12 +187,17 @@ static void __init __socfpga_gate_init(struct device_node *node,
188 const char *clk_name = node->name; 187 const char *clk_name = node->name;
189 const char *parent_name[SOCFPGA_MAX_PARENTS]; 188 const char *parent_name[SOCFPGA_MAX_PARENTS];
190 struct clk_init_data init; 189 struct clk_init_data init;
190 struct clk_ops *ops;
191 int rc; 191 int rc;
192 192
193 socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL); 193 socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
194 if (WARN_ON(!socfpga_clk)) 194 if (WARN_ON(!socfpga_clk))
195 return; 195 return;
196 196
197 ops = kmemdup(&gateclk_ops, sizeof(gateclk_ops), GFP_KERNEL);
198 if (WARN_ON(!ops))
199 return;
200
197 rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2); 201 rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
198 if (rc) 202 if (rc)
199 clk_gate[0] = 0; 203 clk_gate[0] = 0;
@@ -202,8 +206,8 @@ static void __init __socfpga_gate_init(struct device_node *node,
202 socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0]; 206 socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
203 socfpga_clk->hw.bit_idx = clk_gate[1]; 207 socfpga_clk->hw.bit_idx = clk_gate[1];
204 208
205 gateclk_ops.enable = clk_gate_ops.enable; 209 ops->enable = clk_gate_ops.enable;
206 gateclk_ops.disable = clk_gate_ops.disable; 210 ops->disable = clk_gate_ops.disable;
207 } 211 }
208 212
209 rc = of_property_read_u32(node, "fixed-divider", &fixed_div); 213 rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
@@ -234,6 +238,11 @@ static void __init __socfpga_gate_init(struct device_node *node,
234 init.flags = 0; 238 init.flags = 0;
235 239
236 init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS); 240 init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS);
241 if (init.num_parents < 2) {
242 ops->get_parent = NULL;
243 ops->set_parent = NULL;
244 }
245
237 init.parent_names = parent_name; 246 init.parent_names = parent_name;
238 socfpga_clk->hw.hw.init = &init; 247 socfpga_clk->hw.hw.init = &init;
239 248
@@ -246,8 +255,3 @@ static void __init __socfpga_gate_init(struct device_node *node,
246 if (WARN_ON(rc)) 255 if (WARN_ON(rc))
247 return; 256 return;
248} 257}
249
250void __init socfpga_gate_init(struct device_node *node)
251{
252 __socfpga_gate_init(node, &gateclk_ops);
253}