1 files changed, 256 insertions, 65 deletions
diff --git a/drivers/phy/phy-exynos-mipi-video.c b/drivers/phy/phy-exynos-mipi-video.c
index 2a54caba93b4..cc093ebfda94 100644
--- a/drivers/phy/phy-exynos-mipi-video.c
+++ b/drivers/phy/phy-exynos-mipi-video.c
@@ -1,7 +1,7 @@
 /*
 * Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
 *
- * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Copyright (C) 2013,2016 Samsung Electronics Co., Ltd.
 * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
 *
 * This program is free software; you can redistribute it and/or modify
@@ -13,96 +13,276 @@
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/mfd/syscon/exynos4-pmu.h>
+#include <linux/mfd/syscon/exynos5-pmu.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/of_device.h>
 #include <linux/phy/phy.h>
-#include <linux/platform_device.h>
 #include <linux/regmap.h>
 #include <linux/spinlock.h>
 #include <linux/mfd/syscon.h>
-/* MIPI_PHYn_CONTROL reg. offset (for base address from ioremap): n = 0..1 */
-#define EXYNOS_MIPI_PHY_CONTROL(n)      ((n) * 4)
 enum exynos_mipi_phy_id {
+        EXYNOS_MIPI_PHY_ID_NONE = -1,
        EXYNOS_MIPI_PHY_ID_CSIS0,
        EXYNOS_MIPI_PHY_ID_DSIM0,
        EXYNOS_MIPI_PHY_ID_CSIS1,
        EXYNOS_MIPI_PHY_ID_DSIM1,
+        EXYNOS_MIPI_PHY_ID_CSIS2,
        EXYNOS_MIPI_PHYS_NUM
 };
-#define is_mipi_dsim_phy_id(id) \
+enum exynos_mipi_phy_regmap_id {
-        ((id) == EXYNOS_MIPI_PHY_ID_DSIM0 || (id) == EXYNOS_MIPI_PHY_ID_DSIM1)
+        EXYNOS_MIPI_REGMAP_PMU,
+        EXYNOS_MIPI_REGMAP_DISP,
+        EXYNOS_MIPI_REGMAP_CAM0,
+        EXYNOS_MIPI_REGMAP_CAM1,
+        EXYNOS_MIPI_REGMAPS_NUM
+};
+struct mipi_phy_device_desc {
+        int num_phys;
+        int num_regmaps;
+        const char *regmap_names[EXYNOS_MIPI_REGMAPS_NUM];
+        struct exynos_mipi_phy_desc {
+                enum exynos_mipi_phy_id coupled_phy_id;
+                u32 enable_val;
+                unsigned int enable_reg;
+                enum exynos_mipi_phy_regmap_id enable_map;
+                u32 resetn_val;
+                unsigned int resetn_reg;
+                enum exynos_mipi_phy_regmap_id resetn_map;
+        } phys[EXYNOS_MIPI_PHYS_NUM];
+};
+static const struct mipi_phy_device_desc s5pv210_mipi_phy = {
+        .num_regmaps = 1,
+        .regmap_names = {"syscon"},
+        .num_phys = 4,
+        .phys = {
+                {
+                        /* EXYNOS_MIPI_PHY_ID_CSIS0 */
+                        .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
+                        .enable_val = EXYNOS4_MIPI_PHY_ENABLE,
+                        .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
+                        .enable_map = EXYNOS_MIPI_REGMAP_PMU,
+                        .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
+                        .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
+                        .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
+                }, {
+                        /* EXYNOS_MIPI_PHY_ID_DSIM0 */
+                        .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
+                        .enable_val = EXYNOS4_MIPI_PHY_ENABLE,
+                        .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
+                        .enable_map = EXYNOS_MIPI_REGMAP_PMU,
+                        .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
+                        .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
+                        .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
+                }, {
+                        /* EXYNOS_MIPI_PHY_ID_CSIS1 */
+                        .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
+                        .enable_val = EXYNOS4_MIPI_PHY_ENABLE,
+                        .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
+                        .enable_map = EXYNOS_MIPI_REGMAP_PMU,
+                        .resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
+                        .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
+                        .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
+                }, {
+                        /* EXYNOS_MIPI_PHY_ID_DSIM1 */
+                        .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
+                        .enable_val = EXYNOS4_MIPI_PHY_ENABLE,
+                        .enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
+                        .enable_map = EXYNOS_MIPI_REGMAP_PMU,
+                        .resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
+                        .resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
+                        .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
+                },
+        },
+};
+static const struct mipi_phy_device_desc exynos5420_mipi_phy = {
+        .num_regmaps = 1,
+        .regmap_names = {"syscon"},
+        .num_phys = 5,
+        .phys = {
+                {
+                        /* EXYNOS_MIPI_PHY_ID_CSIS0 */
+                        .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
+                        .enable_val = EXYNOS5_PHY_ENABLE,
+                        .enable_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
+                        .enable_map = EXYNOS_MIPI_REGMAP_PMU,
+                        .resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
+                        .resetn_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
+                        .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
+                }, {
+                        /* EXYNOS_MIPI_PHY_ID_DSIM0 */
+                        .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
+                        .enable_val = EXYNOS5_PHY_ENABLE,
+                        .enable_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
+                        .enable_map = EXYNOS_MIPI_REGMAP_PMU,
+                        .resetn_val = EXYNOS5_MIPI_PHY_M_RESETN,
+                        .resetn_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
+                        .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
+                }, {
+                        /* EXYNOS_MIPI_PHY_ID_CSIS1 */
+                        .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
+                        .enable_val = EXYNOS5_PHY_ENABLE,
+                        .enable_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
+                        .enable_map = EXYNOS_MIPI_REGMAP_PMU,
+                        .resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
+                        .resetn_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
+                        .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
+                }, {
+                        /* EXYNOS_MIPI_PHY_ID_DSIM1 */
+                        .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
+                        .enable_val = EXYNOS5_PHY_ENABLE,
+                        .enable_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
+                        .enable_map = EXYNOS_MIPI_REGMAP_PMU,
+                        .resetn_val = EXYNOS5_MIPI_PHY_M_RESETN,
+                        .resetn_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
+                        .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
+                }, {
+                        /* EXYNOS_MIPI_PHY_ID_CSIS2 */
+                        .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
+                        .enable_val = EXYNOS5_PHY_ENABLE,
+                        .enable_reg = EXYNOS5420_MIPI_PHY2_CONTROL,
+                        .enable_map = EXYNOS_MIPI_REGMAP_PMU,
+                        .resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
+                        .resetn_reg = EXYNOS5420_MIPI_PHY2_CONTROL,
+                        .resetn_map = EXYNOS_MIPI_REGMAP_PMU,
+                },
+        },
+};
+#define EXYNOS5433_SYSREG_DISP_MIPI_PHY         0x100C
+#define EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON    0x1014
+#define EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON    0x1020
+static const struct mipi_phy_device_desc exynos5433_mipi_phy = {
+        .num_regmaps = 4,
+        .regmap_names = {
+                "samsung,pmu-syscon",
+                "samsung,disp-sysreg",
+                "samsung,cam0-sysreg",
+                "samsung,cam1-sysreg"
+        },
+        .num_phys = 5,
+        .phys = {
+                {
+                        /* EXYNOS_MIPI_PHY_ID_CSIS0 */
+                        .coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
+                        .enable_val = EXYNOS5_PHY_ENABLE,
+                        .enable_reg = EXYNOS5433_MIPI_PHY0_CONTROL,
+                        .enable_map = EXYNOS_MIPI_REGMAP_PMU,
+                        .resetn_val = BIT(0),
+                        .resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
+                        .resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
+                }, {
+                        /* EXYNOS_MIPI_PHY_ID_DSIM0 */
+                        .coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
+                        .enable_val = EXYNOS5_PHY_ENABLE,
+                        .enable_reg = EXYNOS5433_MIPI_PHY0_CONTROL,
+                        .enable_map = EXYNOS_MIPI_REGMAP_PMU,
+                        .resetn_val = BIT(0),
+                        .resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
+                        .resetn_map = EXYNOS_MIPI_REGMAP_DISP,
+                }, {
+                        /* EXYNOS_MIPI_PHY_ID_CSIS1 */
+                        .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
+                        .enable_val = EXYNOS5_PHY_ENABLE,
+                        .enable_reg = EXYNOS5433_MIPI_PHY1_CONTROL,
+                        .enable_map = EXYNOS_MIPI_REGMAP_PMU,
+                        .resetn_val = BIT(1),
+                        .resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
+                        .resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
+                }, {
+                        /* EXYNOS_MIPI_PHY_ID_DSIM1 */
+                        .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
+                        .enable_val = EXYNOS5_PHY_ENABLE,
+                        .enable_reg = EXYNOS5433_MIPI_PHY1_CONTROL,
+                        .enable_map = EXYNOS_MIPI_REGMAP_PMU,
+                        .resetn_val = BIT(1),
+                        .resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
+                        .resetn_map = EXYNOS_MIPI_REGMAP_DISP,
+                }, {
+                        /* EXYNOS_MIPI_PHY_ID_CSIS2 */
+                        .coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
+                        .enable_val = EXYNOS5_PHY_ENABLE,
+                        .enable_reg = EXYNOS5433_MIPI_PHY2_CONTROL,
+                        .enable_map = EXYNOS_MIPI_REGMAP_PMU,
+                        .resetn_val = BIT(0),
+                        .resetn_reg = EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON,
+                        .resetn_map = EXYNOS_MIPI_REGMAP_CAM1,
+                },
+        },
+};
 struct exynos_mipi_video_phy {
+        struct regmap *regmaps[EXYNOS_MIPI_REGMAPS_NUM];
+        int num_phys;
        struct video_phy_desc {
                struct phy *phy;
                unsigned int index;
+                const struct exynos_mipi_phy_desc *data;
        } phys[EXYNOS_MIPI_PHYS_NUM];
        spinlock_t slock;
-        void __iomem *regs;
-        struct regmap *regmap;
 };
-static int __set_phy_state(struct exynos_mipi_video_phy *state,
+static inline int __is_running(const struct exynos_mipi_phy_desc *data,
-                        enum exynos_mipi_phy_id id, unsigned int on)
+                        struct exynos_mipi_video_phy *state)
 {
-        const unsigned int offset = EXYNOS4_MIPI_PHY_CONTROL(id / 2);
+        u32 val;
-        void __iomem *addr;
-        u32 val, reset;
-        if (is_mipi_dsim_phy_id(id))
+        regmap_read(state->regmaps[data->resetn_map], data->resetn_reg, &val);
-                reset = EXYNOS4_MIPI_PHY_MRESETN;
+        return val & data->resetn_val;
-        else
+}
-                reset = EXYNOS4_MIPI_PHY_SRESETN;
+static int __set_phy_state(const struct exynos_mipi_phy_desc *data,
+                           struct exynos_mipi_video_phy *state, unsigned int on)
+{
+        u32 val;
        spin_lock(&state->slock);
-        if (!IS_ERR(state->regmap)) {
+        /* disable in PMU sysreg */
-                regmap_read(state->regmap, offset, &val);
+        if (!on && data->coupled_phy_id >= 0 &&
-                if (on)
+            !__is_running(state->phys[data->coupled_phy_id].data, state)) {
-                        val |= reset;
+                regmap_read(state->regmaps[data->enable_map], data->enable_reg,
-                else
+                            &val);
-                        val &= ~reset;
+                val &= ~data->enable_val;
-                regmap_write(state->regmap, offset, val);
+                regmap_write(state->regmaps[data->enable_map], data->enable_reg,
-                if (on)
+                             val);
-                        val |= EXYNOS4_MIPI_PHY_ENABLE;
+        }
-                else if (!(val & EXYNOS4_MIPI_PHY_RESET_MASK))
-                        val &= ~EXYNOS4_MIPI_PHY_ENABLE;
+        /* PHY reset */
-                regmap_write(state->regmap, offset, val);
+        regmap_read(state->regmaps[data->resetn_map], data->resetn_reg, &val);
-        } else {
+        val = on ? (val | data->resetn_val) : (val & ~data->resetn_val);
-                addr = state->regs + EXYNOS_MIPI_PHY_CONTROL(id / 2);
+        regmap_write(state->regmaps[data->resetn_map], data->resetn_reg, val);
-                val = readl(addr);
+        /* enable in PMU sysreg */
-                if (on)
+        if (on) {
-                        val |= reset;
+                regmap_read(state->regmaps[data->enable_map], data->enable_reg,
-                else
+                            &val);
-                        val &= ~reset;
+                val |= data->enable_val;
-                writel(val, addr);
+                regmap_write(state->regmaps[data->enable_map], data->enable_reg,
-                /* Clear ENABLE bit only if MRESETN, SRESETN bits are not set */
+                             val);
-                if (on)
-                        val |= EXYNOS4_MIPI_PHY_ENABLE;
-                else if (!(val & EXYNOS4_MIPI_PHY_RESET_MASK))
-                        val &= ~EXYNOS4_MIPI_PHY_ENABLE;
-                writel(val, addr);
        }
        spin_unlock(&state->slock);
        return 0;
 }
 #define to_mipi_video_phy(desc) \
-        container_of((desc), struct exynos_mipi_video_phy, phys[(desc)->index]);
+        container_of((desc), struct exynos_mipi_video_phy, phys[(desc)->index])
 static int exynos_mipi_video_phy_power_on(struct phy *phy)
 {
        struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
        struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
-        return __set_phy_state(state, phy_desc->index, 1);
+        return __set_phy_state(phy_desc->data, state, 1);
 }
 static int exynos_mipi_video_phy_power_off(struct phy *phy)
@@ -110,7 +290,7 @@ static int exynos_mipi_video_phy_power_off(struct phy *phy)
        struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
        struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
-        return __set_phy_state(state, phy_desc->index, 0);
+        return __set_phy_state(phy_desc->data, state, 0);
 }
 static struct phy *exynos_mipi_video_phy_xlate(struct device *dev,
@@ -118,7 +298,7 @@ static struct phy *exynos_mipi_video_phy_xlate(struct device *dev,
 {
        struct exynos_mipi_video_phy *state = dev_get_drvdata(dev);
-        if (WARN_ON(args->args[0] >= EXYNOS_MIPI_PHYS_NUM))
+        if (WARN_ON(args->args[0] >= state->num_phys))
                return ERR_PTR(-ENODEV);
        return state->phys[args->args[0]].phy;
@@ -132,32 +312,33 @@ static const struct phy_ops exynos_mipi_video_phy_ops = {
 static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
 {
+        const struct mipi_phy_device_desc *phy_dev;
        struct exynos_mipi_video_phy *state;
        struct device *dev = &pdev->dev;
+        struct device_node *np = dev->of_node;
        struct phy_provider *phy_provider;
        unsigned int i;
+        phy_dev = of_device_get_match_data(dev);
+        if (!phy_dev)
+                return -ENODEV;
        state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
        if (!state)
                return -ENOMEM;
-        state->regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");
+        for (i = 0; i < phy_dev->num_regmaps; i++) {
-        if (IS_ERR(state->regmap)) {
+                state->regmaps[i] = syscon_regmap_lookup_by_phandle(np,
-                struct resource *res;
+                                                phy_dev->regmap_names[i]);
+                if (IS_ERR(state->regmaps[i]))
-                dev_info(dev, "regmap lookup failed: %ld\n",
+                        return PTR_ERR(state->regmaps[i]);
-                         PTR_ERR(state->regmap));
-                res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-                state->regs = devm_ioremap_resource(dev, res);
-                if (IS_ERR(state->regs))
-                        return PTR_ERR(state->regs);
        }
+        state->num_phys = phy_dev->num_phys;
+        spin_lock_init(&state->slock);
        dev_set_drvdata(dev, state);
-        spin_lock_init(&state->slock);
-        for (i = 0; i < EXYNOS_MIPI_PHYS_NUM; i++) {
+        for (i = 0; i < state->num_phys; i++) {
                struct phy *phy = devm_phy_create(dev, NULL,
                                                  &exynos_mipi_video_phy_ops);
                if (IS_ERR(phy)) {
@@ -167,6 +348,7 @@ static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
                state->phys[i].phy = phy;
                state->phys[i].index = i;
+                state->phys[i].data = &phy_dev->phys[i];
                phy_set_drvdata(phy, &state->phys[i]);
        }
@@ -177,8 +359,17 @@ static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
 }
 static const struct of_device_id exynos_mipi_video_phy_of_match[] = {
-        { .compatible = "samsung,s5pv210-mipi-video-phy" },
+        {
-        { },
+                .compatible = "samsung,s5pv210-mipi-video-phy",
+                .data = &s5pv210_mipi_phy,
+        }, {
+                .compatible = "samsung,exynos5420-mipi-video-phy",
+                .data = &exynos5420_mipi_phy,
+        }, {
+                .compatible = "samsung,exynos5433-mipi-video-phy",
+                .data = &exynos5433_mipi_phy,
+        },
+        { /* sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, exynos_mipi_video_phy_of_match);

diff --git a/drivers/phy/phy-exynos-mipi-video.c b/drivers/phy/phy-exynos-mipi-video.c index 2a54caba93b4..cc093ebfda94 100644 --- a/drivers/phy/phy-exynos-mipi-video.c +++ b/drivers/phy/phy-exynos-mipi-video.c
@@ -1,7 +1,7 @@
1	/*	1	/*
2	* Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver	2	* Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY driver
3	*	3	*
4	* Copyright (C) 2013 Samsung Electronics Co., Ltd.	4	* Copyright (C) 2013,2016 Samsung Electronics Co., Ltd.
5	* Author: Sylwester Nawrocki <s.nawrocki@samsung.com>	5	* Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
6	*	6	*
7	* This program is free software; you can redistribute it and/or modify	7	* This program is free software; you can redistribute it and/or modify
@@ -13,96 +13,276 @@
13	#include <linux/io.h>	13	#include <linux/io.h>
14	#include <linux/kernel.h>	14	#include <linux/kernel.h>
15	#include <linux/mfd/syscon/exynos4-pmu.h>	15	#include <linux/mfd/syscon/exynos4-pmu.h>
		16	#include <linux/mfd/syscon/exynos5-pmu.h>
16	#include <linux/module.h>	17	#include <linux/module.h>
17	#include <linux/of.h>	18	#include <linux/of.h>
18	#include <linux/of_address.h>	19	#include <linux/of_address.h>
		20	#include <linux/of_device.h>
19	#include <linux/phy/phy.h>	21	#include <linux/phy/phy.h>
20	#include <linux/platform_device.h>
21	#include <linux/regmap.h>	22	#include <linux/regmap.h>
22	#include <linux/spinlock.h>	23	#include <linux/spinlock.h>
23	#include <linux/mfd/syscon.h>	24	#include <linux/mfd/syscon.h>
24		25
25	/* MIPI_PHYn_CONTROL reg. offset (for base address from ioremap): n = 0..1 */
26	#define EXYNOS_MIPI_PHY_CONTROL(n) ((n) * 4)
27
28	enum exynos_mipi_phy_id {	26	enum exynos_mipi_phy_id {
		27	EXYNOS_MIPI_PHY_ID_NONE = -1,
29	EXYNOS_MIPI_PHY_ID_CSIS0,	28	EXYNOS_MIPI_PHY_ID_CSIS0,
30	EXYNOS_MIPI_PHY_ID_DSIM0,	29	EXYNOS_MIPI_PHY_ID_DSIM0,
31	EXYNOS_MIPI_PHY_ID_CSIS1,	30	EXYNOS_MIPI_PHY_ID_CSIS1,
32	EXYNOS_MIPI_PHY_ID_DSIM1,	31	EXYNOS_MIPI_PHY_ID_DSIM1,
		32	EXYNOS_MIPI_PHY_ID_CSIS2,
33	EXYNOS_MIPI_PHYS_NUM	33	EXYNOS_MIPI_PHYS_NUM
34	};	34	};
35		35
36	#define is_mipi_dsim_phy_id(id) \	36	enum exynos_mipi_phy_regmap_id {
37	((id) == EXYNOS_MIPI_PHY_ID_DSIM0 \|\| (id) == EXYNOS_MIPI_PHY_ID_DSIM1)	37	EXYNOS_MIPI_REGMAP_PMU,
		38	EXYNOS_MIPI_REGMAP_DISP,
		39	EXYNOS_MIPI_REGMAP_CAM0,
		40	EXYNOS_MIPI_REGMAP_CAM1,
		41	EXYNOS_MIPI_REGMAPS_NUM
		42	};
		43
		44	struct mipi_phy_device_desc {
		45	int num_phys;
		46	int num_regmaps;
		47	const char *regmap_names[EXYNOS_MIPI_REGMAPS_NUM];
		48	struct exynos_mipi_phy_desc {
		49	enum exynos_mipi_phy_id coupled_phy_id;
		50	u32 enable_val;
		51	unsigned int enable_reg;
		52	enum exynos_mipi_phy_regmap_id enable_map;
		53	u32 resetn_val;
		54	unsigned int resetn_reg;
		55	enum exynos_mipi_phy_regmap_id resetn_map;
		56	} phys[EXYNOS_MIPI_PHYS_NUM];
		57	};
		58
		59	static const struct mipi_phy_device_desc s5pv210_mipi_phy = {
		60	.num_regmaps = 1,
		61	.regmap_names = {"syscon"},
		62	.num_phys = 4,
		63	.phys = {
		64	{
		65	/* EXYNOS_MIPI_PHY_ID_CSIS0 */
		66	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
		67	.enable_val = EXYNOS4_MIPI_PHY_ENABLE,
		68	.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
		69	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
		70	.resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
		71	.resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
		72	.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
		73	}, {
		74	/* EXYNOS_MIPI_PHY_ID_DSIM0 */
		75	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
		76	.enable_val = EXYNOS4_MIPI_PHY_ENABLE,
		77	.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
		78	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
		79	.resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
		80	.resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(0),
		81	.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
		82	}, {
		83	/* EXYNOS_MIPI_PHY_ID_CSIS1 */
		84	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
		85	.enable_val = EXYNOS4_MIPI_PHY_ENABLE,
		86	.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
		87	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
		88	.resetn_val = EXYNOS4_MIPI_PHY_SRESETN,
		89	.resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
		90	.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
		91	}, {
		92	/* EXYNOS_MIPI_PHY_ID_DSIM1 */
		93	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
		94	.enable_val = EXYNOS4_MIPI_PHY_ENABLE,
		95	.enable_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
		96	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
		97	.resetn_val = EXYNOS4_MIPI_PHY_MRESETN,
		98	.resetn_reg = EXYNOS4_MIPI_PHY_CONTROL(1),
		99	.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
		100	},
		101	},
		102	};
		103
		104	static const struct mipi_phy_device_desc exynos5420_mipi_phy = {
		105	.num_regmaps = 1,
		106	.regmap_names = {"syscon"},
		107	.num_phys = 5,
		108	.phys = {
		109	{
		110	/* EXYNOS_MIPI_PHY_ID_CSIS0 */
		111	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
		112	.enable_val = EXYNOS5_PHY_ENABLE,
		113	.enable_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
		114	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
		115	.resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
		116	.resetn_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
		117	.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
		118	}, {
		119	/* EXYNOS_MIPI_PHY_ID_DSIM0 */
		120	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
		121	.enable_val = EXYNOS5_PHY_ENABLE,
		122	.enable_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
		123	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
		124	.resetn_val = EXYNOS5_MIPI_PHY_M_RESETN,
		125	.resetn_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
		126	.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
		127	}, {
		128	/* EXYNOS_MIPI_PHY_ID_CSIS1 */
		129	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
		130	.enable_val = EXYNOS5_PHY_ENABLE,
		131	.enable_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
		132	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
		133	.resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
		134	.resetn_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
		135	.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
		136	}, {
		137	/* EXYNOS_MIPI_PHY_ID_DSIM1 */
		138	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
		139	.enable_val = EXYNOS5_PHY_ENABLE,
		140	.enable_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
		141	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
		142	.resetn_val = EXYNOS5_MIPI_PHY_M_RESETN,
		143	.resetn_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
		144	.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
		145	}, {
		146	/* EXYNOS_MIPI_PHY_ID_CSIS2 */
		147	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
		148	.enable_val = EXYNOS5_PHY_ENABLE,
		149	.enable_reg = EXYNOS5420_MIPI_PHY2_CONTROL,
		150	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
		151	.resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
		152	.resetn_reg = EXYNOS5420_MIPI_PHY2_CONTROL,
		153	.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
		154	},
		155	},
		156	};
		157
		158	#define EXYNOS5433_SYSREG_DISP_MIPI_PHY 0x100C
		159	#define EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON 0x1014
		160	#define EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON 0x1020
		161
		162	static const struct mipi_phy_device_desc exynos5433_mipi_phy = {
		163	.num_regmaps = 4,
		164	.regmap_names = {
		165	"samsung,pmu-syscon",
		166	"samsung,disp-sysreg",
		167	"samsung,cam0-sysreg",
		168	"samsung,cam1-sysreg"
		169	},
		170	.num_phys = 5,
		171	.phys = {
		172	{
		173	/* EXYNOS_MIPI_PHY_ID_CSIS0 */
		174	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
		175	.enable_val = EXYNOS5_PHY_ENABLE,
		176	.enable_reg = EXYNOS5433_MIPI_PHY0_CONTROL,
		177	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
		178	.resetn_val = BIT(0),
		179	.resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
		180	.resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
		181	}, {
		182	/* EXYNOS_MIPI_PHY_ID_DSIM0 */
		183	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
		184	.enable_val = EXYNOS5_PHY_ENABLE,
		185	.enable_reg = EXYNOS5433_MIPI_PHY0_CONTROL,
		186	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
		187	.resetn_val = BIT(0),
		188	.resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
		189	.resetn_map = EXYNOS_MIPI_REGMAP_DISP,
		190	}, {
		191	/* EXYNOS_MIPI_PHY_ID_CSIS1 */
		192	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
		193	.enable_val = EXYNOS5_PHY_ENABLE,
		194	.enable_reg = EXYNOS5433_MIPI_PHY1_CONTROL,
		195	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
		196	.resetn_val = BIT(1),
		197	.resetn_reg = EXYNOS5433_SYSREG_CAM0_MIPI_DPHY_CON,
		198	.resetn_map = EXYNOS_MIPI_REGMAP_CAM0,
		199	}, {
		200	/* EXYNOS_MIPI_PHY_ID_DSIM1 */
		201	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
		202	.enable_val = EXYNOS5_PHY_ENABLE,
		203	.enable_reg = EXYNOS5433_MIPI_PHY1_CONTROL,
		204	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
		205	.resetn_val = BIT(1),
		206	.resetn_reg = EXYNOS5433_SYSREG_DISP_MIPI_PHY,
		207	.resetn_map = EXYNOS_MIPI_REGMAP_DISP,
		208	}, {
		209	/* EXYNOS_MIPI_PHY_ID_CSIS2 */
		210	.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
		211	.enable_val = EXYNOS5_PHY_ENABLE,
		212	.enable_reg = EXYNOS5433_MIPI_PHY2_CONTROL,
		213	.enable_map = EXYNOS_MIPI_REGMAP_PMU,
		214	.resetn_val = BIT(0),
		215	.resetn_reg = EXYNOS5433_SYSREG_CAM1_MIPI_DPHY_CON,
		216	.resetn_map = EXYNOS_MIPI_REGMAP_CAM1,
		217	},
		218	},
		219	};
38		220
39	struct exynos_mipi_video_phy {	221	struct exynos_mipi_video_phy {
		222	struct regmap *regmaps[EXYNOS_MIPI_REGMAPS_NUM];
		223	int num_phys;
40	struct video_phy_desc {	224	struct video_phy_desc {
41	struct phy *phy;	225	struct phy *phy;
42	unsigned int index;	226	unsigned int index;
		227	const struct exynos_mipi_phy_desc *data;
43	} phys[EXYNOS_MIPI_PHYS_NUM];	228	} phys[EXYNOS_MIPI_PHYS_NUM];
44	spinlock_t slock;	229	spinlock_t slock;
45	void __iomem *regs;
46	struct regmap *regmap;
47	};	230	};
48		231
49	static int __set_phy_state(struct exynos_mipi_video_phy *state,	232	static inline int __is_running(const struct exynos_mipi_phy_desc *data,
50	enum exynos_mipi_phy_id id, unsigned int on)	233	struct exynos_mipi_video_phy *state)
51	{	234	{
52	const unsigned int offset = EXYNOS4_MIPI_PHY_CONTROL(id / 2);	235	u32 val;
53	void __iomem *addr;
54	u32 val, reset;
55		236
56	if (is_mipi_dsim_phy_id(id))	237	regmap_read(state->regmaps[data->resetn_map], data->resetn_reg, &val);
57	reset = EXYNOS4_MIPI_PHY_MRESETN;	238	return val & data->resetn_val;
58	else	239	}
59	reset = EXYNOS4_MIPI_PHY_SRESETN;	240
		241	static int __set_phy_state(const struct exynos_mipi_phy_desc *data,
		242	struct exynos_mipi_video_phy *state, unsigned int on)
		243	{
		244	u32 val;
60		245
61	spin_lock(&state->slock);	246	spin_lock(&state->slock);
62		247
63	if (!IS_ERR(state->regmap)) {	248	/* disable in PMU sysreg */
64	regmap_read(state->regmap, offset, &val);	249	if (!on && data->coupled_phy_id >= 0 &&
65	if (on)	250	!__is_running(state->phys[data->coupled_phy_id].data, state)) {
66	val \|= reset;	251	regmap_read(state->regmaps[data->enable_map], data->enable_reg,
67	else	252	&val);
68	val &= ~reset;	253	val &= ~data->enable_val;
69	regmap_write(state->regmap, offset, val);	254	regmap_write(state->regmaps[data->enable_map], data->enable_reg,
70	if (on)	255	val);
71	val \|= EXYNOS4_MIPI_PHY_ENABLE;	256	}
72	else if (!(val & EXYNOS4_MIPI_PHY_RESET_MASK))	257
73	val &= ~EXYNOS4_MIPI_PHY_ENABLE;	258	/* PHY reset */
74	regmap_write(state->regmap, offset, val);	259	regmap_read(state->regmaps[data->resetn_map], data->resetn_reg, &val);
75	} else {	260	val = on ? (val \| data->resetn_val) : (val & ~data->resetn_val);
76	addr = state->regs + EXYNOS_MIPI_PHY_CONTROL(id / 2);	261	regmap_write(state->regmaps[data->resetn_map], data->resetn_reg, val);
77		262
78	val = readl(addr);	263	/* enable in PMU sysreg */
79	if (on)	264	if (on) {
80	val \|= reset;	265	regmap_read(state->regmaps[data->enable_map], data->enable_reg,
81	else	266	&val);
82	val &= ~reset;	267	val \|= data->enable_val;
83	writel(val, addr);	268	regmap_write(state->regmaps[data->enable_map], data->enable_reg,
84	/* Clear ENABLE bit only if MRESETN, SRESETN bits are not set */	269	val);
85	if (on)
86	val \|= EXYNOS4_MIPI_PHY_ENABLE;
87	else if (!(val & EXYNOS4_MIPI_PHY_RESET_MASK))
88	val &= ~EXYNOS4_MIPI_PHY_ENABLE;
89
90	writel(val, addr);
91	}	270	}
92		271
93	spin_unlock(&state->slock);	272	spin_unlock(&state->slock);
		273
94	return 0;	274	return 0;
95	}	275	}
96		276
97	#define to_mipi_video_phy(desc) \	277	#define to_mipi_video_phy(desc) \
98	container_of((desc), struct exynos_mipi_video_phy, phys[(desc)->index]);	278	container_of((desc), struct exynos_mipi_video_phy, phys[(desc)->index])
99		279
100	static int exynos_mipi_video_phy_power_on(struct phy *phy)	280	static int exynos_mipi_video_phy_power_on(struct phy *phy)
101	{	281	{
102	struct video_phy_desc *phy_desc = phy_get_drvdata(phy);	282	struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
103	struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);	283	struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
104		284
105	return __set_phy_state(state, phy_desc->index, 1);	285	return __set_phy_state(phy_desc->data, state, 1);
106	}	286	}
107		287
108	static int exynos_mipi_video_phy_power_off(struct phy *phy)	288	static int exynos_mipi_video_phy_power_off(struct phy *phy)
@@ -110,7 +290,7 @@ static int exynos_mipi_video_phy_power_off(struct phy *phy)
110	struct video_phy_desc *phy_desc = phy_get_drvdata(phy);	290	struct video_phy_desc *phy_desc = phy_get_drvdata(phy);
111	struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);	291	struct exynos_mipi_video_phy *state = to_mipi_video_phy(phy_desc);
112		292
113	return __set_phy_state(state, phy_desc->index, 0);	293	return __set_phy_state(phy_desc->data, state, 0);
114	}	294	}
115		295
116	static struct phy exynos_mipi_video_phy_xlate(struct device dev,	296	static struct phy exynos_mipi_video_phy_xlate(struct device dev,
@@ -118,7 +298,7 @@ static struct phy exynos_mipi_video_phy_xlate(struct device dev,
118	{	298	{
119	struct exynos_mipi_video_phy *state = dev_get_drvdata(dev);	299	struct exynos_mipi_video_phy *state = dev_get_drvdata(dev);
120		300
121	if (WARN_ON(args->args[0] >= EXYNOS_MIPI_PHYS_NUM))	301	if (WARN_ON(args->args[0] >= state->num_phys))
122	return ERR_PTR(-ENODEV);	302	return ERR_PTR(-ENODEV);
123		303
124	return state->phys[args->args[0]].phy;	304	return state->phys[args->args[0]].phy;
@@ -132,32 +312,33 @@ static const struct phy_ops exynos_mipi_video_phy_ops = {
132		312
133	static int exynos_mipi_video_phy_probe(struct platform_device *pdev)	313	static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
134	{	314	{
		315	const struct mipi_phy_device_desc *phy_dev;
135	struct exynos_mipi_video_phy *state;	316	struct exynos_mipi_video_phy *state;
136	struct device *dev = &pdev->dev;	317	struct device *dev = &pdev->dev;
		318	struct device_node *np = dev->of_node;
137	struct phy_provider *phy_provider;	319	struct phy_provider *phy_provider;
138	unsigned int i;	320	unsigned int i;
139		321
		322	phy_dev = of_device_get_match_data(dev);
		323	if (!phy_dev)
		324	return -ENODEV;
		325
140	state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);	326	state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
141	if (!state)	327	if (!state)
142	return -ENOMEM;	328	return -ENOMEM;
143		329
144	state->regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");	330	for (i = 0; i < phy_dev->num_regmaps; i++) {
145	if (IS_ERR(state->regmap)) {	331	state->regmaps[i] = syscon_regmap_lookup_by_phandle(np,
146	struct resource *res;	332	phy_dev->regmap_names[i]);
147		333	if (IS_ERR(state->regmaps[i]))
148	dev_info(dev, "regmap lookup failed: %ld\n",	334	return PTR_ERR(state->regmaps[i]);
149	PTR_ERR(state->regmap));
150
151	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
152	state->regs = devm_ioremap_resource(dev, res);
153	if (IS_ERR(state->regs))
154	return PTR_ERR(state->regs);
155	}	335	}
		336	state->num_phys = phy_dev->num_phys;
		337	spin_lock_init(&state->slock);
156		338
157	dev_set_drvdata(dev, state);	339	dev_set_drvdata(dev, state);
158	spin_lock_init(&state->slock);
159		340
160	for (i = 0; i < EXYNOS_MIPI_PHYS_NUM; i++) {	341	for (i = 0; i < state->num_phys; i++) {
161	struct phy *phy = devm_phy_create(dev, NULL,	342	struct phy *phy = devm_phy_create(dev, NULL,
162	&exynos_mipi_video_phy_ops);	343	&exynos_mipi_video_phy_ops);
163	if (IS_ERR(phy)) {	344	if (IS_ERR(phy)) {
@@ -167,6 +348,7 @@ static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
167		348
168	state->phys[i].phy = phy;	349	state->phys[i].phy = phy;
169	state->phys[i].index = i;	350	state->phys[i].index = i;
		351	state->phys[i].data = &phy_dev->phys[i];
170	phy_set_drvdata(phy, &state->phys[i]);	352	phy_set_drvdata(phy, &state->phys[i]);
171	}	353	}
172		354
@@ -177,8 +359,17 @@ static int exynos_mipi_video_phy_probe(struct platform_device *pdev)
177	}	359	}
178		360
179	static const struct of_device_id exynos_mipi_video_phy_of_match[] = {	361	static const struct of_device_id exynos_mipi_video_phy_of_match[] = {
180	{ .compatible = "samsung,s5pv210-mipi-video-phy" },	362	{
181	{ },	363	.compatible = "samsung,s5pv210-mipi-video-phy",
		364	.data = &s5pv210_mipi_phy,
		365	}, {
		366	.compatible = "samsung,exynos5420-mipi-video-phy",
		367	.data = &exynos5420_mipi_phy,
		368	}, {
		369	.compatible = "samsung,exynos5433-mipi-video-phy",
		370	.data = &exynos5433_mipi_phy,
		371	},
		372	{ /* sentinel */ },
182	};	373	};
183	MODULE_DEVICE_TABLE(of, exynos_mipi_video_phy_of_match);	374	MODULE_DEVICE_TABLE(of, exynos_mipi_video_phy_of_match);
184		375