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Diffstat (limited to 'drivers/pci/quirks.c')
-rw-r--r--drivers/pci/quirks.c89
1 files changed, 89 insertions, 0 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 6967c6b4cf6b..140760403f36 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -4016,6 +4016,95 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
4016 quirk_tw686x_class); 4016 quirk_tw686x_class);
4017 4017
4018/* 4018/*
4019 * Some devices have problems with Transaction Layer Packets with the Relaxed
4020 * Ordering Attribute set. Such devices should mark themselves and other
4021 * Device Drivers should check before sending TLPs with RO set.
4022 */
4023static void quirk_relaxedordering_disable(struct pci_dev *dev)
4024{
4025 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
4026 dev_info(&dev->dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
4027}
4028
4029/*
4030 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root
4031 * Complex has a Flow Control Credit issue which can cause performance
4032 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set.
4033 */
4034DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
4035 quirk_relaxedordering_disable);
4036DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
4037 quirk_relaxedordering_disable);
4038DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
4039 quirk_relaxedordering_disable);
4040DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
4041 quirk_relaxedordering_disable);
4042DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
4043 quirk_relaxedordering_disable);
4044DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
4045 quirk_relaxedordering_disable);
4046DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
4047 quirk_relaxedordering_disable);
4048DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
4049 quirk_relaxedordering_disable);
4050DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
4051 quirk_relaxedordering_disable);
4052DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
4053 quirk_relaxedordering_disable);
4054DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
4055 quirk_relaxedordering_disable);
4056DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
4057 quirk_relaxedordering_disable);
4058DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
4059 quirk_relaxedordering_disable);
4060DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
4061 quirk_relaxedordering_disable);
4062DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
4063 quirk_relaxedordering_disable);
4064DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
4065 quirk_relaxedordering_disable);
4066DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
4067 quirk_relaxedordering_disable);
4068DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
4069 quirk_relaxedordering_disable);
4070DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
4071 quirk_relaxedordering_disable);
4072DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
4073 quirk_relaxedordering_disable);
4074DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
4075 quirk_relaxedordering_disable);
4076DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
4077 quirk_relaxedordering_disable);
4078DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
4079 quirk_relaxedordering_disable);
4080DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
4081 quirk_relaxedordering_disable);
4082DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
4083 quirk_relaxedordering_disable);
4084DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
4085 quirk_relaxedordering_disable);
4086DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
4087 quirk_relaxedordering_disable);
4088DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
4089 quirk_relaxedordering_disable);
4090
4091/*
4092 * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex
4093 * where Upstream Transaction Layer Packets with the Relaxed Ordering
4094 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
4095 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
4096 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
4097 * November 10, 2010). As a result, on this platform we can't use Relaxed
4098 * Ordering for Upstream TLPs.
4099 */
4100DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
4101 quirk_relaxedordering_disable);
4102DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
4103 quirk_relaxedordering_disable);
4104DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
4105 quirk_relaxedordering_disable);
4106
4107/*
4019 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4108 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4020 * values for the Attribute as were supplied in the header of the 4109 * values for the Attribute as were supplied in the header of the
4021 * corresponding Request, except as explicitly allowed when IDO is used." 4110 * corresponding Request, except as explicitly allowed when IDO is used."
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-29 09:54:59 -0400