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-rw-r--r--drivers/mtd/devices/Kconfig16
-rw-r--r--drivers/mtd/devices/Makefile2
-rw-r--r--drivers/mtd/devices/doc2000.c2
-rw-r--r--drivers/mtd/devices/doc2001.c2
-rw-r--r--drivers/mtd/devices/doc2001plus.c2
-rw-r--r--drivers/mtd/devices/m25p80.c582
-rw-r--r--drivers/mtd/devices/mtd_dataflash.c629
7 files changed, 1232 insertions, 3 deletions
diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig
index 9a2aa4033c6a..5038e90ceb12 100644
--- a/drivers/mtd/devices/Kconfig
+++ b/drivers/mtd/devices/Kconfig
@@ -47,6 +47,22 @@ config MTD_MS02NV
47 accelerator. Say Y here if you have a DECstation 5000/2x0 or a 47 accelerator. Say Y here if you have a DECstation 5000/2x0 or a
48 DECsystem 5900 equipped with such a module. 48 DECsystem 5900 equipped with such a module.
49 49
50config MTD_DATAFLASH
51 tristate "Support for AT45xxx DataFlash"
52 depends on MTD && SPI_MASTER && EXPERIMENTAL
53 help
54 This enables access to AT45xxx DataFlash chips, using SPI.
55 Sometimes DataFlash chips are packaged inside MMC-format
56 cards; at this writing, the MMC stack won't handle those.
57
58config MTD_M25P80
59 tristate "Support for M25 SPI Flash"
60 depends on MTD && SPI_MASTER && EXPERIMENTAL
61 help
62 This enables access to ST M25P80 and similar SPI flash chips,
63 used for program and data storage. Set up your spi devices
64 with the right board-specific platform data.
65
50config MTD_SLRAM 66config MTD_SLRAM
51 tristate "Uncached system RAM" 67 tristate "Uncached system RAM"
52 depends on MTD 68 depends on MTD
diff --git a/drivers/mtd/devices/Makefile b/drivers/mtd/devices/Makefile
index e38db348057d..7c5ed2178380 100644
--- a/drivers/mtd/devices/Makefile
+++ b/drivers/mtd/devices/Makefile
@@ -23,3 +23,5 @@ obj-$(CONFIG_MTD_MTDRAM) += mtdram.o
23obj-$(CONFIG_MTD_LART) += lart.o 23obj-$(CONFIG_MTD_LART) += lart.o
24obj-$(CONFIG_MTD_BLKMTD) += blkmtd.o 24obj-$(CONFIG_MTD_BLKMTD) += blkmtd.o
25obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd.o 25obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd.o
26obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o
27obj-$(CONFIG_MTD_M25P80) += m25p80.o
diff --git a/drivers/mtd/devices/doc2000.c b/drivers/mtd/devices/doc2000.c
index be5e88b3888d..e4345cf744a2 100644
--- a/drivers/mtd/devices/doc2000.c
+++ b/drivers/mtd/devices/doc2000.c
@@ -138,7 +138,7 @@ static inline int DoC_WaitReady(struct DiskOnChip *doc)
138 bypass the internal pipeline. Each of 4 delay cycles (read from the NOP register) is 138 bypass the internal pipeline. Each of 4 delay cycles (read from the NOP register) is
139 required after writing to CDSN Control register, see Software Requirement 11.4 item 3. */ 139 required after writing to CDSN Control register, see Software Requirement 11.4 item 3. */
140 140
141static inline int DoC_Command(struct DiskOnChip *doc, unsigned char command, 141static int DoC_Command(struct DiskOnChip *doc, unsigned char command,
142 unsigned char xtraflags) 142 unsigned char xtraflags)
143{ 143{
144 void __iomem *docptr = doc->virtadr; 144 void __iomem *docptr = doc->virtadr;
diff --git a/drivers/mtd/devices/doc2001.c b/drivers/mtd/devices/doc2001.c
index fcb28a6fd89f..681a9c73a2a3 100644
--- a/drivers/mtd/devices/doc2001.c
+++ b/drivers/mtd/devices/doc2001.c
@@ -103,7 +103,7 @@ static inline int DoC_WaitReady(void __iomem * docptr)
103 with the internal pipeline. Each of 4 delay cycles (read from the NOP register) is 103 with the internal pipeline. Each of 4 delay cycles (read from the NOP register) is
104 required after writing to CDSN Control register, see Software Requirement 11.4 item 3. */ 104 required after writing to CDSN Control register, see Software Requirement 11.4 item 3. */
105 105
106static inline void DoC_Command(void __iomem * docptr, unsigned char command, 106static void DoC_Command(void __iomem * docptr, unsigned char command,
107 unsigned char xtraflags) 107 unsigned char xtraflags)
108{ 108{
109 /* Assert the CLE (Command Latch Enable) line to the flash chip */ 109 /* Assert the CLE (Command Latch Enable) line to the flash chip */
diff --git a/drivers/mtd/devices/doc2001plus.c b/drivers/mtd/devices/doc2001plus.c
index 0595cc7324b2..5f57f29efee4 100644
--- a/drivers/mtd/devices/doc2001plus.c
+++ b/drivers/mtd/devices/doc2001plus.c
@@ -118,7 +118,7 @@ static inline void DoC_CheckASIC(void __iomem * docptr)
118/* DoC_Command: Send a flash command to the flash chip through the Flash 118/* DoC_Command: Send a flash command to the flash chip through the Flash
119 * command register. Need 2 Write Pipeline Terminates to complete send. 119 * command register. Need 2 Write Pipeline Terminates to complete send.
120 */ 120 */
121static inline void DoC_Command(void __iomem * docptr, unsigned char command, 121static void DoC_Command(void __iomem * docptr, unsigned char command,
122 unsigned char xtraflags) 122 unsigned char xtraflags)
123{ 123{
124 WriteDOC(command, docptr, Mplus_FlashCmd); 124 WriteDOC(command, docptr, Mplus_FlashCmd);
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
new file mode 100644
index 000000000000..d5f24089be71
--- /dev/null
+++ b/drivers/mtd/devices/m25p80.c
@@ -0,0 +1,582 @@
1/*
2 * MTD SPI driver for ST M25Pxx flash chips
3 *
4 * Author: Mike Lavender, mike@steroidmicros.com
5 *
6 * Copyright (c) 2005, Intec Automation Inc.
7 *
8 * Some parts are based on lart.c by Abraham Van Der Merwe
9 *
10 * Cleaned up and generalized based on mtd_dataflash.c
11 *
12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
21#include <linux/interrupt.h>
22#include <linux/interrupt.h>
23#include <linux/mtd/mtd.h>
24#include <linux/mtd/partitions.h>
25#include <linux/spi/spi.h>
26#include <linux/spi/flash.h>
27
28#include <asm/semaphore.h>
29
30
31/* NOTE: AT 25F and SST 25LF series are very similar,
32 * but commands for sector erase and chip id differ...
33 */
34
35#define FLASH_PAGESIZE 256
36
37/* Flash opcodes. */
38#define OPCODE_WREN 6 /* Write enable */
39#define OPCODE_RDSR 5 /* Read status register */
40#define OPCODE_READ 3 /* Read data bytes */
41#define OPCODE_PP 2 /* Page program */
42#define OPCODE_SE 0xd8 /* Sector erase */
43#define OPCODE_RES 0xab /* Read Electronic Signature */
44#define OPCODE_RDID 0x9f /* Read JEDEC ID */
45
46/* Status Register bits. */
47#define SR_WIP 1 /* Write in progress */
48#define SR_WEL 2 /* Write enable latch */
49#define SR_BP0 4 /* Block protect 0 */
50#define SR_BP1 8 /* Block protect 1 */
51#define SR_BP2 0x10 /* Block protect 2 */
52#define SR_SRWD 0x80 /* SR write protect */
53
54/* Define max times to check status register before we give up. */
55#define MAX_READY_WAIT_COUNT 100000
56
57
58#ifdef CONFIG_MTD_PARTITIONS
59#define mtd_has_partitions() (1)
60#else
61#define mtd_has_partitions() (0)
62#endif
63
64/****************************************************************************/
65
66struct m25p {
67 struct spi_device *spi;
68 struct semaphore lock;
69 struct mtd_info mtd;
70 unsigned partitioned;
71 u8 command[4];
72};
73
74static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
75{
76 return container_of(mtd, struct m25p, mtd);
77}
78
79/****************************************************************************/
80
81/*
82 * Internal helper functions
83 */
84
85/*
86 * Read the status register, returning its value in the location
87 * Return the status register value.
88 * Returns negative if error occurred.
89 */
90static int read_sr(struct m25p *flash)
91{
92 ssize_t retval;
93 u8 code = OPCODE_RDSR;
94 u8 val;
95
96 retval = spi_write_then_read(flash->spi, &code, 1, &val, 1);
97
98 if (retval < 0) {
99 dev_err(&flash->spi->dev, "error %d reading SR\n",
100 (int) retval);
101 return retval;
102 }
103
104 return val;
105}
106
107
108/*
109 * Set write enable latch with Write Enable command.
110 * Returns negative if error occurred.
111 */
112static inline int write_enable(struct m25p *flash)
113{
114 u8 code = OPCODE_WREN;
115
116 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
117}
118
119
120/*
121 * Service routine to read status register until ready, or timeout occurs.
122 * Returns non-zero if error.
123 */
124static int wait_till_ready(struct m25p *flash)
125{
126 int count;
127 int sr;
128
129 /* one chip guarantees max 5 msec wait here after page writes,
130 * but potentially three seconds (!) after page erase.
131 */
132 for (count = 0; count < MAX_READY_WAIT_COUNT; count++) {
133 if ((sr = read_sr(flash)) < 0)
134 break;
135 else if (!(sr & SR_WIP))
136 return 0;
137
138 /* REVISIT sometimes sleeping would be best */
139 }
140
141 return 1;
142}
143
144
145/*
146 * Erase one sector of flash memory at offset ``offset'' which is any
147 * address within the sector which should be erased.
148 *
149 * Returns 0 if successful, non-zero otherwise.
150 */
151static int erase_sector(struct m25p *flash, u32 offset)
152{
153 DEBUG(MTD_DEBUG_LEVEL3, "%s: %s at 0x%08x\n", flash->spi->dev.bus_id,
154 __FUNCTION__, offset);
155
156 /* Wait until finished previous write command. */
157 if (wait_till_ready(flash))
158 return 1;
159
160 /* Send write enable, then erase commands. */
161 write_enable(flash);
162
163 /* Set up command buffer. */
164 flash->command[0] = OPCODE_SE;
165 flash->command[1] = offset >> 16;
166 flash->command[2] = offset >> 8;
167 flash->command[3] = offset;
168
169 spi_write(flash->spi, flash->command, sizeof(flash->command));
170
171 return 0;
172}
173
174/****************************************************************************/
175
176/*
177 * MTD implementation
178 */
179
180/*
181 * Erase an address range on the flash chip. The address range may extend
182 * one or more erase sectors. Return an error is there is a problem erasing.
183 */
184static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
185{
186 struct m25p *flash = mtd_to_m25p(mtd);
187 u32 addr,len;
188
189 DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n",
190 flash->spi->dev.bus_id, __FUNCTION__, "at",
191 (u32)instr->addr, instr->len);
192
193 /* sanity checks */
194 if (instr->addr + instr->len > flash->mtd.size)
195 return -EINVAL;
196 if ((instr->addr % mtd->erasesize) != 0
197 || (instr->len % mtd->erasesize) != 0) {
198 return -EINVAL;
199 }
200
201 addr = instr->addr;
202 len = instr->len;
203
204 down(&flash->lock);
205
206 /* now erase those sectors */
207 while (len) {
208 if (erase_sector(flash, addr)) {
209 instr->state = MTD_ERASE_FAILED;
210 up(&flash->lock);
211 return -EIO;
212 }
213
214 addr += mtd->erasesize;
215 len -= mtd->erasesize;
216 }
217
218 up(&flash->lock);
219
220 instr->state = MTD_ERASE_DONE;
221 mtd_erase_callback(instr);
222
223 return 0;
224}
225
226/*
227 * Read an address range from the flash chip. The address range
228 * may be any size provided it is within the physical boundaries.
229 */
230static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
231 size_t *retlen, u_char *buf)
232{
233 struct m25p *flash = mtd_to_m25p(mtd);
234 struct spi_transfer t[2];
235 struct spi_message m;
236
237 DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n",
238 flash->spi->dev.bus_id, __FUNCTION__, "from",
239 (u32)from, len);
240
241 /* sanity checks */
242 if (!len)
243 return 0;
244
245 if (from + len > flash->mtd.size)
246 return -EINVAL;
247
248 spi_message_init(&m);
249 memset(t, 0, (sizeof t));
250
251 t[0].tx_buf = flash->command;
252 t[0].len = sizeof(flash->command);
253 spi_message_add_tail(&t[0], &m);
254
255 t[1].rx_buf = buf;
256 t[1].len = len;
257 spi_message_add_tail(&t[1], &m);
258
259 /* Byte count starts at zero. */
260 if (retlen)
261 *retlen = 0;
262
263 down(&flash->lock);
264
265 /* Wait till previous write/erase is done. */
266 if (wait_till_ready(flash)) {
267 /* REVISIT status return?? */
268 up(&flash->lock);
269 return 1;
270 }
271
272 /* NOTE: OPCODE_FAST_READ (if available) is faster... */
273
274 /* Set up the write data buffer. */
275 flash->command[0] = OPCODE_READ;
276 flash->command[1] = from >> 16;
277 flash->command[2] = from >> 8;
278 flash->command[3] = from;
279
280 spi_sync(flash->spi, &m);
281
282 *retlen = m.actual_length - sizeof(flash->command);
283
284 up(&flash->lock);
285
286 return 0;
287}
288
289/*
290 * Write an address range to the flash chip. Data must be written in
291 * FLASH_PAGESIZE chunks. The address range may be any size provided
292 * it is within the physical boundaries.
293 */
294static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
295 size_t *retlen, const u_char *buf)
296{
297 struct m25p *flash = mtd_to_m25p(mtd);
298 u32 page_offset, page_size;
299 struct spi_transfer t[2];
300 struct spi_message m;
301
302 DEBUG(MTD_DEBUG_LEVEL2, "%s: %s %s 0x%08x, len %zd\n",
303 flash->spi->dev.bus_id, __FUNCTION__, "to",
304 (u32)to, len);
305
306 if (retlen)
307 *retlen = 0;
308
309 /* sanity checks */
310 if (!len)
311 return(0);
312
313 if (to + len > flash->mtd.size)
314 return -EINVAL;
315
316 spi_message_init(&m);
317 memset(t, 0, (sizeof t));
318
319 t[0].tx_buf = flash->command;
320 t[0].len = sizeof(flash->command);
321 spi_message_add_tail(&t[0], &m);
322
323 t[1].tx_buf = buf;
324 spi_message_add_tail(&t[1], &m);
325
326 down(&flash->lock);
327
328 /* Wait until finished previous write command. */
329 if (wait_till_ready(flash))
330 return 1;
331
332 write_enable(flash);
333
334 /* Set up the opcode in the write buffer. */
335 flash->command[0] = OPCODE_PP;
336 flash->command[1] = to >> 16;
337 flash->command[2] = to >> 8;
338 flash->command[3] = to;
339
340 /* what page do we start with? */
341 page_offset = to % FLASH_PAGESIZE;
342
343 /* do all the bytes fit onto one page? */
344 if (page_offset + len <= FLASH_PAGESIZE) {
345 t[1].len = len;
346
347 spi_sync(flash->spi, &m);
348
349 *retlen = m.actual_length - sizeof(flash->command);
350 } else {
351 u32 i;
352
353 /* the size of data remaining on the first page */
354 page_size = FLASH_PAGESIZE - page_offset;
355
356 t[1].len = page_size;
357 spi_sync(flash->spi, &m);
358
359 *retlen = m.actual_length - sizeof(flash->command);
360
361 /* write everything in PAGESIZE chunks */
362 for (i = page_size; i < len; i += page_size) {
363 page_size = len - i;
364 if (page_size > FLASH_PAGESIZE)
365 page_size = FLASH_PAGESIZE;
366
367 /* write the next page to flash */
368 flash->command[1] = (to + i) >> 16;
369 flash->command[2] = (to + i) >> 8;
370 flash->command[3] = (to + i);
371
372 t[1].tx_buf = buf + i;
373 t[1].len = page_size;
374
375 wait_till_ready(flash);
376
377 write_enable(flash);
378
379 spi_sync(flash->spi, &m);
380
381 if (retlen)
382 *retlen += m.actual_length
383 - sizeof(flash->command);
384 }
385 }
386
387 up(&flash->lock);
388
389 return 0;
390}
391
392
393/****************************************************************************/
394
395/*
396 * SPI device driver setup and teardown
397 */
398
399struct flash_info {
400 char *name;
401 u8 id;
402 u16 jedec_id;
403 unsigned sector_size;
404 unsigned n_sectors;
405};
406
407static struct flash_info __devinitdata m25p_data [] = {
408 /* REVISIT: fill in JEDEC ids, for parts that have them */
409 { "m25p05", 0x05, 0x0000, 32 * 1024, 2 },
410 { "m25p10", 0x10, 0x0000, 32 * 1024, 4 },
411 { "m25p20", 0x11, 0x0000, 64 * 1024, 4 },
412 { "m25p40", 0x12, 0x0000, 64 * 1024, 8 },
413 { "m25p80", 0x13, 0x0000, 64 * 1024, 16 },
414 { "m25p16", 0x14, 0x0000, 64 * 1024, 32 },
415 { "m25p32", 0x15, 0x0000, 64 * 1024, 64 },
416 { "m25p64", 0x16, 0x2017, 64 * 1024, 128 },
417};
418
419/*
420 * board specific setup should have ensured the SPI clock used here
421 * matches what the READ command supports, at least until this driver
422 * understands FAST_READ (for clocks over 25 MHz).
423 */
424static int __devinit m25p_probe(struct spi_device *spi)
425{
426 struct flash_platform_data *data;
427 struct m25p *flash;
428 struct flash_info *info;
429 unsigned i;
430
431 /* Platform data helps sort out which chip type we have, as
432 * well as how this board partitions it.
433 */
434 data = spi->dev.platform_data;
435 if (!data || !data->type) {
436 /* FIXME some chips can identify themselves with RES
437 * or JEDEC get-id commands. Try them ...
438 */
439 DEBUG(MTD_DEBUG_LEVEL1, "%s: no chip id\n",
440 flash->spi->dev.bus_id);
441 return -ENODEV;
442 }
443
444 for (i = 0, info = m25p_data; i < ARRAY_SIZE(m25p_data); i++, info++) {
445 if (strcmp(data->type, info->name) == 0)
446 break;
447 }
448 if (i == ARRAY_SIZE(m25p_data)) {
449 DEBUG(MTD_DEBUG_LEVEL1, "%s: unrecognized id %s\n",
450 flash->spi->dev.bus_id, data->type);
451 return -ENODEV;
452 }
453
454 flash = kzalloc(sizeof *flash, SLAB_KERNEL);
455 if (!flash)
456 return -ENOMEM;
457
458 flash->spi = spi;
459 init_MUTEX(&flash->lock);
460 dev_set_drvdata(&spi->dev, flash);
461
462 if (data->name)
463 flash->mtd.name = data->name;
464 else
465 flash->mtd.name = spi->dev.bus_id;
466
467 flash->mtd.type = MTD_NORFLASH;
468 flash->mtd.flags = MTD_CAP_NORFLASH;
469 flash->mtd.size = info->sector_size * info->n_sectors;
470 flash->mtd.erasesize = info->sector_size;
471 flash->mtd.erase = m25p80_erase;
472 flash->mtd.read = m25p80_read;
473 flash->mtd.write = m25p80_write;
474
475 dev_info(&spi->dev, "%s (%d Kbytes)\n", info->name,
476 flash->mtd.size / 1024);
477
478 DEBUG(MTD_DEBUG_LEVEL2,
479 "mtd .name = %s, .size = 0x%.8x (%uM) "
480 ".erasesize = 0x%.8x (%uK) .numeraseregions = %d\n",
481 flash->mtd.name,
482 flash->mtd.size, flash->mtd.size / (1024*1024),
483 flash->mtd.erasesize, flash->mtd.erasesize / 1024,
484 flash->mtd.numeraseregions);
485
486 if (flash->mtd.numeraseregions)
487 for (i = 0; i < flash->mtd.numeraseregions; i++)
488 DEBUG(MTD_DEBUG_LEVEL2,
489 "mtd.eraseregions[%d] = { .offset = 0x%.8x, "
490 ".erasesize = 0x%.8x (%uK), "
491 ".numblocks = %d }\n",
492 i, flash->mtd.eraseregions[i].offset,
493 flash->mtd.eraseregions[i].erasesize,
494 flash->mtd.eraseregions[i].erasesize / 1024,
495 flash->mtd.eraseregions[i].numblocks);
496
497
498 /* partitions should match sector boundaries; and it may be good to
499 * use readonly partitions for writeprotected sectors (BP2..BP0).
500 */
501 if (mtd_has_partitions()) {
502 struct mtd_partition *parts = NULL;
503 int nr_parts = 0;
504
505#ifdef CONFIG_MTD_CMDLINE_PARTS
506 static const char *part_probes[] = { "cmdlinepart", NULL, };
507
508 nr_parts = parse_mtd_partitions(&flash->mtd,
509 part_probes, &parts, 0);
510#endif
511
512 if (nr_parts <= 0 && data && data->parts) {
513 parts = data->parts;
514 nr_parts = data->nr_parts;
515 }
516
517 if (nr_parts > 0) {
518 for (i = 0; i < data->nr_parts; i++) {
519 DEBUG(MTD_DEBUG_LEVEL2, "partitions[%d] = "
520 "{.name = %s, .offset = 0x%.8x, "
521 ".size = 0x%.8x (%uK) }\n",
522 i, data->parts[i].name,
523 data->parts[i].offset,
524 data->parts[i].size,
525 data->parts[i].size / 1024);
526 }
527 flash->partitioned = 1;
528 return add_mtd_partitions(&flash->mtd, parts, nr_parts);
529 }
530 } else if (data->nr_parts)
531 dev_warn(&spi->dev, "ignoring %d default partitions on %s\n",
532 data->nr_parts, data->name);
533
534 return add_mtd_device(&flash->mtd) == 1 ? -ENODEV : 0;
535}
536
537
538static int __devexit m25p_remove(struct spi_device *spi)
539{
540 struct m25p *flash = dev_get_drvdata(&spi->dev);
541 int status;
542
543 /* Clean up MTD stuff. */
544 if (mtd_has_partitions() && flash->partitioned)
545 status = del_mtd_partitions(&flash->mtd);
546 else
547 status = del_mtd_device(&flash->mtd);
548 if (status == 0)
549 kfree(flash);
550 return 0;
551}
552
553
554static struct spi_driver m25p80_driver = {
555 .driver = {
556 .name = "m25p80",
557 .bus = &spi_bus_type,
558 .owner = THIS_MODULE,
559 },
560 .probe = m25p_probe,
561 .remove = __devexit_p(m25p_remove),
562};
563
564
565static int m25p80_init(void)
566{
567 return spi_register_driver(&m25p80_driver);
568}
569
570
571static void m25p80_exit(void)
572{
573 spi_unregister_driver(&m25p80_driver);
574}
575
576
577module_init(m25p80_init);
578module_exit(m25p80_exit);
579
580MODULE_LICENSE("GPL");
581MODULE_AUTHOR("Mike Lavender");
582MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");
diff --git a/drivers/mtd/devices/mtd_dataflash.c b/drivers/mtd/devices/mtd_dataflash.c
new file mode 100644
index 000000000000..155737e7483f
--- /dev/null
+++ b/drivers/mtd/devices/mtd_dataflash.c
@@ -0,0 +1,629 @@
1/*
2 * Atmel AT45xxx DataFlash MTD driver for lightweight SPI framework
3 *
4 * Largely derived from at91_dataflash.c:
5 * Copyright (C) 2003-2005 SAN People (Pty) Ltd
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11*/
12#include <linux/config.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/slab.h>
16#include <linux/delay.h>
17#include <linux/device.h>
18#include <linux/spi/spi.h>
19#include <linux/spi/flash.h>
20
21#include <linux/mtd/mtd.h>
22#include <linux/mtd/partitions.h>
23
24
25/*
26 * DataFlash is a kind of SPI flash. Most AT45 chips have two buffers in
27 * each chip, which may be used for double buffered I/O; but this driver
28 * doesn't (yet) use these for any kind of i/o overlap or prefetching.
29 *
30 * Sometimes DataFlash is packaged in MMC-format cards, although the
31 * MMC stack can't use SPI (yet), or distinguish between MMC and DataFlash
32 * protocols during enumeration.
33 */
34
35#define CONFIG_DATAFLASH_WRITE_VERIFY
36
37/* reads can bypass the buffers */
38#define OP_READ_CONTINUOUS 0xE8
39#define OP_READ_PAGE 0xD2
40
41/* group B requests can run even while status reports "busy" */
42#define OP_READ_STATUS 0xD7 /* group B */
43
44/* move data between host and buffer */
45#define OP_READ_BUFFER1 0xD4 /* group B */
46#define OP_READ_BUFFER2 0xD6 /* group B */
47#define OP_WRITE_BUFFER1 0x84 /* group B */
48#define OP_WRITE_BUFFER2 0x87 /* group B */
49
50/* erasing flash */
51#define OP_ERASE_PAGE 0x81
52#define OP_ERASE_BLOCK 0x50
53
54/* move data between buffer and flash */
55#define OP_TRANSFER_BUF1 0x53
56#define OP_TRANSFER_BUF2 0x55
57#define OP_MREAD_BUFFER1 0xD4
58#define OP_MREAD_BUFFER2 0xD6
59#define OP_MWERASE_BUFFER1 0x83
60#define OP_MWERASE_BUFFER2 0x86
61#define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */
62#define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */
63
64/* write to buffer, then write-erase to flash */
65#define OP_PROGRAM_VIA_BUF1 0x82
66#define OP_PROGRAM_VIA_BUF2 0x85
67
68/* compare buffer to flash */
69#define OP_COMPARE_BUF1 0x60
70#define OP_COMPARE_BUF2 0x61
71
72/* read flash to buffer, then write-erase to flash */
73#define OP_REWRITE_VIA_BUF1 0x58
74#define OP_REWRITE_VIA_BUF2 0x59
75
76/* newer chips report JEDEC manufacturer and device IDs; chip
77 * serial number and OTP bits; and per-sector writeprotect.
78 */
79#define OP_READ_ID 0x9F
80#define OP_READ_SECURITY 0x77
81#define OP_WRITE_SECURITY 0x9A /* OTP bits */
82
83
84struct dataflash {
85 u8 command[4];
86 char name[24];
87
88 unsigned partitioned:1;
89
90 unsigned short page_offset; /* offset in flash address */
91 unsigned int page_size; /* of bytes per page */
92
93 struct semaphore lock;
94 struct spi_device *spi;
95
96 struct mtd_info mtd;
97};
98
99#ifdef CONFIG_MTD_PARTITIONS
100#define mtd_has_partitions() (1)
101#else
102#define mtd_has_partitions() (0)
103#endif
104
105/* ......................................................................... */
106
107/*
108 * Return the status of the DataFlash device.
109 */
110static inline int dataflash_status(struct spi_device *spi)
111{
112 /* NOTE: at45db321c over 25 MHz wants to write
113 * a dummy byte after the opcode...
114 */
115 return spi_w8r8(spi, OP_READ_STATUS);
116}
117
118/*
119 * Poll the DataFlash device until it is READY.
120 * This usually takes 5-20 msec or so; more for sector erase.
121 */
122static int dataflash_waitready(struct spi_device *spi)
123{
124 int status;
125
126 for (;;) {
127 status = dataflash_status(spi);
128 if (status < 0) {
129 DEBUG(MTD_DEBUG_LEVEL1, "%s: status %d?\n",
130 spi->dev.bus_id, status);
131 status = 0;
132 }
133
134 if (status & (1 << 7)) /* RDY/nBSY */
135 return status;
136
137 msleep(3);
138 }
139}
140
141/* ......................................................................... */
142
143/*
144 * Erase pages of flash.
145 */
146static int dataflash_erase(struct mtd_info *mtd, struct erase_info *instr)
147{
148 struct dataflash *priv = (struct dataflash *)mtd->priv;
149 struct spi_device *spi = priv->spi;
150 struct spi_transfer x = { .tx_dma = 0, };
151 struct spi_message msg;
152 unsigned blocksize = priv->page_size << 3;
153 u8 *command;
154
155 DEBUG(MTD_DEBUG_LEVEL2, "%s: erase addr=0x%x len 0x%x\n",
156 spi->dev.bus_id,
157 instr->addr, instr->len);
158
159 /* Sanity checks */
160 if ((instr->addr + instr->len) > mtd->size
161 || (instr->len % priv->page_size) != 0
162 || (instr->addr % priv->page_size) != 0)
163 return -EINVAL;
164
165 spi_message_init(&msg);
166
167 x.tx_buf = command = priv->command;
168 x.len = 4;
169 spi_message_add_tail(&x, &msg);
170
171 down(&priv->lock);
172 while (instr->len > 0) {
173 unsigned int pageaddr;
174 int status;
175 int do_block;
176
177 /* Calculate flash page address; use block erase (for speed) if
178 * we're at a block boundary and need to erase the whole block.
179 */
180 pageaddr = instr->addr / priv->page_size;
181 do_block = (pageaddr & 0x7) == 0 && instr->len <= blocksize;
182 pageaddr = pageaddr << priv->page_offset;
183
184 command[0] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE;
185 command[1] = (u8)(pageaddr >> 16);
186 command[2] = (u8)(pageaddr >> 8);
187 command[3] = 0;
188
189 DEBUG(MTD_DEBUG_LEVEL3, "ERASE %s: (%x) %x %x %x [%i]\n",
190 do_block ? "block" : "page",
191 command[0], command[1], command[2], command[3],
192 pageaddr);
193
194 status = spi_sync(spi, &msg);
195 (void) dataflash_waitready(spi);
196
197 if (status < 0) {
198 printk(KERN_ERR "%s: erase %x, err %d\n",
199 spi->dev.bus_id, pageaddr, status);
200 /* REVISIT: can retry instr->retries times; or
201 * giveup and instr->fail_addr = instr->addr;
202 */
203 continue;
204 }
205
206 if (do_block) {
207 instr->addr += blocksize;
208 instr->len -= blocksize;
209 } else {
210 instr->addr += priv->page_size;
211 instr->len -= priv->page_size;
212 }
213 }
214 up(&priv->lock);
215
216 /* Inform MTD subsystem that erase is complete */
217 instr->state = MTD_ERASE_DONE;
218 mtd_erase_callback(instr);
219
220 return 0;
221}
222
223/*
224 * Read from the DataFlash device.
225 * from : Start offset in flash device
226 * len : Amount to read
227 * retlen : About of data actually read
228 * buf : Buffer containing the data
229 */
230static int dataflash_read(struct mtd_info *mtd, loff_t from, size_t len,
231 size_t *retlen, u_char *buf)
232{
233 struct dataflash *priv = (struct dataflash *)mtd->priv;
234 struct spi_transfer x[2] = { { .tx_dma = 0, }, };
235 struct spi_message msg;
236 unsigned int addr;
237 u8 *command;
238 int status;
239
240 DEBUG(MTD_DEBUG_LEVEL2, "%s: read 0x%x..0x%x\n",
241 priv->spi->dev.bus_id, (unsigned)from, (unsigned)(from + len));
242
243 *retlen = 0;
244
245 /* Sanity checks */
246 if (!len)
247 return 0;
248 if (from + len > mtd->size)
249 return -EINVAL;
250
251 /* Calculate flash page/byte address */
252 addr = (((unsigned)from / priv->page_size) << priv->page_offset)
253 + ((unsigned)from % priv->page_size);
254
255 command = priv->command;
256
257 DEBUG(MTD_DEBUG_LEVEL3, "READ: (%x) %x %x %x\n",
258 command[0], command[1], command[2], command[3]);
259
260 spi_message_init(&msg);
261
262 x[0].tx_buf = command;
263 x[0].len = 8;
264 spi_message_add_tail(&x[0], &msg);
265
266 x[1].rx_buf = buf;
267 x[1].len = len;
268 spi_message_add_tail(&x[1], &msg);
269
270 down(&priv->lock);
271
272 /* Continuous read, max clock = f(car) which may be less than
273 * the peak rate available. Some chips support commands with
274 * fewer "don't care" bytes. Both buffers stay unchanged.
275 */
276 command[0] = OP_READ_CONTINUOUS;
277 command[1] = (u8)(addr >> 16);
278 command[2] = (u8)(addr >> 8);
279 command[3] = (u8)(addr >> 0);
280 /* plus 4 "don't care" bytes */
281
282 status = spi_sync(priv->spi, &msg);
283 up(&priv->lock);
284
285 if (status >= 0) {
286 *retlen = msg.actual_length - 8;
287 status = 0;
288 } else
289 DEBUG(MTD_DEBUG_LEVEL1, "%s: read %x..%x --> %d\n",
290 priv->spi->dev.bus_id,
291 (unsigned)from, (unsigned)(from + len),
292 status);
293 return status;
294}
295
296/*
297 * Write to the DataFlash device.
298 * to : Start offset in flash device
299 * len : Amount to write
300 * retlen : Amount of data actually written
301 * buf : Buffer containing the data
302 */
303static int dataflash_write(struct mtd_info *mtd, loff_t to, size_t len,
304 size_t * retlen, const u_char * buf)
305{
306 struct dataflash *priv = (struct dataflash *)mtd->priv;
307 struct spi_device *spi = priv->spi;
308 struct spi_transfer x[2] = { { .tx_dma = 0, }, };
309 struct spi_message msg;
310 unsigned int pageaddr, addr, offset, writelen;
311 size_t remaining = len;
312 u_char *writebuf = (u_char *) buf;
313 int status = -EINVAL;
314 u8 *command;
315
316 DEBUG(MTD_DEBUG_LEVEL2, "%s: write 0x%x..0x%x\n",
317 spi->dev.bus_id, (unsigned)to, (unsigned)(to + len));
318
319 *retlen = 0;
320
321 /* Sanity checks */
322 if (!len)
323 return 0;
324 if ((to + len) > mtd->size)
325 return -EINVAL;
326
327 spi_message_init(&msg);
328
329 x[0].tx_buf = command = priv->command;
330 x[0].len = 4;
331 spi_message_add_tail(&x[0], &msg);
332
333 pageaddr = ((unsigned)to / priv->page_size);
334 offset = ((unsigned)to % priv->page_size);
335 if (offset + len > priv->page_size)
336 writelen = priv->page_size - offset;
337 else
338 writelen = len;
339
340 down(&priv->lock);
341 while (remaining > 0) {
342 DEBUG(MTD_DEBUG_LEVEL3, "write @ %i:%i len=%i\n",
343 pageaddr, offset, writelen);
344
345 /* REVISIT:
346 * (a) each page in a sector must be rewritten at least
347 * once every 10K sibling erase/program operations.
348 * (b) for pages that are already erased, we could
349 * use WRITE+MWRITE not PROGRAM for ~30% speedup.
350 * (c) WRITE to buffer could be done while waiting for
351 * a previous MWRITE/MWERASE to complete ...
352 * (d) error handling here seems to be mostly missing.
353 *
354 * Two persistent bits per page, plus a per-sector counter,
355 * could support (a) and (b) ... we might consider using
356 * the second half of sector zero, which is just one block,
357 * to track that state. (On AT91, that sector should also
358 * support boot-from-DataFlash.)
359 */
360
361 addr = pageaddr << priv->page_offset;
362
363 /* (1) Maybe transfer partial page to Buffer1 */
364 if (writelen != priv->page_size) {
365 command[0] = OP_TRANSFER_BUF1;
366 command[1] = (addr & 0x00FF0000) >> 16;
367 command[2] = (addr & 0x0000FF00) >> 8;
368 command[3] = 0;
369
370 DEBUG(MTD_DEBUG_LEVEL3, "TRANSFER: (%x) %x %x %x\n",
371 command[0], command[1], command[2], command[3]);
372
373 status = spi_sync(spi, &msg);
374 if (status < 0)
375 DEBUG(MTD_DEBUG_LEVEL1, "%s: xfer %u -> %d \n",
376 spi->dev.bus_id, addr, status);
377
378 (void) dataflash_waitready(priv->spi);
379 }
380
381 /* (2) Program full page via Buffer1 */
382 addr += offset;
383 command[0] = OP_PROGRAM_VIA_BUF1;
384 command[1] = (addr & 0x00FF0000) >> 16;
385 command[2] = (addr & 0x0000FF00) >> 8;
386 command[3] = (addr & 0x000000FF);
387
388 DEBUG(MTD_DEBUG_LEVEL3, "PROGRAM: (%x) %x %x %x\n",
389 command[0], command[1], command[2], command[3]);
390
391 x[1].tx_buf = writebuf;
392 x[1].len = writelen;
393 spi_message_add_tail(x + 1, &msg);
394 status = spi_sync(spi, &msg);
395 spi_transfer_del(x + 1);
396 if (status < 0)
397 DEBUG(MTD_DEBUG_LEVEL1, "%s: pgm %u/%u -> %d \n",
398 spi->dev.bus_id, addr, writelen, status);
399
400 (void) dataflash_waitready(priv->spi);
401
402
403#ifdef CONFIG_DATAFLASH_WRITE_VERIFY
404
405 /* (3) Compare to Buffer1 */
406 addr = pageaddr << priv->page_offset;
407 command[0] = OP_COMPARE_BUF1;
408 command[1] = (addr & 0x00FF0000) >> 16;
409 command[2] = (addr & 0x0000FF00) >> 8;
410 command[3] = 0;
411
412 DEBUG(MTD_DEBUG_LEVEL3, "COMPARE: (%x) %x %x %x\n",
413 command[0], command[1], command[2], command[3]);
414
415 status = spi_sync(spi, &msg);
416 if (status < 0)
417 DEBUG(MTD_DEBUG_LEVEL1, "%s: compare %u -> %d \n",
418 spi->dev.bus_id, addr, status);
419
420 status = dataflash_waitready(priv->spi);
421
422 /* Check result of the compare operation */
423 if ((status & (1 << 6)) == 1) {
424 printk(KERN_ERR "%s: compare page %u, err %d\n",
425 spi->dev.bus_id, pageaddr, status);
426 remaining = 0;
427 status = -EIO;
428 break;
429 } else
430 status = 0;
431
432#endif /* CONFIG_DATAFLASH_WRITE_VERIFY */
433
434 remaining = remaining - writelen;
435 pageaddr++;
436 offset = 0;
437 writebuf += writelen;
438 *retlen += writelen;
439
440 if (remaining > priv->page_size)
441 writelen = priv->page_size;
442 else
443 writelen = remaining;
444 }
445 up(&priv->lock);
446
447 return status;
448}
449
450/* ......................................................................... */
451
452/*
453 * Register DataFlash device with MTD subsystem.
454 */
455static int __devinit
456add_dataflash(struct spi_device *spi, char *name,
457 int nr_pages, int pagesize, int pageoffset)
458{
459 struct dataflash *priv;
460 struct mtd_info *device;
461 struct flash_platform_data *pdata = spi->dev.platform_data;
462
463 priv = (struct dataflash *) kzalloc(sizeof *priv, GFP_KERNEL);
464 if (!priv)
465 return -ENOMEM;
466
467 init_MUTEX(&priv->lock);
468 priv->spi = spi;
469 priv->page_size = pagesize;
470 priv->page_offset = pageoffset;
471
472 /* name must be usable with cmdlinepart */
473 sprintf(priv->name, "spi%d.%d-%s",
474 spi->master->bus_num, spi->chip_select,
475 name);
476
477 device = &priv->mtd;
478 device->name = (pdata && pdata->name) ? pdata->name : priv->name;
479 device->size = nr_pages * pagesize;
480 device->erasesize = pagesize;
481 device->owner = THIS_MODULE;
482 device->type = MTD_DATAFLASH;
483 device->flags = MTD_CAP_NORFLASH;
484 device->erase = dataflash_erase;
485 device->read = dataflash_read;
486 device->write = dataflash_write;
487 device->priv = priv;
488
489 dev_info(&spi->dev, "%s (%d KBytes)\n", name, device->size/1024);
490 dev_set_drvdata(&spi->dev, priv);
491
492 if (mtd_has_partitions()) {
493 struct mtd_partition *parts;
494 int nr_parts = 0;
495
496#ifdef CONFIG_MTD_CMDLINE_PARTS
497 static const char *part_probes[] = { "cmdlinepart", NULL, };
498
499 nr_parts = parse_mtd_partitions(device, part_probes, &parts, 0);
500#endif
501
502 if (nr_parts <= 0 && pdata && pdata->parts) {
503 parts = pdata->parts;
504 nr_parts = pdata->nr_parts;
505 }
506
507 if (nr_parts > 0) {
508 priv->partitioned = 1;
509 return add_mtd_partitions(device, parts, nr_parts);
510 }
511 } else if (pdata && pdata->nr_parts)
512 dev_warn(&spi->dev, "ignoring %d default partitions on %s\n",
513 pdata->nr_parts, device->name);
514
515 return add_mtd_device(device) == 1 ? -ENODEV : 0;
516}
517
518/*
519 * Detect and initialize DataFlash device:
520 *
521 * Device Density ID code #Pages PageSize Offset
522 * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9
523 * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1025 264 9
524 * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9
525 * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9
526 * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10
527 * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10
528 * AT45DB0642 64Mbit (8M) xx111xxx (0x3c) 8192 1056 11
529 * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11
530 */
531static int __devinit dataflash_probe(struct spi_device *spi)
532{
533 int status;
534
535 status = dataflash_status(spi);
536 if (status <= 0 || status == 0xff) {
537 DEBUG(MTD_DEBUG_LEVEL1, "%s: status error %d\n",
538 spi->dev.bus_id, status);
539 if (status == 0xff)
540 status = -ENODEV;
541 return status;
542 }
543
544 /* if there's a device there, assume it's dataflash.
545 * board setup should have set spi->max_speed_max to
546 * match f(car) for continuous reads, mode 0 or 3.
547 */
548 switch (status & 0x3c) {
549 case 0x0c: /* 0 0 1 1 x x */
550 status = add_dataflash(spi, "AT45DB011B", 512, 264, 9);
551 break;
552 case 0x14: /* 0 1 0 1 x x */
553 status = add_dataflash(spi, "AT45DB021B", 1025, 264, 9);
554 break;
555 case 0x1c: /* 0 1 1 1 x x */
556 status = add_dataflash(spi, "AT45DB041x", 2048, 264, 9);
557 break;
558 case 0x24: /* 1 0 0 1 x x */
559 status = add_dataflash(spi, "AT45DB081B", 4096, 264, 9);
560 break;
561 case 0x2c: /* 1 0 1 1 x x */
562 status = add_dataflash(spi, "AT45DB161x", 4096, 528, 10);
563 break;
564 case 0x34: /* 1 1 0 1 x x */
565 status = add_dataflash(spi, "AT45DB321x", 8192, 528, 10);
566 break;
567 case 0x38: /* 1 1 1 x x x */
568 case 0x3c:
569 status = add_dataflash(spi, "AT45DB642x", 8192, 1056, 11);
570 break;
571 /* obsolete AT45DB1282 not (yet?) supported */
572 default:
573 DEBUG(MTD_DEBUG_LEVEL1, "%s: unsupported device (%x)\n",
574 spi->dev.bus_id, status & 0x3c);
575 status = -ENODEV;
576 }
577
578 if (status < 0)
579 DEBUG(MTD_DEBUG_LEVEL1, "%s: add_dataflash --> %d\n",
580 spi->dev.bus_id, status);
581
582 return status;
583}
584
585static int __devexit dataflash_remove(struct spi_device *spi)
586{
587 struct dataflash *flash = dev_get_drvdata(&spi->dev);
588 int status;
589
590 DEBUG(MTD_DEBUG_LEVEL1, "%s: remove\n", spi->dev.bus_id);
591
592 if (mtd_has_partitions() && flash->partitioned)
593 status = del_mtd_partitions(&flash->mtd);
594 else
595 status = del_mtd_device(&flash->mtd);
596 if (status == 0)
597 kfree(flash);
598 return status;
599}
600
601static struct spi_driver dataflash_driver = {
602 .driver = {
603 .name = "mtd_dataflash",
604 .bus = &spi_bus_type,
605 .owner = THIS_MODULE,
606 },
607
608 .probe = dataflash_probe,
609 .remove = __devexit_p(dataflash_remove),
610
611 /* FIXME: investigate suspend and resume... */
612};
613
614static int __init dataflash_init(void)
615{
616 return spi_register_driver(&dataflash_driver);
617}
618module_init(dataflash_init);
619
620static void __exit dataflash_exit(void)
621{
622 spi_unregister_driver(&dataflash_driver);
623}
624module_exit(dataflash_exit);
625
626
627MODULE_LICENSE("GPL");
628MODULE_AUTHOR("Andrew Victor, David Brownell");
629MODULE_DESCRIPTION("MTD DataFlash driver");
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-16 10:52:33 -0400