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path: root/drivers/irqchip/irq-mips-gic.c
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Diffstat (limited to 'drivers/irqchip/irq-mips-gic.c')
-rw-r--r--drivers/irqchip/irq-mips-gic.c19
1 files changed, 11 insertions, 8 deletions
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 6e52a88bbd9e..c90976d7e53c 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -169,20 +169,19 @@ static void gic_mask_irq(struct irq_data *d)
169{ 169{
170 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); 170 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
171 171
172 write_gic_rmask(BIT(intr)); 172 write_gic_rmask(intr);
173 gic_clear_pcpu_masks(intr); 173 gic_clear_pcpu_masks(intr);
174} 174}
175 175
176static void gic_unmask_irq(struct irq_data *d) 176static void gic_unmask_irq(struct irq_data *d)
177{ 177{
178 struct cpumask *affinity = irq_data_get_affinity_mask(d);
179 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq); 178 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
180 unsigned int cpu; 179 unsigned int cpu;
181 180
182 write_gic_smask(BIT(intr)); 181 write_gic_smask(intr);
183 182
184 gic_clear_pcpu_masks(intr); 183 gic_clear_pcpu_masks(intr);
185 cpu = cpumask_first_and(affinity, cpu_online_mask); 184 cpu = cpumask_first(irq_data_get_effective_affinity_mask(d));
186 set_bit(intr, per_cpu_ptr(pcpu_masks, cpu)); 185 set_bit(intr, per_cpu_ptr(pcpu_masks, cpu));
187} 186}
188 187
@@ -420,13 +419,17 @@ static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
420 irq_hw_number_t hw, unsigned int cpu) 419 irq_hw_number_t hw, unsigned int cpu)
421{ 420{
422 int intr = GIC_HWIRQ_TO_SHARED(hw); 421 int intr = GIC_HWIRQ_TO_SHARED(hw);
422 struct irq_data *data;
423 unsigned long flags; 423 unsigned long flags;
424 424
425 data = irq_get_irq_data(virq);
426
425 spin_lock_irqsave(&gic_lock, flags); 427 spin_lock_irqsave(&gic_lock, flags);
426 write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); 428 write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin);
427 write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu))); 429 write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu)));
428 gic_clear_pcpu_masks(intr); 430 gic_clear_pcpu_masks(intr);
429 set_bit(intr, per_cpu_ptr(pcpu_masks, cpu)); 431 set_bit(intr, per_cpu_ptr(pcpu_masks, cpu));
432 irq_data_update_effective_affinity(data, cpumask_of(cpu));
430 spin_unlock_irqrestore(&gic_lock, flags); 433 spin_unlock_irqrestore(&gic_lock, flags);
431 434
432 return 0; 435 return 0;
@@ -645,7 +648,7 @@ static int __init gic_of_init(struct device_node *node,
645 648
646 /* Find the first available CPU vector. */ 649 /* Find the first available CPU vector. */
647 i = 0; 650 i = 0;
648 reserved = (C_SW0 | C_SW1) >> __fls(C_SW0); 651 reserved = (C_SW0 | C_SW1) >> __ffs(C_SW0);
649 while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors", 652 while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
650 i++, &cpu_vec)) 653 i++, &cpu_vec))
651 reserved |= BIT(cpu_vec); 654 reserved |= BIT(cpu_vec);
@@ -684,11 +687,11 @@ static int __init gic_of_init(struct device_node *node,
684 687
685 gicconfig = read_gic_config(); 688 gicconfig = read_gic_config();
686 gic_shared_intrs = gicconfig & GIC_CONFIG_NUMINTERRUPTS; 689 gic_shared_intrs = gicconfig & GIC_CONFIG_NUMINTERRUPTS;
687 gic_shared_intrs >>= __fls(GIC_CONFIG_NUMINTERRUPTS); 690 gic_shared_intrs >>= __ffs(GIC_CONFIG_NUMINTERRUPTS);
688 gic_shared_intrs = (gic_shared_intrs + 1) * 8; 691 gic_shared_intrs = (gic_shared_intrs + 1) * 8;
689 692
690 gic_vpes = gicconfig & GIC_CONFIG_PVPS; 693 gic_vpes = gicconfig & GIC_CONFIG_PVPS;
691 gic_vpes >>= __fls(GIC_CONFIG_PVPS); 694 gic_vpes >>= __ffs(GIC_CONFIG_PVPS);
692 gic_vpes = gic_vpes + 1; 695 gic_vpes = gic_vpes + 1;
693 696
694 if (cpu_has_veic) { 697 if (cpu_has_veic) {
@@ -767,7 +770,7 @@ static int __init gic_of_init(struct device_node *node,
767 for (i = 0; i < gic_shared_intrs; i++) { 770 for (i = 0; i < gic_shared_intrs; i++) {
768 change_gic_pol(i, GIC_POL_ACTIVE_HIGH); 771 change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
769 change_gic_trig(i, GIC_TRIG_LEVEL); 772 change_gic_trig(i, GIC_TRIG_LEVEL);
770 write_gic_rmask(BIT(i)); 773 write_gic_rmask(i);
771 } 774 }
772 775
773 for (i = 0; i < gic_vpes; i++) { 776 for (i = 0; i < gic_vpes; i++) {