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path: root/drivers/irqchip/irq-atmel-aic5.c
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Diffstat (limited to 'drivers/irqchip/irq-atmel-aic5.c')
-rw-r--r--drivers/irqchip/irq-atmel-aic5.c65
1 files changed, 31 insertions, 34 deletions
diff --git a/drivers/irqchip/irq-atmel-aic5.c b/drivers/irqchip/irq-atmel-aic5.c
index a11aae8fb006..a2e8c3f876cb 100644
--- a/drivers/irqchip/irq-atmel-aic5.c
+++ b/drivers/irqchip/irq-atmel-aic5.c
@@ -75,11 +75,11 @@ aic5_handle(struct pt_regs *regs)
75 u32 irqnr; 75 u32 irqnr;
76 u32 irqstat; 76 u32 irqstat;
77 77
78 irqnr = irq_reg_readl(gc->reg_base + AT91_AIC5_IVR); 78 irqnr = irq_reg_readl(gc, AT91_AIC5_IVR);
79 irqstat = irq_reg_readl(gc->reg_base + AT91_AIC5_ISR); 79 irqstat = irq_reg_readl(gc, AT91_AIC5_ISR);
80 80
81 if (!irqstat) 81 if (!irqstat)
82 irq_reg_writel(0, gc->reg_base + AT91_AIC5_EOICR); 82 irq_reg_writel(gc, 0, AT91_AIC5_EOICR);
83 else 83 else
84 handle_domain_irq(aic5_domain, irqnr, regs); 84 handle_domain_irq(aic5_domain, irqnr, regs);
85} 85}
@@ -92,8 +92,8 @@ static void aic5_mask(struct irq_data *d)
92 92
93 /* Disable interrupt on AIC5 */ 93 /* Disable interrupt on AIC5 */
94 irq_gc_lock(gc); 94 irq_gc_lock(gc);
95 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR); 95 irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);
96 irq_reg_writel(1, gc->reg_base + AT91_AIC5_IDCR); 96 irq_reg_writel(gc, 1, AT91_AIC5_IDCR);
97 gc->mask_cache &= ~d->mask; 97 gc->mask_cache &= ~d->mask;
98 irq_gc_unlock(gc); 98 irq_gc_unlock(gc);
99} 99}
@@ -106,8 +106,8 @@ static void aic5_unmask(struct irq_data *d)
106 106
107 /* Enable interrupt on AIC5 */ 107 /* Enable interrupt on AIC5 */
108 irq_gc_lock(gc); 108 irq_gc_lock(gc);
109 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR); 109 irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);
110 irq_reg_writel(1, gc->reg_base + AT91_AIC5_IECR); 110 irq_reg_writel(gc, 1, AT91_AIC5_IECR);
111 gc->mask_cache |= d->mask; 111 gc->mask_cache |= d->mask;
112 irq_gc_unlock(gc); 112 irq_gc_unlock(gc);
113} 113}
@@ -120,8 +120,8 @@ static int aic5_retrigger(struct irq_data *d)
120 120
121 /* Enable interrupt on AIC5 */ 121 /* Enable interrupt on AIC5 */
122 irq_gc_lock(gc); 122 irq_gc_lock(gc);
123 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR); 123 irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);
124 irq_reg_writel(1, gc->reg_base + AT91_AIC5_ISCR); 124 irq_reg_writel(gc, 1, AT91_AIC5_ISCR);
125 irq_gc_unlock(gc); 125 irq_gc_unlock(gc);
126 126
127 return 0; 127 return 0;
@@ -136,11 +136,11 @@ static int aic5_set_type(struct irq_data *d, unsigned type)
136 int ret; 136 int ret;
137 137
138 irq_gc_lock(gc); 138 irq_gc_lock(gc);
139 irq_reg_writel(d->hwirq, gc->reg_base + AT91_AIC5_SSR); 139 irq_reg_writel(gc, d->hwirq, AT91_AIC5_SSR);
140 smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR); 140 smr = irq_reg_readl(gc, AT91_AIC5_SMR);
141 ret = aic_common_set_type(d, type, &smr); 141 ret = aic_common_set_type(d, type, &smr);
142 if (!ret) 142 if (!ret)
143 irq_reg_writel(smr, gc->reg_base + AT91_AIC5_SMR); 143 irq_reg_writel(gc, smr, AT91_AIC5_SMR);
144 irq_gc_unlock(gc); 144 irq_gc_unlock(gc);
145 145
146 return ret; 146 return ret;
@@ -162,12 +162,11 @@ static void aic5_suspend(struct irq_data *d)
162 if ((mask & gc->mask_cache) == (mask & gc->wake_active)) 162 if ((mask & gc->mask_cache) == (mask & gc->wake_active))
163 continue; 163 continue;
164 164
165 irq_reg_writel(i + gc->irq_base, 165 irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);
166 bgc->reg_base + AT91_AIC5_SSR);
167 if (mask & gc->wake_active) 166 if (mask & gc->wake_active)
168 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IECR); 167 irq_reg_writel(bgc, 1, AT91_AIC5_IECR);
169 else 168 else
170 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR); 169 irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);
171 } 170 }
172 irq_gc_unlock(bgc); 171 irq_gc_unlock(bgc);
173} 172}
@@ -187,12 +186,11 @@ static void aic5_resume(struct irq_data *d)
187 if ((mask & gc->mask_cache) == (mask & gc->wake_active)) 186 if ((mask & gc->mask_cache) == (mask & gc->wake_active))
188 continue; 187 continue;
189 188
190 irq_reg_writel(i + gc->irq_base, 189 irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);
191 bgc->reg_base + AT91_AIC5_SSR);
192 if (mask & gc->mask_cache) 190 if (mask & gc->mask_cache)
193 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IECR); 191 irq_reg_writel(bgc, 1, AT91_AIC5_IECR);
194 else 192 else
195 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR); 193 irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);
196 } 194 }
197 irq_gc_unlock(bgc); 195 irq_gc_unlock(bgc);
198} 196}
@@ -207,10 +205,9 @@ static void aic5_pm_shutdown(struct irq_data *d)
207 205
208 irq_gc_lock(bgc); 206 irq_gc_lock(bgc);
209 for (i = 0; i < dgc->irqs_per_chip; i++) { 207 for (i = 0; i < dgc->irqs_per_chip; i++) {
210 irq_reg_writel(i + gc->irq_base, 208 irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);
211 bgc->reg_base + AT91_AIC5_SSR); 209 irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);
212 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_IDCR); 210 irq_reg_writel(bgc, 1, AT91_AIC5_ICCR);
213 irq_reg_writel(1, bgc->reg_base + AT91_AIC5_ICCR);
214 } 211 }
215 irq_gc_unlock(bgc); 212 irq_gc_unlock(bgc);
216} 213}
@@ -230,24 +227,24 @@ static void __init aic5_hw_init(struct irq_domain *domain)
230 * will not Lock out nIRQ 227 * will not Lock out nIRQ
231 */ 228 */
232 for (i = 0; i < 8; i++) 229 for (i = 0; i < 8; i++)
233 irq_reg_writel(0, gc->reg_base + AT91_AIC5_EOICR); 230 irq_reg_writel(gc, 0, AT91_AIC5_EOICR);
234 231
235 /* 232 /*
236 * Spurious Interrupt ID in Spurious Vector Register. 233 * Spurious Interrupt ID in Spurious Vector Register.
237 * When there is no current interrupt, the IRQ Vector Register 234 * When there is no current interrupt, the IRQ Vector Register
238 * reads the value stored in AIC_SPU 235 * reads the value stored in AIC_SPU
239 */ 236 */
240 irq_reg_writel(0xffffffff, gc->reg_base + AT91_AIC5_SPU); 237 irq_reg_writel(gc, 0xffffffff, AT91_AIC5_SPU);
241 238
242 /* No debugging in AIC: Debug (Protect) Control Register */ 239 /* No debugging in AIC: Debug (Protect) Control Register */
243 irq_reg_writel(0, gc->reg_base + AT91_AIC5_DCR); 240 irq_reg_writel(gc, 0, AT91_AIC5_DCR);
244 241
245 /* Disable and clear all interrupts initially */ 242 /* Disable and clear all interrupts initially */
246 for (i = 0; i < domain->revmap_size; i++) { 243 for (i = 0; i < domain->revmap_size; i++) {
247 irq_reg_writel(i, gc->reg_base + AT91_AIC5_SSR); 244 irq_reg_writel(gc, i, AT91_AIC5_SSR);
248 irq_reg_writel(i, gc->reg_base + AT91_AIC5_SVR); 245 irq_reg_writel(gc, i, AT91_AIC5_SVR);
249 irq_reg_writel(1, gc->reg_base + AT91_AIC5_IDCR); 246 irq_reg_writel(gc, 1, AT91_AIC5_IDCR);
250 irq_reg_writel(1, gc->reg_base + AT91_AIC5_ICCR); 247 irq_reg_writel(gc, 1, AT91_AIC5_ICCR);
251 } 248 }
252} 249}
253 250
@@ -273,11 +270,11 @@ static int aic5_irq_domain_xlate(struct irq_domain *d,
273 gc = dgc->gc[0]; 270 gc = dgc->gc[0];
274 271
275 irq_gc_lock(gc); 272 irq_gc_lock(gc);
276 irq_reg_writel(*out_hwirq, gc->reg_base + AT91_AIC5_SSR); 273 irq_reg_writel(gc, *out_hwirq, AT91_AIC5_SSR);
277 smr = irq_reg_readl(gc->reg_base + AT91_AIC5_SMR); 274 smr = irq_reg_readl(gc, AT91_AIC5_SMR);
278 ret = aic_common_set_priority(intspec[2], &smr); 275 ret = aic_common_set_priority(intspec[2], &smr);
279 if (!ret) 276 if (!ret)
280 irq_reg_writel(intspec[2] | smr, gc->reg_base + AT91_AIC5_SMR); 277 irq_reg_writel(gc, intspec[2] | smr, AT91_AIC5_SMR);
281 irq_gc_unlock(gc); 278 irq_gc_unlock(gc);
282 279
283 return ret; 280 return ret;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 07:01:18 -0500