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-rw-r--r--drivers/gpu/drm/drm_dp_mst_topology.c19
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_fimc.c1
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_gsc.c6
-rw-r--r--drivers/gpu/drm/exynos/exynos_hdmi.c7
-rw-r--r--drivers/gpu/drm/exynos/exynos_mixer.c21
-rw-r--r--drivers/gpu/drm/i915/intel_atomic.c45
-rw-r--r--drivers/gpu/drm/i915/intel_display.c59
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c29
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c4
9 files changed, 68 insertions, 123 deletions
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c
index b0487c9f018c..eb603f1defc2 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -873,9 +873,10 @@ static void drm_dp_destroy_port(struct kref *kref)
873 from an EDID retrieval */ 873 from an EDID retrieval */
874 if (port->connector) { 874 if (port->connector) {
875 mutex_lock(&mgr->destroy_connector_lock); 875 mutex_lock(&mgr->destroy_connector_lock);
876 list_add(&port->connector->destroy_list, &mgr->destroy_connector_list); 876 list_add(&port->next, &mgr->destroy_connector_list);
877 mutex_unlock(&mgr->destroy_connector_lock); 877 mutex_unlock(&mgr->destroy_connector_lock);
878 schedule_work(&mgr->destroy_connector_work); 878 schedule_work(&mgr->destroy_connector_work);
879 return;
879 } 880 }
880 drm_dp_port_teardown_pdt(port, port->pdt); 881 drm_dp_port_teardown_pdt(port, port->pdt);
881 882
@@ -2659,7 +2660,7 @@ static void drm_dp_tx_work(struct work_struct *work)
2659static void drm_dp_destroy_connector_work(struct work_struct *work) 2660static void drm_dp_destroy_connector_work(struct work_struct *work)
2660{ 2661{
2661 struct drm_dp_mst_topology_mgr *mgr = container_of(work, struct drm_dp_mst_topology_mgr, destroy_connector_work); 2662 struct drm_dp_mst_topology_mgr *mgr = container_of(work, struct drm_dp_mst_topology_mgr, destroy_connector_work);
2662 struct drm_connector *connector; 2663 struct drm_dp_mst_port *port;
2663 2664
2664 /* 2665 /*
2665 * Not a regular list traverse as we have to drop the destroy 2666 * Not a regular list traverse as we have to drop the destroy
@@ -2668,15 +2669,21 @@ static void drm_dp_destroy_connector_work(struct work_struct *work)
2668 */ 2669 */
2669 for (;;) { 2670 for (;;) {
2670 mutex_lock(&mgr->destroy_connector_lock); 2671 mutex_lock(&mgr->destroy_connector_lock);
2671 connector = list_first_entry_or_null(&mgr->destroy_connector_list, struct drm_connector, destroy_list); 2672 port = list_first_entry_or_null(&mgr->destroy_connector_list, struct drm_dp_mst_port, next);
2672 if (!connector) { 2673 if (!port) {
2673 mutex_unlock(&mgr->destroy_connector_lock); 2674 mutex_unlock(&mgr->destroy_connector_lock);
2674 break; 2675 break;
2675 } 2676 }
2676 list_del(&connector->destroy_list); 2677 list_del(&port->next);
2677 mutex_unlock(&mgr->destroy_connector_lock); 2678 mutex_unlock(&mgr->destroy_connector_lock);
2678 2679
2679 mgr->cbs->destroy_connector(mgr, connector); 2680 mgr->cbs->destroy_connector(mgr, port->connector);
2681
2682 drm_dp_port_teardown_pdt(port, port->pdt);
2683
2684 if (!port->input && port->vcpi.vcpi > 0)
2685 drm_dp_mst_put_payload_id(mgr, port->vcpi.vcpi);
2686 kfree(port);
2680 } 2687 }
2681} 2688}
2682 2689
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
index 842d6b8dc3c4..2a652359af64 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
@@ -1745,7 +1745,6 @@ static int fimc_probe(struct platform_device *pdev)
1745 spin_lock_init(&ctx->lock); 1745 spin_lock_init(&ctx->lock);
1746 platform_set_drvdata(pdev, ctx); 1746 platform_set_drvdata(pdev, ctx);
1747 1747
1748 pm_runtime_set_active(dev);
1749 pm_runtime_enable(dev); 1748 pm_runtime_enable(dev);
1750 1749
1751 ret = exynos_drm_ippdrv_register(ippdrv); 1750 ret = exynos_drm_ippdrv_register(ippdrv);
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c b/drivers/gpu/drm/exynos/exynos_drm_gsc.c
index 8040ed2a831f..f1c6b76c127f 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gsc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.c
@@ -593,8 +593,7 @@ static int gsc_src_set_transf(struct device *dev,
593 593
594 gsc_write(cfg, GSC_IN_CON); 594 gsc_write(cfg, GSC_IN_CON);
595 595
596 ctx->rotation = cfg & 596 ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0;
597 (GSC_IN_ROT_90 | GSC_IN_ROT_270) ? 1 : 0;
598 *swap = ctx->rotation; 597 *swap = ctx->rotation;
599 598
600 return 0; 599 return 0;
@@ -857,8 +856,7 @@ static int gsc_dst_set_transf(struct device *dev,
857 856
858 gsc_write(cfg, GSC_IN_CON); 857 gsc_write(cfg, GSC_IN_CON);
859 858
860 ctx->rotation = cfg & 859 ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0;
861 (GSC_IN_ROT_90 | GSC_IN_ROT_270) ? 1 : 0;
862 *swap = ctx->rotation; 860 *swap = ctx->rotation;
863 861
864 return 0; 862 return 0;
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 99e286489031..4a00990e4ae4 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -1064,6 +1064,7 @@ static int hdmi_get_modes(struct drm_connector *connector)
1064{ 1064{
1065 struct hdmi_context *hdata = ctx_from_connector(connector); 1065 struct hdmi_context *hdata = ctx_from_connector(connector);
1066 struct edid *edid; 1066 struct edid *edid;
1067 int ret;
1067 1068
1068 if (!hdata->ddc_adpt) 1069 if (!hdata->ddc_adpt)
1069 return -ENODEV; 1070 return -ENODEV;
@@ -1079,7 +1080,11 @@ static int hdmi_get_modes(struct drm_connector *connector)
1079 1080
1080 drm_mode_connector_update_edid_property(connector, edid); 1081 drm_mode_connector_update_edid_property(connector, edid);
1081 1082
1082 return drm_add_edid_modes(connector, edid); 1083 ret = drm_add_edid_modes(connector, edid);
1084
1085 kfree(edid);
1086
1087 return ret;
1083} 1088}
1084 1089
1085static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock) 1090static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index cae98db33062..4706b56902b4 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -718,6 +718,10 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
718 718
719 /* handling VSYNC */ 719 /* handling VSYNC */
720 if (val & MXR_INT_STATUS_VSYNC) { 720 if (val & MXR_INT_STATUS_VSYNC) {
721 /* vsync interrupt use different bit for read and clear */
722 val |= MXR_INT_CLEAR_VSYNC;
723 val &= ~MXR_INT_STATUS_VSYNC;
724
721 /* interlace scan need to check shadow register */ 725 /* interlace scan need to check shadow register */
722 if (ctx->interlace) { 726 if (ctx->interlace) {
723 base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0)); 727 base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
@@ -743,11 +747,6 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
743 747
744out: 748out:
745 /* clear interrupts */ 749 /* clear interrupts */
746 if (~val & MXR_INT_EN_VSYNC) {
747 /* vsync interrupt use different bit for read and clear */
748 val &= ~MXR_INT_EN_VSYNC;
749 val |= MXR_INT_CLEAR_VSYNC;
750 }
751 mixer_reg_write(res, MXR_INT_STATUS, val); 750 mixer_reg_write(res, MXR_INT_STATUS, val);
752 751
753 spin_unlock(&res->reg_slock); 752 spin_unlock(&res->reg_slock);
@@ -907,8 +906,8 @@ static int mixer_enable_vblank(struct exynos_drm_crtc *crtc)
907 } 906 }
908 907
909 /* enable vsync interrupt */ 908 /* enable vsync interrupt */
910 mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC, 909 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
911 MXR_INT_EN_VSYNC); 910 mixer_reg_writemask(res, MXR_INT_EN, ~0, MXR_INT_EN_VSYNC);
912 911
913 return 0; 912 return 0;
914} 913}
@@ -918,7 +917,13 @@ static void mixer_disable_vblank(struct exynos_drm_crtc *crtc)
918 struct mixer_context *mixer_ctx = crtc->ctx; 917 struct mixer_context *mixer_ctx = crtc->ctx;
919 struct mixer_resources *res = &mixer_ctx->mixer_res; 918 struct mixer_resources *res = &mixer_ctx->mixer_res;
920 919
920 if (!mixer_ctx->powered) {
921 mixer_ctx->int_en &= MXR_INT_EN_VSYNC;
922 return;
923 }
924
921 /* disable vsync interrupt */ 925 /* disable vsync interrupt */
926 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
922 mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC); 927 mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC);
923} 928}
924 929
@@ -1047,6 +1052,8 @@ static void mixer_enable(struct exynos_drm_crtc *crtc)
1047 1052
1048 mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET); 1053 mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET);
1049 1054
1055 if (ctx->int_en & MXR_INT_EN_VSYNC)
1056 mixer_reg_writemask(res, MXR_INT_STATUS, ~0, MXR_INT_CLEAR_VSYNC);
1050 mixer_reg_write(res, MXR_INT_EN, ctx->int_en); 1057 mixer_reg_write(res, MXR_INT_EN, ctx->int_en);
1051 mixer_win_reset(ctx); 1058 mixer_win_reset(ctx);
1052} 1059}
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index 7ed8033aae60..8e35e0d013df 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -129,8 +129,9 @@ int intel_atomic_commit(struct drm_device *dev,
129 struct drm_atomic_state *state, 129 struct drm_atomic_state *state,
130 bool async) 130 bool async)
131{ 131{
132 int ret; 132 struct drm_crtc_state *crtc_state;
133 int i; 133 struct drm_crtc *crtc;
134 int ret, i;
134 135
135 if (async) { 136 if (async) {
136 DRM_DEBUG_KMS("i915 does not yet support async commit\n"); 137 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
@@ -142,48 +143,18 @@ int intel_atomic_commit(struct drm_device *dev,
142 return ret; 143 return ret;
143 144
144 /* Point of no return */ 145 /* Point of no return */
145 146 drm_atomic_helper_swap_state(dev, state);
146 /*
147 * FIXME: The proper sequence here will eventually be:
148 *
149 * drm_atomic_helper_swap_state(dev, state)
150 * drm_atomic_helper_commit_modeset_disables(dev, state);
151 * drm_atomic_helper_commit_planes(dev, state);
152 * drm_atomic_helper_commit_modeset_enables(dev, state);
153 * drm_atomic_helper_wait_for_vblanks(dev, state);
154 * drm_atomic_helper_cleanup_planes(dev, state);
155 * drm_atomic_state_free(state);
156 *
157 * once we have full atomic modeset. For now, just manually update
158 * plane states to avoid clobbering good states with dummy states
159 * while nuclear pageflipping.
160 */
161 for (i = 0; i < dev->mode_config.num_total_plane; i++) {
162 struct drm_plane *plane = state->planes[i];
163
164 if (!plane)
165 continue;
166
167 plane->state->state = state;
168 swap(state->plane_states[i], plane->state);
169 plane->state->state = NULL;
170 }
171 147
172 /* swap crtc_scaler_state */ 148 /* swap crtc_scaler_state */
173 for (i = 0; i < dev->mode_config.num_crtc; i++) { 149 for_each_crtc_in_state(state, crtc, crtc_state, i) {
174 struct drm_crtc *crtc = state->crtcs[i]; 150 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
175 if (!crtc) {
176 continue;
177 }
178
179 to_intel_crtc(crtc)->config->scaler_state =
180 to_intel_crtc_state(state->crtc_states[i])->scaler_state;
181 151
182 if (INTEL_INFO(dev)->gen >= 9) 152 if (INTEL_INFO(dev)->gen >= 9)
183 skl_detach_scalers(to_intel_crtc(crtc)); 153 skl_detach_scalers(to_intel_crtc(crtc));
154
155 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
184 } 156 }
185 157
186 drm_atomic_helper_commit_planes(dev, state);
187 drm_atomic_helper_wait_for_vblanks(dev, state); 158 drm_atomic_helper_wait_for_vblanks(dev, state);
188 drm_atomic_helper_cleanup_planes(dev, state); 159 drm_atomic_helper_cleanup_planes(dev, state);
189 drm_atomic_state_free(state); 160 drm_atomic_state_free(state);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 30e0f54ba19d..87476ff181dd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11826,7 +11826,9 @@ encoder_retry:
11826 goto encoder_retry; 11826 goto encoder_retry;
11827 } 11827 }
11828 11828
11829 pipe_config->dither = pipe_config->pipe_bpp != base_bpp; 11829 /* Dithering seems to not pass-through bits correctly when it should, so
11830 * only enable it on 6bpc panels. */
11831 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
11830 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", 11832 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11831 base_bpp, pipe_config->pipe_bpp, pipe_config->dither); 11833 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11832 11834
@@ -12624,17 +12626,17 @@ static int __intel_set_mode(struct drm_crtc *modeset_crtc,
12624 12626
12625 modeset_update_crtc_power_domains(state); 12627 modeset_update_crtc_power_domains(state);
12626 12628
12627 drm_atomic_helper_commit_planes(dev, state);
12628
12629 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 12629 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12630 for_each_crtc_in_state(state, crtc, crtc_state, i) { 12630 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12631 if (!needs_modeset(crtc->state) || !crtc->state->enable) 12631 if (!needs_modeset(crtc->state) || !crtc->state->enable) {
12632 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
12632 continue; 12633 continue;
12634 }
12633 12635
12634 update_scanline_offset(to_intel_crtc(crtc)); 12636 update_scanline_offset(to_intel_crtc(crtc));
12635 12637
12636 dev_priv->display.crtc_enable(crtc); 12638 dev_priv->display.crtc_enable(crtc);
12637 intel_crtc_enable_planes(crtc); 12639 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
12638 } 12640 }
12639 12641
12640 /* FIXME: add subpixel order */ 12642 /* FIXME: add subpixel order */
@@ -12891,20 +12893,11 @@ intel_modeset_stage_output_state(struct drm_device *dev,
12891 return 0; 12893 return 0;
12892} 12894}
12893 12895
12894static bool primary_plane_visible(struct drm_crtc *crtc)
12895{
12896 struct intel_plane_state *plane_state =
12897 to_intel_plane_state(crtc->primary->state);
12898
12899 return plane_state->visible;
12900}
12901
12902static int intel_crtc_set_config(struct drm_mode_set *set) 12896static int intel_crtc_set_config(struct drm_mode_set *set)
12903{ 12897{
12904 struct drm_device *dev; 12898 struct drm_device *dev;
12905 struct drm_atomic_state *state = NULL; 12899 struct drm_atomic_state *state = NULL;
12906 struct intel_crtc_state *pipe_config; 12900 struct intel_crtc_state *pipe_config;
12907 bool primary_plane_was_visible;
12908 int ret; 12901 int ret;
12909 12902
12910 BUG_ON(!set); 12903 BUG_ON(!set);
@@ -12943,38 +12936,8 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
12943 12936
12944 intel_update_pipe_size(to_intel_crtc(set->crtc)); 12937 intel_update_pipe_size(to_intel_crtc(set->crtc));
12945 12938
12946 primary_plane_was_visible = primary_plane_visible(set->crtc);
12947
12948 ret = intel_set_mode_with_config(set->crtc, pipe_config, true); 12939 ret = intel_set_mode_with_config(set->crtc, pipe_config, true);
12949 12940
12950 if (ret == 0 &&
12951 pipe_config->base.enable &&
12952 pipe_config->base.planes_changed &&
12953 !needs_modeset(&pipe_config->base)) {
12954 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12955
12956 /*
12957 * We need to make sure the primary plane is re-enabled if it
12958 * has previously been turned off.
12959 */
12960 if (ret == 0 && !primary_plane_was_visible &&
12961 primary_plane_visible(set->crtc)) {
12962 WARN_ON(!intel_crtc->active);
12963 intel_post_enable_primary(set->crtc);
12964 }
12965
12966 /*
12967 * In the fastboot case this may be our only check of the
12968 * state after boot. It would be better to only do it on
12969 * the first update, but we don't have a nice way of doing that
12970 * (and really, set_config isn't used much for high freq page
12971 * flipping, so increasing its cost here shouldn't be a big
12972 * deal).
12973 */
12974 if (i915.fastboot && ret == 0)
12975 intel_modeset_check_state(set->crtc->dev);
12976 }
12977
12978 if (ret) { 12941 if (ret) {
12979 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", 12942 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12980 set->crtc->base.id, ret); 12943 set->crtc->base.id, ret);
@@ -13305,6 +13268,9 @@ intel_check_primary_plane(struct drm_plane *plane,
13305 */ 13268 */
13306 if (IS_BROADWELL(dev)) 13269 if (IS_BROADWELL(dev))
13307 intel_crtc->atomic.wait_vblank = true; 13270 intel_crtc->atomic.wait_vblank = true;
13271
13272 if (crtc_state)
13273 intel_crtc->atomic.post_enable_primary = true;
13308 } 13274 }
13309 13275
13310 /* 13276 /*
@@ -13317,6 +13283,10 @@ intel_check_primary_plane(struct drm_plane *plane,
13317 if (!state->visible || !fb) 13283 if (!state->visible || !fb)
13318 intel_crtc->atomic.disable_ips = true; 13284 intel_crtc->atomic.disable_ips = true;
13319 13285
13286 if (!state->visible && old_state->visible &&
13287 crtc_state && !needs_modeset(&crtc_state->base))
13288 intel_crtc->atomic.pre_disable_primary = true;
13289
13320 intel_crtc->atomic.fb_bits |= 13290 intel_crtc->atomic.fb_bits |=
13321 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); 13291 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13322 13292
@@ -15034,6 +15004,7 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
15034 struct intel_plane_state *plane_state; 15004 struct intel_plane_state *plane_state;
15035 15005
15036 memset(crtc->config, 0, sizeof(*crtc->config)); 15006 memset(crtc->config, 0, sizeof(*crtc->config));
15007 crtc->config->base.crtc = &crtc->base;
15037 15008
15038 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; 15009 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
15039 15010
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
index 52c22b026005..e10f9644140f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
@@ -166,30 +166,14 @@ gk104_fifo_context_attach(struct nvkm_object *parent,
166} 166}
167 167
168static int 168static int
169gk104_fifo_chan_kick(struct gk104_fifo_chan *chan)
170{
171 struct nvkm_object *obj = (void *)chan;
172 struct gk104_fifo_priv *priv = (void *)obj->engine;
173
174 nv_wr32(priv, 0x002634, chan->base.chid);
175 if (!nv_wait(priv, 0x002634, 0x100000, 0x000000)) {
176 nv_error(priv, "channel %d [%s] kick timeout\n",
177 chan->base.chid, nvkm_client_name(chan));
178 return -EBUSY;
179 }
180
181 return 0;
182}
183
184static int
185gk104_fifo_context_detach(struct nvkm_object *parent, bool suspend, 169gk104_fifo_context_detach(struct nvkm_object *parent, bool suspend,
186 struct nvkm_object *object) 170 struct nvkm_object *object)
187{ 171{
188 struct nvkm_bar *bar = nvkm_bar(parent); 172 struct nvkm_bar *bar = nvkm_bar(parent);
173 struct gk104_fifo_priv *priv = (void *)parent->engine;
189 struct gk104_fifo_base *base = (void *)parent->parent; 174 struct gk104_fifo_base *base = (void *)parent->parent;
190 struct gk104_fifo_chan *chan = (void *)parent; 175 struct gk104_fifo_chan *chan = (void *)parent;
191 u32 addr; 176 u32 addr;
192 int ret;
193 177
194 switch (nv_engidx(object->engine)) { 178 switch (nv_engidx(object->engine)) {
195 case NVDEV_ENGINE_SW : return 0; 179 case NVDEV_ENGINE_SW : return 0;
@@ -204,9 +188,13 @@ gk104_fifo_context_detach(struct nvkm_object *parent, bool suspend,
204 return -EINVAL; 188 return -EINVAL;
205 } 189 }
206 190
207 ret = gk104_fifo_chan_kick(chan); 191 nv_wr32(priv, 0x002634, chan->base.chid);
208 if (ret && suspend) 192 if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
209 return ret; 193 nv_error(priv, "channel %d [%s] kick timeout\n",
194 chan->base.chid, nvkm_client_name(chan));
195 if (suspend)
196 return -EBUSY;
197 }
210 198
211 if (addr) { 199 if (addr) {
212 nv_wo32(base, addr + 0x00, 0x00000000); 200 nv_wo32(base, addr + 0x00, 0x00000000);
@@ -331,7 +319,6 @@ gk104_fifo_chan_fini(struct nvkm_object *object, bool suspend)
331 gk104_fifo_runlist_update(priv, chan->engine); 319 gk104_fifo_runlist_update(priv, chan->engine);
332 } 320 }
333 321
334 gk104_fifo_chan_kick(chan);
335 nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000); 322 nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000);
336 return nvkm_fifo_channel_fini(&chan->base, suspend); 323 return nvkm_fifo_channel_fini(&chan->base, suspend);
337} 324}
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
index 654c8daeb5ab..97ad3bcb99a7 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
@@ -2492,7 +2492,7 @@ int vmw_execbuf_process(struct drm_file *file_priv,
2492 ret = ttm_eu_reserve_buffers(&ticket, &sw_context->validate_nodes, 2492 ret = ttm_eu_reserve_buffers(&ticket, &sw_context->validate_nodes,
2493 true, NULL); 2493 true, NULL);
2494 if (unlikely(ret != 0)) 2494 if (unlikely(ret != 0))
2495 goto out_err; 2495 goto out_err_nores;
2496 2496
2497 ret = vmw_validate_buffers(dev_priv, sw_context); 2497 ret = vmw_validate_buffers(dev_priv, sw_context);
2498 if (unlikely(ret != 0)) 2498 if (unlikely(ret != 0))
@@ -2536,6 +2536,7 @@ int vmw_execbuf_process(struct drm_file *file_priv,
2536 vmw_resource_relocations_free(&sw_context->res_relocations); 2536 vmw_resource_relocations_free(&sw_context->res_relocations);
2537 2537
2538 vmw_fifo_commit(dev_priv, command_size); 2538 vmw_fifo_commit(dev_priv, command_size);
2539 mutex_unlock(&dev_priv->binding_mutex);
2539 2540
2540 vmw_query_bo_switch_commit(dev_priv, sw_context); 2541 vmw_query_bo_switch_commit(dev_priv, sw_context);
2541 ret = vmw_execbuf_fence_commands(file_priv, dev_priv, 2542 ret = vmw_execbuf_fence_commands(file_priv, dev_priv,
@@ -2551,7 +2552,6 @@ int vmw_execbuf_process(struct drm_file *file_priv,
2551 DRM_ERROR("Fence submission error. Syncing.\n"); 2552 DRM_ERROR("Fence submission error. Syncing.\n");
2552 2553
2553 vmw_resource_list_unreserve(&sw_context->resource_list, false); 2554 vmw_resource_list_unreserve(&sw_context->resource_list, false);
2554 mutex_unlock(&dev_priv->binding_mutex);
2555 2555
2556 ttm_eu_fence_buffer_objects(&ticket, &sw_context->validate_nodes, 2556 ttm_eu_fence_buffer_objects(&ticket, &sw_context->validate_nodes,
2557 (void *) fence); 2557 (void *) fence);