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path: root/drivers/gpio/gpio-omap.c
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Diffstat (limited to 'drivers/gpio/gpio-omap.c')
-rw-r--r--drivers/gpio/gpio-omap.c509
1 files changed, 171 insertions, 338 deletions
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 9276ef616430..d0f27084a942 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -44,8 +44,9 @@ struct gpio_regs {
44}; 44};
45 45
46struct gpio_bank { 46struct gpio_bank {
47 struct list_head node;
48 void __iomem *base; 47 void __iomem *base;
48 const struct omap_gpio_reg_offs *regs;
49
49 int irq; 50 int irq;
50 u32 non_wakeup_gpios; 51 u32 non_wakeup_gpios;
51 u32 enabled_non_wakeup_gpios; 52 u32 enabled_non_wakeup_gpios;
@@ -72,11 +73,7 @@ struct gpio_bank {
72 int context_loss_count; 73 int context_loss_count;
73 74
74 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); 75 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
75 void (*set_dataout_multiple)(struct gpio_bank *bank,
76 unsigned long *mask, unsigned long *bits);
77 int (*get_context_loss_count)(struct device *dev); 76 int (*get_context_loss_count)(struct device *dev);
78
79 struct omap_gpio_reg_offs *regs;
80}; 77};
81 78
82#define GPIO_MOD_CTRL_BIT BIT(0) 79#define GPIO_MOD_CTRL_BIT BIT(0)
@@ -92,20 +89,25 @@ static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
92 return gpiochip_get_data(chip); 89 return gpiochip_get_data(chip);
93} 90}
94 91
95static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, 92static inline u32 omap_gpio_rmw(void __iomem *reg, u32 mask, bool set)
96 int is_input)
97{ 93{
98 void __iomem *reg = bank->base; 94 u32 val = readl_relaxed(reg);
99 u32 l;
100 95
101 reg += bank->regs->direction; 96 if (set)
102 l = readl_relaxed(reg); 97 val |= mask;
103 if (is_input)
104 l |= BIT(gpio);
105 else 98 else
106 l &= ~(BIT(gpio)); 99 val &= ~mask;
107 writel_relaxed(l, reg); 100
108 bank->context.oe = l; 101 writel_relaxed(val, reg);
102
103 return val;
104}
105
106static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
107 int is_input)
108{
109 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction,
110 BIT(gpio), is_input);
109} 111}
110 112
111 113
@@ -131,88 +133,8 @@ static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
131static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, 133static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
132 int enable) 134 int enable)
133{ 135{
134 void __iomem *reg = bank->base + bank->regs->dataout; 136 bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout,
135 u32 gpio_bit = BIT(offset); 137 BIT(offset), enable);
136 u32 l;
137
138 l = readl_relaxed(reg);
139 if (enable)
140 l |= gpio_bit;
141 else
142 l &= ~gpio_bit;
143 writel_relaxed(l, reg);
144 bank->context.dataout = l;
145}
146
147static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
148{
149 void __iomem *reg = bank->base + bank->regs->datain;
150
151 return (readl_relaxed(reg) & (BIT(offset))) != 0;
152}
153
154static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
155{
156 void __iomem *reg = bank->base + bank->regs->dataout;
157
158 return (readl_relaxed(reg) & (BIT(offset))) != 0;
159}
160
161/* set multiple data out values using dedicate set/clear register */
162static void omap_set_gpio_dataout_reg_multiple(struct gpio_bank *bank,
163 unsigned long *mask,
164 unsigned long *bits)
165{
166 void __iomem *reg = bank->base;
167 u32 l;
168
169 l = *bits & *mask;
170 writel_relaxed(l, reg + bank->regs->set_dataout);
171 bank->context.dataout |= l;
172
173 l = ~*bits & *mask;
174 writel_relaxed(l, reg + bank->regs->clr_dataout);
175 bank->context.dataout &= ~l;
176}
177
178/* set multiple data out values using mask register */
179static void omap_set_gpio_dataout_mask_multiple(struct gpio_bank *bank,
180 unsigned long *mask,
181 unsigned long *bits)
182{
183 void __iomem *reg = bank->base + bank->regs->dataout;
184 u32 l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask);
185
186 writel_relaxed(l, reg);
187 bank->context.dataout = l;
188}
189
190static unsigned long omap_get_gpio_datain_multiple(struct gpio_bank *bank,
191 unsigned long *mask)
192{
193 void __iomem *reg = bank->base + bank->regs->datain;
194
195 return readl_relaxed(reg) & *mask;
196}
197
198static unsigned long omap_get_gpio_dataout_multiple(struct gpio_bank *bank,
199 unsigned long *mask)
200{
201 void __iomem *reg = bank->base + bank->regs->dataout;
202
203 return readl_relaxed(reg) & *mask;
204}
205
206static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
207{
208 int l = readl_relaxed(base + reg);
209
210 if (set)
211 l |= mask;
212 else
213 l &= ~mask;
214
215 writel_relaxed(l, base + reg);
216} 138}
217 139
218static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) 140static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
@@ -256,7 +178,6 @@ static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
256static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, 178static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
257 unsigned debounce) 179 unsigned debounce)
258{ 180{
259 void __iomem *reg;
260 u32 val; 181 u32 val;
261 u32 l; 182 u32 l;
262 bool enable = !!debounce; 183 bool enable = !!debounce;
@@ -273,19 +194,11 @@ static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
273 l = BIT(offset); 194 l = BIT(offset);
274 195
275 clk_enable(bank->dbck); 196 clk_enable(bank->dbck);
276 reg = bank->base + bank->regs->debounce; 197 writel_relaxed(debounce, bank->base + bank->regs->debounce);
277 writel_relaxed(debounce, reg);
278 198
279 reg = bank->base + bank->regs->debounce_en; 199 val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable);
280 val = readl_relaxed(reg);
281
282 if (enable)
283 val |= l;
284 else
285 val &= ~l;
286 bank->dbck_enable_mask = val; 200 bank->dbck_enable_mask = val;
287 201
288 writel_relaxed(val, reg);
289 clk_disable(bank->dbck); 202 clk_disable(bank->dbck);
290 /* 203 /*
291 * Enable debounce clock per module. 204 * Enable debounce clock per module.
@@ -360,9 +273,9 @@ static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
360 void __iomem *base = bank->base; 273 void __iomem *base = bank->base;
361 u32 gpio_bit = BIT(gpio); 274 u32 gpio_bit = BIT(gpio);
362 275
363 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, 276 omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit,
364 trigger & IRQ_TYPE_LEVEL_LOW); 277 trigger & IRQ_TYPE_LEVEL_LOW);
365 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, 278 omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit,
366 trigger & IRQ_TYPE_LEVEL_HIGH); 279 trigger & IRQ_TYPE_LEVEL_HIGH);
367 280
368 /* 281 /*
@@ -370,9 +283,9 @@ static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
370 * to be woken from idle state. Set the appropriate edge detection 283 * to be woken from idle state. Set the appropriate edge detection
371 * in addition to the level detection. 284 * in addition to the level detection.
372 */ 285 */
373 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit, 286 omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit,
374 trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)); 287 trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH));
375 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, 288 omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit,
376 trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)); 289 trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW));
377 290
378 bank->context.leveldetect0 = 291 bank->context.leveldetect0 =
@@ -384,11 +297,8 @@ static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
384 bank->context.fallingdetect = 297 bank->context.fallingdetect =
385 readl_relaxed(bank->base + bank->regs->fallingdetect); 298 readl_relaxed(bank->base + bank->regs->fallingdetect);
386 299
387 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { 300 bank->level_mask = bank->context.leveldetect0 |
388 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); 301 bank->context.leveldetect1;
389 bank->context.wake_en =
390 readl_relaxed(bank->base + bank->regs->wkup_en);
391 }
392 302
393 /* This part needs to be executed always for OMAP{34xx, 44xx} */ 303 /* This part needs to be executed always for OMAP{34xx, 44xx} */
394 if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) { 304 if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
@@ -403,44 +313,25 @@ static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
403 else 313 else
404 bank->enabled_non_wakeup_gpios &= ~gpio_bit; 314 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
405 } 315 }
406
407 bank->level_mask =
408 readl_relaxed(bank->base + bank->regs->leveldetect0) |
409 readl_relaxed(bank->base + bank->regs->leveldetect1);
410} 316}
411 317
412#ifdef CONFIG_ARCH_OMAP1
413/* 318/*
414 * This only applies to chips that can't do both rising and falling edge 319 * This only applies to chips that can't do both rising and falling edge
415 * detection at once. For all other chips, this function is a noop. 320 * detection at once. For all other chips, this function is a noop.
416 */ 321 */
417static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) 322static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
418{ 323{
419 void __iomem *reg = bank->base; 324 if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) {
420 u32 l = 0; 325 void __iomem *reg = bank->base + bank->regs->irqctrl;
421
422 if (!bank->regs->irqctrl)
423 return;
424 326
425 reg += bank->regs->irqctrl; 327 writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg);
426 328 }
427 l = readl_relaxed(reg);
428 if ((l >> gpio) & 1)
429 l &= ~(BIT(gpio));
430 else
431 l |= BIT(gpio);
432
433 writel_relaxed(l, reg);
434} 329}
435#else
436static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
437#endif
438 330
439static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, 331static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
440 unsigned trigger) 332 unsigned trigger)
441{ 333{
442 void __iomem *reg = bank->base; 334 void __iomem *reg = bank->base;
443 void __iomem *base = bank->base;
444 u32 l = 0; 335 u32 l = 0;
445 336
446 if (bank->regs->leveldetect0 && bank->regs->wkup_en) { 337 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
@@ -472,11 +363,6 @@ static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
472 l |= 2 << (gpio << 1); 363 l |= 2 << (gpio << 1);
473 if (trigger & IRQ_TYPE_EDGE_FALLING) 364 if (trigger & IRQ_TYPE_EDGE_FALLING)
474 l |= BIT(gpio << 1); 365 l |= BIT(gpio << 1);
475
476 /* Enable wake-up during idle for dynamic tick */
477 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
478 bank->context.wake_en =
479 readl_relaxed(bank->base + bank->regs->wkup_en);
480 writel_relaxed(l, reg); 366 writel_relaxed(l, reg);
481 } 367 }
482 return 0; 368 return 0;
@@ -505,17 +391,6 @@ static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
505 391
506static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) 392static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
507{ 393{
508 void __iomem *base = bank->base;
509
510 if (bank->regs->wkup_en &&
511 !LINE_USED(bank->mod_usage, offset) &&
512 !LINE_USED(bank->irq_usage, offset)) {
513 /* Disable wake-up during idle for dynamic tick */
514 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
515 bank->context.wake_en =
516 readl_relaxed(bank->base + bank->regs->wkup_en);
517 }
518
519 if (bank->regs->ctrl && !BANK_USED(bank)) { 394 if (bank->regs->ctrl && !BANK_USED(bank)) {
520 void __iomem *reg = bank->base + bank->regs->ctrl; 395 void __iomem *reg = bank->base + bank->regs->ctrl;
521 u32 ctrl; 396 u32 ctrl;
@@ -626,57 +501,39 @@ static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
626 return l; 501 return l;
627} 502}
628 503
629static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) 504static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
505 unsigned offset, int enable)
630{ 506{
631 void __iomem *reg = bank->base; 507 void __iomem *reg = bank->base;
632 u32 l; 508 u32 gpio_mask = BIT(offset);
633 509
634 if (bank->regs->set_irqenable) { 510 if (bank->regs->set_irqenable && bank->regs->clr_irqenable) {
635 reg += bank->regs->set_irqenable; 511 if (enable) {
636 l = gpio_mask; 512 reg += bank->regs->set_irqenable;
637 bank->context.irqenable1 |= gpio_mask; 513 bank->context.irqenable1 |= gpio_mask;
514 } else {
515 reg += bank->regs->clr_irqenable;
516 bank->context.irqenable1 &= ~gpio_mask;
517 }
518 writel_relaxed(gpio_mask, reg);
638 } else { 519 } else {
639 reg += bank->regs->irqenable; 520 bank->context.irqenable1 =
640 l = readl_relaxed(reg); 521 omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask,
641 if (bank->regs->irqenable_inv) 522 enable ^ bank->regs->irqenable_inv);
642 l &= ~gpio_mask;
643 else
644 l |= gpio_mask;
645 bank->context.irqenable1 = l;
646 } 523 }
647 524
648 writel_relaxed(l, reg); 525 /*
649} 526 * Program GPIO wakeup along with IRQ enable to satisfy OMAP4430 TRM
650 527 * note requiring correlation between the IRQ enable registers and
651static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) 528 * the wakeup registers. In any case, we want wakeup from idle
652{ 529 * enabled for the GPIOs which support this feature.
653 void __iomem *reg = bank->base; 530 */
654 u32 l; 531 if (bank->regs->wkup_en &&
655 532 (bank->regs->edgectrl1 || !(bank->non_wakeup_gpios & gpio_mask))) {
656 if (bank->regs->clr_irqenable) { 533 bank->context.wake_en =
657 reg += bank->regs->clr_irqenable; 534 omap_gpio_rmw(bank->base + bank->regs->wkup_en,
658 l = gpio_mask; 535 gpio_mask, enable);
659 bank->context.irqenable1 &= ~gpio_mask;
660 } else {
661 reg += bank->regs->irqenable;
662 l = readl_relaxed(reg);
663 if (bank->regs->irqenable_inv)
664 l |= gpio_mask;
665 else
666 l &= ~gpio_mask;
667 bank->context.irqenable1 = l;
668 } 536 }
669
670 writel_relaxed(l, reg);
671}
672
673static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
674 unsigned offset, int enable)
675{
676 if (enable)
677 omap_enable_gpio_irqbank(bank, BIT(offset));
678 else
679 omap_disable_gpio_irqbank(bank, BIT(offset));
680} 537}
681 538
682/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ 539/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
@@ -687,38 +544,6 @@ static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
687 return irq_set_irq_wake(bank->irq, enable); 544 return irq_set_irq_wake(bank->irq, enable);
688} 545}
689 546
690static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
691{
692 struct gpio_bank *bank = gpiochip_get_data(chip);
693 unsigned long flags;
694
695 pm_runtime_get_sync(chip->parent);
696
697 raw_spin_lock_irqsave(&bank->lock, flags);
698 omap_enable_gpio_module(bank, offset);
699 bank->mod_usage |= BIT(offset);
700 raw_spin_unlock_irqrestore(&bank->lock, flags);
701
702 return 0;
703}
704
705static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
706{
707 struct gpio_bank *bank = gpiochip_get_data(chip);
708 unsigned long flags;
709
710 raw_spin_lock_irqsave(&bank->lock, flags);
711 bank->mod_usage &= ~(BIT(offset));
712 if (!LINE_USED(bank->irq_usage, offset)) {
713 omap_set_gpio_direction(bank, offset, 1);
714 omap_clear_gpio_debounce(bank, offset);
715 }
716 omap_disable_gpio_module(bank, offset);
717 raw_spin_unlock_irqrestore(&bank->lock, flags);
718
719 pm_runtime_put(chip->parent);
720}
721
722/* 547/*
723 * We need to unmask the GPIO bank interrupt as soon as possible to 548 * We need to unmask the GPIO bank interrupt as soon as possible to
724 * avoid missing GPIO interrupts for other lines in the bank. 549 * avoid missing GPIO interrupts for other lines in the bank.
@@ -731,7 +556,7 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
731static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank) 556static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
732{ 557{
733 void __iomem *isr_reg = NULL; 558 void __iomem *isr_reg = NULL;
734 u32 enabled, isr, level_mask; 559 u32 enabled, isr, edge;
735 unsigned int bit; 560 unsigned int bit;
736 struct gpio_bank *bank = gpiobank; 561 struct gpio_bank *bank = gpiobank;
737 unsigned long wa_lock_flags; 562 unsigned long wa_lock_flags;
@@ -751,16 +576,14 @@ static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
751 enabled = omap_get_gpio_irqbank_mask(bank); 576 enabled = omap_get_gpio_irqbank_mask(bank);
752 isr = readl_relaxed(isr_reg) & enabled; 577 isr = readl_relaxed(isr_reg) & enabled;
753 578
754 if (bank->level_mask) 579 /*
755 level_mask = bank->level_mask & enabled; 580 * Clear edge sensitive interrupts before calling handler(s)
756 else 581 * so subsequent edge transitions are not missed while the
757 level_mask = 0; 582 * handlers are running.
758 583 */
759 /* clear edge sensitive interrupts before handler(s) are 584 edge = isr & ~bank->level_mask;
760 called so that we don't miss any interrupt occurred while 585 if (edge)
761 executing them */ 586 omap_clear_gpio_irqbank(bank, edge);
762 if (isr & ~level_mask)
763 omap_clear_gpio_irqbank(bank, isr & ~level_mask);
764 587
765 raw_spin_unlock_irqrestore(&bank->lock, lock_flags); 588 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
766 589
@@ -807,8 +630,6 @@ static unsigned int omap_gpio_irq_startup(struct irq_data *d)
807 630
808 if (!LINE_USED(bank->mod_usage, offset)) 631 if (!LINE_USED(bank->mod_usage, offset))
809 omap_set_gpio_direction(bank, offset, 1); 632 omap_set_gpio_direction(bank, offset, 1);
810 else if (!omap_gpio_is_input(bank, offset))
811 goto err;
812 omap_enable_gpio_module(bank, offset); 633 omap_enable_gpio_module(bank, offset);
813 bank->irq_usage |= BIT(offset); 634 bank->irq_usage |= BIT(offset);
814 635
@@ -816,9 +637,6 @@ static unsigned int omap_gpio_irq_startup(struct irq_data *d)
816 omap_gpio_unmask_irq(d); 637 omap_gpio_unmask_irq(d);
817 638
818 return 0; 639 return 0;
819err:
820 raw_spin_unlock_irqrestore(&bank->lock, flags);
821 return -EINVAL;
822} 640}
823 641
824static void omap_gpio_irq_shutdown(struct irq_data *d) 642static void omap_gpio_irq_shutdown(struct irq_data *d)
@@ -829,9 +647,9 @@ static void omap_gpio_irq_shutdown(struct irq_data *d)
829 647
830 raw_spin_lock_irqsave(&bank->lock, flags); 648 raw_spin_lock_irqsave(&bank->lock, flags);
831 bank->irq_usage &= ~(BIT(offset)); 649 bank->irq_usage &= ~(BIT(offset));
832 omap_set_gpio_irqenable(bank, offset, 0);
833 omap_clear_gpio_irqstatus(bank, offset);
834 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); 650 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
651 omap_clear_gpio_irqstatus(bank, offset);
652 omap_set_gpio_irqenable(bank, offset, 0);
835 if (!LINE_USED(bank->mod_usage, offset)) 653 if (!LINE_USED(bank->mod_usage, offset))
836 omap_clear_gpio_debounce(bank, offset); 654 omap_clear_gpio_debounce(bank, offset);
837 omap_disable_gpio_module(bank, offset); 655 omap_disable_gpio_module(bank, offset);
@@ -852,14 +670,6 @@ static void gpio_irq_bus_sync_unlock(struct irq_data *data)
852 pm_runtime_put(bank->chip.parent); 670 pm_runtime_put(bank->chip.parent);
853} 671}
854 672
855static void omap_gpio_ack_irq(struct irq_data *d)
856{
857 struct gpio_bank *bank = omap_irq_data_get_bank(d);
858 unsigned offset = d->hwirq;
859
860 omap_clear_gpio_irqstatus(bank, offset);
861}
862
863static void omap_gpio_mask_irq(struct irq_data *d) 673static void omap_gpio_mask_irq(struct irq_data *d)
864{ 674{
865 struct gpio_bank *bank = omap_irq_data_get_bank(d); 675 struct gpio_bank *bank = omap_irq_data_get_bank(d);
@@ -867,8 +677,8 @@ static void omap_gpio_mask_irq(struct irq_data *d)
867 unsigned long flags; 677 unsigned long flags;
868 678
869 raw_spin_lock_irqsave(&bank->lock, flags); 679 raw_spin_lock_irqsave(&bank->lock, flags);
870 omap_set_gpio_irqenable(bank, offset, 0);
871 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); 680 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
681 omap_set_gpio_irqenable(bank, offset, 0);
872 raw_spin_unlock_irqrestore(&bank->lock, flags); 682 raw_spin_unlock_irqrestore(&bank->lock, flags);
873} 683}
874 684
@@ -880,9 +690,6 @@ static void omap_gpio_unmask_irq(struct irq_data *d)
880 unsigned long flags; 690 unsigned long flags;
881 691
882 raw_spin_lock_irqsave(&bank->lock, flags); 692 raw_spin_lock_irqsave(&bank->lock, flags);
883 if (trigger)
884 omap_set_gpio_triggering(bank, offset, trigger);
885
886 omap_set_gpio_irqenable(bank, offset, 1); 693 omap_set_gpio_irqenable(bank, offset, 1);
887 694
888 /* 695 /*
@@ -890,9 +697,13 @@ static void omap_gpio_unmask_irq(struct irq_data *d)
890 * is cleared, thus after the handler has run. OMAP4 needs this done 697 * is cleared, thus after the handler has run. OMAP4 needs this done
891 * after enabing the interrupt to clear the wakeup status. 698 * after enabing the interrupt to clear the wakeup status.
892 */ 699 */
893 if (bank->level_mask & BIT(offset)) 700 if (bank->regs->leveldetect0 && bank->regs->wkup_en &&
701 trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
894 omap_clear_gpio_irqstatus(bank, offset); 702 omap_clear_gpio_irqstatus(bank, offset);
895 703
704 if (trigger)
705 omap_set_gpio_triggering(bank, offset, trigger);
706
896 raw_spin_unlock_irqrestore(&bank->lock, flags); 707 raw_spin_unlock_irqrestore(&bank->lock, flags);
897} 708}
898 709
@@ -958,19 +769,44 @@ static inline void omap_mpuio_init(struct gpio_bank *bank)
958 769
959/*---------------------------------------------------------------------*/ 770/*---------------------------------------------------------------------*/
960 771
961static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 772static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
962{ 773{
963 struct gpio_bank *bank; 774 struct gpio_bank *bank = gpiochip_get_data(chip);
775 unsigned long flags;
776
777 pm_runtime_get_sync(chip->parent);
778
779 raw_spin_lock_irqsave(&bank->lock, flags);
780 omap_enable_gpio_module(bank, offset);
781 bank->mod_usage |= BIT(offset);
782 raw_spin_unlock_irqrestore(&bank->lock, flags);
783
784 return 0;
785}
786
787static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
788{
789 struct gpio_bank *bank = gpiochip_get_data(chip);
964 unsigned long flags; 790 unsigned long flags;
965 void __iomem *reg;
966 int dir;
967 791
968 bank = gpiochip_get_data(chip);
969 reg = bank->base + bank->regs->direction;
970 raw_spin_lock_irqsave(&bank->lock, flags); 792 raw_spin_lock_irqsave(&bank->lock, flags);
971 dir = !!(readl_relaxed(reg) & BIT(offset)); 793 bank->mod_usage &= ~(BIT(offset));
794 if (!LINE_USED(bank->irq_usage, offset)) {
795 omap_set_gpio_direction(bank, offset, 1);
796 omap_clear_gpio_debounce(bank, offset);
797 }
798 omap_disable_gpio_module(bank, offset);
972 raw_spin_unlock_irqrestore(&bank->lock, flags); 799 raw_spin_unlock_irqrestore(&bank->lock, flags);
973 return dir; 800
801 pm_runtime_put(chip->parent);
802}
803
804static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
805{
806 struct gpio_bank *bank = gpiochip_get_data(chip);
807
808 return !!(readl_relaxed(bank->base + bank->regs->direction) &
809 BIT(offset));
974} 810}
975 811
976static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) 812static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
@@ -987,14 +823,15 @@ static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
987 823
988static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) 824static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
989{ 825{
990 struct gpio_bank *bank; 826 struct gpio_bank *bank = gpiochip_get_data(chip);
991 827 void __iomem *reg;
992 bank = gpiochip_get_data(chip);
993 828
994 if (omap_gpio_is_input(bank, offset)) 829 if (omap_gpio_is_input(bank, offset))
995 return omap_get_gpio_datain(bank, offset); 830 reg = bank->base + bank->regs->datain;
996 else 831 else
997 return omap_get_gpio_dataout(bank, offset); 832 reg = bank->base + bank->regs->dataout;
833
834 return (readl_relaxed(reg) & BIT(offset)) != 0;
998} 835}
999 836
1000static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) 837static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
@@ -1014,18 +851,20 @@ static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
1014 unsigned long *bits) 851 unsigned long *bits)
1015{ 852{
1016 struct gpio_bank *bank = gpiochip_get_data(chip); 853 struct gpio_bank *bank = gpiochip_get_data(chip);
1017 void __iomem *reg = bank->base + bank->regs->direction; 854 void __iomem *base = bank->base;
1018 unsigned long in = readl_relaxed(reg), l; 855 u32 direction, m, val = 0;
1019 856
1020 *bits = 0; 857 direction = readl_relaxed(base + bank->regs->direction);
1021 858
1022 l = in & *mask; 859 m = direction & *mask;
1023 if (l) 860 if (m)
1024 *bits |= omap_get_gpio_datain_multiple(bank, &l); 861 val |= readl_relaxed(base + bank->regs->datain) & m;
1025 862
1026 l = ~in & *mask; 863 m = ~direction & *mask;
1027 if (l) 864 if (m)
1028 *bits |= omap_get_gpio_dataout_multiple(bank, &l); 865 val |= readl_relaxed(base + bank->regs->dataout) & m;
866
867 *bits = val;
1029 868
1030 return 0; 869 return 0;
1031} 870}
@@ -1078,10 +917,14 @@ static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
1078 unsigned long *bits) 917 unsigned long *bits)
1079{ 918{
1080 struct gpio_bank *bank = gpiochip_get_data(chip); 919 struct gpio_bank *bank = gpiochip_get_data(chip);
920 void __iomem *reg = bank->base + bank->regs->dataout;
1081 unsigned long flags; 921 unsigned long flags;
922 u32 l;
1082 923
1083 raw_spin_lock_irqsave(&bank->lock, flags); 924 raw_spin_lock_irqsave(&bank->lock, flags);
1084 bank->set_dataout_multiple(bank, mask, bits); 925 l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask);
926 writel_relaxed(l, reg);
927 bank->context.dataout = l;
1085 raw_spin_unlock_irqrestore(&bank->lock, flags); 928 raw_spin_unlock_irqrestore(&bank->lock, flags);
1086} 929}
1087 930
@@ -1115,9 +958,9 @@ static void omap_gpio_mod_init(struct gpio_bank *bank)
1115 return; 958 return;
1116 } 959 }
1117 960
1118 omap_gpio_rmw(base, bank->regs->irqenable, l, 961 omap_gpio_rmw(base + bank->regs->irqenable, l,
1119 bank->regs->irqenable_inv); 962 bank->regs->irqenable_inv);
1120 omap_gpio_rmw(base, bank->regs->irqstatus, l, 963 omap_gpio_rmw(base + bank->regs->irqstatus, l,
1121 !bank->regs->irqenable_inv); 964 !bank->regs->irqenable_inv);
1122 if (bank->regs->debounce_en) 965 if (bank->regs->debounce_en)
1123 writel_relaxed(0, base + bank->regs->debounce_en); 966 writel_relaxed(0, base + bank->regs->debounce_en);
@@ -1180,11 +1023,8 @@ static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1180#endif 1023#endif
1181 1024
1182 /* MPUIO is a bit different, reading IRQ status clears it */ 1025 /* MPUIO is a bit different, reading IRQ status clears it */
1183 if (bank->is_mpuio) { 1026 if (bank->is_mpuio && !bank->regs->wkup_en)
1184 irqc->irq_ack = dummy_irq_chip.irq_ack; 1027 irqc->irq_set_wake = NULL;
1185 if (!bank->regs->wkup_en)
1186 irqc->irq_set_wake = NULL;
1187 }
1188 1028
1189 irq = &bank->chip.irq; 1029 irq = &bank->chip.irq;
1190 irq->chip = irqc; 1030 irq->chip = irqc;
@@ -1215,7 +1055,7 @@ static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1215 1055
1216static void omap_gpio_init_context(struct gpio_bank *p) 1056static void omap_gpio_init_context(struct gpio_bank *p)
1217{ 1057{
1218 struct omap_gpio_reg_offs *regs = p->regs; 1058 const struct omap_gpio_reg_offs *regs = p->regs;
1219 void __iomem *base = p->base; 1059 void __iomem *base = p->base;
1220 1060
1221 p->context.ctrl = readl_relaxed(base + regs->ctrl); 1061 p->context.ctrl = readl_relaxed(base + regs->ctrl);
@@ -1227,60 +1067,56 @@ static void omap_gpio_init_context(struct gpio_bank *p)
1227 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); 1067 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1228 p->context.irqenable1 = readl_relaxed(base + regs->irqenable); 1068 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1229 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); 1069 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1230 1070 p->context.dataout = readl_relaxed(base + regs->dataout);
1231 if (regs->set_dataout && p->regs->clr_dataout)
1232 p->context.dataout = readl_relaxed(base + regs->set_dataout);
1233 else
1234 p->context.dataout = readl_relaxed(base + regs->dataout);
1235 1071
1236 p->context_valid = true; 1072 p->context_valid = true;
1237} 1073}
1238 1074
1239static void omap_gpio_restore_context(struct gpio_bank *bank) 1075static void omap_gpio_restore_context(struct gpio_bank *bank)
1240{ 1076{
1241 writel_relaxed(bank->context.wake_en, 1077 const struct omap_gpio_reg_offs *regs = bank->regs;
1242 bank->base + bank->regs->wkup_en); 1078 void __iomem *base = bank->base;
1243 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl); 1079
1244 writel_relaxed(bank->context.leveldetect0, 1080 writel_relaxed(bank->context.wake_en, base + regs->wkup_en);
1245 bank->base + bank->regs->leveldetect0); 1081 writel_relaxed(bank->context.ctrl, base + regs->ctrl);
1246 writel_relaxed(bank->context.leveldetect1, 1082 writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0);
1247 bank->base + bank->regs->leveldetect1); 1083 writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1);
1248 writel_relaxed(bank->context.risingdetect, 1084 writel_relaxed(bank->context.risingdetect, base + regs->risingdetect);
1249 bank->base + bank->regs->risingdetect); 1085 writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect);
1250 writel_relaxed(bank->context.fallingdetect, 1086 writel_relaxed(bank->context.dataout, base + regs->dataout);
1251 bank->base + bank->regs->fallingdetect); 1087 writel_relaxed(bank->context.oe, base + regs->direction);
1252 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1253 writel_relaxed(bank->context.dataout,
1254 bank->base + bank->regs->set_dataout);
1255 else
1256 writel_relaxed(bank->context.dataout,
1257 bank->base + bank->regs->dataout);
1258 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1259 1088
1260 if (bank->dbck_enable_mask) { 1089 if (bank->dbck_enable_mask) {
1261 writel_relaxed(bank->context.debounce, bank->base + 1090 writel_relaxed(bank->context.debounce, base + regs->debounce);
1262 bank->regs->debounce);
1263 writel_relaxed(bank->context.debounce_en, 1091 writel_relaxed(bank->context.debounce_en,
1264 bank->base + bank->regs->debounce_en); 1092 base + regs->debounce_en);
1265 } 1093 }
1266 1094
1267 writel_relaxed(bank->context.irqenable1, 1095 writel_relaxed(bank->context.irqenable1, base + regs->irqenable);
1268 bank->base + bank->regs->irqenable); 1096 writel_relaxed(bank->context.irqenable2, base + regs->irqenable2);
1269 writel_relaxed(bank->context.irqenable2,
1270 bank->base + bank->regs->irqenable2);
1271} 1097}
1272 1098
1273static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context) 1099static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)
1274{ 1100{
1275 struct device *dev = bank->chip.parent; 1101 struct device *dev = bank->chip.parent;
1276 void __iomem *base = bank->base; 1102 void __iomem *base = bank->base;
1277 u32 nowake; 1103 u32 mask, nowake;
1278 1104
1279 bank->saved_datain = readl_relaxed(base + bank->regs->datain); 1105 bank->saved_datain = readl_relaxed(base + bank->regs->datain);
1280 1106
1281 if (!bank->enabled_non_wakeup_gpios) 1107 if (!bank->enabled_non_wakeup_gpios)
1282 goto update_gpio_context_count; 1108 goto update_gpio_context_count;
1283 1109
1110 /* Check for pending EDGE_FALLING, ignore EDGE_BOTH */
1111 mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect;
1112 mask &= ~bank->context.risingdetect;
1113 bank->saved_datain |= mask;
1114
1115 /* Check for pending EDGE_RISING, ignore EDGE_BOTH */
1116 mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect;
1117 mask &= ~bank->context.fallingdetect;
1118 bank->saved_datain &= ~mask;
1119
1284 if (!may_lose_context) 1120 if (!may_lose_context)
1285 goto update_gpio_context_count; 1121 goto update_gpio_context_count;
1286 1122
@@ -1291,8 +1127,8 @@ static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)
1291 */ 1127 */
1292 if (!bank->loses_context && bank->enabled_non_wakeup_gpios) { 1128 if (!bank->loses_context && bank->enabled_non_wakeup_gpios) {
1293 nowake = bank->enabled_non_wakeup_gpios; 1129 nowake = bank->enabled_non_wakeup_gpios;
1294 omap_gpio_rmw(base, bank->regs->fallingdetect, nowake, ~nowake); 1130 omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake);
1295 omap_gpio_rmw(base, bank->regs->risingdetect, nowake, ~nowake); 1131 omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake);
1296 } 1132 }
1297 1133
1298update_gpio_context_count: 1134update_gpio_context_count:
@@ -1421,7 +1257,7 @@ static int gpio_omap_cpu_notifier(struct notifier_block *nb,
1421 return NOTIFY_OK; 1257 return NOTIFY_OK;
1422} 1258}
1423 1259
1424static struct omap_gpio_reg_offs omap2_gpio_regs = { 1260static const struct omap_gpio_reg_offs omap2_gpio_regs = {
1425 .revision = OMAP24XX_GPIO_REVISION, 1261 .revision = OMAP24XX_GPIO_REVISION,
1426 .direction = OMAP24XX_GPIO_OE, 1262 .direction = OMAP24XX_GPIO_OE,
1427 .datain = OMAP24XX_GPIO_DATAIN, 1263 .datain = OMAP24XX_GPIO_DATAIN,
@@ -1444,7 +1280,7 @@ static struct omap_gpio_reg_offs omap2_gpio_regs = {
1444 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, 1280 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1445}; 1281};
1446 1282
1447static struct omap_gpio_reg_offs omap4_gpio_regs = { 1283static const struct omap_gpio_reg_offs omap4_gpio_regs = {
1448 .revision = OMAP4_GPIO_REVISION, 1284 .revision = OMAP4_GPIO_REVISION,
1449 .direction = OMAP4_GPIO_OE, 1285 .direction = OMAP4_GPIO_OE,
1450 .datain = OMAP4_GPIO_DATAIN, 1286 .datain = OMAP4_GPIO_DATAIN,
@@ -1453,6 +1289,8 @@ static struct omap_gpio_reg_offs omap4_gpio_regs = {
1453 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, 1289 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1454 .irqstatus = OMAP4_GPIO_IRQSTATUS0, 1290 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1455 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, 1291 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1292 .irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0,
1293 .irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1,
1456 .irqenable = OMAP4_GPIO_IRQSTATUSSET0, 1294 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1457 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, 1295 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1458 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, 1296 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
@@ -1528,7 +1366,7 @@ static int omap_gpio_probe(struct platform_device *pdev)
1528 1366
1529 irqc->irq_startup = omap_gpio_irq_startup, 1367 irqc->irq_startup = omap_gpio_irq_startup,
1530 irqc->irq_shutdown = omap_gpio_irq_shutdown, 1368 irqc->irq_shutdown = omap_gpio_irq_shutdown,
1531 irqc->irq_ack = omap_gpio_ack_irq, 1369 irqc->irq_ack = dummy_irq_chip.irq_ack,
1532 irqc->irq_mask = omap_gpio_mask_irq, 1370 irqc->irq_mask = omap_gpio_mask_irq,
1533 irqc->irq_unmask = omap_gpio_unmask_irq, 1371 irqc->irq_unmask = omap_gpio_unmask_irq,
1534 irqc->irq_set_type = omap_gpio_irq_type, 1372 irqc->irq_set_type = omap_gpio_irq_type,
@@ -1572,14 +1410,10 @@ static int omap_gpio_probe(struct platform_device *pdev)
1572 pdata->get_context_loss_count; 1410 pdata->get_context_loss_count;
1573 } 1411 }
1574 1412
1575 if (bank->regs->set_dataout && bank->regs->clr_dataout) { 1413 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1576 bank->set_dataout = omap_set_gpio_dataout_reg; 1414 bank->set_dataout = omap_set_gpio_dataout_reg;
1577 bank->set_dataout_multiple = omap_set_gpio_dataout_reg_multiple; 1415 else
1578 } else {
1579 bank->set_dataout = omap_set_gpio_dataout_mask; 1416 bank->set_dataout = omap_set_gpio_dataout_mask;
1580 bank->set_dataout_multiple =
1581 omap_set_gpio_dataout_mask_multiple;
1582 }
1583 1417
1584 raw_spin_lock_init(&bank->lock); 1418 raw_spin_lock_init(&bank->lock);
1585 raw_spin_lock_init(&bank->wa_lock); 1419 raw_spin_lock_init(&bank->wa_lock);
@@ -1635,7 +1469,6 @@ static int omap_gpio_remove(struct platform_device *pdev)
1635 struct gpio_bank *bank = platform_get_drvdata(pdev); 1469 struct gpio_bank *bank = platform_get_drvdata(pdev);
1636 1470
1637 cpu_pm_unregister_notifier(&bank->nb); 1471 cpu_pm_unregister_notifier(&bank->nb);
1638 list_del(&bank->node);
1639 gpiochip_remove(&bank->chip); 1472 gpiochip_remove(&bank->chip);
1640 pm_runtime_disable(&pdev->dev); 1473 pm_runtime_disable(&pdev->dev);
1641 if (bank->dbck_flag) 1474 if (bank->dbck_flag)
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-25 20:36:19 -0400