1 files changed, 19 insertions, 7 deletions

diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index efc85a279d54..f8c550de6c72 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -208,9 +208,11 @@ static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
  * OMAP's debounce time is in 31us steps
  *   <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
  * so we need to convert and round up to the closest unit.
+ *
+ * Return: 0 on success, negative error otherwise.
  */
-static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
-                                    unsigned debounce)
+static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
+                                   unsigned debounce)
 {
         void __iomem            *reg;
         u32                     val;
@@ -218,11 +220,12 @@ static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
         bool                    enable = !!debounce;
 
         if (!bank->dbck_flag)
-                return;
+                return -ENOTSUPP;
 
         if (enable) {
                 debounce = DIV_ROUND_UP(debounce, 31) - 1;
-                debounce &= OMAP4_GPIO_DEBOUNCINGTIME_MASK;
+                if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
+                        return -EINVAL;
         }
 
         l = BIT(offset);
@@ -255,6 +258,8 @@ static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
                 bank->context.debounce = debounce;
                 bank->context.debounce_en = val;
         }
+
+        return 0;
 }
 
 /**
@@ -964,14 +969,20 @@ static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
 {
         struct gpio_bank *bank;
         unsigned long flags;
+        int ret;
 
         bank = gpiochip_get_data(chip);
 
         raw_spin_lock_irqsave(&bank->lock, flags);
-        omap2_set_gpio_debounce(bank, offset, debounce);
+        ret = omap2_set_gpio_debounce(bank, offset, debounce);
         raw_spin_unlock_irqrestore(&bank->lock, flags);
 
-        return 0;
+        if (ret)
+                dev_info(chip->parent,
+                         "Could not set line %u debounce to %u microseconds (%d)",
+                         offset, debounce, ret);
+
+        return ret;
 }
 
 static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,
@@ -1085,7 +1096,8 @@ static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
          * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
          * irq_alloc_descs() since a base IRQ offset will no longer be needed.
          */
-        irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
+        irq_base = devm_irq_alloc_descs(bank->chip.parent,
+                                        -1, 0, bank->width, 0);
         if (irq_base < 0) {
                 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
                 return -ENODEV;