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-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/am335x-bone-common.dtsi262
-rw-r--r--arch/arm/boot/dts/am335x-bone.dts256
-rw-r--r--arch/arm/boot/dts/am335x-boneblack.dts17
-rw-r--r--arch/arm/boot/dts/imx27.dtsi6
-rw-r--r--arch/arm/boot/dts/imx51.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6q-pinfunc.h4
-rw-r--r--arch/arm/boot/dts/omap3-beagle-xm.dts2
-rw-r--r--arch/arm/boot/dts/omap3-igep.dtsi14
-rw-r--r--arch/arm/boot/dts/omap4-panda-common.dtsi46
-rw-r--r--arch/arm/boot/dts/omap4-sdp.dts39
-rw-r--r--arch/arm/boot/dts/omap5.dtsi7
-rw-r--r--arch/arm/configs/multi_v7_defconfig2
-rw-r--r--arch/arm/mach-imx/clk-fixup-mux.c1
-rw-r--r--arch/arm/mach-imx/clk-imx27.c2
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c4
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c9
-rw-r--r--arch/arm/mach-imx/system.c11
-rw-r--r--arch/arm/mach-omap2/cclock44xx_data.c2
-rw-r--r--arch/arm/mach-omap2/cpuidle44xx.c2
-rw-r--r--arch/arm/mach-omap2/gpmc.c4
-rw-r--r--arch/arm/mach-omap2/mux34xx.c2
-rw-r--r--arch/arm/mach-omap2/omap-smp.c2
-rw-r--r--arch/arm/mach-omap2/omap_device.c2
-rw-r--r--arch/arm/mach-sa1100/collie.c2
-rw-r--r--arch/arm/mach-shmobile/clock-r8a73a4.c2
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c2
-rw-r--r--arch/arm/mach-u300/Kconfig10
-rw-r--r--arch/arm/mach-ux500/cache-l2x0.c1
-rw-r--r--arch/arm64/include/asm/hwcap.h2
-rw-r--r--arch/arm64/kernel/process.c21
-rw-r--r--arch/arm64/kernel/setup.c2
-rw-r--r--arch/arm64/mm/fault.c2
-rw-r--r--arch/mips/Makefile3
-rw-r--r--arch/mips/alchemy/common/usb.c3
-rw-r--r--arch/mips/bcm63xx/cpu.c4
l---------arch/mips/boot/dts/include/dt-bindings2
-rw-r--r--arch/mips/cavium-octeon/csrc-octeon.c1
-rw-r--r--arch/mips/dec/prom/init.c1
-rw-r--r--arch/mips/include/asm/cpu-features.h6
-rw-r--r--arch/mips/include/asm/cpu-info.h1
-rw-r--r--arch/mips/include/asm/cpu-type.h203
-rw-r--r--arch/mips/include/asm/cpu.h38
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h4
-rw-r--r--arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h2
-rw-r--r--arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h2
-rw-r--r--arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h2
-rw-r--r--arch/mips/include/asm/mipsregs.h7
-rw-r--r--arch/mips/include/asm/pci.h12
-rw-r--r--arch/mips/include/asm/timex.h33
-rw-r--r--arch/mips/include/asm/vga.h3
-rw-r--r--arch/mips/kernel/cpu-probe.c58
-rw-r--r--arch/mips/kernel/idle.c3
-rw-r--r--arch/mips/kernel/time.c1
-rw-r--r--arch/mips/kernel/traps.c3
-rw-r--r--arch/mips/mm/c-octeon.c6
-rw-r--r--arch/mips/mm/c-r4k.c48
-rw-r--r--arch/mips/mm/dma-default.c1
-rw-r--r--arch/mips/mm/page.c1
-rw-r--r--arch/mips/mm/sc-mips.c3
-rw-r--r--arch/mips/mm/tlb-r4k.c1
-rw-r--r--arch/mips/mm/tlbex.c1
-rw-r--r--arch/mips/mti-malta/malta-time.c5
-rw-r--r--arch/mips/mti-sead3/sead3-time.c3
-rw-r--r--arch/mips/netlogic/xlr/fmn-config.c3
-rw-r--r--arch/mips/oprofile/common.c1
-rw-r--r--arch/mips/pci/pci-bcm1480.c1
-rw-r--r--arch/mips/sibyte/bcm1480/setup.c3
-rw-r--r--arch/mips/sibyte/sb1250/setup.c3
-rw-r--r--arch/mips/sni/setup.c3
-rw-r--r--arch/x86/Kconfig5
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_ds.c1
-rw-r--r--arch/x86/kernel/entry_64.S15
-rw-r--r--arch/x86/kernel/smpboot.c3
74 files changed, 855 insertions, 387 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cc0f1fb61753..e95af3f5433b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -183,6 +183,7 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
183 am335x-evm.dtb \ 183 am335x-evm.dtb \
184 am335x-evmsk.dtb \ 184 am335x-evmsk.dtb \
185 am335x-bone.dtb \ 185 am335x-bone.dtb \
186 am335x-boneblack.dtb \
186 am3517-evm.dtb \ 187 am3517-evm.dtb \
187 am3517_mt_ventoux.dtb \ 188 am3517_mt_ventoux.dtb \
188 am43x-epos-evm.dtb 189 am43x-epos-evm.dtb
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
new file mode 100644
index 000000000000..2f66deda9f5c
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -0,0 +1,262 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/ {
10 model = "TI AM335x BeagleBone";
11 compatible = "ti,am335x-bone", "ti,am33xx";
12
13 cpus {
14 cpu@0 {
15 cpu0-supply = <&dcdc2_reg>;
16 };
17 };
18
19 memory {
20 device_type = "memory";
21 reg = <0x80000000 0x10000000>; /* 256 MB */
22 };
23
24 am33xx_pinmux: pinmux@44e10800 {
25 pinctrl-names = "default";
26 pinctrl-0 = <&clkout2_pin>;
27
28 user_leds_s0: user_leds_s0 {
29 pinctrl-single,pins = <
30 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
31 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
32 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
33 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
34 >;
35 };
36
37 i2c0_pins: pinmux_i2c0_pins {
38 pinctrl-single,pins = <
39 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
40 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
41 >;
42 };
43
44 uart0_pins: pinmux_uart0_pins {
45 pinctrl-single,pins = <
46 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
47 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
48 >;
49 };
50
51 clkout2_pin: pinmux_clkout2_pin {
52 pinctrl-single,pins = <
53 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
54 >;
55 };
56
57 cpsw_default: cpsw_default {
58 pinctrl-single,pins = <
59 /* Slave 1 */
60 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
61 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
62 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
63 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
64 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
65 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
66 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
67 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
68 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
69 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
70 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
71 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
72 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
73 >;
74 };
75
76 cpsw_sleep: cpsw_sleep {
77 pinctrl-single,pins = <
78 /* Slave 1 reset value */
79 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
80 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
81 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
82 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
83 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
84 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
85 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
86 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
87 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
88 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
89 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
90 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
91 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
92 >;
93 };
94
95 davinci_mdio_default: davinci_mdio_default {
96 pinctrl-single,pins = <
97 /* MDIO */
98 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
99 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
100 >;
101 };
102
103 davinci_mdio_sleep: davinci_mdio_sleep {
104 pinctrl-single,pins = <
105 /* MDIO reset value */
106 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
107 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
108 >;
109 };
110 };
111
112 ocp {
113 uart0: serial@44e09000 {
114 pinctrl-names = "default";
115 pinctrl-0 = <&uart0_pins>;
116
117 status = "okay";
118 };
119
120 musb: usb@47400000 {
121 status = "okay";
122
123 control@44e10000 {
124 status = "okay";
125 };
126
127 usb-phy@47401300 {
128 status = "okay";
129 };
130
131 usb-phy@47401b00 {
132 status = "okay";
133 };
134
135 usb@47401000 {
136 status = "okay";
137 };
138
139 usb@47401800 {
140 status = "okay";
141 dr_mode = "host";
142 };
143
144 dma-controller@07402000 {
145 status = "okay";
146 };
147 };
148
149 i2c0: i2c@44e0b000 {
150 pinctrl-names = "default";
151 pinctrl-0 = <&i2c0_pins>;
152
153 status = "okay";
154 clock-frequency = <400000>;
155
156 tps: tps@24 {
157 reg = <0x24>;
158 };
159
160 };
161 };
162
163 leds {
164 pinctrl-names = "default";
165 pinctrl-0 = <&user_leds_s0>;
166
167 compatible = "gpio-leds";
168
169 led@2 {
170 label = "beaglebone:green:heartbeat";
171 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
172 linux,default-trigger = "heartbeat";
173 default-state = "off";
174 };
175
176 led@3 {
177 label = "beaglebone:green:mmc0";
178 gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
179 linux,default-trigger = "mmc0";
180 default-state = "off";
181 };
182
183 led@4 {
184 label = "beaglebone:green:usr2";
185 gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
186 default-state = "off";
187 };
188
189 led@5 {
190 label = "beaglebone:green:usr3";
191 gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
192 default-state = "off";
193 };
194 };
195};
196
197/include/ "tps65217.dtsi"
198
199&tps {
200 regulators {
201 dcdc1_reg: regulator@0 {
202 regulator-always-on;
203 };
204
205 dcdc2_reg: regulator@1 {
206 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
207 regulator-name = "vdd_mpu";
208 regulator-min-microvolt = <925000>;
209 regulator-max-microvolt = <1325000>;
210 regulator-boot-on;
211 regulator-always-on;
212 };
213
214 dcdc3_reg: regulator@2 {
215 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
216 regulator-name = "vdd_core";
217 regulator-min-microvolt = <925000>;
218 regulator-max-microvolt = <1150000>;
219 regulator-boot-on;
220 regulator-always-on;
221 };
222
223 ldo1_reg: regulator@3 {
224 regulator-always-on;
225 };
226
227 ldo2_reg: regulator@4 {
228 regulator-always-on;
229 };
230
231 ldo3_reg: regulator@5 {
232 regulator-always-on;
233 };
234
235 ldo4_reg: regulator@6 {
236 regulator-always-on;
237 };
238 };
239};
240
241&cpsw_emac0 {
242 phy_id = <&davinci_mdio>, <0>;
243 phy-mode = "mii";
244};
245
246&cpsw_emac1 {
247 phy_id = <&davinci_mdio>, <1>;
248 phy-mode = "mii";
249};
250
251&mac {
252 pinctrl-names = "default", "sleep";
253 pinctrl-0 = <&cpsw_default>;
254 pinctrl-1 = <&cpsw_sleep>;
255
256};
257
258&davinci_mdio {
259 pinctrl-names = "default", "sleep";
260 pinctrl-0 = <&davinci_mdio_default>;
261 pinctrl-1 = <&davinci_mdio_sleep>;
262};
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index d318987d44a1..7993c489982c 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -8,258 +8,4 @@
8/dts-v1/; 8/dts-v1/;
9 9
10#include "am33xx.dtsi" 10#include "am33xx.dtsi"
11 11#include "am335x-bone-common.dtsi"
12/ {
13 model = "TI AM335x BeagleBone";
14 compatible = "ti,am335x-bone", "ti,am33xx";
15
16 cpus {
17 cpu@0 {
18 cpu0-supply = <&dcdc2_reg>;
19 };
20 };
21
22 memory {
23 device_type = "memory";
24 reg = <0x80000000 0x10000000>; /* 256 MB */
25 };
26
27 am33xx_pinmux: pinmux@44e10800 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&clkout2_pin>;
30
31 user_leds_s0: user_leds_s0 {
32 pinctrl-single,pins = <
33 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
34 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
35 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
36 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
37 >;
38 };
39
40 i2c0_pins: pinmux_i2c0_pins {
41 pinctrl-single,pins = <
42 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
43 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
44 >;
45 };
46
47 uart0_pins: pinmux_uart0_pins {
48 pinctrl-single,pins = <
49 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
50 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
51 >;
52 };
53
54 clkout2_pin: pinmux_clkout2_pin {
55 pinctrl-single,pins = <
56 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
57 >;
58 };
59
60 cpsw_default: cpsw_default {
61 pinctrl-single,pins = <
62 /* Slave 1 */
63 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
64 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
65 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
66 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
67 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
68 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
69 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
70 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
71 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
72 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
73 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
74 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
75 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
76 >;
77 };
78
79 cpsw_sleep: cpsw_sleep {
80 pinctrl-single,pins = <
81 /* Slave 1 reset value */
82 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
83 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
84 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
85 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
86 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
87 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
88 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
89 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
90 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
91 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
92 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
93 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
94 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
95 >;
96 };
97
98 davinci_mdio_default: davinci_mdio_default {
99 pinctrl-single,pins = <
100 /* MDIO */
101 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
102 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
103 >;
104 };
105
106 davinci_mdio_sleep: davinci_mdio_sleep {
107 pinctrl-single,pins = <
108 /* MDIO reset value */
109 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
110 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
111 >;
112 };
113 };
114
115 ocp {
116 uart0: serial@44e09000 {
117 pinctrl-names = "default";
118 pinctrl-0 = <&uart0_pins>;
119
120 status = "okay";
121 };
122
123 musb: usb@47400000 {
124 status = "okay";
125
126 control@44e10000 {
127 status = "okay";
128 };
129
130 usb-phy@47401300 {
131 status = "okay";
132 };
133
134 usb-phy@47401b00 {
135 status = "okay";
136 };
137
138 usb@47401000 {
139 status = "okay";
140 };
141
142 usb@47401800 {
143 status = "okay";
144 dr_mode = "host";
145 };
146
147 dma-controller@07402000 {
148 status = "okay";
149 };
150 };
151
152 i2c0: i2c@44e0b000 {
153 pinctrl-names = "default";
154 pinctrl-0 = <&i2c0_pins>;
155
156 status = "okay";
157 clock-frequency = <400000>;
158
159 tps: tps@24 {
160 reg = <0x24>;
161 };
162
163 };
164 };
165
166 leds {
167 pinctrl-names = "default";
168 pinctrl-0 = <&user_leds_s0>;
169
170 compatible = "gpio-leds";
171
172 led@2 {
173 label = "beaglebone:green:heartbeat";
174 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
175 linux,default-trigger = "heartbeat";
176 default-state = "off";
177 };
178
179 led@3 {
180 label = "beaglebone:green:mmc0";
181 gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
182 linux,default-trigger = "mmc0";
183 default-state = "off";
184 };
185
186 led@4 {
187 label = "beaglebone:green:usr2";
188 gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
189 default-state = "off";
190 };
191
192 led@5 {
193 label = "beaglebone:green:usr3";
194 gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
195 default-state = "off";
196 };
197 };
198};
199
200/include/ "tps65217.dtsi"
201
202&tps {
203 regulators {
204 dcdc1_reg: regulator@0 {
205 regulator-always-on;
206 };
207
208 dcdc2_reg: regulator@1 {
209 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
210 regulator-name = "vdd_mpu";
211 regulator-min-microvolt = <925000>;
212 regulator-max-microvolt = <1325000>;
213 regulator-boot-on;
214 regulator-always-on;
215 };
216
217 dcdc3_reg: regulator@2 {
218 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
219 regulator-name = "vdd_core";
220 regulator-min-microvolt = <925000>;
221 regulator-max-microvolt = <1150000>;
222 regulator-boot-on;
223 regulator-always-on;
224 };
225
226 ldo1_reg: regulator@3 {
227 regulator-always-on;
228 };
229
230 ldo2_reg: regulator@4 {
231 regulator-always-on;
232 };
233
234 ldo3_reg: regulator@5 {
235 regulator-always-on;
236 };
237
238 ldo4_reg: regulator@6 {
239 regulator-always-on;
240 };
241 };
242};
243
244&cpsw_emac0 {
245 phy_id = <&davinci_mdio>, <0>;
246 phy-mode = "mii";
247};
248
249&cpsw_emac1 {
250 phy_id = <&davinci_mdio>, <1>;
251 phy-mode = "mii";
252};
253
254&mac {
255 pinctrl-names = "default", "sleep";
256 pinctrl-0 = <&cpsw_default>;
257 pinctrl-1 = <&cpsw_sleep>;
258
259};
260
261&davinci_mdio {
262 pinctrl-names = "default", "sleep";
263 pinctrl-0 = <&davinci_mdio_default>;
264 pinctrl-1 = <&davinci_mdio_sleep>;
265};
diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts
new file mode 100644
index 000000000000..197cadf72d2c
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-boneblack.dts
@@ -0,0 +1,17 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "am33xx.dtsi"
11#include "am335x-bone-common.dtsi"
12
13&ldo3_reg {
14 regulator-min-microvolt = <1800000>;
15 regulator-max-microvolt = <1800000>;
16 regulator-always-on;
17};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index c037c223619a..b7a1c6d950b9 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -187,7 +187,7 @@
187 compatible = "fsl,imx27-cspi"; 187 compatible = "fsl,imx27-cspi";
188 reg = <0x1000e000 0x1000>; 188 reg = <0x1000e000 0x1000>;
189 interrupts = <16>; 189 interrupts = <16>;
190 clocks = <&clks 53>, <&clks 53>; 190 clocks = <&clks 53>, <&clks 60>;
191 clock-names = "ipg", "per"; 191 clock-names = "ipg", "per";
192 status = "disabled"; 192 status = "disabled";
193 }; 193 };
@@ -198,7 +198,7 @@
198 compatible = "fsl,imx27-cspi"; 198 compatible = "fsl,imx27-cspi";
199 reg = <0x1000f000 0x1000>; 199 reg = <0x1000f000 0x1000>;
200 interrupts = <15>; 200 interrupts = <15>;
201 clocks = <&clks 52>, <&clks 52>; 201 clocks = <&clks 52>, <&clks 60>;
202 clock-names = "ipg", "per"; 202 clock-names = "ipg", "per";
203 status = "disabled"; 203 status = "disabled";
204 }; 204 };
@@ -309,7 +309,7 @@
309 compatible = "fsl,imx27-cspi"; 309 compatible = "fsl,imx27-cspi";
310 reg = <0x10017000 0x1000>; 310 reg = <0x10017000 0x1000>;
311 interrupts = <6>; 311 interrupts = <6>;
312 clocks = <&clks 51>, <&clks 51>; 312 clocks = <&clks 51>, <&clks 60>;
313 clock-names = "ipg", "per"; 313 clock-names = "ipg", "per";
314 status = "disabled"; 314 status = "disabled";
315 }; 315 };
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index a85abb424c34..54cee6517902 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -474,7 +474,7 @@
474 compatible = "fsl,imx51-pata", "fsl,imx27-pata"; 474 compatible = "fsl,imx51-pata", "fsl,imx27-pata";
475 reg = <0x83fe0000 0x4000>; 475 reg = <0x83fe0000 0x4000>;
476 interrupts = <70>; 476 interrupts = <70>;
477 clocks = <&clks 161>; 477 clocks = <&clks 172>;
478 status = "disabled"; 478 status = "disabled";
479 }; 479 };
480 480
diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h
index c0e38a45e4bb..9bbe82bdee41 100644
--- a/arch/arm/boot/dts/imx6q-pinfunc.h
+++ b/arch/arm/boot/dts/imx6q-pinfunc.h
@@ -207,8 +207,8 @@
207#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1 207#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1
208#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1 208#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1
209#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0 209#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0
210#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c4 0x3dc 0x000 0x4 0x0 210#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c8 0x3dc 0x000 0x4 0x0
211#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c4 0x3dc 0x924 0x4 0x1 211#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c8 0x3dc 0x924 0x4 0x1
212#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0 212#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0
213#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0 213#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0
214#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0 214#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index afdb16417d4e..0c514dc8460c 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -11,7 +11,7 @@
11 11
12/ { 12/ {
13 model = "TI OMAP3 BeagleBoard xM"; 13 model = "TI OMAP3 BeagleBoard xM";
14 compatible = "ti,omap3-beagle-xm, ti,omap3-beagle", "ti,omap3"; 14 compatible = "ti,omap3-beagle-xm", "ti,omap3-beagle", "ti,omap3";
15 15
16 cpus { 16 cpus {
17 cpu@0 { 17 cpu@0 {
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index bc48b114eae6..2326d11462a5 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -48,6 +48,15 @@
48 >; 48 >;
49 }; 49 };
50 50
51 mcbsp2_pins: pinmux_mcbsp2_pins {
52 pinctrl-single,pins = <
53 0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
54 0x10e (PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */
55 0x110 (PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */
56 0x112 (PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */
57 >;
58 };
59
51 mmc1_pins: pinmux_mmc1_pins { 60 mmc1_pins: pinmux_mmc1_pins {
52 pinctrl-single,pins = < 61 pinctrl-single,pins = <
53 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ 62 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
@@ -93,6 +102,11 @@
93 clock-frequency = <400000>; 102 clock-frequency = <400000>;
94}; 103};
95 104
105&mcbsp2 {
106 pinctrl-names = "default";
107 pinctrl-0 = <&mcbsp2_pins>;
108};
109
96&mmc1 { 110&mmc1 {
97 pinctrl-names = "default"; 111 pinctrl-names = "default";
98 pinctrl-0 = <&mmc1_pins>; 112 pinctrl-0 = <&mmc1_pins>;
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index faa95b5b242e..814ab67c8c29 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -107,6 +107,19 @@
107 */ 107 */
108 clock-frequency = <19200000>; 108 clock-frequency = <19200000>;
109 }; 109 };
110
111 /* regulator for wl12xx on sdio5 */
112 wl12xx_vmmc: wl12xx_vmmc {
113 pinctrl-names = "default";
114 pinctrl-0 = <&wl12xx_gpio>;
115 compatible = "regulator-fixed";
116 regulator-name = "vwl1271";
117 regulator-min-microvolt = <1800000>;
118 regulator-max-microvolt = <1800000>;
119 gpio = <&gpio2 11 0>;
120 startup-delay-us = <70000>;
121 enable-active-high;
122 };
110}; 123};
111 124
112&omap4_pmx_wkup { 125&omap4_pmx_wkup {
@@ -235,6 +248,33 @@
235 0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */ 248 0x1c (PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
236 >; 249 >;
237 }; 250 };
251
252 /*
253 * wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP
254 * REVISIT: Are the pull-ups needed for GPIO 48 and 49?
255 */
256 wl12xx_gpio: pinmux_wl12xx_gpio {
257 pinctrl-single,pins = <
258 0x26 (PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */
259 0x2c (PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 */
260 0x30 (PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48 */
261 0x32 (PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 */
262 >;
263 };
264
265 /* wl12xx GPIO inputs and SDIO pins */
266 wl12xx_pins: pinmux_wl12xx_pins {
267 pinctrl-single,pins = <
268 0x38 (PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */
269 0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
270 0x108 (PIN_OUTPUT | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
271 0x10a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */
272 0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */
273 0x10e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */
274 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */
275 0x112 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */
276 >;
277 };
238}; 278};
239 279
240&i2c1 { 280&i2c1 {
@@ -314,8 +354,12 @@
314}; 354};
315 355
316&mmc5 { 356&mmc5 {
317 ti,non-removable; 357 pinctrl-names = "default";
358 pinctrl-0 = <&wl12xx_pins>;
359 vmmc-supply = <&wl12xx_vmmc>;
360 non-removable;
318 bus-width = <4>; 361 bus-width = <4>;
362 cap-power-off-card;
319}; 363};
320 364
321&emif1 { 365&emif1 {
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 7951b4ea500a..4f78380ecdb8 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -140,6 +140,19 @@
140 "DMic", "Digital Mic", 140 "DMic", "Digital Mic",
141 "Digital Mic", "Digital Mic1 Bias"; 141 "Digital Mic", "Digital Mic1 Bias";
142 }; 142 };
143
144 /* regulator for wl12xx on sdio5 */
145 wl12xx_vmmc: wl12xx_vmmc {
146 pinctrl-names = "default";
147 pinctrl-0 = <&wl12xx_gpio>;
148 compatible = "regulator-fixed";
149 regulator-name = "vwl1271";
150 regulator-min-microvolt = <1800000>;
151 regulator-max-microvolt = <1800000>;
152 gpio = <&gpio2 22 0>;
153 startup-delay-us = <70000>;
154 enable-active-high;
155 };
143}; 156};
144 157
145&omap4_pmx_wkup { 158&omap4_pmx_wkup {
@@ -295,6 +308,26 @@
295 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ 308 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */
296 >; 309 >;
297 }; 310 };
311
312 /* wl12xx GPIO output for WLAN_EN */
313 wl12xx_gpio: pinmux_wl12xx_gpio {
314 pinctrl-single,pins = <
315 0x3c (PIN_OUTPUT | MUX_MODE3) /* gpmc_nwp.gpio_54 */
316 >;
317 };
318
319 /* wl12xx GPIO inputs and SDIO pins */
320 wl12xx_pins: pinmux_wl12xx_pins {
321 pinctrl-single,pins = <
322 0x3a (PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
323 0x108 (PIN_OUTPUT | MUX_MODE3) /* sdmmc5_clk.sdmmc5_clk */
324 0x10a (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_cmd.sdmmc5_cmd */
325 0x10c (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat0.sdmmc5_dat0 */
326 0x10e (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat1.sdmmc5_dat1 */
327 0x110 (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat2.sdmmc5_dat2 */
328 0x112 (PIN_INPUT_PULLUP | MUX_MODE3) /* sdmmc5_dat3.sdmmc5_dat3 */
329 >;
330 };
298}; 331};
299 332
300&i2c1 { 333&i2c1 {
@@ -420,8 +453,12 @@
420}; 453};
421 454
422&mmc5 { 455&mmc5 {
456 pinctrl-names = "default";
457 pinctrl-0 = <&wl12xx_pins>;
458 vmmc-supply = <&wl12xx_vmmc>;
459 non-removable;
423 bus-width = <4>; 460 bus-width = <4>;
424 ti,non-removable; 461 cap-power-off-card;
425}; 462};
426 463
427&emif1 { 464&emif1 {
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 07be2cd7b318..7cdea1bfea09 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -637,7 +637,7 @@
637 omap_dwc3@4a020000 { 637 omap_dwc3@4a020000 {
638 compatible = "ti,dwc3"; 638 compatible = "ti,dwc3";
639 ti,hwmods = "usb_otg_ss"; 639 ti,hwmods = "usb_otg_ss";
640 reg = <0x4a020000 0x1000>; 640 reg = <0x4a020000 0x10000>;
641 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 641 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
642 #address-cells = <1>; 642 #address-cells = <1>;
643 #size-cells = <1>; 643 #size-cells = <1>;
@@ -645,17 +645,18 @@
645 ranges; 645 ranges;
646 dwc3@4a030000 { 646 dwc3@4a030000 {
647 compatible = "snps,dwc3"; 647 compatible = "snps,dwc3";
648 reg = <0x4a030000 0x1000>; 648 reg = <0x4a030000 0x10000>;
649 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 649 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
650 usb-phy = <&usb2_phy>, <&usb3_phy>; 650 usb-phy = <&usb2_phy>, <&usb3_phy>;
651 tx-fifo-resize; 651 tx-fifo-resize;
652 }; 652 };
653 }; 653 };
654 654
655 ocp2scp { 655 ocp2scp@4a080000 {
656 compatible = "ti,omap-ocp2scp"; 656 compatible = "ti,omap-ocp2scp";
657 #address-cells = <1>; 657 #address-cells = <1>;
658 #size-cells = <1>; 658 #size-cells = <1>;
659 reg = <0x4a080000 0x20>;
659 ranges; 660 ranges;
660 ti,hwmods = "ocp2scp1"; 661 ti,hwmods = "ocp2scp1";
661 usb2_phy: usb2phy@4a084000 { 662 usb2_phy: usb2phy@4a084000 {
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 6e572c64cf5a..f3935b46df29 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -36,6 +36,7 @@ CONFIG_ARCH_TEGRA_114_SOC=y
36CONFIG_TEGRA_PCI=y 36CONFIG_TEGRA_PCI=y
37CONFIG_TEGRA_EMC_SCALING_ENABLE=y 37CONFIG_TEGRA_EMC_SCALING_ENABLE=y
38CONFIG_ARCH_U8500=y 38CONFIG_ARCH_U8500=y
39CONFIG_MACH_HREFV60=y
39CONFIG_MACH_SNOWBALL=y 40CONFIG_MACH_SNOWBALL=y
40CONFIG_MACH_UX500_DT=y 41CONFIG_MACH_UX500_DT=y
41CONFIG_ARCH_VEXPRESS=y 42CONFIG_ARCH_VEXPRESS=y
@@ -46,6 +47,7 @@ CONFIG_ARCH_ZYNQ=y
46CONFIG_SMP=y 47CONFIG_SMP=y
47CONFIG_HIGHPTE=y 48CONFIG_HIGHPTE=y
48CONFIG_ARM_APPENDED_DTB=y 49CONFIG_ARM_APPENDED_DTB=y
50CONFIG_ARM_ATAG_DTB_COMPAT=y
49CONFIG_NET=y 51CONFIG_NET=y
50CONFIG_UNIX=y 52CONFIG_UNIX=y
51CONFIG_INET=y 53CONFIG_INET=y
diff --git a/arch/arm/mach-imx/clk-fixup-mux.c b/arch/arm/mach-imx/clk-fixup-mux.c
index deb4b8093b30..0d40b35c557c 100644
--- a/arch/arm/mach-imx/clk-fixup-mux.c
+++ b/arch/arm/mach-imx/clk-fixup-mux.c
@@ -90,6 +90,7 @@ struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
90 init.ops = &clk_fixup_mux_ops; 90 init.ops = &clk_fixup_mux_ops;
91 init.parent_names = parents; 91 init.parent_names = parents;
92 init.num_parents = num_parents; 92 init.num_parents = num_parents;
93 init.flags = 0;
93 94
94 fixup_mux->mux.reg = reg; 95 fixup_mux->mux.reg = reg;
95 fixup_mux->mux.shift = shift; 96 fixup_mux->mux.shift = shift;
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index c3cfa4116dc0..c6b40f386786 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -285,7 +285,7 @@ int __init mx27_clocks_init(unsigned long fref)
285 clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL); 285 clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL);
286 clk_register_clkdev(clk[rtc_ipg_gate], NULL, "imx21-rtc"); 286 clk_register_clkdev(clk[rtc_ipg_gate], NULL, "imx21-rtc");
287 clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL); 287 clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
288 clk_register_clkdev(clk[cpu_div], NULL, "cpufreq-cpu0.0"); 288 clk_register_clkdev(clk[cpu_div], NULL, "cpu0");
289 clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL); 289 clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
290 290
291 mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1); 291 mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 1a56a3319997..7c0dc4540aa4 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -328,7 +328,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
328 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1"); 328 clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
329 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2"); 329 clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
330 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); 330 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
331 clk_register_clkdev(clk[cpu_podf], NULL, "cpufreq-cpu0.0"); 331 clk_register_clkdev(clk[cpu_podf], NULL, "cpu0");
332 clk_register_clkdev(clk[iim_gate], "iim", NULL); 332 clk_register_clkdev(clk[iim_gate], "iim", NULL);
333 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0"); 333 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.0");
334 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1"); 334 clk_register_clkdev(clk[dummy], NULL, "imx2-wdt.1");
@@ -397,7 +397,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
397 mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel)); 397 mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
398 clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2, 398 clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
399 spdif_sel, ARRAY_SIZE(spdif_sel)); 399 spdif_sel, ARRAY_SIZE(spdif_sel));
400 clk[spdif1_pred] = imx_clk_divider("spdif1_podf", "spdif1_sel", MXC_CCM_CDCDR, 16, 3); 400 clk[spdif1_pred] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
401 clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6); 401 clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
402 clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1, 402 clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
403 mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel)); 403 mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 85a1b51346c8..90372a21087f 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -233,10 +233,15 @@ put_node:
233 of_node_put(np); 233 of_node_put(np);
234} 234}
235 235
236static void __init imx6q_opp_init(struct device *cpu_dev) 236static void __init imx6q_opp_init(void)
237{ 237{
238 struct device_node *np; 238 struct device_node *np;
239 struct device *cpu_dev = get_cpu_device(0);
239 240
241 if (!cpu_dev) {
242 pr_warn("failed to get cpu0 device\n");
243 return;
244 }
240 np = of_node_get(cpu_dev->of_node); 245 np = of_node_get(cpu_dev->of_node);
241 if (!np) { 246 if (!np) {
242 pr_warn("failed to find cpu0 node\n"); 247 pr_warn("failed to find cpu0 node\n");
@@ -268,7 +273,7 @@ static void __init imx6q_init_late(void)
268 imx6q_cpuidle_init(); 273 imx6q_cpuidle_init();
269 274
270 if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) { 275 if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
271 imx6q_opp_init(&imx6q_cpufreq_pdev.dev); 276 imx6q_opp_init();
272 platform_device_register(&imx6q_cpufreq_pdev); 277 platform_device_register(&imx6q_cpufreq_pdev);
273 } 278 }
274} 279}
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 64ff37ea72b1..80c177c36c5f 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -117,6 +117,17 @@ void __init imx_init_l2cache(void)
117 /* Configure the L2 PREFETCH and POWER registers */ 117 /* Configure the L2 PREFETCH and POWER registers */
118 val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL); 118 val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
119 val |= 0x70800000; 119 val |= 0x70800000;
120 /*
121 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
122 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
123 * But according to ARM PL310 errata: 752271
124 * ID: 752271: Double linefill feature can cause data corruption
125 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
126 * Workaround: The only workaround to this erratum is to disable the
127 * double linefill feature. This is the default behavior.
128 */
129 if (cpu_is_imx6q())
130 val &= ~(1 << 30 | 1 << 23);
120 writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL); 131 writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
121 val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN; 132 val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
122 writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL); 133 writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index 1d5b5290d2af..b237950eb8a3 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -1632,7 +1632,7 @@ static struct omap_clk omap44xx_clks[] = {
1632 CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck), 1632 CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck),
1633 CLK(NULL, "auxclk5_ck", &auxclk5_ck), 1633 CLK(NULL, "auxclk5_ck", &auxclk5_ck),
1634 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck), 1634 CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck),
1635 CLK("omap-gpmc", "fck", &dummy_ck), 1635 CLK("50000000.gpmc", "fck", &dummy_ck),
1636 CLK("omap_i2c.1", "ick", &dummy_ck), 1636 CLK("omap_i2c.1", "ick", &dummy_ck),
1637 CLK("omap_i2c.2", "ick", &dummy_ck), 1637 CLK("omap_i2c.2", "ick", &dummy_ck),
1638 CLK("omap_i2c.3", "ick", &dummy_ck), 1638 CLK("omap_i2c.3", "ick", &dummy_ck),
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index c443f2e97e10..4c8982ae9529 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -143,7 +143,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
143 * Call idle CPU cluster PM exit notifier chain 143 * Call idle CPU cluster PM exit notifier chain
144 * to restore GIC and wakeupgen context. 144 * to restore GIC and wakeupgen context.
145 */ 145 */
146 if ((cx->mpu_state == PWRDM_POWER_RET) && 146 if (dev->cpu == 0 && (cx->mpu_state == PWRDM_POWER_RET) &&
147 (cx->mpu_logic_state == PWRDM_POWER_OFF)) 147 (cx->mpu_logic_state == PWRDM_POWER_OFF))
148 cpu_cluster_pm_exit(); 148 cpu_cluster_pm_exit();
149 149
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 9f4795aff48a..579697adaae7 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -1491,8 +1491,8 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
1491 */ 1491 */
1492 ret = gpmc_cs_remap(cs, res.start); 1492 ret = gpmc_cs_remap(cs, res.start);
1493 if (ret < 0) { 1493 if (ret < 0) {
1494 dev_err(&pdev->dev, "cannot remap GPMC CS %d to 0x%x\n", 1494 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
1495 cs, res.start); 1495 cs, &res.start);
1496 goto err; 1496 goto err;
1497 } 1497 }
1498 1498
diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
index c53609f46294..be271f1d585b 100644
--- a/arch/arm/mach-omap2/mux34xx.c
+++ b/arch/arm/mach-omap2/mux34xx.c
@@ -620,7 +620,7 @@ static struct omap_mux __initdata omap3_muxmodes[] = {
620 "uart1_rts", "ssi1_flag_tx", NULL, NULL, 620 "uart1_rts", "ssi1_flag_tx", NULL, NULL,
621 "gpio_149", NULL, NULL, "safe_mode"), 621 "gpio_149", NULL, NULL, "safe_mode"),
622 _OMAP3_MUXENTRY(UART1_RX, 151, 622 _OMAP3_MUXENTRY(UART1_RX, 151,
623 "uart1_rx", "ss1_wake_tx", "mcbsp1_clkr", "mcspi4_clk", 623 "uart1_rx", "ssi1_wake_tx", "mcbsp1_clkr", "mcspi4_clk",
624 "gpio_151", NULL, NULL, "safe_mode"), 624 "gpio_151", NULL, NULL, "safe_mode"),
625 _OMAP3_MUXENTRY(UART1_TX, 148, 625 _OMAP3_MUXENTRY(UART1_TX, 148,
626 "uart1_tx", "ssi1_dat_tx", NULL, NULL, 626 "uart1_tx", "ssi1_dat_tx", NULL, NULL,
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 8708b2a9da45..891211093295 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * OMAP4 SMP source file. It contains platform specific fucntions 2 * OMAP4 SMP source file. It contains platform specific functions
3 * needed for the linux smp kernel. 3 * needed for the linux smp kernel.
4 * 4 *
5 * Copyright (C) 2009 Texas Instruments, Inc. 5 * Copyright (C) 2009 Texas Instruments, Inc.
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index f99f68e1e85b..b69dd9abb50a 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -158,7 +158,7 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
158 } 158 }
159 159
160 od = omap_device_alloc(pdev, hwmods, oh_cnt); 160 od = omap_device_alloc(pdev, hwmods, oh_cnt);
161 if (!od) { 161 if (IS_ERR(od)) {
162 dev_err(&pdev->dev, "Cannot allocate omap_device for :%s\n", 162 dev_err(&pdev->dev, "Cannot allocate omap_device for :%s\n",
163 oh_name); 163 oh_name);
164 ret = PTR_ERR(od); 164 ret = PTR_ERR(od);
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index 612a45689770..7fb96ebdc0fb 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -289,7 +289,7 @@ static void collie_flash_exit(void)
289} 289}
290 290
291static struct flash_platform_data collie_flash_data = { 291static struct flash_platform_data collie_flash_data = {
292 .map_name = "cfi_probe", 292 .map_name = "jedec_probe",
293 .init = collie_flash_init, 293 .init = collie_flash_init,
294 .set_vpp = collie_set_vpp, 294 .set_vpp = collie_set_vpp,
295 .exit = collie_flash_exit, 295 .exit = collie_flash_exit,
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index 8ea5ef6c79cc..5bd2e851e3c7 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -555,7 +555,7 @@ static struct clk_lookup lookups[] = {
555 CLKDEV_CON_ID("pll2h", &pll2h_clk), 555 CLKDEV_CON_ID("pll2h", &pll2h_clk),
556 556
557 /* CPU clock */ 557 /* CPU clock */
558 CLKDEV_DEV_ID("cpufreq-cpu0", &z_clk), 558 CLKDEV_DEV_ID("cpu0", &z_clk),
559 559
560 /* DIV6 */ 560 /* DIV6 */
561 CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]), 561 CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]),
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 1942eaef5181..c92c023f0d27 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -616,7 +616,7 @@ static struct clk_lookup lookups[] = {
616 CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */ 616 CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */
617 617
618 /* DIV4 clocks */ 618 /* DIV4 clocks */
619 CLKDEV_DEV_ID("cpufreq-cpu0", &div4_clks[DIV4_Z]), 619 CLKDEV_DEV_ID("cpu0", &div4_clks[DIV4_Z]),
620 620
621 /* DIV6 clocks */ 621 /* DIV6 clocks */
622 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), 622 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index a85adcd00882..a1659863bfd5 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -1,7 +1,3 @@
1menu "ST-Ericsson AB U300/U335 Platform"
2
3comment "ST-Ericsson Mobile Platform Products"
4
5config ARCH_U300 1config ARCH_U300
6 bool "ST-Ericsson U300 Series" if ARCH_MULTI_V5 2 bool "ST-Ericsson U300 Series" if ARCH_MULTI_V5
7 depends on MMU 3 depends on MMU
@@ -25,7 +21,9 @@ config ARCH_U300
25 help 21 help
26 Support for ST-Ericsson U300 series mobile platforms. 22 Support for ST-Ericsson U300 series mobile platforms.
27 23
28comment "ST-Ericsson U300/U335 Feature Selections" 24if ARCH_U300
25
26menu "ST-Ericsson AB U300/U335 Platform"
29 27
30config MACH_U300 28config MACH_U300
31 depends on ARCH_U300 29 depends on ARCH_U300
@@ -53,3 +51,5 @@ config MACH_U300_SPIDUMMY
53 SPI framework and ARM PL022 support. 51 SPI framework and ARM PL022 support.
54 52
55endmenu 53endmenu
54
55endif
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index 82ccf1d98735..264f894c0e3d 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -69,6 +69,7 @@ static int __init ux500_l2x0_init(void)
69 * some SMI service available. 69 * some SMI service available.
70 */ 70 */
71 outer_cache.disable = NULL; 71 outer_cache.disable = NULL;
72 outer_cache.set_debug = NULL;
72 73
73 return 0; 74 return 0;
74} 75}
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index 6d4482fa35bc..e2950b098e76 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -43,6 +43,6 @@
43 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\ 43 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
44 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV) 44 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV)
45 45
46extern unsigned int elf_hwcap; 46extern unsigned long elf_hwcap;
47#endif 47#endif
48#endif 48#endif
diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 57fb55c44c90..7ae8a1f00c3c 100644
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -143,15 +143,26 @@ void machine_restart(char *cmd)
143 143
144void __show_regs(struct pt_regs *regs) 144void __show_regs(struct pt_regs *regs)
145{ 145{
146 int i; 146 int i, top_reg;
147 u64 lr, sp;
148
149 if (compat_user_mode(regs)) {
150 lr = regs->compat_lr;
151 sp = regs->compat_sp;
152 top_reg = 12;
153 } else {
154 lr = regs->regs[30];
155 sp = regs->sp;
156 top_reg = 29;
157 }
147 158
148 show_regs_print_info(KERN_DEFAULT); 159 show_regs_print_info(KERN_DEFAULT);
149 print_symbol("PC is at %s\n", instruction_pointer(regs)); 160 print_symbol("PC is at %s\n", instruction_pointer(regs));
150 print_symbol("LR is at %s\n", regs->regs[30]); 161 print_symbol("LR is at %s\n", lr);
151 printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n", 162 printk("pc : [<%016llx>] lr : [<%016llx>] pstate: %08llx\n",
152 regs->pc, regs->regs[30], regs->pstate); 163 regs->pc, lr, regs->pstate);
153 printk("sp : %016llx\n", regs->sp); 164 printk("sp : %016llx\n", sp);
154 for (i = 29; i >= 0; i--) { 165 for (i = top_reg; i >= 0; i--) {
155 printk("x%-2d: %016llx ", i, regs->regs[i]); 166 printk("x%-2d: %016llx ", i, regs->regs[i]);
156 if (i % 2 == 0) 167 if (i % 2 == 0)
157 printk("\n"); 168 printk("\n");
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index 12ad8f3d0cfd..055cfb80e05c 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -57,7 +57,7 @@
57unsigned int processor_id; 57unsigned int processor_id;
58EXPORT_SYMBOL(processor_id); 58EXPORT_SYMBOL(processor_id);
59 59
60unsigned int elf_hwcap __read_mostly; 60unsigned long elf_hwcap __read_mostly;
61EXPORT_SYMBOL_GPL(elf_hwcap); 61EXPORT_SYMBOL_GPL(elf_hwcap);
62 62
63static const char *cpu_name; 63static const char *cpu_name;
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index 6d6acf153bff..c23751b06120 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -130,7 +130,7 @@ static void __do_user_fault(struct task_struct *tsk, unsigned long addr,
130 force_sig_info(sig, &si, tsk); 130 force_sig_info(sig, &si, tsk);
131} 131}
132 132
133void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *regs) 133static void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *regs)
134{ 134{
135 struct task_struct *tsk = current; 135 struct task_struct *tsk = current;
136 struct mm_struct *mm = tsk->active_mm; 136 struct mm_struct *mm = tsk->active_mm;
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 75a36ad11ff5..ca8f8340d75f 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -288,9 +288,6 @@ endif
288vmlinux.32: vmlinux 288vmlinux.32: vmlinux
289 $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@ 289 $(OBJCOPY) -O $(32bit-bfd) $(OBJCOPYFLAGS) $< $@
290 290
291
292#obj-$(CONFIG_KPROBES) += kprobes.o
293
294# 291#
295# The 64-bit ELF tools are pretty broken so at this time we generate 64-bit 292# The 64-bit ELF tools are pretty broken so at this time we generate 64-bit
296# ELF files from 32-bit files by conversion. 293# ELF files from 32-bit files by conversion.
diff --git a/arch/mips/alchemy/common/usb.c b/arch/mips/alchemy/common/usb.c
index fcc695626117..2adc7edda49c 100644
--- a/arch/mips/alchemy/common/usb.c
+++ b/arch/mips/alchemy/common/usb.c
@@ -14,6 +14,7 @@
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/spinlock.h> 15#include <linux/spinlock.h>
16#include <linux/syscore_ops.h> 16#include <linux/syscore_ops.h>
17#include <asm/cpu.h>
17#include <asm/mach-au1x00/au1000.h> 18#include <asm/mach-au1x00/au1000.h>
18 19
19/* control register offsets */ 20/* control register offsets */
@@ -358,7 +359,7 @@ static inline int au1200_coherency_bug(void)
358{ 359{
359#if defined(CONFIG_DMA_COHERENT) 360#if defined(CONFIG_DMA_COHERENT)
360 /* Au1200 AB USB does not support coherent memory */ 361 /* Au1200 AB USB does not support coherent memory */
361 if (!(read_c0_prid() & 0xff)) { 362 if (!(read_c0_prid() & PRID_REV_MASK)) {
362 printk(KERN_INFO "Au1200 USB: this is chip revision AB !!\n"); 363 printk(KERN_INFO "Au1200 USB: this is chip revision AB !!\n");
363 printk(KERN_INFO "Au1200 USB: update your board or re-configure" 364 printk(KERN_INFO "Au1200 USB: update your board or re-configure"
364 " the kernel\n"); 365 " the kernel\n");
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index 7e17374a9ae8..b713cd64b087 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -306,14 +306,14 @@ void __init bcm63xx_cpu_init(void)
306 306
307 switch (c->cputype) { 307 switch (c->cputype) {
308 case CPU_BMIPS3300: 308 case CPU_BMIPS3300:
309 if ((read_c0_prid() & 0xff00) != PRID_IMP_BMIPS3300_ALT) 309 if ((read_c0_prid() & PRID_IMP_MASK) != PRID_IMP_BMIPS3300_ALT)
310 __cpu_name[cpu] = "Broadcom BCM6338"; 310 __cpu_name[cpu] = "Broadcom BCM6338";
311 /* fall-through */ 311 /* fall-through */
312 case CPU_BMIPS32: 312 case CPU_BMIPS32:
313 chipid_reg = BCM_6345_PERF_BASE; 313 chipid_reg = BCM_6345_PERF_BASE;
314 break; 314 break;
315 case CPU_BMIPS4350: 315 case CPU_BMIPS4350:
316 switch ((read_c0_prid() & 0xff)) { 316 switch ((read_c0_prid() & PRID_REV_MASK)) {
317 case 0x04: 317 case 0x04:
318 chipid_reg = BCM_3368_PERF_BASE; 318 chipid_reg = BCM_3368_PERF_BASE;
319 break; 319 break;
diff --git a/arch/mips/boot/dts/include/dt-bindings b/arch/mips/boot/dts/include/dt-bindings
index 68ae3887b3e5..08c00e4972fa 120000
--- a/arch/mips/boot/dts/include/dt-bindings
+++ b/arch/mips/boot/dts/include/dt-bindings
@@ -1 +1 @@
../../../../../include/dt-bindings ../../../../../include/dt-bindings \ No newline at end of file
diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c
index 02193953eb9e..b752c4ed0b79 100644
--- a/arch/mips/cavium-octeon/csrc-octeon.c
+++ b/arch/mips/cavium-octeon/csrc-octeon.c
@@ -12,6 +12,7 @@
12#include <linux/smp.h> 12#include <linux/smp.h>
13 13
14#include <asm/cpu-info.h> 14#include <asm/cpu-info.h>
15#include <asm/cpu-type.h>
15#include <asm/time.h> 16#include <asm/time.h>
16 17
17#include <asm/octeon/octeon.h> 18#include <asm/octeon/octeon.h>
diff --git a/arch/mips/dec/prom/init.c b/arch/mips/dec/prom/init.c
index ab169046e442..468f665de7bb 100644
--- a/arch/mips/dec/prom/init.c
+++ b/arch/mips/dec/prom/init.c
@@ -13,6 +13,7 @@
13 13
14#include <asm/bootinfo.h> 14#include <asm/bootinfo.h>
15#include <asm/cpu.h> 15#include <asm/cpu.h>
16#include <asm/cpu-type.h>
16#include <asm/processor.h> 17#include <asm/processor.h>
17 18
18#include <asm/dec/prom.h> 19#include <asm/dec/prom.h>
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index fa44f3ec5302..51680d15ca8e 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -13,12 +13,6 @@
13#include <asm/cpu-info.h> 13#include <asm/cpu-info.h>
14#include <cpu-feature-overrides.h> 14#include <cpu-feature-overrides.h>
15 15
16#ifndef current_cpu_type
17#define current_cpu_type() current_cpu_data.cputype
18#endif
19
20#define boot_cpu_type() cpu_data[0].cputype
21
22/* 16/*
23 * SMP assumption: Options of CPU 0 are a superset of all processors. 17 * SMP assumption: Options of CPU 0 are a superset of all processors.
24 * This is true for all known MIPS systems. 18 * This is true for all known MIPS systems.
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index 41401d8eb7d1..21c8e29c8f91 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -84,6 +84,7 @@ struct cpuinfo_mips {
84extern struct cpuinfo_mips cpu_data[]; 84extern struct cpuinfo_mips cpu_data[];
85#define current_cpu_data cpu_data[smp_processor_id()] 85#define current_cpu_data cpu_data[smp_processor_id()]
86#define raw_current_cpu_data cpu_data[raw_smp_processor_id()] 86#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
87#define boot_cpu_data cpu_data[0]
87 88
88extern void cpu_probe(void); 89extern void cpu_probe(void);
89extern void cpu_report(void); 90extern void cpu_report(void);
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
new file mode 100644
index 000000000000..4a402cc60c03
--- /dev/null
+++ b/arch/mips/include/asm/cpu-type.h
@@ -0,0 +1,203 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Ralf Baechle
7 * Copyright (C) 2004 Maciej W. Rozycki
8 */
9#ifndef __ASM_CPU_TYPE_H
10#define __ASM_CPU_TYPE_H
11
12#include <linux/smp.h>
13#include <linux/compiler.h>
14
15static inline int __pure __get_cpu_type(const int cpu_type)
16{
17 switch (cpu_type) {
18#if defined(CONFIG_SYS_HAS_CPU_LOONGSON2E) || \
19 defined(CONFIG_SYS_HAS_CPU_LOONGSON2F)
20 case CPU_LOONGSON2:
21#endif
22
23#ifdef CONFIG_SYS_HAS_CPU_LOONGSON1B
24 case CPU_LOONGSON1:
25#endif
26
27#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1
28 case CPU_4KC:
29 case CPU_ALCHEMY:
30 case CPU_BMIPS3300:
31 case CPU_BMIPS4350:
32 case CPU_PR4450:
33 case CPU_BMIPS32:
34 case CPU_JZRISC:
35#endif
36
37#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R1) || \
38 defined(CONFIG_SYS_HAS_CPU_MIPS32_R2)
39 case CPU_4KEC:
40#endif
41
42#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R2
43 case CPU_4KSC:
44 case CPU_24K:
45 case CPU_34K:
46 case CPU_1004K:
47 case CPU_74K:
48 case CPU_M14KC:
49 case CPU_M14KEC:
50#endif
51
52#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1
53 case CPU_5KC:
54 case CPU_5KE:
55 case CPU_20KC:
56 case CPU_25KF:
57 case CPU_SB1:
58 case CPU_SB1A:
59#endif
60
61#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R2
62 /*
63 * All MIPS64 R2 processors have their own special symbols. That is,
64 * there currently is no pure R2 core
65 */
66#endif
67
68#ifdef CONFIG_SYS_HAS_CPU_R3000
69 case CPU_R2000:
70 case CPU_R3000:
71 case CPU_R3000A:
72 case CPU_R3041:
73 case CPU_R3051:
74 case CPU_R3052:
75 case CPU_R3081:
76 case CPU_R3081E:
77#endif
78
79#ifdef CONFIG_SYS_HAS_CPU_TX39XX
80 case CPU_TX3912:
81 case CPU_TX3922:
82 case CPU_TX3927:
83#endif
84
85#ifdef CONFIG_SYS_HAS_CPU_VR41XX
86 case CPU_VR41XX:
87 case CPU_VR4111:
88 case CPU_VR4121:
89 case CPU_VR4122:
90 case CPU_VR4131:
91 case CPU_VR4133:
92 case CPU_VR4181:
93 case CPU_VR4181A:
94#endif
95
96#ifdef CONFIG_SYS_HAS_CPU_R4300
97 case CPU_R4300:
98 case CPU_R4310:
99#endif
100
101#ifdef CONFIG_SYS_HAS_CPU_R4X00
102 case CPU_R4000PC:
103 case CPU_R4000SC:
104 case CPU_R4000MC:
105 case CPU_R4200:
106 case CPU_R4400PC:
107 case CPU_R4400SC:
108 case CPU_R4400MC:
109 case CPU_R4600:
110 case CPU_R4700:
111 case CPU_R4640:
112 case CPU_R4650:
113#endif
114
115#ifdef CONFIG_SYS_HAS_CPU_TX49XX
116 case CPU_TX49XX:
117#endif
118
119#ifdef CONFIG_SYS_HAS_CPU_R5000
120 case CPU_R5000:
121#endif
122
123#ifdef CONFIG_SYS_HAS_CPU_R5432
124 case CPU_R5432:
125#endif
126
127#ifdef CONFIG_SYS_HAS_CPU_R5500
128 case CPU_R5500:
129#endif
130
131#ifdef CONFIG_SYS_HAS_CPU_R6000
132 case CPU_R6000:
133 case CPU_R6000A:
134#endif
135
136#ifdef CONFIG_SYS_HAS_CPU_NEVADA
137 case CPU_NEVADA:
138#endif
139
140#ifdef CONFIG_SYS_HAS_CPU_R8000
141 case CPU_R8000:
142#endif
143
144#ifdef CONFIG_SYS_HAS_CPU_R10000
145 case CPU_R10000:
146 case CPU_R12000:
147 case CPU_R14000:
148#endif
149#ifdef CONFIG_SYS_HAS_CPU_RM7000
150 case CPU_RM7000:
151 case CPU_SR71000:
152#endif
153#ifdef CONFIG_SYS_HAS_CPU_RM9000
154 case CPU_RM9000:
155#endif
156#ifdef CONFIG_SYS_HAS_CPU_SB1
157 case CPU_SB1:
158 case CPU_SB1A:
159#endif
160#ifdef CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON
161 case CPU_CAVIUM_OCTEON:
162 case CPU_CAVIUM_OCTEON_PLUS:
163 case CPU_CAVIUM_OCTEON2:
164#endif
165
166#ifdef CONFIG_SYS_HAS_CPU_BMIPS4380
167 case CPU_BMIPS4380:
168#endif
169
170#ifdef CONFIG_SYS_HAS_CPU_BMIPS5000
171 case CPU_BMIPS5000:
172#endif
173
174#ifdef CONFIG_SYS_HAS_CPU_XLP
175 case CPU_XLP:
176#endif
177
178#ifdef CONFIG_SYS_HAS_CPU_XLR
179 case CPU_XLR:
180#endif
181 break;
182 default:
183 unreachable();
184 }
185
186 return cpu_type;
187}
188
189static inline int __pure current_cpu_type(void)
190{
191 const int cpu_type = current_cpu_data.cputype;
192
193 return __get_cpu_type(cpu_type);
194}
195
196static inline int __pure boot_cpu_type(void)
197{
198 const int cpu_type = cpu_data[0].cputype;
199
200 return __get_cpu_type(cpu_type);
201}
202
203#endif /* __ASM_CPU_TYPE_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 71b9f1998be7..d2035e16502a 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -3,15 +3,14 @@
3 * various MIPS cpu types. 3 * various MIPS cpu types.
4 * 4 *
5 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 5 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
6 * Copyright (C) 2004 Maciej W. Rozycki 6 * Copyright (C) 2004, 2013 Maciej W. Rozycki
7 */ 7 */
8#ifndef _ASM_CPU_H 8#ifndef _ASM_CPU_H
9#define _ASM_CPU_H 9#define _ASM_CPU_H
10 10
11/* Assigned Company values for bits 23:16 of the PRId Register 11/*
12 (CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from 12 As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
13 MTI, the PRId register is defined in this (backwards compatible) 13 register 15, select 0) is defined in this (backwards compatible) way:
14 way:
15 14
16 +----------------+----------------+----------------+----------------+ 15 +----------------+----------------+----------------+----------------+
17 | Company Options| Company ID | Processor ID | Revision | 16 | Company Options| Company ID | Processor ID | Revision |
@@ -23,6 +22,14 @@
23 spec. 22 spec.
24*/ 23*/
25 24
25#define PRID_OPT_MASK 0xff000000
26
27/*
28 * Assigned Company values for bits 23:16 of the PRId register.
29 */
30
31#define PRID_COMP_MASK 0xff0000
32
26#define PRID_COMP_LEGACY 0x000000 33#define PRID_COMP_LEGACY 0x000000
27#define PRID_COMP_MIPS 0x010000 34#define PRID_COMP_MIPS 0x010000
28#define PRID_COMP_BROADCOM 0x020000 35#define PRID_COMP_BROADCOM 0x020000
@@ -38,10 +45,17 @@
38#define PRID_COMP_INGENIC 0xd00000 45#define PRID_COMP_INGENIC 0xd00000
39 46
40/* 47/*
41 * Assigned values for the product ID register. In order to detect a 48 * Assigned Processor ID (implementation) values for bits 15:8 of the PRId
42 * certain CPU type exactly eventually additional registers may need to 49 * register. In order to detect a certain CPU type exactly eventually
43 * be examined. These are valid when 23:16 == PRID_COMP_LEGACY 50 * additional registers may need to be examined.
44 */ 51 */
52
53#define PRID_IMP_MASK 0xff00
54
55/*
56 * These are valid when 23:16 == PRID_COMP_LEGACY
57 */
58
45#define PRID_IMP_R2000 0x0100 59#define PRID_IMP_R2000 0x0100
46#define PRID_IMP_AU1_REV1 0x0100 60#define PRID_IMP_AU1_REV1 0x0100
47#define PRID_IMP_AU1_REV2 0x0200 61#define PRID_IMP_AU1_REV2 0x0200
@@ -182,11 +196,15 @@
182#define PRID_IMP_NETLOGIC_XLP2XX 0x1200 196#define PRID_IMP_NETLOGIC_XLP2XX 0x1200
183 197
184/* 198/*
185 * Definitions for 7:0 on legacy processors 199 * Particular Revision values for bits 7:0 of the PRId register.
186 */ 200 */
187 201
188#define PRID_REV_MASK 0x00ff 202#define PRID_REV_MASK 0x00ff
189 203
204/*
205 * Definitions for 7:0 on legacy processors
206 */
207
190#define PRID_REV_TX4927 0x0022 208#define PRID_REV_TX4927 0x0022
191#define PRID_REV_TX4937 0x0030 209#define PRID_REV_TX4937 0x0030
192#define PRID_REV_R4400 0x0040 210#define PRID_REV_R4400 0x0040
@@ -227,6 +245,8 @@
227 * 31 16 15 8 7 0 245 * 31 16 15 8 7 0
228 */ 246 */
229 247
248#define FPIR_IMP_MASK 0xff00
249
230#define FPIR_IMP_NONE 0x0000 250#define FPIR_IMP_NONE 0x0000
231 251
232enum cpu_type_enum { 252enum cpu_type_enum {
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 3e11a468cdf8..54f9e84db8ac 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -43,6 +43,8 @@
43#include <linux/io.h> 43#include <linux/io.h>
44#include <linux/irq.h> 44#include <linux/irq.h>
45 45
46#include <asm/cpu.h>
47
46/* cpu pipeline flush */ 48/* cpu pipeline flush */
47void static inline au_sync(void) 49void static inline au_sync(void)
48{ 50{
@@ -140,7 +142,7 @@ static inline int au1xxx_cpu_needs_config_od(void)
140 142
141static inline int alchemy_get_cputype(void) 143static inline int alchemy_get_cputype(void)
142{ 144{
143 switch (read_c0_prid() & 0xffff0000) { 145 switch (read_c0_prid() & (PRID_OPT_MASK | PRID_COMP_MASK)) {
144 case 0x00030000: 146 case 0x00030000:
145 return ALCHEMY_CPU_AU1000; 147 return ALCHEMY_CPU_AU1000;
146 break; 148 break;
diff --git a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
index f4caacd25552..1bcb6421205e 100644
--- a/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
@@ -8,6 +8,8 @@
8#ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H 8#ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H 9#define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
10 10
11#include <asm/cpu.h>
12
11/* 13/*
12 * IP22 with a variety of processors so we can't use defaults for everything. 14 * IP22 with a variety of processors so we can't use defaults for everything.
13 */ 15 */
diff --git a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
index 1d2b6ff60d33..d6111aa2e886 100644
--- a/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
@@ -8,6 +8,8 @@
8#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H 8#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H 9#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
10 10
11#include <asm/cpu.h>
12
11/* 13/*
12 * IP27 only comes with R10000 family processors all using the same config 14 * IP27 only comes with R10000 family processors all using the same config
13 */ 15 */
diff --git a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
index 65e9c856390d..4cec06d133db 100644
--- a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
@@ -9,6 +9,8 @@
9#ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H 9#ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
10#define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H 10#define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
11 11
12#include <asm/cpu.h>
13
12/* 14/*
13 * IP28 only comes with R10000 family processors all using the same config 15 * IP28 only comes with R10000 family processors all using the same config
14 */ 16 */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index fed1c3e9b486..e0331414c7d6 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -603,6 +603,13 @@
603#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 603#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
604#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) 604#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
605 605
606#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
607#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
608#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
609#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
610#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
611#define MIPS_CONF5_K (_ULCAST_(1) << 30)
612
606#define MIPS_CONF6_SYND (_ULCAST_(1) << 13) 613#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
607 614
608#define MIPS_CONF7_WII (_ULCAST_(1) << 31) 615#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index f194c08bd057..12d6842962be 100644
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -83,6 +83,18 @@ static inline void pcibios_penalize_isa_irq(int irq, int active)
83extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 83extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
84 enum pci_mmap_state mmap_state, int write_combine); 84 enum pci_mmap_state mmap_state, int write_combine);
85 85
86#define HAVE_ARCH_PCI_RESOURCE_TO_USER
87
88static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
89 const struct resource *rsrc, resource_size_t *start,
90 resource_size_t *end)
91{
92 phys_t size = resource_size(rsrc);
93
94 *start = fixup_bigphys_addr(rsrc->start, size);
95 *end = rsrc->start + size;
96}
97
86/* 98/*
87 * Dynamic DMA mapping stuff. 99 * Dynamic DMA mapping stuff.
88 * MIPS has everything mapped statically. 100 * MIPS has everything mapped statically.
diff --git a/arch/mips/include/asm/timex.h b/arch/mips/include/asm/timex.h
index 6529704aa73a..c5424757da65 100644
--- a/arch/mips/include/asm/timex.h
+++ b/arch/mips/include/asm/timex.h
@@ -10,7 +10,9 @@
10 10
11#ifdef __KERNEL__ 11#ifdef __KERNEL__
12 12
13#include <asm/cpu-features.h>
13#include <asm/mipsregs.h> 14#include <asm/mipsregs.h>
15#include <asm/cpu-type.h>
14 16
15/* 17/*
16 * This is the clock rate of the i8253 PIT. A MIPS system may not have 18 * This is the clock rate of the i8253 PIT. A MIPS system may not have
@@ -33,9 +35,38 @@
33 35
34typedef unsigned int cycles_t; 36typedef unsigned int cycles_t;
35 37
38/*
39 * On R4000/R4400 before version 5.0 an erratum exists such that if the
40 * cycle counter is read in the exact moment that it is matching the
41 * compare register, no interrupt will be generated.
42 *
43 * There is a suggested workaround and also the erratum can't strike if
44 * the compare interrupt isn't being used as the clock source device.
45 * However for now the implementaton of this function doesn't get these
46 * fine details right.
47 */
36static inline cycles_t get_cycles(void) 48static inline cycles_t get_cycles(void)
37{ 49{
38 return 0; 50 switch (boot_cpu_type()) {
51 case CPU_R4400PC:
52 case CPU_R4400SC:
53 case CPU_R4400MC:
54 if ((read_c0_prid() & 0xff) >= 0x0050)
55 return read_c0_count();
56 break;
57
58 case CPU_R4000PC:
59 case CPU_R4000SC:
60 case CPU_R4000MC:
61 break;
62
63 default:
64 if (cpu_has_counter)
65 return read_c0_count();
66 break;
67 }
68
69 return 0; /* no usable counter */
39} 70}
40 71
41#endif /* __KERNEL__ */ 72#endif /* __KERNEL__ */
diff --git a/arch/mips/include/asm/vga.h b/arch/mips/include/asm/vga.h
index f4cff7e4fa8a..f82c83749a08 100644
--- a/arch/mips/include/asm/vga.h
+++ b/arch/mips/include/asm/vga.h
@@ -6,6 +6,7 @@
6#ifndef _ASM_VGA_H 6#ifndef _ASM_VGA_H
7#define _ASM_VGA_H 7#define _ASM_VGA_H
8 8
9#include <asm/addrspace.h>
9#include <asm/byteorder.h> 10#include <asm/byteorder.h>
10 11
11/* 12/*
@@ -13,7 +14,7 @@
13 * access the videoram directly without any black magic. 14 * access the videoram directly without any black magic.
14 */ 15 */
15 16
16#define VGA_MAP_MEM(x, s) (0xb0000000L + (unsigned long)(x)) 17#define VGA_MAP_MEM(x, s) CKSEG1ADDR(0x10000000L + (unsigned long)(x))
17 18
18#define vga_readb(x) (*(x)) 19#define vga_readb(x) (*(x))
19#define vga_writeb(x, y) (*(y) = (x)) 20#define vga_writeb(x, y) (*(y) = (x))
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 37663c7862a5..5465dc183e5a 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -20,6 +20,7 @@
20 20
21#include <asm/bugs.h> 21#include <asm/bugs.h>
22#include <asm/cpu.h> 22#include <asm/cpu.h>
23#include <asm/cpu-type.h>
23#include <asm/fpu.h> 24#include <asm/fpu.h>
24#include <asm/mipsregs.h> 25#include <asm/mipsregs.h>
25#include <asm/watch.h> 26#include <asm/watch.h>
@@ -55,7 +56,7 @@ static inline void check_errata(void)
55{ 56{
56 struct cpuinfo_mips *c = &current_cpu_data; 57 struct cpuinfo_mips *c = &current_cpu_data;
57 58
58 switch (c->cputype) { 59 switch (current_cpu_type()) {
59 case CPU_34K: 60 case CPU_34K:
60 /* 61 /*
61 * Erratum "RPS May Cause Incorrect Instruction Execution" 62 * Erratum "RPS May Cause Incorrect Instruction Execution"
@@ -122,7 +123,7 @@ static inline unsigned long cpu_get_fpu_id(void)
122 */ 123 */
123static inline int __cpu_has_fpu(void) 124static inline int __cpu_has_fpu(void)
124{ 125{
125 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); 126 return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
126} 127}
127 128
128static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) 129static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
@@ -290,6 +291,17 @@ static inline unsigned int decode_config4(struct cpuinfo_mips *c)
290 return config4 & MIPS_CONF_M; 291 return config4 & MIPS_CONF_M;
291} 292}
292 293
294static inline unsigned int decode_config5(struct cpuinfo_mips *c)
295{
296 unsigned int config5;
297
298 config5 = read_c0_config5();
299 config5 &= ~MIPS_CONF5_UFR;
300 write_c0_config5(config5);
301
302 return config5 & MIPS_CONF_M;
303}
304
293static void decode_configs(struct cpuinfo_mips *c) 305static void decode_configs(struct cpuinfo_mips *c)
294{ 306{
295 int ok; 307 int ok;
@@ -310,6 +322,8 @@ static void decode_configs(struct cpuinfo_mips *c)
310 ok = decode_config3(c); 322 ok = decode_config3(c);
311 if (ok) 323 if (ok)
312 ok = decode_config4(c); 324 ok = decode_config4(c);
325 if (ok)
326 ok = decode_config5(c);
313 327
314 mips_probe_watch_registers(c); 328 mips_probe_watch_registers(c);
315 329
@@ -322,7 +336,7 @@ static void decode_configs(struct cpuinfo_mips *c)
322 336
323static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) 337static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
324{ 338{
325 switch (c->processor_id & 0xff00) { 339 switch (c->processor_id & PRID_IMP_MASK) {
326 case PRID_IMP_R2000: 340 case PRID_IMP_R2000:
327 c->cputype = CPU_R2000; 341 c->cputype = CPU_R2000;
328 __cpu_name[cpu] = "R2000"; 342 __cpu_name[cpu] = "R2000";
@@ -333,7 +347,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
333 c->tlbsize = 64; 347 c->tlbsize = 64;
334 break; 348 break;
335 case PRID_IMP_R3000: 349 case PRID_IMP_R3000:
336 if ((c->processor_id & 0xff) == PRID_REV_R3000A) { 350 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
337 if (cpu_has_confreg()) { 351 if (cpu_has_confreg()) {
338 c->cputype = CPU_R3081E; 352 c->cputype = CPU_R3081E;
339 __cpu_name[cpu] = "R3081"; 353 __cpu_name[cpu] = "R3081";
@@ -353,7 +367,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
353 break; 367 break;
354 case PRID_IMP_R4000: 368 case PRID_IMP_R4000:
355 if (read_c0_config() & CONF_SC) { 369 if (read_c0_config() & CONF_SC) {
356 if ((c->processor_id & 0xff) >= PRID_REV_R4400) { 370 if ((c->processor_id & PRID_REV_MASK) >=
371 PRID_REV_R4400) {
357 c->cputype = CPU_R4400PC; 372 c->cputype = CPU_R4400PC;
358 __cpu_name[cpu] = "R4400PC"; 373 __cpu_name[cpu] = "R4400PC";
359 } else { 374 } else {
@@ -361,7 +376,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
361 __cpu_name[cpu] = "R4000PC"; 376 __cpu_name[cpu] = "R4000PC";
362 } 377 }
363 } else { 378 } else {
364 if ((c->processor_id & 0xff) >= PRID_REV_R4400) { 379 if ((c->processor_id & PRID_REV_MASK) >=
380 PRID_REV_R4400) {
365 c->cputype = CPU_R4400SC; 381 c->cputype = CPU_R4400SC;
366 __cpu_name[cpu] = "R4400SC"; 382 __cpu_name[cpu] = "R4400SC";
367 } else { 383 } else {
@@ -454,7 +470,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
454 __cpu_name[cpu] = "TX3927"; 470 __cpu_name[cpu] = "TX3927";
455 c->tlbsize = 64; 471 c->tlbsize = 64;
456 } else { 472 } else {
457 switch (c->processor_id & 0xff) { 473 switch (c->processor_id & PRID_REV_MASK) {
458 case PRID_REV_TX3912: 474 case PRID_REV_TX3912:
459 c->cputype = CPU_TX3912; 475 c->cputype = CPU_TX3912;
460 __cpu_name[cpu] = "TX3912"; 476 __cpu_name[cpu] = "TX3912";
@@ -640,7 +656,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
640static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) 656static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
641{ 657{
642 decode_configs(c); 658 decode_configs(c);
643 switch (c->processor_id & 0xff00) { 659 switch (c->processor_id & PRID_IMP_MASK) {
644 case PRID_IMP_4KC: 660 case PRID_IMP_4KC:
645 c->cputype = CPU_4KC; 661 c->cputype = CPU_4KC;
646 __cpu_name[cpu] = "MIPS 4Kc"; 662 __cpu_name[cpu] = "MIPS 4Kc";
@@ -711,7 +727,7 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
711static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) 727static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
712{ 728{
713 decode_configs(c); 729 decode_configs(c);
714 switch (c->processor_id & 0xff00) { 730 switch (c->processor_id & PRID_IMP_MASK) {
715 case PRID_IMP_AU1_REV1: 731 case PRID_IMP_AU1_REV1:
716 case PRID_IMP_AU1_REV2: 732 case PRID_IMP_AU1_REV2:
717 c->cputype = CPU_ALCHEMY; 733 c->cputype = CPU_ALCHEMY;
@@ -730,7 +746,7 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
730 break; 746 break;
731 case 4: 747 case 4:
732 __cpu_name[cpu] = "Au1200"; 748 __cpu_name[cpu] = "Au1200";
733 if ((c->processor_id & 0xff) == 2) 749 if ((c->processor_id & PRID_REV_MASK) == 2)
734 __cpu_name[cpu] = "Au1250"; 750 __cpu_name[cpu] = "Au1250";
735 break; 751 break;
736 case 5: 752 case 5:
@@ -748,12 +764,12 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
748{ 764{
749 decode_configs(c); 765 decode_configs(c);
750 766
751 switch (c->processor_id & 0xff00) { 767 switch (c->processor_id & PRID_IMP_MASK) {
752 case PRID_IMP_SB1: 768 case PRID_IMP_SB1:
753 c->cputype = CPU_SB1; 769 c->cputype = CPU_SB1;
754 __cpu_name[cpu] = "SiByte SB1"; 770 __cpu_name[cpu] = "SiByte SB1";
755 /* FPU in pass1 is known to have issues. */ 771 /* FPU in pass1 is known to have issues. */
756 if ((c->processor_id & 0xff) < 0x02) 772 if ((c->processor_id & PRID_REV_MASK) < 0x02)
757 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); 773 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
758 break; 774 break;
759 case PRID_IMP_SB1A: 775 case PRID_IMP_SB1A:
@@ -766,7 +782,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
766static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) 782static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
767{ 783{
768 decode_configs(c); 784 decode_configs(c);
769 switch (c->processor_id & 0xff00) { 785 switch (c->processor_id & PRID_IMP_MASK) {
770 case PRID_IMP_SR71000: 786 case PRID_IMP_SR71000:
771 c->cputype = CPU_SR71000; 787 c->cputype = CPU_SR71000;
772 __cpu_name[cpu] = "Sandcraft SR71000"; 788 __cpu_name[cpu] = "Sandcraft SR71000";
@@ -779,7 +795,7 @@ static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
779static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) 795static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
780{ 796{
781 decode_configs(c); 797 decode_configs(c);
782 switch (c->processor_id & 0xff00) { 798 switch (c->processor_id & PRID_IMP_MASK) {
783 case PRID_IMP_PR4450: 799 case PRID_IMP_PR4450:
784 c->cputype = CPU_PR4450; 800 c->cputype = CPU_PR4450;
785 __cpu_name[cpu] = "Philips PR4450"; 801 __cpu_name[cpu] = "Philips PR4450";
@@ -791,7 +807,7 @@ static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
791static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) 807static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
792{ 808{
793 decode_configs(c); 809 decode_configs(c);
794 switch (c->processor_id & 0xff00) { 810 switch (c->processor_id & PRID_IMP_MASK) {
795 case PRID_IMP_BMIPS32_REV4: 811 case PRID_IMP_BMIPS32_REV4:
796 case PRID_IMP_BMIPS32_REV8: 812 case PRID_IMP_BMIPS32_REV8:
797 c->cputype = CPU_BMIPS32; 813 c->cputype = CPU_BMIPS32;
@@ -806,7 +822,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
806 set_elf_platform(cpu, "bmips3300"); 822 set_elf_platform(cpu, "bmips3300");
807 break; 823 break;
808 case PRID_IMP_BMIPS43XX: { 824 case PRID_IMP_BMIPS43XX: {
809 int rev = c->processor_id & 0xff; 825 int rev = c->processor_id & PRID_REV_MASK;
810 826
811 if (rev >= PRID_REV_BMIPS4380_LO && 827 if (rev >= PRID_REV_BMIPS4380_LO &&
812 rev <= PRID_REV_BMIPS4380_HI) { 828 rev <= PRID_REV_BMIPS4380_HI) {
@@ -832,7 +848,7 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
832static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) 848static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
833{ 849{
834 decode_configs(c); 850 decode_configs(c);
835 switch (c->processor_id & 0xff00) { 851 switch (c->processor_id & PRID_IMP_MASK) {
836 case PRID_IMP_CAVIUM_CN38XX: 852 case PRID_IMP_CAVIUM_CN38XX:
837 case PRID_IMP_CAVIUM_CN31XX: 853 case PRID_IMP_CAVIUM_CN31XX:
838 case PRID_IMP_CAVIUM_CN30XX: 854 case PRID_IMP_CAVIUM_CN30XX:
@@ -875,7 +891,7 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
875 decode_configs(c); 891 decode_configs(c);
876 /* JZRISC does not implement the CP0 counter. */ 892 /* JZRISC does not implement the CP0 counter. */
877 c->options &= ~MIPS_CPU_COUNTER; 893 c->options &= ~MIPS_CPU_COUNTER;
878 switch (c->processor_id & 0xff00) { 894 switch (c->processor_id & PRID_IMP_MASK) {
879 case PRID_IMP_JZRISC: 895 case PRID_IMP_JZRISC:
880 c->cputype = CPU_JZRISC; 896 c->cputype = CPU_JZRISC;
881 __cpu_name[cpu] = "Ingenic JZRISC"; 897 __cpu_name[cpu] = "Ingenic JZRISC";
@@ -890,7 +906,7 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
890{ 906{
891 decode_configs(c); 907 decode_configs(c);
892 908
893 if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) { 909 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
894 c->cputype = CPU_ALCHEMY; 910 c->cputype = CPU_ALCHEMY;
895 __cpu_name[cpu] = "Au1300"; 911 __cpu_name[cpu] = "Au1300";
896 /* following stuff is not for Alchemy */ 912 /* following stuff is not for Alchemy */
@@ -905,7 +921,7 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
905 MIPS_CPU_EJTAG | 921 MIPS_CPU_EJTAG |
906 MIPS_CPU_LLSC); 922 MIPS_CPU_LLSC);
907 923
908 switch (c->processor_id & 0xff00) { 924 switch (c->processor_id & PRID_IMP_MASK) {
909 case PRID_IMP_NETLOGIC_XLP2XX: 925 case PRID_IMP_NETLOGIC_XLP2XX:
910 c->cputype = CPU_XLP; 926 c->cputype = CPU_XLP;
911 __cpu_name[cpu] = "Broadcom XLPII"; 927 __cpu_name[cpu] = "Broadcom XLPII";
@@ -984,7 +1000,7 @@ void cpu_probe(void)
984 c->cputype = CPU_UNKNOWN; 1000 c->cputype = CPU_UNKNOWN;
985 1001
986 c->processor_id = read_c0_prid(); 1002 c->processor_id = read_c0_prid();
987 switch (c->processor_id & 0xff0000) { 1003 switch (c->processor_id & PRID_COMP_MASK) {
988 case PRID_COMP_LEGACY: 1004 case PRID_COMP_LEGACY:
989 cpu_probe_legacy(c, cpu); 1005 cpu_probe_legacy(c, cpu);
990 break; 1006 break;
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 42f8875d2444..f7991d95bff9 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -18,6 +18,7 @@
18#include <linux/sched.h> 18#include <linux/sched.h>
19#include <asm/cpu.h> 19#include <asm/cpu.h>
20#include <asm/cpu-info.h> 20#include <asm/cpu-info.h>
21#include <asm/cpu-type.h>
21#include <asm/idle.h> 22#include <asm/idle.h>
22#include <asm/mipsregs.h> 23#include <asm/mipsregs.h>
23 24
@@ -136,7 +137,7 @@ void __init check_wait(void)
136 return; 137 return;
137 } 138 }
138 139
139 switch (c->cputype) { 140 switch (current_cpu_type()) {
140 case CPU_R3081: 141 case CPU_R3081:
141 case CPU_R3081E: 142 case CPU_R3081E:
142 cpu_wait = r3081_wait; 143 cpu_wait = r3081_wait;
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 364d26ae4215..dcb8e5d3bb8a 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -24,6 +24,7 @@
24#include <linux/export.h> 24#include <linux/export.h>
25 25
26#include <asm/cpu-features.h> 26#include <asm/cpu-features.h>
27#include <asm/cpu-type.h>
27#include <asm/div64.h> 28#include <asm/div64.h>
28#include <asm/smtc_ipi.h> 29#include <asm/smtc_ipi.h>
29#include <asm/time.h> 30#include <asm/time.h>
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index aec3408edd4b..524841f02803 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -39,6 +39,7 @@
39#include <asm/break.h> 39#include <asm/break.h>
40#include <asm/cop2.h> 40#include <asm/cop2.h>
41#include <asm/cpu.h> 41#include <asm/cpu.h>
42#include <asm/cpu-type.h>
42#include <asm/dsp.h> 43#include <asm/dsp.h>
43#include <asm/fpu.h> 44#include <asm/fpu.h>
44#include <asm/fpu_emulator.h> 45#include <asm/fpu_emulator.h>
@@ -622,7 +623,7 @@ static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
622 regs->regs[rt] = read_c0_count(); 623 regs->regs[rt] = read_c0_count();
623 return 0; 624 return 0;
624 case 3: /* Count register resolution */ 625 case 3: /* Count register resolution */
625 switch (current_cpu_data.cputype) { 626 switch (current_cpu_type()) {
626 case CPU_20KC: 627 case CPU_20KC:
627 case CPU_25KF: 628 case CPU_25KF:
628 regs->regs[rt] = 1; 629 regs->regs[rt] = 1;
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 729e7702b1de..c8efdb5b6ee0 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -19,6 +19,7 @@
19#include <asm/bootinfo.h> 19#include <asm/bootinfo.h>
20#include <asm/cacheops.h> 20#include <asm/cacheops.h>
21#include <asm/cpu-features.h> 21#include <asm/cpu-features.h>
22#include <asm/cpu-type.h>
22#include <asm/page.h> 23#include <asm/page.h>
23#include <asm/pgtable.h> 24#include <asm/pgtable.h>
24#include <asm/r4kcache.h> 25#include <asm/r4kcache.h>
@@ -186,9 +187,10 @@ static void probe_octeon(void)
186 unsigned long dcache_size; 187 unsigned long dcache_size;
187 unsigned int config1; 188 unsigned int config1;
188 struct cpuinfo_mips *c = &current_cpu_data; 189 struct cpuinfo_mips *c = &current_cpu_data;
190 int cputype = current_cpu_type();
189 191
190 config1 = read_c0_config1(); 192 config1 = read_c0_config1();
191 switch (c->cputype) { 193 switch (cputype) {
192 case CPU_CAVIUM_OCTEON: 194 case CPU_CAVIUM_OCTEON:
193 case CPU_CAVIUM_OCTEON_PLUS: 195 case CPU_CAVIUM_OCTEON_PLUS:
194 c->icache.linesz = 2 << ((config1 >> 19) & 7); 196 c->icache.linesz = 2 << ((config1 >> 19) & 7);
@@ -199,7 +201,7 @@ static void probe_octeon(void)
199 c->icache.sets * c->icache.ways * c->icache.linesz; 201 c->icache.sets * c->icache.ways * c->icache.linesz;
200 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; 202 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
201 c->dcache.linesz = 128; 203 c->dcache.linesz = 128;
202 if (c->cputype == CPU_CAVIUM_OCTEON_PLUS) 204 if (cputype == CPU_CAVIUM_OCTEON_PLUS)
203 c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ 205 c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
204 else 206 else
205 c->dcache.sets = 1; /* CN3XXX has one Dcache set */ 207 c->dcache.sets = 1; /* CN3XXX has one Dcache set */
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index f749f687ee87..627883bc6d5f 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -12,6 +12,7 @@
12#include <linux/highmem.h> 12#include <linux/highmem.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/linkage.h> 14#include <linux/linkage.h>
15#include <linux/preempt.h>
15#include <linux/sched.h> 16#include <linux/sched.h>
16#include <linux/smp.h> 17#include <linux/smp.h>
17#include <linux/mm.h> 18#include <linux/mm.h>
@@ -24,6 +25,7 @@
24#include <asm/cacheops.h> 25#include <asm/cacheops.h>
25#include <asm/cpu.h> 26#include <asm/cpu.h>
26#include <asm/cpu-features.h> 27#include <asm/cpu-features.h>
28#include <asm/cpu-type.h>
27#include <asm/io.h> 29#include <asm/io.h>
28#include <asm/page.h> 30#include <asm/page.h>
29#include <asm/pgtable.h> 31#include <asm/pgtable.h>
@@ -601,6 +603,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
601 /* Catch bad driver code */ 603 /* Catch bad driver code */
602 BUG_ON(size == 0); 604 BUG_ON(size == 0);
603 605
606 preempt_disable();
604 if (cpu_has_inclusive_pcaches) { 607 if (cpu_has_inclusive_pcaches) {
605 if (size >= scache_size) 608 if (size >= scache_size)
606 r4k_blast_scache(); 609 r4k_blast_scache();
@@ -621,6 +624,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
621 R4600_HIT_CACHEOP_WAR_IMPL; 624 R4600_HIT_CACHEOP_WAR_IMPL;
622 blast_dcache_range(addr, addr + size); 625 blast_dcache_range(addr, addr + size);
623 } 626 }
627 preempt_enable();
624 628
625 bc_wback_inv(addr, size); 629 bc_wback_inv(addr, size);
626 __sync(); 630 __sync();
@@ -631,6 +635,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
631 /* Catch bad driver code */ 635 /* Catch bad driver code */
632 BUG_ON(size == 0); 636 BUG_ON(size == 0);
633 637
638 preempt_disable();
634 if (cpu_has_inclusive_pcaches) { 639 if (cpu_has_inclusive_pcaches) {
635 if (size >= scache_size) 640 if (size >= scache_size)
636 r4k_blast_scache(); 641 r4k_blast_scache();
@@ -655,6 +660,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
655 R4600_HIT_CACHEOP_WAR_IMPL; 660 R4600_HIT_CACHEOP_WAR_IMPL;
656 blast_inv_dcache_range(addr, addr + size); 661 blast_inv_dcache_range(addr, addr + size);
657 } 662 }
663 preempt_enable();
658 664
659 bc_inv(addr, size); 665 bc_inv(addr, size);
660 __sync(); 666 __sync();
@@ -780,20 +786,30 @@ static inline void rm7k_erratum31(void)
780 786
781static inline void alias_74k_erratum(struct cpuinfo_mips *c) 787static inline void alias_74k_erratum(struct cpuinfo_mips *c)
782{ 788{
789 unsigned int imp = c->processor_id & PRID_IMP_MASK;
790 unsigned int rev = c->processor_id & PRID_REV_MASK;
791
783 /* 792 /*
784 * Early versions of the 74K do not update the cache tags on a 793 * Early versions of the 74K do not update the cache tags on a
785 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG 794 * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
786 * aliases. In this case it is better to treat the cache as always 795 * aliases. In this case it is better to treat the cache as always
787 * having aliases. 796 * having aliases.
788 */ 797 */
789 if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0)) 798 switch (imp) {
790 c->dcache.flags |= MIPS_CACHE_VTAG; 799 case PRID_IMP_74K:
791 if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0)) 800 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
792 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); 801 c->dcache.flags |= MIPS_CACHE_VTAG;
793 if (((c->processor_id & 0xff00) == PRID_IMP_1074K) && 802 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
794 ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) { 803 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
795 c->dcache.flags |= MIPS_CACHE_VTAG; 804 break;
796 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND); 805 case PRID_IMP_1074K:
806 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
807 c->dcache.flags |= MIPS_CACHE_VTAG;
808 write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
809 }
810 break;
811 default:
812 BUG();
797 } 813 }
798} 814}
799 815
@@ -809,7 +825,7 @@ static void probe_pcache(void)
809 unsigned long config1; 825 unsigned long config1;
810 unsigned int lsize; 826 unsigned int lsize;
811 827
812 switch (c->cputype) { 828 switch (current_cpu_type()) {
813 case CPU_R4600: /* QED style two way caches? */ 829 case CPU_R4600: /* QED style two way caches? */
814 case CPU_R4700: 830 case CPU_R4700:
815 case CPU_R5000: 831 case CPU_R5000:
@@ -1025,7 +1041,8 @@ static void probe_pcache(void)
1025 * presumably no vendor is shipping his hardware in the "bad" 1041 * presumably no vendor is shipping his hardware in the "bad"
1026 * configuration. 1042 * configuration.
1027 */ 1043 */
1028 if ((prid & 0xff00) == PRID_IMP_R4000 && (prid & 0xff) < 0x40 && 1044 if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
1045 (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
1029 !(config & CONF_SC) && c->icache.linesz != 16 && 1046 !(config & CONF_SC) && c->icache.linesz != 16 &&
1030 PAGE_SIZE <= 0x8000) 1047 PAGE_SIZE <= 0x8000)
1031 panic("Improper R4000SC processor configuration detected"); 1048 panic("Improper R4000SC processor configuration detected");
@@ -1045,7 +1062,7 @@ static void probe_pcache(void)
1045 * normally they'd suffer from aliases but magic in the hardware deals 1062 * normally they'd suffer from aliases but magic in the hardware deals
1046 * with that for us so we don't need to take care ourselves. 1063 * with that for us so we don't need to take care ourselves.
1047 */ 1064 */
1048 switch (c->cputype) { 1065 switch (current_cpu_type()) {
1049 case CPU_20KC: 1066 case CPU_20KC:
1050 case CPU_25KF: 1067 case CPU_25KF:
1051 case CPU_SB1: 1068 case CPU_SB1:
@@ -1065,7 +1082,7 @@ static void probe_pcache(void)
1065 case CPU_34K: 1082 case CPU_34K:
1066 case CPU_74K: 1083 case CPU_74K:
1067 case CPU_1004K: 1084 case CPU_1004K:
1068 if (c->cputype == CPU_74K) 1085 if (current_cpu_type() == CPU_74K)
1069 alias_74k_erratum(c); 1086 alias_74k_erratum(c);
1070 if ((read_c0_config7() & (1 << 16))) { 1087 if ((read_c0_config7() & (1 << 16))) {
1071 /* effectively physically indexed dcache, 1088 /* effectively physically indexed dcache,
@@ -1078,7 +1095,7 @@ static void probe_pcache(void)
1078 c->dcache.flags |= MIPS_CACHE_ALIASES; 1095 c->dcache.flags |= MIPS_CACHE_ALIASES;
1079 } 1096 }
1080 1097
1081 switch (c->cputype) { 1098 switch (current_cpu_type()) {
1082 case CPU_20KC: 1099 case CPU_20KC:
1083 /* 1100 /*
1084 * Some older 20Kc chips doesn't have the 'VI' bit in 1101 * Some older 20Kc chips doesn't have the 'VI' bit in
@@ -1207,7 +1224,7 @@ static void setup_scache(void)
1207 * processors don't have a S-cache that would be relevant to the 1224 * processors don't have a S-cache that would be relevant to the
1208 * Linux memory management. 1225 * Linux memory management.
1209 */ 1226 */
1210 switch (c->cputype) { 1227 switch (current_cpu_type()) {
1211 case CPU_R4000SC: 1228 case CPU_R4000SC:
1212 case CPU_R4000MC: 1229 case CPU_R4000MC:
1213 case CPU_R4400SC: 1230 case CPU_R4400SC:
@@ -1384,9 +1401,8 @@ static void r4k_cache_error_setup(void)
1384{ 1401{
1385 extern char __weak except_vec2_generic; 1402 extern char __weak except_vec2_generic;
1386 extern char __weak except_vec2_sb1; 1403 extern char __weak except_vec2_sb1;
1387 struct cpuinfo_mips *c = &current_cpu_data;
1388 1404
1389 switch (c->cputype) { 1405 switch (current_cpu_type()) {
1390 case CPU_SB1: 1406 case CPU_SB1:
1391 case CPU_SB1A: 1407 case CPU_SB1A:
1392 set_uncached_handler(0x100, &except_vec2_sb1, 0x80); 1408 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 664e523653d0..f25a7e9f8cbc 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -18,6 +18,7 @@
18#include <linux/highmem.h> 18#include <linux/highmem.h>
19 19
20#include <asm/cache.h> 20#include <asm/cache.h>
21#include <asm/cpu-type.h>
21#include <asm/io.h> 22#include <asm/io.h>
22 23
23#include <dma-coherence.h> 24#include <dma-coherence.h>
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 218c2109a55d..cbd81d17793a 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -18,6 +18,7 @@
18 18
19#include <asm/bugs.h> 19#include <asm/bugs.h>
20#include <asm/cacheops.h> 20#include <asm/cacheops.h>
21#include <asm/cpu-type.h>
21#include <asm/inst.h> 22#include <asm/inst.h>
22#include <asm/io.h> 23#include <asm/io.h>
23#include <asm/page.h> 24#include <asm/page.h>
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 5d01392e3518..08d05aee8788 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -6,6 +6,7 @@
6#include <linux/sched.h> 6#include <linux/sched.h>
7#include <linux/mm.h> 7#include <linux/mm.h>
8 8
9#include <asm/cpu-type.h>
9#include <asm/mipsregs.h> 10#include <asm/mipsregs.h>
10#include <asm/bcache.h> 11#include <asm/bcache.h>
11#include <asm/cacheops.h> 12#include <asm/cacheops.h>
@@ -71,7 +72,7 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
71 unsigned int tmp; 72 unsigned int tmp;
72 73
73 /* Check the bypass bit (L2B) */ 74 /* Check the bypass bit (L2B) */
74 switch (c->cputype) { 75 switch (current_cpu_type()) {
75 case CPU_34K: 76 case CPU_34K:
76 case CPU_74K: 77 case CPU_74K:
77 case CPU_1004K: 78 case CPU_1004K:
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 00b26a67a06d..bb3a5f643e97 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -16,6 +16,7 @@
16#include <linux/module.h> 16#include <linux/module.h>
17 17
18#include <asm/cpu.h> 18#include <asm/cpu.h>
19#include <asm/cpu-type.h>
19#include <asm/bootinfo.h> 20#include <asm/bootinfo.h>
20#include <asm/mmu_context.h> 21#include <asm/mmu_context.h>
21#include <asm/pgtable.h> 22#include <asm/pgtable.h>
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 821b45175dc1..9bb3a9363b06 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -30,6 +30,7 @@
30#include <linux/cache.h> 30#include <linux/cache.h>
31 31
32#include <asm/cacheflush.h> 32#include <asm/cacheflush.h>
33#include <asm/cpu-type.h>
33#include <asm/pgtable.h> 34#include <asm/pgtable.h>
34#include <asm/war.h> 35#include <asm/war.h>
35#include <asm/uasm.h> 36#include <asm/uasm.h>
diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index 53aad4a35375..a18af5fce67e 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -27,6 +27,7 @@
27#include <linux/timex.h> 27#include <linux/timex.h>
28#include <linux/mc146818rtc.h> 28#include <linux/mc146818rtc.h>
29 29
30#include <asm/cpu.h>
30#include <asm/mipsregs.h> 31#include <asm/mipsregs.h>
31#include <asm/mipsmtregs.h> 32#include <asm/mipsmtregs.h>
32#include <asm/hardirq.h> 33#include <asm/hardirq.h>
@@ -76,7 +77,7 @@ static void __init estimate_frequencies(void)
76#endif 77#endif
77 78
78#if defined (CONFIG_KVM_GUEST) && defined (CONFIG_KVM_HOST_FREQ) 79#if defined (CONFIG_KVM_GUEST) && defined (CONFIG_KVM_HOST_FREQ)
79 unsigned int prid = read_c0_prid() & 0xffff00; 80 unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
80 81
81 /* 82 /*
82 * XXXKYMA: hardwire the CPU frequency to Host Freq/4 83 * XXXKYMA: hardwire the CPU frequency to Host Freq/4
@@ -169,7 +170,7 @@ unsigned int get_c0_compare_int(void)
169 170
170void __init plat_time_init(void) 171void __init plat_time_init(void)
171{ 172{
172 unsigned int prid = read_c0_prid() & 0xffff00; 173 unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
173 unsigned int freq; 174 unsigned int freq;
174 175
175 estimate_frequencies(); 176 estimate_frequencies();
diff --git a/arch/mips/mti-sead3/sead3-time.c b/arch/mips/mti-sead3/sead3-time.c
index a43ea3cc0a3b..552d26c34386 100644
--- a/arch/mips/mti-sead3/sead3-time.c
+++ b/arch/mips/mti-sead3/sead3-time.c
@@ -7,6 +7,7 @@
7 */ 7 */
8#include <linux/init.h> 8#include <linux/init.h>
9 9
10#include <asm/cpu.h>
10#include <asm/setup.h> 11#include <asm/setup.h>
11#include <asm/time.h> 12#include <asm/time.h>
12#include <asm/irq.h> 13#include <asm/irq.h>
@@ -34,7 +35,7 @@ static void __iomem *status_reg = (void __iomem *)0xbf000410;
34 */ 35 */
35static unsigned int __init estimate_cpu_frequency(void) 36static unsigned int __init estimate_cpu_frequency(void)
36{ 37{
37 unsigned int prid = read_c0_prid() & 0xffff00; 38 unsigned int prid = read_c0_prid() & (PRID_COMP_MASK | PRID_IMP_MASK);
38 unsigned int tick = 0; 39 unsigned int tick = 0;
39 unsigned int freq; 40 unsigned int freq;
40 unsigned int orig; 41 unsigned int orig;
diff --git a/arch/mips/netlogic/xlr/fmn-config.c b/arch/mips/netlogic/xlr/fmn-config.c
index ed3bf0e3f309..c7622c6e5f67 100644
--- a/arch/mips/netlogic/xlr/fmn-config.c
+++ b/arch/mips/netlogic/xlr/fmn-config.c
@@ -36,6 +36,7 @@
36#include <linux/irq.h> 36#include <linux/irq.h>
37#include <linux/interrupt.h> 37#include <linux/interrupt.h>
38 38
39#include <asm/cpu.h>
39#include <asm/mipsregs.h> 40#include <asm/mipsregs.h>
40#include <asm/netlogic/xlr/fmn.h> 41#include <asm/netlogic/xlr/fmn.h>
41#include <asm/netlogic/xlr/xlr.h> 42#include <asm/netlogic/xlr/xlr.h>
@@ -187,7 +188,7 @@ void xlr_board_info_setup(void)
187 int processor_id, num_core; 188 int processor_id, num_core;
188 189
189 num_core = hweight32(nlm_current_node()->coremask); 190 num_core = hweight32(nlm_current_node()->coremask);
190 processor_id = read_c0_prid() & 0xff00; 191 processor_id = read_c0_prid() & PRID_IMP_MASK;
191 192
192 setup_cpu_fmninfo(cpu, num_core); 193 setup_cpu_fmninfo(cpu, num_core);
193 switch (processor_id) { 194 switch (processor_id) {
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 5e5424753b56..4d1736fc1955 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -12,6 +12,7 @@
12#include <linux/oprofile.h> 12#include <linux/oprofile.h>
13#include <linux/smp.h> 13#include <linux/smp.h>
14#include <asm/cpu-info.h> 14#include <asm/cpu-info.h>
15#include <asm/cpu-type.h>
15 16
16#include "op_impl.h" 17#include "op_impl.h"
17 18
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
index 44dd5aa2e36f..5ec2a7bae02c 100644
--- a/arch/mips/pci/pci-bcm1480.c
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -39,6 +39,7 @@
39#include <linux/mm.h> 39#include <linux/mm.h>
40#include <linux/console.h> 40#include <linux/console.h>
41#include <linux/tty.h> 41#include <linux/tty.h>
42#include <linux/vt.h>
42 43
43#include <asm/sibyte/bcm1480_regs.h> 44#include <asm/sibyte/bcm1480_regs.h>
44#include <asm/sibyte/bcm1480_scd.h> 45#include <asm/sibyte/bcm1480_scd.h>
diff --git a/arch/mips/sibyte/bcm1480/setup.c b/arch/mips/sibyte/bcm1480/setup.c
index 05ed92c92b69..8e2e04f77870 100644
--- a/arch/mips/sibyte/bcm1480/setup.c
+++ b/arch/mips/sibyte/bcm1480/setup.c
@@ -22,6 +22,7 @@
22#include <linux/string.h> 22#include <linux/string.h>
23 23
24#include <asm/bootinfo.h> 24#include <asm/bootinfo.h>
25#include <asm/cpu.h>
25#include <asm/mipsregs.h> 26#include <asm/mipsregs.h>
26#include <asm/io.h> 27#include <asm/io.h>
27#include <asm/sibyte/sb1250.h> 28#include <asm/sibyte/sb1250.h>
@@ -119,7 +120,7 @@ void __init bcm1480_setup(void)
119 uint64_t sys_rev; 120 uint64_t sys_rev;
120 int plldiv; 121 int plldiv;
121 122
122 sb1_pass = read_c0_prid() & 0xff; 123 sb1_pass = read_c0_prid() & PRID_REV_MASK;
123 sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION)); 124 sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION));
124 soc_type = SYS_SOC_TYPE(sys_rev); 125 soc_type = SYS_SOC_TYPE(sys_rev);
125 part_type = G_SYS_PART(sys_rev); 126 part_type = G_SYS_PART(sys_rev);
diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c
index a14bd4cb0bc0..3c02b2a77ae9 100644
--- a/arch/mips/sibyte/sb1250/setup.c
+++ b/arch/mips/sibyte/sb1250/setup.c
@@ -22,6 +22,7 @@
22#include <linux/string.h> 22#include <linux/string.h>
23 23
24#include <asm/bootinfo.h> 24#include <asm/bootinfo.h>
25#include <asm/cpu.h>
25#include <asm/mipsregs.h> 26#include <asm/mipsregs.h>
26#include <asm/io.h> 27#include <asm/io.h>
27#include <asm/sibyte/sb1250.h> 28#include <asm/sibyte/sb1250.h>
@@ -182,7 +183,7 @@ void __init sb1250_setup(void)
182 int plldiv; 183 int plldiv;
183 int bad_config = 0; 184 int bad_config = 0;
184 185
185 sb1_pass = read_c0_prid() & 0xff; 186 sb1_pass = read_c0_prid() & PRID_REV_MASK;
186 sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION)); 187 sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION));
187 soc_type = SYS_SOC_TYPE(sys_rev); 188 soc_type = SYS_SOC_TYPE(sys_rev);
188 soc_pass = G_SYS_REVISION(sys_rev); 189 soc_pass = G_SYS_REVISION(sys_rev);
diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c
index 5b09b3544edd..efad85c8c823 100644
--- a/arch/mips/sni/setup.c
+++ b/arch/mips/sni/setup.c
@@ -25,6 +25,7 @@
25#endif 25#endif
26 26
27#include <asm/bootinfo.h> 27#include <asm/bootinfo.h>
28#include <asm/cpu.h>
28#include <asm/io.h> 29#include <asm/io.h>
29#include <asm/reboot.h> 30#include <asm/reboot.h>
30#include <asm/sni.h> 31#include <asm/sni.h>
@@ -173,7 +174,7 @@ void __init plat_mem_setup(void)
173 system_type = "RM300-Cxx"; 174 system_type = "RM300-Cxx";
174 break; 175 break;
175 case SNI_BRD_PCI_DESKTOP: 176 case SNI_BRD_PCI_DESKTOP:
176 switch (read_c0_prid() & 0xff00) { 177 switch (read_c0_prid() & PRID_IMP_MASK) {
177 case PRID_IMP_R4600: 178 case PRID_IMP_R4600:
178 case PRID_IMP_R4700: 179 case PRID_IMP_R4700:
179 system_type = "RM200-C20"; 180 system_type = "RM200-C20";
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index e241a1930c98..ee2fb9d37745 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -481,11 +481,12 @@ config X86_INTEL_LPSS
481 bool "Intel Low Power Subsystem Support" 481 bool "Intel Low Power Subsystem Support"
482 depends on ACPI 482 depends on ACPI
483 select COMMON_CLK 483 select COMMON_CLK
484 select PINCTRL
484 ---help--- 485 ---help---
485 Select to build support for Intel Low Power Subsystem such as 486 Select to build support for Intel Low Power Subsystem such as
486 found on Intel Lynxpoint PCH. Selecting this option enables 487 found on Intel Lynxpoint PCH. Selecting this option enables
487 things like clock tree (common clock framework) which are needed 488 things like clock tree (common clock framework) and pincontrol
488 by the LPSS peripheral drivers. 489 which are needed by the LPSS peripheral drivers.
489 490
490config X86_RDC321X 491config X86_RDC321X
491 bool "RDC R-321x SoC" 492 bool "RDC R-321x SoC"
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index 63438aad177f..ab3ba1c1b7dd 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -584,6 +584,7 @@ struct event_constraint intel_snb_pebs_event_constraints[] = {
584 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */ 584 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
585 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 585 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
586 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ 586 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
587 INTEL_EVENT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
587 INTEL_UEVENT_CONSTRAINT(0x02d4, 0xf), /* MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS */ 588 INTEL_UEVENT_CONSTRAINT(0x02d4, 0xf), /* MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS */
588 EVENT_CONSTRAINT_END 589 EVENT_CONSTRAINT_END
589}; 590};
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index 1b69951a81e2..b077f4cc225a 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -487,21 +487,6 @@ ENDPROC(native_usergs_sysret64)
487 TRACE_IRQS_OFF 487 TRACE_IRQS_OFF
488 .endm 488 .endm
489 489
490ENTRY(save_rest)
491 PARTIAL_FRAME 1 (REST_SKIP+8)
492 movq 5*8+16(%rsp), %r11 /* save return address */
493 movq_cfi rbx, RBX+16
494 movq_cfi rbp, RBP+16
495 movq_cfi r12, R12+16
496 movq_cfi r13, R13+16
497 movq_cfi r14, R14+16
498 movq_cfi r15, R15+16
499 movq %r11, 8(%rsp) /* return address */
500 FIXUP_TOP_OF_STACK %r11, 16
501 ret
502 CFI_ENDPROC
503END(save_rest)
504
505/* save complete stack frame */ 490/* save complete stack frame */
506 .pushsection .kprobes.text, "ax" 491 .pushsection .kprobes.text, "ax"
507ENTRY(save_paranoid) 492ENTRY(save_paranoid)
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index aecc98a93d1b..6cacab671f9b 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -653,6 +653,7 @@ static void announce_cpu(int cpu, int apicid)
653{ 653{
654 static int current_node = -1; 654 static int current_node = -1;
655 int node = early_cpu_to_node(cpu); 655 int node = early_cpu_to_node(cpu);
656 int max_cpu_present = find_last_bit(cpumask_bits(cpu_present_mask), NR_CPUS);
656 657
657 if (system_state == SYSTEM_BOOTING) { 658 if (system_state == SYSTEM_BOOTING) {
658 if (node != current_node) { 659 if (node != current_node) {
@@ -661,7 +662,7 @@ static void announce_cpu(int cpu, int apicid)
661 current_node = node; 662 current_node = node;
662 pr_info("Booting Node %3d, Processors ", node); 663 pr_info("Booting Node %3d, Processors ", node);
663 } 664 }
664 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " OK\n" : ""); 665 pr_cont(" #%4d%s", cpu, cpu == max_cpu_present ? " OK\n" : "");
665 return; 666 return;
666 } else 667 } else
667 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 668 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-13 23:22:17 -0500