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-rw-r--r--arch/arm/mach-ns9xxx/board-a9m9750dev.c8
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/board.h2
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/memory.h2
-rw-r--r--arch/arm/mach-ns9xxx/include/mach/module.h5
-rw-r--r--arch/arm/mach-ns9xxx/irq.c59
5 files changed, 9 insertions, 67 deletions
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
index 0c0d5248c368..e27687d53504 100644
--- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c
+++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
@@ -107,8 +107,8 @@ void __init board_a9m9750dev_init_irq(void)
107 __func__); 107 __func__);
108 108
109 for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { 109 for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
110 set_irq_chip(i, &a9m9750dev_fpga_chip); 110 irq_set_chip_and_handler(i, &a9m9750dev_fpga_chip,
111 set_irq_handler(i, handle_level_irq); 111 handle_level_irq);
112 set_irq_flags(i, IRQF_VALID); 112 set_irq_flags(i, IRQF_VALID);
113 } 113 }
114 114
@@ -118,8 +118,8 @@ void __init board_a9m9750dev_init_irq(void)
118 REGSET(eic, SYS_EIC, LVEDG, LEVEL); 118 REGSET(eic, SYS_EIC, LVEDG, LEVEL);
119 __raw_writel(eic, SYS_EIC(2)); 119 __raw_writel(eic, SYS_EIC(2));
120 120
121 set_irq_chained_handler(IRQ_NS9XXX_EXT2, 121 irq_set_chained_handler(IRQ_NS9XXX_EXT2,
122 a9m9750dev_fpga_demux_handler); 122 a9m9750dev_fpga_demux_handler);
123} 123}
124 124
125void __init board_a9m9750dev_init_machine(void) 125void __init board_a9m9750dev_init_machine(void)
diff --git a/arch/arm/mach-ns9xxx/include/mach/board.h b/arch/arm/mach-ns9xxx/include/mach/board.h
index f7e9196eb9ab..19ca6de46a45 100644
--- a/arch/arm/mach-ns9xxx/include/mach/board.h
+++ b/arch/arm/mach-ns9xxx/include/mach/board.h
@@ -14,12 +14,10 @@
14#include <asm/mach-types.h> 14#include <asm/mach-types.h>
15 15
16#define board_is_a9m9750dev() (0 \ 16#define board_is_a9m9750dev() (0 \
17 || machine_is_cc9p9360dev() \
18 || machine_is_cc9p9750dev() \ 17 || machine_is_cc9p9750dev() \
19 ) 18 )
20 19
21#define board_is_a9mvali() (0 \ 20#define board_is_a9mvali() (0 \
22 || machine_is_cc9p9360val() \
23 || machine_is_cc9p9750val() \ 21 || machine_is_cc9p9750val() \
24 ) 22 )
25 23
diff --git a/arch/arm/mach-ns9xxx/include/mach/memory.h b/arch/arm/mach-ns9xxx/include/mach/memory.h
index 6107193adbfe..5c65aee6e7a9 100644
--- a/arch/arm/mach-ns9xxx/include/mach/memory.h
+++ b/arch/arm/mach-ns9xxx/include/mach/memory.h
@@ -19,6 +19,6 @@
19#define NS9XXX_CS2STAT_LENGTH UL(0x1000) 19#define NS9XXX_CS2STAT_LENGTH UL(0x1000)
20#define NS9XXX_CS3STAT_LENGTH UL(0x1000) 20#define NS9XXX_CS3STAT_LENGTH UL(0x1000)
21 21
22#define PHYS_OFFSET UL(0x00000000) 22#define PLAT_PHYS_OFFSET UL(0x00000000)
23 23
24#endif 24#endif
diff --git a/arch/arm/mach-ns9xxx/include/mach/module.h b/arch/arm/mach-ns9xxx/include/mach/module.h
index f851a6b7da6c..628e9752589b 100644
--- a/arch/arm/mach-ns9xxx/include/mach/module.h
+++ b/arch/arm/mach-ns9xxx/include/mach/module.h
@@ -18,7 +18,6 @@
18 ) 18 )
19 19
20#define module_is_cc9c() (0 \ 20#define module_is_cc9c() (0 \
21 || machine_is_cc9c() \
22 ) 21 )
23 22
24#define module_is_cc9p9210() (0 \ 23#define module_is_cc9p9210() (0 \
@@ -32,21 +31,17 @@
32 ) 31 )
33 32
34#define module_is_cc9p9360() (0 \ 33#define module_is_cc9p9360() (0 \
35 || machine_is_a9m9360() \
36 || machine_is_cc9p9360dev() \ 34 || machine_is_cc9p9360dev() \
37 || machine_is_cc9p9360js() \ 35 || machine_is_cc9p9360js() \
38 || machine_is_cc9p9360val() \
39 ) 36 )
40 37
41#define module_is_cc9p9750() (0 \ 38#define module_is_cc9p9750() (0 \
42 || machine_is_a9m9750() \ 39 || machine_is_a9m9750() \
43 || machine_is_cc9p9750dev() \
44 || machine_is_cc9p9750js() \ 40 || machine_is_cc9p9750js() \
45 || machine_is_cc9p9750val() \ 41 || machine_is_cc9p9750val() \
46 ) 42 )
47 43
48#define module_is_ccw9c() (0 \ 44#define module_is_ccw9c() (0 \
49 || machine_is_ccw9c() \
50 ) 45 )
51 46
52#define module_is_inc20otter() (0 \ 47#define module_is_inc20otter() (0 \
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c
index 389fa5c669de..37ab0a2b83ad 100644
--- a/arch/arm/mach-ns9xxx/irq.c
+++ b/arch/arm/mach-ns9xxx/irq.c
@@ -31,17 +31,11 @@ static void ns9xxx_mask_irq(struct irq_data *d)
31 __raw_writel(ic, SYS_IC(prio / 4)); 31 __raw_writel(ic, SYS_IC(prio / 4));
32} 32}
33 33
34static void ns9xxx_ack_irq(struct irq_data *d) 34static void ns9xxx_eoi_irq(struct irq_data *d)
35{ 35{
36 __raw_writel(0, SYS_ISRADDR); 36 __raw_writel(0, SYS_ISRADDR);
37} 37}
38 38
39static void ns9xxx_maskack_irq(struct irq_data *d)
40{
41 ns9xxx_mask_irq(d);
42 ns9xxx_ack_irq(d);
43}
44
45static void ns9xxx_unmask_irq(struct irq_data *d) 39static void ns9xxx_unmask_irq(struct irq_data *d)
46{ 40{
47 /* XXX: better use cpp symbols */ 41 /* XXX: better use cpp symbols */
@@ -52,56 +46,11 @@ static void ns9xxx_unmask_irq(struct irq_data *d)
52} 46}
53 47
54static struct irq_chip ns9xxx_chip = { 48static struct irq_chip ns9xxx_chip = {
55 .irq_ack = ns9xxx_ack_irq, 49 .irq_eoi = ns9xxx_eoi_irq,
56 .irq_mask = ns9xxx_mask_irq, 50 .irq_mask = ns9xxx_mask_irq,
57 .irq_mask_ack = ns9xxx_maskack_irq,
58 .irq_unmask = ns9xxx_unmask_irq, 51 .irq_unmask = ns9xxx_unmask_irq,
59}; 52};
60 53
61#if 0
62#define handle_irq handle_level_irq
63#else
64static void handle_prio_irq(unsigned int irq, struct irq_desc *desc)
65{
66 struct irqaction *action;
67 irqreturn_t action_ret;
68
69 raw_spin_lock(&desc->lock);
70
71 BUG_ON(desc->status & IRQ_INPROGRESS);
72
73 desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
74 kstat_incr_irqs_this_cpu(irq, desc);
75
76 action = desc->action;
77 if (unlikely(!action || (desc->status & IRQ_DISABLED)))
78 goto out_mask;
79
80 desc->status |= IRQ_INPROGRESS;
81 raw_spin_unlock(&desc->lock);
82
83 action_ret = handle_IRQ_event(irq, action);
84
85 /* XXX: There is no direct way to access noirqdebug, so check
86 * unconditionally for spurious irqs...
87 * Maybe this function should go to kernel/irq/chip.c? */
88 note_interrupt(irq, desc, action_ret);
89
90 raw_spin_lock(&desc->lock);
91 desc->status &= ~IRQ_INPROGRESS;
92
93 if (desc->status & IRQ_DISABLED)
94out_mask:
95 desc->irq_data.chip->irq_mask(&desc->irq_data);
96
97 /* ack unconditionally to unmask lower prio irqs */
98 desc->irq_data.chip->irq_ack(&desc->irq_data);
99
100 raw_spin_unlock(&desc->lock);
101}
102#define handle_irq handle_prio_irq
103#endif
104
105void __init ns9xxx_init_irq(void) 54void __init ns9xxx_init_irq(void)
106{ 55{
107 int i; 56 int i;
@@ -118,8 +67,8 @@ void __init ns9xxx_init_irq(void)
118 __raw_writel(prio2irq(i), SYS_IVA(i)); 67 __raw_writel(prio2irq(i), SYS_IVA(i));
119 68
120 for (i = 0; i <= 31; ++i) { 69 for (i = 0; i <= 31; ++i) {
121 set_irq_chip(i, &ns9xxx_chip); 70 irq_set_chip_and_handler(i, &ns9xxx_chip, handle_fasteoi_irq);
122 set_irq_handler(i, handle_irq);
123 set_irq_flags(i, IRQF_VALID); 71 set_irq_flags(i, IRQF_VALID);
72 irq_set_status_flags(i, IRQ_LEVEL);
124 } 73 }
125} 74}