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-rw-r--r--arch/arm/common/Kconfig23
-rw-r--r--arch/arm/common/Makefile2
-rw-r--r--arch/arm/common/gic.c832
-rw-r--r--arch/arm/common/vic.c464
4 files changed, 0 insertions, 1321 deletions
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 45ceeb0e93e0..9353184d730d 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -1,26 +1,3 @@
1config ARM_GIC
2 bool
3 select IRQ_DOMAIN
4 select MULTI_IRQ_HANDLER
5
6config GIC_NON_BANKED
7 bool
8
9config ARM_VIC
10 bool
11 select IRQ_DOMAIN
12 select MULTI_IRQ_HANDLER
13
14config ARM_VIC_NR
15 int
16 default 4 if ARCH_S5PV210
17 default 3 if ARCH_S5PC100
18 default 2
19 depends on ARM_VIC
20 help
21 The maximum number of VICs available in the system, for
22 power management.
23
24config ICST 1config ICST
25 bool 2 bool
26 3
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index e8a4e58f1b82..dc8dd0de5c0f 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -2,8 +2,6 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-$(CONFIG_ARM_GIC) += gic.o
6obj-$(CONFIG_ARM_VIC) += vic.o
7obj-$(CONFIG_ICST) += icst.o 5obj-$(CONFIG_ICST) += icst.o
8obj-$(CONFIG_SA1111) += sa1111.o 6obj-$(CONFIG_SA1111) += sa1111.o
9obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o 7obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
deleted file mode 100644
index 87dfa9026c5b..000000000000
--- a/arch/arm/common/gic.c
+++ /dev/null
@@ -1,832 +0,0 @@
1/*
2 * linux/arch/arm/common/gic.c
3 *
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Interrupt architecture for the GIC:
11 *
12 * o There is one Interrupt Distributor, which receives interrupts
13 * from system devices and sends them to the Interrupt Controllers.
14 *
15 * o There is one CPU Interface per CPU, which sends interrupts sent
16 * by the Distributor, and interrupts generated locally, to the
17 * associated CPU. The base address of the CPU interface is usually
18 * aliased so that the same address points to different chips depending
19 * on the CPU it is accessed from.
20 *
21 * Note that IRQs 0-31 are special - they are local to each CPU.
22 * As such, the enable set/clear, pending set/clear and active bit
23 * registers are banked per-cpu for these sources.
24 */
25#include <linux/init.h>
26#include <linux/kernel.h>
27#include <linux/err.h>
28#include <linux/module.h>
29#include <linux/list.h>
30#include <linux/smp.h>
31#include <linux/cpu_pm.h>
32#include <linux/cpumask.h>
33#include <linux/io.h>
34#include <linux/of.h>
35#include <linux/of_address.h>
36#include <linux/of_irq.h>
37#include <linux/irqdomain.h>
38#include <linux/interrupt.h>
39#include <linux/percpu.h>
40#include <linux/slab.h>
41
42#include <asm/irq.h>
43#include <asm/exception.h>
44#include <asm/smp_plat.h>
45#include <asm/mach/irq.h>
46#include <asm/hardware/gic.h>
47
48union gic_base {
49 void __iomem *common_base;
50 void __percpu __iomem **percpu_base;
51};
52
53struct gic_chip_data {
54 union gic_base dist_base;
55 union gic_base cpu_base;
56#ifdef CONFIG_CPU_PM
57 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
58 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
59 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
60 u32 __percpu *saved_ppi_enable;
61 u32 __percpu *saved_ppi_conf;
62#endif
63 struct irq_domain *domain;
64 unsigned int gic_irqs;
65#ifdef CONFIG_GIC_NON_BANKED
66 void __iomem *(*get_base)(union gic_base *);
67#endif
68};
69
70static DEFINE_RAW_SPINLOCK(irq_controller_lock);
71
72/*
73 * The GIC mapping of CPU interfaces does not necessarily match
74 * the logical CPU numbering. Let's use a mapping as returned
75 * by the GIC itself.
76 */
77#define NR_GIC_CPU_IF 8
78static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
79
80/*
81 * Supported arch specific GIC irq extension.
82 * Default make them NULL.
83 */
84struct irq_chip gic_arch_extn = {
85 .irq_eoi = NULL,
86 .irq_mask = NULL,
87 .irq_unmask = NULL,
88 .irq_retrigger = NULL,
89 .irq_set_type = NULL,
90 .irq_set_wake = NULL,
91};
92
93#ifndef MAX_GIC_NR
94#define MAX_GIC_NR 1
95#endif
96
97static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
98
99#ifdef CONFIG_GIC_NON_BANKED
100static void __iomem *gic_get_percpu_base(union gic_base *base)
101{
102 return *__this_cpu_ptr(base->percpu_base);
103}
104
105static void __iomem *gic_get_common_base(union gic_base *base)
106{
107 return base->common_base;
108}
109
110static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
111{
112 return data->get_base(&data->dist_base);
113}
114
115static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
116{
117 return data->get_base(&data->cpu_base);
118}
119
120static inline void gic_set_base_accessor(struct gic_chip_data *data,
121 void __iomem *(*f)(union gic_base *))
122{
123 data->get_base = f;
124}
125#else
126#define gic_data_dist_base(d) ((d)->dist_base.common_base)
127#define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
128#define gic_set_base_accessor(d,f)
129#endif
130
131static inline void __iomem *gic_dist_base(struct irq_data *d)
132{
133 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
134 return gic_data_dist_base(gic_data);
135}
136
137static inline void __iomem *gic_cpu_base(struct irq_data *d)
138{
139 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
140 return gic_data_cpu_base(gic_data);
141}
142
143static inline unsigned int gic_irq(struct irq_data *d)
144{
145 return d->hwirq;
146}
147
148/*
149 * Routines to acknowledge, disable and enable interrupts
150 */
151static void gic_mask_irq(struct irq_data *d)
152{
153 u32 mask = 1 << (gic_irq(d) % 32);
154
155 raw_spin_lock(&irq_controller_lock);
156 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
157 if (gic_arch_extn.irq_mask)
158 gic_arch_extn.irq_mask(d);
159 raw_spin_unlock(&irq_controller_lock);
160}
161
162static void gic_unmask_irq(struct irq_data *d)
163{
164 u32 mask = 1 << (gic_irq(d) % 32);
165
166 raw_spin_lock(&irq_controller_lock);
167 if (gic_arch_extn.irq_unmask)
168 gic_arch_extn.irq_unmask(d);
169 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
170 raw_spin_unlock(&irq_controller_lock);
171}
172
173static void gic_eoi_irq(struct irq_data *d)
174{
175 if (gic_arch_extn.irq_eoi) {
176 raw_spin_lock(&irq_controller_lock);
177 gic_arch_extn.irq_eoi(d);
178 raw_spin_unlock(&irq_controller_lock);
179 }
180
181 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
182}
183
184static int gic_set_type(struct irq_data *d, unsigned int type)
185{
186 void __iomem *base = gic_dist_base(d);
187 unsigned int gicirq = gic_irq(d);
188 u32 enablemask = 1 << (gicirq % 32);
189 u32 enableoff = (gicirq / 32) * 4;
190 u32 confmask = 0x2 << ((gicirq % 16) * 2);
191 u32 confoff = (gicirq / 16) * 4;
192 bool enabled = false;
193 u32 val;
194
195 /* Interrupt configuration for SGIs can't be changed */
196 if (gicirq < 16)
197 return -EINVAL;
198
199 if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
200 return -EINVAL;
201
202 raw_spin_lock(&irq_controller_lock);
203
204 if (gic_arch_extn.irq_set_type)
205 gic_arch_extn.irq_set_type(d, type);
206
207 val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
208 if (type == IRQ_TYPE_LEVEL_HIGH)
209 val &= ~confmask;
210 else if (type == IRQ_TYPE_EDGE_RISING)
211 val |= confmask;
212
213 /*
214 * As recommended by the spec, disable the interrupt before changing
215 * the configuration
216 */
217 if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
218 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
219 enabled = true;
220 }
221
222 writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
223
224 if (enabled)
225 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
226
227 raw_spin_unlock(&irq_controller_lock);
228
229 return 0;
230}
231
232static int gic_retrigger(struct irq_data *d)
233{
234 if (gic_arch_extn.irq_retrigger)
235 return gic_arch_extn.irq_retrigger(d);
236
237 return -ENXIO;
238}
239
240#ifdef CONFIG_SMP
241static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
242 bool force)
243{
244 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
245 unsigned int shift = (gic_irq(d) % 4) * 8;
246 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
247 u32 val, mask, bit;
248
249 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
250 return -EINVAL;
251
252 mask = 0xff << shift;
253 bit = gic_cpu_map[cpu] << shift;
254
255 raw_spin_lock(&irq_controller_lock);
256 val = readl_relaxed(reg) & ~mask;
257 writel_relaxed(val | bit, reg);
258 raw_spin_unlock(&irq_controller_lock);
259
260 return IRQ_SET_MASK_OK;
261}
262#endif
263
264#ifdef CONFIG_PM
265static int gic_set_wake(struct irq_data *d, unsigned int on)
266{
267 int ret = -ENXIO;
268
269 if (gic_arch_extn.irq_set_wake)
270 ret = gic_arch_extn.irq_set_wake(d, on);
271
272 return ret;
273}
274
275#else
276#define gic_set_wake NULL
277#endif
278
279asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
280{
281 u32 irqstat, irqnr;
282 struct gic_chip_data *gic = &gic_data[0];
283 void __iomem *cpu_base = gic_data_cpu_base(gic);
284
285 do {
286 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
287 irqnr = irqstat & ~0x1c00;
288
289 if (likely(irqnr > 15 && irqnr < 1021)) {
290 irqnr = irq_find_mapping(gic->domain, irqnr);
291 handle_IRQ(irqnr, regs);
292 continue;
293 }
294 if (irqnr < 16) {
295 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
296#ifdef CONFIG_SMP
297 handle_IPI(irqnr, regs);
298#endif
299 continue;
300 }
301 break;
302 } while (1);
303}
304
305static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
306{
307 struct gic_chip_data *chip_data = irq_get_handler_data(irq);
308 struct irq_chip *chip = irq_get_chip(irq);
309 unsigned int cascade_irq, gic_irq;
310 unsigned long status;
311
312 chained_irq_enter(chip, desc);
313
314 raw_spin_lock(&irq_controller_lock);
315 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
316 raw_spin_unlock(&irq_controller_lock);
317
318 gic_irq = (status & 0x3ff);
319 if (gic_irq == 1023)
320 goto out;
321
322 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
323 if (unlikely(gic_irq < 32 || gic_irq > 1020))
324 do_bad_IRQ(cascade_irq, desc);
325 else
326 generic_handle_irq(cascade_irq);
327
328 out:
329 chained_irq_exit(chip, desc);
330}
331
332static struct irq_chip gic_chip = {
333 .name = "GIC",
334 .irq_mask = gic_mask_irq,
335 .irq_unmask = gic_unmask_irq,
336 .irq_eoi = gic_eoi_irq,
337 .irq_set_type = gic_set_type,
338 .irq_retrigger = gic_retrigger,
339#ifdef CONFIG_SMP
340 .irq_set_affinity = gic_set_affinity,
341#endif
342 .irq_set_wake = gic_set_wake,
343};
344
345void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
346{
347 if (gic_nr >= MAX_GIC_NR)
348 BUG();
349 if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
350 BUG();
351 irq_set_chained_handler(irq, gic_handle_cascade_irq);
352}
353
354static u8 gic_get_cpumask(struct gic_chip_data *gic)
355{
356 void __iomem *base = gic_data_dist_base(gic);
357 u32 mask, i;
358
359 for (i = mask = 0; i < 32; i += 4) {
360 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
361 mask |= mask >> 16;
362 mask |= mask >> 8;
363 if (mask)
364 break;
365 }
366
367 if (!mask)
368 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
369
370 return mask;
371}
372
373static void __init gic_dist_init(struct gic_chip_data *gic)
374{
375 unsigned int i;
376 u32 cpumask;
377 unsigned int gic_irqs = gic->gic_irqs;
378 void __iomem *base = gic_data_dist_base(gic);
379
380 writel_relaxed(0, base + GIC_DIST_CTRL);
381
382 /*
383 * Set all global interrupts to be level triggered, active low.
384 */
385 for (i = 32; i < gic_irqs; i += 16)
386 writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
387
388 /*
389 * Set all global interrupts to this CPU only.
390 */
391 cpumask = gic_get_cpumask(gic);
392 cpumask |= cpumask << 8;
393 cpumask |= cpumask << 16;
394 for (i = 32; i < gic_irqs; i += 4)
395 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
396
397 /*
398 * Set priority on all global interrupts.
399 */
400 for (i = 32; i < gic_irqs; i += 4)
401 writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
402
403 /*
404 * Disable all interrupts. Leave the PPI and SGIs alone
405 * as these enables are banked registers.
406 */
407 for (i = 32; i < gic_irqs; i += 32)
408 writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
409
410 writel_relaxed(1, base + GIC_DIST_CTRL);
411}
412
413static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
414{
415 void __iomem *dist_base = gic_data_dist_base(gic);
416 void __iomem *base = gic_data_cpu_base(gic);
417 unsigned int cpu_mask, cpu = smp_processor_id();
418 int i;
419
420 /*
421 * Get what the GIC says our CPU mask is.
422 */
423 BUG_ON(cpu >= NR_GIC_CPU_IF);
424 cpu_mask = gic_get_cpumask(gic);
425 gic_cpu_map[cpu] = cpu_mask;
426
427 /*
428 * Clear our mask from the other map entries in case they're
429 * still undefined.
430 */
431 for (i = 0; i < NR_GIC_CPU_IF; i++)
432 if (i != cpu)
433 gic_cpu_map[i] &= ~cpu_mask;
434
435 /*
436 * Deal with the banked PPI and SGI interrupts - disable all
437 * PPI interrupts, ensure all SGI interrupts are enabled.
438 */
439 writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
440 writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
441
442 /*
443 * Set priority on PPI and SGI interrupts
444 */
445 for (i = 0; i < 32; i += 4)
446 writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
447
448 writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
449 writel_relaxed(1, base + GIC_CPU_CTRL);
450}
451
452#ifdef CONFIG_CPU_PM
453/*
454 * Saves the GIC distributor registers during suspend or idle. Must be called
455 * with interrupts disabled but before powering down the GIC. After calling
456 * this function, no interrupts will be delivered by the GIC, and another
457 * platform-specific wakeup source must be enabled.
458 */
459static void gic_dist_save(unsigned int gic_nr)
460{
461 unsigned int gic_irqs;
462 void __iomem *dist_base;
463 int i;
464
465 if (gic_nr >= MAX_GIC_NR)
466 BUG();
467
468 gic_irqs = gic_data[gic_nr].gic_irqs;
469 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
470
471 if (!dist_base)
472 return;
473
474 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
475 gic_data[gic_nr].saved_spi_conf[i] =
476 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
477
478 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
479 gic_data[gic_nr].saved_spi_target[i] =
480 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
481
482 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
483 gic_data[gic_nr].saved_spi_enable[i] =
484 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
485}
486
487/*
488 * Restores the GIC distributor registers during resume or when coming out of
489 * idle. Must be called before enabling interrupts. If a level interrupt
490 * that occured while the GIC was suspended is still present, it will be
491 * handled normally, but any edge interrupts that occured will not be seen by
492 * the GIC and need to be handled by the platform-specific wakeup source.
493 */
494static void gic_dist_restore(unsigned int gic_nr)
495{
496 unsigned int gic_irqs;
497 unsigned int i;
498 void __iomem *dist_base;
499
500 if (gic_nr >= MAX_GIC_NR)
501 BUG();
502
503 gic_irqs = gic_data[gic_nr].gic_irqs;
504 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
505
506 if (!dist_base)
507 return;
508
509 writel_relaxed(0, dist_base + GIC_DIST_CTRL);
510
511 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
512 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
513 dist_base + GIC_DIST_CONFIG + i * 4);
514
515 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
516 writel_relaxed(0xa0a0a0a0,
517 dist_base + GIC_DIST_PRI + i * 4);
518
519 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
520 writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
521 dist_base + GIC_DIST_TARGET + i * 4);
522
523 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
524 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
525 dist_base + GIC_DIST_ENABLE_SET + i * 4);
526
527 writel_relaxed(1, dist_base + GIC_DIST_CTRL);
528}
529
530static void gic_cpu_save(unsigned int gic_nr)
531{
532 int i;
533 u32 *ptr;
534 void __iomem *dist_base;
535 void __iomem *cpu_base;
536
537 if (gic_nr >= MAX_GIC_NR)
538 BUG();
539
540 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
541 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
542
543 if (!dist_base || !cpu_base)
544 return;
545
546 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
547 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
548 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
549
550 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
551 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
552 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
553
554}
555
556static void gic_cpu_restore(unsigned int gic_nr)
557{
558 int i;
559 u32 *ptr;
560 void __iomem *dist_base;
561 void __iomem *cpu_base;
562
563 if (gic_nr >= MAX_GIC_NR)
564 BUG();
565
566 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
567 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
568
569 if (!dist_base || !cpu_base)
570 return;
571
572 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
573 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
574 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
575
576 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
577 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
578 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
579
580 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
581 writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4);
582
583 writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK);
584 writel_relaxed(1, cpu_base + GIC_CPU_CTRL);
585}
586
587static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
588{
589 int i;
590
591 for (i = 0; i < MAX_GIC_NR; i++) {
592#ifdef CONFIG_GIC_NON_BANKED
593 /* Skip over unused GICs */
594 if (!gic_data[i].get_base)
595 continue;
596#endif
597 switch (cmd) {
598 case CPU_PM_ENTER:
599 gic_cpu_save(i);
600 break;
601 case CPU_PM_ENTER_FAILED:
602 case CPU_PM_EXIT:
603 gic_cpu_restore(i);
604 break;
605 case CPU_CLUSTER_PM_ENTER:
606 gic_dist_save(i);
607 break;
608 case CPU_CLUSTER_PM_ENTER_FAILED:
609 case CPU_CLUSTER_PM_EXIT:
610 gic_dist_restore(i);
611 break;
612 }
613 }
614
615 return NOTIFY_OK;
616}
617
618static struct notifier_block gic_notifier_block = {
619 .notifier_call = gic_notifier,
620};
621
622static void __init gic_pm_init(struct gic_chip_data *gic)
623{
624 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
625 sizeof(u32));
626 BUG_ON(!gic->saved_ppi_enable);
627
628 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
629 sizeof(u32));
630 BUG_ON(!gic->saved_ppi_conf);
631
632 if (gic == &gic_data[0])
633 cpu_pm_register_notifier(&gic_notifier_block);
634}
635#else
636static void __init gic_pm_init(struct gic_chip_data *gic)
637{
638}
639#endif
640
641static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
642 irq_hw_number_t hw)
643{
644 if (hw < 32) {
645 irq_set_percpu_devid(irq);
646 irq_set_chip_and_handler(irq, &gic_chip,
647 handle_percpu_devid_irq);
648 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
649 } else {
650 irq_set_chip_and_handler(irq, &gic_chip,
651 handle_fasteoi_irq);
652 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
653 }
654 irq_set_chip_data(irq, d->host_data);
655 return 0;
656}
657
658static int gic_irq_domain_xlate(struct irq_domain *d,
659 struct device_node *controller,
660 const u32 *intspec, unsigned int intsize,
661 unsigned long *out_hwirq, unsigned int *out_type)
662{
663 if (d->of_node != controller)
664 return -EINVAL;
665 if (intsize < 3)
666 return -EINVAL;
667
668 /* Get the interrupt number and add 16 to skip over SGIs */
669 *out_hwirq = intspec[1] + 16;
670
671 /* For SPIs, we need to add 16 more to get the GIC irq ID number */
672 if (!intspec[0])
673 *out_hwirq += 16;
674
675 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
676 return 0;
677}
678
679const struct irq_domain_ops gic_irq_domain_ops = {
680 .map = gic_irq_domain_map,
681 .xlate = gic_irq_domain_xlate,
682};
683
684void __init gic_init_bases(unsigned int gic_nr, int irq_start,
685 void __iomem *dist_base, void __iomem *cpu_base,
686 u32 percpu_offset, struct device_node *node)
687{
688 irq_hw_number_t hwirq_base;
689 struct gic_chip_data *gic;
690 int gic_irqs, irq_base, i;
691
692 BUG_ON(gic_nr >= MAX_GIC_NR);
693
694 gic = &gic_data[gic_nr];
695#ifdef CONFIG_GIC_NON_BANKED
696 if (percpu_offset) { /* Frankein-GIC without banked registers... */
697 unsigned int cpu;
698
699 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
700 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
701 if (WARN_ON(!gic->dist_base.percpu_base ||
702 !gic->cpu_base.percpu_base)) {
703 free_percpu(gic->dist_base.percpu_base);
704 free_percpu(gic->cpu_base.percpu_base);
705 return;
706 }
707
708 for_each_possible_cpu(cpu) {
709 unsigned long offset = percpu_offset * cpu_logical_map(cpu);
710 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
711 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
712 }
713
714 gic_set_base_accessor(gic, gic_get_percpu_base);
715 } else
716#endif
717 { /* Normal, sane GIC... */
718 WARN(percpu_offset,
719 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
720 percpu_offset);
721 gic->dist_base.common_base = dist_base;
722 gic->cpu_base.common_base = cpu_base;
723 gic_set_base_accessor(gic, gic_get_common_base);
724 }
725
726 /*
727 * Initialize the CPU interface map to all CPUs.
728 * It will be refined as each CPU probes its ID.
729 */
730 for (i = 0; i < NR_GIC_CPU_IF; i++)
731 gic_cpu_map[i] = 0xff;
732
733 /*
734 * For primary GICs, skip over SGIs.
735 * For secondary GICs, skip over PPIs, too.
736 */
737 if (gic_nr == 0 && (irq_start & 31) > 0) {
738 hwirq_base = 16;
739 if (irq_start != -1)
740 irq_start = (irq_start & ~31) + 16;
741 } else {
742 hwirq_base = 32;
743 }
744
745 /*
746 * Find out how many interrupts are supported.
747 * The GIC only supports up to 1020 interrupt sources.
748 */
749 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
750 gic_irqs = (gic_irqs + 1) * 32;
751 if (gic_irqs > 1020)
752 gic_irqs = 1020;
753 gic->gic_irqs = gic_irqs;
754
755 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
756 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, numa_node_id());
757 if (IS_ERR_VALUE(irq_base)) {
758 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
759 irq_start);
760 irq_base = irq_start;
761 }
762 gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
763 hwirq_base, &gic_irq_domain_ops, gic);
764 if (WARN_ON(!gic->domain))
765 return;
766
767 gic_chip.flags |= gic_arch_extn.flags;
768 gic_dist_init(gic);
769 gic_cpu_init(gic);
770 gic_pm_init(gic);
771}
772
773void __cpuinit gic_secondary_init(unsigned int gic_nr)
774{
775 BUG_ON(gic_nr >= MAX_GIC_NR);
776
777 gic_cpu_init(&gic_data[gic_nr]);
778}
779
780#ifdef CONFIG_SMP
781void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
782{
783 int cpu;
784 unsigned long map = 0;
785
786 /* Convert our logical CPU mask into a physical one. */
787 for_each_cpu(cpu, mask)
788 map |= gic_cpu_map[cpu];
789
790 /*
791 * Ensure that stores to Normal memory are visible to the
792 * other CPUs before issuing the IPI.
793 */
794 dsb();
795
796 /* this always happens on GIC0 */
797 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
798}
799#endif
800
801#ifdef CONFIG_OF
802static int gic_cnt __initdata = 0;
803
804int __init gic_of_init(struct device_node *node, struct device_node *parent)
805{
806 void __iomem *cpu_base;
807 void __iomem *dist_base;
808 u32 percpu_offset;
809 int irq;
810
811 if (WARN_ON(!node))
812 return -ENODEV;
813
814 dist_base = of_iomap(node, 0);
815 WARN(!dist_base, "unable to map gic dist registers\n");
816
817 cpu_base = of_iomap(node, 1);
818 WARN(!cpu_base, "unable to map gic cpu registers\n");
819
820 if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
821 percpu_offset = 0;
822
823 gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
824
825 if (parent) {
826 irq = irq_of_parse_and_map(node, 0);
827 gic_cascade_irq(gic_cnt, irq);
828 }
829 gic_cnt++;
830 return 0;
831}
832#endif
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
deleted file mode 100644
index 8f324b99416e..000000000000
--- a/arch/arm/common/vic.c
+++ /dev/null
@@ -1,464 +0,0 @@
1/*
2 * linux/arch/arm/common/vic.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/export.h>
23#include <linux/init.h>
24#include <linux/list.h>
25#include <linux/io.h>
26#include <linux/irqdomain.h>
27#include <linux/of.h>
28#include <linux/of_address.h>
29#include <linux/of_irq.h>
30#include <linux/syscore_ops.h>
31#include <linux/device.h>
32#include <linux/amba/bus.h>
33
34#include <asm/exception.h>
35#include <asm/mach/irq.h>
36#include <asm/hardware/vic.h>
37
38/**
39 * struct vic_device - VIC PM device
40 * @irq: The IRQ number for the base of the VIC.
41 * @base: The register base for the VIC.
42 * @valid_sources: A bitmask of valid interrupts
43 * @resume_sources: A bitmask of interrupts for resume.
44 * @resume_irqs: The IRQs enabled for resume.
45 * @int_select: Save for VIC_INT_SELECT.
46 * @int_enable: Save for VIC_INT_ENABLE.
47 * @soft_int: Save for VIC_INT_SOFT.
48 * @protect: Save for VIC_PROTECT.
49 * @domain: The IRQ domain for the VIC.
50 */
51struct vic_device {
52 void __iomem *base;
53 int irq;
54 u32 valid_sources;
55 u32 resume_sources;
56 u32 resume_irqs;
57 u32 int_select;
58 u32 int_enable;
59 u32 soft_int;
60 u32 protect;
61 struct irq_domain *domain;
62};
63
64/* we cannot allocate memory when VICs are initially registered */
65static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
66
67static int vic_id;
68
69/**
70 * vic_init2 - common initialisation code
71 * @base: Base of the VIC.
72 *
73 * Common initialisation code for registration
74 * and resume.
75*/
76static void vic_init2(void __iomem *base)
77{
78 int i;
79
80 for (i = 0; i < 16; i++) {
81 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
82 writel(VIC_VECT_CNTL_ENABLE | i, reg);
83 }
84
85 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
86}
87
88#ifdef CONFIG_PM
89static void resume_one_vic(struct vic_device *vic)
90{
91 void __iomem *base = vic->base;
92
93 printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
94
95 /* re-initialise static settings */
96 vic_init2(base);
97
98 writel(vic->int_select, base + VIC_INT_SELECT);
99 writel(vic->protect, base + VIC_PROTECT);
100
101 /* set the enabled ints and then clear the non-enabled */
102 writel(vic->int_enable, base + VIC_INT_ENABLE);
103 writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
104
105 /* and the same for the soft-int register */
106
107 writel(vic->soft_int, base + VIC_INT_SOFT);
108 writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
109}
110
111static void vic_resume(void)
112{
113 int id;
114
115 for (id = vic_id - 1; id >= 0; id--)
116 resume_one_vic(vic_devices + id);
117}
118
119static void suspend_one_vic(struct vic_device *vic)
120{
121 void __iomem *base = vic->base;
122
123 printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
124
125 vic->int_select = readl(base + VIC_INT_SELECT);
126 vic->int_enable = readl(base + VIC_INT_ENABLE);
127 vic->soft_int = readl(base + VIC_INT_SOFT);
128 vic->protect = readl(base + VIC_PROTECT);
129
130 /* set the interrupts (if any) that are used for
131 * resuming the system */
132
133 writel(vic->resume_irqs, base + VIC_INT_ENABLE);
134 writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
135}
136
137static int vic_suspend(void)
138{
139 int id;
140
141 for (id = 0; id < vic_id; id++)
142 suspend_one_vic(vic_devices + id);
143
144 return 0;
145}
146
147struct syscore_ops vic_syscore_ops = {
148 .suspend = vic_suspend,
149 .resume = vic_resume,
150};
151
152/**
153 * vic_pm_init - initicall to register VIC pm
154 *
155 * This is called via late_initcall() to register
156 * the resources for the VICs due to the early
157 * nature of the VIC's registration.
158*/
159static int __init vic_pm_init(void)
160{
161 if (vic_id > 0)
162 register_syscore_ops(&vic_syscore_ops);
163
164 return 0;
165}
166late_initcall(vic_pm_init);
167#endif /* CONFIG_PM */
168
169static struct irq_chip vic_chip;
170
171static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq,
172 irq_hw_number_t hwirq)
173{
174 struct vic_device *v = d->host_data;
175
176 /* Skip invalid IRQs, only register handlers for the real ones */
177 if (!(v->valid_sources & (1 << hwirq)))
178 return -ENOTSUPP;
179 irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
180 irq_set_chip_data(irq, v->base);
181 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
182 return 0;
183}
184
185static struct irq_domain_ops vic_irqdomain_ops = {
186 .map = vic_irqdomain_map,
187 .xlate = irq_domain_xlate_onetwocell,
188};
189
190/**
191 * vic_register() - Register a VIC.
192 * @base: The base address of the VIC.
193 * @irq: The base IRQ for the VIC.
194 * @valid_sources: bitmask of valid interrupts
195 * @resume_sources: bitmask of interrupts allowed for resume sources.
196 * @node: The device tree node associated with the VIC.
197 *
198 * Register the VIC with the system device tree so that it can be notified
199 * of suspend and resume requests and ensure that the correct actions are
200 * taken to re-instate the settings on resume.
201 *
202 * This also configures the IRQ domain for the VIC.
203 */
204static void __init vic_register(void __iomem *base, unsigned int irq,
205 u32 valid_sources, u32 resume_sources,
206 struct device_node *node)
207{
208 struct vic_device *v;
209 int i;
210
211 if (vic_id >= ARRAY_SIZE(vic_devices)) {
212 printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
213 return;
214 }
215
216 v = &vic_devices[vic_id];
217 v->base = base;
218 v->valid_sources = valid_sources;
219 v->resume_sources = resume_sources;
220 v->irq = irq;
221 vic_id++;
222 v->domain = irq_domain_add_simple(node, fls(valid_sources), irq,
223 &vic_irqdomain_ops, v);
224 /* create an IRQ mapping for each valid IRQ */
225 for (i = 0; i < fls(valid_sources); i++)
226 if (valid_sources & (1 << i))
227 irq_create_mapping(v->domain, i);
228}
229
230static void vic_ack_irq(struct irq_data *d)
231{
232 void __iomem *base = irq_data_get_irq_chip_data(d);
233 unsigned int irq = d->hwirq;
234 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
235 /* moreover, clear the soft-triggered, in case it was the reason */
236 writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
237}
238
239static void vic_mask_irq(struct irq_data *d)
240{
241 void __iomem *base = irq_data_get_irq_chip_data(d);
242 unsigned int irq = d->hwirq;
243 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
244}
245
246static void vic_unmask_irq(struct irq_data *d)
247{
248 void __iomem *base = irq_data_get_irq_chip_data(d);
249 unsigned int irq = d->hwirq;
250 writel(1 << irq, base + VIC_INT_ENABLE);
251}
252
253#if defined(CONFIG_PM)
254static struct vic_device *vic_from_irq(unsigned int irq)
255{
256 struct vic_device *v = vic_devices;
257 unsigned int base_irq = irq & ~31;
258 int id;
259
260 for (id = 0; id < vic_id; id++, v++) {
261 if (v->irq == base_irq)
262 return v;
263 }
264
265 return NULL;
266}
267
268static int vic_set_wake(struct irq_data *d, unsigned int on)
269{
270 struct vic_device *v = vic_from_irq(d->irq);
271 unsigned int off = d->hwirq;
272 u32 bit = 1 << off;
273
274 if (!v)
275 return -EINVAL;
276
277 if (!(bit & v->resume_sources))
278 return -EINVAL;
279
280 if (on)
281 v->resume_irqs |= bit;
282 else
283 v->resume_irqs &= ~bit;
284
285 return 0;
286}
287#else
288#define vic_set_wake NULL
289#endif /* CONFIG_PM */
290
291static struct irq_chip vic_chip = {
292 .name = "VIC",
293 .irq_ack = vic_ack_irq,
294 .irq_mask = vic_mask_irq,
295 .irq_unmask = vic_unmask_irq,
296 .irq_set_wake = vic_set_wake,
297};
298
299static void __init vic_disable(void __iomem *base)
300{
301 writel(0, base + VIC_INT_SELECT);
302 writel(0, base + VIC_INT_ENABLE);
303 writel(~0, base + VIC_INT_ENABLE_CLEAR);
304 writel(0, base + VIC_ITCR);
305 writel(~0, base + VIC_INT_SOFT_CLEAR);
306}
307
308static void __init vic_clear_interrupts(void __iomem *base)
309{
310 unsigned int i;
311
312 writel(0, base + VIC_PL190_VECT_ADDR);
313 for (i = 0; i < 19; i++) {
314 unsigned int value;
315
316 value = readl(base + VIC_PL190_VECT_ADDR);
317 writel(value, base + VIC_PL190_VECT_ADDR);
318 }
319}
320
321/*
322 * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
323 * The original cell has 32 interrupts, while the modified one has 64,
324 * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
325 * the probe function is called twice, with base set to offset 000
326 * and 020 within the page. We call this "second block".
327 */
328static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
329 u32 vic_sources, struct device_node *node)
330{
331 unsigned int i;
332 int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
333
334 /* Disable all interrupts initially. */
335 vic_disable(base);
336
337 /*
338 * Make sure we clear all existing interrupts. The vector registers
339 * in this cell are after the second block of general registers,
340 * so we can address them using standard offsets, but only from
341 * the second base address, which is 0x20 in the page
342 */
343 if (vic_2nd_block) {
344 vic_clear_interrupts(base);
345
346 /* ST has 16 vectors as well, but we don't enable them by now */
347 for (i = 0; i < 16; i++) {
348 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
349 writel(0, reg);
350 }
351
352 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
353 }
354
355 vic_register(base, irq_start, vic_sources, 0, node);
356}
357
358void __init __vic_init(void __iomem *base, int irq_start,
359 u32 vic_sources, u32 resume_sources,
360 struct device_node *node)
361{
362 unsigned int i;
363 u32 cellid = 0;
364 enum amba_vendor vendor;
365
366 /* Identify which VIC cell this one is, by reading the ID */
367 for (i = 0; i < 4; i++) {
368 void __iomem *addr;
369 addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
370 cellid |= (readl(addr) & 0xff) << (8 * i);
371 }
372 vendor = (cellid >> 12) & 0xff;
373 printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
374 base, cellid, vendor);
375
376 switch(vendor) {
377 case AMBA_VENDOR_ST:
378 vic_init_st(base, irq_start, vic_sources, node);
379 return;
380 default:
381 printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
382 /* fall through */
383 case AMBA_VENDOR_ARM:
384 break;
385 }
386
387 /* Disable all interrupts initially. */
388 vic_disable(base);
389
390 /* Make sure we clear all existing interrupts */
391 vic_clear_interrupts(base);
392
393 vic_init2(base);
394
395 vic_register(base, irq_start, vic_sources, resume_sources, node);
396}
397
398/**
399 * vic_init() - initialise a vectored interrupt controller
400 * @base: iomem base address
401 * @irq_start: starting interrupt number, must be muliple of 32
402 * @vic_sources: bitmask of interrupt sources to allow
403 * @resume_sources: bitmask of interrupt sources to allow for resume
404 */
405void __init vic_init(void __iomem *base, unsigned int irq_start,
406 u32 vic_sources, u32 resume_sources)
407{
408 __vic_init(base, irq_start, vic_sources, resume_sources, NULL);
409}
410
411#ifdef CONFIG_OF
412int __init vic_of_init(struct device_node *node, struct device_node *parent)
413{
414 void __iomem *regs;
415
416 if (WARN(parent, "non-root VICs are not supported"))
417 return -EINVAL;
418
419 regs = of_iomap(node, 0);
420 if (WARN_ON(!regs))
421 return -EIO;
422
423 /*
424 * Passing 0 as first IRQ makes the simple domain allocate descriptors
425 */
426 __vic_init(regs, 0, ~0, ~0, node);
427
428 return 0;
429}
430#endif /* CONFIG OF */
431
432/*
433 * Handle each interrupt in a single VIC. Returns non-zero if we've
434 * handled at least one interrupt. This reads the status register
435 * before handling each interrupt, which is necessary given that
436 * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
437 */
438static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
439{
440 u32 stat, irq;
441 int handled = 0;
442
443 while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
444 irq = ffs(stat) - 1;
445 handle_IRQ(irq_find_mapping(vic->domain, irq), regs);
446 handled = 1;
447 }
448
449 return handled;
450}
451
452/*
453 * Keep iterating over all registered VIC's until there are no pending
454 * interrupts.
455 */
456asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
457{
458 int i, handled;
459
460 do {
461 for (i = 0, handled = 0; i < vic_id; ++i)
462 handled |= handle_one_vic(&vic_devices[i], regs);
463 } while (handled);
464}
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-05 14:04:14 -0500