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-rw-r--r--Documentation/memory-barriers.txt10
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diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
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+++ b/Documentation/memory-barriers.txt
@@ -498,11 +498,11 @@ And a couple of implicit varieties:
498 This means that ACQUIRE acts as a minimal "acquire" operation and 498 This means that ACQUIRE acts as a minimal "acquire" operation and
499 RELEASE acts as a minimal "release" operation. 499 RELEASE acts as a minimal "release" operation.
500 500
501A subset of the atomic operations described in atomic_ops.txt have ACQUIRE 501A subset of the atomic operations described in core-api/atomic_ops.rst have
502and RELEASE variants in addition to fully-ordered and relaxed (no barrier 502ACQUIRE and RELEASE variants in addition to fully-ordered and relaxed (no
503semantics) definitions. For compound atomics performing both a load and a 503barrier semantics) definitions. For compound atomics performing both a load
504store, ACQUIRE semantics apply only to the load and RELEASE semantics apply 504and a store, ACQUIRE semantics apply only to the load and RELEASE semantics
505only to the store portion of the operation. 505apply only to the store portion of the operation.
506 506
507Memory barriers are only required where there's a possibility of interaction 507Memory barriers are only required where there's a possibility of interaction
508between two CPUs or between a CPU and a device. If it can be guaranteed that 508between two CPUs or between a CPU and a device. If it can be guaranteed that