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-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt2
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt22
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt2
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt22
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt22
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt22
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt22
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt2
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt22
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt22
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt2
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/clk-exynos-audss.txt6
-rw-r--r--Documentation/devicetree/bindings/clock/exynos4-clock.txt43
-rw-r--r--Documentation/devicetree/bindings/clock/exynos5433-clock.txt16
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,rpmcc.txt11
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt5
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt4
-rw-r--r--Documentation/driver-model/devres.txt1
-rw-r--r--MAINTAINERS1
-rw-r--r--drivers/clk/at91/clk-utmi.c95
-rw-r--r--drivers/clk/bcm/clk-kona-setup.c7
-rw-r--r--drivers/clk/clk-cdce925.c2
-rw-r--r--drivers/clk/clk-gpio.c84
-rw-r--r--drivers/clk/clk-hsdk-pll.c4
-rw-r--r--drivers/clk/clk-mux.c6
-rw-r--r--drivers/clk/clk-stm32h7.c4
-rw-r--r--drivers/clk/clk-twl6040.c2
-rw-r--r--drivers/clk/clk-u300.c84
-rw-r--r--drivers/clk/clk-wm831x.c6
-rw-r--r--drivers/clk/clk-xgene.c20
-rw-r--r--drivers/clk/clk.c178
-rw-r--r--drivers/clk/hisilicon/clk-hi3620.c2
-rw-r--r--drivers/clk/hisilicon/clk-hi3660.c2
-rw-r--r--drivers/clk/hisilicon/clk-hi6220.c2
-rw-r--r--drivers/clk/hisilicon/clk-hix5hd2.c4
-rw-r--r--drivers/clk/hisilicon/clkgate-separated.c6
-rw-r--r--drivers/clk/hisilicon/crg-hi3798cv200.c12
-rw-r--r--drivers/clk/imx/clk-busy.c4
-rw-r--r--drivers/clk/imx/clk-gate2.c2
-rw-r--r--drivers/clk/imx/clk-imx6q.c2
-rw-r--r--drivers/clk/imx/clk-imx6ul.c2
-rw-r--r--drivers/clk/imx/clk-imx7d.c11
-rw-r--r--drivers/clk/imx/clk-pllv1.c2
-rw-r--r--drivers/clk/imx/clk-pllv2.c2
-rw-r--r--drivers/clk/mediatek/Kconfig80
-rw-r--r--drivers/clk/mediatek/Makefile12
-rw-r--r--drivers/clk/mediatek/clk-mt2701.c2
-rw-r--r--drivers/clk/mediatek/clk-mt2712-bdp.c102
-rw-r--r--drivers/clk/mediatek/clk-mt2712-img.c80
-rw-r--r--drivers/clk/mediatek/clk-mt2712-jpgdec.c76
-rw-r--r--drivers/clk/mediatek/clk-mt2712-mfg.c75
-rw-r--r--drivers/clk/mediatek/clk-mt2712-mm.c170
-rw-r--r--drivers/clk/mediatek/clk-mt2712-vdec.c94
-rw-r--r--drivers/clk/mediatek/clk-mt2712-venc.c77
-rw-r--r--drivers/clk/mediatek/clk-mt2712.c1435
-rw-r--r--drivers/clk/mediatek/clk-mt7622-aud.c195
-rw-r--r--drivers/clk/mediatek/clk-mt7622-eth.c156
-rw-r--r--drivers/clk/mediatek/clk-mt7622-hif.c169
-rw-r--r--drivers/clk/mediatek/clk-mt7622.c780
-rw-r--r--drivers/clk/mediatek/clk-mtk.h3
-rw-r--r--drivers/clk/mediatek/clk-pll.c18
-rw-r--r--drivers/clk/meson/gxbb.c292
-rw-r--r--drivers/clk/meson/gxbb.h6
-rw-r--r--drivers/clk/mmp/clk-apbc.c2
-rw-r--r--drivers/clk/mmp/clk-apmu.c2
-rw-r--r--drivers/clk/mmp/clk-frac.c6
-rw-r--r--drivers/clk/mmp/clk-gate.c4
-rw-r--r--drivers/clk/mmp/clk-mix.c27
-rw-r--r--drivers/clk/mmp/clk-mmp2.c6
-rw-r--r--drivers/clk/mmp/clk-pxa168.c6
-rw-r--r--drivers/clk/mmp/clk-pxa910.c8
-rw-r--r--drivers/clk/mxs/clk-div.c2
-rw-r--r--drivers/clk/mxs/clk-frac.c2
-rw-r--r--drivers/clk/pxa/clk-pxa.c4
-rw-r--r--drivers/clk/qcom/clk-rcg.h3
-rw-r--r--drivers/clk/qcom/clk-rcg2.c79
-rw-r--r--drivers/clk/qcom/clk-rpm.c93
-rw-r--r--drivers/clk/qcom/clk-smd-rpm.c82
-rw-r--r--drivers/clk/qcom/common.c32
-rw-r--r--drivers/clk/renesas/Kconfig5
-rw-r--r--drivers/clk/renesas/Makefile1
-rw-r--r--drivers/clk/renesas/clk-div6.c38
-rw-r--r--drivers/clk/renesas/clk-div6.h3
-rw-r--r--drivers/clk/renesas/clk-mstp.c5
-rw-r--r--drivers/clk/renesas/clk-rcar-gen2.c1
-rw-r--r--drivers/clk/renesas/clk-rz.c2
-rw-r--r--drivers/clk/renesas/r8a7745-cpg-mssr.c1
-rw-r--r--drivers/clk/renesas/r8a7795-cpg-mssr.c3
-rw-r--r--drivers/clk/renesas/r8a7796-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/r8a77970-cpg-mssr.c199
-rw-r--r--drivers/clk/renesas/r8a77995-cpg-mssr.c2
-rw-r--r--drivers/clk/renesas/rcar-gen2-cpg.c7
-rw-r--r--drivers/clk/renesas/rcar-gen2-cpg.h6
-rw-r--r--drivers/clk/renesas/rcar-gen3-cpg.c79
-rw-r--r--drivers/clk/renesas/rcar-gen3-cpg.h3
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.c105
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.h4
-rw-r--r--drivers/clk/rockchip/clk-cpu.c2
-rw-r--r--drivers/clk/rockchip/clk-rk3188.c12
-rw-r--r--drivers/clk/rockchip/clk-rk3368.c2
-rw-r--r--drivers/clk/samsung/Makefile1
-rw-r--r--drivers/clk/samsung/clk-cpu.c2
-rw-r--r--drivers/clk/samsung/clk-exynos-audss.c76
-rw-r--r--drivers/clk/samsung/clk-exynos-clkout.c2
-rw-r--r--drivers/clk/samsung/clk-exynos4.c111
-rw-r--r--drivers/clk/samsung/clk-exynos4412-isp.c179
-rw-r--r--drivers/clk/samsung/clk-exynos5250.c18
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c5
-rw-r--r--drivers/clk/samsung/clk-exynos5433.c409
-rw-r--r--drivers/clk/samsung/clk-exynos5440.c12
-rw-r--r--drivers/clk/samsung/clk-pll.c11
-rw-r--r--drivers/clk/samsung/clk-s3c2443.c16
-rw-r--r--drivers/clk/samsung/clk.c45
-rw-r--r--drivers/clk/samsung/clk.h80
-rw-r--r--drivers/clk/sirf/clk-atlas6.c2
-rw-r--r--drivers/clk/sirf/clk-atlas7.c18
-rw-r--r--drivers/clk/sirf/clk-common.c92
-rw-r--r--drivers/clk/sirf/clk-prima2.c2
-rw-r--r--drivers/clk/spear/clk-aux-synth.c10
-rw-r--r--drivers/clk/spear/clk-frac-synth.c6
-rw-r--r--drivers/clk/spear/clk-gpt-synth.c6
-rw-r--r--drivers/clk/spear/clk-vco-pll.c12
-rw-r--r--drivers/clk/spear/clk.h4
-rw-r--r--drivers/clk/spear/spear1310_clock.c2
-rw-r--r--drivers/clk/spear/spear1340_clock.c2
-rw-r--r--drivers/clk/sunxi-ng/Makefile1
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun4i-a10.c28
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun4i-a10.h4
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun5i.c27
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun6i-a31.c40
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun6i-a31.h8
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-a23.c38
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-a83t.c6
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-de2.c21
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-h3.c56
-rw-r--r--drivers/clk/sunxi-ng/ccu_common.h1
-rw-r--r--drivers/clk/sunxi-ng/ccu_nm.c25
-rw-r--r--drivers/clk/sunxi-ng/ccu_nm.h25
-rw-r--r--drivers/clk/sunxi-ng/ccu_reset.c14
-rw-r--r--drivers/clk/sunxi-ng/ccu_sdm.c158
-rw-r--r--drivers/clk/sunxi-ng/ccu_sdm.h80
-rw-r--r--drivers/clk/sunxi/clk-factors.c2
-rw-r--r--drivers/clk/sunxi/clk-sun9i-mmc.c2
-rw-r--r--drivers/clk/tegra/clk-bpmp.c15
-rw-r--r--drivers/clk/tegra/clk-dfll.c10
-rw-r--r--drivers/clk/tegra/clk-dfll.h2
-rw-r--r--drivers/clk/tegra/clk-id.h1
-rw-r--r--drivers/clk/tegra/clk-periph.c8
-rw-r--r--drivers/clk/tegra/clk-tegra-periph.c24
-rw-r--r--drivers/clk/tegra/clk-tegra-super-gen4.c2
-rw-r--r--drivers/clk/tegra/clk-tegra114.c4
-rw-r--r--drivers/clk/tegra/clk-tegra124-dfll-fcpu.c12
-rw-r--r--drivers/clk/tegra/clk-tegra20.c13
-rw-r--r--drivers/clk/tegra/clk-tegra210.c51
-rw-r--r--drivers/clk/tegra/clk-tegra30.c23
-rw-r--r--drivers/clk/tegra/clk.h3
-rw-r--r--drivers/clk/ti/clk-dra7-atl.c3
-rw-r--r--drivers/clk/ti/divider.c4
-rw-r--r--drivers/clk/ti/mux.c4
-rw-r--r--drivers/clk/uniphier/clk-uniphier-mio.c7
-rw-r--r--drivers/clk/uniphier/clk-uniphier-sys.c2
-rw-r--r--drivers/clk/ux500/clk-prcc.c6
-rw-r--r--drivers/clk/ux500/clk-prcmu.c6
-rw-r--r--drivers/clk/ux500/clk-sysctrl.c6
-rw-r--r--drivers/clk/versatile/clk-icst.c7
-rw-r--r--include/dt-bindings/clock/exynos4.h35
-rw-r--r--include/dt-bindings/clock/gxbb-clkc.h11
-rw-r--r--include/dt-bindings/clock/imx7d-clock.h8
-rw-r--r--include/dt-bindings/clock/mt2712-clk.h427
-rw-r--r--include/dt-bindings/clock/mt7622-clk.h289
-rw-r--r--include/dt-bindings/clock/qcom,rpmcc.h17
-rw-r--r--include/dt-bindings/clock/r8a77970-cpg-mssr.h48
-rw-r--r--include/dt-bindings/clock/s3c2443.h2
-rw-r--r--include/dt-bindings/clock/sun4i-a10-ccu.h2
-rw-r--r--include/dt-bindings/clock/sun6i-a31-ccu.h4
-rw-r--r--include/linux/clk-provider.h25
-rw-r--r--include/linux/soc/qcom/smd-rpm.h4
-rw-r--r--include/soc/at91/atmel-sfr.h2
185 files changed, 7230 insertions, 979 deletions
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
index cd977db7630c..b404d592ce58 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
@@ -7,7 +7,9 @@ Required Properties:
7 7
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-apmixedsys" 9 - "mediatek,mt2701-apmixedsys"
10 - "mediatek,mt2712-apmixedsys", "syscon"
10 - "mediatek,mt6797-apmixedsys" 11 - "mediatek,mt6797-apmixedsys"
12 - "mediatek,mt7622-apmixedsys"
11 - "mediatek,mt8135-apmixedsys" 13 - "mediatek,mt8135-apmixedsys"
12 - "mediatek,mt8173-apmixedsys" 14 - "mediatek,mt8173-apmixedsys"
13- #clock-cells: Must be 1 15- #clock-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
new file mode 100644
index 000000000000..9b8f578d5e19
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
@@ -0,0 +1,22 @@
1MediaTek AUDSYS controller
2============================
3
4The MediaTek AUDSYS controller provides various clocks to the system.
5
6Required Properties:
7
8- compatible: Should be one of:
9 - "mediatek,mt7622-audsys", "syscon"
10- #clock-cells: Must be 1
11
12The AUDSYS controller uses the common clk binding from
13Documentation/devicetree/bindings/clock/clock-bindings.txt
14The available clocks are defined in dt-bindings/clock/mt*-clk.h.
15
16Example:
17
18audsys: audsys@11220000 {
19 compatible = "mediatek,mt7622-audsys", "syscon";
20 reg = <0 0x11220000 0 0x1000>;
21 #clock-cells = <1>;
22};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
index 4137196dd686..4010e37c53a0 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,bdpsys.txt
@@ -7,6 +7,7 @@ Required Properties:
7 7
8- compatible: Should be: 8- compatible: Should be:
9 - "mediatek,mt2701-bdpsys", "syscon" 9 - "mediatek,mt2701-bdpsys", "syscon"
10 - "mediatek,mt2712-bdpsys", "syscon"
10- #clock-cells: Must be 1 11- #clock-cells: Must be 1
11 12
12The bdpsys controller uses the common clk binding from 13The bdpsys controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
index 768f3a5bc055..7aa3fa167668 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
@@ -7,6 +7,7 @@ Required Properties:
7 7
8- compatible: Should be: 8- compatible: Should be:
9 - "mediatek,mt2701-ethsys", "syscon" 9 - "mediatek,mt2701-ethsys", "syscon"
10 - "mediatek,mt7622-ethsys", "syscon"
10- #clock-cells: Must be 1 11- #clock-cells: Must be 1
11 12
12The ethsys controller uses the common clk binding from 13The ethsys controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
index beed7b594cea..f5629d64cef2 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt
@@ -8,6 +8,7 @@ Required Properties:
8 8
9- compatible: Should be: 9- compatible: Should be:
10 - "mediatek,mt2701-hifsys", "syscon" 10 - "mediatek,mt2701-hifsys", "syscon"
11 - "mediatek,mt7622-hifsys", "syscon"
11- #clock-cells: Must be 1 12- #clock-cells: Must be 1
12 13
13The hifsys controller uses the common clk binding from 14The hifsys controller uses the common clk binding from
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
index 047b11ae5f45..868bd51a98be 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
@@ -7,6 +7,7 @@ Required Properties:
7 7
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-imgsys", "syscon" 9 - "mediatek,mt2701-imgsys", "syscon"
10 - "mediatek,mt2712-imgsys", "syscon"
10 - "mediatek,mt6797-imgsys", "syscon" 11 - "mediatek,mt6797-imgsys", "syscon"
11 - "mediatek,mt8173-imgsys", "syscon" 12 - "mediatek,mt8173-imgsys", "syscon"
12- #clock-cells: Must be 1 13- #clock-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
index 58d58e2006b8..566f153f9f83 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
@@ -8,7 +8,9 @@ Required Properties:
8 8
9- compatible: Should be one of: 9- compatible: Should be one of:
10 - "mediatek,mt2701-infracfg", "syscon" 10 - "mediatek,mt2701-infracfg", "syscon"
11 - "mediatek,mt2712-infracfg", "syscon"
11 - "mediatek,mt6797-infracfg", "syscon" 12 - "mediatek,mt6797-infracfg", "syscon"
13 - "mediatek,mt7622-infracfg", "syscon"
12 - "mediatek,mt8135-infracfg", "syscon" 14 - "mediatek,mt8135-infracfg", "syscon"
13 - "mediatek,mt8173-infracfg", "syscon" 15 - "mediatek,mt8173-infracfg", "syscon"
14- #clock-cells: Must be 1 16- #clock-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt
new file mode 100644
index 000000000000..2df799cd06a7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,jpgdecsys.txt
@@ -0,0 +1,22 @@
1Mediatek jpgdecsys controller
2============================
3
4The Mediatek jpgdecsys controller provides various clocks to the system.
5
6Required Properties:
7
8- compatible: Should be:
9 - "mediatek,mt2712-jpgdecsys", "syscon"
10- #clock-cells: Must be 1
11
12The jpgdecsys controller uses the common clk binding from
13Documentation/devicetree/bindings/clock/clock-bindings.txt
14The available clocks are defined in dt-bindings/clock/mt*-clk.h.
15
16Example:
17
18jpgdecsys: syscon@19000000 {
19 compatible = "mediatek,mt2712-jpgdecsys", "syscon";
20 reg = <0 0x19000000 0 0x1000>;
21 #clock-cells = <1>;
22};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt
new file mode 100644
index 000000000000..b8fb03f3613e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mcucfg.txt
@@ -0,0 +1,22 @@
1Mediatek mcucfg controller
2============================
3
4The Mediatek mcucfg controller provides various clocks to the system.
5
6Required Properties:
7
8- compatible: Should be one of:
9 - "mediatek,mt2712-mcucfg", "syscon"
10- #clock-cells: Must be 1
11
12The mcucfg controller uses the common clk binding from
13Documentation/devicetree/bindings/clock/clock-bindings.txt
14The available clocks are defined in dt-bindings/clock/mt*-clk.h.
15
16Example:
17
18mcucfg: syscon@10220000 {
19 compatible = "mediatek,mt2712-mcucfg", "syscon";
20 reg = <0 0x10220000 0 0x1000>;
21 #clock-cells = <1>;
22};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
new file mode 100644
index 000000000000..859e67b416d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
@@ -0,0 +1,22 @@
1Mediatek mfgcfg controller
2============================
3
4The Mediatek mfgcfg controller provides various clocks to the system.
5
6Required Properties:
7
8- compatible: Should be one of:
9 - "mediatek,mt2712-mfgcfg", "syscon"
10- #clock-cells: Must be 1
11
12The mfgcfg controller uses the common clk binding from
13Documentation/devicetree/bindings/clock/clock-bindings.txt
14The available clocks are defined in dt-bindings/clock/mt*-clk.h.
15
16Example:
17
18mfgcfg: syscon@13000000 {
19 compatible = "mediatek,mt2712-mfgcfg", "syscon";
20 reg = <0 0x13000000 0 0x1000>;
21 #clock-cells = <1>;
22};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
index 70529e0b58e9..4eb8bbe15c01 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
@@ -7,6 +7,7 @@ Required Properties:
7 7
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-mmsys", "syscon" 9 - "mediatek,mt2701-mmsys", "syscon"
10 - "mediatek,mt2712-mmsys", "syscon"
10 - "mediatek,mt6797-mmsys", "syscon" 11 - "mediatek,mt6797-mmsys", "syscon"
11 - "mediatek,mt8173-mmsys", "syscon" 12 - "mediatek,mt8173-mmsys", "syscon"
12- #clock-cells: Must be 1 13- #clock-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
new file mode 100644
index 000000000000..d5d5f1227665
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt
@@ -0,0 +1,22 @@
1MediaTek PCIESYS controller
2============================
3
4The MediaTek PCIESYS controller provides various clocks to the system.
5
6Required Properties:
7
8- compatible: Should be:
9 - "mediatek,mt7622-pciesys", "syscon"
10- #clock-cells: Must be 1
11
12The PCIESYS controller uses the common clk binding from
13Documentation/devicetree/bindings/clock/clock-bindings.txt
14The available clocks are defined in dt-bindings/clock/mt*-clk.h.
15
16Example:
17
18pciesys: pciesys@1a100800 {
19 compatible = "mediatek,mt7622-pciesys", "syscon";
20 reg = <0 0x1a100800 0 0x1000>;
21 #clock-cells = <1>;
22};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
index e494366782aa..fb58ca8c2770 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
@@ -8,6 +8,8 @@ Required Properties:
8 8
9- compatible: Should be one of: 9- compatible: Should be one of:
10 - "mediatek,mt2701-pericfg", "syscon" 10 - "mediatek,mt2701-pericfg", "syscon"
11 - "mediatek,mt2712-pericfg", "syscon"
12 - "mediatek,mt7622-pericfg", "syscon"
11 - "mediatek,mt8135-pericfg", "syscon" 13 - "mediatek,mt8135-pericfg", "syscon"
12 - "mediatek,mt8173-pericfg", "syscon" 14 - "mediatek,mt8173-pericfg", "syscon"
13- #clock-cells: Must be 1 15- #clock-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
new file mode 100644
index 000000000000..d113b8e741f3
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,sgmiisys.txt
@@ -0,0 +1,22 @@
1MediaTek SGMIISYS controller
2============================
3
4The MediaTek SGMIISYS controller provides various clocks to the system.
5
6Required Properties:
7
8- compatible: Should be:
9 - "mediatek,mt7622-sgmiisys", "syscon"
10- #clock-cells: Must be 1
11
12The SGMIISYS controller uses the common clk binding from
13Documentation/devicetree/bindings/clock/clock-bindings.txt
14The available clocks are defined in dt-bindings/clock/mt*-clk.h.
15
16Example:
17
18sgmiisys: sgmiisys@1b128000 {
19 compatible = "mediatek,mt7622-sgmiisys", "syscon";
20 reg = <0 0x1b128000 0 0x1000>;
21 #clock-cells = <1>;
22};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
new file mode 100644
index 000000000000..00760019da00
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt
@@ -0,0 +1,22 @@
1MediaTek SSUSBSYS controller
2============================
3
4The MediaTek SSUSBSYS controller provides various clocks to the system.
5
6Required Properties:
7
8- compatible: Should be:
9 - "mediatek,mt7622-ssusbsys", "syscon"
10- #clock-cells: Must be 1
11
12The SSUSBSYS controller uses the common clk binding from
13Documentation/devicetree/bindings/clock/clock-bindings.txt
14The available clocks are defined in dt-bindings/clock/mt*-clk.h.
15
16Example:
17
18ssusbsys: ssusbsys@1a000000 {
19 compatible = "mediatek,mt7622-ssusbsys", "syscon";
20 reg = <0 0x1a000000 0 0x1000>;
21 #clock-cells = <1>;
22};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
index ec93ecbb9f3c..24014a7e2332 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
@@ -7,7 +7,9 @@ Required Properties:
7 7
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-topckgen" 9 - "mediatek,mt2701-topckgen"
10 - "mediatek,mt2712-topckgen", "syscon"
10 - "mediatek,mt6797-topckgen" 11 - "mediatek,mt6797-topckgen"
12 - "mediatek,mt7622-topckgen"
11 - "mediatek,mt8135-topckgen" 13 - "mediatek,mt8135-topckgen"
12 - "mediatek,mt8173-topckgen" 14 - "mediatek,mt8173-topckgen"
13- #clock-cells: Must be 1 15- #clock-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
index d150104f928a..ea40d05089f8 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
@@ -7,6 +7,7 @@ Required Properties:
7 7
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-vdecsys", "syscon" 9 - "mediatek,mt2701-vdecsys", "syscon"
10 - "mediatek,mt2712-vdecsys", "syscon"
10 - "mediatek,mt6797-vdecsys", "syscon" 11 - "mediatek,mt6797-vdecsys", "syscon"
11 - "mediatek,mt8173-vdecsys", "syscon" 12 - "mediatek,mt8173-vdecsys", "syscon"
12- #clock-cells: Must be 1 13- #clock-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
index 8a93be643647..851545357e94 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
@@ -6,6 +6,7 @@ The Mediatek vencsys controller provides various clocks to the system.
6Required Properties: 6Required Properties:
7 7
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2712-vencsys", "syscon"
9 - "mediatek,mt6797-vencsys", "syscon" 10 - "mediatek,mt6797-vencsys", "syscon"
10 - "mediatek,mt8173-vencsys", "syscon" 11 - "mediatek,mt8173-vencsys", "syscon"
11- #clock-cells: Must be 1 12- #clock-cells: Must be 1
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index 2cba012f5af0..6030afb10b5c 100644
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -33,6 +33,12 @@ Required Properties:
33- clock-names: Aliases for the above clocks. They should be "pll_ref", 33- clock-names: Aliases for the above clocks. They should be "pll_ref",
34 "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively. 34 "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
35 35
36Optional Properties:
37
38 - power-domains: a phandle to respective power domain node as described by
39 generic PM domain bindings (see power/power_domain.txt for more
40 information).
41
36The following is the list of clocks generated by the controller. Each clock is 42The following is the list of clocks generated by the controller. Each clock is
37assigned an identifier and client nodes use this identifier to specify the 43assigned an identifier and client nodes use this identifier to specify the
38clock which they consume. Some of the clocks are available only on a particular 44clock which they consume. Some of the clocks are available only on a particular
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
index f5a5b19ed3b2..bc61c952cb0b 100644
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
@@ -41,3 +41,46 @@ Example 2: UART controller node that consumes the clock generated by the clock
41 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; 41 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
42 clock-names = "uart", "clk_uart_baud0"; 42 clock-names = "uart", "clk_uart_baud0";
43 }; 43 };
44
45Exynos4412 SoC contains some additional clocks for FIMC-ISP (Camera ISP)
46subsystem. Registers for those clocks are located in the ISP power domain.
47Because those registers are also located in a different memory region than
48the main clock controller, a separate clock controller has to be defined for
49handling them.
50
51Required Properties:
52
53- compatible: should be "samsung,exynos4412-isp-clock".
54
55- reg: physical base address of the ISP clock controller and length of memory
56 mapped region.
57
58- #clock-cells: should be 1.
59
60- clocks: list of the clock controller input clock identifiers,
61 from common clock bindings, should point to CLK_ACLK200 and
62 CLK_ACLK400_MCUISP clocks from the main clock controller.
63
64- clock-names: list of the clock controller input clock names,
65 as described in clock-bindings.txt, should be "aclk200" and
66 "aclk400_mcuisp".
67
68- power-domains: a phandle to ISP power domain node as described by
69 generic PM domain bindings.
70
71Example 3: The clock controllers bindings for Exynos4412 SoCs.
72
73 clock: clock-controller@10030000 {
74 compatible = "samsung,exynos4412-clock";
75 reg = <0x10030000 0x18000>;
76 #clock-cells = <1>;
77 };
78
79 isp_clock: clock-controller@10048000 {
80 compatible = "samsung,exynos4412-isp-clock";
81 reg = <0x10048000 0x1000>;
82 #clock-cells = <1>;
83 power-domains = <&pd_isp>;
84 clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
85 clock-names = "aclk200", "aclk400_mcuisp";
86 };
diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index fe885abc9cb4..c473dd38dd55 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -168,6 +168,11 @@ Required Properties:
168 - aclk_cam1_400 168 - aclk_cam1_400
169 - aclk_cam1_552 169 - aclk_cam1_552
170 170
171Optional properties:
172 - power-domains: a phandle to respective power domain node as described by
173 generic PM domain bindings (see power/power_domain.txt for more
174 information).
175
171Each clock is assigned an identifier and client nodes can use this identifier 176Each clock is assigned an identifier and client nodes can use this identifier
172to specify the clock which they consume. 177to specify the clock which they consume.
173 178
@@ -270,6 +275,7 @@ Example 2: Examples of clock controller nodes are listed below.
270 clocks = <&xxti>, 275 clocks = <&xxti>,
271 <&cmu_top CLK_ACLK_G2D_266>, 276 <&cmu_top CLK_ACLK_G2D_266>,
272 <&cmu_top CLK_ACLK_G2D_400>; 277 <&cmu_top CLK_ACLK_G2D_400>;
278 power-domains = <&pd_g2d>;
273 }; 279 };
274 280
275 cmu_disp: clock-controller@13b90000 { 281 cmu_disp: clock-controller@13b90000 {
@@ -295,6 +301,7 @@ Example 2: Examples of clock controller nodes are listed below.
295 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, 301 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
296 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, 302 <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
297 <&cmu_mif CLK_ACLK_DISP_333>; 303 <&cmu_mif CLK_ACLK_DISP_333>;
304 power-domains = <&pd_disp>;
298 }; 305 };
299 306
300 cmu_aud: clock-controller@114c0000 { 307 cmu_aud: clock-controller@114c0000 {
@@ -304,6 +311,7 @@ Example 2: Examples of clock controller nodes are listed below.
304 311
305 clock-names = "oscclk", "fout_aud_pll"; 312 clock-names = "oscclk", "fout_aud_pll";
306 clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>; 313 clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
314 power-domains = <&pd_aud>;
307 }; 315 };
308 316
309 cmu_bus0: clock-controller@13600000 { 317 cmu_bus0: clock-controller@13600000 {
@@ -340,6 +348,7 @@ Example 2: Examples of clock controller nodes are listed below.
340 348
341 clock-names = "oscclk", "aclk_g3d_400"; 349 clock-names = "oscclk", "aclk_g3d_400";
342 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>; 350 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
351 power-domains = <&pd_g3d>;
343 }; 352 };
344 353
345 cmu_gscl: clock-controller@13cf0000 { 354 cmu_gscl: clock-controller@13cf0000 {
@@ -353,6 +362,7 @@ Example 2: Examples of clock controller nodes are listed below.
353 clocks = <&xxti>, 362 clocks = <&xxti>,
354 <&cmu_top CLK_ACLK_GSCL_111>, 363 <&cmu_top CLK_ACLK_GSCL_111>,
355 <&cmu_top CLK_ACLK_GSCL_333>; 364 <&cmu_top CLK_ACLK_GSCL_333>;
365 power-domains = <&pd_gscl>;
356 }; 366 };
357 367
358 cmu_apollo: clock-controller@11900000 { 368 cmu_apollo: clock-controller@11900000 {
@@ -384,6 +394,7 @@ Example 2: Examples of clock controller nodes are listed below.
384 clocks = <&xxti>, 394 clocks = <&xxti>,
385 <&cmu_top CLK_SCLK_JPEG_MSCL>, 395 <&cmu_top CLK_SCLK_JPEG_MSCL>,
386 <&cmu_top CLK_ACLK_MSCL_400>; 396 <&cmu_top CLK_ACLK_MSCL_400>;
397 power-domains = <&pd_mscl>;
387 }; 398 };
388 399
389 cmu_mfc: clock-controller@15280000 { 400 cmu_mfc: clock-controller@15280000 {
@@ -393,6 +404,7 @@ Example 2: Examples of clock controller nodes are listed below.
393 404
394 clock-names = "oscclk", "aclk_mfc_400"; 405 clock-names = "oscclk", "aclk_mfc_400";
395 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>; 406 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
407 power-domains = <&pd_mfc>;
396 }; 408 };
397 409
398 cmu_hevc: clock-controller@14f80000 { 410 cmu_hevc: clock-controller@14f80000 {
@@ -402,6 +414,7 @@ Example 2: Examples of clock controller nodes are listed below.
402 414
403 clock-names = "oscclk", "aclk_hevc_400"; 415 clock-names = "oscclk", "aclk_hevc_400";
404 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>; 416 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
417 power-domains = <&pd_hevc>;
405 }; 418 };
406 419
407 cmu_isp: clock-controller@146d0000 { 420 cmu_isp: clock-controller@146d0000 {
@@ -415,6 +428,7 @@ Example 2: Examples of clock controller nodes are listed below.
415 clocks = <&xxti>, 428 clocks = <&xxti>,
416 <&cmu_top CLK_ACLK_ISP_DIS_400>, 429 <&cmu_top CLK_ACLK_ISP_DIS_400>,
417 <&cmu_top CLK_ACLK_ISP_400>; 430 <&cmu_top CLK_ACLK_ISP_400>;
431 power-domains = <&pd_isp>;
418 }; 432 };
419 433
420 cmu_cam0: clock-controller@120d0000 { 434 cmu_cam0: clock-controller@120d0000 {
@@ -430,6 +444,7 @@ Example 2: Examples of clock controller nodes are listed below.
430 <&cmu_top CLK_ACLK_CAM0_333>, 444 <&cmu_top CLK_ACLK_CAM0_333>,
431 <&cmu_top CLK_ACLK_CAM0_400>, 445 <&cmu_top CLK_ACLK_CAM0_400>,
432 <&cmu_top CLK_ACLK_CAM0_552>; 446 <&cmu_top CLK_ACLK_CAM0_552>;
447 power-domains = <&pd_cam0>;
433 }; 448 };
434 449
435 cmu_cam1: clock-controller@145d0000 { 450 cmu_cam1: clock-controller@145d0000 {
@@ -451,6 +466,7 @@ Example 2: Examples of clock controller nodes are listed below.
451 <&cmu_top CLK_ACLK_CAM1_333>, 466 <&cmu_top CLK_ACLK_CAM1_333>,
452 <&cmu_top CLK_ACLK_CAM1_400>, 467 <&cmu_top CLK_ACLK_CAM1_400>,
453 <&cmu_top CLK_ACLK_CAM1_552>; 468 <&cmu_top CLK_ACLK_CAM1_552>;
469 power-domains = <&pd_cam1>;
454 }; 470 };
455 471
456Example 3: UART controller node that consumes the clock generated by the clock 472Example 3: UART controller node that consumes the clock generated by the clock
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
index a7235e9e1c97..4491d1c104aa 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
@@ -10,12 +10,23 @@ Required properties :
10- compatible : shall contain only one of the following. The generic 10- compatible : shall contain only one of the following. The generic
11 compatible "qcom,rpmcc" should be also included. 11 compatible "qcom,rpmcc" should be also included.
12 12
13 "qcom,rpmcc-msm8660", "qcom,rpmcc"
14 "qcom,rpmcc-apq8060", "qcom,rpmcc"
13 "qcom,rpmcc-msm8916", "qcom,rpmcc" 15 "qcom,rpmcc-msm8916", "qcom,rpmcc"
14 "qcom,rpmcc-msm8974", "qcom,rpmcc" 16 "qcom,rpmcc-msm8974", "qcom,rpmcc"
15 "qcom,rpmcc-apq8064", "qcom,rpmcc" 17 "qcom,rpmcc-apq8064", "qcom,rpmcc"
18 "qcom,rpmcc-msm8996", "qcom,rpmcc"
16 19
17- #clock-cells : shall contain 1 20- #clock-cells : shall contain 1
18 21
22The clock enumerators are defined in <dt-bindings/clock/qcom,rpmcc.h>
23and come in pairs: FOO_CLK followed by FOO_A_CLK. The latter clock
24is an "active" clock, which means that the consumer only care that the
25clock is available when the apps CPU subsystem is active, i.e. not
26suspended or in deep idle. If it is important that the clock keeps running
27during system suspend, you need to specify the non-active clock, the one
28not containing *_A_* in the enumerator name.
29
19Example: 30Example:
20 smd { 31 smd {
21 compatible = "qcom,smd"; 32 compatible = "qcom,smd";
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
index 316e13686568..f1890d0777a6 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
@@ -22,6 +22,7 @@ Required Properties:
22 - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2) 22 - "renesas,r8a7794-cpg-mssr" for the r8a7794 SoC (R-Car E2)
23 - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3) 23 - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
24 - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W) 24 - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
25 - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)
25 - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3) 26 - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)
26 27
27 - reg: Base address and length of the memory resource used by the CPG/MSSR 28 - reg: Base address and length of the memory resource used by the CPG/MSSR
@@ -31,8 +32,8 @@ Required Properties:
31 clock-names 32 clock-names
32 - clock-names: List of external parent clock names. Valid names are: 33 - clock-names: List of external parent clock names. Valid names are:
33 - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794, 34 - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,
34 r8a7795, r8a7796, r8a77995) 35 r8a7795, r8a7796, r8a77970, r8a77995)
35 - "extalr" (r8a7795, r8a7796) 36 - "extalr" (r8a7795, r8a7796, r8a77970)
36 - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794) 37 - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)
37 38
38 - #clock-cells: Must be 2 39 - #clock-cells: Must be 2
diff --git a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
index bb5d942075fb..8ff3e2774ed8 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,rz-cpg-clocks.txt
@@ -1,6 +1,6 @@
1* Renesas RZ Clock Pulse Generator (CPG) 1* Renesas RZ/A1 Clock Pulse Generator (CPG)
2 2
3The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable 3The CPG generates core clocks for the RZ/A1 SoCs. It includes the PLL, variable
4CPU and GPU clocks, and several fixed ratio dividers. 4CPU and GPU clocks, and several fixed ratio dividers.
5The CPG also provides a Clock Domain for SoC devices, in combination with the 5The CPG also provides a Clock Domain for SoC devices, in combination with the
6CPG Module Stop (MSTP) Clocks. 6CPG Module Stop (MSTP) Clocks.
diff --git a/Documentation/driver-model/devres.txt b/Documentation/driver-model/devres.txt
index 69f08c0f23a8..c180045eb43b 100644
--- a/Documentation/driver-model/devres.txt
+++ b/Documentation/driver-model/devres.txt
@@ -237,6 +237,7 @@ CLOCK
237 devm_clk_get() 237 devm_clk_get()
238 devm_clk_put() 238 devm_clk_put()
239 devm_clk_hw_register() 239 devm_clk_hw_register()
240 devm_of_clk_add_hw_provider()
240 241
241DMA 242DMA
242 dmam_alloc_coherent() 243 dmam_alloc_coherent()
diff --git a/MAINTAINERS b/MAINTAINERS
index bcab816b25f4..16137acd7f2f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11543,6 +11543,7 @@ F: include/linux/rpmsg/
11543RENESAS CLOCK DRIVERS 11543RENESAS CLOCK DRIVERS
11544M: Geert Uytterhoeven <geert+renesas@glider.be> 11544M: Geert Uytterhoeven <geert+renesas@glider.be>
11545L: linux-renesas-soc@vger.kernel.org 11545L: linux-renesas-soc@vger.kernel.org
11546T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git clk-renesas
11546S: Supported 11547S: Supported
11547F: drivers/clk/renesas/ 11548F: drivers/clk/renesas/
11548 11549
diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c
index aadabd9d1e2b..cd8d689138ff 100644
--- a/drivers/clk/at91/clk-utmi.c
+++ b/drivers/clk/at91/clk-utmi.c
@@ -14,14 +14,20 @@
14#include <linux/of.h> 14#include <linux/of.h>
15#include <linux/mfd/syscon.h> 15#include <linux/mfd/syscon.h>
16#include <linux/regmap.h> 16#include <linux/regmap.h>
17#include <soc/at91/atmel-sfr.h>
17 18
18#include "pmc.h" 19#include "pmc.h"
19 20
20#define UTMI_FIXED_MUL 40 21/*
22 * The purpose of this clock is to generate a 480 MHz signal. A different
23 * rate can't be configured.
24 */
25#define UTMI_RATE 480000000
21 26
22struct clk_utmi { 27struct clk_utmi {
23 struct clk_hw hw; 28 struct clk_hw hw;
24 struct regmap *regmap; 29 struct regmap *regmap_pmc;
30 struct regmap *regmap_sfr;
25}; 31};
26 32
27#define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw) 33#define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw)
@@ -37,13 +43,54 @@ static inline bool clk_utmi_ready(struct regmap *regmap)
37 43
38static int clk_utmi_prepare(struct clk_hw *hw) 44static int clk_utmi_prepare(struct clk_hw *hw)
39{ 45{
46 struct clk_hw *hw_parent;
40 struct clk_utmi *utmi = to_clk_utmi(hw); 47 struct clk_utmi *utmi = to_clk_utmi(hw);
41 unsigned int uckr = AT91_PMC_UPLLEN | AT91_PMC_UPLLCOUNT | 48 unsigned int uckr = AT91_PMC_UPLLEN | AT91_PMC_UPLLCOUNT |
42 AT91_PMC_BIASEN; 49 AT91_PMC_BIASEN;
50 unsigned int utmi_ref_clk_freq;
51 unsigned long parent_rate;
52
53 /*
54 * If mainck rate is different from 12 MHz, we have to configure the
55 * FREQ field of the SFR_UTMICKTRIM register to generate properly
56 * the utmi clock.
57 */
58 hw_parent = clk_hw_get_parent(hw);
59 parent_rate = clk_hw_get_rate(hw_parent);
60
61 switch (parent_rate) {
62 case 12000000:
63 utmi_ref_clk_freq = 0;
64 break;
65 case 16000000:
66 utmi_ref_clk_freq = 1;
67 break;
68 case 24000000:
69 utmi_ref_clk_freq = 2;
70 break;
71 /*
72 * Not supported on SAMA5D2 but it's not an issue since MAINCK
73 * maximum value is 24 MHz.
74 */
75 case 48000000:
76 utmi_ref_clk_freq = 3;
77 break;
78 default:
79 pr_err("UTMICK: unsupported mainck rate\n");
80 return -EINVAL;
81 }
43 82
44 regmap_update_bits(utmi->regmap, AT91_CKGR_UCKR, uckr, uckr); 83 if (utmi->regmap_sfr) {
84 regmap_update_bits(utmi->regmap_sfr, AT91_SFR_UTMICKTRIM,
85 AT91_UTMICKTRIM_FREQ, utmi_ref_clk_freq);
86 } else if (utmi_ref_clk_freq) {
87 pr_err("UTMICK: sfr node required\n");
88 return -EINVAL;
89 }
45 90
46 while (!clk_utmi_ready(utmi->regmap)) 91 regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, uckr, uckr);
92
93 while (!clk_utmi_ready(utmi->regmap_pmc))
47 cpu_relax(); 94 cpu_relax();
48 95
49 return 0; 96 return 0;
@@ -53,21 +100,22 @@ static int clk_utmi_is_prepared(struct clk_hw *hw)
53{ 100{
54 struct clk_utmi *utmi = to_clk_utmi(hw); 101 struct clk_utmi *utmi = to_clk_utmi(hw);
55 102
56 return clk_utmi_ready(utmi->regmap); 103 return clk_utmi_ready(utmi->regmap_pmc);
57} 104}
58 105
59static void clk_utmi_unprepare(struct clk_hw *hw) 106static void clk_utmi_unprepare(struct clk_hw *hw)
60{ 107{
61 struct clk_utmi *utmi = to_clk_utmi(hw); 108 struct clk_utmi *utmi = to_clk_utmi(hw);
62 109
63 regmap_update_bits(utmi->regmap, AT91_CKGR_UCKR, AT91_PMC_UPLLEN, 0); 110 regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR,
111 AT91_PMC_UPLLEN, 0);
64} 112}
65 113
66static unsigned long clk_utmi_recalc_rate(struct clk_hw *hw, 114static unsigned long clk_utmi_recalc_rate(struct clk_hw *hw,
67 unsigned long parent_rate) 115 unsigned long parent_rate)
68{ 116{
69 /* UTMI clk is a fixed clk multiplier */ 117 /* UTMI clk rate is fixed. */
70 return parent_rate * UTMI_FIXED_MUL; 118 return UTMI_RATE;
71} 119}
72 120
73static const struct clk_ops utmi_ops = { 121static const struct clk_ops utmi_ops = {
@@ -78,7 +126,7 @@ static const struct clk_ops utmi_ops = {
78}; 126};
79 127
80static struct clk_hw * __init 128static struct clk_hw * __init
81at91_clk_register_utmi(struct regmap *regmap, 129at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
82 const char *name, const char *parent_name) 130 const char *name, const char *parent_name)
83{ 131{
84 struct clk_utmi *utmi; 132 struct clk_utmi *utmi;
@@ -97,7 +145,8 @@ at91_clk_register_utmi(struct regmap *regmap,
97 init.flags = CLK_SET_RATE_GATE; 145 init.flags = CLK_SET_RATE_GATE;
98 146
99 utmi->hw.init = &init; 147 utmi->hw.init = &init;
100 utmi->regmap = regmap; 148 utmi->regmap_pmc = regmap_pmc;
149 utmi->regmap_sfr = regmap_sfr;
101 150
102 hw = &utmi->hw; 151 hw = &utmi->hw;
103 ret = clk_hw_register(NULL, &utmi->hw); 152 ret = clk_hw_register(NULL, &utmi->hw);
@@ -114,17 +163,35 @@ static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np)
114 struct clk_hw *hw; 163 struct clk_hw *hw;
115 const char *parent_name; 164 const char *parent_name;
116 const char *name = np->name; 165 const char *name = np->name;
117 struct regmap *regmap; 166 struct regmap *regmap_pmc, *regmap_sfr;
118 167
119 parent_name = of_clk_get_parent_name(np, 0); 168 parent_name = of_clk_get_parent_name(np, 0);
120 169
121 of_property_read_string(np, "clock-output-names", &name); 170 of_property_read_string(np, "clock-output-names", &name);
122 171
123 regmap = syscon_node_to_regmap(of_get_parent(np)); 172 regmap_pmc = syscon_node_to_regmap(of_get_parent(np));
124 if (IS_ERR(regmap)) 173 if (IS_ERR(regmap_pmc))
125 return; 174 return;
126 175
127 hw = at91_clk_register_utmi(regmap, name, parent_name); 176 /*
177 * If the device supports different mainck rates, this value has to be
178 * set in the UTMI Clock Trimming register.
179 * - 9x5: mainck supports several rates but it is indicated that a
180 * 12 MHz is needed in case of USB.
181 * - sama5d3 and sama5d2: mainck supports several rates. Configuring
182 * the FREQ field of the UTMI Clock Trimming register is mandatory.
183 * - sama5d4: mainck is at 12 MHz.
184 *
185 * We only need to retrieve sama5d3 or sama5d2 sfr regmap.
186 */
187 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d3-sfr");
188 if (IS_ERR(regmap_sfr)) {
189 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
190 if (IS_ERR(regmap_sfr))
191 regmap_sfr = NULL;
192 }
193
194 hw = at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, parent_name);
128 if (IS_ERR(hw)) 195 if (IS_ERR(hw))
129 return; 196 return;
130 197
diff --git a/drivers/clk/bcm/clk-kona-setup.c b/drivers/clk/bcm/clk-kona-setup.c
index c37a7f0e83aa..281f4322355c 100644
--- a/drivers/clk/bcm/clk-kona-setup.c
+++ b/drivers/clk/bcm/clk-kona-setup.c
@@ -579,18 +579,13 @@ static u32 *parent_process(const char *clocks[],
579 */ 579 */
580 parent_names = kmalloc_array(parent_count, sizeof(*parent_names), 580 parent_names = kmalloc_array(parent_count, sizeof(*parent_names),
581 GFP_KERNEL); 581 GFP_KERNEL);
582 if (!parent_names) { 582 if (!parent_names)
583 pr_err("%s: error allocating %u parent names\n", __func__,
584 parent_count);
585 return ERR_PTR(-ENOMEM); 583 return ERR_PTR(-ENOMEM);
586 }
587 584
588 /* There is at least one parent, so allocate a selector array */ 585 /* There is at least one parent, so allocate a selector array */
589 parent_sel = kmalloc_array(parent_count, sizeof(*parent_sel), 586 parent_sel = kmalloc_array(parent_count, sizeof(*parent_sel),
590 GFP_KERNEL); 587 GFP_KERNEL);
591 if (!parent_sel) { 588 if (!parent_sel) {
592 pr_err("%s: error allocating %u parent selectors\n", __func__,
593 parent_count);
594 kfree(parent_names); 589 kfree(parent_names);
595 590
596 return ERR_PTR(-ENOMEM); 591 return ERR_PTR(-ENOMEM);
diff --git a/drivers/clk/clk-cdce925.c b/drivers/clk/clk-cdce925.c
index c933be01c7db..0a7e7d5a7506 100644
--- a/drivers/clk/clk-cdce925.c
+++ b/drivers/clk/clk-cdce925.c
@@ -665,7 +665,7 @@ static int cdce925_probe(struct i2c_client *client,
665 init.ops = &cdce925_pll_ops; 665 init.ops = &cdce925_pll_ops;
666 init.flags = 0; 666 init.flags = 0;
667 init.parent_names = &parent_name; 667 init.parent_names = &parent_name;
668 init.num_parents = parent_name ? 1 : 0; 668 init.num_parents = 1;
669 669
670 /* Register PLL clocks */ 670 /* Register PLL clocks */
671 for (i = 0; i < data->chip_info->num_plls; ++i) { 671 for (i = 0; i < data->chip_info->num_plls; ++i) {
diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c
index 86b245746a6b..151513c655c3 100644
--- a/drivers/clk/clk-gpio.c
+++ b/drivers/clk/clk-gpio.c
@@ -15,9 +15,7 @@
15#include <linux/clk-provider.h> 15#include <linux/clk-provider.h>
16#include <linux/export.h> 16#include <linux/export.h>
17#include <linux/slab.h> 17#include <linux/slab.h>
18#include <linux/gpio.h>
19#include <linux/gpio/consumer.h> 18#include <linux/gpio/consumer.h>
20#include <linux/of_gpio.h>
21#include <linux/err.h> 19#include <linux/err.h>
22#include <linux/device.h> 20#include <linux/device.h>
23#include <linux/platform_device.h> 21#include <linux/platform_device.h>
@@ -95,14 +93,12 @@ const struct clk_ops clk_gpio_mux_ops = {
95EXPORT_SYMBOL_GPL(clk_gpio_mux_ops); 93EXPORT_SYMBOL_GPL(clk_gpio_mux_ops);
96 94
97static struct clk_hw *clk_register_gpio(struct device *dev, const char *name, 95static struct clk_hw *clk_register_gpio(struct device *dev, const char *name,
98 const char * const *parent_names, u8 num_parents, unsigned gpio, 96 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
99 bool active_low, unsigned long flags, 97 unsigned long flags, const struct clk_ops *clk_gpio_ops)
100 const struct clk_ops *clk_gpio_ops)
101{ 98{
102 struct clk_gpio *clk_gpio; 99 struct clk_gpio *clk_gpio;
103 struct clk_hw *hw; 100 struct clk_hw *hw;
104 struct clk_init_data init = {}; 101 struct clk_init_data init = {};
105 unsigned long gpio_flags;
106 int err; 102 int err;
107 103
108 if (dev) 104 if (dev)
@@ -113,32 +109,13 @@ static struct clk_hw *clk_register_gpio(struct device *dev, const char *name,
113 if (!clk_gpio) 109 if (!clk_gpio)
114 return ERR_PTR(-ENOMEM); 110 return ERR_PTR(-ENOMEM);
115 111
116 if (active_low)
117 gpio_flags = GPIOF_ACTIVE_LOW | GPIOF_OUT_INIT_HIGH;
118 else
119 gpio_flags = GPIOF_OUT_INIT_LOW;
120
121 if (dev)
122 err = devm_gpio_request_one(dev, gpio, gpio_flags, name);
123 else
124 err = gpio_request_one(gpio, gpio_flags, name);
125 if (err) {
126 if (err != -EPROBE_DEFER)
127 pr_err("%s: %s: Error requesting clock control gpio %u\n",
128 __func__, name, gpio);
129 if (!dev)
130 kfree(clk_gpio);
131
132 return ERR_PTR(err);
133 }
134
135 init.name = name; 112 init.name = name;
136 init.ops = clk_gpio_ops; 113 init.ops = clk_gpio_ops;
137 init.flags = flags | CLK_IS_BASIC; 114 init.flags = flags | CLK_IS_BASIC;
138 init.parent_names = parent_names; 115 init.parent_names = parent_names;
139 init.num_parents = num_parents; 116 init.num_parents = num_parents;
140 117
141 clk_gpio->gpiod = gpio_to_desc(gpio); 118 clk_gpio->gpiod = gpiod;
142 clk_gpio->hw.init = &init; 119 clk_gpio->hw.init = &init;
143 120
144 hw = &clk_gpio->hw; 121 hw = &clk_gpio->hw;
@@ -151,7 +128,6 @@ static struct clk_hw *clk_register_gpio(struct device *dev, const char *name,
151 return hw; 128 return hw;
152 129
153 if (!dev) { 130 if (!dev) {
154 gpiod_put(clk_gpio->gpiod);
155 kfree(clk_gpio); 131 kfree(clk_gpio);
156 } 132 }
157 133
@@ -164,29 +140,27 @@ static struct clk_hw *clk_register_gpio(struct device *dev, const char *name,
164 * @dev: device that is registering this clock 140 * @dev: device that is registering this clock
165 * @name: name of this clock 141 * @name: name of this clock
166 * @parent_name: name of this clock's parent 142 * @parent_name: name of this clock's parent
167 * @gpio: gpio number to gate this clock 143 * @gpiod: gpio descriptor to gate this clock
168 * @active_low: true if gpio should be set to 0 to enable clock
169 * @flags: clock flags 144 * @flags: clock flags
170 */ 145 */
171struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name, 146struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name,
172 const char *parent_name, unsigned gpio, bool active_low, 147 const char *parent_name, struct gpio_desc *gpiod,
173 unsigned long flags) 148 unsigned long flags)
174{ 149{
175 return clk_register_gpio(dev, name, 150 return clk_register_gpio(dev, name,
176 (parent_name ? &parent_name : NULL), 151 (parent_name ? &parent_name : NULL),
177 (parent_name ? 1 : 0), gpio, active_low, flags, 152 (parent_name ? 1 : 0), gpiod, flags,
178 &clk_gpio_gate_ops); 153 &clk_gpio_gate_ops);
179} 154}
180EXPORT_SYMBOL_GPL(clk_hw_register_gpio_gate); 155EXPORT_SYMBOL_GPL(clk_hw_register_gpio_gate);
181 156
182struct clk *clk_register_gpio_gate(struct device *dev, const char *name, 157struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
183 const char *parent_name, unsigned gpio, bool active_low, 158 const char *parent_name, struct gpio_desc *gpiod,
184 unsigned long flags) 159 unsigned long flags)
185{ 160{
186 struct clk_hw *hw; 161 struct clk_hw *hw;
187 162
188 hw = clk_hw_register_gpio_gate(dev, name, parent_name, gpio, active_low, 163 hw = clk_hw_register_gpio_gate(dev, name, parent_name, gpiod, flags);
189 flags);
190 if (IS_ERR(hw)) 164 if (IS_ERR(hw))
191 return ERR_CAST(hw); 165 return ERR_CAST(hw);
192 return hw->clk; 166 return hw->clk;
@@ -199,13 +173,12 @@ EXPORT_SYMBOL_GPL(clk_register_gpio_gate);
199 * @name: name of this clock 173 * @name: name of this clock
200 * @parent_names: names of this clock's parents 174 * @parent_names: names of this clock's parents
201 * @num_parents: number of parents listed in @parent_names 175 * @num_parents: number of parents listed in @parent_names
202 * @gpio: gpio number to gate this clock 176 * @gpiod: gpio descriptor to gate this clock
203 * @active_low: true if gpio should be set to 0 to enable clock
204 * @flags: clock flags 177 * @flags: clock flags
205 */ 178 */
206struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name, 179struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name,
207 const char * const *parent_names, u8 num_parents, unsigned gpio, 180 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
208 bool active_low, unsigned long flags) 181 unsigned long flags)
209{ 182{
210 if (num_parents != 2) { 183 if (num_parents != 2) {
211 pr_err("mux-clock %s must have 2 parents\n", name); 184 pr_err("mux-clock %s must have 2 parents\n", name);
@@ -213,18 +186,18 @@ struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name,
213 } 186 }
214 187
215 return clk_register_gpio(dev, name, parent_names, num_parents, 188 return clk_register_gpio(dev, name, parent_names, num_parents,
216 gpio, active_low, flags, &clk_gpio_mux_ops); 189 gpiod, flags, &clk_gpio_mux_ops);
217} 190}
218EXPORT_SYMBOL_GPL(clk_hw_register_gpio_mux); 191EXPORT_SYMBOL_GPL(clk_hw_register_gpio_mux);
219 192
220struct clk *clk_register_gpio_mux(struct device *dev, const char *name, 193struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
221 const char * const *parent_names, u8 num_parents, unsigned gpio, 194 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
222 bool active_low, unsigned long flags) 195 unsigned long flags)
223{ 196{
224 struct clk_hw *hw; 197 struct clk_hw *hw;
225 198
226 hw = clk_hw_register_gpio_mux(dev, name, parent_names, num_parents, 199 hw = clk_hw_register_gpio_mux(dev, name, parent_names, num_parents,
227 gpio, active_low, flags); 200 gpiod, flags);
228 if (IS_ERR(hw)) 201 if (IS_ERR(hw))
229 return ERR_CAST(hw); 202 return ERR_CAST(hw);
230 return hw->clk; 203 return hw->clk;
@@ -236,10 +209,10 @@ static int gpio_clk_driver_probe(struct platform_device *pdev)
236 struct device_node *node = pdev->dev.of_node; 209 struct device_node *node = pdev->dev.of_node;
237 const char **parent_names, *gpio_name; 210 const char **parent_names, *gpio_name;
238 unsigned int num_parents; 211 unsigned int num_parents;
239 int gpio; 212 struct gpio_desc *gpiod;
240 enum of_gpio_flags of_flags;
241 struct clk *clk; 213 struct clk *clk;
242 bool active_low, is_mux; 214 bool is_mux;
215 int ret;
243 216
244 num_parents = of_clk_get_parent_count(node); 217 num_parents = of_clk_get_parent_count(node);
245 if (num_parents) { 218 if (num_parents) {
@@ -255,28 +228,27 @@ static int gpio_clk_driver_probe(struct platform_device *pdev)
255 228
256 is_mux = of_device_is_compatible(node, "gpio-mux-clock"); 229 is_mux = of_device_is_compatible(node, "gpio-mux-clock");
257 230
258 gpio_name = is_mux ? "select-gpios" : "enable-gpios"; 231 gpio_name = is_mux ? "select" : "enable";
259 gpio = of_get_named_gpio_flags(node, gpio_name, 0, &of_flags); 232 gpiod = devm_gpiod_get(&pdev->dev, gpio_name, GPIOD_OUT_LOW);
260 if (gpio < 0) { 233 if (IS_ERR(gpiod)) {
261 if (gpio == -EPROBE_DEFER) 234 ret = PTR_ERR(gpiod);
235 if (ret == -EPROBE_DEFER)
262 pr_debug("%s: %s: GPIOs not yet available, retry later\n", 236 pr_debug("%s: %s: GPIOs not yet available, retry later\n",
263 node->name, __func__); 237 node->name, __func__);
264 else 238 else
265 pr_err("%s: %s: Can't get '%s' DT property\n", 239 pr_err("%s: %s: Can't get '%s' named GPIO property\n",
266 node->name, __func__, 240 node->name, __func__,
267 gpio_name); 241 gpio_name);
268 return gpio; 242 return ret;
269 } 243 }
270 244
271 active_low = of_flags & OF_GPIO_ACTIVE_LOW;
272
273 if (is_mux) 245 if (is_mux)
274 clk = clk_register_gpio_mux(&pdev->dev, node->name, 246 clk = clk_register_gpio_mux(&pdev->dev, node->name,
275 parent_names, num_parents, gpio, active_low, 0); 247 parent_names, num_parents, gpiod, 0);
276 else 248 else
277 clk = clk_register_gpio_gate(&pdev->dev, node->name, 249 clk = clk_register_gpio_gate(&pdev->dev, node->name,
278 parent_names ? parent_names[0] : NULL, gpio, 250 parent_names ? parent_names[0] : NULL, gpiod,
279 active_low, 0); 251 0);
280 if (IS_ERR(clk)) 252 if (IS_ERR(clk))
281 return PTR_ERR(clk); 253 return PTR_ERR(clk);
282 254
diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
index bbf237173b37..c4ee280f454d 100644
--- a/drivers/clk/clk-hsdk-pll.c
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -139,7 +139,7 @@ static inline void hsdk_pll_set_cfg(struct hsdk_pll_clk *clk,
139 val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT; 139 val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
140 val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT; 140 val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
141 141
142 dev_dbg(clk->dev, "write configurarion: %#x\n", val); 142 dev_dbg(clk->dev, "write configuration: %#x\n", val);
143 143
144 hsdk_pll_write(clk, CGU_PLL_CTRL, val); 144 hsdk_pll_write(clk, CGU_PLL_CTRL, val);
145} 145}
@@ -169,7 +169,7 @@ static unsigned long hsdk_pll_recalc_rate(struct clk_hw *hw,
169 169
170 val = hsdk_pll_read(clk, CGU_PLL_CTRL); 170 val = hsdk_pll_read(clk, CGU_PLL_CTRL);
171 171
172 dev_dbg(clk->dev, "current configurarion: %#x\n", val); 172 dev_dbg(clk->dev, "current configuration: %#x\n", val);
173 173
174 /* Check if PLL is disabled */ 174 /* Check if PLL is disabled */
175 if (val & CGU_PLL_CTRL_PD) 175 if (val & CGU_PLL_CTRL_PD)
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 16a3d5717f4e..39cabe157163 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -134,11 +134,9 @@ struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
134 } 134 }
135 135
136 /* allocate the mux */ 136 /* allocate the mux */
137 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); 137 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
138 if (!mux) { 138 if (!mux)
139 pr_err("%s: could not allocate mux clk\n", __func__);
140 return ERR_PTR(-ENOMEM); 139 return ERR_PTR(-ENOMEM);
141 }
142 140
143 init.name = name; 141 init.name = name;
144 if (clk_mux_flags & CLK_MUX_READ_ONLY) 142 if (clk_mux_flags & CLK_MUX_READ_ONLY)
diff --git a/drivers/clk/clk-stm32h7.c b/drivers/clk/clk-stm32h7.c
index a94c3f56c590..61c3e40507d3 100644
--- a/drivers/clk/clk-stm32h7.c
+++ b/drivers/clk/clk-stm32h7.c
@@ -384,7 +384,7 @@ static void get_cfg_composite_div(const struct composite_clk_gcfg *gcfg,
384 mux_ops = div_ops = gate_ops = NULL; 384 mux_ops = div_ops = gate_ops = NULL;
385 mux_hw = div_hw = gate_hw = NULL; 385 mux_hw = div_hw = gate_hw = NULL;
386 386
387 if (gcfg->mux && gcfg->mux) { 387 if (gcfg->mux && cfg->mux) {
388 mux = _get_cmux(base + cfg->mux->offset, 388 mux = _get_cmux(base + cfg->mux->offset,
389 cfg->mux->shift, 389 cfg->mux->shift,
390 cfg->mux->width, 390 cfg->mux->width,
@@ -410,7 +410,7 @@ static void get_cfg_composite_div(const struct composite_clk_gcfg *gcfg,
410 } 410 }
411 } 411 }
412 412
413 if (gcfg->gate && gcfg->gate) { 413 if (gcfg->gate && cfg->gate) {
414 gate = _get_cgate(base + cfg->gate->offset, 414 gate = _get_cgate(base + cfg->gate->offset,
415 cfg->gate->bit_idx, 415 cfg->gate->bit_idx,
416 gcfg->gate->flags, lock); 416 gcfg->gate->flags, lock);
diff --git a/drivers/clk/clk-twl6040.c b/drivers/clk/clk-twl6040.c
index 7b222a5db931..25dfe050ae9f 100644
--- a/drivers/clk/clk-twl6040.c
+++ b/drivers/clk/clk-twl6040.c
@@ -82,7 +82,7 @@ static const struct clk_ops twl6040_pdmclk_ops = {
82 .recalc_rate = twl6040_pdmclk_recalc_rate, 82 .recalc_rate = twl6040_pdmclk_recalc_rate,
83}; 83};
84 84
85static struct clk_init_data twl6040_pdmclk_init = { 85static const struct clk_init_data twl6040_pdmclk_init = {
86 .name = "pdmclk", 86 .name = "pdmclk",
87 .ops = &twl6040_pdmclk_ops, 87 .ops = &twl6040_pdmclk_ops,
88 .flags = CLK_GET_RATE_NOCACHE, 88 .flags = CLK_GET_RATE_NOCACHE,
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index ec8aafda6e24..7b3e1921771f 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -229,15 +229,15 @@
229#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0) 229#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0)
230#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E) 230#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E)
231#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001) 231#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001)
232#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1) 232#define U300_SYSCON_S0CCR_SEL_MCLK (0x8 << 1)
233#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1) 233#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA << 1)
234#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1) 234#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC << 1)
235#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1) 235#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD << 1)
236#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1) 236#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE << 1)
237#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1) 237#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0 << 1)
238#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1) 238#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2 << 1)
239#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1) 239#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4 << 1)
240#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1) 240#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6 << 1)
241/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */ 241/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
242#define U300_SYSCON_S1CCR (0x124) 242#define U300_SYSCON_S1CCR (0x124)
243#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF) 243#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF)
@@ -247,16 +247,16 @@
247#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0) 247#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0)
248#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E) 248#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E)
249#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001) 249#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001)
250#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1) 250#define U300_SYSCON_S1CCR_SEL_MCLK (0x8 << 1)
251#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1) 251#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA << 1)
252#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1) 252#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC << 1)
253#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1) 253#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD << 1)
254#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1) 254#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE << 1)
255#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1) 255#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0 << 1)
256#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1) 256#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2 << 1)
257#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1) 257#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4 << 1)
258#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1) 258#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6 << 1)
259/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */ 259/* SYS_2_CLK_CONTROL third clock control 16 bit (R/W) */
260#define U300_SYSCON_S2CCR (0x128) 260#define U300_SYSCON_S2CCR (0x128)
261#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF) 261#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF)
262#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000) 262#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000)
@@ -266,15 +266,15 @@
266#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0) 266#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0)
267#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E) 267#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E)
268#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001) 268#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001)
269#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1) 269#define U300_SYSCON_S2CCR_SEL_MCLK (0x8 << 1)
270#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1) 270#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA << 1)
271#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1) 271#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC << 1)
272#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1) 272#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD << 1)
273#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1) 273#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE << 1)
274#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1) 274#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0 << 1)
275#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1) 275#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2 << 1)
276#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1) 276#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4 << 1)
277#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1) 277#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6 << 1)
278/* SC_PLL_IRQ_CONTROL 16bit (R/W) */ 278/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
279#define U300_SYSCON_PICR (0x0130) 279#define U300_SYSCON_PICR (0x0130)
280#define U300_SYSCON_PICR_MASK (0x00FF) 280#define U300_SYSCON_PICR_MASK (0x00FF)
@@ -378,7 +378,7 @@
378 * +- ISP Image Signal Processor (U335 only) 378 * +- ISP Image Signal Processor (U335 only)
379 * +- CDS (U335 only) 379 * +- CDS (U335 only)
380 * +- DMA Direct Memory Access Controller 380 * +- DMA Direct Memory Access Controller
381 * +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL) 381 * +- AAIF APP/ACC Interface (Mobile Scalable Link, MSL)
382 * +- APEX 382 * +- APEX
383 * +- VIDEO_ENC AVE2/3 Video Encoder 383 * +- VIDEO_ENC AVE2/3 Video Encoder
384 * +- XGAM Graphics Accelerator Controller 384 * +- XGAM Graphics Accelerator Controller
@@ -568,14 +568,14 @@ syscon_clk_recalc_rate(struct clk_hw *hw,
568 struct clk_syscon *sclk = to_syscon(hw); 568 struct clk_syscon *sclk = to_syscon(hw);
569 u16 perf = syscon_get_perf(); 569 u16 perf = syscon_get_perf();
570 570
571 switch(sclk->clk_val) { 571 switch (sclk->clk_val) {
572 case U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN: 572 case U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN:
573 case U300_SYSCON_SBCER_I2C0_CLK_EN: 573 case U300_SYSCON_SBCER_I2C0_CLK_EN:
574 case U300_SYSCON_SBCER_I2C1_CLK_EN: 574 case U300_SYSCON_SBCER_I2C1_CLK_EN:
575 case U300_SYSCON_SBCER_MMC_CLK_EN: 575 case U300_SYSCON_SBCER_MMC_CLK_EN:
576 case U300_SYSCON_SBCER_SPI_CLK_EN: 576 case U300_SYSCON_SBCER_SPI_CLK_EN:
577 /* The FAST clocks have one progression */ 577 /* The FAST clocks have one progression */
578 switch(perf) { 578 switch (perf) {
579 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: 579 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
580 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: 580 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
581 return 13000000; 581 return 13000000;
@@ -586,7 +586,7 @@ syscon_clk_recalc_rate(struct clk_hw *hw,
586 case U300_SYSCON_SBCER_NANDIF_CLK_EN: 586 case U300_SYSCON_SBCER_NANDIF_CLK_EN:
587 case U300_SYSCON_SBCER_XGAM_CLK_EN: 587 case U300_SYSCON_SBCER_XGAM_CLK_EN:
588 /* AMBA interconnect peripherals */ 588 /* AMBA interconnect peripherals */
589 switch(perf) { 589 switch (perf) {
590 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: 590 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
591 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: 591 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
592 return 6500000; 592 return 6500000;
@@ -598,7 +598,7 @@ syscon_clk_recalc_rate(struct clk_hw *hw,
598 case U300_SYSCON_SBCER_SEMI_CLK_EN: 598 case U300_SYSCON_SBCER_SEMI_CLK_EN:
599 case U300_SYSCON_SBCER_EMIF_CLK_EN: 599 case U300_SYSCON_SBCER_EMIF_CLK_EN:
600 /* EMIF speeds */ 600 /* EMIF speeds */
601 switch(perf) { 601 switch (perf) {
602 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: 602 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
603 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: 603 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
604 return 13000000; 604 return 13000000;
@@ -609,7 +609,7 @@ syscon_clk_recalc_rate(struct clk_hw *hw,
609 } 609 }
610 case U300_SYSCON_SBCER_CPU_CLK_EN: 610 case U300_SYSCON_SBCER_CPU_CLK_EN:
611 /* And the fast CPU clock */ 611 /* And the fast CPU clock */
612 switch(perf) { 612 switch (perf) {
613 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER: 613 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
614 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW: 614 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
615 return 13000000; 615 return 13000000;
@@ -702,12 +702,10 @@ syscon_clk_register(struct device *dev, const char *name,
702 struct clk_init_data init; 702 struct clk_init_data init;
703 int ret; 703 int ret;
704 704
705 sclk = kzalloc(sizeof(struct clk_syscon), GFP_KERNEL); 705 sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
706 if (!sclk) { 706 if (!sclk)
707 pr_err("could not allocate syscon clock %s\n",
708 name);
709 return ERR_PTR(-ENOMEM); 707 return ERR_PTR(-ENOMEM);
710 } 708
711 init.name = name; 709 init.name = name;
712 init.ops = &syscon_clk_ops; 710 init.ops = &syscon_clk_ops;
713 init.flags = flags; 711 init.flags = flags;
@@ -1123,12 +1121,10 @@ mclk_clk_register(struct device *dev, const char *name,
1123 struct clk_init_data init; 1121 struct clk_init_data init;
1124 int ret; 1122 int ret;
1125 1123
1126 mclk = kzalloc(sizeof(struct clk_mclk), GFP_KERNEL); 1124 mclk = kzalloc(sizeof(*mclk), GFP_KERNEL);
1127 if (!mclk) { 1125 if (!mclk)
1128 pr_err("could not allocate MMC/SD clock %s\n",
1129 name);
1130 return ERR_PTR(-ENOMEM); 1126 return ERR_PTR(-ENOMEM);
1131 } 1127
1132 init.name = "mclk"; 1128 init.name = "mclk";
1133 init.ops = &mclk_ops; 1129 init.ops = &mclk_ops;
1134 init.flags = 0; 1130 init.flags = 0;
diff --git a/drivers/clk/clk-wm831x.c b/drivers/clk/clk-wm831x.c
index a47960aacfa5..146769532325 100644
--- a/drivers/clk/clk-wm831x.c
+++ b/drivers/clk/clk-wm831x.c
@@ -52,7 +52,7 @@ static const struct clk_ops wm831x_xtal_ops = {
52 .recalc_rate = wm831x_xtal_recalc_rate, 52 .recalc_rate = wm831x_xtal_recalc_rate,
53}; 53};
54 54
55static struct clk_init_data wm831x_xtal_init = { 55static const struct clk_init_data wm831x_xtal_init = {
56 .name = "xtal", 56 .name = "xtal",
57 .ops = &wm831x_xtal_ops, 57 .ops = &wm831x_xtal_ops,
58}; 58};
@@ -225,7 +225,7 @@ static const struct clk_ops wm831x_fll_ops = {
225 .get_parent = wm831x_fll_get_parent, 225 .get_parent = wm831x_fll_get_parent,
226}; 226};
227 227
228static struct clk_init_data wm831x_fll_init = { 228static const struct clk_init_data wm831x_fll_init = {
229 .name = "fll", 229 .name = "fll",
230 .ops = &wm831x_fll_ops, 230 .ops = &wm831x_fll_ops,
231 .parent_names = wm831x_fll_parents, 231 .parent_names = wm831x_fll_parents,
@@ -338,7 +338,7 @@ static const struct clk_ops wm831x_clkout_ops = {
338 .set_parent = wm831x_clkout_set_parent, 338 .set_parent = wm831x_clkout_set_parent,
339}; 339};
340 340
341static struct clk_init_data wm831x_clkout_init = { 341static const struct clk_init_data wm831x_clkout_init = {
342 .name = "clkout", 342 .name = "clkout",
343 .ops = &wm831x_clkout_ops, 343 .ops = &wm831x_clkout_ops,
344 .parent_names = wm831x_clkout_parents, 344 .parent_names = wm831x_clkout_parents,
diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c
index 4c75821a3933..531b030d4d4e 100644
--- a/drivers/clk/clk-xgene.c
+++ b/drivers/clk/clk-xgene.c
@@ -146,10 +146,8 @@ static struct clk *xgene_register_clk_pll(struct device *dev,
146 146
147 /* allocate the APM clock structure */ 147 /* allocate the APM clock structure */
148 apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL); 148 apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL);
149 if (!apmclk) { 149 if (!apmclk)
150 pr_err("%s: could not allocate APM clk\n", __func__);
151 return ERR_PTR(-ENOMEM); 150 return ERR_PTR(-ENOMEM);
152 }
153 151
154 init.name = name; 152 init.name = name;
155 init.ops = &xgene_clk_pll_ops; 153 init.ops = &xgene_clk_pll_ops;
@@ -191,7 +189,7 @@ static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_ty
191 int version = xgene_pllclk_version(np); 189 int version = xgene_pllclk_version(np);
192 190
193 reg = of_iomap(np, 0); 191 reg = of_iomap(np, 0);
194 if (reg == NULL) { 192 if (!reg) {
195 pr_err("Unable to map CSR register for %pOF\n", np); 193 pr_err("Unable to map CSR register for %pOF\n", np);
196 return; 194 return;
197 } 195 }
@@ -467,7 +465,7 @@ static int xgene_clk_enable(struct clk_hw *hw)
467 if (pclk->lock) 465 if (pclk->lock)
468 spin_lock_irqsave(pclk->lock, flags); 466 spin_lock_irqsave(pclk->lock, flags);
469 467
470 if (pclk->param.csr_reg != NULL) { 468 if (pclk->param.csr_reg) {
471 pr_debug("%s clock enabled\n", clk_hw_get_name(hw)); 469 pr_debug("%s clock enabled\n", clk_hw_get_name(hw));
472 /* First enable the clock */ 470 /* First enable the clock */
473 data = xgene_clk_read(pclk->param.csr_reg + 471 data = xgene_clk_read(pclk->param.csr_reg +
@@ -507,7 +505,7 @@ static void xgene_clk_disable(struct clk_hw *hw)
507 if (pclk->lock) 505 if (pclk->lock)
508 spin_lock_irqsave(pclk->lock, flags); 506 spin_lock_irqsave(pclk->lock, flags);
509 507
510 if (pclk->param.csr_reg != NULL) { 508 if (pclk->param.csr_reg) {
511 pr_debug("%s clock disabled\n", clk_hw_get_name(hw)); 509 pr_debug("%s clock disabled\n", clk_hw_get_name(hw));
512 /* First put the CSR in reset */ 510 /* First put the CSR in reset */
513 data = xgene_clk_read(pclk->param.csr_reg + 511 data = xgene_clk_read(pclk->param.csr_reg +
@@ -533,7 +531,7 @@ static int xgene_clk_is_enabled(struct clk_hw *hw)
533 struct xgene_clk *pclk = to_xgene_clk(hw); 531 struct xgene_clk *pclk = to_xgene_clk(hw);
534 u32 data = 0; 532 u32 data = 0;
535 533
536 if (pclk->param.csr_reg != NULL) { 534 if (pclk->param.csr_reg) {
537 pr_debug("%s clock checking\n", clk_hw_get_name(hw)); 535 pr_debug("%s clock checking\n", clk_hw_get_name(hw));
538 data = xgene_clk_read(pclk->param.csr_reg + 536 data = xgene_clk_read(pclk->param.csr_reg +
539 pclk->param.reg_clk_offset); 537 pclk->param.reg_clk_offset);
@@ -542,7 +540,7 @@ static int xgene_clk_is_enabled(struct clk_hw *hw)
542 "disabled"); 540 "disabled");
543 } 541 }
544 542
545 if (pclk->param.csr_reg == NULL) 543 if (!pclk->param.csr_reg)
546 return 1; 544 return 1;
547 return data & pclk->param.reg_clk_mask ? 1 : 0; 545 return data & pclk->param.reg_clk_mask ? 1 : 0;
548} 546}
@@ -650,10 +648,8 @@ static struct clk *xgene_register_clk(struct device *dev,
650 648
651 /* allocate the APM clock structure */ 649 /* allocate the APM clock structure */
652 apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL); 650 apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL);
653 if (!apmclk) { 651 if (!apmclk)
654 pr_err("%s: could not allocate APM clk\n", __func__);
655 return ERR_PTR(-ENOMEM); 652 return ERR_PTR(-ENOMEM);
656 }
657 653
658 init.name = name; 654 init.name = name;
659 init.ops = &xgene_clk_ops; 655 init.ops = &xgene_clk_ops;
@@ -709,7 +705,7 @@ static void __init xgene_devclk_init(struct device_node *np)
709 break; 705 break;
710 } 706 }
711 map_res = of_iomap(np, i); 707 map_res = of_iomap(np, i);
712 if (map_res == NULL) { 708 if (!map_res) {
713 pr_err("Unable to map resource %d for %pOF\n", i, np); 709 pr_err("Unable to map resource %d for %pOF\n", i, np);
714 goto err; 710 goto err;
715 } 711 }
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index c8d83acda006..647d056df88c 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -21,6 +21,7 @@
21#include <linux/of.h> 21#include <linux/of.h>
22#include <linux/device.h> 22#include <linux/device.h>
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/pm_runtime.h>
24#include <linux/sched.h> 25#include <linux/sched.h>
25#include <linux/clkdev.h> 26#include <linux/clkdev.h>
26 27
@@ -46,6 +47,7 @@ struct clk_core {
46 const struct clk_ops *ops; 47 const struct clk_ops *ops;
47 struct clk_hw *hw; 48 struct clk_hw *hw;
48 struct module *owner; 49 struct module *owner;
50 struct device *dev;
49 struct clk_core *parent; 51 struct clk_core *parent;
50 const char **parent_names; 52 const char **parent_names;
51 struct clk_core **parents; 53 struct clk_core **parents;
@@ -87,6 +89,26 @@ struct clk {
87 struct hlist_node clks_node; 89 struct hlist_node clks_node;
88}; 90};
89 91
92/*** runtime pm ***/
93static int clk_pm_runtime_get(struct clk_core *core)
94{
95 int ret = 0;
96
97 if (!core->dev)
98 return 0;
99
100 ret = pm_runtime_get_sync(core->dev);
101 return ret < 0 ? ret : 0;
102}
103
104static void clk_pm_runtime_put(struct clk_core *core)
105{
106 if (!core->dev)
107 return;
108
109 pm_runtime_put_sync(core->dev);
110}
111
90/*** locking ***/ 112/*** locking ***/
91static void clk_prepare_lock(void) 113static void clk_prepare_lock(void)
92{ 114{
@@ -150,6 +172,8 @@ static void clk_enable_unlock(unsigned long flags)
150 172
151static bool clk_core_is_prepared(struct clk_core *core) 173static bool clk_core_is_prepared(struct clk_core *core)
152{ 174{
175 bool ret = false;
176
153 /* 177 /*
154 * .is_prepared is optional for clocks that can prepare 178 * .is_prepared is optional for clocks that can prepare
155 * fall back to software usage counter if it is missing 179 * fall back to software usage counter if it is missing
@@ -157,11 +181,18 @@ static bool clk_core_is_prepared(struct clk_core *core)
157 if (!core->ops->is_prepared) 181 if (!core->ops->is_prepared)
158 return core->prepare_count; 182 return core->prepare_count;
159 183
160 return core->ops->is_prepared(core->hw); 184 if (!clk_pm_runtime_get(core)) {
185 ret = core->ops->is_prepared(core->hw);
186 clk_pm_runtime_put(core);
187 }
188
189 return ret;
161} 190}
162 191
163static bool clk_core_is_enabled(struct clk_core *core) 192static bool clk_core_is_enabled(struct clk_core *core)
164{ 193{
194 bool ret = false;
195
165 /* 196 /*
166 * .is_enabled is only mandatory for clocks that gate 197 * .is_enabled is only mandatory for clocks that gate
167 * fall back to software usage counter if .is_enabled is missing 198 * fall back to software usage counter if .is_enabled is missing
@@ -169,7 +200,29 @@ static bool clk_core_is_enabled(struct clk_core *core)
169 if (!core->ops->is_enabled) 200 if (!core->ops->is_enabled)
170 return core->enable_count; 201 return core->enable_count;
171 202
172 return core->ops->is_enabled(core->hw); 203 /*
204 * Check if clock controller's device is runtime active before
205 * calling .is_enabled callback. If not, assume that clock is
206 * disabled, because we might be called from atomic context, from
207 * which pm_runtime_get() is not allowed.
208 * This function is called mainly from clk_disable_unused_subtree,
209 * which ensures proper runtime pm activation of controller before
210 * taking enable spinlock, but the below check is needed if one tries
211 * to call it from other places.
212 */
213 if (core->dev) {
214 pm_runtime_get_noresume(core->dev);
215 if (!pm_runtime_active(core->dev)) {
216 ret = false;
217 goto done;
218 }
219 }
220
221 ret = core->ops->is_enabled(core->hw);
222done:
223 clk_pm_runtime_put(core);
224
225 return ret;
173} 226}
174 227
175/*** helper functions ***/ 228/*** helper functions ***/
@@ -489,6 +542,8 @@ static void clk_core_unprepare(struct clk_core *core)
489 if (core->ops->unprepare) 542 if (core->ops->unprepare)
490 core->ops->unprepare(core->hw); 543 core->ops->unprepare(core->hw);
491 544
545 clk_pm_runtime_put(core);
546
492 trace_clk_unprepare_complete(core); 547 trace_clk_unprepare_complete(core);
493 clk_core_unprepare(core->parent); 548 clk_core_unprepare(core->parent);
494} 549}
@@ -530,10 +585,14 @@ static int clk_core_prepare(struct clk_core *core)
530 return 0; 585 return 0;
531 586
532 if (core->prepare_count == 0) { 587 if (core->prepare_count == 0) {
533 ret = clk_core_prepare(core->parent); 588 ret = clk_pm_runtime_get(core);
534 if (ret) 589 if (ret)
535 return ret; 590 return ret;
536 591
592 ret = clk_core_prepare(core->parent);
593 if (ret)
594 goto runtime_put;
595
537 trace_clk_prepare(core); 596 trace_clk_prepare(core);
538 597
539 if (core->ops->prepare) 598 if (core->ops->prepare)
@@ -541,15 +600,18 @@ static int clk_core_prepare(struct clk_core *core)
541 600
542 trace_clk_prepare_complete(core); 601 trace_clk_prepare_complete(core);
543 602
544 if (ret) { 603 if (ret)
545 clk_core_unprepare(core->parent); 604 goto unprepare;
546 return ret;
547 }
548 } 605 }
549 606
550 core->prepare_count++; 607 core->prepare_count++;
551 608
552 return 0; 609 return 0;
610unprepare:
611 clk_core_unprepare(core->parent);
612runtime_put:
613 clk_pm_runtime_put(core);
614 return ret;
553} 615}
554 616
555static int clk_core_prepare_lock(struct clk_core *core) 617static int clk_core_prepare_lock(struct clk_core *core)
@@ -745,6 +807,9 @@ static void clk_unprepare_unused_subtree(struct clk_core *core)
745 if (core->flags & CLK_IGNORE_UNUSED) 807 if (core->flags & CLK_IGNORE_UNUSED)
746 return; 808 return;
747 809
810 if (clk_pm_runtime_get(core))
811 return;
812
748 if (clk_core_is_prepared(core)) { 813 if (clk_core_is_prepared(core)) {
749 trace_clk_unprepare(core); 814 trace_clk_unprepare(core);
750 if (core->ops->unprepare_unused) 815 if (core->ops->unprepare_unused)
@@ -753,6 +818,8 @@ static void clk_unprepare_unused_subtree(struct clk_core *core)
753 core->ops->unprepare(core->hw); 818 core->ops->unprepare(core->hw);
754 trace_clk_unprepare_complete(core); 819 trace_clk_unprepare_complete(core);
755 } 820 }
821
822 clk_pm_runtime_put(core);
756} 823}
757 824
758static void clk_disable_unused_subtree(struct clk_core *core) 825static void clk_disable_unused_subtree(struct clk_core *core)
@@ -768,6 +835,9 @@ static void clk_disable_unused_subtree(struct clk_core *core)
768 if (core->flags & CLK_OPS_PARENT_ENABLE) 835 if (core->flags & CLK_OPS_PARENT_ENABLE)
769 clk_core_prepare_enable(core->parent); 836 clk_core_prepare_enable(core->parent);
770 837
838 if (clk_pm_runtime_get(core))
839 goto unprepare_out;
840
771 flags = clk_enable_lock(); 841 flags = clk_enable_lock();
772 842
773 if (core->enable_count) 843 if (core->enable_count)
@@ -792,6 +862,8 @@ static void clk_disable_unused_subtree(struct clk_core *core)
792 862
793unlock_out: 863unlock_out:
794 clk_enable_unlock(flags); 864 clk_enable_unlock(flags);
865 clk_pm_runtime_put(core);
866unprepare_out:
795 if (core->flags & CLK_OPS_PARENT_ENABLE) 867 if (core->flags & CLK_OPS_PARENT_ENABLE)
796 clk_core_disable_unprepare(core->parent); 868 clk_core_disable_unprepare(core->parent);
797} 869}
@@ -1038,9 +1110,13 @@ EXPORT_SYMBOL_GPL(clk_get_accuracy);
1038static unsigned long clk_recalc(struct clk_core *core, 1110static unsigned long clk_recalc(struct clk_core *core,
1039 unsigned long parent_rate) 1111 unsigned long parent_rate)
1040{ 1112{
1041 if (core->ops->recalc_rate) 1113 unsigned long rate = parent_rate;
1042 return core->ops->recalc_rate(core->hw, parent_rate); 1114
1043 return parent_rate; 1115 if (core->ops->recalc_rate && !clk_pm_runtime_get(core)) {
1116 rate = core->ops->recalc_rate(core->hw, parent_rate);
1117 clk_pm_runtime_put(core);
1118 }
1119 return rate;
1044} 1120}
1045 1121
1046/** 1122/**
@@ -1565,6 +1641,7 @@ static int clk_core_set_rate_nolock(struct clk_core *core,
1565{ 1641{
1566 struct clk_core *top, *fail_clk; 1642 struct clk_core *top, *fail_clk;
1567 unsigned long rate = req_rate; 1643 unsigned long rate = req_rate;
1644 int ret = 0;
1568 1645
1569 if (!core) 1646 if (!core)
1570 return 0; 1647 return 0;
@@ -1581,21 +1658,28 @@ static int clk_core_set_rate_nolock(struct clk_core *core,
1581 if (!top) 1658 if (!top)
1582 return -EINVAL; 1659 return -EINVAL;
1583 1660
1661 ret = clk_pm_runtime_get(core);
1662 if (ret)
1663 return ret;
1664
1584 /* notify that we are about to change rates */ 1665 /* notify that we are about to change rates */
1585 fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE); 1666 fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE);
1586 if (fail_clk) { 1667 if (fail_clk) {
1587 pr_debug("%s: failed to set %s rate\n", __func__, 1668 pr_debug("%s: failed to set %s rate\n", __func__,
1588 fail_clk->name); 1669 fail_clk->name);
1589 clk_propagate_rate_change(top, ABORT_RATE_CHANGE); 1670 clk_propagate_rate_change(top, ABORT_RATE_CHANGE);
1590 return -EBUSY; 1671 ret = -EBUSY;
1672 goto err;
1591 } 1673 }
1592 1674
1593 /* change the rates */ 1675 /* change the rates */
1594 clk_change_rate(top); 1676 clk_change_rate(top);
1595 1677
1596 core->req_rate = req_rate; 1678 core->req_rate = req_rate;
1679err:
1680 clk_pm_runtime_put(core);
1597 1681
1598 return 0; 1682 return ret;
1599} 1683}
1600 1684
1601/** 1685/**
@@ -1826,12 +1910,16 @@ static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent)
1826 p_rate = parent->rate; 1910 p_rate = parent->rate;
1827 } 1911 }
1828 1912
1913 ret = clk_pm_runtime_get(core);
1914 if (ret)
1915 goto out;
1916
1829 /* propagate PRE_RATE_CHANGE notifications */ 1917 /* propagate PRE_RATE_CHANGE notifications */
1830 ret = __clk_speculate_rates(core, p_rate); 1918 ret = __clk_speculate_rates(core, p_rate);
1831 1919
1832 /* abort if a driver objects */ 1920 /* abort if a driver objects */
1833 if (ret & NOTIFY_STOP_MASK) 1921 if (ret & NOTIFY_STOP_MASK)
1834 goto out; 1922 goto runtime_put;
1835 1923
1836 /* do the re-parent */ 1924 /* do the re-parent */
1837 ret = __clk_set_parent(core, parent, p_index); 1925 ret = __clk_set_parent(core, parent, p_index);
@@ -1844,6 +1932,8 @@ static int clk_core_set_parent(struct clk_core *core, struct clk_core *parent)
1844 __clk_recalc_accuracies(core); 1932 __clk_recalc_accuracies(core);
1845 } 1933 }
1846 1934
1935runtime_put:
1936 clk_pm_runtime_put(core);
1847out: 1937out:
1848 clk_prepare_unlock(); 1938 clk_prepare_unlock();
1849 1939
@@ -2350,7 +2440,7 @@ static inline void clk_debug_unregister(struct clk_core *core)
2350 */ 2440 */
2351static int __clk_core_init(struct clk_core *core) 2441static int __clk_core_init(struct clk_core *core)
2352{ 2442{
2353 int i, ret = 0; 2443 int i, ret;
2354 struct clk_core *orphan; 2444 struct clk_core *orphan;
2355 struct hlist_node *tmp2; 2445 struct hlist_node *tmp2;
2356 unsigned long rate; 2446 unsigned long rate;
@@ -2360,6 +2450,10 @@ static int __clk_core_init(struct clk_core *core)
2360 2450
2361 clk_prepare_lock(); 2451 clk_prepare_lock();
2362 2452
2453 ret = clk_pm_runtime_get(core);
2454 if (ret)
2455 goto unlock;
2456
2363 /* check to see if a clock with this name is already registered */ 2457 /* check to see if a clock with this name is already registered */
2364 if (clk_core_lookup(core->name)) { 2458 if (clk_core_lookup(core->name)) {
2365 pr_debug("%s: clk %s already initialized\n", 2459 pr_debug("%s: clk %s already initialized\n",
@@ -2512,6 +2606,8 @@ static int __clk_core_init(struct clk_core *core)
2512 2606
2513 kref_init(&core->ref); 2607 kref_init(&core->ref);
2514out: 2608out:
2609 clk_pm_runtime_put(core);
2610unlock:
2515 clk_prepare_unlock(); 2611 clk_prepare_unlock();
2516 2612
2517 if (!ret) 2613 if (!ret)
@@ -2583,6 +2679,8 @@ struct clk *clk_register(struct device *dev, struct clk_hw *hw)
2583 goto fail_name; 2679 goto fail_name;
2584 } 2680 }
2585 core->ops = hw->init->ops; 2681 core->ops = hw->init->ops;
2682 if (dev && pm_runtime_enabled(dev))
2683 core->dev = dev;
2586 if (dev && dev->driver) 2684 if (dev && dev->driver)
2587 core->owner = dev->driver->owner; 2685 core->owner = dev->driver->owner;
2588 core->hw = hw; 2686 core->hw = hw;
@@ -3177,6 +3275,37 @@ int of_clk_add_hw_provider(struct device_node *np,
3177} 3275}
3178EXPORT_SYMBOL_GPL(of_clk_add_hw_provider); 3276EXPORT_SYMBOL_GPL(of_clk_add_hw_provider);
3179 3277
3278static void devm_of_clk_release_provider(struct device *dev, void *res)
3279{
3280 of_clk_del_provider(*(struct device_node **)res);
3281}
3282
3283int devm_of_clk_add_hw_provider(struct device *dev,
3284 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
3285 void *data),
3286 void *data)
3287{
3288 struct device_node **ptr, *np;
3289 int ret;
3290
3291 ptr = devres_alloc(devm_of_clk_release_provider, sizeof(*ptr),
3292 GFP_KERNEL);
3293 if (!ptr)
3294 return -ENOMEM;
3295
3296 np = dev->of_node;
3297 ret = of_clk_add_hw_provider(np, get, data);
3298 if (!ret) {
3299 *ptr = np;
3300 devres_add(dev, ptr);
3301 } else {
3302 devres_free(ptr);
3303 }
3304
3305 return ret;
3306}
3307EXPORT_SYMBOL_GPL(devm_of_clk_add_hw_provider);
3308
3180/** 3309/**
3181 * of_clk_del_provider() - Remove a previously registered clock provider 3310 * of_clk_del_provider() - Remove a previously registered clock provider
3182 * @np: Device node pointer associated with clock provider 3311 * @np: Device node pointer associated with clock provider
@@ -3198,6 +3327,27 @@ void of_clk_del_provider(struct device_node *np)
3198} 3327}
3199EXPORT_SYMBOL_GPL(of_clk_del_provider); 3328EXPORT_SYMBOL_GPL(of_clk_del_provider);
3200 3329
3330static int devm_clk_provider_match(struct device *dev, void *res, void *data)
3331{
3332 struct device_node **np = res;
3333
3334 if (WARN_ON(!np || !*np))
3335 return 0;
3336
3337 return *np == data;
3338}
3339
3340void devm_of_clk_del_provider(struct device *dev)
3341{
3342 int ret;
3343
3344 ret = devres_release(dev, devm_of_clk_release_provider,
3345 devm_clk_provider_match, dev->of_node);
3346
3347 WARN_ON(ret);
3348}
3349EXPORT_SYMBOL(devm_of_clk_del_provider);
3350
3201static struct clk_hw * 3351static struct clk_hw *
3202__of_clk_get_hw_from_provider(struct of_clk_provider *provider, 3352__of_clk_get_hw_from_provider(struct of_clk_provider *provider,
3203 struct of_phandle_args *clkspec) 3353 struct of_phandle_args *clkspec)
diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c
index fa0fba653898..77072c7778b9 100644
--- a/drivers/clk/hisilicon/clk-hi3620.c
+++ b/drivers/clk/hisilicon/clk-hi3620.c
@@ -415,7 +415,7 @@ static int mmc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
415 return mmc_clk_set_timing(hw, rate); 415 return mmc_clk_set_timing(hw, rate);
416} 416}
417 417
418static struct clk_ops clk_mmc_ops = { 418static const struct clk_ops clk_mmc_ops = {
419 .prepare = mmc_clk_prepare, 419 .prepare = mmc_clk_prepare,
420 .determine_rate = mmc_clk_determine_rate, 420 .determine_rate = mmc_clk_determine_rate,
421 .set_rate = mmc_clk_set_rate, 421 .set_rate = mmc_clk_set_rate,
diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c
index a18258eb89cb..f40419959656 100644
--- a/drivers/clk/hisilicon/clk-hi3660.c
+++ b/drivers/clk/hisilicon/clk-hi3660.c
@@ -34,7 +34,7 @@ static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = {
34 34
35/* crgctrl */ 35/* crgctrl */
36static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = { 36static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = {
37 { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 8, 0, }, 37 { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 16, 0, },
38 { HI3660_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys", 1, 6, 0, }, 38 { HI3660_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys", 1, 6, 0, },
39 { HI3660_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_iomcu", 1, 4, 0, }, 39 { HI3660_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_iomcu", 1, 4, 0, },
40 { HI3660_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_iomcu", 1, 4, 0, }, 40 { HI3660_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_iomcu", 1, 4, 0, },
diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c
index e786d717f75d..a87809d4bd52 100644
--- a/drivers/clk/hisilicon/clk-hi6220.c
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -145,7 +145,7 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = {
145 { HI6220_BBPPLL_SEL, "bbppll_sel", "pll0_bbp_gate", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 9, 0, }, 145 { HI6220_BBPPLL_SEL, "bbppll_sel", "pll0_bbp_gate", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 9, 0, },
146 { HI6220_MEDIA_PLL_SRC, "media_pll_src", "pll_media_gate", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 10, 0, }, 146 { HI6220_MEDIA_PLL_SRC, "media_pll_src", "pll_media_gate", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 10, 0, },
147 { HI6220_MMC2_SEL, "mmc2_sel", "mmc2_mux1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 11, 0, }, 147 { HI6220_MMC2_SEL, "mmc2_sel", "mmc2_mux1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 11, 0, },
148 { HI6220_CS_ATB_SYSPLL, "cs_atb_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 12, 0, }, 148 { HI6220_CS_ATB_SYSPLL, "cs_atb_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IS_CRITICAL, 0x270, 12, 0, },
149}; 149};
150 150
151static struct hisi_mux_clock hi6220_mux_clks_sys[] __initdata = { 151static struct hisi_mux_clock hi6220_mux_clks_sys[] __initdata = {
diff --git a/drivers/clk/hisilicon/clk-hix5hd2.c b/drivers/clk/hisilicon/clk-hix5hd2.c
index 14b05efa3c2a..9584f0c32dda 100644
--- a/drivers/clk/hisilicon/clk-hix5hd2.c
+++ b/drivers/clk/hisilicon/clk-hix5hd2.c
@@ -208,7 +208,7 @@ static void clk_ether_unprepare(struct clk_hw *hw)
208 writel_relaxed(val, clk->ctrl_reg); 208 writel_relaxed(val, clk->ctrl_reg);
209} 209}
210 210
211static struct clk_ops clk_ether_ops = { 211static const struct clk_ops clk_ether_ops = {
212 .prepare = clk_ether_prepare, 212 .prepare = clk_ether_prepare,
213 .unprepare = clk_ether_unprepare, 213 .unprepare = clk_ether_unprepare,
214}; 214};
@@ -247,7 +247,7 @@ static void clk_complex_disable(struct clk_hw *hw)
247 writel_relaxed(val, clk->phy_reg); 247 writel_relaxed(val, clk->phy_reg);
248} 248}
249 249
250static struct clk_ops clk_complex_ops = { 250static const struct clk_ops clk_complex_ops = {
251 .enable = clk_complex_enable, 251 .enable = clk_complex_enable,
252 .disable = clk_complex_disable, 252 .disable = clk_complex_disable,
253}; 253};
diff --git a/drivers/clk/hisilicon/clkgate-separated.c b/drivers/clk/hisilicon/clkgate-separated.c
index 7908bc3c9ec7..f36bdef91831 100644
--- a/drivers/clk/hisilicon/clkgate-separated.c
+++ b/drivers/clk/hisilicon/clkgate-separated.c
@@ -88,7 +88,7 @@ static int clkgate_separated_is_enabled(struct clk_hw *hw)
88 return reg ? 1 : 0; 88 return reg ? 1 : 0;
89} 89}
90 90
91static struct clk_ops clkgate_separated_ops = { 91static const struct clk_ops clkgate_separated_ops = {
92 .enable = clkgate_separated_enable, 92 .enable = clkgate_separated_enable,
93 .disable = clkgate_separated_disable, 93 .disable = clkgate_separated_disable,
94 .is_enabled = clkgate_separated_is_enabled, 94 .is_enabled = clkgate_separated_is_enabled,
@@ -105,10 +105,8 @@ struct clk *hisi_register_clkgate_sep(struct device *dev, const char *name,
105 struct clk_init_data init; 105 struct clk_init_data init;
106 106
107 sclk = kzalloc(sizeof(*sclk), GFP_KERNEL); 107 sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
108 if (!sclk) { 108 if (!sclk)
109 pr_err("%s: fail to allocate separated gated clk\n", __func__);
110 return ERR_PTR(-ENOMEM); 109 return ERR_PTR(-ENOMEM);
111 }
112 110
113 init.name = name; 111 init.name = name;
114 init.ops = &clkgate_separated_ops; 112 init.ops = &clkgate_separated_ops;
diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c
index ed8bb5f7507f..8478948e858e 100644
--- a/drivers/clk/hisilicon/crg-hi3798cv200.c
+++ b/drivers/clk/hisilicon/crg-hi3798cv200.c
@@ -47,6 +47,8 @@
47#define HI3798CV200_FIXED_12M 81 47#define HI3798CV200_FIXED_12M 81
48#define HI3798CV200_FIXED_48M 82 48#define HI3798CV200_FIXED_48M 82
49#define HI3798CV200_FIXED_60M 83 49#define HI3798CV200_FIXED_60M 83
50#define HI3798CV200_FIXED_166P5M 84
51#define HI3798CV200_SDIO0_MUX 85
50 52
51#define HI3798CV200_CRG_NR_CLKS 128 53#define HI3798CV200_CRG_NR_CLKS 128
52 54
@@ -63,6 +65,7 @@ static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = {
63 { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, }, 65 { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
64 { HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, }, 66 { HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, },
65 { HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, }, 67 { HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, },
68 { HI3798CV200_FIXED_166P5M, "166p5m", NULL, 0, 165000000, },
66 { HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, }, 69 { HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, },
67 { HI3798CV200_FIXED_250M, "250m", NULL, 0, 250000000, }, 70 { HI3798CV200_FIXED_250M, "250m", NULL, 0, 250000000, },
68}; 71};
@@ -75,12 +78,19 @@ static const char *const comphy1_mux_p[] = {
75 "100m", "25m"}; 78 "100m", "25m"};
76static u32 comphy1_mux_table[] = {2, 3}; 79static u32 comphy1_mux_table[] = {2, 3};
77 80
81static const char *const sdio_mux_p[] = {
82 "100m", "50m", "150m", "166p5m" };
83static u32 sdio_mux_table[] = {0, 1, 2, 3};
84
78static struct hisi_mux_clock hi3798cv200_mux_clks[] = { 85static struct hisi_mux_clock hi3798cv200_mux_clks[] = {
79 { HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p), 86 { HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
80 CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, }, 87 CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
81 { HI3798CV200_COMBPHY1_MUX, "combphy1_mux", 88 { HI3798CV200_COMBPHY1_MUX, "combphy1_mux",
82 comphy1_mux_p, ARRAY_SIZE(comphy1_mux_p), 89 comphy1_mux_p, ARRAY_SIZE(comphy1_mux_p),
83 CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy1_mux_table, }, 90 CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy1_mux_table, },
91 { HI3798CV200_SDIO0_MUX, "sdio0_mux", sdio_mux_p,
92 ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT,
93 0x9c, 8, 2, 0, sdio_mux_table, },
84}; 94};
85 95
86static const struct hisi_gate_clock hi3798cv200_gate_clks[] = { 96static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
@@ -104,7 +114,7 @@ static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
104 /* SDIO */ 114 /* SDIO */
105 { HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m", 115 { HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m",
106 CLK_SET_RATE_PARENT, 0x9c, 0, 0, }, 116 CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
107 { HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "mmc_mux", 117 { HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "sdio0_mux",
108 CLK_SET_RATE_PARENT, 0x9c, 1, 0, }, 118 CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
109 /* EMMC */ 119 /* EMMC */
110 { HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m", 120 { HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m",
diff --git a/drivers/clk/imx/clk-busy.c b/drivers/clk/imx/clk-busy.c
index 5cc99590f9a3..6df3389687bc 100644
--- a/drivers/clk/imx/clk-busy.c
+++ b/drivers/clk/imx/clk-busy.c
@@ -72,7 +72,7 @@ static int clk_busy_divider_set_rate(struct clk_hw *hw, unsigned long rate,
72 return ret; 72 return ret;
73} 73}
74 74
75static struct clk_ops clk_busy_divider_ops = { 75static const struct clk_ops clk_busy_divider_ops = {
76 .recalc_rate = clk_busy_divider_recalc_rate, 76 .recalc_rate = clk_busy_divider_recalc_rate,
77 .round_rate = clk_busy_divider_round_rate, 77 .round_rate = clk_busy_divider_round_rate,
78 .set_rate = clk_busy_divider_set_rate, 78 .set_rate = clk_busy_divider_set_rate,
@@ -147,7 +147,7 @@ static int clk_busy_mux_set_parent(struct clk_hw *hw, u8 index)
147 return ret; 147 return ret;
148} 148}
149 149
150static struct clk_ops clk_busy_mux_ops = { 150static const struct clk_ops clk_busy_mux_ops = {
151 .get_parent = clk_busy_mux_get_parent, 151 .get_parent = clk_busy_mux_get_parent,
152 .set_parent = clk_busy_mux_set_parent, 152 .set_parent = clk_busy_mux_set_parent,
153}; 153};
diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c
index db44a198a0d9..60fc9d7a9723 100644
--- a/drivers/clk/imx/clk-gate2.c
+++ b/drivers/clk/imx/clk-gate2.c
@@ -118,7 +118,7 @@ static void clk_gate2_disable_unused(struct clk_hw *hw)
118 spin_unlock_irqrestore(gate->lock, flags); 118 spin_unlock_irqrestore(gate->lock, flags);
119} 119}
120 120
121static struct clk_ops clk_gate2_ops = { 121static const struct clk_ops clk_gate2_ops = {
122 .enable = clk_gate2_enable, 122 .enable = clk_gate2_enable,
123 .disable = clk_gate2_disable, 123 .disable = clk_gate2_disable,
124 .disable_unused = clk_gate2_disable_unused, 124 .disable_unused = clk_gate2_disable_unused,
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index c07df719b8a3..8d518ad5dc13 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -761,7 +761,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
761 clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); 761 clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
762 clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); 762 clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
763 clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); 763 clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
764 clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "video_27m", base + 0x70, 4); 764 clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "mipi_core_cfg", base + 0x70, 4);
765 clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6); 765 clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
766 clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8); 766 clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
767 clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); 767 clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index 5e8c18afce9a..85c118164469 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -267,7 +267,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
267 clks[IMX6ULL_CLK_EPDC_SEL] = imx_clk_mux("epdc_sel", base + 0x34, 9, 3, epdc_sels, ARRAY_SIZE(epdc_sels)); 267 clks[IMX6ULL_CLK_EPDC_SEL] = imx_clk_mux("epdc_sel", base + 0x34, 9, 3, epdc_sels, ARRAY_SIZE(epdc_sels));
268 } 268 }
269 clks[IMX6UL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); 269 clks[IMX6UL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
270 clks[IMX6UL_CLK_LCDIF_PRE_SEL] = imx_clk_mux("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels)); 270 clks[IMX6UL_CLK_LCDIF_PRE_SEL] = imx_clk_mux_flags("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels), CLK_SET_RATE_PARENT);
271 clks[IMX6UL_CLK_LCDIF_SEL] = imx_clk_mux("lcdif_sel", base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels)); 271 clks[IMX6UL_CLK_LCDIF_SEL] = imx_clk_mux("lcdif_sel", base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels));
272 272
273 clks[IMX6UL_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux("ldb_di0", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels)); 273 clks[IMX6UL_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux("ldb_di0", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels));
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 2305699db467..80dc211eb74b 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -54,11 +54,6 @@ static const char *arm_m4_sel[] = { "osc", "pll_sys_main_240m_clk",
54 "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk", 54 "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk",
55 "pll_usb_main_clk", }; 55 "pll_usb_main_clk", };
56 56
57static const char *arm_m0_sel[] = { "osc", "pll_sys_main_120m_clk",
58 "pll_enet_125m_clk", "pll_sys_pfd2_135m_clk",
59 "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk",
60 "pll_usb_main_clk", };
61
62static const char *axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk", 57static const char *axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk",
63 "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd5_clk", 58 "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd5_clk",
64 "pll_audio_post_div", "pll_video_main_clk", "pll_sys_pfd7_clk", }; 59 "pll_audio_post_div", "pll_video_main_clk", "pll_sys_pfd7_clk", };
@@ -510,7 +505,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
510 505
511 clks[IMX7D_ARM_A7_ROOT_SRC] = imx_clk_mux2("arm_a7_src", base + 0x8000, 24, 3, arm_a7_sel, ARRAY_SIZE(arm_a7_sel)); 506 clks[IMX7D_ARM_A7_ROOT_SRC] = imx_clk_mux2("arm_a7_src", base + 0x8000, 24, 3, arm_a7_sel, ARRAY_SIZE(arm_a7_sel));
512 clks[IMX7D_ARM_M4_ROOT_SRC] = imx_clk_mux2("arm_m4_src", base + 0x8080, 24, 3, arm_m4_sel, ARRAY_SIZE(arm_m4_sel)); 507 clks[IMX7D_ARM_M4_ROOT_SRC] = imx_clk_mux2("arm_m4_src", base + 0x8080, 24, 3, arm_m4_sel, ARRAY_SIZE(arm_m4_sel));
513 clks[IMX7D_ARM_M0_ROOT_SRC] = imx_clk_mux2("arm_m0_src", base + 0x8100, 24, 3, arm_m0_sel, ARRAY_SIZE(arm_m0_sel));
514 clks[IMX7D_MAIN_AXI_ROOT_SRC] = imx_clk_mux2("axi_src", base + 0x8800, 24, 3, axi_sel, ARRAY_SIZE(axi_sel)); 508 clks[IMX7D_MAIN_AXI_ROOT_SRC] = imx_clk_mux2("axi_src", base + 0x8800, 24, 3, axi_sel, ARRAY_SIZE(axi_sel));
515 clks[IMX7D_DISP_AXI_ROOT_SRC] = imx_clk_mux2("disp_axi_src", base + 0x8880, 24, 3, disp_axi_sel, ARRAY_SIZE(disp_axi_sel)); 509 clks[IMX7D_DISP_AXI_ROOT_SRC] = imx_clk_mux2("disp_axi_src", base + 0x8880, 24, 3, disp_axi_sel, ARRAY_SIZE(disp_axi_sel));
516 clks[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_mux2("enet_axi_src", base + 0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel)); 510 clks[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_mux2("enet_axi_src", base + 0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel));
@@ -582,7 +576,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
582 576
583 clks[IMX7D_ARM_A7_ROOT_CG] = imx_clk_gate3("arm_a7_cg", "arm_a7_src", base + 0x8000, 28); 577 clks[IMX7D_ARM_A7_ROOT_CG] = imx_clk_gate3("arm_a7_cg", "arm_a7_src", base + 0x8000, 28);
584 clks[IMX7D_ARM_M4_ROOT_CG] = imx_clk_gate3("arm_m4_cg", "arm_m4_src", base + 0x8080, 28); 578 clks[IMX7D_ARM_M4_ROOT_CG] = imx_clk_gate3("arm_m4_cg", "arm_m4_src", base + 0x8080, 28);
585 clks[IMX7D_ARM_M0_ROOT_CG] = imx_clk_gate3("arm_m0_cg", "arm_m0_src", base + 0x8100, 28);
586 clks[IMX7D_MAIN_AXI_ROOT_CG] = imx_clk_gate3("axi_cg", "axi_src", base + 0x8800, 28); 579 clks[IMX7D_MAIN_AXI_ROOT_CG] = imx_clk_gate3("axi_cg", "axi_src", base + 0x8800, 28);
587 clks[IMX7D_DISP_AXI_ROOT_CG] = imx_clk_gate3("disp_axi_cg", "disp_axi_src", base + 0x8880, 28); 580 clks[IMX7D_DISP_AXI_ROOT_CG] = imx_clk_gate3("disp_axi_cg", "disp_axi_src", base + 0x8880, 28);
588 clks[IMX7D_ENET_AXI_ROOT_CG] = imx_clk_gate3("enet_axi_cg", "enet_axi_src", base + 0x8900, 28); 581 clks[IMX7D_ENET_AXI_ROOT_CG] = imx_clk_gate3("enet_axi_cg", "enet_axi_src", base + 0x8900, 28);
@@ -721,7 +714,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
721 714
722 clks[IMX7D_ARM_A7_ROOT_DIV] = imx_clk_divider2("arm_a7_div", "arm_a7_cg", base + 0x8000, 0, 3); 715 clks[IMX7D_ARM_A7_ROOT_DIV] = imx_clk_divider2("arm_a7_div", "arm_a7_cg", base + 0x8000, 0, 3);
723 clks[IMX7D_ARM_M4_ROOT_DIV] = imx_clk_divider2("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3); 716 clks[IMX7D_ARM_M4_ROOT_DIV] = imx_clk_divider2("arm_m4_div", "arm_m4_cg", base + 0x8080, 0, 3);
724 clks[IMX7D_ARM_M0_ROOT_DIV] = imx_clk_divider2("arm_m0_div", "arm_m0_cg", base + 0x8100, 0, 3);
725 clks[IMX7D_MAIN_AXI_ROOT_DIV] = imx_clk_divider2("axi_post_div", "axi_pre_div", base + 0x8800, 0, 6); 717 clks[IMX7D_MAIN_AXI_ROOT_DIV] = imx_clk_divider2("axi_post_div", "axi_pre_div", base + 0x8800, 0, 6);
726 clks[IMX7D_DISP_AXI_ROOT_DIV] = imx_clk_divider2("disp_axi_post_div", "disp_axi_pre_div", base + 0x8880, 0, 6); 718 clks[IMX7D_DISP_AXI_ROOT_DIV] = imx_clk_divider2("disp_axi_post_div", "disp_axi_pre_div", base + 0x8880, 0, 6);
727 clks[IMX7D_ENET_AXI_ROOT_DIV] = imx_clk_divider2("enet_axi_post_div", "enet_axi_pre_div", base + 0x8900, 0, 6); 719 clks[IMX7D_ENET_AXI_ROOT_DIV] = imx_clk_divider2("enet_axi_post_div", "enet_axi_pre_div", base + 0x8900, 0, 6);
@@ -793,11 +785,10 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
793 785
794 clks[IMX7D_ARM_A7_ROOT_CLK] = imx_clk_gate4("arm_a7_root_clk", "arm_a7_div", base + 0x4000, 0); 786 clks[IMX7D_ARM_A7_ROOT_CLK] = imx_clk_gate4("arm_a7_root_clk", "arm_a7_div", base + 0x4000, 0);
795 clks[IMX7D_ARM_M4_ROOT_CLK] = imx_clk_gate4("arm_m4_root_clk", "arm_m4_div", base + 0x4010, 0); 787 clks[IMX7D_ARM_M4_ROOT_CLK] = imx_clk_gate4("arm_m4_root_clk", "arm_m4_div", base + 0x4010, 0);
796 clks[IMX7D_ARM_M0_ROOT_CLK] = imx_clk_gate4("arm_m0_root_clk", "arm_m0_div", base + 0x4020, 0);
797 clks[IMX7D_MAIN_AXI_ROOT_CLK] = imx_clk_gate4("main_axi_root_clk", "axi_post_div", base + 0x4040, 0); 788 clks[IMX7D_MAIN_AXI_ROOT_CLK] = imx_clk_gate4("main_axi_root_clk", "axi_post_div", base + 0x4040, 0);
798 clks[IMX7D_DISP_AXI_ROOT_CLK] = imx_clk_gate4("disp_axi_root_clk", "disp_axi_post_div", base + 0x4050, 0); 789 clks[IMX7D_DISP_AXI_ROOT_CLK] = imx_clk_gate4("disp_axi_root_clk", "disp_axi_post_div", base + 0x4050, 0);
799 clks[IMX7D_ENET_AXI_ROOT_CLK] = imx_clk_gate4("enet_axi_root_clk", "enet_axi_post_div", base + 0x4060, 0); 790 clks[IMX7D_ENET_AXI_ROOT_CLK] = imx_clk_gate4("enet_axi_root_clk", "enet_axi_post_div", base + 0x4060, 0);
800 clks[IMX7D_OCRAM_CLK] = imx_clk_gate4("ocram_clk", "axi_post_div", base + 0x4110, 0); 791 clks[IMX7D_OCRAM_CLK] = imx_clk_gate4("ocram_clk", "main_axi_root_clk", base + 0x4110, 0);
801 clks[IMX7D_OCRAM_S_CLK] = imx_clk_gate4("ocram_s_clk", "ahb_root_clk", base + 0x4120, 0); 792 clks[IMX7D_OCRAM_S_CLK] = imx_clk_gate4("ocram_s_clk", "ahb_root_clk", base + 0x4120, 0);
802 clks[IMX7D_DRAM_ROOT_CLK] = imx_clk_gate4("dram_root_clk", "dram_post_div", base + 0x4130, 0); 793 clks[IMX7D_DRAM_ROOT_CLK] = imx_clk_gate4("dram_root_clk", "dram_post_div", base + 0x4130, 0);
803 clks[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_gate4("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0); 794 clks[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_gate4("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0);
diff --git a/drivers/clk/imx/clk-pllv1.c b/drivers/clk/imx/clk-pllv1.c
index e47a1c2fe8bd..4ba9973d4c18 100644
--- a/drivers/clk/imx/clk-pllv1.c
+++ b/drivers/clk/imx/clk-pllv1.c
@@ -107,7 +107,7 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
107 return ull; 107 return ull;
108} 108}
109 109
110static struct clk_ops clk_pllv1_ops = { 110static const struct clk_ops clk_pllv1_ops = {
111 .recalc_rate = clk_pllv1_recalc_rate, 111 .recalc_rate = clk_pllv1_recalc_rate,
112}; 112};
113 113
diff --git a/drivers/clk/imx/clk-pllv2.c b/drivers/clk/imx/clk-pllv2.c
index 9842d657e974..85b5cbe9744c 100644
--- a/drivers/clk/imx/clk-pllv2.c
+++ b/drivers/clk/imx/clk-pllv2.c
@@ -227,7 +227,7 @@ static void clk_pllv2_unprepare(struct clk_hw *hw)
227 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); 227 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
228} 228}
229 229
230static struct clk_ops clk_pllv2_ops = { 230static const struct clk_ops clk_pllv2_ops = {
231 .prepare = clk_pllv2_prepare, 231 .prepare = clk_pllv2_prepare,
232 .unprepare = clk_pllv2_unprepare, 232 .unprepare = clk_pllv2_unprepare,
233 .recalc_rate = clk_pllv2_recalc_rate, 233 .recalc_rate = clk_pllv2_recalc_rate,
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 28739a9a6e37..59dc0aad553c 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -50,6 +50,56 @@ config COMMON_CLK_MT2701_BDPSYS
50 ---help--- 50 ---help---
51 This driver supports Mediatek MT2701 bdpsys clocks. 51 This driver supports Mediatek MT2701 bdpsys clocks.
52 52
53config COMMON_CLK_MT2712
54 bool "Clock driver for Mediatek MT2712"
55 depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
56 select COMMON_CLK_MEDIATEK
57 default ARCH_MEDIATEK && ARM64
58 ---help---
59 This driver supports Mediatek MT2712 basic clocks.
60
61config COMMON_CLK_MT2712_BDPSYS
62 bool "Clock driver for Mediatek MT2712 bdpsys"
63 depends on COMMON_CLK_MT2712
64 ---help---
65 This driver supports Mediatek MT2712 bdpsys clocks.
66
67config COMMON_CLK_MT2712_IMGSYS
68 bool "Clock driver for Mediatek MT2712 imgsys"
69 depends on COMMON_CLK_MT2712
70 ---help---
71 This driver supports Mediatek MT2712 imgsys clocks.
72
73config COMMON_CLK_MT2712_JPGDECSYS
74 bool "Clock driver for Mediatek MT2712 jpgdecsys"
75 depends on COMMON_CLK_MT2712
76 ---help---
77 This driver supports Mediatek MT2712 jpgdecsys clocks.
78
79config COMMON_CLK_MT2712_MFGCFG
80 bool "Clock driver for Mediatek MT2712 mfgcfg"
81 depends on COMMON_CLK_MT2712
82 ---help---
83 This driver supports Mediatek MT2712 mfgcfg clocks.
84
85config COMMON_CLK_MT2712_MMSYS
86 bool "Clock driver for Mediatek MT2712 mmsys"
87 depends on COMMON_CLK_MT2712
88 ---help---
89 This driver supports Mediatek MT2712 mmsys clocks.
90
91config COMMON_CLK_MT2712_VDECSYS
92 bool "Clock driver for Mediatek MT2712 vdecsys"
93 depends on COMMON_CLK_MT2712
94 ---help---
95 This driver supports Mediatek MT2712 vdecsys clocks.
96
97config COMMON_CLK_MT2712_VENCSYS
98 bool "Clock driver for Mediatek MT2712 vencsys"
99 depends on COMMON_CLK_MT2712
100 ---help---
101 This driver supports Mediatek MT2712 vencsys clocks.
102
53config COMMON_CLK_MT6797 103config COMMON_CLK_MT6797
54 bool "Clock driver for Mediatek MT6797" 104 bool "Clock driver for Mediatek MT6797"
55 depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST 105 depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
@@ -82,6 +132,36 @@ config COMMON_CLK_MT6797_VENCSYS
82 ---help--- 132 ---help---
83 This driver supports Mediatek MT6797 vencsys clocks. 133 This driver supports Mediatek MT6797 vencsys clocks.
84 134
135config COMMON_CLK_MT7622
136 bool "Clock driver for MediaTek MT7622"
137 depends on ARCH_MEDIATEK || COMPILE_TEST
138 select COMMON_CLK_MEDIATEK
139 default ARCH_MEDIATEK
140 ---help---
141 This driver supports MediaTek MT7622 basic clocks and clocks
142 required for various periperals found on MediaTek.
143
144config COMMON_CLK_MT7622_ETHSYS
145 bool "Clock driver for MediaTek MT7622 ETHSYS"
146 depends on COMMON_CLK_MT7622
147 ---help---
148 This driver add support for clocks for Ethernet and SGMII
149 required on MediaTek MT7622 SoC.
150
151config COMMON_CLK_MT7622_HIFSYS
152 bool "Clock driver for MediaTek MT7622 HIFSYS"
153 depends on COMMON_CLK_MT7622
154 ---help---
155 This driver supports MediaTek MT7622 HIFSYS clocks providing
156 to PCI-E and USB.
157
158config COMMON_CLK_MT7622_AUDSYS
159 bool "Clock driver for MediaTek MT7622 AUDSYS"
160 depends on COMMON_CLK_MT7622
161 ---help---
162 This driver supports MediaTek MT7622 AUDSYS clocks providing
163 to audio consumers such as I2S and TDM.
164
85config COMMON_CLK_MT8135 165config COMMON_CLK_MT8135
86 bool "Clock driver for Mediatek MT8135" 166 bool "Clock driver for Mediatek MT8135"
87 depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST 167 depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index ba2a070765f0..c421ffcd49ff 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -13,5 +13,17 @@ obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
13obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o 13obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o
14obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o 14obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o
15obj-$(CONFIG_COMMON_CLK_MT2701_VDECSYS) += clk-mt2701-vdec.o 15obj-$(CONFIG_COMMON_CLK_MT2701_VDECSYS) += clk-mt2701-vdec.o
16obj-$(CONFIG_COMMON_CLK_MT2712) += clk-mt2712.o
17obj-$(CONFIG_COMMON_CLK_MT2712_BDPSYS) += clk-mt2712-bdp.o
18obj-$(CONFIG_COMMON_CLK_MT2712_IMGSYS) += clk-mt2712-img.o
19obj-$(CONFIG_COMMON_CLK_MT2712_JPGDECSYS) += clk-mt2712-jpgdec.o
20obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) += clk-mt2712-mfg.o
21obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) += clk-mt2712-mm.o
22obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) += clk-mt2712-vdec.o
23obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) += clk-mt2712-venc.o
24obj-$(CONFIG_COMMON_CLK_MT7622) += clk-mt7622.o
25obj-$(CONFIG_COMMON_CLK_MT7622_ETHSYS) += clk-mt7622-eth.o
26obj-$(CONFIG_COMMON_CLK_MT7622_HIFSYS) += clk-mt7622-hif.o
27obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) += clk-mt7622-aud.o
16obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o 28obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
17obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o 29obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 9598889f972b..8e7f16fd87c9 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -750,7 +750,7 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {
750 750
751static struct clk_onecell_data *infra_clk_data; 751static struct clk_onecell_data *infra_clk_data;
752 752
753static void mtk_infrasys_init_early(struct device_node *node) 753static void __init mtk_infrasys_init_early(struct device_node *node)
754{ 754{
755 int r, i; 755 int r, i;
756 756
diff --git a/drivers/clk/mediatek/clk-mt2712-bdp.c b/drivers/clk/mediatek/clk-mt2712-bdp.c
new file mode 100644
index 000000000000..5fe4728c076e
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt2712-bdp.c
@@ -0,0 +1,102 @@
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk-provider.h>
16#include <linux/platform_device.h>
17
18#include "clk-mtk.h"
19#include "clk-gate.h"
20
21#include <dt-bindings/clock/mt2712-clk.h>
22
23static const struct mtk_gate_regs bdp_cg_regs = {
24 .set_ofs = 0x100,
25 .clr_ofs = 0x100,
26 .sta_ofs = 0x100,
27};
28
29#define GATE_BDP(_id, _name, _parent, _shift) { \
30 .id = _id, \
31 .name = _name, \
32 .parent_name = _parent, \
33 .regs = &bdp_cg_regs, \
34 .shift = _shift, \
35 .ops = &mtk_clk_gate_ops_no_setclr, \
36 }
37
38static const struct mtk_gate bdp_clks[] = {
39 GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0),
40 GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d", "mm_sel", 1),
41 GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d", "mm_sel", 2),
42 GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl", "tvd_sel", 3),
43 GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d", "mm_sel", 4),
44 GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b", "mm_sel", 5),
45 GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b", "mm_sel", 9),
46 GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m", "di_sel", 10),
47 GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout", "di_sel", 11),
48 GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74", "di_sel", 12),
49 GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs", "di_sel", 13),
50 GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148", "di_sel", 14),
51 GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b", "mm_sel", 15),
52 GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d", "mm_sel", 16),
53 GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs", "di_sel", 17),
54 GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b", "mm_sel", 18),
55 GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19),
56 GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20),
57 GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b", "mm_sel", 21),
58 GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent", "nr_sel", 22),
59 GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d", "mm_sel", 23),
60 GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b", "mm_sel", 24),
61 GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b", "mm_sel", 25),
62 GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d", "mm_sel", 26),
63 GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d", "mm_sel", 27),
64 GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc", "mm_sel", 28),
65 GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54", "tvd_sel", 29),
66 GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus", "mm_sel", 30),
67};
68
69static int clk_mt2712_bdp_probe(struct platform_device *pdev)
70{
71 struct clk_onecell_data *clk_data;
72 int r;
73 struct device_node *node = pdev->dev.of_node;
74
75 clk_data = mtk_alloc_clk_data(CLK_BDP_NR_CLK);
76
77 mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
78 clk_data);
79
80 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
81
82 if (r != 0)
83 pr_err("%s(): could not register clock provider: %d\n",
84 __func__, r);
85
86 return r;
87}
88
89static const struct of_device_id of_match_clk_mt2712_bdp[] = {
90 { .compatible = "mediatek,mt2712-bdpsys", },
91 {}
92};
93
94static struct platform_driver clk_mt2712_bdp_drv = {
95 .probe = clk_mt2712_bdp_probe,
96 .driver = {
97 .name = "clk-mt2712-bdp",
98 .of_match_table = of_match_clk_mt2712_bdp,
99 },
100};
101
102builtin_platform_driver(clk_mt2712_bdp_drv);
diff --git a/drivers/clk/mediatek/clk-mt2712-img.c b/drivers/clk/mediatek/clk-mt2712-img.c
new file mode 100644
index 000000000000..139ff55d495e
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt2712-img.c
@@ -0,0 +1,80 @@
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk-provider.h>
16#include <linux/platform_device.h>
17
18#include "clk-mtk.h"
19#include "clk-gate.h"
20
21#include <dt-bindings/clock/mt2712-clk.h>
22
23static const struct mtk_gate_regs img_cg_regs = {
24 .set_ofs = 0x0,
25 .clr_ofs = 0x0,
26 .sta_ofs = 0x0,
27};
28
29#define GATE_IMG(_id, _name, _parent, _shift) { \
30 .id = _id, \
31 .name = _name, \
32 .parent_name = _parent, \
33 .regs = &img_cg_regs, \
34 .shift = _shift, \
35 .ops = &mtk_clk_gate_ops_no_setclr, \
36 }
37
38static const struct mtk_gate img_clks[] = {
39 GATE_IMG(CLK_IMG_SMI_LARB2, "img_smi_larb2", "mm_sel", 0),
40 GATE_IMG(CLK_IMG_SENINF_SCAM_EN, "img_scam_en", "csi0", 3),
41 GATE_IMG(CLK_IMG_SENINF_CAM_EN, "img_cam_en", "mm_sel", 8),
42 GATE_IMG(CLK_IMG_CAM_SV_EN, "img_cam_sv_en", "mm_sel", 9),
43 GATE_IMG(CLK_IMG_CAM_SV1_EN, "img_cam_sv1_en", "mm_sel", 10),
44 GATE_IMG(CLK_IMG_CAM_SV2_EN, "img_cam_sv2_en", "mm_sel", 11),
45};
46
47static int clk_mt2712_img_probe(struct platform_device *pdev)
48{
49 struct clk_onecell_data *clk_data;
50 int r;
51 struct device_node *node = pdev->dev.of_node;
52
53 clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
54
55 mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
56 clk_data);
57
58 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
59
60 if (r != 0)
61 pr_err("%s(): could not register clock provider: %d\n",
62 __func__, r);
63
64 return r;
65}
66
67static const struct of_device_id of_match_clk_mt2712_img[] = {
68 { .compatible = "mediatek,mt2712-imgsys", },
69 {}
70};
71
72static struct platform_driver clk_mt2712_img_drv = {
73 .probe = clk_mt2712_img_probe,
74 .driver = {
75 .name = "clk-mt2712-img",
76 .of_match_table = of_match_clk_mt2712_img,
77 },
78};
79
80builtin_platform_driver(clk_mt2712_img_drv);
diff --git a/drivers/clk/mediatek/clk-mt2712-jpgdec.c b/drivers/clk/mediatek/clk-mt2712-jpgdec.c
new file mode 100644
index 000000000000..c7d4aada4892
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt2712-jpgdec.c
@@ -0,0 +1,76 @@
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk-provider.h>
16#include <linux/platform_device.h>
17
18#include "clk-mtk.h"
19#include "clk-gate.h"
20
21#include <dt-bindings/clock/mt2712-clk.h>
22
23static const struct mtk_gate_regs jpgdec_cg_regs = {
24 .set_ofs = 0x4,
25 .clr_ofs = 0x8,
26 .sta_ofs = 0x0,
27};
28
29#define GATE_JPGDEC(_id, _name, _parent, _shift) { \
30 .id = _id, \
31 .name = _name, \
32 .parent_name = _parent, \
33 .regs = &jpgdec_cg_regs, \
34 .shift = _shift, \
35 .ops = &mtk_clk_gate_ops_setclr_inv, \
36 }
37
38static const struct mtk_gate jpgdec_clks[] = {
39 GATE_JPGDEC(CLK_JPGDEC_JPGDEC1, "jpgdec_jpgdec1", "jpgdec_sel", 0),
40 GATE_JPGDEC(CLK_JPGDEC_JPGDEC, "jpgdec_jpgdec", "jpgdec_sel", 4),
41};
42
43static int clk_mt2712_jpgdec_probe(struct platform_device *pdev)
44{
45 struct clk_onecell_data *clk_data;
46 int r;
47 struct device_node *node = pdev->dev.of_node;
48
49 clk_data = mtk_alloc_clk_data(CLK_JPGDEC_NR_CLK);
50
51 mtk_clk_register_gates(node, jpgdec_clks, ARRAY_SIZE(jpgdec_clks),
52 clk_data);
53
54 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
55
56 if (r != 0)
57 pr_err("%s(): could not register clock provider: %d\n",
58 __func__, r);
59
60 return r;
61}
62
63static const struct of_device_id of_match_clk_mt2712_jpgdec[] = {
64 { .compatible = "mediatek,mt2712-jpgdecsys", },
65 {}
66};
67
68static struct platform_driver clk_mt2712_jpgdec_drv = {
69 .probe = clk_mt2712_jpgdec_probe,
70 .driver = {
71 .name = "clk-mt2712-jpgdec",
72 .of_match_table = of_match_clk_mt2712_jpgdec,
73 },
74};
75
76builtin_platform_driver(clk_mt2712_jpgdec_drv);
diff --git a/drivers/clk/mediatek/clk-mt2712-mfg.c b/drivers/clk/mediatek/clk-mt2712-mfg.c
new file mode 100644
index 000000000000..570f72d48d4d
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt2712-mfg.c
@@ -0,0 +1,75 @@
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk-provider.h>
16#include <linux/platform_device.h>
17
18#include "clk-mtk.h"
19#include "clk-gate.h"
20
21#include <dt-bindings/clock/mt2712-clk.h>
22
23static const struct mtk_gate_regs mfg_cg_regs = {
24 .set_ofs = 0x4,
25 .clr_ofs = 0x8,
26 .sta_ofs = 0x0,
27};
28
29#define GATE_MFG(_id, _name, _parent, _shift) { \
30 .id = _id, \
31 .name = _name, \
32 .parent_name = _parent, \
33 .regs = &mfg_cg_regs, \
34 .shift = _shift, \
35 .ops = &mtk_clk_gate_ops_setclr, \
36 }
37
38static const struct mtk_gate mfg_clks[] = {
39 GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
40};
41
42static int clk_mt2712_mfg_probe(struct platform_device *pdev)
43{
44 struct clk_onecell_data *clk_data;
45 int r;
46 struct device_node *node = pdev->dev.of_node;
47
48 clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
49
50 mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
51 clk_data);
52
53 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
54
55 if (r != 0)
56 pr_err("%s(): could not register clock provider: %d\n",
57 __func__, r);
58
59 return r;
60}
61
62static const struct of_device_id of_match_clk_mt2712_mfg[] = {
63 { .compatible = "mediatek,mt2712-mfgcfg", },
64 {}
65};
66
67static struct platform_driver clk_mt2712_mfg_drv = {
68 .probe = clk_mt2712_mfg_probe,
69 .driver = {
70 .name = "clk-mt2712-mfg",
71 .of_match_table = of_match_clk_mt2712_mfg,
72 },
73};
74
75builtin_platform_driver(clk_mt2712_mfg_drv);
diff --git a/drivers/clk/mediatek/clk-mt2712-mm.c b/drivers/clk/mediatek/clk-mt2712-mm.c
new file mode 100644
index 000000000000..a8b4b6d42488
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt2712-mm.c
@@ -0,0 +1,170 @@
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk-provider.h>
16#include <linux/platform_device.h>
17
18#include "clk-mtk.h"
19#include "clk-gate.h"
20
21#include <dt-bindings/clock/mt2712-clk.h>
22
23static const struct mtk_gate_regs mm0_cg_regs = {
24 .set_ofs = 0x104,
25 .clr_ofs = 0x108,
26 .sta_ofs = 0x100,
27};
28
29static const struct mtk_gate_regs mm1_cg_regs = {
30 .set_ofs = 0x114,
31 .clr_ofs = 0x118,
32 .sta_ofs = 0x110,
33};
34
35static const struct mtk_gate_regs mm2_cg_regs = {
36 .set_ofs = 0x224,
37 .clr_ofs = 0x228,
38 .sta_ofs = 0x220,
39};
40
41#define GATE_MM0(_id, _name, _parent, _shift) { \
42 .id = _id, \
43 .name = _name, \
44 .parent_name = _parent, \
45 .regs = &mm0_cg_regs, \
46 .shift = _shift, \
47 .ops = &mtk_clk_gate_ops_setclr, \
48 }
49
50#define GATE_MM1(_id, _name, _parent, _shift) { \
51 .id = _id, \
52 .name = _name, \
53 .parent_name = _parent, \
54 .regs = &mm1_cg_regs, \
55 .shift = _shift, \
56 .ops = &mtk_clk_gate_ops_setclr, \
57 }
58
59#define GATE_MM2(_id, _name, _parent, _shift) { \
60 .id = _id, \
61 .name = _name, \
62 .parent_name = _parent, \
63 .regs = &mm2_cg_regs, \
64 .shift = _shift, \
65 .ops = &mtk_clk_gate_ops_setclr, \
66 }
67
68static const struct mtk_gate mm_clks[] = {
69 /* MM0 */
70 GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
71 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
72 GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
73 GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
74 GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
75 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
76 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
77 GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
78 GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
79 GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
80 GATE_MM0(CLK_MM_MDP_CROP, "mm_mdp_crop", "mm_sel", 10),
81 GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
82 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
83 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
84 GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
85 GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "clk32k", 15),
86 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
87 GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
88 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
89 GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
90 GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
91 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
92 GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
93 GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
94 GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
95 GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
96 GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
97 GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
98 GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
99 GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
100 /* MM1 */
101 GATE_MM1(CLK_MM_DISP_PWM0_MM, "mm_pwm0_mm", "mm_sel", 0),
102 GATE_MM1(CLK_MM_DISP_PWM0_26M, "mm_pwm0_26m", "pwm_sel", 1),
103 GATE_MM1(CLK_MM_DISP_PWM1_MM, "mm_pwm1_mm", "mm_sel", 2),
104 GATE_MM1(CLK_MM_DISP_PWM1_26M, "mm_pwm1_26m", "pwm_sel", 3),
105 GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
106 GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_lntc", 5),
107 GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
108 GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_lntc", 7),
109 GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "vpll_dpix", 8),
110 GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
111 GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "vpll3_dpix", 10),
112 GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
113 GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "vpll_dpix", 16),
114 GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx", 17),
115 GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
116 GATE_MM1(CLK_MM_SMI_COMMON1, "mm_smi_common1", "mm_sel", 21),
117 GATE_MM1(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 22),
118 GATE_MM1(CLK_MM_MDP_RDMA2, "mm_mdp_rdma2", "mm_sel", 23),
119 GATE_MM1(CLK_MM_MDP_TDSHP2, "mm_mdp_tdshp2", "mm_sel", 24),
120 GATE_MM1(CLK_MM_DISP_OVL2, "mm_disp_ovl2", "mm_sel", 25),
121 GATE_MM1(CLK_MM_DISP_WDMA2, "mm_disp_wdma2", "mm_sel", 26),
122 GATE_MM1(CLK_MM_DISP_COLOR2, "mm_disp_color2", "mm_sel", 27),
123 GATE_MM1(CLK_MM_DISP_AAL1, "mm_disp_aal1", "mm_sel", 28),
124 GATE_MM1(CLK_MM_DISP_OD1, "mm_disp_od1", "mm_sel", 29),
125 GATE_MM1(CLK_MM_LVDS1_PIXEL, "mm_lvds1_pixel", "vpll3_dpix", 30),
126 GATE_MM1(CLK_MM_LVDS1_CTS, "mm_lvds1_cts", "lvdstx3", 31),
127 /* MM2 */
128 GATE_MM2(CLK_MM_SMI_LARB7, "mm_smi_larb7", "mm_sel", 0),
129 GATE_MM2(CLK_MM_MDP_RDMA3, "mm_mdp_rdma3", "mm_sel", 1),
130 GATE_MM2(CLK_MM_MDP_WROT2, "mm_mdp_wrot2", "mm_sel", 2),
131 GATE_MM2(CLK_MM_DSI2, "mm_dsi2", "mm_sel", 3),
132 GATE_MM2(CLK_MM_DSI2_DIGITAL, "mm_dsi2_digital", "dsi0_lntc", 4),
133 GATE_MM2(CLK_MM_DSI3, "mm_dsi3", "mm_sel", 5),
134 GATE_MM2(CLK_MM_DSI3_DIGITAL, "mm_dsi3_digital", "dsi1_lntc", 6),
135};
136
137static int clk_mt2712_mm_probe(struct platform_device *pdev)
138{
139 struct clk_onecell_data *clk_data;
140 int r;
141 struct device_node *node = pdev->dev.of_node;
142
143 clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
144
145 mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
146 clk_data);
147
148 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
149
150 if (r != 0)
151 pr_err("%s(): could not register clock provider: %d\n",
152 __func__, r);
153
154 return r;
155}
156
157static const struct of_device_id of_match_clk_mt2712_mm[] = {
158 { .compatible = "mediatek,mt2712-mmsys", },
159 {}
160};
161
162static struct platform_driver clk_mt2712_mm_drv = {
163 .probe = clk_mt2712_mm_probe,
164 .driver = {
165 .name = "clk-mt2712-mm",
166 .of_match_table = of_match_clk_mt2712_mm,
167 },
168};
169
170builtin_platform_driver(clk_mt2712_mm_drv);
diff --git a/drivers/clk/mediatek/clk-mt2712-vdec.c b/drivers/clk/mediatek/clk-mt2712-vdec.c
new file mode 100644
index 000000000000..55c64ee8cc91
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt2712-vdec.c
@@ -0,0 +1,94 @@
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk-provider.h>
16#include <linux/platform_device.h>
17
18#include "clk-mtk.h"
19#include "clk-gate.h"
20
21#include <dt-bindings/clock/mt2712-clk.h>
22
23static const struct mtk_gate_regs vdec0_cg_regs = {
24 .set_ofs = 0x0,
25 .clr_ofs = 0x4,
26 .sta_ofs = 0x0,
27};
28
29static const struct mtk_gate_regs vdec1_cg_regs = {
30 .set_ofs = 0x8,
31 .clr_ofs = 0xc,
32 .sta_ofs = 0x8,
33};
34
35#define GATE_VDEC0(_id, _name, _parent, _shift) { \
36 .id = _id, \
37 .name = _name, \
38 .parent_name = _parent, \
39 .regs = &vdec0_cg_regs, \
40 .shift = _shift, \
41 .ops = &mtk_clk_gate_ops_setclr_inv, \
42 }
43
44#define GATE_VDEC1(_id, _name, _parent, _shift) { \
45 .id = _id, \
46 .name = _name, \
47 .parent_name = _parent, \
48 .regs = &vdec1_cg_regs, \
49 .shift = _shift, \
50 .ops = &mtk_clk_gate_ops_setclr_inv, \
51 }
52
53static const struct mtk_gate vdec_clks[] = {
54 /* VDEC0 */
55 GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
56 /* VDEC1 */
57 GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "vdec_sel", 0),
58 GATE_VDEC1(CLK_VDEC_IMGRZ_CKEN, "vdec_imgrz_cken", "vdec_sel", 1),
59};
60
61static int clk_mt2712_vdec_probe(struct platform_device *pdev)
62{
63 struct clk_onecell_data *clk_data;
64 int r;
65 struct device_node *node = pdev->dev.of_node;
66
67 clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
68
69 mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
70 clk_data);
71
72 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
73
74 if (r != 0)
75 pr_err("%s(): could not register clock provider: %d\n",
76 __func__, r);
77
78 return r;
79}
80
81static const struct of_device_id of_match_clk_mt2712_vdec[] = {
82 { .compatible = "mediatek,mt2712-vdecsys", },
83 {}
84};
85
86static struct platform_driver clk_mt2712_vdec_drv = {
87 .probe = clk_mt2712_vdec_probe,
88 .driver = {
89 .name = "clk-mt2712-vdec",
90 .of_match_table = of_match_clk_mt2712_vdec,
91 },
92};
93
94builtin_platform_driver(clk_mt2712_vdec_drv);
diff --git a/drivers/clk/mediatek/clk-mt2712-venc.c b/drivers/clk/mediatek/clk-mt2712-venc.c
new file mode 100644
index 000000000000..ccbfe98777c8
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt2712-venc.c
@@ -0,0 +1,77 @@
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk-provider.h>
16#include <linux/platform_device.h>
17
18#include "clk-mtk.h"
19#include "clk-gate.h"
20
21#include <dt-bindings/clock/mt2712-clk.h>
22
23static const struct mtk_gate_regs venc_cg_regs = {
24 .set_ofs = 0x4,
25 .clr_ofs = 0x8,
26 .sta_ofs = 0x0,
27};
28
29#define GATE_VENC(_id, _name, _parent, _shift) { \
30 .id = _id, \
31 .name = _name, \
32 .parent_name = _parent, \
33 .regs = &venc_cg_regs, \
34 .shift = _shift, \
35 .ops = &mtk_clk_gate_ops_setclr_inv, \
36 }
37
38static const struct mtk_gate venc_clks[] = {
39 GATE_VENC(CLK_VENC_SMI_COMMON_CON, "venc_smi", "mm_sel", 0),
40 GATE_VENC(CLK_VENC_VENC, "venc_venc", "venc_sel", 4),
41 GATE_VENC(CLK_VENC_SMI_LARB6, "venc_smi_larb6", "jpgdec_sel", 12),
42};
43
44static int clk_mt2712_venc_probe(struct platform_device *pdev)
45{
46 struct clk_onecell_data *clk_data;
47 int r;
48 struct device_node *node = pdev->dev.of_node;
49
50 clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
51
52 mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
53 clk_data);
54
55 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
56
57 if (r != 0)
58 pr_err("%s(): could not register clock provider: %d\n",
59 __func__, r);
60
61 return r;
62}
63
64static const struct of_device_id of_match_clk_mt2712_venc[] = {
65 { .compatible = "mediatek,mt2712-vencsys", },
66 {}
67};
68
69static struct platform_driver clk_mt2712_venc_drv = {
70 .probe = clk_mt2712_venc_probe,
71 .driver = {
72 .name = "clk-mt2712-venc",
73 .of_match_table = of_match_clk_mt2712_venc,
74 },
75};
76
77builtin_platform_driver(clk_mt2712_venc_drv);
diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
new file mode 100644
index 000000000000..498d13799388
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -0,0 +1,1435 @@
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/mfd/syscon.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_device.h>
21#include <linux/platform_device.h>
22#include <linux/slab.h>
23
24#include "clk-mtk.h"
25#include "clk-gate.h"
26
27#include <dt-bindings/clock/mt2712-clk.h>
28
29static DEFINE_SPINLOCK(mt2712_clk_lock);
30
31static const struct mtk_fixed_clk top_fixed_clks[] = {
32 FIXED_CLK(CLK_TOP_VPLL3_DPIX, "vpll3_dpix", NULL, 200000000),
33 FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", NULL, 200000000),
34 FIXED_CLK(CLK_TOP_LTEPLL_FS26M, "ltepll_fs26m", NULL, 26000000),
35 FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 350000000),
36 FIXED_CLK(CLK_TOP_DSI0_LNTC, "dsi0_lntc", NULL, 143000000),
37 FIXED_CLK(CLK_TOP_DSI1_LNTC, "dsi1_lntc", NULL, 143000000),
38 FIXED_CLK(CLK_TOP_LVDSTX3_CLKDIG_CTS, "lvdstx3", NULL, 140000000),
39 FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx", NULL, 140000000),
40 FIXED_CLK(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", NULL, 32768),
41 FIXED_CLK(CLK_TOP_CLKRTC_INT, "clkrtc_int", NULL, 32747),
42 FIXED_CLK(CLK_TOP_CSI0, "csi0", NULL, 26000000),
43 FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000),
44};
45
46static const struct mtk_fixed_factor top_early_divs[] = {
47 FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1,
48 1),
49 FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1,
50 2),
51};
52
53static const struct mtk_fixed_factor top_divs[] = {
54 FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1,
55 1),
56 FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1,
57 2),
58 FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1,
59 3),
60 FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1,
61 1),
62 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1,
63 1),
64 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
65 2),
66 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1,
67 2),
68 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1,
69 4),
70 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1,
71 8),
72 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1,
73 16),
74 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1,
75 3),
76 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1,
77 2),
78 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1,
79 4),
80 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1,
81 5),
82 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1,
83 2),
84 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1,
85 4),
86 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1,
87 7),
88 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1,
89 2),
90 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1,
91 4),
92 FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1,
93 1),
94 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1,
95 7),
96 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1,
97 26),
98 FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1,
99 52),
100 FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1,
101 104),
102 FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1,
103 208),
104 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
105 2),
106 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1,
107 2),
108 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1,
109 4),
110 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1,
111 8),
112 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1,
113 3),
114 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1,
115 2),
116 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1,
117 4),
118 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1,
119 8),
120 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1,
121 5),
122 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1,
123 2),
124 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1,
125 4),
126 FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1,
127 8),
128 FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1,
129 1),
130 FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1,
131 1),
132 FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1,
133 1),
134 FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1,
135 1),
136 FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1,
137 1),
138 FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1,
139 1),
140 FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1,
141 1),
142 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1,
143 2),
144 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1,
145 4),
146 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1,
147 8),
148 FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1,
149 16),
150 FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1,
151 1),
152 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1,
153 2),
154 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1,
155 4),
156 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1,
157 8),
158 FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1,
159 16),
160 FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1,
161 1),
162 FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1,
163 2),
164 FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1,
165 4),
166 FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1,
167 8),
168 FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1,
169 1),
170 FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1,
171 2),
172 FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1,
173 4),
174 FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1,
175 8),
176 FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1,
177 1),
178 FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1,
179 1),
180 FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1,
181 1),
182 FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1,
183 2),
184 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1,
185 1),
186 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1,
187 2),
188 FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1,
189 1),
190 FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1,
191 2),
192 FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1,
193 1),
194 FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1,
195 2),
196 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1,
197 1),
198 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
199 2),
200 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1,
201 4),
202 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1,
203 8),
204 FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1,
205 1),
206 FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1,
207 2),
208 FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1,
209 4),
210 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1,
211 1),
212 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1,
213 2),
214 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1,
215 4),
216 FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1,
217 1),
218 FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1,
219 2),
220 FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1,
221 4),
222 FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1,
223 4),
224};
225
226static const char * const axi_parents[] = {
227 "clk26m",
228 "syspll1_d2",
229 "syspll_d5",
230 "syspll1_d4",
231 "univpll_d5",
232 "univpll2_d2",
233 "msdcpll2_ck"
234};
235
236static const char * const mem_parents[] = {
237 "clk26m",
238 "dmpll_ck"
239};
240
241static const char * const mm_parents[] = {
242 "clk26m",
243 "vencpll_ck",
244 "syspll_d3",
245 "syspll1_d2",
246 "syspll_d5",
247 "syspll1_d4",
248 "univpll1_d2",
249 "univpll2_d2"
250};
251
252static const char * const pwm_parents[] = {
253 "clk26m",
254 "univpll2_d4",
255 "univpll3_d2",
256 "univpll1_d4"
257};
258
259static const char * const vdec_parents[] = {
260 "clk26m",
261 "vcodecpll_ck",
262 "tvdpll_429m",
263 "univpll_d3",
264 "vencpll_ck",
265 "syspll_d3",
266 "univpll1_d2",
267 "mmpll_d2",
268 "syspll3_d2",
269 "tvdpll_ck"
270};
271
272static const char * const venc_parents[] = {
273 "clk26m",
274 "univpll1_d2",
275 "mmpll_d2",
276 "tvdpll_d2",
277 "syspll1_d2",
278 "univpll_d5",
279 "vcodecpll_d2",
280 "univpll2_d2",
281 "syspll3_d2"
282};
283
284static const char * const mfg_parents[] = {
285 "clk26m",
286 "mmpll_ck",
287 "univpll_d3",
288 "clk26m",
289 "clk26m",
290 "clk26m",
291 "clk26m",
292 "clk26m",
293 "clk26m",
294 "syspll_d3",
295 "syspll1_d2",
296 "syspll_d5",
297 "univpll_d3",
298 "univpll1_d2",
299 "univpll_d5",
300 "univpll2_d2"
301};
302
303static const char * const camtg_parents[] = {
304 "clk26m",
305 "univpll_d52",
306 "univpll_d208",
307 "univpll_d104",
308 "clk26m_d2",
309 "univpll_d26",
310 "univpll2_d8",
311 "syspll3_d4",
312 "syspll3_d2",
313 "univpll1_d4",
314 "univpll2_d2"
315};
316
317static const char * const uart_parents[] = {
318 "clk26m",
319 "univpll2_d8"
320};
321
322static const char * const spi_parents[] = {
323 "clk26m",
324 "univpll2_d4",
325 "univpll1_d4",
326 "univpll2_d2",
327 "univpll3_d2",
328 "univpll1_d8"
329};
330
331static const char * const usb20_parents[] = {
332 "clk26m",
333 "univpll1_d8",
334 "univpll3_d4"
335};
336
337static const char * const usb30_parents[] = {
338 "clk26m",
339 "univpll3_d2",
340 "univpll3_d4",
341 "univpll2_d4"
342};
343
344static const char * const msdc50_0_h_parents[] = {
345 "clk26m",
346 "syspll1_d2",
347 "syspll2_d2",
348 "syspll4_d2",
349 "univpll_d5",
350 "univpll1_d4"
351};
352
353static const char * const msdc50_0_parents[] = {
354 "clk26m",
355 "msdcpll_ck",
356 "msdcpll_d2",
357 "univpll1_d4",
358 "syspll2_d2",
359 "msdcpll_d4",
360 "vencpll_d2",
361 "univpll1_d2",
362 "msdcpll2_ck",
363 "msdcpll2_d2",
364 "msdcpll2_d4"
365};
366
367static const char * const msdc30_1_parents[] = {
368 "clk26m",
369 "univpll2_d2",
370 "msdcpll_d2",
371 "univpll1_d4",
372 "syspll2_d2",
373 "univpll_d7",
374 "vencpll_d2"
375};
376
377static const char * const msdc30_3_parents[] = {
378 "clk26m",
379 "msdcpll2_ck",
380 "msdcpll2_d2",
381 "univpll2_d2",
382 "msdcpll2_d4",
383 "univpll1_d4",
384 "syspll2_d2",
385 "syspll_d7",
386 "univpll_d7",
387 "vencpll_d2",
388 "msdcpll_ck",
389 "msdcpll_d2",
390 "msdcpll_d4"
391};
392
393static const char * const audio_parents[] = {
394 "clk26m",
395 "syspll3_d4",
396 "syspll4_d4",
397 "syspll1_d16"
398};
399
400static const char * const aud_intbus_parents[] = {
401 "clk26m",
402 "syspll1_d4",
403 "syspll4_d2",
404 "univpll3_d2",
405 "univpll2_d8",
406 "syspll3_d2",
407 "syspll3_d4"
408};
409
410static const char * const pmicspi_parents[] = {
411 "clk26m",
412 "syspll1_d8",
413 "syspll3_d4",
414 "syspll1_d16",
415 "univpll3_d4",
416 "univpll_d26",
417 "syspll3_d4"
418};
419
420static const char * const dpilvds1_parents[] = {
421 "clk26m",
422 "lvdspll2_ck",
423 "lvdspll2_d2",
424 "lvdspll2_d4",
425 "lvdspll2_d8",
426 "clkfpc"
427};
428
429static const char * const atb_parents[] = {
430 "clk26m",
431 "syspll1_d2",
432 "univpll_d5",
433 "syspll_d5"
434};
435
436static const char * const nr_parents[] = {
437 "clk26m",
438 "univpll1_d4",
439 "syspll2_d2",
440 "syspll1_d4",
441 "univpll1_d8",
442 "univpll3_d2",
443 "univpll2_d2",
444 "syspll_d5"
445};
446
447static const char * const nfi2x_parents[] = {
448 "clk26m",
449 "syspll4_d4",
450 "univpll3_d4",
451 "univpll1_d8",
452 "syspll2_d4",
453 "univpll3_d2",
454 "syspll_d7",
455 "syspll2_d2",
456 "univpll2_d2",
457 "syspll_d5",
458 "syspll1_d2"
459};
460
461static const char * const irda_parents[] = {
462 "clk26m",
463 "univpll2_d4",
464 "syspll2_d4",
465 "univpll2_d8"
466};
467
468static const char * const cci400_parents[] = {
469 "clk26m",
470 "vencpll_ck",
471 "armca35pll_600m",
472 "armca35pll_400m",
473 "univpll_d2",
474 "syspll_d2",
475 "msdcpll_ck",
476 "univpll_d3"
477};
478
479static const char * const aud_1_parents[] = {
480 "clk26m",
481 "apll1_ck",
482 "univpll2_d4",
483 "univpll2_d8"
484};
485
486static const char * const aud_2_parents[] = {
487 "clk26m",
488 "apll2_ck",
489 "univpll2_d4",
490 "univpll2_d8"
491};
492
493static const char * const mem_mfg_parents[] = {
494 "clk26m",
495 "mmpll_ck",
496 "univpll_d3"
497};
498
499static const char * const axi_mfg_parents[] = {
500 "clk26m",
501 "axi_sel",
502 "univpll_d5"
503};
504
505static const char * const scam_parents[] = {
506 "clk26m",
507 "syspll3_d2",
508 "univpll2_d4",
509 "syspll2_d4"
510};
511
512static const char * const nfiecc_parents[] = {
513 "clk26m",
514 "nfi2x_sel",
515 "syspll_d7",
516 "syspll2_d2",
517 "univpll2_d2",
518 "univpll_d5",
519 "syspll1_d2"
520};
521
522static const char * const pe2_mac_p0_parents[] = {
523 "clk26m",
524 "syspll1_d8",
525 "syspll4_d2",
526 "syspll2_d4",
527 "univpll2_d4",
528 "syspll3_d2"
529};
530
531static const char * const dpilvds_parents[] = {
532 "clk26m",
533 "lvdspll_ck",
534 "lvdspll_d2",
535 "lvdspll_d4",
536 "lvdspll_d8",
537 "clkfpc"
538};
539
540static const char * const hdcp_parents[] = {
541 "clk26m",
542 "syspll4_d2",
543 "syspll3_d4",
544 "univpll2_d4"
545};
546
547static const char * const hdcp_24m_parents[] = {
548 "clk26m",
549 "univpll_d26",
550 "univpll_d52",
551 "univpll2_d8"
552};
553
554static const char * const rtc_parents[] = {
555 "clkrtc_int",
556 "clkrtc_ext",
557 "clk26m",
558 "univpll3_d8"
559};
560
561static const char * const spinor_parents[] = {
562 "clk26m",
563 "clk26m_d2",
564 "syspll4_d4",
565 "univpll2_d8",
566 "univpll3_d4",
567 "syspll4_d2",
568 "syspll2_d4",
569 "univpll2_d4",
570 "etherpll_125m",
571 "syspll1_d4"
572};
573
574static const char * const apll_parents[] = {
575 "clk26m",
576 "apll1_ck",
577 "apll1_d2",
578 "apll1_d4",
579 "apll1_d8",
580 "apll1_d16",
581 "apll2_ck",
582 "apll2_d2",
583 "apll2_d4",
584 "apll2_d8",
585 "apll2_d16",
586 "clk26m",
587 "clk26m"
588};
589
590static const char * const a1sys_hp_parents[] = {
591 "clk26m",
592 "apll1_ck",
593 "apll1_d2",
594 "apll1_d4",
595 "apll1_d8"
596};
597
598static const char * const a2sys_hp_parents[] = {
599 "clk26m",
600 "apll2_ck",
601 "apll2_d2",
602 "apll2_d4",
603 "apll2_d8"
604};
605
606static const char * const asm_l_parents[] = {
607 "clk26m",
608 "univpll2_d4",
609 "univpll2_d2",
610 "syspll_d5"
611};
612
613static const char * const i2so1_parents[] = {
614 "clk26m",
615 "apll1_ck",
616 "apll2_ck"
617};
618
619static const char * const ether_125m_parents[] = {
620 "clk26m",
621 "etherpll_125m",
622 "univpll3_d2"
623};
624
625static const char * const ether_50m_parents[] = {
626 "clk26m",
627 "etherpll_50m",
628 "univpll_d26",
629 "univpll3_d4"
630};
631
632static const char * const jpgdec_parents[] = {
633 "clk26m",
634 "univpll_d3",
635 "tvdpll_429m",
636 "vencpll_ck",
637 "syspll_d3",
638 "vcodecpll_ck",
639 "univpll1_d2",
640 "armca35pll_400m",
641 "tvdpll_429m_d2",
642 "tvdpll_429m_d4"
643};
644
645static const char * const spislv_parents[] = {
646 "clk26m",
647 "univpll2_d4",
648 "univpll1_d4",
649 "univpll2_d2",
650 "univpll3_d2",
651 "univpll1_d8",
652 "univpll1_d2",
653 "univpll_d5"
654};
655
656static const char * const ether_parents[] = {
657 "clk26m",
658 "etherpll_50m",
659 "univpll_d26"
660};
661
662static const char * const di_parents[] = {
663 "clk26m",
664 "tvdpll_d2",
665 "tvdpll_d4",
666 "tvdpll_d8",
667 "vencpll_ck",
668 "vencpll_d2",
669 "cvbs",
670 "cvbs_d2"
671};
672
673static const char * const tvd_parents[] = {
674 "clk26m",
675 "cvbs_d2",
676 "univpll2_d8"
677};
678
679static const char * const i2c_parents[] = {
680 "clk26m",
681 "univpll_d26",
682 "univpll2_d4",
683 "univpll3_d2",
684 "univpll1_d4"
685};
686
687static const char * const msdc0p_aes_parents[] = {
688 "clk26m",
689 "msdcpll_ck",
690 "univpll_d3",
691 "vcodecpll_ck"
692};
693
694static const char * const cmsys_parents[] = {
695 "clk26m",
696 "univpll_d3",
697 "syspll_d3",
698 "syspll1_d2",
699 "syspll2_d2"
700};
701
702static const char * const gcpu_parents[] = {
703 "clk26m",
704 "syspll_d3",
705 "syspll1_d2",
706 "univpll1_d2",
707 "univpll_d5",
708 "univpll3_d2",
709 "univpll_d3"
710};
711
712static const char * const aud_apll1_parents[] = {
713 "apll1",
714 "clkaud_ext_i_1"
715};
716
717static const char * const aud_apll2_parents[] = {
718 "apll2",
719 "clkaud_ext_i_2"
720};
721
722static const char * const audull_vtx_parents[] = {
723 "d2a_ulclk_6p5m",
724 "clkaud_ext_i_0"
725};
726
727static struct mtk_composite top_muxes[] = {
728 /* CLK_CFG_0 */
729 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3,
730 7, CLK_IS_CRITICAL),
731 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,
732 15, CLK_IS_CRITICAL),
733 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel",
734 mm_parents, 0x040, 24, 3, 31),
735 /* CLK_CFG_1 */
736 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel",
737 pwm_parents, 0x050, 0, 2, 7),
738 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel",
739 vdec_parents, 0x050, 8, 4, 15),
740 MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel",
741 venc_parents, 0x050, 16, 4, 23),
742 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel",
743 mfg_parents, 0x050, 24, 4, 31),
744 /* CLK_CFG_2 */
745 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel",
746 camtg_parents, 0x060, 0, 4, 7),
747 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel",
748 uart_parents, 0x060, 8, 1, 15),
749 MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel",
750 spi_parents, 0x060, 16, 3, 23),
751 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel",
752 usb20_parents, 0x060, 24, 2, 31),
753 /* CLK_CFG_3 */
754 MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel",
755 usb30_parents, 0x070, 0, 2, 7),
756 MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel",
757 msdc50_0_h_parents, 0x070, 8, 3, 15),
758 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
759 msdc50_0_parents, 0x070, 16, 4, 23),
760 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
761 msdc30_1_parents, 0x070, 24, 3, 31),
762 /* CLK_CFG_4 */
763 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
764 msdc30_1_parents, 0x080, 0, 3, 7),
765 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel",
766 msdc30_3_parents, 0x080, 8, 4, 15),
767 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel",
768 audio_parents, 0x080, 16, 2, 23),
769 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
770 aud_intbus_parents, 0x080, 24, 3, 31),
771 /* CLK_CFG_5 */
772 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel",
773 pmicspi_parents, 0x090, 0, 3, 7),
774 MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel",
775 dpilvds1_parents, 0x090, 8, 3, 15),
776 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel",
777 atb_parents, 0x090, 16, 2, 23),
778 MUX_GATE(CLK_TOP_NR_SEL, "nr_sel",
779 nr_parents, 0x090, 24, 3, 31),
780 /* CLK_CFG_6 */
781 MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel",
782 nfi2x_parents, 0x0a0, 0, 4, 7),
783 MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel",
784 irda_parents, 0x0a0, 8, 2, 15),
785 MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel",
786 cci400_parents, 0x0a0, 16, 3, 23),
787 MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel",
788 aud_1_parents, 0x0a0, 24, 2, 31),
789 /* CLK_CFG_7 */
790 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel",
791 aud_2_parents, 0x0b0, 0, 2, 7),
792 MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel",
793 mem_mfg_parents, 0x0b0, 8, 2, 15),
794 MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel",
795 axi_mfg_parents, 0x0b0, 16, 2, 23),
796 MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel",
797 scam_parents, 0x0b0, 24, 2, 31),
798 /* CLK_CFG_8 */
799 MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel",
800 nfiecc_parents, 0x0c0, 0, 3, 7),
801 MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel",
802 pe2_mac_p0_parents, 0x0c0, 8, 3, 15),
803 MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel",
804 pe2_mac_p0_parents, 0x0c0, 16, 3, 23),
805 MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel",
806 dpilvds_parents, 0x0c0, 24, 3, 31),
807 /* CLK_CFG_9 */
808 MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel",
809 msdc50_0_h_parents, 0x0d0, 0, 3, 7),
810 MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel",
811 hdcp_parents, 0x0d0, 8, 2, 15),
812 MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel",
813 hdcp_24m_parents, 0x0d0, 16, 2, 23),
814 MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x0d0, 24, 2,
815 31, CLK_IS_CRITICAL),
816 /* CLK_CFG_10 */
817 MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel",
818 spinor_parents, 0x500, 0, 4, 7),
819 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel",
820 apll_parents, 0x500, 8, 4, 15),
821 MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel",
822 apll_parents, 0x500, 16, 4, 23),
823 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel",
824 a1sys_hp_parents, 0x500, 24, 3, 31),
825 /* CLK_CFG_11 */
826 MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel",
827 a2sys_hp_parents, 0x510, 0, 3, 7),
828 MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel",
829 asm_l_parents, 0x510, 8, 2, 15),
830 MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel",
831 asm_l_parents, 0x510, 16, 2, 23),
832 MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel",
833 asm_l_parents, 0x510, 24, 2, 31),
834 /* CLK_CFG_12 */
835 MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel",
836 i2so1_parents, 0x520, 0, 2, 7),
837 MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel",
838 i2so1_parents, 0x520, 8, 2, 15),
839 MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel",
840 i2so1_parents, 0x520, 16, 2, 23),
841 MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel",
842 i2so1_parents, 0x520, 24, 2, 31),
843 /* CLK_CFG_13 */
844 MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel",
845 i2so1_parents, 0x530, 0, 2, 7),
846 MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel",
847 i2so1_parents, 0x530, 8, 2, 15),
848 MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel",
849 i2so1_parents, 0x530, 16, 2, 23),
850 MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel",
851 i2so1_parents, 0x530, 24, 2, 31),
852 /* CLK_CFG_14 */
853 MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel",
854 ether_125m_parents, 0x540, 0, 2, 7),
855 MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel",
856 ether_50m_parents, 0x540, 8, 2, 15),
857 MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel",
858 jpgdec_parents, 0x540, 16, 4, 23),
859 MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel",
860 spislv_parents, 0x540, 24, 3, 31),
861 /* CLK_CFG_15 */
862 MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel",
863 ether_parents, 0x550, 0, 2, 7),
864 MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel",
865 camtg_parents, 0x550, 8, 4, 15),
866 MUX_GATE(CLK_TOP_DI_SEL, "di_sel",
867 di_parents, 0x550, 16, 3, 23),
868 MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel",
869 tvd_parents, 0x550, 24, 2, 31),
870 /* CLK_CFG_16 */
871 MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel",
872 i2c_parents, 0x560, 0, 3, 7),
873 MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel",
874 pwm_parents, 0x560, 8, 2, 15),
875 MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel",
876 msdc0p_aes_parents, 0x560, 16, 2, 23),
877 MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel",
878 cmsys_parents, 0x560, 24, 3, 31),
879 /* CLK_CFG_17 */
880 MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel",
881 gcpu_parents, 0x570, 0, 3, 7),
882 /* CLK_AUDDIV_4 */
883 MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel",
884 aud_apll1_parents, 0x134, 0, 1),
885 MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel",
886 aud_apll2_parents, 0x134, 1, 1),
887 MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel",
888 audull_vtx_parents, 0x134, 31, 1),
889};
890
891static const char * const mcu_mp0_parents[] = {
892 "clk26m",
893 "armca35pll_ck",
894 "f_mp0_pll1_ck",
895 "f_mp0_pll2_ck"
896};
897
898static const char * const mcu_mp2_parents[] = {
899 "clk26m",
900 "armca72pll_ck",
901 "f_big_pll1_ck",
902 "f_big_pll2_ck"
903};
904
905static const char * const mcu_bus_parents[] = {
906 "clk26m",
907 "cci400_sel",
908 "f_bus_pll1_ck",
909 "f_bus_pll2_ck"
910};
911
912static struct mtk_composite mcu_muxes[] = {
913 /* mp0_pll_divider_cfg */
914 MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0,
915 9, 2, -1, CLK_IS_CRITICAL),
916 /* mp2_pll_divider_cfg */
917 MUX_GATE_FLAGS(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8,
918 9, 2, -1, CLK_IS_CRITICAL),
919 /* bus_pll_divider_cfg */
920 MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0,
921 9, 2, -1, CLK_IS_CRITICAL),
922};
923
924static const struct mtk_clk_divider top_adj_divs[] = {
925 DIV_ADJ(CLK_TOP_APLL_DIV0, "apll_div0", "i2so1_sel", 0x124, 0, 8),
926 DIV_ADJ(CLK_TOP_APLL_DIV1, "apll_div1", "i2so2_sel", 0x124, 8, 8),
927 DIV_ADJ(CLK_TOP_APLL_DIV2, "apll_div2", "i2so3_sel", 0x124, 16, 8),
928 DIV_ADJ(CLK_TOP_APLL_DIV3, "apll_div3", "tdmo0_sel", 0x124, 24, 8),
929 DIV_ADJ(CLK_TOP_APLL_DIV4, "apll_div4", "tdmo1_sel", 0x128, 0, 8),
930 DIV_ADJ(CLK_TOP_APLL_DIV5, "apll_div5", "i2si1_sel", 0x128, 8, 8),
931 DIV_ADJ(CLK_TOP_APLL_DIV6, "apll_div6", "i2si2_sel", 0x128, 16, 8),
932 DIV_ADJ(CLK_TOP_APLL_DIV7, "apll_div7", "i2si3_sel", 0x128, 24, 8),
933};
934
935static const struct mtk_gate_regs top_cg_regs = {
936 .set_ofs = 0x120,
937 .clr_ofs = 0x120,
938 .sta_ofs = 0x120,
939};
940
941#define GATE_TOP(_id, _name, _parent, _shift) { \
942 .id = _id, \
943 .name = _name, \
944 .parent_name = _parent, \
945 .regs = &top_cg_regs, \
946 .shift = _shift, \
947 .ops = &mtk_clk_gate_ops_no_setclr, \
948 }
949
950static const struct mtk_gate top_clks[] = {
951 GATE_TOP(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0),
952 GATE_TOP(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1),
953 GATE_TOP(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2),
954 GATE_TOP(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3),
955 GATE_TOP(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4),
956 GATE_TOP(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5),
957 GATE_TOP(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6),
958 GATE_TOP(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7),
959};
960
961static const struct mtk_gate_regs infra_cg_regs = {
962 .set_ofs = 0x40,
963 .clr_ofs = 0x44,
964 .sta_ofs = 0x40,
965};
966
967#define GATE_INFRA(_id, _name, _parent, _shift) { \
968 .id = _id, \
969 .name = _name, \
970 .parent_name = _parent, \
971 .regs = &infra_cg_regs, \
972 .shift = _shift, \
973 .ops = &mtk_clk_gate_ops_setclr, \
974 }
975
976static const struct mtk_gate infra_clks[] = {
977 GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
978 GATE_INFRA(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
979 GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
980 GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
981 GATE_INFRA(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 24),
982 GATE_INFRA(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spislv_sel", 25),
983 GATE_INFRA(CLK_INFRA_AO_UART5, "infra_ao_uart5", "axi_sel", 26),
984};
985
986static const struct mtk_gate_regs peri0_cg_regs = {
987 .set_ofs = 0x8,
988 .clr_ofs = 0x10,
989 .sta_ofs = 0x18,
990};
991
992static const struct mtk_gate_regs peri1_cg_regs = {
993 .set_ofs = 0xc,
994 .clr_ofs = 0x14,
995 .sta_ofs = 0x1c,
996};
997
998static const struct mtk_gate_regs peri2_cg_regs = {
999 .set_ofs = 0x42c,
1000 .clr_ofs = 0x42c,
1001 .sta_ofs = 0x42c,
1002};
1003
1004#define GATE_PERI0(_id, _name, _parent, _shift) { \
1005 .id = _id, \
1006 .name = _name, \
1007 .parent_name = _parent, \
1008 .regs = &peri0_cg_regs, \
1009 .shift = _shift, \
1010 .ops = &mtk_clk_gate_ops_setclr, \
1011 }
1012
1013#define GATE_PERI1(_id, _name, _parent, _shift) { \
1014 .id = _id, \
1015 .name = _name, \
1016 .parent_name = _parent, \
1017 .regs = &peri1_cg_regs, \
1018 .shift = _shift, \
1019 .ops = &mtk_clk_gate_ops_setclr, \
1020 }
1021
1022#define GATE_PERI2(_id, _name, _parent, _shift) { \
1023 .id = _id, \
1024 .name = _name, \
1025 .parent_name = _parent, \
1026 .regs = &peri2_cg_regs, \
1027 .shift = _shift, \
1028 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
1029 }
1030
1031static const struct mtk_gate peri_clks[] = {
1032 /* PERI0 */
1033 GATE_PERI0(CLK_PERI_NFI, "per_nfi",
1034 "axi_sel", 0),
1035 GATE_PERI0(CLK_PERI_THERM, "per_therm",
1036 "axi_sel", 1),
1037 GATE_PERI0(CLK_PERI_PWM0, "per_pwm0",
1038 "pwm_sel", 2),
1039 GATE_PERI0(CLK_PERI_PWM1, "per_pwm1",
1040 "pwm_sel", 3),
1041 GATE_PERI0(CLK_PERI_PWM2, "per_pwm2",
1042 "pwm_sel", 4),
1043 GATE_PERI0(CLK_PERI_PWM3, "per_pwm3",
1044 "pwm_sel", 5),
1045 GATE_PERI0(CLK_PERI_PWM4, "per_pwm4",
1046 "pwm_sel", 6),
1047 GATE_PERI0(CLK_PERI_PWM5, "per_pwm5",
1048 "pwm_sel", 7),
1049 GATE_PERI0(CLK_PERI_PWM6, "per_pwm6",
1050 "pwm_sel", 8),
1051 GATE_PERI0(CLK_PERI_PWM7, "per_pwm7",
1052 "pwm_sel", 9),
1053 GATE_PERI0(CLK_PERI_PWM, "per_pwm",
1054 "pwm_sel", 10),
1055 GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma",
1056 "axi_sel", 13),
1057 GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0",
1058 "msdc50_0_sel", 14),
1059 GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1",
1060 "msdc30_1_sel", 15),
1061 GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2",
1062 "msdc30_2_sel", 16),
1063 GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3",
1064 "msdc30_3_sel", 17),
1065 GATE_PERI0(CLK_PERI_UART0, "per_uart0",
1066 "uart_sel", 20),
1067 GATE_PERI0(CLK_PERI_UART1, "per_uart1",
1068 "uart_sel", 21),
1069 GATE_PERI0(CLK_PERI_UART2, "per_uart2",
1070 "uart_sel", 22),
1071 GATE_PERI0(CLK_PERI_UART3, "per_uart3",
1072 "uart_sel", 23),
1073 GATE_PERI0(CLK_PERI_I2C0, "per_i2c0",
1074 "axi_sel", 24),
1075 GATE_PERI0(CLK_PERI_I2C1, "per_i2c1",
1076 "axi_sel", 25),
1077 GATE_PERI0(CLK_PERI_I2C2, "per_i2c2",
1078 "axi_sel", 26),
1079 GATE_PERI0(CLK_PERI_I2C3, "per_i2c3",
1080 "axi_sel", 27),
1081 GATE_PERI0(CLK_PERI_I2C4, "per_i2c4",
1082 "axi_sel", 28),
1083 GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc",
1084 "ltepll_fs26m", 29),
1085 GATE_PERI0(CLK_PERI_SPI0, "per_spi0",
1086 "spi_sel", 30),
1087 /* PERI1 */
1088 GATE_PERI1(CLK_PERI_SPI, "per_spi",
1089 "spinor_sel", 1),
1090 GATE_PERI1(CLK_PERI_I2C5, "per_i2c5",
1091 "axi_sel", 3),
1092 GATE_PERI1(CLK_PERI_SPI2, "per_spi2",
1093 "spi_sel", 5),
1094 GATE_PERI1(CLK_PERI_SPI3, "per_spi3",
1095 "spi_sel", 6),
1096 GATE_PERI1(CLK_PERI_SPI5, "per_spi5",
1097 "spi_sel", 8),
1098 GATE_PERI1(CLK_PERI_UART4, "per_uart4",
1099 "uart_sel", 9),
1100 GATE_PERI1(CLK_PERI_SFLASH, "per_sflash",
1101 "uart_sel", 11),
1102 GATE_PERI1(CLK_PERI_GMAC, "per_gmac",
1103 "uart_sel", 12),
1104 GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0",
1105 "uart_sel", 14),
1106 GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1",
1107 "uart_sel", 15),
1108 GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk",
1109 "uart_sel", 16),
1110 /* PERI2 */
1111 GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en",
1112 "msdc50_0_sel", 0),
1113 GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en",
1114 "msdc30_1_sel", 1),
1115 GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en",
1116 "msdc30_2_sel", 2),
1117 GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en",
1118 "msdc30_3_sel", 3),
1119 GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h",
1120 "msdc50_0_h_sel", 4),
1121 GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h",
1122 "msdc50_3_h_sel", 5),
1123};
1124
1125#define MT2712_PLL_FMAX (3000UL * MHZ)
1126
1127#define CON0_MT2712_RST_BAR BIT(24)
1128
1129#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
1130 _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
1131 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1132 _div_table) { \
1133 .id = _id, \
1134 .name = _name, \
1135 .reg = _reg, \
1136 .pwr_reg = _pwr_reg, \
1137 .en_mask = _en_mask, \
1138 .flags = _flags, \
1139 .rst_bar_mask = CON0_MT2712_RST_BAR, \
1140 .fmax = MT2712_PLL_FMAX, \
1141 .pcwbits = _pcwbits, \
1142 .pd_reg = _pd_reg, \
1143 .pd_shift = _pd_shift, \
1144 .tuner_reg = _tuner_reg, \
1145 .tuner_en_reg = _tuner_en_reg, \
1146 .tuner_en_bit = _tuner_en_bit, \
1147 .pcw_reg = _pcw_reg, \
1148 .pcw_shift = _pcw_shift, \
1149 .div_table = _div_table, \
1150 }
1151
1152#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
1153 _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg, \
1154 _tuner_en_bit, _pcw_reg, _pcw_shift) \
1155 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1156 _pcwbits, _pd_reg, _pd_shift, _tuner_reg, \
1157 _tuner_en_reg, _tuner_en_bit, _pcw_reg, \
1158 _pcw_shift, NULL)
1159
1160static const struct mtk_pll_div_table armca35pll_div_table[] = {
1161 { .div = 0, .freq = MT2712_PLL_FMAX },
1162 { .div = 1, .freq = 1202500000 },
1163 { .div = 2, .freq = 500500000 },
1164 { .div = 3, .freq = 315250000 },
1165 { .div = 4, .freq = 157625000 },
1166 { } /* sentinel */
1167};
1168
1169static const struct mtk_pll_div_table armca72pll_div_table[] = {
1170 { .div = 0, .freq = MT2712_PLL_FMAX },
1171 { .div = 1, .freq = 994500000 },
1172 { .div = 2, .freq = 520000000 },
1173 { .div = 3, .freq = 315250000 },
1174 { .div = 4, .freq = 157625000 },
1175 { } /* sentinel */
1176};
1177
1178static const struct mtk_pll_div_table mmpll_div_table[] = {
1179 { .div = 0, .freq = MT2712_PLL_FMAX },
1180 { .div = 1, .freq = 1001000000 },
1181 { .div = 2, .freq = 601250000 },
1182 { .div = 3, .freq = 250250000 },
1183 { .div = 4, .freq = 125125000 },
1184 { } /* sentinel */
1185};
1186
1187static const struct mtk_pll_data plls[] = {
1188 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000101,
1189 HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
1190 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000101,
1191 HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
1192 PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000101,
1193 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
1194 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000101,
1195 0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
1196 PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000101,
1197 0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
1198 PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000101,
1199 0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
1200 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000101,
1201 0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
1202 PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000101,
1203 0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
1204 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000101,
1205 0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
1206 PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000101,
1207 0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
1208 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000101,
1209 0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
1210 PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000101,
1211 0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0,
1212 mmpll_div_table),
1213 PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000101,
1214 HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0,
1215 armca35pll_div_table),
1216 PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000101,
1217 0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0,
1218 armca72pll_div_table),
1219 PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000101,
1220 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
1221};
1222
1223static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
1224{
1225 struct clk_onecell_data *clk_data;
1226 int r;
1227 struct device_node *node = pdev->dev.of_node;
1228
1229 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1230
1231 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1232
1233 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1234
1235 if (r != 0)
1236 pr_err("%s(): could not register clock provider: %d\n",
1237 __func__, r);
1238
1239 return r;
1240}
1241
1242static struct clk_onecell_data *top_clk_data;
1243
1244static void clk_mt2712_top_init_early(struct device_node *node)
1245{
1246 int r, i;
1247
1248 if (!top_clk_data) {
1249 top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1250
1251 for (i = 0; i < CLK_TOP_NR_CLK; i++)
1252 top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
1253 }
1254
1255 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
1256 top_clk_data);
1257
1258 r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
1259 if (r)
1260 pr_err("%s(): could not register clock provider: %d\n",
1261 __func__, r);
1262}
1263
1264CLK_OF_DECLARE_DRIVER(mt2712_topckgen, "mediatek,mt2712-topckgen",
1265 clk_mt2712_top_init_early);
1266
1267static int clk_mt2712_top_probe(struct platform_device *pdev)
1268{
1269 int r, i;
1270 struct device_node *node = pdev->dev.of_node;
1271 void __iomem *base;
1272 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1273
1274 base = devm_ioremap_resource(&pdev->dev, res);
1275 if (IS_ERR(base)) {
1276 pr_err("%s(): ioremap failed\n", __func__);
1277 return PTR_ERR(base);
1278 }
1279
1280 if (!top_clk_data) {
1281 top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1282 } else {
1283 for (i = 0; i < CLK_TOP_NR_CLK; i++) {
1284 if (top_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
1285 top_clk_data->clks[i] = ERR_PTR(-ENOENT);
1286 }
1287 }
1288
1289 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1290 top_clk_data);
1291 mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
1292 top_clk_data);
1293 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1294 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
1295 &mt2712_clk_lock, top_clk_data);
1296 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
1297 &mt2712_clk_lock, top_clk_data);
1298 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
1299 top_clk_data);
1300
1301 r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
1302
1303 if (r != 0)
1304 pr_err("%s(): could not register clock provider: %d\n",
1305 __func__, r);
1306
1307 return r;
1308}
1309
1310static int clk_mt2712_infra_probe(struct platform_device *pdev)
1311{
1312 struct clk_onecell_data *clk_data;
1313 int r;
1314 struct device_node *node = pdev->dev.of_node;
1315
1316 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1317
1318 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
1319 clk_data);
1320
1321 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1322
1323 if (r != 0)
1324 pr_err("%s(): could not register clock provider: %d\n",
1325 __func__, r);
1326
1327 mtk_register_reset_controller(node, 2, 0x30);
1328
1329 return r;
1330}
1331
1332static int clk_mt2712_peri_probe(struct platform_device *pdev)
1333{
1334 struct clk_onecell_data *clk_data;
1335 int r;
1336 struct device_node *node = pdev->dev.of_node;
1337
1338 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
1339
1340 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
1341 clk_data);
1342
1343 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1344
1345 if (r != 0)
1346 pr_err("%s(): could not register clock provider: %d\n",
1347 __func__, r);
1348
1349 mtk_register_reset_controller(node, 2, 0);
1350
1351 return r;
1352}
1353
1354static int clk_mt2712_mcu_probe(struct platform_device *pdev)
1355{
1356 struct clk_onecell_data *clk_data;
1357 int r;
1358 struct device_node *node = pdev->dev.of_node;
1359 void __iomem *base;
1360 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1361
1362 base = devm_ioremap_resource(&pdev->dev, res);
1363 if (IS_ERR(base)) {
1364 pr_err("%s(): ioremap failed\n", __func__);
1365 return PTR_ERR(base);
1366 }
1367
1368 clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
1369
1370 mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
1371 &mt2712_clk_lock, clk_data);
1372
1373 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1374
1375 if (r != 0)
1376 pr_err("%s(): could not register clock provider: %d\n",
1377 __func__, r);
1378
1379 return r;
1380}
1381
1382static const struct of_device_id of_match_clk_mt2712[] = {
1383 {
1384 .compatible = "mediatek,mt2712-apmixedsys",
1385 .data = clk_mt2712_apmixed_probe,
1386 }, {
1387 .compatible = "mediatek,mt2712-topckgen",
1388 .data = clk_mt2712_top_probe,
1389 }, {
1390 .compatible = "mediatek,mt2712-infracfg",
1391 .data = clk_mt2712_infra_probe,
1392 }, {
1393 .compatible = "mediatek,mt2712-pericfg",
1394 .data = clk_mt2712_peri_probe,
1395 }, {
1396 .compatible = "mediatek,mt2712-mcucfg",
1397 .data = clk_mt2712_mcu_probe,
1398 }, {
1399 /* sentinel */
1400 }
1401};
1402
1403static int clk_mt2712_probe(struct platform_device *pdev)
1404{
1405 int (*clk_probe)(struct platform_device *);
1406 int r;
1407
1408 clk_probe = of_device_get_match_data(&pdev->dev);
1409 if (!clk_probe)
1410 return -EINVAL;
1411
1412 r = clk_probe(pdev);
1413 if (r != 0)
1414 dev_err(&pdev->dev,
1415 "could not register clock provider: %s: %d\n",
1416 pdev->name, r);
1417
1418 return r;
1419}
1420
1421static struct platform_driver clk_mt2712_drv = {
1422 .probe = clk_mt2712_probe,
1423 .driver = {
1424 .name = "clk-mt2712",
1425 .owner = THIS_MODULE,
1426 .of_match_table = of_match_clk_mt2712,
1427 },
1428};
1429
1430static int __init clk_mt2712_init(void)
1431{
1432 return platform_driver_register(&clk_mt2712_drv);
1433}
1434
1435arch_initcall(clk_mt2712_init);
diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/clk-mt7622-aud.c
new file mode 100644
index 000000000000..fad7d9fc53ba
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7622-aud.c
@@ -0,0 +1,195 @@
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Chen Zhong <chen.zhong@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk-provider.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/of_device.h>
20#include <linux/platform_device.h>
21
22#include "clk-mtk.h"
23#include "clk-gate.h"
24
25#include <dt-bindings/clock/mt7622-clk.h>
26
27#define GATE_AUDIO0(_id, _name, _parent, _shift) { \
28 .id = _id, \
29 .name = _name, \
30 .parent_name = _parent, \
31 .regs = &audio0_cg_regs, \
32 .shift = _shift, \
33 .ops = &mtk_clk_gate_ops_no_setclr, \
34 }
35
36#define GATE_AUDIO1(_id, _name, _parent, _shift) { \
37 .id = _id, \
38 .name = _name, \
39 .parent_name = _parent, \
40 .regs = &audio1_cg_regs, \
41 .shift = _shift, \
42 .ops = &mtk_clk_gate_ops_no_setclr, \
43 }
44
45#define GATE_AUDIO2(_id, _name, _parent, _shift) { \
46 .id = _id, \
47 .name = _name, \
48 .parent_name = _parent, \
49 .regs = &audio2_cg_regs, \
50 .shift = _shift, \
51 .ops = &mtk_clk_gate_ops_no_setclr, \
52 }
53
54#define GATE_AUDIO3(_id, _name, _parent, _shift) { \
55 .id = _id, \
56 .name = _name, \
57 .parent_name = _parent, \
58 .regs = &audio3_cg_regs, \
59 .shift = _shift, \
60 .ops = &mtk_clk_gate_ops_no_setclr, \
61 }
62
63static const struct mtk_gate_regs audio0_cg_regs = {
64 .set_ofs = 0x0,
65 .clr_ofs = 0x0,
66 .sta_ofs = 0x0,
67};
68
69static const struct mtk_gate_regs audio1_cg_regs = {
70 .set_ofs = 0x10,
71 .clr_ofs = 0x10,
72 .sta_ofs = 0x10,
73};
74
75static const struct mtk_gate_regs audio2_cg_regs = {
76 .set_ofs = 0x14,
77 .clr_ofs = 0x14,
78 .sta_ofs = 0x14,
79};
80
81static const struct mtk_gate_regs audio3_cg_regs = {
82 .set_ofs = 0x634,
83 .clr_ofs = 0x634,
84 .sta_ofs = 0x634,
85};
86
87static const struct mtk_gate audio_clks[] = {
88 /* AUDIO0 */
89 GATE_AUDIO0(CLK_AUDIO_AFE, "audio_afe", "rtc", 2),
90 GATE_AUDIO0(CLK_AUDIO_HDMI, "audio_hdmi", "apll1_ck_sel", 20),
91 GATE_AUDIO0(CLK_AUDIO_SPDF, "audio_spdf", "apll1_ck_sel", 21),
92 GATE_AUDIO0(CLK_AUDIO_APLL, "audio_apll", "apll1_ck_sel", 23),
93 /* AUDIO1 */
94 GATE_AUDIO1(CLK_AUDIO_I2SIN1, "audio_i2sin1", "a1sys_hp_sel", 0),
95 GATE_AUDIO1(CLK_AUDIO_I2SIN2, "audio_i2sin2", "a1sys_hp_sel", 1),
96 GATE_AUDIO1(CLK_AUDIO_I2SIN3, "audio_i2sin3", "a1sys_hp_sel", 2),
97 GATE_AUDIO1(CLK_AUDIO_I2SIN4, "audio_i2sin4", "a1sys_hp_sel", 3),
98 GATE_AUDIO1(CLK_AUDIO_I2SO1, "audio_i2so1", "a1sys_hp_sel", 6),
99 GATE_AUDIO1(CLK_AUDIO_I2SO2, "audio_i2so2", "a1sys_hp_sel", 7),
100 GATE_AUDIO1(CLK_AUDIO_I2SO3, "audio_i2so3", "a1sys_hp_sel", 8),
101 GATE_AUDIO1(CLK_AUDIO_I2SO4, "audio_i2so4", "a1sys_hp_sel", 9),
102 GATE_AUDIO1(CLK_AUDIO_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
103 GATE_AUDIO1(CLK_AUDIO_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
104 GATE_AUDIO1(CLK_AUDIO_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
105 GATE_AUDIO1(CLK_AUDIO_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
106 GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20),
107 GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21),
108 GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22),
109 /* AUDIO2 */
110 GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0),
111 GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1),
112 GATE_AUDIO2(CLK_AUDIO_UL3, "audio_ul3", "a1sys_hp_sel", 2),
113 GATE_AUDIO2(CLK_AUDIO_UL4, "audio_ul4", "a1sys_hp_sel", 3),
114 GATE_AUDIO2(CLK_AUDIO_UL5, "audio_ul5", "a1sys_hp_sel", 4),
115 GATE_AUDIO2(CLK_AUDIO_UL6, "audio_ul6", "a1sys_hp_sel", 5),
116 GATE_AUDIO2(CLK_AUDIO_DL1, "audio_dl1", "a1sys_hp_sel", 6),
117 GATE_AUDIO2(CLK_AUDIO_DL2, "audio_dl2", "a1sys_hp_sel", 7),
118 GATE_AUDIO2(CLK_AUDIO_DL3, "audio_dl3", "a1sys_hp_sel", 8),
119 GATE_AUDIO2(CLK_AUDIO_DL4, "audio_dl4", "a1sys_hp_sel", 9),
120 GATE_AUDIO2(CLK_AUDIO_DL5, "audio_dl5", "a1sys_hp_sel", 10),
121 GATE_AUDIO2(CLK_AUDIO_DL6, "audio_dl6", "a1sys_hp_sel", 11),
122 GATE_AUDIO2(CLK_AUDIO_DLMCH, "audio_dlmch", "a1sys_hp_sel", 12),
123 GATE_AUDIO2(CLK_AUDIO_ARB1, "audio_arb1", "a1sys_hp_sel", 13),
124 GATE_AUDIO2(CLK_AUDIO_AWB, "audio_awb", "a1sys_hp_sel", 14),
125 GATE_AUDIO2(CLK_AUDIO_AWB2, "audio_awb2", "a1sys_hp_sel", 15),
126 GATE_AUDIO2(CLK_AUDIO_DAI, "audio_dai", "a1sys_hp_sel", 16),
127 GATE_AUDIO2(CLK_AUDIO_MOD, "audio_mod", "a1sys_hp_sel", 17),
128 /* AUDIO3 */
129 GATE_AUDIO3(CLK_AUDIO_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
130 GATE_AUDIO3(CLK_AUDIO_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
131 GATE_AUDIO3(CLK_AUDIO_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
132 GATE_AUDIO3(CLK_AUDIO_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
133 GATE_AUDIO3(CLK_AUDIO_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
134 GATE_AUDIO3(CLK_AUDIO_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
135 GATE_AUDIO3(CLK_AUDIO_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
136 GATE_AUDIO3(CLK_AUDIO_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
137 GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
138};
139
140static int clk_mt7622_audiosys_init(struct platform_device *pdev)
141{
142 struct clk_onecell_data *clk_data;
143 struct device_node *node = pdev->dev.of_node;
144 int r;
145
146 clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
147
148 mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
149 clk_data);
150
151 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
152 if (r)
153 dev_err(&pdev->dev,
154 "could not register clock provider: %s: %d\n",
155 pdev->name, r);
156
157 return r;
158}
159
160static const struct of_device_id of_match_clk_mt7622_aud[] = {
161 {
162 .compatible = "mediatek,mt7622-audsys",
163 .data = clk_mt7622_audiosys_init,
164 }, {
165 /* sentinel */
166 }
167};
168
169static int clk_mt7622_aud_probe(struct platform_device *pdev)
170{
171 int (*clk_init)(struct platform_device *);
172 int r;
173
174 clk_init = of_device_get_match_data(&pdev->dev);
175 if (!clk_init)
176 return -EINVAL;
177
178 r = clk_init(pdev);
179 if (r)
180 dev_err(&pdev->dev,
181 "could not register clock provider: %s: %d\n",
182 pdev->name, r);
183
184 return r;
185}
186
187static struct platform_driver clk_mt7622_aud_drv = {
188 .probe = clk_mt7622_aud_probe,
189 .driver = {
190 .name = "clk-mt7622-aud",
191 .of_match_table = of_match_clk_mt7622_aud,
192 },
193};
194
195builtin_platform_driver(clk_mt7622_aud_drv);
diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c
new file mode 100644
index 000000000000..6328127bbb3c
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
@@ -0,0 +1,156 @@
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Chen Zhong <chen.zhong@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk-provider.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/of_device.h>
20#include <linux/platform_device.h>
21
22#include "clk-mtk.h"
23#include "clk-gate.h"
24
25#include <dt-bindings/clock/mt7622-clk.h>
26
27#define GATE_ETH(_id, _name, _parent, _shift) { \
28 .id = _id, \
29 .name = _name, \
30 .parent_name = _parent, \
31 .regs = &eth_cg_regs, \
32 .shift = _shift, \
33 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
34 }
35
36static const struct mtk_gate_regs eth_cg_regs = {
37 .set_ofs = 0x30,
38 .clr_ofs = 0x30,
39 .sta_ofs = 0x30,
40};
41
42static const struct mtk_gate eth_clks[] = {
43 GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5),
44 GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6),
45 GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
46 GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
47 GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
48};
49
50static const struct mtk_gate_regs sgmii_cg_regs = {
51 .set_ofs = 0xE4,
52 .clr_ofs = 0xE4,
53 .sta_ofs = 0xE4,
54};
55
56#define GATE_SGMII(_id, _name, _parent, _shift) { \
57 .id = _id, \
58 .name = _name, \
59 .parent_name = _parent, \
60 .regs = &sgmii_cg_regs, \
61 .shift = _shift, \
62 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
63 }
64
65static const struct mtk_gate sgmii_clks[] = {
66 GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en",
67 "ssusb_tx250m", 2),
68 GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en",
69 "ssusb_eq_rx250m", 3),
70 GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
71 "ssusb_cdr_ref", 4),
72 GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
73 "ssusb_cdr_fb", 5),
74};
75
76static int clk_mt7622_ethsys_init(struct platform_device *pdev)
77{
78 struct clk_onecell_data *clk_data;
79 struct device_node *node = pdev->dev.of_node;
80 int r;
81
82 clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
83
84 mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
85 clk_data);
86
87 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
88 if (r)
89 dev_err(&pdev->dev,
90 "could not register clock provider: %s: %d\n",
91 pdev->name, r);
92
93 mtk_register_reset_controller(node, 1, 0x34);
94
95 return r;
96}
97
98static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
99{
100 struct clk_onecell_data *clk_data;
101 struct device_node *node = pdev->dev.of_node;
102 int r;
103
104 clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
105
106 mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
107 clk_data);
108
109 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
110 if (r)
111 dev_err(&pdev->dev,
112 "could not register clock provider: %s: %d\n",
113 pdev->name, r);
114
115 return r;
116}
117
118static const struct of_device_id of_match_clk_mt7622_eth[] = {
119 {
120 .compatible = "mediatek,mt7622-ethsys",
121 .data = clk_mt7622_ethsys_init,
122 }, {
123 .compatible = "mediatek,mt7622-sgmiisys",
124 .data = clk_mt7622_sgmiisys_init,
125 }, {
126 /* sentinel */
127 }
128};
129
130static int clk_mt7622_eth_probe(struct platform_device *pdev)
131{
132 int (*clk_init)(struct platform_device *);
133 int r;
134
135 clk_init = of_device_get_match_data(&pdev->dev);
136 if (!clk_init)
137 return -EINVAL;
138
139 r = clk_init(pdev);
140 if (r)
141 dev_err(&pdev->dev,
142 "could not register clock provider: %s: %d\n",
143 pdev->name, r);
144
145 return r;
146}
147
148static struct platform_driver clk_mt7622_eth_drv = {
149 .probe = clk_mt7622_eth_probe,
150 .driver = {
151 .name = "clk-mt7622-eth",
152 .of_match_table = of_match_clk_mt7622_eth,
153 },
154};
155
156builtin_platform_driver(clk_mt7622_eth_drv);
diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c
new file mode 100644
index 000000000000..a6e8534276c6
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
@@ -0,0 +1,169 @@
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Chen Zhong <chen.zhong@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk-provider.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/of_device.h>
20#include <linux/platform_device.h>
21
22#include "clk-mtk.h"
23#include "clk-gate.h"
24
25#include <dt-bindings/clock/mt7622-clk.h>
26
27#define GATE_PCIE(_id, _name, _parent, _shift) { \
28 .id = _id, \
29 .name = _name, \
30 .parent_name = _parent, \
31 .regs = &pcie_cg_regs, \
32 .shift = _shift, \
33 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
34 }
35
36#define GATE_SSUSB(_id, _name, _parent, _shift) { \
37 .id = _id, \
38 .name = _name, \
39 .parent_name = _parent, \
40 .regs = &ssusb_cg_regs, \
41 .shift = _shift, \
42 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
43 }
44
45static const struct mtk_gate_regs pcie_cg_regs = {
46 .set_ofs = 0x30,
47 .clr_ofs = 0x30,
48 .sta_ofs = 0x30,
49};
50
51static const struct mtk_gate_regs ssusb_cg_regs = {
52 .set_ofs = 0x30,
53 .clr_ofs = 0x30,
54 .sta_ofs = 0x30,
55};
56
57static const struct mtk_gate ssusb_clks[] = {
58 GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p",
59 "to_u2_phy_1p", 0),
60 GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1),
61 GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5),
62 GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6),
63 GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "axi_sel", 7),
64 GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "hif_sel", 8),
65};
66
67static const struct mtk_gate pcie_clks[] = {
68 GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12),
69 GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13),
70 GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "axi_sel", 14),
71 GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "hif_sel", 15),
72 GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16),
73 GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17),
74 GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18),
75 GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19),
76 GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "axi_sel", 20),
77 GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "hif_sel", 21),
78 GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22),
79 GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
80 GATE_PCIE(CLK_SATA_AHB_EN, "sata_ahb_en", "axi_sel", 26),
81 GATE_PCIE(CLK_SATA_AXI_EN, "sata_axi_en", "hif_sel", 27),
82 GATE_PCIE(CLK_SATA_ASIC_EN, "sata_asic_en", "sata_asic", 28),
83 GATE_PCIE(CLK_SATA_RBC_EN, "sata_rbc_en", "sata_rbc", 29),
84 GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30),
85};
86
87static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
88{
89 struct clk_onecell_data *clk_data;
90 struct device_node *node = pdev->dev.of_node;
91 int r;
92
93 clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
94
95 mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
96 clk_data);
97
98 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
99 if (r)
100 dev_err(&pdev->dev,
101 "could not register clock provider: %s: %d\n",
102 pdev->name, r);
103
104 mtk_register_reset_controller(node, 1, 0x34);
105
106 return r;
107}
108
109static int clk_mt7622_pciesys_init(struct platform_device *pdev)
110{
111 struct clk_onecell_data *clk_data;
112 struct device_node *node = pdev->dev.of_node;
113 int r;
114
115 clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
116
117 mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
118 clk_data);
119
120 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
121 if (r)
122 dev_err(&pdev->dev,
123 "could not register clock provider: %s: %d\n",
124 pdev->name, r);
125
126 mtk_register_reset_controller(node, 1, 0x34);
127
128 return r;
129}
130
131static const struct of_device_id of_match_clk_mt7622_hif[] = {
132 {
133 .compatible = "mediatek,mt7622-pciesys",
134 .data = clk_mt7622_pciesys_init,
135 }, {
136 .compatible = "mediatek,mt7622-ssusbsys",
137 .data = clk_mt7622_ssusbsys_init,
138 }, {
139 /* sentinel */
140 }
141};
142
143static int clk_mt7622_hif_probe(struct platform_device *pdev)
144{
145 int (*clk_init)(struct platform_device *);
146 int r;
147
148 clk_init = of_device_get_match_data(&pdev->dev);
149 if (!clk_init)
150 return -EINVAL;
151
152 r = clk_init(pdev);
153 if (r)
154 dev_err(&pdev->dev,
155 "could not register clock provider: %s: %d\n",
156 pdev->name, r);
157
158 return r;
159}
160
161static struct platform_driver clk_mt7622_hif_drv = {
162 .probe = clk_mt7622_hif_probe,
163 .driver = {
164 .name = "clk-mt7622-hif",
165 .of_match_table = of_match_clk_mt7622_hif,
166 },
167};
168
169builtin_platform_driver(clk_mt7622_hif_drv);
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
new file mode 100644
index 000000000000..92f7e32770c6
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -0,0 +1,780 @@
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Chen Zhong <chen.zhong@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk-provider.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/of_device.h>
20#include <linux/platform_device.h>
21
22#include "clk-mtk.h"
23#include "clk-gate.h"
24#include "clk-cpumux.h"
25
26#include <dt-bindings/clock/mt7622-clk.h>
27#include <linux/clk.h> /* for consumer */
28
29#define MT7622_PLL_FMAX (2500UL * MHZ)
30#define CON0_MT7622_RST_BAR BIT(27)
31
32#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
33 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
34 _pcw_shift, _div_table, _parent_name) { \
35 .id = _id, \
36 .name = _name, \
37 .reg = _reg, \
38 .pwr_reg = _pwr_reg, \
39 .en_mask = _en_mask, \
40 .flags = _flags, \
41 .rst_bar_mask = CON0_MT7622_RST_BAR, \
42 .fmax = MT7622_PLL_FMAX, \
43 .pcwbits = _pcwbits, \
44 .pd_reg = _pd_reg, \
45 .pd_shift = _pd_shift, \
46 .tuner_reg = _tuner_reg, \
47 .pcw_reg = _pcw_reg, \
48 .pcw_shift = _pcw_shift, \
49 .div_table = _div_table, \
50 .parent_name = _parent_name, \
51 }
52
53#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
54 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
55 _pcw_shift) \
56 PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
57 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
58 NULL, "clkxtal")
59
60#define GATE_APMIXED(_id, _name, _parent, _shift) { \
61 .id = _id, \
62 .name = _name, \
63 .parent_name = _parent, \
64 .regs = &apmixed_cg_regs, \
65 .shift = _shift, \
66 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
67 }
68
69#define GATE_INFRA(_id, _name, _parent, _shift) { \
70 .id = _id, \
71 .name = _name, \
72 .parent_name = _parent, \
73 .regs = &infra_cg_regs, \
74 .shift = _shift, \
75 .ops = &mtk_clk_gate_ops_setclr, \
76 }
77
78#define GATE_TOP0(_id, _name, _parent, _shift) { \
79 .id = _id, \
80 .name = _name, \
81 .parent_name = _parent, \
82 .regs = &top0_cg_regs, \
83 .shift = _shift, \
84 .ops = &mtk_clk_gate_ops_no_setclr, \
85 }
86
87#define GATE_TOP1(_id, _name, _parent, _shift) { \
88 .id = _id, \
89 .name = _name, \
90 .parent_name = _parent, \
91 .regs = &top1_cg_regs, \
92 .shift = _shift, \
93 .ops = &mtk_clk_gate_ops_no_setclr, \
94 }
95
96#define GATE_PERI0(_id, _name, _parent, _shift) { \
97 .id = _id, \
98 .name = _name, \
99 .parent_name = _parent, \
100 .regs = &peri0_cg_regs, \
101 .shift = _shift, \
102 .ops = &mtk_clk_gate_ops_setclr, \
103 }
104
105#define GATE_PERI1(_id, _name, _parent, _shift) { \
106 .id = _id, \
107 .name = _name, \
108 .parent_name = _parent, \
109 .regs = &peri1_cg_regs, \
110 .shift = _shift, \
111 .ops = &mtk_clk_gate_ops_setclr, \
112 }
113
114static DEFINE_SPINLOCK(mt7622_clk_lock);
115
116static const char * const infra_mux1_parents[] = {
117 "clkxtal",
118 "armpll",
119 "main_core_en",
120 "armpll"
121};
122
123static const char * const axi_parents[] = {
124 "clkxtal",
125 "syspll1_d2",
126 "syspll_d5",
127 "syspll1_d4",
128 "univpll_d5",
129 "univpll2_d2",
130 "univpll_d7"
131};
132
133static const char * const mem_parents[] = {
134 "clkxtal",
135 "dmpll_ck"
136};
137
138static const char * const ddrphycfg_parents[] = {
139 "clkxtal",
140 "syspll1_d8"
141};
142
143static const char * const eth_parents[] = {
144 "clkxtal",
145 "syspll1_d2",
146 "univpll1_d2",
147 "syspll1_d4",
148 "univpll_d5",
149 "clk_null",
150 "univpll_d7"
151};
152
153static const char * const pwm_parents[] = {
154 "clkxtal",
155 "univpll2_d4"
156};
157
158static const char * const f10m_ref_parents[] = {
159 "clkxtal",
160 "syspll4_d16"
161};
162
163static const char * const nfi_infra_parents[] = {
164 "clkxtal",
165 "clkxtal",
166 "clkxtal",
167 "clkxtal",
168 "clkxtal",
169 "clkxtal",
170 "clkxtal",
171 "clkxtal",
172 "univpll2_d8",
173 "syspll1_d8",
174 "univpll1_d8",
175 "syspll4_d2",
176 "univpll2_d4",
177 "univpll3_d2",
178 "syspll1_d4"
179};
180
181static const char * const flash_parents[] = {
182 "clkxtal",
183 "univpll_d80_d4",
184 "syspll2_d8",
185 "syspll3_d4",
186 "univpll3_d4",
187 "univpll1_d8",
188 "syspll2_d4",
189 "univpll2_d4"
190};
191
192static const char * const uart_parents[] = {
193 "clkxtal",
194 "univpll2_d8"
195};
196
197static const char * const spi0_parents[] = {
198 "clkxtal",
199 "syspll3_d2",
200 "clkxtal",
201 "syspll2_d4",
202 "syspll4_d2",
203 "univpll2_d4",
204 "univpll1_d8",
205 "clkxtal"
206};
207
208static const char * const spi1_parents[] = {
209 "clkxtal",
210 "syspll3_d2",
211 "clkxtal",
212 "syspll4_d4",
213 "syspll4_d2",
214 "univpll2_d4",
215 "univpll1_d8",
216 "clkxtal"
217};
218
219static const char * const msdc30_0_parents[] = {
220 "clkxtal",
221 "univpll2_d16",
222 "univ48m"
223};
224
225static const char * const a1sys_hp_parents[] = {
226 "clkxtal",
227 "aud1pll_ck",
228 "aud2pll_ck",
229 "clkxtal"
230};
231
232static const char * const intdir_parents[] = {
233 "clkxtal",
234 "syspll_d2",
235 "univpll_d2",
236 "sgmiipll_ck"
237};
238
239static const char * const aud_intbus_parents[] = {
240 "clkxtal",
241 "syspll1_d4",
242 "syspll4_d2",
243 "syspll3_d2"
244};
245
246static const char * const pmicspi_parents[] = {
247 "clkxtal",
248 "clk_null",
249 "clk_null",
250 "clk_null",
251 "clk_null",
252 "univpll2_d16"
253};
254
255static const char * const atb_parents[] = {
256 "clkxtal",
257 "syspll1_d2",
258 "syspll_d5"
259};
260
261static const char * const audio_parents[] = {
262 "clkxtal",
263 "syspll3_d4",
264 "syspll4_d4",
265 "univpll1_d16"
266};
267
268static const char * const usb20_parents[] = {
269 "clkxtal",
270 "univpll3_d4",
271 "syspll1_d8",
272 "clkxtal"
273};
274
275static const char * const aud1_parents[] = {
276 "clkxtal",
277 "aud1pll_ck"
278};
279
280static const char * const aud2_parents[] = {
281 "clkxtal",
282 "aud2pll_ck"
283};
284
285static const char * const asm_l_parents[] = {
286 "clkxtal",
287 "syspll_d5",
288 "univpll2_d2",
289 "univpll2_d4"
290};
291
292static const char * const apll1_ck_parents[] = {
293 "aud1_sel",
294 "aud2_sel"
295};
296
297static const char * const peribus_ck_parents[] = {
298 "syspll1_d8",
299 "syspll1_d4"
300};
301
302static const struct mtk_gate_regs apmixed_cg_regs = {
303 .set_ofs = 0x8,
304 .clr_ofs = 0x8,
305 .sta_ofs = 0x8,
306};
307
308static const struct mtk_gate_regs infra_cg_regs = {
309 .set_ofs = 0x40,
310 .clr_ofs = 0x44,
311 .sta_ofs = 0x48,
312};
313
314static const struct mtk_gate_regs top0_cg_regs = {
315 .set_ofs = 0x120,
316 .clr_ofs = 0x120,
317 .sta_ofs = 0x120,
318};
319
320static const struct mtk_gate_regs top1_cg_regs = {
321 .set_ofs = 0x128,
322 .clr_ofs = 0x128,
323 .sta_ofs = 0x128,
324};
325
326static const struct mtk_gate_regs peri0_cg_regs = {
327 .set_ofs = 0x8,
328 .clr_ofs = 0x10,
329 .sta_ofs = 0x18,
330};
331
332static const struct mtk_gate_regs peri1_cg_regs = {
333 .set_ofs = 0xC,
334 .clr_ofs = 0x14,
335 .sta_ofs = 0x1C,
336};
337
338static const struct mtk_pll_data plls[] = {
339 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
340 PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
341 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
342 HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
343 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
344 HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
345 PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
346 0, 21, 0x0300, 1, 0, 0x0304, 0),
347 PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
348 0, 21, 0x0314, 1, 0, 0x0318, 0),
349 PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000001,
350 0, 31, 0x0324, 1, 0, 0x0328, 0),
351 PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000001,
352 0, 31, 0x0334, 1, 0, 0x0338, 0),
353 PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000001,
354 0, 21, 0x0344, 1, 0, 0x0348, 0),
355 PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
356 0, 21, 0x0358, 1, 0, 0x035C, 0),
357};
358
359static const struct mtk_gate apmixed_clks[] = {
360 GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
361};
362
363static const struct mtk_gate infra_clks[] = {
364 GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),
365 GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),
366 GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),
367 GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),
368 GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),
369 GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),
370};
371
372static const struct mtk_fixed_clk top_fixed_clks[] = {
373 FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
374 31250000),
375 FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
376 31250000),
377 FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
378 125000000),
379 FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
380 125000000),
381 FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
382 250000000),
383 FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
384 250000000),
385 FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
386 33333333),
387 FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
388 50000000),
389 FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
390 50000000),
391 FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
392 50000000),
393};
394
395static const struct mtk_fixed_factor top_divs[] = {
396 FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
397 FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
398 FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
399 FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
400 FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
401 FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
402 FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
403 FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
404 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
405 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
406 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
407 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
408 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
409 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
410 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
411 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
412 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
413 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
414 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
415 FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
416 FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
417 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
418 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
419 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
420 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
421 FACTOR(CLK_TOP_UNIVPLL1_D16, "univpll1_d16", "univpll", 1, 32),
422 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
423 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
424 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
425 FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
426 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
427 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
428 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
429 FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
430 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
431 FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
432 FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
433 FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck", "sgmipll", 1, 1),
434 FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
435 FACTOR(CLK_TOP_AUD1PLL, "aud1pll_ck", "aud1pll", 1, 1),
436 FACTOR(CLK_TOP_AUD2PLL, "aud2pll_ck", "aud2pll", 1, 1),
437 FACTOR(CLK_TOP_AUD_I2S2_MCK, "aud_i2s2_mck", "i2s2_mck_sel", 1, 2),
438 FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "univpll2_d4", 1, 4),
439 FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1),
440 FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1),
441 FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
442};
443
444static const struct mtk_gate top_clks[] = {
445 /* TOP0 */
446 GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0),
447 GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1),
448 GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div",
449 2),
450 GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div",
451 3),
452 GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div",
453 4),
454 GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div",
455 5),
456
457 /* TOP1 */
458 GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0),
459 GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16),
460};
461
462static const struct mtk_clk_divider top_adj_divs[] = {
463 DIV_ADJ(CLK_TOP_APLL1_DIV, "apll1_ck_div", "apll1_ck_sel",
464 0x120, 24, 3),
465 DIV_ADJ(CLK_TOP_APLL2_DIV, "apll2_ck_div", "apll2_ck_sel",
466 0x120, 28, 3),
467 DIV_ADJ(CLK_TOP_I2S0_MCK_DIV, "i2s0_mck_div", "i2s0_mck_sel",
468 0x124, 0, 7),
469 DIV_ADJ(CLK_TOP_I2S1_MCK_DIV, "i2s1_mck_div", "i2s1_mck_sel",
470 0x124, 8, 7),
471 DIV_ADJ(CLK_TOP_I2S2_MCK_DIV, "i2s2_mck_div", "aud_i2s2_mck",
472 0x124, 16, 7),
473 DIV_ADJ(CLK_TOP_I2S3_MCK_DIV, "i2s3_mck_div", "i2s3_mck_sel",
474 0x124, 24, 7),
475 DIV_ADJ(CLK_TOP_A1SYS_HP_DIV, "a1sys_div", "a1sys_hp_sel",
476 0x128, 8, 7),
477 DIV_ADJ(CLK_TOP_A2SYS_HP_DIV, "a2sys_div", "a2sys_hp_sel",
478 0x128, 24, 7),
479};
480
481static const struct mtk_gate peri_clks[] = {
482 /* PERI0 */
483 GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1),
484 GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2),
485 GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3),
486 GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4),
487 GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5),
488 GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6),
489 GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7),
490 GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8),
491 GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9),
492 GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12),
493 GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13),
494 GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14),
495 GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17),
496 GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18),
497 GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19),
498 GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20),
499 GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21),
500 GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22),
501 GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23),
502 GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24),
503 GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25),
504 GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26),
505 GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27),
506 GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28),
507 GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29),
508 GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30),
509 GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31),
510
511 /* PERI1 */
512 GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1),
513 GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2),
514};
515
516static struct mtk_composite infra_muxes[] __initdata = {
517 MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents,
518 0x000, 2, 2),
519};
520
521static struct mtk_composite top_muxes[] = {
522 /* CLK_CFG_0 */
523 MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
524 0x040, 0, 3, 7),
525 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
526 0x040, 8, 1, 15),
527 MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
528 0x040, 16, 1, 23),
529 MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
530 0x040, 24, 3, 31),
531
532 /* CLK_CFG_1 */
533 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
534 0x050, 0, 2, 7),
535 MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
536 0x050, 8, 1, 15),
537 MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
538 0x050, 16, 4, 23),
539 MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
540 0x050, 24, 3, 31),
541
542 /* CLK_CFG_2 */
543 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
544 0x060, 0, 1, 7),
545 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
546 0x060, 8, 3, 15),
547 MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
548 0x060, 16, 3, 23),
549 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
550 0x060, 24, 3, 31),
551
552 /* CLK_CFG_3 */
553 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
554 0x070, 0, 3, 7),
555 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents,
556 0x070, 8, 3, 15),
557 MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
558 0x070, 16, 2, 23),
559 MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a1sys_hp_parents,
560 0x070, 24, 2, 31),
561
562 /* CLK_CFG_4 */
563 MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
564 0x080, 0, 2, 7),
565 MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
566 0x080, 8, 2, 15),
567 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
568 0x080, 16, 3, 23),
569 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
570 0x080, 24, 2, 31),
571
572 /* CLK_CFG_5 */
573 MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
574 0x090, 0, 2, 7),
575 MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents,
576 0x090, 8, 3, 15),
577 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
578 0x090, 16, 2, 23),
579 MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
580 0x090, 24, 2, 31),
581
582 /* CLK_CFG_6 */
583 MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
584 0x0A0, 0, 1, 7),
585 MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
586 0x0A0, 8, 1, 15),
587 MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", f10m_ref_parents,
588 0x0A0, 16, 1, 23),
589 MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents,
590 0x0A0, 24, 1, 31),
591
592 /* CLK_CFG_7 */
593 MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents,
594 0x0B0, 0, 2, 7),
595 MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents,
596 0x0B0, 8, 2, 15),
597 MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents,
598 0x0B0, 16, 2, 23),
599
600 /* CLK_AUDDIV_0 */
601 MUX(CLK_TOP_APLL1_SEL, "apll1_ck_sel", apll1_ck_parents,
602 0x120, 6, 1),
603 MUX(CLK_TOP_APLL2_SEL, "apll2_ck_sel", apll1_ck_parents,
604 0x120, 7, 1),
605 MUX(CLK_TOP_I2S0_MCK_SEL, "i2s0_mck_sel", apll1_ck_parents,
606 0x120, 8, 1),
607 MUX(CLK_TOP_I2S1_MCK_SEL, "i2s1_mck_sel", apll1_ck_parents,
608 0x120, 9, 1),
609 MUX(CLK_TOP_I2S2_MCK_SEL, "i2s2_mck_sel", apll1_ck_parents,
610 0x120, 10, 1),
611 MUX(CLK_TOP_I2S3_MCK_SEL, "i2s3_mck_sel", apll1_ck_parents,
612 0x120, 11, 1),
613};
614
615static struct mtk_composite peri_muxes[] = {
616 /* PERI_GLOBALCON_CKSEL */
617 MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
618};
619
620static int mtk_topckgen_init(struct platform_device *pdev)
621{
622 struct clk_onecell_data *clk_data;
623 void __iomem *base;
624 struct device_node *node = pdev->dev.of_node;
625 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
626
627 base = devm_ioremap_resource(&pdev->dev, res);
628 if (IS_ERR(base))
629 return PTR_ERR(base);
630
631 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
632
633 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
634 clk_data);
635
636 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
637 clk_data);
638
639 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
640 base, &mt7622_clk_lock, clk_data);
641
642 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
643 base, &mt7622_clk_lock, clk_data);
644
645 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
646 clk_data);
647
648 clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]);
649 clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]);
650 clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
651
652 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
653}
654
655static int __init mtk_infrasys_init(struct platform_device *pdev)
656{
657 struct device_node *node = pdev->dev.of_node;
658 struct clk_onecell_data *clk_data;
659 int r;
660
661 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
662
663 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
664 clk_data);
665
666 mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
667 clk_data);
668
669 r = of_clk_add_provider(node, of_clk_src_onecell_get,
670 clk_data);
671 if (r)
672 return r;
673
674 mtk_register_reset_controller(node, 1, 0x30);
675
676 return 0;
677}
678
679static int mtk_apmixedsys_init(struct platform_device *pdev)
680{
681 struct clk_onecell_data *clk_data;
682 struct device_node *node = pdev->dev.of_node;
683
684 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
685 if (!clk_data)
686 return -ENOMEM;
687
688 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
689 clk_data);
690
691 mtk_clk_register_gates(node, apmixed_clks,
692 ARRAY_SIZE(apmixed_clks), clk_data);
693
694 clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
695 clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]);
696
697 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
698}
699
700static int mtk_pericfg_init(struct platform_device *pdev)
701{
702 struct clk_onecell_data *clk_data;
703 void __iomem *base;
704 int r;
705 struct device_node *node = pdev->dev.of_node;
706 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
707
708 base = devm_ioremap_resource(&pdev->dev, res);
709 if (IS_ERR(base))
710 return PTR_ERR(base);
711
712 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
713
714 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
715 clk_data);
716
717 mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
718 &mt7622_clk_lock, clk_data);
719
720 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
721 if (r)
722 return r;
723
724 clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
725
726 mtk_register_reset_controller(node, 2, 0x0);
727
728 return 0;
729}
730
731static const struct of_device_id of_match_clk_mt7622[] = {
732 {
733 .compatible = "mediatek,mt7622-apmixedsys",
734 .data = mtk_apmixedsys_init,
735 }, {
736 .compatible = "mediatek,mt7622-infracfg",
737 .data = mtk_infrasys_init,
738 }, {
739 .compatible = "mediatek,mt7622-topckgen",
740 .data = mtk_topckgen_init,
741 }, {
742 .compatible = "mediatek,mt7622-pericfg",
743 .data = mtk_pericfg_init,
744 }, {
745 /* sentinel */
746 }
747};
748
749static int clk_mt7622_probe(struct platform_device *pdev)
750{
751 int (*clk_init)(struct platform_device *);
752 int r;
753
754 clk_init = of_device_get_match_data(&pdev->dev);
755 if (!clk_init)
756 return -EINVAL;
757
758 r = clk_init(pdev);
759 if (r)
760 dev_err(&pdev->dev,
761 "could not register clock provider: %s: %d\n",
762 pdev->name, r);
763
764 return r;
765}
766
767static struct platform_driver clk_mt7622_drv = {
768 .probe = clk_mt7622_probe,
769 .driver = {
770 .name = "clk-mt7622",
771 .of_match_table = of_match_clk_mt7622,
772 },
773};
774
775static int clk_mt7622_init(void)
776{
777 return platform_driver_register(&clk_mt7622_drv);
778}
779
780arch_initcall(clk_mt7622_init);
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index f5d6b70ce189..f10250dcece4 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -207,6 +207,8 @@ struct mtk_pll_data {
207 uint32_t en_mask; 207 uint32_t en_mask;
208 uint32_t pd_reg; 208 uint32_t pd_reg;
209 uint32_t tuner_reg; 209 uint32_t tuner_reg;
210 uint32_t tuner_en_reg;
211 uint8_t tuner_en_bit;
210 int pd_shift; 212 int pd_shift;
211 unsigned int flags; 213 unsigned int flags;
212 const struct clk_ops *ops; 214 const struct clk_ops *ops;
@@ -216,6 +218,7 @@ struct mtk_pll_data {
216 uint32_t pcw_reg; 218 uint32_t pcw_reg;
217 int pcw_shift; 219 int pcw_shift;
218 const struct mtk_pll_div_table *div_table; 220 const struct mtk_pll_div_table *div_table;
221 const char *parent_name;
219}; 222};
220 223
221void mtk_clk_register_plls(struct device_node *node, 224void mtk_clk_register_plls(struct device_node *node,
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index a409142e9346..f54e4015b0b1 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -47,6 +47,7 @@ struct mtk_clk_pll {
47 void __iomem *pd_addr; 47 void __iomem *pd_addr;
48 void __iomem *pwr_addr; 48 void __iomem *pwr_addr;
49 void __iomem *tuner_addr; 49 void __iomem *tuner_addr;
50 void __iomem *tuner_en_addr;
50 void __iomem *pcw_addr; 51 void __iomem *pcw_addr;
51 const struct mtk_pll_data *data; 52 const struct mtk_pll_data *data;
52}; 53};
@@ -227,7 +228,10 @@ static int mtk_pll_prepare(struct clk_hw *hw)
227 r |= pll->data->en_mask; 228 r |= pll->data->en_mask;
228 writel(r, pll->base_addr + REG_CON0); 229 writel(r, pll->base_addr + REG_CON0);
229 230
230 if (pll->tuner_addr) { 231 if (pll->tuner_en_addr) {
232 r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
233 writel(r, pll->tuner_en_addr);
234 } else if (pll->tuner_addr) {
231 r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN; 235 r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
232 writel(r, pll->tuner_addr); 236 writel(r, pll->tuner_addr);
233 } 237 }
@@ -254,7 +258,10 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
254 writel(r, pll->base_addr + REG_CON0); 258 writel(r, pll->base_addr + REG_CON0);
255 } 259 }
256 260
257 if (pll->tuner_addr) { 261 if (pll->tuner_en_addr) {
262 r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
263 writel(r, pll->tuner_en_addr);
264 } else if (pll->tuner_addr) {
258 r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN; 265 r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
259 writel(r, pll->tuner_addr); 266 writel(r, pll->tuner_addr);
260 } 267 }
@@ -297,13 +304,18 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
297 pll->pcw_addr = base + data->pcw_reg; 304 pll->pcw_addr = base + data->pcw_reg;
298 if (data->tuner_reg) 305 if (data->tuner_reg)
299 pll->tuner_addr = base + data->tuner_reg; 306 pll->tuner_addr = base + data->tuner_reg;
307 if (data->tuner_en_reg)
308 pll->tuner_en_addr = base + data->tuner_en_reg;
300 pll->hw.init = &init; 309 pll->hw.init = &init;
301 pll->data = data; 310 pll->data = data;
302 311
303 init.name = data->name; 312 init.name = data->name;
304 init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0; 313 init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
305 init.ops = &mtk_pll_ops; 314 init.ops = &mtk_pll_ops;
306 init.parent_names = &parent_name; 315 if (data->parent_name)
316 init.parent_names = &data->parent_name;
317 else
318 init.parent_names = &parent_name;
307 init.num_parents = 1; 319 init.num_parents = 1;
308 320
309 clk = clk_register(NULL, &pll->hw); 321 clk = clk_register(NULL, &pll->hw);
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index b2d1e8ed7152..ae385310e980 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -1131,6 +1131,253 @@ static struct clk_gate gxbb_sd_emmc_c_clk0 = {
1131 }, 1131 },
1132}; 1132};
1133 1133
1134/* VPU Clock */
1135
1136static u32 mux_table_vpu[] = {0, 1, 2, 3};
1137static const char * const gxbb_vpu_parent_names[] = {
1138 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1139};
1140
1141static struct clk_mux gxbb_vpu_0_sel = {
1142 .reg = (void *)HHI_VPU_CLK_CNTL,
1143 .mask = 0x3,
1144 .shift = 9,
1145 .lock = &clk_lock,
1146 .table = mux_table_vpu,
1147 .hw.init = &(struct clk_init_data){
1148 .name = "vpu_0_sel",
1149 .ops = &clk_mux_ops,
1150 /*
1151 * bits 9:10 selects from 4 possible parents:
1152 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1153 */
1154 .parent_names = gxbb_vpu_parent_names,
1155 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
1156 .flags = CLK_SET_RATE_NO_REPARENT,
1157 },
1158};
1159
1160static struct clk_divider gxbb_vpu_0_div = {
1161 .reg = (void *)HHI_VPU_CLK_CNTL,
1162 .shift = 0,
1163 .width = 7,
1164 .lock = &clk_lock,
1165 .hw.init = &(struct clk_init_data){
1166 .name = "vpu_0_div",
1167 .ops = &clk_divider_ops,
1168 .parent_names = (const char *[]){ "vpu_0_sel" },
1169 .num_parents = 1,
1170 .flags = CLK_SET_RATE_PARENT,
1171 },
1172};
1173
1174static struct clk_gate gxbb_vpu_0 = {
1175 .reg = (void *)HHI_VPU_CLK_CNTL,
1176 .bit_idx = 8,
1177 .lock = &clk_lock,
1178 .hw.init = &(struct clk_init_data) {
1179 .name = "vpu_0",
1180 .ops = &clk_gate_ops,
1181 .parent_names = (const char *[]){ "vpu_0_div" },
1182 .num_parents = 1,
1183 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1184 },
1185};
1186
1187static struct clk_mux gxbb_vpu_1_sel = {
1188 .reg = (void *)HHI_VPU_CLK_CNTL,
1189 .mask = 0x3,
1190 .shift = 25,
1191 .lock = &clk_lock,
1192 .table = mux_table_vpu,
1193 .hw.init = &(struct clk_init_data){
1194 .name = "vpu_1_sel",
1195 .ops = &clk_mux_ops,
1196 /*
1197 * bits 25:26 selects from 4 possible parents:
1198 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1199 */
1200 .parent_names = gxbb_vpu_parent_names,
1201 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
1202 .flags = CLK_SET_RATE_NO_REPARENT,
1203 },
1204};
1205
1206static struct clk_divider gxbb_vpu_1_div = {
1207 .reg = (void *)HHI_VPU_CLK_CNTL,
1208 .shift = 16,
1209 .width = 7,
1210 .lock = &clk_lock,
1211 .hw.init = &(struct clk_init_data){
1212 .name = "vpu_1_div",
1213 .ops = &clk_divider_ops,
1214 .parent_names = (const char *[]){ "vpu_1_sel" },
1215 .num_parents = 1,
1216 .flags = CLK_SET_RATE_PARENT,
1217 },
1218};
1219
1220static struct clk_gate gxbb_vpu_1 = {
1221 .reg = (void *)HHI_VPU_CLK_CNTL,
1222 .bit_idx = 24,
1223 .lock = &clk_lock,
1224 .hw.init = &(struct clk_init_data) {
1225 .name = "vpu_1",
1226 .ops = &clk_gate_ops,
1227 .parent_names = (const char *[]){ "vpu_1_div" },
1228 .num_parents = 1,
1229 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1230 },
1231};
1232
1233static struct clk_mux gxbb_vpu = {
1234 .reg = (void *)HHI_VPU_CLK_CNTL,
1235 .mask = 1,
1236 .shift = 31,
1237 .lock = &clk_lock,
1238 .hw.init = &(struct clk_init_data){
1239 .name = "vpu",
1240 .ops = &clk_mux_ops,
1241 /*
1242 * bit 31 selects from 2 possible parents:
1243 * vpu_0 or vpu_1
1244 */
1245 .parent_names = (const char *[]){ "vpu_0", "vpu_1" },
1246 .num_parents = 2,
1247 .flags = CLK_SET_RATE_NO_REPARENT,
1248 },
1249};
1250
1251/* VAPB Clock */
1252
1253static u32 mux_table_vapb[] = {0, 1, 2, 3};
1254static const char * const gxbb_vapb_parent_names[] = {
1255 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1256};
1257
1258static struct clk_mux gxbb_vapb_0_sel = {
1259 .reg = (void *)HHI_VAPBCLK_CNTL,
1260 .mask = 0x3,
1261 .shift = 9,
1262 .lock = &clk_lock,
1263 .table = mux_table_vapb,
1264 .hw.init = &(struct clk_init_data){
1265 .name = "vapb_0_sel",
1266 .ops = &clk_mux_ops,
1267 /*
1268 * bits 9:10 selects from 4 possible parents:
1269 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1270 */
1271 .parent_names = gxbb_vapb_parent_names,
1272 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
1273 .flags = CLK_SET_RATE_NO_REPARENT,
1274 },
1275};
1276
1277static struct clk_divider gxbb_vapb_0_div = {
1278 .reg = (void *)HHI_VAPBCLK_CNTL,
1279 .shift = 0,
1280 .width = 7,
1281 .lock = &clk_lock,
1282 .hw.init = &(struct clk_init_data){
1283 .name = "vapb_0_div",
1284 .ops = &clk_divider_ops,
1285 .parent_names = (const char *[]){ "vapb_0_sel" },
1286 .num_parents = 1,
1287 .flags = CLK_SET_RATE_PARENT,
1288 },
1289};
1290
1291static struct clk_gate gxbb_vapb_0 = {
1292 .reg = (void *)HHI_VAPBCLK_CNTL,
1293 .bit_idx = 8,
1294 .lock = &clk_lock,
1295 .hw.init = &(struct clk_init_data) {
1296 .name = "vapb_0",
1297 .ops = &clk_gate_ops,
1298 .parent_names = (const char *[]){ "vapb_0_div" },
1299 .num_parents = 1,
1300 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1301 },
1302};
1303
1304static struct clk_mux gxbb_vapb_1_sel = {
1305 .reg = (void *)HHI_VAPBCLK_CNTL,
1306 .mask = 0x3,
1307 .shift = 25,
1308 .lock = &clk_lock,
1309 .table = mux_table_vapb,
1310 .hw.init = &(struct clk_init_data){
1311 .name = "vapb_1_sel",
1312 .ops = &clk_mux_ops,
1313 /*
1314 * bits 25:26 selects from 4 possible parents:
1315 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1316 */
1317 .parent_names = gxbb_vapb_parent_names,
1318 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
1319 .flags = CLK_SET_RATE_NO_REPARENT,
1320 },
1321};
1322
1323static struct clk_divider gxbb_vapb_1_div = {
1324 .reg = (void *)HHI_VAPBCLK_CNTL,
1325 .shift = 16,
1326 .width = 7,
1327 .lock = &clk_lock,
1328 .hw.init = &(struct clk_init_data){
1329 .name = "vapb_1_div",
1330 .ops = &clk_divider_ops,
1331 .parent_names = (const char *[]){ "vapb_1_sel" },
1332 .num_parents = 1,
1333 .flags = CLK_SET_RATE_PARENT,
1334 },
1335};
1336
1337static struct clk_gate gxbb_vapb_1 = {
1338 .reg = (void *)HHI_VAPBCLK_CNTL,
1339 .bit_idx = 24,
1340 .lock = &clk_lock,
1341 .hw.init = &(struct clk_init_data) {
1342 .name = "vapb_1",
1343 .ops = &clk_gate_ops,
1344 .parent_names = (const char *[]){ "vapb_1_div" },
1345 .num_parents = 1,
1346 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1347 },
1348};
1349
1350static struct clk_mux gxbb_vapb_sel = {
1351 .reg = (void *)HHI_VAPBCLK_CNTL,
1352 .mask = 1,
1353 .shift = 31,
1354 .lock = &clk_lock,
1355 .hw.init = &(struct clk_init_data){
1356 .name = "vapb_sel",
1357 .ops = &clk_mux_ops,
1358 /*
1359 * bit 31 selects from 2 possible parents:
1360 * vapb_0 or vapb_1
1361 */
1362 .parent_names = (const char *[]){ "vapb_0", "vapb_1" },
1363 .num_parents = 2,
1364 .flags = CLK_SET_RATE_NO_REPARENT,
1365 },
1366};
1367
1368static struct clk_gate gxbb_vapb = {
1369 .reg = (void *)HHI_VAPBCLK_CNTL,
1370 .bit_idx = 30,
1371 .lock = &clk_lock,
1372 .hw.init = &(struct clk_init_data) {
1373 .name = "vapb",
1374 .ops = &clk_gate_ops,
1375 .parent_names = (const char *[]){ "vapb_sel" },
1376 .num_parents = 1,
1377 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1378 },
1379};
1380
1134/* Everything Else (EE) domain gates */ 1381/* Everything Else (EE) domain gates */
1135static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); 1382static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
1136static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); 1383static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -1349,6 +1596,21 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
1349 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 1596 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
1350 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 1597 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
1351 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 1598 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
1599 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
1600 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
1601 [CLKID_VPU_0] = &gxbb_vpu_0.hw,
1602 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
1603 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
1604 [CLKID_VPU_1] = &gxbb_vpu_1.hw,
1605 [CLKID_VPU] = &gxbb_vpu.hw,
1606 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
1607 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
1608 [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
1609 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
1610 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
1611 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
1612 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
1613 [CLKID_VAPB] = &gxbb_vapb.hw,
1352 [NR_CLKS] = NULL, 1614 [NR_CLKS] = NULL,
1353 }, 1615 },
1354 .num = NR_CLKS, 1616 .num = NR_CLKS,
@@ -1481,6 +1743,21 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
1481 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw, 1743 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
1482 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw, 1744 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
1483 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw, 1745 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
1746 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
1747 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
1748 [CLKID_VPU_0] = &gxbb_vpu_0.hw,
1749 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
1750 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
1751 [CLKID_VPU_1] = &gxbb_vpu_1.hw,
1752 [CLKID_VPU] = &gxbb_vpu.hw,
1753 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
1754 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
1755 [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
1756 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
1757 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
1758 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
1759 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
1760 [CLKID_VAPB] = &gxbb_vapb.hw,
1484 [NR_CLKS] = NULL, 1761 [NR_CLKS] = NULL,
1485 }, 1762 },
1486 .num = NR_CLKS, 1763 .num = NR_CLKS,
@@ -1600,6 +1877,11 @@ static struct clk_gate *const gxbb_clk_gates[] = {
1600 &gxbb_sd_emmc_a_clk0, 1877 &gxbb_sd_emmc_a_clk0,
1601 &gxbb_sd_emmc_b_clk0, 1878 &gxbb_sd_emmc_b_clk0,
1602 &gxbb_sd_emmc_c_clk0, 1879 &gxbb_sd_emmc_c_clk0,
1880 &gxbb_vpu_0,
1881 &gxbb_vpu_1,
1882 &gxbb_vapb_0,
1883 &gxbb_vapb_1,
1884 &gxbb_vapb,
1603}; 1885};
1604 1886
1605static struct clk_mux *const gxbb_clk_muxes[] = { 1887static struct clk_mux *const gxbb_clk_muxes[] = {
@@ -1615,6 +1897,12 @@ static struct clk_mux *const gxbb_clk_muxes[] = {
1615 &gxbb_sd_emmc_a_clk0_sel, 1897 &gxbb_sd_emmc_a_clk0_sel,
1616 &gxbb_sd_emmc_b_clk0_sel, 1898 &gxbb_sd_emmc_b_clk0_sel,
1617 &gxbb_sd_emmc_c_clk0_sel, 1899 &gxbb_sd_emmc_c_clk0_sel,
1900 &gxbb_vpu_0_sel,
1901 &gxbb_vpu_1_sel,
1902 &gxbb_vpu,
1903 &gxbb_vapb_0_sel,
1904 &gxbb_vapb_1_sel,
1905 &gxbb_vapb_sel,
1618}; 1906};
1619 1907
1620static struct clk_divider *const gxbb_clk_dividers[] = { 1908static struct clk_divider *const gxbb_clk_dividers[] = {
@@ -1627,6 +1915,10 @@ static struct clk_divider *const gxbb_clk_dividers[] = {
1627 &gxbb_sd_emmc_a_clk0_div, 1915 &gxbb_sd_emmc_a_clk0_div,
1628 &gxbb_sd_emmc_b_clk0_div, 1916 &gxbb_sd_emmc_b_clk0_div,
1629 &gxbb_sd_emmc_c_clk0_div, 1917 &gxbb_sd_emmc_c_clk0_div,
1918 &gxbb_vpu_0_div,
1919 &gxbb_vpu_1_div,
1920 &gxbb_vapb_0_div,
1921 &gxbb_vapb_1_div,
1630}; 1922};
1631 1923
1632static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = { 1924static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 5b1d4b374d1c..aee6fbba2004 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -190,8 +190,12 @@
190#define CLKID_SD_EMMC_B_CLK0_DIV 121 190#define CLKID_SD_EMMC_B_CLK0_DIV 121
191#define CLKID_SD_EMMC_C_CLK0_SEL 123 191#define CLKID_SD_EMMC_C_CLK0_SEL 123
192#define CLKID_SD_EMMC_C_CLK0_DIV 124 192#define CLKID_SD_EMMC_C_CLK0_DIV 124
193#define CLKID_VPU_0_DIV 127
194#define CLKID_VPU_1_DIV 130
195#define CLKID_VAPB_0_DIV 134
196#define CLKID_VAPB_1_DIV 137
193 197
194#define NR_CLKS 126 198#define NR_CLKS 141
195 199
196/* include the CLKIDs that have been made part of the DT binding */ 200/* include the CLKIDs that have been made part of the DT binding */
197#include <dt-bindings/clock/gxbb-clkc.h> 201#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/drivers/clk/mmp/clk-apbc.c b/drivers/clk/mmp/clk-apbc.c
index 4c717db05f2d..fb294ada0b03 100644
--- a/drivers/clk/mmp/clk-apbc.c
+++ b/drivers/clk/mmp/clk-apbc.c
@@ -114,7 +114,7 @@ static void clk_apbc_unprepare(struct clk_hw *hw)
114 spin_unlock_irqrestore(apbc->lock, flags); 114 spin_unlock_irqrestore(apbc->lock, flags);
115} 115}
116 116
117static struct clk_ops clk_apbc_ops = { 117static const struct clk_ops clk_apbc_ops = {
118 .prepare = clk_apbc_prepare, 118 .prepare = clk_apbc_prepare,
119 .unprepare = clk_apbc_unprepare, 119 .unprepare = clk_apbc_unprepare,
120}; 120};
diff --git a/drivers/clk/mmp/clk-apmu.c b/drivers/clk/mmp/clk-apmu.c
index 47b5542ce50f..b7ce8f52026e 100644
--- a/drivers/clk/mmp/clk-apmu.c
+++ b/drivers/clk/mmp/clk-apmu.c
@@ -60,7 +60,7 @@ static void clk_apmu_disable(struct clk_hw *hw)
60 spin_unlock_irqrestore(apmu->lock, flags); 60 spin_unlock_irqrestore(apmu->lock, flags);
61} 61}
62 62
63static struct clk_ops clk_apmu_ops = { 63static const struct clk_ops clk_apmu_ops = {
64 .enable = clk_apmu_enable, 64 .enable = clk_apmu_enable,
65 .disable = clk_apmu_disable, 65 .disable = clk_apmu_disable,
66}; 66};
diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c
index 584a9927993b..cb43d54735b0 100644
--- a/drivers/clk/mmp/clk-frac.c
+++ b/drivers/clk/mmp/clk-frac.c
@@ -149,7 +149,7 @@ static void clk_factor_init(struct clk_hw *hw)
149 spin_unlock_irqrestore(factor->lock, flags); 149 spin_unlock_irqrestore(factor->lock, flags);
150} 150}
151 151
152static struct clk_ops clk_factor_ops = { 152static const struct clk_ops clk_factor_ops = {
153 .recalc_rate = clk_factor_recalc_rate, 153 .recalc_rate = clk_factor_recalc_rate,
154 .round_rate = clk_factor_round_rate, 154 .round_rate = clk_factor_round_rate,
155 .set_rate = clk_factor_set_rate, 155 .set_rate = clk_factor_set_rate,
@@ -172,10 +172,8 @@ struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
172 } 172 }
173 173
174 factor = kzalloc(sizeof(*factor), GFP_KERNEL); 174 factor = kzalloc(sizeof(*factor), GFP_KERNEL);
175 if (!factor) { 175 if (!factor)
176 pr_err("%s: could not allocate factor clk\n", __func__);
177 return ERR_PTR(-ENOMEM); 176 return ERR_PTR(-ENOMEM);
178 }
179 177
180 /* struct clk_aux assignments */ 178 /* struct clk_aux assignments */
181 factor->base = base; 179 factor->base = base;
diff --git a/drivers/clk/mmp/clk-gate.c b/drivers/clk/mmp/clk-gate.c
index d20cd3431ac2..7355595c42e2 100644
--- a/drivers/clk/mmp/clk-gate.c
+++ b/drivers/clk/mmp/clk-gate.c
@@ -103,10 +103,8 @@ struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
103 103
104 /* allocate the gate */ 104 /* allocate the gate */
105 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 105 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
106 if (!gate) { 106 if (!gate)
107 pr_err("%s:%s could not allocate gate clk\n", __func__, name);
108 return ERR_PTR(-ENOMEM); 107 return ERR_PTR(-ENOMEM);
109 }
110 108
111 init.name = name; 109 init.name = name;
112 init.ops = &mmp_clk_gate_ops; 110 init.ops = &mmp_clk_gate_ops;
diff --git a/drivers/clk/mmp/clk-mix.c b/drivers/clk/mmp/clk-mix.c
index c554833cffc5..90814b2613c0 100644
--- a/drivers/clk/mmp/clk-mix.c
+++ b/drivers/clk/mmp/clk-mix.c
@@ -229,7 +229,7 @@ static int mmp_clk_mix_determine_rate(struct clk_hw *hw,
229 parent_rate = clk_hw_get_rate(parent); 229 parent_rate = clk_hw_get_rate(parent);
230 mix_rate = parent_rate / item->divisor; 230 mix_rate = parent_rate / item->divisor;
231 gap = abs(mix_rate - req->rate); 231 gap = abs(mix_rate - req->rate);
232 if (parent_best == NULL || gap < gap_best) { 232 if (!parent_best || gap < gap_best) {
233 parent_best = parent; 233 parent_best = parent;
234 parent_rate_best = parent_rate; 234 parent_rate_best = parent_rate;
235 mix_rate_best = mix_rate; 235 mix_rate_best = mix_rate;
@@ -247,7 +247,7 @@ static int mmp_clk_mix_determine_rate(struct clk_hw *hw,
247 div = _get_div(mix, j); 247 div = _get_div(mix, j);
248 mix_rate = parent_rate / div; 248 mix_rate = parent_rate / div;
249 gap = abs(mix_rate - req->rate); 249 gap = abs(mix_rate - req->rate);
250 if (parent_best == NULL || gap < gap_best) { 250 if (!parent_best || gap < gap_best) {
251 parent_best = parent; 251 parent_best = parent;
252 parent_rate_best = parent_rate; 252 parent_rate_best = parent_rate;
253 mix_rate_best = mix_rate; 253 mix_rate_best = mix_rate;
@@ -451,11 +451,8 @@ struct clk *mmp_clk_register_mix(struct device *dev,
451 size_t table_bytes; 451 size_t table_bytes;
452 452
453 mix = kzalloc(sizeof(*mix), GFP_KERNEL); 453 mix = kzalloc(sizeof(*mix), GFP_KERNEL);
454 if (!mix) { 454 if (!mix)
455 pr_err("%s:%s: could not allocate mmp mix clk\n",
456 __func__, name);
457 return ERR_PTR(-ENOMEM); 455 return ERR_PTR(-ENOMEM);
458 }
459 456
460 init.name = name; 457 init.name = name;
461 init.flags = flags | CLK_GET_RATE_NOCACHE; 458 init.flags = flags | CLK_GET_RATE_NOCACHE;
@@ -467,12 +464,9 @@ struct clk *mmp_clk_register_mix(struct device *dev,
467 if (config->table) { 464 if (config->table) {
468 table_bytes = sizeof(*config->table) * config->table_size; 465 table_bytes = sizeof(*config->table) * config->table_size;
469 mix->table = kmemdup(config->table, table_bytes, GFP_KERNEL); 466 mix->table = kmemdup(config->table, table_bytes, GFP_KERNEL);
470 if (!mix->table) { 467 if (!mix->table)
471 pr_err("%s:%s: could not allocate mmp mix table\n", 468 goto free_mix;
472 __func__, name); 469
473 kfree(mix);
474 return ERR_PTR(-ENOMEM);
475 }
476 mix->table_size = config->table_size; 470 mix->table_size = config->table_size;
477 } 471 }
478 472
@@ -481,11 +475,8 @@ struct clk *mmp_clk_register_mix(struct device *dev,
481 mix->mux_table = kmemdup(config->mux_table, table_bytes, 475 mix->mux_table = kmemdup(config->mux_table, table_bytes,
482 GFP_KERNEL); 476 GFP_KERNEL);
483 if (!mix->mux_table) { 477 if (!mix->mux_table) {
484 pr_err("%s:%s: could not allocate mmp mix mux-table\n",
485 __func__, name);
486 kfree(mix->table); 478 kfree(mix->table);
487 kfree(mix); 479 goto free_mix;
488 return ERR_PTR(-ENOMEM);
489 } 480 }
490 } 481 }
491 482
@@ -509,4 +500,8 @@ struct clk *mmp_clk_register_mix(struct device *dev,
509 } 500 }
510 501
511 return clk; 502 return clk;
503
504free_mix:
505 kfree(mix);
506 return ERR_PTR(-ENOMEM);
512} 507}
diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c
index 038023483b98..7460031714da 100644
--- a/drivers/clk/mmp/clk-mmp2.c
+++ b/drivers/clk/mmp/clk-mmp2.c
@@ -83,19 +83,19 @@ void __init mmp2_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
83 void __iomem *apbc_base; 83 void __iomem *apbc_base;
84 84
85 mpmu_base = ioremap(mpmu_phys, SZ_4K); 85 mpmu_base = ioremap(mpmu_phys, SZ_4K);
86 if (mpmu_base == NULL) { 86 if (!mpmu_base) {
87 pr_err("error to ioremap MPMU base\n"); 87 pr_err("error to ioremap MPMU base\n");
88 return; 88 return;
89 } 89 }
90 90
91 apmu_base = ioremap(apmu_phys, SZ_4K); 91 apmu_base = ioremap(apmu_phys, SZ_4K);
92 if (apmu_base == NULL) { 92 if (!apmu_base) {
93 pr_err("error to ioremap APMU base\n"); 93 pr_err("error to ioremap APMU base\n");
94 return; 94 return;
95 } 95 }
96 96
97 apbc_base = ioremap(apbc_phys, SZ_4K); 97 apbc_base = ioremap(apbc_phys, SZ_4K);
98 if (apbc_base == NULL) { 98 if (!apbc_base) {
99 pr_err("error to ioremap APBC base\n"); 99 pr_err("error to ioremap APBC base\n");
100 return; 100 return;
101 } 101 }
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c
index a9ef9209532a..8e2551ab8462 100644
--- a/drivers/clk/mmp/clk-pxa168.c
+++ b/drivers/clk/mmp/clk-pxa168.c
@@ -75,19 +75,19 @@ void __init pxa168_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
75 void __iomem *apbc_base; 75 void __iomem *apbc_base;
76 76
77 mpmu_base = ioremap(mpmu_phys, SZ_4K); 77 mpmu_base = ioremap(mpmu_phys, SZ_4K);
78 if (mpmu_base == NULL) { 78 if (!mpmu_base) {
79 pr_err("error to ioremap MPMU base\n"); 79 pr_err("error to ioremap MPMU base\n");
80 return; 80 return;
81 } 81 }
82 82
83 apmu_base = ioremap(apmu_phys, SZ_4K); 83 apmu_base = ioremap(apmu_phys, SZ_4K);
84 if (apmu_base == NULL) { 84 if (!apmu_base) {
85 pr_err("error to ioremap APMU base\n"); 85 pr_err("error to ioremap APMU base\n");
86 return; 86 return;
87 } 87 }
88 88
89 apbc_base = ioremap(apbc_phys, SZ_4K); 89 apbc_base = ioremap(apbc_phys, SZ_4K);
90 if (apbc_base == NULL) { 90 if (!apbc_base) {
91 pr_err("error to ioremap APBC base\n"); 91 pr_err("error to ioremap APBC base\n");
92 return; 92 return;
93 } 93 }
diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c
index a520cf7702a1..7a7965141918 100644
--- a/drivers/clk/mmp/clk-pxa910.c
+++ b/drivers/clk/mmp/clk-pxa910.c
@@ -74,25 +74,25 @@ void __init pxa910_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
74 void __iomem *apbc_base; 74 void __iomem *apbc_base;
75 75
76 mpmu_base = ioremap(mpmu_phys, SZ_4K); 76 mpmu_base = ioremap(mpmu_phys, SZ_4K);
77 if (mpmu_base == NULL) { 77 if (!mpmu_base) {
78 pr_err("error to ioremap MPMU base\n"); 78 pr_err("error to ioremap MPMU base\n");
79 return; 79 return;
80 } 80 }
81 81
82 apmu_base = ioremap(apmu_phys, SZ_4K); 82 apmu_base = ioremap(apmu_phys, SZ_4K);
83 if (apmu_base == NULL) { 83 if (!apmu_base) {
84 pr_err("error to ioremap APMU base\n"); 84 pr_err("error to ioremap APMU base\n");
85 return; 85 return;
86 } 86 }
87 87
88 apbcp_base = ioremap(apbcp_phys, SZ_4K); 88 apbcp_base = ioremap(apbcp_phys, SZ_4K);
89 if (apbcp_base == NULL) { 89 if (!apbcp_base) {
90 pr_err("error to ioremap APBC extension base\n"); 90 pr_err("error to ioremap APBC extension base\n");
91 return; 91 return;
92 } 92 }
93 93
94 apbc_base = ioremap(apbc_phys, SZ_4K); 94 apbc_base = ioremap(apbc_phys, SZ_4K);
95 if (apbc_base == NULL) { 95 if (!apbc_base) {
96 pr_err("error to ioremap APBC base\n"); 96 pr_err("error to ioremap APBC base\n");
97 return; 97 return;
98 } 98 }
diff --git a/drivers/clk/mxs/clk-div.c b/drivers/clk/mxs/clk-div.c
index f75e989c578f..ccebd014fc1e 100644
--- a/drivers/clk/mxs/clk-div.c
+++ b/drivers/clk/mxs/clk-div.c
@@ -67,7 +67,7 @@ static int clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
67 return ret; 67 return ret;
68} 68}
69 69
70static struct clk_ops clk_div_ops = { 70static const struct clk_ops clk_div_ops = {
71 .recalc_rate = clk_div_recalc_rate, 71 .recalc_rate = clk_div_recalc_rate,
72 .round_rate = clk_div_round_rate, 72 .round_rate = clk_div_round_rate,
73 .set_rate = clk_div_set_rate, 73 .set_rate = clk_div_set_rate,
diff --git a/drivers/clk/mxs/clk-frac.c b/drivers/clk/mxs/clk-frac.c
index f8dd10f6df3d..27b3372adc37 100644
--- a/drivers/clk/mxs/clk-frac.c
+++ b/drivers/clk/mxs/clk-frac.c
@@ -107,7 +107,7 @@ static int clk_frac_set_rate(struct clk_hw *hw, unsigned long rate,
107 return mxs_clk_wait(frac->reg, frac->busy); 107 return mxs_clk_wait(frac->reg, frac->busy);
108} 108}
109 109
110static struct clk_ops clk_frac_ops = { 110static const struct clk_ops clk_frac_ops = {
111 .recalc_rate = clk_frac_recalc_rate, 111 .recalc_rate = clk_frac_recalc_rate,
112 .round_rate = clk_frac_round_rate, 112 .round_rate = clk_frac_round_rate,
113 .set_rate = clk_frac_set_rate, 113 .set_rate = clk_frac_set_rate,
diff --git a/drivers/clk/pxa/clk-pxa.c b/drivers/clk/pxa/clk-pxa.c
index 74f64c3c4290..b80dc9d5855c 100644
--- a/drivers/clk/pxa/clk-pxa.c
+++ b/drivers/clk/pxa/clk-pxa.c
@@ -147,9 +147,7 @@ void pxa2xx_core_turbo_switch(bool on)
147 " b 3f\n" 147 " b 3f\n"
148 "2: b 1b\n" 148 "2: b 1b\n"
149 "3: nop\n" 149 "3: nop\n"
150 : "=&r" (unused) 150 : "=&r" (unused) : "r" (clkcfg));
151 : "r" (clkcfg)
152 : );
153 151
154 local_irq_restore(flags); 152 local_irq_restore(flags);
155} 153}
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index 1b3e8d265bdb..a2495457e564 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -156,7 +156,6 @@ extern const struct clk_ops clk_dyn_rcg_ops;
156 * @hid_width: number of bits in half integer divider 156 * @hid_width: number of bits in half integer divider
157 * @parent_map: map from software's parent index to hardware's src_sel field 157 * @parent_map: map from software's parent index to hardware's src_sel field
158 * @freq_tbl: frequency table 158 * @freq_tbl: frequency table
159 * @current_freq: last cached frequency when using branches with shared RCGs
160 * @clkr: regmap clock handle 159 * @clkr: regmap clock handle
161 * 160 *
162 */ 161 */
@@ -166,7 +165,6 @@ struct clk_rcg2 {
166 u8 hid_width; 165 u8 hid_width;
167 const struct parent_map *parent_map; 166 const struct parent_map *parent_map;
168 const struct freq_tbl *freq_tbl; 167 const struct freq_tbl *freq_tbl;
169 unsigned long current_freq;
170 struct clk_regmap clkr; 168 struct clk_regmap clkr;
171}; 169};
172 170
@@ -174,7 +172,6 @@ struct clk_rcg2 {
174 172
175extern const struct clk_ops clk_rcg2_ops; 173extern const struct clk_ops clk_rcg2_ops;
176extern const struct clk_ops clk_rcg2_floor_ops; 174extern const struct clk_ops clk_rcg2_floor_ops;
177extern const struct clk_ops clk_rcg2_shared_ops;
178extern const struct clk_ops clk_edp_pixel_ops; 175extern const struct clk_ops clk_edp_pixel_ops;
179extern const struct clk_ops clk_byte_ops; 176extern const struct clk_ops clk_byte_ops;
180extern const struct clk_ops clk_byte2_ops; 177extern const struct clk_ops clk_byte2_ops;
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 1a0985ae20d2..bbeaf9c09dbb 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -358,85 +358,6 @@ const struct clk_ops clk_rcg2_floor_ops = {
358}; 358};
359EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops); 359EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
360 360
361static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate)
362{
363 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
364 const char *name = clk_hw_get_name(hw);
365 int ret, count;
366
367 /* force enable RCG */
368 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
369 CMD_ROOT_EN, CMD_ROOT_EN);
370 if (ret)
371 return ret;
372
373 /* wait for RCG to turn ON */
374 for (count = 500; count > 0; count--) {
375 ret = clk_rcg2_is_enabled(hw);
376 if (ret)
377 break;
378 udelay(1);
379 }
380 if (!count)
381 pr_err("%s: RCG did not turn on\n", name);
382
383 /* set clock rate */
384 ret = __clk_rcg2_set_rate(hw, rate, CEIL);
385 if (ret)
386 return ret;
387
388 /* clear force enable RCG */
389 return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
390 CMD_ROOT_EN, 0);
391}
392
393static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate,
394 unsigned long parent_rate)
395{
396 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
397
398 /* cache the rate */
399 rcg->current_freq = rate;
400
401 if (!__clk_is_enabled(hw->clk))
402 return 0;
403
404 return clk_rcg2_shared_force_enable(hw, rcg->current_freq);
405}
406
407static unsigned long
408clk_rcg2_shared_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
409{
410 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
411
412 return rcg->current_freq = clk_rcg2_recalc_rate(hw, parent_rate);
413}
414
415static int clk_rcg2_shared_enable(struct clk_hw *hw)
416{
417 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
418
419 return clk_rcg2_shared_force_enable(hw, rcg->current_freq);
420}
421
422static void clk_rcg2_shared_disable(struct clk_hw *hw)
423{
424 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
425
426 /* switch to XO, which is the lowest entry in the freq table */
427 clk_rcg2_shared_set_rate(hw, rcg->freq_tbl[0].freq, 0);
428}
429
430const struct clk_ops clk_rcg2_shared_ops = {
431 .enable = clk_rcg2_shared_enable,
432 .disable = clk_rcg2_shared_disable,
433 .get_parent = clk_rcg2_get_parent,
434 .recalc_rate = clk_rcg2_shared_recalc_rate,
435 .determine_rate = clk_rcg2_determine_rate,
436 .set_rate = clk_rcg2_shared_set_rate,
437};
438EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
439
440struct frac_entry { 361struct frac_entry {
441 int num; 362 int num;
442 int den; 363 int den;
diff --git a/drivers/clk/qcom/clk-rpm.c b/drivers/clk/qcom/clk-rpm.c
index df3e5fe8442a..c60f61b10c7f 100644
--- a/drivers/clk/qcom/clk-rpm.c
+++ b/drivers/clk/qcom/clk-rpm.c
@@ -56,6 +56,18 @@
56 }, \ 56 }, \
57 } 57 }
58 58
59#define DEFINE_CLK_RPM_FIXED(_platform, _name, _active, r_id, r) \
60 static struct clk_rpm _platform##_##_name = { \
61 .rpm_clk_id = (r_id), \
62 .rate = (r), \
63 .hw.init = &(struct clk_init_data){ \
64 .ops = &clk_rpm_fixed_ops, \
65 .name = #_name, \
66 .parent_names = (const char *[]){ "pxo" }, \
67 .num_parents = 1, \
68 }, \
69 }
70
59#define DEFINE_CLK_RPM_PXO_BRANCH(_platform, _name, _active, r_id, r) \ 71#define DEFINE_CLK_RPM_PXO_BRANCH(_platform, _name, _active, r_id, r) \
60 static struct clk_rpm _platform##_##_active; \ 72 static struct clk_rpm _platform##_##_active; \
61 static struct clk_rpm _platform##_##_name = { \ 73 static struct clk_rpm _platform##_##_name = { \
@@ -143,6 +155,13 @@ static int clk_rpm_handoff(struct clk_rpm *r)
143 int ret; 155 int ret;
144 u32 value = INT_MAX; 156 u32 value = INT_MAX;
145 157
158 /*
159 * The vendor tree simply reads the status for this
160 * RPM clock.
161 */
162 if (r->rpm_clk_id == QCOM_RPM_PLL_4)
163 return 0;
164
146 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, 165 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
147 r->rpm_clk_id, &value, 1); 166 r->rpm_clk_id, &value, 1);
148 if (ret) 167 if (ret)
@@ -269,6 +288,32 @@ out:
269 mutex_unlock(&rpm_clk_lock); 288 mutex_unlock(&rpm_clk_lock);
270} 289}
271 290
291static int clk_rpm_fixed_prepare(struct clk_hw *hw)
292{
293 struct clk_rpm *r = to_clk_rpm(hw);
294 u32 value = 1;
295 int ret;
296
297 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
298 r->rpm_clk_id, &value, 1);
299 if (!ret)
300 r->enabled = true;
301
302 return ret;
303}
304
305static void clk_rpm_fixed_unprepare(struct clk_hw *hw)
306{
307 struct clk_rpm *r = to_clk_rpm(hw);
308 u32 value = 0;
309 int ret;
310
311 ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
312 r->rpm_clk_id, &value, 1);
313 if (!ret)
314 r->enabled = false;
315}
316
272static int clk_rpm_set_rate(struct clk_hw *hw, 317static int clk_rpm_set_rate(struct clk_hw *hw,
273 unsigned long rate, unsigned long parent_rate) 318 unsigned long rate, unsigned long parent_rate)
274{ 319{
@@ -333,6 +378,13 @@ static unsigned long clk_rpm_recalc_rate(struct clk_hw *hw,
333 return r->rate; 378 return r->rate;
334} 379}
335 380
381static const struct clk_ops clk_rpm_fixed_ops = {
382 .prepare = clk_rpm_fixed_prepare,
383 .unprepare = clk_rpm_fixed_unprepare,
384 .round_rate = clk_rpm_round_rate,
385 .recalc_rate = clk_rpm_recalc_rate,
386};
387
336static const struct clk_ops clk_rpm_ops = { 388static const struct clk_ops clk_rpm_ops = {
337 .prepare = clk_rpm_prepare, 389 .prepare = clk_rpm_prepare,
338 .unprepare = clk_rpm_unprepare, 390 .unprepare = clk_rpm_unprepare,
@@ -348,6 +400,45 @@ static const struct clk_ops clk_rpm_branch_ops = {
348 .recalc_rate = clk_rpm_recalc_rate, 400 .recalc_rate = clk_rpm_recalc_rate,
349}; 401};
350 402
403/* MSM8660/APQ8060 */
404DEFINE_CLK_RPM(msm8660, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
405DEFINE_CLK_RPM(msm8660, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
406DEFINE_CLK_RPM(msm8660, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK);
407DEFINE_CLK_RPM(msm8660, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
408DEFINE_CLK_RPM(msm8660, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
409DEFINE_CLK_RPM(msm8660, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
410DEFINE_CLK_RPM(msm8660, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK);
411DEFINE_CLK_RPM(msm8660, smi_clk, smi_a_clk, QCOM_RPM_SMI_CLK);
412DEFINE_CLK_RPM(msm8660, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
413DEFINE_CLK_RPM_FIXED(msm8660, pll4_clk, pll4_a_clk, QCOM_RPM_PLL_4, 540672000);
414
415static struct clk_rpm *msm8660_clks[] = {
416 [RPM_APPS_FABRIC_CLK] = &msm8660_afab_clk,
417 [RPM_APPS_FABRIC_A_CLK] = &msm8660_afab_a_clk,
418 [RPM_SYS_FABRIC_CLK] = &msm8660_sfab_clk,
419 [RPM_SYS_FABRIC_A_CLK] = &msm8660_sfab_a_clk,
420 [RPM_MM_FABRIC_CLK] = &msm8660_mmfab_clk,
421 [RPM_MM_FABRIC_A_CLK] = &msm8660_mmfab_a_clk,
422 [RPM_DAYTONA_FABRIC_CLK] = &msm8660_daytona_clk,
423 [RPM_DAYTONA_FABRIC_A_CLK] = &msm8660_daytona_a_clk,
424 [RPM_SFPB_CLK] = &msm8660_sfpb_clk,
425 [RPM_SFPB_A_CLK] = &msm8660_sfpb_a_clk,
426 [RPM_CFPB_CLK] = &msm8660_cfpb_clk,
427 [RPM_CFPB_A_CLK] = &msm8660_cfpb_a_clk,
428 [RPM_MMFPB_CLK] = &msm8660_mmfpb_clk,
429 [RPM_MMFPB_A_CLK] = &msm8660_mmfpb_a_clk,
430 [RPM_SMI_CLK] = &msm8660_smi_clk,
431 [RPM_SMI_A_CLK] = &msm8660_smi_a_clk,
432 [RPM_EBI1_CLK] = &msm8660_ebi1_clk,
433 [RPM_EBI1_A_CLK] = &msm8660_ebi1_a_clk,
434 [RPM_PLL4_CLK] = &msm8660_pll4_clk,
435};
436
437static const struct rpm_clk_desc rpm_clk_msm8660 = {
438 .clks = msm8660_clks,
439 .num_clks = ARRAY_SIZE(msm8660_clks),
440};
441
351/* apq8064 */ 442/* apq8064 */
352DEFINE_CLK_RPM(apq8064, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK); 443DEFINE_CLK_RPM(apq8064, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
353DEFINE_CLK_RPM(apq8064, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK); 444DEFINE_CLK_RPM(apq8064, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
@@ -386,6 +477,8 @@ static const struct rpm_clk_desc rpm_clk_apq8064 = {
386}; 477};
387 478
388static const struct of_device_id rpm_clk_match_table[] = { 479static const struct of_device_id rpm_clk_match_table[] = {
480 { .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 },
481 { .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 },
389 { .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 }, 482 { .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },
390 { } 483 { }
391}; 484};
diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
index cc03d5508627..c26d9007bfc4 100644
--- a/drivers/clk/qcom/clk-smd-rpm.c
+++ b/drivers/clk/qcom/clk-smd-rpm.c
@@ -530,9 +530,91 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
530 .clks = msm8974_clks, 530 .clks = msm8974_clks,
531 .num_clks = ARRAY_SIZE(msm8974_clks), 531 .num_clks = ARRAY_SIZE(msm8974_clks),
532}; 532};
533
534/* msm8996 */
535DEFINE_CLK_SMD_RPM(msm8996, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
536DEFINE_CLK_SMD_RPM(msm8996, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
537DEFINE_CLK_SMD_RPM(msm8996, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
538DEFINE_CLK_SMD_RPM(msm8996, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
539DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk,
540 QCOM_SMD_RPM_MMAXI_CLK, 0);
541DEFINE_CLK_SMD_RPM(msm8996, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
542DEFINE_CLK_SMD_RPM(msm8996, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
543DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc_clk, aggre1_noc_a_clk,
544 QCOM_SMD_RPM_AGGR_CLK, 1, 1000);
545DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc_clk, aggre2_noc_a_clk,
546 QCOM_SMD_RPM_AGGR_CLK, 2, 1000);
547DEFINE_CLK_SMD_RPM_QDSS(msm8996, qdss_clk, qdss_a_clk,
548 QCOM_SMD_RPM_MISC_CLK, 1);
549DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk1, bb_clk1_a, 1);
550DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk2, bb_clk2_a, 2);
551DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk1, rf_clk1_a, 4);
552DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk2, rf_clk2_a, 5);
553DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, ln_bb_clk, ln_bb_a_clk, 8);
554DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk1, div_clk1_a, 0xb);
555DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk2, div_clk2_a, 0xc);
556DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk3, div_clk3_a, 0xd);
557DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk1_pin, bb_clk1_a_pin, 1);
558DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk2_pin, bb_clk2_a_pin, 2);
559DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk1_pin, rf_clk1_a_pin, 4);
560DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk2_pin, rf_clk2_a_pin, 5);
561
562static struct clk_smd_rpm *msm8996_clks[] = {
563 [RPM_SMD_PCNOC_CLK] = &msm8996_pcnoc_clk,
564 [RPM_SMD_PCNOC_A_CLK] = &msm8996_pcnoc_a_clk,
565 [RPM_SMD_SNOC_CLK] = &msm8996_snoc_clk,
566 [RPM_SMD_SNOC_A_CLK] = &msm8996_snoc_a_clk,
567 [RPM_SMD_CNOC_CLK] = &msm8996_cnoc_clk,
568 [RPM_SMD_CNOC_A_CLK] = &msm8996_cnoc_a_clk,
569 [RPM_SMD_BIMC_CLK] = &msm8996_bimc_clk,
570 [RPM_SMD_BIMC_A_CLK] = &msm8996_bimc_a_clk,
571 [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
572 [RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk,
573 [RPM_SMD_IPA_CLK] = &msm8996_ipa_clk,
574 [RPM_SMD_IPA_A_CLK] = &msm8996_ipa_a_clk,
575 [RPM_SMD_CE1_CLK] = &msm8996_ce1_clk,
576 [RPM_SMD_CE1_A_CLK] = &msm8996_ce1_a_clk,
577 [RPM_SMD_AGGR1_NOC_CLK] = &msm8996_aggre1_noc_clk,
578 [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8996_aggre1_noc_a_clk,
579 [RPM_SMD_AGGR2_NOC_CLK] = &msm8996_aggre2_noc_clk,
580 [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8996_aggre2_noc_a_clk,
581 [RPM_SMD_QDSS_CLK] = &msm8996_qdss_clk,
582 [RPM_SMD_QDSS_A_CLK] = &msm8996_qdss_a_clk,
583 [RPM_SMD_BB_CLK1] = &msm8996_bb_clk1,
584 [RPM_SMD_BB_CLK1_A] = &msm8996_bb_clk1_a,
585 [RPM_SMD_BB_CLK2] = &msm8996_bb_clk2,
586 [RPM_SMD_BB_CLK2_A] = &msm8996_bb_clk2_a,
587 [RPM_SMD_RF_CLK1] = &msm8996_rf_clk1,
588 [RPM_SMD_RF_CLK1_A] = &msm8996_rf_clk1_a,
589 [RPM_SMD_RF_CLK2] = &msm8996_rf_clk2,
590 [RPM_SMD_RF_CLK2_A] = &msm8996_rf_clk2_a,
591 [RPM_SMD_LN_BB_CLK] = &msm8996_ln_bb_clk,
592 [RPM_SMD_LN_BB_A_CLK] = &msm8996_ln_bb_a_clk,
593 [RPM_SMD_DIV_CLK1] = &msm8996_div_clk1,
594 [RPM_SMD_DIV_A_CLK1] = &msm8996_div_clk1_a,
595 [RPM_SMD_DIV_CLK2] = &msm8996_div_clk2,
596 [RPM_SMD_DIV_A_CLK2] = &msm8996_div_clk2_a,
597 [RPM_SMD_DIV_CLK3] = &msm8996_div_clk3,
598 [RPM_SMD_DIV_A_CLK3] = &msm8996_div_clk3_a,
599 [RPM_SMD_BB_CLK1_PIN] = &msm8996_bb_clk1_pin,
600 [RPM_SMD_BB_CLK1_A_PIN] = &msm8996_bb_clk1_a_pin,
601 [RPM_SMD_BB_CLK2_PIN] = &msm8996_bb_clk2_pin,
602 [RPM_SMD_BB_CLK2_A_PIN] = &msm8996_bb_clk2_a_pin,
603 [RPM_SMD_RF_CLK1_PIN] = &msm8996_rf_clk1_pin,
604 [RPM_SMD_RF_CLK1_A_PIN] = &msm8996_rf_clk1_a_pin,
605 [RPM_SMD_RF_CLK2_PIN] = &msm8996_rf_clk2_pin,
606 [RPM_SMD_RF_CLK2_A_PIN] = &msm8996_rf_clk2_a_pin,
607};
608
609static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
610 .clks = msm8996_clks,
611 .num_clks = ARRAY_SIZE(msm8996_clks),
612};
613
533static const struct of_device_id rpm_smd_clk_match_table[] = { 614static const struct of_device_id rpm_smd_clk_match_table[] = {
534 { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 }, 615 { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
535 { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 }, 616 { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
617 { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
536 { } 618 { }
537}; 619};
538MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table); 620MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index d523991c945f..b8064a336d46 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -111,16 +111,6 @@ qcom_pll_set_fsm_mode(struct regmap *map, u32 reg, u8 bias_count, u8 lock_count)
111} 111}
112EXPORT_SYMBOL_GPL(qcom_pll_set_fsm_mode); 112EXPORT_SYMBOL_GPL(qcom_pll_set_fsm_mode);
113 113
114static void qcom_cc_del_clk_provider(void *data)
115{
116 of_clk_del_provider(data);
117}
118
119static void qcom_cc_reset_unregister(void *data)
120{
121 reset_controller_unregister(data);
122}
123
124static void qcom_cc_gdsc_unregister(void *data) 114static void qcom_cc_gdsc_unregister(void *data)
125{ 115{
126 gdsc_unregister(data); 116 gdsc_unregister(data);
@@ -143,8 +133,10 @@ static int _qcom_cc_register_board_clk(struct device *dev, const char *path,
143 int ret; 133 int ret;
144 134
145 clocks_node = of_find_node_by_path("/clocks"); 135 clocks_node = of_find_node_by_path("/clocks");
146 if (clocks_node) 136 if (clocks_node) {
147 node = of_find_node_by_name(clocks_node, path); 137 node = of_get_child_by_name(clocks_node, path);
138 of_node_put(clocks_node);
139 }
148 140
149 if (!node) { 141 if (!node) {
150 fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL); 142 fixed = devm_kzalloc(dev, sizeof(*fixed), GFP_KERNEL);
@@ -248,13 +240,7 @@ int qcom_cc_really_probe(struct platform_device *pdev,
248 return ret; 240 return ret;
249 } 241 }
250 242
251 ret = of_clk_add_hw_provider(dev->of_node, qcom_cc_clk_hw_get, cc); 243 ret = devm_of_clk_add_hw_provider(dev, qcom_cc_clk_hw_get, cc);
252 if (ret)
253 return ret;
254
255 ret = devm_add_action_or_reset(dev, qcom_cc_del_clk_provider,
256 pdev->dev.of_node);
257
258 if (ret) 244 if (ret)
259 return ret; 245 return ret;
260 246
@@ -266,13 +252,7 @@ int qcom_cc_really_probe(struct platform_device *pdev,
266 reset->regmap = regmap; 252 reset->regmap = regmap;
267 reset->reset_map = desc->resets; 253 reset->reset_map = desc->resets;
268 254
269 ret = reset_controller_register(&reset->rcdev); 255 ret = devm_reset_controller_register(dev, &reset->rcdev);
270 if (ret)
271 return ret;
272
273 ret = devm_add_action_or_reset(dev, qcom_cc_reset_unregister,
274 &reset->rcdev);
275
276 if (ret) 256 if (ret)
277 return ret; 257 return ret;
278 258
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index acbb38151ba1..43b5a89c4b28 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -15,6 +15,7 @@ config CLK_RENESAS
15 select CLK_R8A7794 if ARCH_R8A7794 15 select CLK_R8A7794 if ARCH_R8A7794
16 select CLK_R8A7795 if ARCH_R8A7795 16 select CLK_R8A7795 if ARCH_R8A7795
17 select CLK_R8A7796 if ARCH_R8A7796 17 select CLK_R8A7796 if ARCH_R8A7796
18 select CLK_R8A77970 if ARCH_R8A77970
18 select CLK_R8A77995 if ARCH_R8A77995 19 select CLK_R8A77995 if ARCH_R8A77995
19 select CLK_SH73A0 if ARCH_SH73A0 20 select CLK_SH73A0 if ARCH_SH73A0
20 21
@@ -95,6 +96,10 @@ config CLK_R8A7796
95 bool "R-Car M3-W clock support" if COMPILE_TEST 96 bool "R-Car M3-W clock support" if COMPILE_TEST
96 select CLK_RCAR_GEN3_CPG 97 select CLK_RCAR_GEN3_CPG
97 98
99config CLK_R8A77970
100 bool "R-Car V3M clock support" if COMPILE_TEST
101 select CLK_RCAR_GEN3_CPG
102
98config CLK_R8A77995 103config CLK_R8A77995
99 bool "R-Car D3 clock support" if COMPILE_TEST 104 bool "R-Car D3 clock support" if COMPILE_TEST
100 select CLK_RCAR_GEN3_CPG 105 select CLK_RCAR_GEN3_CPG
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index cbbb081e2145..34c4e0b37afa 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
14obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o 14obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
15obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o 15obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
16obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o 16obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
17obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o
17obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o 18obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
18obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o 19obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
19 20
diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c
index 3e0040c0ac87..151336d2ba59 100644
--- a/drivers/clk/renesas/clk-div6.c
+++ b/drivers/clk/renesas/clk-div6.c
@@ -14,8 +14,10 @@
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/notifier.h>
17#include <linux/of.h> 18#include <linux/of.h>
18#include <linux/of_address.h> 19#include <linux/of_address.h>
20#include <linux/pm.h>
19#include <linux/slab.h> 21#include <linux/slab.h>
20 22
21#include "clk-div6.h" 23#include "clk-div6.h"
@@ -32,6 +34,7 @@
32 * @src_shift: Shift to access the register bits to select the parent clock 34 * @src_shift: Shift to access the register bits to select the parent clock
33 * @src_width: Number of register bits to select the parent clock (may be 0) 35 * @src_width: Number of register bits to select the parent clock (may be 0)
34 * @parents: Array to map from valid parent clocks indices to hardware indices 36 * @parents: Array to map from valid parent clocks indices to hardware indices
37 * @nb: Notifier block to save/restore clock state for system resume
35 */ 38 */
36struct div6_clock { 39struct div6_clock {
37 struct clk_hw hw; 40 struct clk_hw hw;
@@ -40,6 +43,7 @@ struct div6_clock {
40 u32 src_shift; 43 u32 src_shift;
41 u32 src_width; 44 u32 src_width;
42 u8 *parents; 45 u8 *parents;
46 struct notifier_block nb;
43}; 47};
44 48
45#define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw) 49#define to_div6_clock(_hw) container_of(_hw, struct div6_clock, hw)
@@ -176,6 +180,29 @@ static const struct clk_ops cpg_div6_clock_ops = {
176 .set_rate = cpg_div6_clock_set_rate, 180 .set_rate = cpg_div6_clock_set_rate,
177}; 181};
178 182
183static int cpg_div6_clock_notifier_call(struct notifier_block *nb,
184 unsigned long action, void *data)
185{
186 struct div6_clock *clock = container_of(nb, struct div6_clock, nb);
187
188 switch (action) {
189 case PM_EVENT_RESUME:
190 /*
191 * TODO: This does not yet support DIV6 clocks with multiple
192 * parents, as the parent selection bits are not restored.
193 * Fortunately so far such DIV6 clocks are found only on
194 * R/SH-Mobile SoCs, while the resume functionality is only
195 * needed on R-Car Gen3.
196 */
197 if (__clk_get_enable_count(clock->hw.clk))
198 cpg_div6_clock_enable(&clock->hw);
199 else
200 cpg_div6_clock_disable(&clock->hw);
201 return NOTIFY_OK;
202 }
203
204 return NOTIFY_DONE;
205}
179 206
180/** 207/**
181 * cpg_div6_register - Register a DIV6 clock 208 * cpg_div6_register - Register a DIV6 clock
@@ -183,11 +210,13 @@ static const struct clk_ops cpg_div6_clock_ops = {
183 * @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8) 210 * @num_parents: Number of parent clocks of the DIV6 clock (1, 4, or 8)
184 * @parent_names: Array containing the names of the parent clocks 211 * @parent_names: Array containing the names of the parent clocks
185 * @reg: Mapped register used to control the DIV6 clock 212 * @reg: Mapped register used to control the DIV6 clock
213 * @notifiers: Optional notifier chain to save/restore state for system resume
186 */ 214 */
187struct clk * __init cpg_div6_register(const char *name, 215struct clk * __init cpg_div6_register(const char *name,
188 unsigned int num_parents, 216 unsigned int num_parents,
189 const char **parent_names, 217 const char **parent_names,
190 void __iomem *reg) 218 void __iomem *reg,
219 struct raw_notifier_head *notifiers)
191{ 220{
192 unsigned int valid_parents; 221 unsigned int valid_parents;
193 struct clk_init_data init; 222 struct clk_init_data init;
@@ -258,6 +287,11 @@ struct clk * __init cpg_div6_register(const char *name,
258 if (IS_ERR(clk)) 287 if (IS_ERR(clk))
259 goto free_parents; 288 goto free_parents;
260 289
290 if (notifiers) {
291 clock->nb.notifier_call = cpg_div6_clock_notifier_call;
292 raw_notifier_chain_register(notifiers, &clock->nb);
293 }
294
261 return clk; 295 return clk;
262 296
263free_parents: 297free_parents:
@@ -301,7 +335,7 @@ static void __init cpg_div6_clock_init(struct device_node *np)
301 for (i = 0; i < num_parents; i++) 335 for (i = 0; i < num_parents; i++)
302 parent_names[i] = of_clk_get_parent_name(np, i); 336 parent_names[i] = of_clk_get_parent_name(np, i);
303 337
304 clk = cpg_div6_register(clk_name, num_parents, parent_names, reg); 338 clk = cpg_div6_register(clk_name, num_parents, parent_names, reg, NULL);
305 if (IS_ERR(clk)) { 339 if (IS_ERR(clk)) {
306 pr_err("%s: failed to register %s DIV6 clock (%ld)\n", 340 pr_err("%s: failed to register %s DIV6 clock (%ld)\n",
307 __func__, np->name, PTR_ERR(clk)); 341 __func__, np->name, PTR_ERR(clk));
diff --git a/drivers/clk/renesas/clk-div6.h b/drivers/clk/renesas/clk-div6.h
index 065dfb49adf6..3af640a0b08d 100644
--- a/drivers/clk/renesas/clk-div6.h
+++ b/drivers/clk/renesas/clk-div6.h
@@ -3,6 +3,7 @@
3#define __RENESAS_CLK_DIV6_H__ 3#define __RENESAS_CLK_DIV6_H__
4 4
5struct clk *cpg_div6_register(const char *name, unsigned int num_parents, 5struct clk *cpg_div6_register(const char *name, unsigned int num_parents,
6 const char **parent_names, void __iomem *reg); 6 const char **parent_names, void __iomem *reg,
7 struct raw_notifier_head *notifiers);
7 8
8#endif 9#endif
diff --git a/drivers/clk/renesas/clk-mstp.c b/drivers/clk/renesas/clk-mstp.c
index 500a9e4e03c4..c944cc421e30 100644
--- a/drivers/clk/renesas/clk-mstp.c
+++ b/drivers/clk/renesas/clk-mstp.c
@@ -156,10 +156,8 @@ static struct clk * __init cpg_mstp_clock_register(const char *name,
156 struct clk *clk; 156 struct clk *clk;
157 157
158 clock = kzalloc(sizeof(*clock), GFP_KERNEL); 158 clock = kzalloc(sizeof(*clock), GFP_KERNEL);
159 if (!clock) { 159 if (!clock)
160 pr_err("%s: failed to allocate MSTP clock.\n", __func__);
161 return ERR_PTR(-ENOMEM); 160 return ERR_PTR(-ENOMEM);
162 }
163 161
164 init.name = name; 162 init.name = name;
165 init.ops = &cpg_mstp_clock_ops; 163 init.ops = &cpg_mstp_clock_ops;
@@ -196,7 +194,6 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
196 if (group == NULL || clks == NULL) { 194 if (group == NULL || clks == NULL) {
197 kfree(group); 195 kfree(group);
198 kfree(clks); 196 kfree(clks);
199 pr_err("%s: failed to allocate group\n", __func__);
200 return; 197 return;
201 } 198 }
202 199
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c
index 0b2e56d0d94b..d14cbe1ca29a 100644
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -423,7 +423,6 @@ static void __init rcar_gen2_cpg_clocks_init(struct device_node *np)
423 /* We're leaking memory on purpose, there's no point in cleaning 423 /* We're leaking memory on purpose, there's no point in cleaning
424 * up as the system won't boot anyway. 424 * up as the system won't boot anyway.
425 */ 425 */
426 pr_err("%s: failed to allocate cpg\n", __func__);
427 return; 426 return;
428 } 427 }
429 428
diff --git a/drivers/clk/renesas/clk-rz.c b/drivers/clk/renesas/clk-rz.c
index 5adb934326d1..127c58135c8f 100644
--- a/drivers/clk/renesas/clk-rz.c
+++ b/drivers/clk/renesas/clk-rz.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * rz Core CPG Clocks 2 * RZ/A1 Core CPG Clocks
3 * 3 *
4 * Copyright (C) 2013 Ideas On Board SPRL 4 * Copyright (C) 2013 Ideas On Board SPRL
5 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com> 5 * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas/r8a7745-cpg-mssr.c
index 9e2360a8e14b..2859504cc866 100644
--- a/drivers/clk/renesas/r8a7745-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c
@@ -129,6 +129,7 @@ static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = {
129 DEF_MOD("scif2", 719, R8A7745_CLK_P), 129 DEF_MOD("scif2", 719, R8A7745_CLK_P),
130 DEF_MOD("scif1", 720, R8A7745_CLK_P), 130 DEF_MOD("scif1", 720, R8A7745_CLK_P),
131 DEF_MOD("scif0", 721, R8A7745_CLK_P), 131 DEF_MOD("scif0", 721, R8A7745_CLK_P),
132 DEF_MOD("du1", 723, R8A7745_CLK_ZX),
132 DEF_MOD("du0", 724, R8A7745_CLK_ZX), 133 DEF_MOD("du0", 724, R8A7745_CLK_ZX),
133 DEF_MOD("ipmmu-sgx", 800, R8A7745_CLK_ZX), 134 DEF_MOD("ipmmu-sgx", 800, R8A7745_CLK_ZX),
134 DEF_MOD("vin1", 810, R8A7745_CLK_ZG), 135 DEF_MOD("vin1", 810, R8A7745_CLK_ZG),
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index 762b2f8824f1..b1d9f48eae9e 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -149,7 +149,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
149 DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1), 149 DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
150 DEF_MOD("rwdt", 402, R8A7795_CLK_R), 150 DEF_MOD("rwdt", 402, R8A7795_CLK_R),
151 DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), 151 DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
152 DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), 152 DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
153 DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3), 153 DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3),
154 DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3), 154 DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3),
155 DEF_MOD("drif7", 508, R8A7795_CLK_S3D2), 155 DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
@@ -348,6 +348,7 @@ static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = {
348 { MOD_CLK_ID(217), R8A7795_CLK_S3D1 }, /* SYS-DMAC2 */ 348 { MOD_CLK_ID(217), R8A7795_CLK_S3D1 }, /* SYS-DMAC2 */
349 { MOD_CLK_ID(218), R8A7795_CLK_S3D1 }, /* SYS-DMAC1 */ 349 { MOD_CLK_ID(218), R8A7795_CLK_S3D1 }, /* SYS-DMAC1 */
350 { MOD_CLK_ID(219), R8A7795_CLK_S3D1 }, /* SYS-DMAC0 */ 350 { MOD_CLK_ID(219), R8A7795_CLK_S3D1 }, /* SYS-DMAC0 */
351 { MOD_CLK_ID(408), R8A7795_CLK_S3D1 }, /* INTC-AP */
351 { MOD_CLK_ID(501), R8A7795_CLK_S3D1 }, /* AUDMAC1 */ 352 { MOD_CLK_ID(501), R8A7795_CLK_S3D1 }, /* AUDMAC1 */
352 { MOD_CLK_ID(502), R8A7795_CLK_S3D1 }, /* AUDMAC0 */ 353 { MOD_CLK_ID(502), R8A7795_CLK_S3D1 }, /* AUDMAC0 */
353 { MOD_CLK_ID(523), R8A7795_CLK_S3D4 }, /* PWM */ 354 { MOD_CLK_ID(523), R8A7795_CLK_S3D4 }, /* PWM */
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index e5e7fb212288..b3767472088a 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -143,7 +143,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
143 DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1), 143 DEF_MOD("usb-dmac1", 331, R8A7796_CLK_S3D1),
144 DEF_MOD("rwdt", 402, R8A7796_CLK_R), 144 DEF_MOD("rwdt", 402, R8A7796_CLK_R),
145 DEF_MOD("intc-ex", 407, R8A7796_CLK_CP), 145 DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
146 DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1), 146 DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3),
147 DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3), 147 DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3),
148 DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3), 148 DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3),
149 DEF_MOD("drif7", 508, R8A7796_CLK_S3D2), 149 DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c
new file mode 100644
index 000000000000..72f98527473a
--- /dev/null
+++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -0,0 +1,199 @@
1/*
2 * r8a77970 Clock Pulse Generator / Module Standby and Software Reset
3 *
4 * Copyright (C) 2017 Cogent Embedded Inc.
5 *
6 * Based on r8a7795-cpg-mssr.c
7 *
8 * Copyright (C) 2015 Glider bvba
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 */
14
15#include <linux/device.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/soc/renesas/rcar-rst.h>
19
20#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
21
22#include "renesas-cpg-mssr.h"
23#include "rcar-gen3-cpg.h"
24
25enum clk_ids {
26 /* Core Clock Outputs exported to DT */
27 LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
28
29 /* External Input Clocks */
30 CLK_EXTAL,
31 CLK_EXTALR,
32
33 /* Internal Core Clocks */
34 CLK_MAIN,
35 CLK_PLL0,
36 CLK_PLL1,
37 CLK_PLL3,
38 CLK_PLL1_DIV2,
39 CLK_PLL1_DIV4,
40
41 /* Module Clocks */
42 MOD_CLK_BASE
43};
44
45static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
46 /* External Clock Inputs */
47 DEF_INPUT("extal", CLK_EXTAL),
48 DEF_INPUT("extalr", CLK_EXTALR),
49
50 /* Internal Core Clocks */
51 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
52 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
53 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
54 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
55
56 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
57 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
58
59 /* Core Clock Outputs */
60 DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
61 DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
62 DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
63 DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
64 DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_PLL1_DIV2, 4, 1),
65 DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_PLL1_DIV2, 8, 1),
66 DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_PLL1_DIV2, 16, 1),
67 DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_PLL1_DIV2, 6, 1),
68 DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_PLL1_DIV2, 12, 1),
69 DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_PLL1_DIV2, 24, 1),
70
71 DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
72 DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
73
74 DEF_DIV6P1("canfd", R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
75 DEF_DIV6P1("mso", R8A77970_CLK_MSO, CLK_PLL1_DIV4, 0x014),
76 DEF_DIV6P1("csi0", R8A77970_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
77
78 DEF_FIXED("osc", R8A77970_CLK_OSC, CLK_PLL1_DIV2, 12*1024, 1),
79 DEF_FIXED("r", R8A77970_CLK_R, CLK_EXTALR, 1, 1),
80};
81
82static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
83 DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
84 DEF_MOD("scif4", 203, R8A77970_CLK_S2D4),
85 DEF_MOD("scif3", 204, R8A77970_CLK_S2D4),
86 DEF_MOD("scif1", 206, R8A77970_CLK_S2D4),
87 DEF_MOD("scif0", 207, R8A77970_CLK_S2D4),
88 DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
89 DEF_MOD("msiof2", 209, R8A77970_CLK_MSO),
90 DEF_MOD("msiof1", 210, R8A77970_CLK_MSO),
91 DEF_MOD("msiof0", 211, R8A77970_CLK_MSO),
92 DEF_MOD("mfis", 213, R8A77970_CLK_S2D2),
93 DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
94 DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
95 DEF_MOD("rwdt", 402, R8A77970_CLK_R),
96 DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
97 DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1),
98 DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1),
99 DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1),
100 DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1),
101 DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1),
102 DEF_MOD("thermal", 522, R8A77970_CLK_CP),
103 DEF_MOD("pwm", 523, R8A77970_CLK_S2D4),
104 DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
105 DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1),
106 DEF_MOD("csi40", 716, R8A77970_CLK_CSI0),
107 DEF_MOD("du0", 724, R8A77970_CLK_S2D1),
108 DEF_MOD("vin3", 808, R8A77970_CLK_S2D1),
109 DEF_MOD("vin2", 809, R8A77970_CLK_S2D1),
110 DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
111 DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
112 DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
113 DEF_MOD("gpio5", 907, R8A77970_CLK_CP),
114 DEF_MOD("gpio4", 908, R8A77970_CLK_CP),
115 DEF_MOD("gpio3", 909, R8A77970_CLK_CP),
116 DEF_MOD("gpio2", 910, R8A77970_CLK_CP),
117 DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
118 DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
119 DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
120 DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
121 DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
122 DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
123 DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2),
124 DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2),
125};
126
127static const unsigned int r8a77970_crit_mod_clks[] __initconst = {
128 MOD_CLK_ID(408), /* INTC-AP (GIC) */
129};
130
131
132/*
133 * CPG Clock Data
134 */
135
136/*
137 * MD EXTAL PLL0 PLL1 PLL3
138 * 14 13 19 (MHz)
139 *-------------------------------------------------
140 * 0 0 0 16.66 x 1 x192 x192 x96
141 * 0 0 1 16.66 x 1 x192 x192 x80
142 * 0 1 0 20 x 1 x160 x160 x80
143 * 0 1 1 20 x 1 x160 x160 x66
144 * 1 0 0 27 / 2 x236 x236 x118
145 * 1 0 1 27 / 2 x236 x236 x98
146 * 1 1 0 33.33 / 2 x192 x192 x96
147 * 1 1 1 33.33 / 2 x192 x192 x80
148 */
149#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
150 (((md) & BIT(13)) >> 12) | \
151 (((md) & BIT(19)) >> 19))
152
153static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] __initconst = {
154 /* EXTAL div PLL1 mult/div PLL3 mult/div */
155 { 1, 192, 1, 96, 1, },
156 { 1, 192, 1, 80, 1, },
157 { 1, 160, 1, 80, 1, },
158 { 1, 160, 1, 66, 1, },
159 { 2, 236, 1, 118, 1, },
160 { 2, 236, 1, 98, 1, },
161 { 2, 192, 1, 96, 1, },
162 { 2, 192, 1, 80, 1, },
163};
164
165static int __init r8a77970_cpg_mssr_init(struct device *dev)
166{
167 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
168 u32 cpg_mode;
169 int error;
170
171 error = rcar_rst_read_mode_pins(&cpg_mode);
172 if (error)
173 return error;
174
175 cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
176
177 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
178}
179
180const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = {
181 /* Core Clocks */
182 .core_clks = r8a77970_core_clks,
183 .num_core_clks = ARRAY_SIZE(r8a77970_core_clks),
184 .last_dt_core_clk = LAST_DT_CORE_CLK,
185 .num_total_core_clks = MOD_CLK_BASE,
186
187 /* Module Clocks */
188 .mod_clks = r8a77970_mod_clks,
189 .num_mod_clks = ARRAY_SIZE(r8a77970_mod_clks),
190 .num_hw_mod_clks = 12 * 32,
191
192 /* Critical Module Clocks */
193 .crit_mod_clks = r8a77970_crit_mod_clks,
194 .num_crit_mod_clks = ARRAY_SIZE(r8a77970_crit_mod_clks),
195
196 /* Callbacks */
197 .init = r8a77970_cpg_mssr_init,
198 .cpg_clk_register = rcar_gen3_cpg_clk_register,
199};
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index e594cf8ee63b..ea4cafbe6e85 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -127,7 +127,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
127 DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1), 127 DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1),
128 DEF_MOD("rwdt", 402, R8A77995_CLK_R), 128 DEF_MOD("rwdt", 402, R8A77995_CLK_R),
129 DEF_MOD("intc-ex", 407, R8A77995_CLK_CP), 129 DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
130 DEF_MOD("intc-ap", 408, R8A77995_CLK_S3D1), 130 DEF_MOD("intc-ap", 408, R8A77995_CLK_S1D2),
131 DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1), 131 DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1),
132 DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C), 132 DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
133 DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C), 133 DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
diff --git a/drivers/clk/renesas/rcar-gen2-cpg.c b/drivers/clk/renesas/rcar-gen2-cpg.c
index 123b1e622179..feb14579a71b 100644
--- a/drivers/clk/renesas/rcar-gen2-cpg.c
+++ b/drivers/clk/renesas/rcar-gen2-cpg.c
@@ -262,10 +262,9 @@ static unsigned int cpg_pll0_div __initdata;
262static u32 cpg_mode __initdata; 262static u32 cpg_mode __initdata;
263 263
264struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev, 264struct clk * __init rcar_gen2_cpg_clk_register(struct device *dev,
265 const struct cpg_core_clk *core, 265 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
266 const struct cpg_mssr_info *info, 266 struct clk **clks, void __iomem *base,
267 struct clk **clks, 267 struct raw_notifier_head *notifiers)
268 void __iomem *base)
269{ 268{
270 const struct clk_div_table *table = NULL; 269 const struct clk_div_table *table = NULL;
271 const struct clk *parent; 270 const struct clk *parent;
diff --git a/drivers/clk/renesas/rcar-gen2-cpg.h b/drivers/clk/renesas/rcar-gen2-cpg.h
index 9eba07ff8b11..020a3baad015 100644
--- a/drivers/clk/renesas/rcar-gen2-cpg.h
+++ b/drivers/clk/renesas/rcar-gen2-cpg.h
@@ -34,9 +34,9 @@ struct rcar_gen2_cpg_pll_config {
34}; 34};
35 35
36struct clk *rcar_gen2_cpg_clk_register(struct device *dev, 36struct clk *rcar_gen2_cpg_clk_register(struct device *dev,
37 const struct cpg_core_clk *core, 37 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
38 const struct cpg_mssr_info *info, 38 struct clk **clks, void __iomem *base,
39 struct clk **clks, void __iomem *base); 39 struct raw_notifier_head *notifiers);
40int rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config, 40int rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
41 unsigned int pll0_div, u32 mode); 41 unsigned int pll0_div, u32 mode);
42 42
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 951105816547..0904886f5501 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -19,6 +19,7 @@
19#include <linux/err.h> 19#include <linux/err.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/pm.h>
22#include <linux/slab.h> 23#include <linux/slab.h>
23#include <linux/sys_soc.h> 24#include <linux/sys_soc.h>
24 25
@@ -29,6 +30,36 @@
29#define CPG_PLL2CR 0x002c 30#define CPG_PLL2CR 0x002c
30#define CPG_PLL4CR 0x01f4 31#define CPG_PLL4CR 0x01f4
31 32
33struct cpg_simple_notifier {
34 struct notifier_block nb;
35 void __iomem *reg;
36 u32 saved;
37};
38
39static int cpg_simple_notifier_call(struct notifier_block *nb,
40 unsigned long action, void *data)
41{
42 struct cpg_simple_notifier *csn =
43 container_of(nb, struct cpg_simple_notifier, nb);
44
45 switch (action) {
46 case PM_EVENT_SUSPEND:
47 csn->saved = readl(csn->reg);
48 return NOTIFY_OK;
49
50 case PM_EVENT_RESUME:
51 writel(csn->saved, csn->reg);
52 return NOTIFY_OK;
53 }
54 return NOTIFY_DONE;
55}
56
57static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers,
58 struct cpg_simple_notifier *csn)
59{
60 csn->nb.notifier_call = cpg_simple_notifier_call;
61 raw_notifier_chain_register(notifiers, &csn->nb);
62}
32 63
33/* 64/*
34 * SDn Clock 65 * SDn Clock
@@ -55,8 +86,8 @@ struct sd_div_table {
55 86
56struct sd_clock { 87struct sd_clock {
57 struct clk_hw hw; 88 struct clk_hw hw;
58 void __iomem *reg;
59 const struct sd_div_table *div_table; 89 const struct sd_div_table *div_table;
90 struct cpg_simple_notifier csn;
60 unsigned int div_num; 91 unsigned int div_num;
61 unsigned int div_min; 92 unsigned int div_min;
62 unsigned int div_max; 93 unsigned int div_max;
@@ -97,12 +128,12 @@ static const struct sd_div_table cpg_sd_div_table[] = {
97static int cpg_sd_clock_enable(struct clk_hw *hw) 128static int cpg_sd_clock_enable(struct clk_hw *hw)
98{ 129{
99 struct sd_clock *clock = to_sd_clock(hw); 130 struct sd_clock *clock = to_sd_clock(hw);
100 u32 val = readl(clock->reg); 131 u32 val = readl(clock->csn.reg);
101 132
102 val &= ~(CPG_SD_STP_MASK); 133 val &= ~(CPG_SD_STP_MASK);
103 val |= clock->div_table[clock->cur_div_idx].val & CPG_SD_STP_MASK; 134 val |= clock->div_table[clock->cur_div_idx].val & CPG_SD_STP_MASK;
104 135
105 writel(val, clock->reg); 136 writel(val, clock->csn.reg);
106 137
107 return 0; 138 return 0;
108} 139}
@@ -111,14 +142,14 @@ static void cpg_sd_clock_disable(struct clk_hw *hw)
111{ 142{
112 struct sd_clock *clock = to_sd_clock(hw); 143 struct sd_clock *clock = to_sd_clock(hw);
113 144
114 writel(readl(clock->reg) | CPG_SD_STP_MASK, clock->reg); 145 writel(readl(clock->csn.reg) | CPG_SD_STP_MASK, clock->csn.reg);
115} 146}
116 147
117static int cpg_sd_clock_is_enabled(struct clk_hw *hw) 148static int cpg_sd_clock_is_enabled(struct clk_hw *hw)
118{ 149{
119 struct sd_clock *clock = to_sd_clock(hw); 150 struct sd_clock *clock = to_sd_clock(hw);
120 151
121 return !(readl(clock->reg) & CPG_SD_STP_MASK); 152 return !(readl(clock->csn.reg) & CPG_SD_STP_MASK);
122} 153}
123 154
124static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw, 155static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
@@ -170,10 +201,10 @@ static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate,
170 201
171 clock->cur_div_idx = i; 202 clock->cur_div_idx = i;
172 203
173 val = readl(clock->reg); 204 val = readl(clock->csn.reg);
174 val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK); 205 val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);
175 val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK); 206 val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);
176 writel(val, clock->reg); 207 writel(val, clock->csn.reg);
177 208
178 return 0; 209 return 0;
179} 210}
@@ -188,8 +219,8 @@ static const struct clk_ops cpg_sd_clock_ops = {
188}; 219};
189 220
190static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core, 221static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
191 void __iomem *base, 222 void __iomem *base, const char *parent_name,
192 const char *parent_name) 223 struct raw_notifier_head *notifiers)
193{ 224{
194 struct clk_init_data init; 225 struct clk_init_data init;
195 struct sd_clock *clock; 226 struct sd_clock *clock;
@@ -207,12 +238,12 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
207 init.parent_names = &parent_name; 238 init.parent_names = &parent_name;
208 init.num_parents = 1; 239 init.num_parents = 1;
209 240
210 clock->reg = base + core->offset; 241 clock->csn.reg = base + core->offset;
211 clock->hw.init = &init; 242 clock->hw.init = &init;
212 clock->div_table = cpg_sd_div_table; 243 clock->div_table = cpg_sd_div_table;
213 clock->div_num = ARRAY_SIZE(cpg_sd_div_table); 244 clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
214 245
215 sd_fc = readl(clock->reg) & CPG_SD_FC_MASK; 246 sd_fc = readl(clock->csn.reg) & CPG_SD_FC_MASK;
216 for (i = 0; i < clock->div_num; i++) 247 for (i = 0; i < clock->div_num; i++)
217 if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK)) 248 if (sd_fc == (clock->div_table[i].val & CPG_SD_FC_MASK))
218 break; 249 break;
@@ -233,8 +264,13 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
233 264
234 clk = clk_register(NULL, &clock->hw); 265 clk = clk_register(NULL, &clock->hw);
235 if (IS_ERR(clk)) 266 if (IS_ERR(clk))
236 kfree(clock); 267 goto free_clock;
237 268
269 cpg_simple_notifier_register(notifiers, &clock->csn);
270 return clk;
271
272free_clock:
273 kfree(clock);
238 return clk; 274 return clk;
239} 275}
240 276
@@ -265,7 +301,8 @@ static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
265 301
266struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, 302struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
267 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 303 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
268 struct clk **clks, void __iomem *base) 304 struct clk **clks, void __iomem *base,
305 struct raw_notifier_head *notifiers)
269{ 306{
270 const struct clk *parent; 307 const struct clk *parent;
271 unsigned int mult = 1; 308 unsigned int mult = 1;
@@ -331,22 +368,32 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
331 break; 368 break;
332 369
333 case CLK_TYPE_GEN3_SD: 370 case CLK_TYPE_GEN3_SD:
334 return cpg_sd_clk_register(core, base, __clk_get_name(parent)); 371 return cpg_sd_clk_register(core, base, __clk_get_name(parent),
372 notifiers);
335 373
336 case CLK_TYPE_GEN3_R: 374 case CLK_TYPE_GEN3_R:
337 if (cpg_quirks & RCKCR_CKSEL) { 375 if (cpg_quirks & RCKCR_CKSEL) {
376 struct cpg_simple_notifier *csn;
377
378 csn = kzalloc(sizeof(*csn), GFP_KERNEL);
379 if (!csn)
380 return ERR_PTR(-ENOMEM);
381
382 csn->reg = base + CPG_RCKCR;
383
338 /* 384 /*
339 * RINT is default. 385 * RINT is default.
340 * Only if EXTALR is populated, we switch to it. 386 * Only if EXTALR is populated, we switch to it.
341 */ 387 */
342 value = readl(base + CPG_RCKCR) & 0x3f; 388 value = readl(csn->reg) & 0x3f;
343 389
344 if (clk_get_rate(clks[cpg_clk_extalr])) { 390 if (clk_get_rate(clks[cpg_clk_extalr])) {
345 parent = clks[cpg_clk_extalr]; 391 parent = clks[cpg_clk_extalr];
346 value |= BIT(15); 392 value |= BIT(15);
347 } 393 }
348 394
349 writel(value, base + CPG_RCKCR); 395 writel(value, csn->reg);
396 cpg_simple_notifier_register(notifiers, csn);
350 break; 397 break;
351 } 398 }
352 399
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index d756ef8b78eb..2e4284399f53 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -44,7 +44,8 @@ struct rcar_gen3_cpg_pll_config {
44 44
45struct clk *rcar_gen3_cpg_clk_register(struct device *dev, 45struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
46 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 46 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
47 struct clk **clks, void __iomem *base); 47 struct clk **clks, void __iomem *base,
48 struct raw_notifier_head *notifiers);
48int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, 49int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
49 unsigned int clk_extalr, u32 mode); 50 unsigned int clk_extalr, u32 mode);
50 51
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index e580a5e6346c..e3d03ffea4bc 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -26,6 +26,7 @@
26#include <linux/platform_device.h> 26#include <linux/platform_device.h>
27#include <linux/pm_clock.h> 27#include <linux/pm_clock.h>
28#include <linux/pm_domain.h> 28#include <linux/pm_domain.h>
29#include <linux/psci.h>
29#include <linux/reset-controller.h> 30#include <linux/reset-controller.h>
30#include <linux/slab.h> 31#include <linux/slab.h>
31 32
@@ -106,6 +107,9 @@ static const u16 srcr[] = {
106 * @num_core_clks: Number of Core Clocks in clks[] 107 * @num_core_clks: Number of Core Clocks in clks[]
107 * @num_mod_clks: Number of Module Clocks in clks[] 108 * @num_mod_clks: Number of Module Clocks in clks[]
108 * @last_dt_core_clk: ID of the last Core Clock exported to DT 109 * @last_dt_core_clk: ID of the last Core Clock exported to DT
110 * @notifiers: Notifier chain to save/restore clock state for system resume
111 * @smstpcr_saved[].mask: Mask of SMSTPCR[] bits under our control
112 * @smstpcr_saved[].val: Saved values of SMSTPCR[]
109 */ 113 */
110struct cpg_mssr_priv { 114struct cpg_mssr_priv {
111#ifdef CONFIG_RESET_CONTROLLER 115#ifdef CONFIG_RESET_CONTROLLER
@@ -119,6 +123,12 @@ struct cpg_mssr_priv {
119 unsigned int num_core_clks; 123 unsigned int num_core_clks;
120 unsigned int num_mod_clks; 124 unsigned int num_mod_clks;
121 unsigned int last_dt_core_clk; 125 unsigned int last_dt_core_clk;
126
127 struct raw_notifier_head notifiers;
128 struct {
129 u32 mask;
130 u32 val;
131 } smstpcr_saved[ARRAY_SIZE(smstpcr)];
122}; 132};
123 133
124 134
@@ -293,7 +303,8 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
293 303
294 if (core->type == CLK_TYPE_DIV6P1) { 304 if (core->type == CLK_TYPE_DIV6P1) {
295 clk = cpg_div6_register(core->name, 1, &parent_name, 305 clk = cpg_div6_register(core->name, 1, &parent_name,
296 priv->base + core->offset); 306 priv->base + core->offset,
307 &priv->notifiers);
297 } else { 308 } else {
298 clk = clk_register_fixed_factor(NULL, core->name, 309 clk = clk_register_fixed_factor(NULL, core->name,
299 parent_name, 0, 310 parent_name, 0,
@@ -304,7 +315,8 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
304 default: 315 default:
305 if (info->cpg_clk_register) 316 if (info->cpg_clk_register)
306 clk = info->cpg_clk_register(dev, core, info, 317 clk = info->cpg_clk_register(dev, core, info,
307 priv->clks, priv->base); 318 priv->clks, priv->base,
319 &priv->notifiers);
308 else 320 else
309 dev_err(dev, "%s has unsupported core clock type %u\n", 321 dev_err(dev, "%s has unsupported core clock type %u\n",
310 core->name, core->type); 322 core->name, core->type);
@@ -382,6 +394,7 @@ static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
382 394
383 dev_dbg(dev, "Module clock %pC at %pCr Hz\n", clk, clk); 395 dev_dbg(dev, "Module clock %pC at %pCr Hz\n", clk, clk);
384 priv->clks[id] = clk; 396 priv->clks[id] = clk;
397 priv->smstpcr_saved[clock->index / 32].mask |= BIT(clock->index % 32);
385 return; 398 return;
386 399
387fail: 400fail:
@@ -680,6 +693,12 @@ static const struct of_device_id cpg_mssr_match[] = {
680 .data = &r8a7796_cpg_mssr_info, 693 .data = &r8a7796_cpg_mssr_info,
681 }, 694 },
682#endif 695#endif
696#ifdef CONFIG_CLK_R8A77970
697 {
698 .compatible = "renesas,r8a77970-cpg-mssr",
699 .data = &r8a77970_cpg_mssr_info,
700 },
701#endif
683#ifdef CONFIG_CLK_R8A77995 702#ifdef CONFIG_CLK_R8A77995
684 { 703 {
685 .compatible = "renesas,r8a77995-cpg-mssr", 704 .compatible = "renesas,r8a77995-cpg-mssr",
@@ -694,6 +713,85 @@ static void cpg_mssr_del_clk_provider(void *data)
694 of_clk_del_provider(data); 713 of_clk_del_provider(data);
695} 714}
696 715
716#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
717static int cpg_mssr_suspend_noirq(struct device *dev)
718{
719 struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
720 unsigned int reg;
721
722 /* This is the best we can do to check for the presence of PSCI */
723 if (!psci_ops.cpu_suspend)
724 return 0;
725
726 /* Save module registers with bits under our control */
727 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
728 if (priv->smstpcr_saved[reg].mask)
729 priv->smstpcr_saved[reg].val =
730 readl(priv->base + SMSTPCR(reg));
731 }
732
733 /* Save core clocks */
734 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_SUSPEND, NULL);
735
736 return 0;
737}
738
739static int cpg_mssr_resume_noirq(struct device *dev)
740{
741 struct cpg_mssr_priv *priv = dev_get_drvdata(dev);
742 unsigned int reg, i;
743 u32 mask, oldval, newval;
744
745 /* This is the best we can do to check for the presence of PSCI */
746 if (!psci_ops.cpu_suspend)
747 return 0;
748
749 /* Restore core clocks */
750 raw_notifier_call_chain(&priv->notifiers, PM_EVENT_RESUME, NULL);
751
752 /* Restore module clocks */
753 for (reg = 0; reg < ARRAY_SIZE(priv->smstpcr_saved); reg++) {
754 mask = priv->smstpcr_saved[reg].mask;
755 if (!mask)
756 continue;
757
758 oldval = readl(priv->base + SMSTPCR(reg));
759 newval = oldval & ~mask;
760 newval |= priv->smstpcr_saved[reg].val & mask;
761 if (newval == oldval)
762 continue;
763
764 writel(newval, priv->base + SMSTPCR(reg));
765
766 /* Wait until enabled clocks are really enabled */
767 mask &= ~priv->smstpcr_saved[reg].val;
768 if (!mask)
769 continue;
770
771 for (i = 1000; i > 0; --i) {
772 oldval = readl(priv->base + MSTPSR(reg));
773 if (!(oldval & mask))
774 break;
775 cpu_relax();
776 }
777
778 if (!i)
779 dev_warn(dev, "Failed to enable SMSTP %p[0x%x]\n",
780 priv->base + SMSTPCR(reg), oldval & mask);
781 }
782
783 return 0;
784}
785
786static const struct dev_pm_ops cpg_mssr_pm = {
787 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(cpg_mssr_suspend_noirq,
788 cpg_mssr_resume_noirq)
789};
790#define DEV_PM_OPS &cpg_mssr_pm
791#else
792#define DEV_PM_OPS NULL
793#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
794
697static int __init cpg_mssr_probe(struct platform_device *pdev) 795static int __init cpg_mssr_probe(struct platform_device *pdev)
698{ 796{
699 struct device *dev = &pdev->dev; 797 struct device *dev = &pdev->dev;
@@ -729,10 +827,12 @@ static int __init cpg_mssr_probe(struct platform_device *pdev)
729 if (!clks) 827 if (!clks)
730 return -ENOMEM; 828 return -ENOMEM;
731 829
830 dev_set_drvdata(dev, priv);
732 priv->clks = clks; 831 priv->clks = clks;
733 priv->num_core_clks = info->num_total_core_clks; 832 priv->num_core_clks = info->num_total_core_clks;
734 priv->num_mod_clks = info->num_hw_mod_clks; 833 priv->num_mod_clks = info->num_hw_mod_clks;
735 priv->last_dt_core_clk = info->last_dt_core_clk; 834 priv->last_dt_core_clk = info->last_dt_core_clk;
835 RAW_INIT_NOTIFIER_HEAD(&priv->notifiers);
736 836
737 for (i = 0; i < nclks; i++) 837 for (i = 0; i < nclks; i++)
738 clks[i] = ERR_PTR(-ENOENT); 838 clks[i] = ERR_PTR(-ENOENT);
@@ -769,6 +869,7 @@ static struct platform_driver cpg_mssr_driver = {
769 .driver = { 869 .driver = {
770 .name = "renesas-cpg-mssr", 870 .name = "renesas-cpg-mssr",
771 .of_match_table = cpg_mssr_match, 871 .of_match_table = cpg_mssr_match,
872 .pm = DEV_PM_OPS,
772 }, 873 },
773}; 874};
774 875
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 94b9071d1061..0745b0930308 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -127,7 +127,8 @@ struct cpg_mssr_info {
127 struct clk *(*cpg_clk_register)(struct device *dev, 127 struct clk *(*cpg_clk_register)(struct device *dev,
128 const struct cpg_core_clk *core, 128 const struct cpg_core_clk *core,
129 const struct cpg_mssr_info *info, 129 const struct cpg_mssr_info *info,
130 struct clk **clks, void __iomem *base); 130 struct clk **clks, void __iomem *base,
131 struct raw_notifier_head *notifiers);
131}; 132};
132 133
133extern const struct cpg_mssr_info r8a7743_cpg_mssr_info; 134extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
@@ -138,6 +139,7 @@ extern const struct cpg_mssr_info r8a7792_cpg_mssr_info;
138extern const struct cpg_mssr_info r8a7794_cpg_mssr_info; 139extern const struct cpg_mssr_info r8a7794_cpg_mssr_info;
139extern const struct cpg_mssr_info r8a7795_cpg_mssr_info; 140extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
140extern const struct cpg_mssr_info r8a7796_cpg_mssr_info; 141extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
142extern const struct cpg_mssr_info r8a77970_cpg_mssr_info;
141extern const struct cpg_mssr_info r8a77995_cpg_mssr_info; 143extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
142 144
143 145
diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index 0e09684d43a5..32c19c0f1e14 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -322,8 +322,6 @@ struct clk *rockchip_clk_register_cpuclk(const char *name,
322 sizeof(*rates) * nrates, 322 sizeof(*rates) * nrates,
323 GFP_KERNEL); 323 GFP_KERNEL);
324 if (!cpuclk->rate_table) { 324 if (!cpuclk->rate_table) {
325 pr_err("%s: could not allocate memory for cpuclk rates\n",
326 __func__);
327 ret = -ENOMEM; 325 ret = -ENOMEM;
328 goto unregister_notifier; 326 goto unregister_notifier;
329 } 327 }
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index 00ad0e5f8d66..67e73fd71f09 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -290,15 +290,15 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
290 RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY, 290 RK2928_CLKSEL_CON(0), 6, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
291 div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS), 291 div_core_peri_t, RK2928_CLKGATE_CON(0), 0, GFLAGS),
292 292
293 COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0, 293 COMPOSITE(ACLK_VEPU, "aclk_vepu", mux_pll_src_cpll_gpll_p, 0,
294 RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS, 294 RK2928_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 5, DFLAGS,
295 RK2928_CLKGATE_CON(3), 9, GFLAGS), 295 RK2928_CLKGATE_CON(3), 9, GFLAGS),
296 GATE(0, "hclk_vepu", "aclk_vepu", 0, 296 GATE(HCLK_VEPU, "hclk_vepu", "aclk_vepu", 0,
297 RK2928_CLKGATE_CON(3), 10, GFLAGS), 297 RK2928_CLKGATE_CON(3), 10, GFLAGS),
298 COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0, 298 COMPOSITE(ACLK_VDPU, "aclk_vdpu", mux_pll_src_cpll_gpll_p, 0,
299 RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS, 299 RK2928_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
300 RK2928_CLKGATE_CON(3), 11, GFLAGS), 300 RK2928_CLKGATE_CON(3), 11, GFLAGS),
301 GATE(0, "hclk_vdpu", "aclk_vdpu", 0, 301 GATE(HCLK_VDPU, "hclk_vdpu", "aclk_vdpu", 0,
302 RK2928_CLKGATE_CON(3), 12, GFLAGS), 302 RK2928_CLKGATE_CON(3), 12, GFLAGS),
303 303
304 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, 304 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
@@ -644,13 +644,13 @@ static struct rockchip_clk_branch rk3066a_clk_branches[] __initdata = {
644 644
645 GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS), 645 GATE(HCLK_I2S1, "hclk_i2s1", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
646 GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS), 646 GATE(HCLK_I2S2, "hclk_i2s2", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
647 GATE(0, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS), 647 GATE(HCLK_CIF1, "hclk_cif1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 6, GFLAGS),
648 GATE(0, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS), 648 GATE(0, "hclk_hdmi", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
649 649
650 GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED, 650 GATE(HCLK_OTG1, "hclk_usbotg1", "hclk_peri", CLK_IGNORE_UNUSED,
651 RK2928_CLKGATE_CON(5), 14, GFLAGS), 651 RK2928_CLKGATE_CON(5), 14, GFLAGS),
652 652
653 GATE(0, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS), 653 GATE(ACLK_CIF1, "aclk_cif1", "aclk_vio1", 0, RK2928_CLKGATE_CON(6), 7, GFLAGS),
654 654
655 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS), 655 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 8, GFLAGS),
656 GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS), 656 GATE(PCLK_TIMER2, "pclk_timer2", "pclk_cpu", 0, RK2928_CLKGATE_CON(7), 9, GFLAGS),
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index fc56565379dd..7c4d242f19c1 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -711,7 +711,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
711 GATE(PCLK_SIM, "pclk_sim", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 8, GFLAGS), 711 GATE(PCLK_SIM, "pclk_sim", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 8, GFLAGS),
712 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS), 712 GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS),
713 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS), 713 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
714 GATE(0, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS), 714 GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
715 GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS), 715 GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
716 716
717 /* 717 /*
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 23835001e8bd..ef8900bc077f 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -6,6 +6,7 @@
6obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o 6obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o clk-cpu.o
7obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o 7obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
8obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o 8obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
9obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4412-isp.o
9obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o 10obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
10obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o 11obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
11obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o 12obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index 6686e8ba61f9..d2c99d8916b8 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -457,8 +457,6 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
457 457
458 cpuclk->cfg = kmemdup(cfg, sizeof(*cfg) * num_cfgs, GFP_KERNEL); 458 cpuclk->cfg = kmemdup(cfg, sizeof(*cfg) * num_cfgs, GFP_KERNEL);
459 if (!cpuclk->cfg) { 459 if (!cpuclk->cfg) {
460 pr_err("%s: could not allocate memory for cpuclk data\n",
461 __func__);
462 ret = -ENOMEM; 460 ret = -ENOMEM;
463 goto unregister_clk_nb; 461 goto unregister_clk_nb;
464 } 462 }
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index b117783ed404..5bfc92ee3129 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -18,6 +18,7 @@
18#include <linux/syscore_ops.h> 18#include <linux/syscore_ops.h>
19#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
21 22
22#include <dt-bindings/clock/exynos-audss-clk.h> 23#include <dt-bindings/clock/exynos-audss-clk.h>
23 24
@@ -36,14 +37,13 @@ static struct clk *epll;
36#define ASS_CLK_DIV 0x4 37#define ASS_CLK_DIV 0x4
37#define ASS_CLK_GATE 0x8 38#define ASS_CLK_GATE 0x8
38 39
39#ifdef CONFIG_PM_SLEEP
40static unsigned long reg_save[][2] = { 40static unsigned long reg_save[][2] = {
41 { ASS_CLK_SRC, 0 }, 41 { ASS_CLK_SRC, 0 },
42 { ASS_CLK_DIV, 0 }, 42 { ASS_CLK_DIV, 0 },
43 { ASS_CLK_GATE, 0 }, 43 { ASS_CLK_GATE, 0 },
44}; 44};
45 45
46static int exynos_audss_clk_suspend(struct device *dev) 46static int __maybe_unused exynos_audss_clk_suspend(struct device *dev)
47{ 47{
48 int i; 48 int i;
49 49
@@ -53,7 +53,7 @@ static int exynos_audss_clk_suspend(struct device *dev)
53 return 0; 53 return 0;
54} 54}
55 55
56static int exynos_audss_clk_resume(struct device *dev) 56static int __maybe_unused exynos_audss_clk_resume(struct device *dev)
57{ 57{
58 int i; 58 int i;
59 59
@@ -62,7 +62,6 @@ static int exynos_audss_clk_resume(struct device *dev)
62 62
63 return 0; 63 return 0;
64} 64}
65#endif /* CONFIG_PM_SLEEP */
66 65
67struct exynos_audss_clk_drvdata { 66struct exynos_audss_clk_drvdata {
68 unsigned int has_adma_clk:1; 67 unsigned int has_adma_clk:1;
@@ -135,6 +134,7 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
135 const struct exynos_audss_clk_drvdata *variant; 134 const struct exynos_audss_clk_drvdata *variant;
136 struct clk_hw **clk_table; 135 struct clk_hw **clk_table;
137 struct resource *res; 136 struct resource *res;
137 struct device *dev = &pdev->dev;
138 int i, ret = 0; 138 int i, ret = 0;
139 139
140 variant = of_device_get_match_data(&pdev->dev); 140 variant = of_device_get_match_data(&pdev->dev);
@@ -142,15 +142,15 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
142 return -EINVAL; 142 return -EINVAL;
143 143
144 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 144 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
145 reg_base = devm_ioremap_resource(&pdev->dev, res); 145 reg_base = devm_ioremap_resource(dev, res);
146 if (IS_ERR(reg_base)) { 146 if (IS_ERR(reg_base)) {
147 dev_err(&pdev->dev, "failed to map audss registers\n"); 147 dev_err(dev, "failed to map audss registers\n");
148 return PTR_ERR(reg_base); 148 return PTR_ERR(reg_base);
149 } 149 }
150 150
151 epll = ERR_PTR(-ENODEV); 151 epll = ERR_PTR(-ENODEV);
152 152
153 clk_data = devm_kzalloc(&pdev->dev, 153 clk_data = devm_kzalloc(dev,
154 sizeof(*clk_data) + 154 sizeof(*clk_data) +
155 sizeof(*clk_data->hws) * EXYNOS_AUDSS_MAX_CLKS, 155 sizeof(*clk_data->hws) * EXYNOS_AUDSS_MAX_CLKS,
156 GFP_KERNEL); 156 GFP_KERNEL);
@@ -160,8 +160,8 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
160 clk_data->num = variant->num_clks; 160 clk_data->num = variant->num_clks;
161 clk_table = clk_data->hws; 161 clk_table = clk_data->hws;
162 162
163 pll_ref = devm_clk_get(&pdev->dev, "pll_ref"); 163 pll_ref = devm_clk_get(dev, "pll_ref");
164 pll_in = devm_clk_get(&pdev->dev, "pll_in"); 164 pll_in = devm_clk_get(dev, "pll_in");
165 if (!IS_ERR(pll_ref)) 165 if (!IS_ERR(pll_ref))
166 mout_audss_p[0] = __clk_get_name(pll_ref); 166 mout_audss_p[0] = __clk_get_name(pll_ref);
167 if (!IS_ERR(pll_in)) { 167 if (!IS_ERR(pll_in)) {
@@ -172,88 +172,103 @@ static int exynos_audss_clk_probe(struct platform_device *pdev)
172 172
173 ret = clk_prepare_enable(epll); 173 ret = clk_prepare_enable(epll);
174 if (ret) { 174 if (ret) {
175 dev_err(&pdev->dev, 175 dev_err(dev,
176 "failed to prepare the epll clock\n"); 176 "failed to prepare the epll clock\n");
177 return ret; 177 return ret;
178 } 178 }
179 } 179 }
180 } 180 }
181 clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(NULL, "mout_audss", 181
182 /*
183 * Enable runtime PM here to allow the clock core using runtime PM
184 * for the registered clocks. Additionally, we increase the runtime
185 * PM usage count before registering the clocks, to prevent the
186 * clock core from runtime suspending the device.
187 */
188 pm_runtime_get_noresume(dev);
189 pm_runtime_set_active(dev);
190 pm_runtime_enable(dev);
191
192 clk_table[EXYNOS_MOUT_AUDSS] = clk_hw_register_mux(dev, "mout_audss",
182 mout_audss_p, ARRAY_SIZE(mout_audss_p), 193 mout_audss_p, ARRAY_SIZE(mout_audss_p),
183 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, 194 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
184 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); 195 reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
185 196
186 cdclk = devm_clk_get(&pdev->dev, "cdclk"); 197 cdclk = devm_clk_get(dev, "cdclk");
187 sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio"); 198 sclk_audio = devm_clk_get(dev, "sclk_audio");
188 if (!IS_ERR(cdclk)) 199 if (!IS_ERR(cdclk))
189 mout_i2s_p[1] = __clk_get_name(cdclk); 200 mout_i2s_p[1] = __clk_get_name(cdclk);
190 if (!IS_ERR(sclk_audio)) 201 if (!IS_ERR(sclk_audio))
191 mout_i2s_p[2] = __clk_get_name(sclk_audio); 202 mout_i2s_p[2] = __clk_get_name(sclk_audio);
192 clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(NULL, "mout_i2s", 203 clk_table[EXYNOS_MOUT_I2S] = clk_hw_register_mux(dev, "mout_i2s",
193 mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 204 mout_i2s_p, ARRAY_SIZE(mout_i2s_p),
194 CLK_SET_RATE_NO_REPARENT, 205 CLK_SET_RATE_NO_REPARENT,
195 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock); 206 reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
196 207
197 clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(NULL, "dout_srp", 208 clk_table[EXYNOS_DOUT_SRP] = clk_hw_register_divider(dev, "dout_srp",
198 "mout_audss", CLK_SET_RATE_PARENT, 209 "mout_audss", CLK_SET_RATE_PARENT,
199 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock); 210 reg_base + ASS_CLK_DIV, 0, 4, 0, &lock);
200 211
201 clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(NULL, 212 clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev,
202 "dout_aud_bus", "dout_srp", CLK_SET_RATE_PARENT, 213 "dout_aud_bus", "dout_srp", CLK_SET_RATE_PARENT,
203 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock); 214 reg_base + ASS_CLK_DIV, 4, 4, 0, &lock);
204 215
205 clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(NULL, "dout_i2s", 216 clk_table[EXYNOS_DOUT_I2S] = clk_hw_register_divider(dev, "dout_i2s",
206 "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0, 217 "mout_i2s", 0, reg_base + ASS_CLK_DIV, 8, 4, 0,
207 &lock); 218 &lock);
208 219
209 clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(NULL, "srp_clk", 220 clk_table[EXYNOS_SRP_CLK] = clk_hw_register_gate(dev, "srp_clk",
210 "dout_srp", CLK_SET_RATE_PARENT, 221 "dout_srp", CLK_SET_RATE_PARENT,
211 reg_base + ASS_CLK_GATE, 0, 0, &lock); 222 reg_base + ASS_CLK_GATE, 0, 0, &lock);
212 223
213 clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(NULL, "i2s_bus", 224 clk_table[EXYNOS_I2S_BUS] = clk_hw_register_gate(dev, "i2s_bus",
214 "dout_aud_bus", CLK_SET_RATE_PARENT, 225 "dout_aud_bus", CLK_SET_RATE_PARENT,
215 reg_base + ASS_CLK_GATE, 2, 0, &lock); 226 reg_base + ASS_CLK_GATE, 2, 0, &lock);
216 227
217 clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(NULL, "sclk_i2s", 228 clk_table[EXYNOS_SCLK_I2S] = clk_hw_register_gate(dev, "sclk_i2s",
218 "dout_i2s", CLK_SET_RATE_PARENT, 229 "dout_i2s", CLK_SET_RATE_PARENT,
219 reg_base + ASS_CLK_GATE, 3, 0, &lock); 230 reg_base + ASS_CLK_GATE, 3, 0, &lock);
220 231
221 clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(NULL, "pcm_bus", 232 clk_table[EXYNOS_PCM_BUS] = clk_hw_register_gate(dev, "pcm_bus",
222 "sclk_pcm", CLK_SET_RATE_PARENT, 233 "sclk_pcm", CLK_SET_RATE_PARENT,
223 reg_base + ASS_CLK_GATE, 4, 0, &lock); 234 reg_base + ASS_CLK_GATE, 4, 0, &lock);
224 235
225 sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in"); 236 sclk_pcm_in = devm_clk_get(dev, "sclk_pcm_in");
226 if (!IS_ERR(sclk_pcm_in)) 237 if (!IS_ERR(sclk_pcm_in))
227 sclk_pcm_p = __clk_get_name(sclk_pcm_in); 238 sclk_pcm_p = __clk_get_name(sclk_pcm_in);
228 clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(NULL, "sclk_pcm", 239 clk_table[EXYNOS_SCLK_PCM] = clk_hw_register_gate(dev, "sclk_pcm",
229 sclk_pcm_p, CLK_SET_RATE_PARENT, 240 sclk_pcm_p, CLK_SET_RATE_PARENT,
230 reg_base + ASS_CLK_GATE, 5, 0, &lock); 241 reg_base + ASS_CLK_GATE, 5, 0, &lock);
231 242
232 if (variant->has_adma_clk) { 243 if (variant->has_adma_clk) {
233 clk_table[EXYNOS_ADMA] = clk_hw_register_gate(NULL, "adma", 244 clk_table[EXYNOS_ADMA] = clk_hw_register_gate(dev, "adma",
234 "dout_srp", CLK_SET_RATE_PARENT, 245 "dout_srp", CLK_SET_RATE_PARENT,
235 reg_base + ASS_CLK_GATE, 9, 0, &lock); 246 reg_base + ASS_CLK_GATE, 9, 0, &lock);
236 } 247 }
237 248
238 for (i = 0; i < clk_data->num; i++) { 249 for (i = 0; i < clk_data->num; i++) {
239 if (IS_ERR(clk_table[i])) { 250 if (IS_ERR(clk_table[i])) {
240 dev_err(&pdev->dev, "failed to register clock %d\n", i); 251 dev_err(dev, "failed to register clock %d\n", i);
241 ret = PTR_ERR(clk_table[i]); 252 ret = PTR_ERR(clk_table[i]);
242 goto unregister; 253 goto unregister;
243 } 254 }
244 } 255 }
245 256
246 ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get, 257 ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
247 clk_data); 258 clk_data);
248 if (ret) { 259 if (ret) {
249 dev_err(&pdev->dev, "failed to add clock provider\n"); 260 dev_err(dev, "failed to add clock provider\n");
250 goto unregister; 261 goto unregister;
251 } 262 }
252 263
264 pm_runtime_put_sync(dev);
265
253 return 0; 266 return 0;
254 267
255unregister: 268unregister:
256 exynos_audss_clk_teardown(); 269 exynos_audss_clk_teardown();
270 pm_runtime_put_sync(dev);
271 pm_runtime_disable(dev);
257 272
258 if (!IS_ERR(epll)) 273 if (!IS_ERR(epll))
259 clk_disable_unprepare(epll); 274 clk_disable_unprepare(epll);
@@ -266,6 +281,7 @@ static int exynos_audss_clk_remove(struct platform_device *pdev)
266 of_clk_del_provider(pdev->dev.of_node); 281 of_clk_del_provider(pdev->dev.of_node);
267 282
268 exynos_audss_clk_teardown(); 283 exynos_audss_clk_teardown();
284 pm_runtime_disable(&pdev->dev);
269 285
270 if (!IS_ERR(epll)) 286 if (!IS_ERR(epll))
271 clk_disable_unprepare(epll); 287 clk_disable_unprepare(epll);
@@ -274,8 +290,10 @@ static int exynos_audss_clk_remove(struct platform_device *pdev)
274} 290}
275 291
276static const struct dev_pm_ops exynos_audss_clk_pm_ops = { 292static const struct dev_pm_ops exynos_audss_clk_pm_ops = {
277 SET_LATE_SYSTEM_SLEEP_PM_OPS(exynos_audss_clk_suspend, 293 SET_RUNTIME_PM_OPS(exynos_audss_clk_suspend, exynos_audss_clk_resume,
278 exynos_audss_clk_resume) 294 NULL)
295 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
296 pm_runtime_force_resume)
279}; 297};
280 298
281static struct platform_driver exynos_audss_clk_driver = { 299static struct platform_driver exynos_audss_clk_driver = {
diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c
index a21aea062bae..f29fb5824005 100644
--- a/drivers/clk/samsung/clk-exynos-clkout.c
+++ b/drivers/clk/samsung/clk-exynos-clkout.c
@@ -144,8 +144,6 @@ static void __init exynos4_clkout_init(struct device_node *node)
144} 144}
145CLK_OF_DECLARE_DRIVER(exynos4210_clkout, "samsung,exynos4210-pmu", 145CLK_OF_DECLARE_DRIVER(exynos4210_clkout, "samsung,exynos4210-pmu",
146 exynos4_clkout_init); 146 exynos4_clkout_init);
147CLK_OF_DECLARE_DRIVER(exynos4212_clkout, "samsung,exynos4212-pmu",
148 exynos4_clkout_init);
149CLK_OF_DECLARE_DRIVER(exynos4412_clkout, "samsung,exynos4412-pmu", 147CLK_OF_DECLARE_DRIVER(exynos4412_clkout, "samsung,exynos4412-pmu",
150 exynos4_clkout_init); 148 exynos4_clkout_init);
151CLK_OF_DECLARE_DRIVER(exynos3250_clkout, "samsung,exynos3250-pmu", 149CLK_OF_DECLARE_DRIVER(exynos3250_clkout, "samsung,exynos3250-pmu",
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index d8d3cb67b402..134f25f2a913 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -550,9 +550,8 @@ static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __
550 550
551/* list of mux clocks supported in all exynos4 soc's */ 551/* list of mux clocks supported in all exynos4 soc's */
552static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = { 552static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = {
553 MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 553 MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
554 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0, 554 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
555 "mout_apll"),
556 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), 555 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),
557 MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), 556 MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),
558 MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), 557 MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
@@ -737,7 +736,7 @@ static const struct samsung_div_clock exynos4_div_clks[] __initconst = {
737 DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3), 736 DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
738 DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3), 737 DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
739 DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3), 738 DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
740 DIV(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3), 739 DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
741 DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3), 740 DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
742 DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3), 741 DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
743 DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6), 742 DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
@@ -837,6 +836,12 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
837 DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4), 836 DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4),
838 DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8), 837 DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8),
839 DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4), 838 DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4),
839 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
840 DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
841 DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
842};
843
844static struct samsung_div_clock exynos4x12_isp_div_clks[] = {
840 DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3, 845 DIV_F(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3,
841 CLK_GET_RATE_NOCACHE, 0), 846 CLK_GET_RATE_NOCACHE, 0),
842 DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3, 847 DIV_F(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3,
@@ -846,18 +851,10 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = {
846 4, 3, CLK_GET_RATE_NOCACHE, 0), 851 4, 3, CLK_GET_RATE_NOCACHE, 0),
847 DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 852 DIV_F(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1,
848 8, 3, CLK_GET_RATE_NOCACHE, 0), 853 8, 3, CLK_GET_RATE_NOCACHE, 0),
849 DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
850 DIV(CLK_DIV_C2C, "div_c2c", "mout_c2c", DIV_DMC1, 4, 3),
851 DIV(0, "div_c2c_aclk", "div_c2c", DIV_DMC1, 12, 3),
852}; 854};
853 855
854/* list of gate clocks supported in all exynos4 soc's */ 856/* list of gate clocks supported in all exynos4 soc's */
855static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = { 857static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = {
856 /*
857 * After all Exynos4 based platforms are migrated to use device tree,
858 * the device name and clock alias names specified below for some
859 * of the clocks can be removed.
860 */
861 GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0), 858 GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
862 GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0), 859 GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
863 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0), 860 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
@@ -1147,6 +1144,13 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
1147 0, 0), 1144 0, 0),
1148 GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3, 1145 GATE(CLK_I2S0, "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3,
1149 0, 0), 1146 0, 0),
1147 GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
1148 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0),
1149 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
1150 0),
1151};
1152
1153static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = {
1150 GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 1154 GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0,
1151 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1155 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1152 GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, 1156 GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1,
@@ -1199,24 +1203,6 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = {
1199 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1203 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1200 GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, 1204 GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
1201 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0), 1205 CLK_IGNORE_UNUSED | CLK_GET_RATE_NOCACHE, 0),
1202 GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
1203 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", GATE_IP_DMC, 24, 0, 0),
1204 GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0,
1205 0),
1206};
1207
1208static const struct samsung_clock_alias exynos4_aliases[] __initconst = {
1209 ALIAS(CLK_MOUT_CORE, NULL, "moutcore"),
1210 ALIAS(CLK_ARM_CLK, NULL, "armclk"),
1211 ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"),
1212};
1213
1214static const struct samsung_clock_alias exynos4210_aliases[] __initconst = {
1215 ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"),
1216};
1217
1218static const struct samsung_clock_alias exynos4x12_aliases[] __initconst = {
1219 ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"),
1220}; 1206};
1221 1207
1222/* 1208/*
@@ -1355,14 +1341,14 @@ static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst =
1355}; 1341};
1356 1342
1357static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = { 1343static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {
1358 [apll] = PLL_A(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll", 1344 [apll] = PLL(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1359 APLL_LOCK, APLL_CON0, "fout_apll", NULL), 1345 APLL_LOCK, APLL_CON0, NULL),
1360 [mpll] = PLL_A(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", 1346 [mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1361 E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL), 1347 E4210_MPLL_LOCK, E4210_MPLL_CON0, NULL),
1362 [epll] = PLL_A(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll", 1348 [epll] = PLL(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1363 EPLL_LOCK, EPLL_CON0, "fout_epll", NULL), 1349 EPLL_LOCK, EPLL_CON0, NULL),
1364 [vpll] = PLL_A(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc", 1350 [vpll] = PLL(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
1365 VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL), 1351 VPLL_LOCK, VPLL_CON0, NULL),
1366}; 1352};
1367 1353
1368static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = { 1354static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
@@ -1416,24 +1402,6 @@ static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
1416 { 0 }, 1402 { 0 },
1417}; 1403};
1418 1404
1419static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {
1420 { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
1421 { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
1422 { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
1423 { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
1424 { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },
1425 { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },
1426 { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
1427 { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
1428 { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
1429 { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
1430 { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
1431 { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
1432 { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
1433 { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },
1434 { 0 },
1435};
1436
1437#define E4412_CPU_DIV1(cores, hpm, copy) \ 1405#define E4412_CPU_DIV1(cores, hpm, copy) \
1438 (((cores) << 8) | ((hpm) << 4) | ((copy) << 0)) 1406 (((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
1439 1407
@@ -1527,8 +1495,6 @@ static void __init exynos4_clk_init(struct device_node *np,
1527 ARRAY_SIZE(exynos4210_div_clks)); 1495 ARRAY_SIZE(exynos4210_div_clks));
1528 samsung_clk_register_gate(ctx, exynos4210_gate_clks, 1496 samsung_clk_register_gate(ctx, exynos4210_gate_clks,
1529 ARRAY_SIZE(exynos4210_gate_clks)); 1497 ARRAY_SIZE(exynos4210_gate_clks));
1530 samsung_clk_register_alias(ctx, exynos4210_aliases,
1531 ARRAY_SIZE(exynos4210_aliases));
1532 samsung_clk_register_fixed_factor(ctx, 1498 samsung_clk_register_fixed_factor(ctx,
1533 exynos4210_fixed_factor_clks, 1499 exynos4210_fixed_factor_clks,
1534 ARRAY_SIZE(exynos4210_fixed_factor_clks)); 1500 ARRAY_SIZE(exynos4210_fixed_factor_clks));
@@ -1537,32 +1503,31 @@ static void __init exynos4_clk_init(struct device_node *np,
1537 e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d), 1503 e4210_armclk_d, ARRAY_SIZE(e4210_armclk_d),
1538 CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); 1504 CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
1539 } else { 1505 } else {
1506 struct resource res;
1507
1540 samsung_clk_register_mux(ctx, exynos4x12_mux_clks, 1508 samsung_clk_register_mux(ctx, exynos4x12_mux_clks,
1541 ARRAY_SIZE(exynos4x12_mux_clks)); 1509 ARRAY_SIZE(exynos4x12_mux_clks));
1542 samsung_clk_register_div(ctx, exynos4x12_div_clks, 1510 samsung_clk_register_div(ctx, exynos4x12_div_clks,
1543 ARRAY_SIZE(exynos4x12_div_clks)); 1511 ARRAY_SIZE(exynos4x12_div_clks));
1544 samsung_clk_register_gate(ctx, exynos4x12_gate_clks, 1512 samsung_clk_register_gate(ctx, exynos4x12_gate_clks,
1545 ARRAY_SIZE(exynos4x12_gate_clks)); 1513 ARRAY_SIZE(exynos4x12_gate_clks));
1546 samsung_clk_register_alias(ctx, exynos4x12_aliases,
1547 ARRAY_SIZE(exynos4x12_aliases));
1548 samsung_clk_register_fixed_factor(ctx, 1514 samsung_clk_register_fixed_factor(ctx,
1549 exynos4x12_fixed_factor_clks, 1515 exynos4x12_fixed_factor_clks,
1550 ARRAY_SIZE(exynos4x12_fixed_factor_clks)); 1516 ARRAY_SIZE(exynos4x12_fixed_factor_clks));
1551 if (of_machine_is_compatible("samsung,exynos4412")) { 1517
1552 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1518 of_address_to_resource(np, 0, &res);
1553 mout_core_p4x12[0], mout_core_p4x12[1], 0x14200, 1519 if (resource_size(&res) > 0x18000) {
1554 e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d), 1520 samsung_clk_register_div(ctx, exynos4x12_isp_div_clks,
1555 CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1); 1521 ARRAY_SIZE(exynos4x12_isp_div_clks));
1556 } else { 1522 samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks,
1557 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", 1523 ARRAY_SIZE(exynos4x12_isp_gate_clks));
1558 mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
1559 e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d),
1560 CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
1561 } 1524 }
1562 }
1563 1525
1564 samsung_clk_register_alias(ctx, exynos4_aliases, 1526 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1565 ARRAY_SIZE(exynos4_aliases)); 1527 mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,
1528 e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),
1529 CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);
1530 }
1566 1531
1567 if (soc == EXYNOS4X12) 1532 if (soc == EXYNOS4X12)
1568 exynos4x12_core_down_clock(); 1533 exynos4x12_core_down_clock();
diff --git a/drivers/clk/samsung/clk-exynos4412-isp.c b/drivers/clk/samsung/clk-exynos4412-isp.c
new file mode 100644
index 000000000000..d5f1ccb36300
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos4412-isp.c
@@ -0,0 +1,179 @@
1/*
2 * Copyright (c) 2017 Samsung Electronics Co., Ltd.
3 * Author: Marek Szyprowski <m.szyprowski@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for Exynos4412 ISP module.
10*/
11
12#include <dt-bindings/clock/exynos4.h>
13#include <linux/slab.h>
14#include <linux/clk.h>
15#include <linux/clk-provider.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19
20#include "clk.h"
21
22/* Exynos4x12 specific registers, which belong to ISP power domain */
23#define E4X12_DIV_ISP0 0x0300
24#define E4X12_DIV_ISP1 0x0304
25#define E4X12_GATE_ISP0 0x0800
26#define E4X12_GATE_ISP1 0x0804
27
28/*
29 * Support for CMU save/restore across system suspends
30 */
31static struct samsung_clk_reg_dump *exynos4x12_save_isp;
32
33static const unsigned long exynos4x12_clk_isp_save[] __initconst = {
34 E4X12_DIV_ISP0,
35 E4X12_DIV_ISP1,
36 E4X12_GATE_ISP0,
37 E4X12_GATE_ISP1,
38};
39
40PNAME(mout_user_aclk400_mcuisp_p4x12) = { "fin_pll", "div_aclk400_mcuisp", };
41
42static struct samsung_div_clock exynos4x12_isp_div_clks[] = {
43 DIV(CLK_ISP_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3),
44 DIV(CLK_ISP_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3),
45 DIV(CLK_ISP_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp",
46 E4X12_DIV_ISP1, 4, 3),
47 DIV(CLK_ISP_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0",
48 E4X12_DIV_ISP1, 8, 3),
49 DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
50};
51
52static struct samsung_gate_clock exynos4x12_isp_gate_clks[] = {
53 GATE(CLK_ISP_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, 0, 0),
54 GATE(CLK_ISP_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, 0, 0),
55 GATE(CLK_ISP_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, 0, 0),
56 GATE(CLK_ISP_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, 0, 0),
57 GATE(CLK_ISP_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, 0, 0),
58 GATE(CLK_ISP_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, 0, 0),
59 GATE(CLK_ISP_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, 0, 0),
60 GATE(CLK_ISP_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, 0, 0),
61 GATE(CLK_ISP_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, 0, 0),
62 GATE(CLK_ISP_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, 0, 0),
63 GATE(CLK_ISP_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11,
64 0, 0),
65 GATE(CLK_ISP_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12,
66 0, 0),
67 GATE(CLK_ISP_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20,
68 0, 0),
69 GATE(CLK_ISP_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21,
70 0, 0),
71 GATE(CLK_ISP_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23,
72 0, 0),
73 GATE(CLK_ISP_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24,
74 0, 0),
75 GATE(CLK_ISP_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25,
76 0, 0),
77 GATE(CLK_ISP_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26,
78 0, 0),
79 GATE(CLK_ISP_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27,
80 0, 0),
81 GATE(CLK_ISP_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, 0, 0),
82 GATE(CLK_ISP_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, 0, 0),
83 GATE(CLK_ISP_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31,
84 0, 0),
85 GATE(CLK_ISP_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0,
86 0, 0),
87 GATE(CLK_ISP_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4,
88 0, 0),
89 GATE(CLK_ISP_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12,
90 0, 0),
91 GATE(CLK_ISP_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
92 0, 0),
93};
94
95static int __maybe_unused exynos4x12_isp_clk_suspend(struct device *dev)
96{
97 struct samsung_clk_provider *ctx = dev_get_drvdata(dev);
98
99 samsung_clk_save(ctx->reg_base, exynos4x12_save_isp,
100 ARRAY_SIZE(exynos4x12_clk_isp_save));
101 return 0;
102}
103
104static int __maybe_unused exynos4x12_isp_clk_resume(struct device *dev)
105{
106 struct samsung_clk_provider *ctx = dev_get_drvdata(dev);
107
108 samsung_clk_restore(ctx->reg_base, exynos4x12_save_isp,
109 ARRAY_SIZE(exynos4x12_clk_isp_save));
110 return 0;
111}
112
113static int __init exynos4x12_isp_clk_probe(struct platform_device *pdev)
114{
115 struct samsung_clk_provider *ctx;
116 struct device *dev = &pdev->dev;
117 struct device_node *np = dev->of_node;
118 struct resource *res;
119 void __iomem *reg_base;
120
121 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
122 reg_base = devm_ioremap_resource(dev, res);
123 if (IS_ERR(reg_base)) {
124 dev_err(dev, "failed to map registers\n");
125 return PTR_ERR(reg_base);
126 }
127
128 exynos4x12_save_isp = samsung_clk_alloc_reg_dump(exynos4x12_clk_isp_save,
129 ARRAY_SIZE(exynos4x12_clk_isp_save));
130 if (!exynos4x12_save_isp)
131 return -ENOMEM;
132
133 ctx = samsung_clk_init(np, reg_base, CLK_NR_ISP_CLKS);
134 ctx->dev = dev;
135
136 platform_set_drvdata(pdev, ctx);
137
138 pm_runtime_set_active(dev);
139 pm_runtime_enable(dev);
140 pm_runtime_get_sync(dev);
141
142 samsung_clk_register_div(ctx, exynos4x12_isp_div_clks,
143 ARRAY_SIZE(exynos4x12_isp_div_clks));
144 samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks,
145 ARRAY_SIZE(exynos4x12_isp_gate_clks));
146
147 samsung_clk_of_add_provider(np, ctx);
148 pm_runtime_put(dev);
149
150 return 0;
151}
152
153static const struct of_device_id exynos4x12_isp_clk_of_match[] = {
154 { .compatible = "samsung,exynos4412-isp-clock", },
155 { },
156};
157
158static const struct dev_pm_ops exynos4x12_isp_pm_ops = {
159 SET_RUNTIME_PM_OPS(exynos4x12_isp_clk_suspend,
160 exynos4x12_isp_clk_resume, NULL)
161 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
162 pm_runtime_force_resume)
163};
164
165static struct platform_driver exynos4x12_isp_clk_driver __refdata = {
166 .driver = {
167 .name = "exynos4x12-isp-clk",
168 .of_match_table = exynos4x12_isp_clk_of_match,
169 .suppress_bind_attrs = true,
170 .pm = &exynos4x12_isp_pm_ops,
171 },
172 .probe = exynos4x12_isp_clk_probe,
173};
174
175static int __init exynos4x12_isp_clk_init(void)
176{
177 return platform_driver_register(&exynos4x12_isp_clk_driver);
178}
179core_initcall(exynos4x12_isp_clk_init);
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 27a227d6620c..9b073c98a891 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -293,14 +293,14 @@ static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = {
293 /* 293 /*
294 * CMU_CPU 294 * CMU_CPU
295 */ 295 */
296 MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, 296 MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
297 CLK_SET_RATE_PARENT, 0, "mout_apll"), 297 CLK_SET_RATE_PARENT, 0),
298 MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"), 298 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
299 299
300 /* 300 /*
301 * CMU_CORE 301 * CMU_CORE
302 */ 302 */
303 MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"), 303 MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),
304 304
305 /* 305 /*
306 * CMU_TOP 306 * CMU_TOP
@@ -391,7 +391,7 @@ static const struct samsung_div_clock exynos5250_div_clks[] __initconst = {
391 */ 391 */
392 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3), 392 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
393 DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3), 393 DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),
394 DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"), 394 DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
395 395
396 /* 396 /*
397 * CMU_TOP 397 * CMU_TOP
@@ -743,10 +743,10 @@ static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = {
743}; 743};
744 744
745static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = { 745static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {
746 [apll] = PLL_A(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", 746 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
747 APLL_LOCK, APLL_CON0, "fout_apll", NULL), 747 APLL_CON0, NULL),
748 [mpll] = PLL_A(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", 748 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
749 MPLL_LOCK, MPLL_CON0, "fout_mpll", NULL), 749 MPLL_CON0, NULL),
750 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK, 750 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
751 BPLL_CON0, NULL), 751 BPLL_CON0, NULL),
752 [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK, 752 [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 25601967d1cd..45d34f601e9e 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -600,8 +600,7 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
600 TOP_SPARE2, 4, 1), 600 TOP_SPARE2, 4, 1),
601 601
602 MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2), 602 MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
603 MUX_A(0, "mout_aclk400_mscl", mout_group1_p, 603 MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
604 SRC_TOP0, 4, 2, "aclk400_mscl"),
605 MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2), 604 MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
606 MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2), 605 MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
607 606
@@ -998,7 +997,7 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
998 GATE(0, "aclk400_isp", "mout_user_aclk400_isp", 997 GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
999 GATE_BUS_TOP, 16, 0, 0), 998 GATE_BUS_TOP, 16, 0, 0),
1000 GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", 999 GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
1001 GATE_BUS_TOP, 17, 0, 0), 1000 GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0),
1002 GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", 1001 GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
1003 GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0), 1002 GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0),
1004 GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", 1003 GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 11343a597093..db270908037a 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -9,9 +9,13 @@
9 * Common Clock Framework support for Exynos5433 SoC. 9 * Common Clock Framework support for Exynos5433 SoC.
10 */ 10 */
11 11
12#include <linux/clk.h>
12#include <linux/clk-provider.h> 13#include <linux/clk-provider.h>
13#include <linux/of.h> 14#include <linux/of.h>
14#include <linux/of_address.h> 15#include <linux/of_address.h>
16#include <linux/of_device.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
15 19
16#include <dt-bindings/clock/exynos5433.h> 20#include <dt-bindings/clock/exynos5433.h>
17 21
@@ -1991,6 +1995,14 @@ static const unsigned long fsys_clk_regs[] __initconst = {
1991 ENABLE_IP_FSYS1, 1995 ENABLE_IP_FSYS1,
1992}; 1996};
1993 1997
1998static const struct samsung_clk_reg_dump fsys_suspend_regs[] = {
1999 { MUX_SEL_FSYS0, 0 },
2000 { MUX_SEL_FSYS1, 0 },
2001 { MUX_SEL_FSYS2, 0 },
2002 { MUX_SEL_FSYS3, 0 },
2003 { MUX_SEL_FSYS4, 0 },
2004};
2005
1994static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = { 2006static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = {
1995 /* PHY clocks from USBDRD30_PHY */ 2007 /* PHY clocks from USBDRD30_PHY */
1996 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY, 2008 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
@@ -2296,16 +2308,11 @@ static const struct samsung_cmu_info fsys_cmu_info __initconst = {
2296 .nr_clk_ids = FSYS_NR_CLK, 2308 .nr_clk_ids = FSYS_NR_CLK,
2297 .clk_regs = fsys_clk_regs, 2309 .clk_regs = fsys_clk_regs,
2298 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs), 2310 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
2311 .suspend_regs = fsys_suspend_regs,
2312 .nr_suspend_regs = ARRAY_SIZE(fsys_suspend_regs),
2313 .clk_name = "aclk_fsys_200",
2299}; 2314};
2300 2315
2301static void __init exynos5433_cmu_fsys_init(struct device_node *np)
2302{
2303 samsung_cmu_register_one(np, &fsys_cmu_info);
2304}
2305
2306CLK_OF_DECLARE(exynos5433_cmu_fsys, "samsung,exynos5433-cmu-fsys",
2307 exynos5433_cmu_fsys_init);
2308
2309/* 2316/*
2310 * Register offset definitions for CMU_G2D 2317 * Register offset definitions for CMU_G2D
2311 */ 2318 */
@@ -2335,6 +2342,10 @@ static const unsigned long g2d_clk_regs[] __initconst = {
2335 DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D, 2342 DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
2336}; 2343};
2337 2344
2345static const struct samsung_clk_reg_dump g2d_suspend_regs[] = {
2346 { MUX_SEL_G2D0, 0 },
2347};
2348
2338/* list of all parent clock list */ 2349/* list of all parent clock list */
2339PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", }; 2350PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", };
2340PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", }; 2351PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", };
@@ -2420,16 +2431,11 @@ static const struct samsung_cmu_info g2d_cmu_info __initconst = {
2420 .nr_clk_ids = G2D_NR_CLK, 2431 .nr_clk_ids = G2D_NR_CLK,
2421 .clk_regs = g2d_clk_regs, 2432 .clk_regs = g2d_clk_regs,
2422 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs), 2433 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
2434 .suspend_regs = g2d_suspend_regs,
2435 .nr_suspend_regs = ARRAY_SIZE(g2d_suspend_regs),
2436 .clk_name = "aclk_g2d_400",
2423}; 2437};
2424 2438
2425static void __init exynos5433_cmu_g2d_init(struct device_node *np)
2426{
2427 samsung_cmu_register_one(np, &g2d_cmu_info);
2428}
2429
2430CLK_OF_DECLARE(exynos5433_cmu_g2d, "samsung,exynos5433-cmu-g2d",
2431 exynos5433_cmu_g2d_init);
2432
2433/* 2439/*
2434 * Register offset definitions for CMU_DISP 2440 * Register offset definitions for CMU_DISP
2435 */ 2441 */
@@ -2494,6 +2500,18 @@ static const unsigned long disp_clk_regs[] __initconst = {
2494 CLKOUT_CMU_DISP_DIV_STAT, 2500 CLKOUT_CMU_DISP_DIV_STAT,
2495}; 2501};
2496 2502
2503static const struct samsung_clk_reg_dump disp_suspend_regs[] = {
2504 /* PLL has to be enabled for suspend */
2505 { DISP_PLL_CON0, 0x85f40502 },
2506 /* ignore status of external PHY muxes during suspend to avoid hangs */
2507 { MUX_IGNORE_DISP2, 0x00111111 },
2508 { MUX_SEL_DISP0, 0 },
2509 { MUX_SEL_DISP1, 0 },
2510 { MUX_SEL_DISP2, 0 },
2511 { MUX_SEL_DISP3, 0 },
2512 { MUX_SEL_DISP4, 0 },
2513};
2514
2497/* list of all parent clock list */ 2515/* list of all parent clock list */
2498PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", }; 2516PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", };
2499PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", }; 2517PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", };
@@ -2841,16 +2859,11 @@ static const struct samsung_cmu_info disp_cmu_info __initconst = {
2841 .nr_clk_ids = DISP_NR_CLK, 2859 .nr_clk_ids = DISP_NR_CLK,
2842 .clk_regs = disp_clk_regs, 2860 .clk_regs = disp_clk_regs,
2843 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs), 2861 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
2862 .suspend_regs = disp_suspend_regs,
2863 .nr_suspend_regs = ARRAY_SIZE(disp_suspend_regs),
2864 .clk_name = "aclk_disp_333",
2844}; 2865};
2845 2866
2846static void __init exynos5433_cmu_disp_init(struct device_node *np)
2847{
2848 samsung_cmu_register_one(np, &disp_cmu_info);
2849}
2850
2851CLK_OF_DECLARE(exynos5433_cmu_disp, "samsung,exynos5433-cmu-disp",
2852 exynos5433_cmu_disp_init);
2853
2854/* 2867/*
2855 * Register offset definitions for CMU_AUD 2868 * Register offset definitions for CMU_AUD
2856 */ 2869 */
@@ -2885,6 +2898,11 @@ static const unsigned long aud_clk_regs[] __initconst = {
2885 ENABLE_IP_AUD1, 2898 ENABLE_IP_AUD1,
2886}; 2899};
2887 2900
2901static const struct samsung_clk_reg_dump aud_suspend_regs[] = {
2902 { MUX_SEL_AUD0, 0 },
2903 { MUX_SEL_AUD1, 0 },
2904};
2905
2888/* list of all parent clock list */ 2906/* list of all parent clock list */
2889PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", }; 2907PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", };
2890PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",}; 2908PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
@@ -3011,16 +3029,11 @@ static const struct samsung_cmu_info aud_cmu_info __initconst = {
3011 .nr_clk_ids = AUD_NR_CLK, 3029 .nr_clk_ids = AUD_NR_CLK,
3012 .clk_regs = aud_clk_regs, 3030 .clk_regs = aud_clk_regs,
3013 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs), 3031 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
3032 .suspend_regs = aud_suspend_regs,
3033 .nr_suspend_regs = ARRAY_SIZE(aud_suspend_regs),
3034 .clk_name = "fout_aud_pll",
3014}; 3035};
3015 3036
3016static void __init exynos5433_cmu_aud_init(struct device_node *np)
3017{
3018 samsung_cmu_register_one(np, &aud_cmu_info);
3019}
3020CLK_OF_DECLARE(exynos5433_cmu_aud, "samsung,exynos5433-cmu-aud",
3021 exynos5433_cmu_aud_init);
3022
3023
3024/* 3037/*
3025 * Register offset definitions for CMU_BUS{0|1|2} 3038 * Register offset definitions for CMU_BUS{0|1|2}
3026 */ 3039 */
@@ -3222,6 +3235,10 @@ static const unsigned long g3d_clk_regs[] __initconst = {
3222 CLK_STOPCTRL, 3235 CLK_STOPCTRL,
3223}; 3236};
3224 3237
3238static const struct samsung_clk_reg_dump g3d_suspend_regs[] = {
3239 { MUX_SEL_G3D, 0 },
3240};
3241
3225/* list of all parent clock list */ 3242/* list of all parent clock list */
3226PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", }; 3243PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", };
3227PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", }; 3244PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", };
@@ -3295,15 +3312,11 @@ static const struct samsung_cmu_info g3d_cmu_info __initconst = {
3295 .nr_clk_ids = G3D_NR_CLK, 3312 .nr_clk_ids = G3D_NR_CLK,
3296 .clk_regs = g3d_clk_regs, 3313 .clk_regs = g3d_clk_regs,
3297 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), 3314 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
3315 .suspend_regs = g3d_suspend_regs,
3316 .nr_suspend_regs = ARRAY_SIZE(g3d_suspend_regs),
3317 .clk_name = "aclk_g3d_400",
3298}; 3318};
3299 3319
3300static void __init exynos5433_cmu_g3d_init(struct device_node *np)
3301{
3302 samsung_cmu_register_one(np, &g3d_cmu_info);
3303}
3304CLK_OF_DECLARE(exynos5433_cmu_g3d, "samsung,exynos5433-cmu-g3d",
3305 exynos5433_cmu_g3d_init);
3306
3307/* 3320/*
3308 * Register offset definitions for CMU_GSCL 3321 * Register offset definitions for CMU_GSCL
3309 */ 3322 */
@@ -3342,6 +3355,12 @@ static const unsigned long gscl_clk_regs[] __initconst = {
3342 ENABLE_IP_GSCL_SECURE_SMMU_GSCL2, 3355 ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
3343}; 3356};
3344 3357
3358static const struct samsung_clk_reg_dump gscl_suspend_regs[] = {
3359 { MUX_SEL_GSCL, 0 },
3360 { ENABLE_ACLK_GSCL, 0xfff },
3361 { ENABLE_PCLK_GSCL, 0xff },
3362};
3363
3345/* list of all parent clock list */ 3364/* list of all parent clock list */
3346PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", }; 3365PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", };
3347PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", }; 3366PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", };
@@ -3436,15 +3455,11 @@ static const struct samsung_cmu_info gscl_cmu_info __initconst = {
3436 .nr_clk_ids = GSCL_NR_CLK, 3455 .nr_clk_ids = GSCL_NR_CLK,
3437 .clk_regs = gscl_clk_regs, 3456 .clk_regs = gscl_clk_regs,
3438 .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs), 3457 .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
3458 .suspend_regs = gscl_suspend_regs,
3459 .nr_suspend_regs = ARRAY_SIZE(gscl_suspend_regs),
3460 .clk_name = "aclk_gscl_111",
3439}; 3461};
3440 3462
3441static void __init exynos5433_cmu_gscl_init(struct device_node *np)
3442{
3443 samsung_cmu_register_one(np, &gscl_cmu_info);
3444}
3445CLK_OF_DECLARE(exynos5433_cmu_gscl, "samsung,exynos5433-cmu-gscl",
3446 exynos5433_cmu_gscl_init);
3447
3448/* 3463/*
3449 * Register offset definitions for CMU_APOLLO 3464 * Register offset definitions for CMU_APOLLO
3450 */ 3465 */
@@ -3970,6 +3985,11 @@ static const unsigned long mscl_clk_regs[] __initconst = {
3970 ENABLE_IP_MSCL_SECURE_SMMU_JPEG, 3985 ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
3971}; 3986};
3972 3987
3988static const struct samsung_clk_reg_dump mscl_suspend_regs[] = {
3989 { MUX_SEL_MSCL0, 0 },
3990 { MUX_SEL_MSCL1, 0 },
3991};
3992
3973/* list of all parent clock list */ 3993/* list of all parent clock list */
3974PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", }; 3994PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", };
3975PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", }; 3995PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", };
@@ -4082,15 +4102,11 @@ static const struct samsung_cmu_info mscl_cmu_info __initconst = {
4082 .nr_clk_ids = MSCL_NR_CLK, 4102 .nr_clk_ids = MSCL_NR_CLK,
4083 .clk_regs = mscl_clk_regs, 4103 .clk_regs = mscl_clk_regs,
4084 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs), 4104 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
4105 .suspend_regs = mscl_suspend_regs,
4106 .nr_suspend_regs = ARRAY_SIZE(mscl_suspend_regs),
4107 .clk_name = "aclk_mscl_400",
4085}; 4108};
4086 4109
4087static void __init exynos5433_cmu_mscl_init(struct device_node *np)
4088{
4089 samsung_cmu_register_one(np, &mscl_cmu_info);
4090}
4091CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl",
4092 exynos5433_cmu_mscl_init);
4093
4094/* 4110/*
4095 * Register offset definitions for CMU_MFC 4111 * Register offset definitions for CMU_MFC
4096 */ 4112 */
@@ -4120,6 +4136,10 @@ static const unsigned long mfc_clk_regs[] __initconst = {
4120 ENABLE_IP_MFC_SECURE_SMMU_MFC, 4136 ENABLE_IP_MFC_SECURE_SMMU_MFC,
4121}; 4137};
4122 4138
4139static const struct samsung_clk_reg_dump mfc_suspend_regs[] = {
4140 { MUX_SEL_MFC, 0 },
4141};
4142
4123PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", }; 4143PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", };
4124 4144
4125static const struct samsung_mux_clock mfc_mux_clks[] __initconst = { 4145static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
@@ -4190,15 +4210,11 @@ static const struct samsung_cmu_info mfc_cmu_info __initconst = {
4190 .nr_clk_ids = MFC_NR_CLK, 4210 .nr_clk_ids = MFC_NR_CLK,
4191 .clk_regs = mfc_clk_regs, 4211 .clk_regs = mfc_clk_regs,
4192 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs), 4212 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
4213 .suspend_regs = mfc_suspend_regs,
4214 .nr_suspend_regs = ARRAY_SIZE(mfc_suspend_regs),
4215 .clk_name = "aclk_mfc_400",
4193}; 4216};
4194 4217
4195static void __init exynos5433_cmu_mfc_init(struct device_node *np)
4196{
4197 samsung_cmu_register_one(np, &mfc_cmu_info);
4198}
4199CLK_OF_DECLARE(exynos5433_cmu_mfc, "samsung,exynos5433-cmu-mfc",
4200 exynos5433_cmu_mfc_init);
4201
4202/* 4218/*
4203 * Register offset definitions for CMU_HEVC 4219 * Register offset definitions for CMU_HEVC
4204 */ 4220 */
@@ -4228,6 +4244,10 @@ static const unsigned long hevc_clk_regs[] __initconst = {
4228 ENABLE_IP_HEVC_SECURE_SMMU_HEVC, 4244 ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
4229}; 4245};
4230 4246
4247static const struct samsung_clk_reg_dump hevc_suspend_regs[] = {
4248 { MUX_SEL_HEVC, 0 },
4249};
4250
4231PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", }; 4251PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", };
4232 4252
4233static const struct samsung_mux_clock hevc_mux_clks[] __initconst = { 4253static const struct samsung_mux_clock hevc_mux_clks[] __initconst = {
@@ -4300,15 +4320,11 @@ static const struct samsung_cmu_info hevc_cmu_info __initconst = {
4300 .nr_clk_ids = HEVC_NR_CLK, 4320 .nr_clk_ids = HEVC_NR_CLK,
4301 .clk_regs = hevc_clk_regs, 4321 .clk_regs = hevc_clk_regs,
4302 .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs), 4322 .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs),
4323 .suspend_regs = hevc_suspend_regs,
4324 .nr_suspend_regs = ARRAY_SIZE(hevc_suspend_regs),
4325 .clk_name = "aclk_hevc_400",
4303}; 4326};
4304 4327
4305static void __init exynos5433_cmu_hevc_init(struct device_node *np)
4306{
4307 samsung_cmu_register_one(np, &hevc_cmu_info);
4308}
4309CLK_OF_DECLARE(exynos5433_cmu_hevc, "samsung,exynos5433-cmu-hevc",
4310 exynos5433_cmu_hevc_init);
4311
4312/* 4328/*
4313 * Register offset definitions for CMU_ISP 4329 * Register offset definitions for CMU_ISP
4314 */ 4330 */
@@ -4342,6 +4358,10 @@ static const unsigned long isp_clk_regs[] __initconst = {
4342 ENABLE_IP_ISP3, 4358 ENABLE_IP_ISP3,
4343}; 4359};
4344 4360
4361static const struct samsung_clk_reg_dump isp_suspend_regs[] = {
4362 { MUX_SEL_ISP, 0 },
4363};
4364
4345PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", }; 4365PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", };
4346PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", }; 4366PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", };
4347 4367
@@ -4553,15 +4573,11 @@ static const struct samsung_cmu_info isp_cmu_info __initconst = {
4553 .nr_clk_ids = ISP_NR_CLK, 4573 .nr_clk_ids = ISP_NR_CLK,
4554 .clk_regs = isp_clk_regs, 4574 .clk_regs = isp_clk_regs,
4555 .nr_clk_regs = ARRAY_SIZE(isp_clk_regs), 4575 .nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
4576 .suspend_regs = isp_suspend_regs,
4577 .nr_suspend_regs = ARRAY_SIZE(isp_suspend_regs),
4578 .clk_name = "aclk_isp_400",
4556}; 4579};
4557 4580
4558static void __init exynos5433_cmu_isp_init(struct device_node *np)
4559{
4560 samsung_cmu_register_one(np, &isp_cmu_info);
4561}
4562CLK_OF_DECLARE(exynos5433_cmu_isp, "samsung,exynos5433-cmu-isp",
4563 exynos5433_cmu_isp_init);
4564
4565/* 4581/*
4566 * Register offset definitions for CMU_CAM0 4582 * Register offset definitions for CMU_CAM0
4567 */ 4583 */
@@ -4625,6 +4641,15 @@ static const unsigned long cam0_clk_regs[] __initconst = {
4625 ENABLE_IP_CAM02, 4641 ENABLE_IP_CAM02,
4626 ENABLE_IP_CAM03, 4642 ENABLE_IP_CAM03,
4627}; 4643};
4644
4645static const struct samsung_clk_reg_dump cam0_suspend_regs[] = {
4646 { MUX_SEL_CAM00, 0 },
4647 { MUX_SEL_CAM01, 0 },
4648 { MUX_SEL_CAM02, 0 },
4649 { MUX_SEL_CAM03, 0 },
4650 { MUX_SEL_CAM04, 0 },
4651};
4652
4628PNAME(mout_aclk_cam0_333_user_p) = { "oscclk", "aclk_cam0_333", }; 4653PNAME(mout_aclk_cam0_333_user_p) = { "oscclk", "aclk_cam0_333", };
4629PNAME(mout_aclk_cam0_400_user_p) = { "oscclk", "aclk_cam0_400", }; 4654PNAME(mout_aclk_cam0_400_user_p) = { "oscclk", "aclk_cam0_400", };
4630PNAME(mout_aclk_cam0_552_user_p) = { "oscclk", "aclk_cam0_552", }; 4655PNAME(mout_aclk_cam0_552_user_p) = { "oscclk", "aclk_cam0_552", };
@@ -5030,15 +5055,11 @@ static const struct samsung_cmu_info cam0_cmu_info __initconst = {
5030 .nr_clk_ids = CAM0_NR_CLK, 5055 .nr_clk_ids = CAM0_NR_CLK,
5031 .clk_regs = cam0_clk_regs, 5056 .clk_regs = cam0_clk_regs,
5032 .nr_clk_regs = ARRAY_SIZE(cam0_clk_regs), 5057 .nr_clk_regs = ARRAY_SIZE(cam0_clk_regs),
5058 .suspend_regs = cam0_suspend_regs,
5059 .nr_suspend_regs = ARRAY_SIZE(cam0_suspend_regs),
5060 .clk_name = "aclk_cam0_400",
5033}; 5061};
5034 5062
5035static void __init exynos5433_cmu_cam0_init(struct device_node *np)
5036{
5037 samsung_cmu_register_one(np, &cam0_cmu_info);
5038}
5039CLK_OF_DECLARE(exynos5433_cmu_cam0, "samsung,exynos5433-cmu-cam0",
5040 exynos5433_cmu_cam0_init);
5041
5042/* 5063/*
5043 * Register offset definitions for CMU_CAM1 5064 * Register offset definitions for CMU_CAM1
5044 */ 5065 */
@@ -5085,6 +5106,12 @@ static const unsigned long cam1_clk_regs[] __initconst = {
5085 ENABLE_IP_CAM12, 5106 ENABLE_IP_CAM12,
5086}; 5107};
5087 5108
5109static const struct samsung_clk_reg_dump cam1_suspend_regs[] = {
5110 { MUX_SEL_CAM10, 0 },
5111 { MUX_SEL_CAM11, 0 },
5112 { MUX_SEL_CAM12, 0 },
5113};
5114
5088PNAME(mout_sclk_isp_uart_user_p) = { "oscclk", "sclk_isp_uart_cam1", }; 5115PNAME(mout_sclk_isp_uart_user_p) = { "oscclk", "sclk_isp_uart_cam1", };
5089PNAME(mout_sclk_isp_spi1_user_p) = { "oscclk", "sclk_isp_spi1_cam1", }; 5116PNAME(mout_sclk_isp_spi1_user_p) = { "oscclk", "sclk_isp_spi1_cam1", };
5090PNAME(mout_sclk_isp_spi0_user_p) = { "oscclk", "sclk_isp_spi0_cam1", }; 5117PNAME(mout_sclk_isp_spi0_user_p) = { "oscclk", "sclk_isp_spi0_cam1", };
@@ -5403,11 +5430,223 @@ static const struct samsung_cmu_info cam1_cmu_info __initconst = {
5403 .nr_clk_ids = CAM1_NR_CLK, 5430 .nr_clk_ids = CAM1_NR_CLK,
5404 .clk_regs = cam1_clk_regs, 5431 .clk_regs = cam1_clk_regs,
5405 .nr_clk_regs = ARRAY_SIZE(cam1_clk_regs), 5432 .nr_clk_regs = ARRAY_SIZE(cam1_clk_regs),
5433 .suspend_regs = cam1_suspend_regs,
5434 .nr_suspend_regs = ARRAY_SIZE(cam1_suspend_regs),
5435 .clk_name = "aclk_cam1_400",
5436};
5437
5438
5439struct exynos5433_cmu_data {
5440 struct samsung_clk_reg_dump *clk_save;
5441 unsigned int nr_clk_save;
5442 const struct samsung_clk_reg_dump *clk_suspend;
5443 unsigned int nr_clk_suspend;
5444
5445 struct clk *clk;
5446 struct clk **pclks;
5447 int nr_pclks;
5448
5449 /* must be the last entry */
5450 struct samsung_clk_provider ctx;
5451};
5452
5453static int __maybe_unused exynos5433_cmu_suspend(struct device *dev)
5454{
5455 struct exynos5433_cmu_data *data = dev_get_drvdata(dev);
5456 int i;
5457
5458 samsung_clk_save(data->ctx.reg_base, data->clk_save,
5459 data->nr_clk_save);
5460
5461 for (i = 0; i < data->nr_pclks; i++)
5462 clk_prepare_enable(data->pclks[i]);
5463
5464 /* for suspend some registers have to be set to certain values */
5465 samsung_clk_restore(data->ctx.reg_base, data->clk_suspend,
5466 data->nr_clk_suspend);
5467
5468 for (i = 0; i < data->nr_pclks; i++)
5469 clk_disable_unprepare(data->pclks[i]);
5470
5471 clk_disable_unprepare(data->clk);
5472
5473 return 0;
5474}
5475
5476static int __maybe_unused exynos5433_cmu_resume(struct device *dev)
5477{
5478 struct exynos5433_cmu_data *data = dev_get_drvdata(dev);
5479 int i;
5480
5481 clk_prepare_enable(data->clk);
5482
5483 for (i = 0; i < data->nr_pclks; i++)
5484 clk_prepare_enable(data->pclks[i]);
5485
5486 samsung_clk_restore(data->ctx.reg_base, data->clk_save,
5487 data->nr_clk_save);
5488
5489 for (i = 0; i < data->nr_pclks; i++)
5490 clk_disable_unprepare(data->pclks[i]);
5491
5492 return 0;
5493}
5494
5495static int __init exynos5433_cmu_probe(struct platform_device *pdev)
5496{
5497 const struct samsung_cmu_info *info;
5498 struct exynos5433_cmu_data *data;
5499 struct samsung_clk_provider *ctx;
5500 struct device *dev = &pdev->dev;
5501 struct resource *res;
5502 void __iomem *reg_base;
5503 int i;
5504
5505 info = of_device_get_match_data(dev);
5506
5507 data = devm_kzalloc(dev, sizeof(*data) +
5508 sizeof(*data->ctx.clk_data.hws) * info->nr_clk_ids,
5509 GFP_KERNEL);
5510 if (!data)
5511 return -ENOMEM;
5512 ctx = &data->ctx;
5513
5514 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5515 reg_base = devm_ioremap_resource(dev, res);
5516 if (IS_ERR(reg_base)) {
5517 dev_err(dev, "failed to map registers\n");
5518 return PTR_ERR(reg_base);
5519 }
5520
5521 for (i = 0; i < info->nr_clk_ids; ++i)
5522 ctx->clk_data.hws[i] = ERR_PTR(-ENOENT);
5523
5524 ctx->clk_data.num = info->nr_clk_ids;
5525 ctx->reg_base = reg_base;
5526 ctx->dev = dev;
5527 spin_lock_init(&ctx->lock);
5528
5529 data->clk_save = samsung_clk_alloc_reg_dump(info->clk_regs,
5530 info->nr_clk_regs);
5531 data->nr_clk_save = info->nr_clk_regs;
5532 data->clk_suspend = info->suspend_regs;
5533 data->nr_clk_suspend = info->nr_suspend_regs;
5534 data->nr_pclks = of_count_phandle_with_args(dev->of_node, "clocks",
5535 "#clock-cells");
5536 if (data->nr_pclks > 0) {
5537 data->pclks = devm_kcalloc(dev, sizeof(struct clk *),
5538 data->nr_pclks, GFP_KERNEL);
5539
5540 for (i = 0; i < data->nr_pclks; i++) {
5541 struct clk *clk = of_clk_get(dev->of_node, i);
5542
5543 if (IS_ERR(clk))
5544 return PTR_ERR(clk);
5545 data->pclks[i] = clk;
5546 }
5547 }
5548
5549 if (info->clk_name)
5550 data->clk = clk_get(dev, info->clk_name);
5551 clk_prepare_enable(data->clk);
5552
5553 platform_set_drvdata(pdev, data);
5554
5555 /*
5556 * Enable runtime PM here to allow the clock core using runtime PM
5557 * for the registered clocks. Additionally, we increase the runtime
5558 * PM usage count before registering the clocks, to prevent the
5559 * clock core from runtime suspending the device.
5560 */
5561 pm_runtime_get_noresume(dev);
5562 pm_runtime_set_active(dev);
5563 pm_runtime_enable(dev);
5564
5565 if (info->pll_clks)
5566 samsung_clk_register_pll(ctx, info->pll_clks, info->nr_pll_clks,
5567 reg_base);
5568 if (info->mux_clks)
5569 samsung_clk_register_mux(ctx, info->mux_clks,
5570 info->nr_mux_clks);
5571 if (info->div_clks)
5572 samsung_clk_register_div(ctx, info->div_clks,
5573 info->nr_div_clks);
5574 if (info->gate_clks)
5575 samsung_clk_register_gate(ctx, info->gate_clks,
5576 info->nr_gate_clks);
5577 if (info->fixed_clks)
5578 samsung_clk_register_fixed_rate(ctx, info->fixed_clks,
5579 info->nr_fixed_clks);
5580 if (info->fixed_factor_clks)
5581 samsung_clk_register_fixed_factor(ctx, info->fixed_factor_clks,
5582 info->nr_fixed_factor_clks);
5583
5584 samsung_clk_of_add_provider(dev->of_node, ctx);
5585 pm_runtime_put_sync(dev);
5586
5587 return 0;
5588}
5589
5590static const struct of_device_id exynos5433_cmu_of_match[] = {
5591 {
5592 .compatible = "samsung,exynos5433-cmu-aud",
5593 .data = &aud_cmu_info,
5594 }, {
5595 .compatible = "samsung,exynos5433-cmu-cam0",
5596 .data = &cam0_cmu_info,
5597 }, {
5598 .compatible = "samsung,exynos5433-cmu-cam1",
5599 .data = &cam1_cmu_info,
5600 }, {
5601 .compatible = "samsung,exynos5433-cmu-disp",
5602 .data = &disp_cmu_info,
5603 }, {
5604 .compatible = "samsung,exynos5433-cmu-g2d",
5605 .data = &g2d_cmu_info,
5606 }, {
5607 .compatible = "samsung,exynos5433-cmu-g3d",
5608 .data = &g3d_cmu_info,
5609 }, {
5610 .compatible = "samsung,exynos5433-cmu-fsys",
5611 .data = &fsys_cmu_info,
5612 }, {
5613 .compatible = "samsung,exynos5433-cmu-gscl",
5614 .data = &gscl_cmu_info,
5615 }, {
5616 .compatible = "samsung,exynos5433-cmu-mfc",
5617 .data = &mfc_cmu_info,
5618 }, {
5619 .compatible = "samsung,exynos5433-cmu-hevc",
5620 .data = &hevc_cmu_info,
5621 }, {
5622 .compatible = "samsung,exynos5433-cmu-isp",
5623 .data = &isp_cmu_info,
5624 }, {
5625 .compatible = "samsung,exynos5433-cmu-mscl",
5626 .data = &mscl_cmu_info,
5627 }, {
5628 },
5629};
5630
5631static const struct dev_pm_ops exynos5433_cmu_pm_ops = {
5632 SET_RUNTIME_PM_OPS(exynos5433_cmu_suspend, exynos5433_cmu_resume,
5633 NULL)
5634 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
5635 pm_runtime_force_resume)
5636};
5637
5638static struct platform_driver exynos5433_cmu_driver __refdata = {
5639 .driver = {
5640 .name = "exynos5433-cmu",
5641 .of_match_table = exynos5433_cmu_of_match,
5642 .suppress_bind_attrs = true,
5643 .pm = &exynos5433_cmu_pm_ops,
5644 },
5645 .probe = exynos5433_cmu_probe,
5406}; 5646};
5407 5647
5408static void __init exynos5433_cmu_cam1_init(struct device_node *np) 5648static int __init exynos5433_cmu_init(void)
5409{ 5649{
5410 samsung_cmu_register_one(np, &cam1_cmu_info); 5650 return platform_driver_register(&exynos5433_cmu_driver);
5411} 5651}
5412CLK_OF_DECLARE(exynos5433_cmu_cam1, "samsung,exynos5433-cmu-cam1", 5652core_initcall(exynos5433_cmu_init);
5413 exynos5433_cmu_cam1_init);
diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c
index a80f3ef20801..b08bd54c5e76 100644
--- a/drivers/clk/samsung/clk-exynos5440.c
+++ b/drivers/clk/samsung/clk-exynos5440.c
@@ -53,8 +53,7 @@ static const struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __
53/* mux clocks */ 53/* mux clocks */
54static const struct samsung_mux_clock exynos5440_mux_clks[] __initconst = { 54static const struct samsung_mux_clock exynos5440_mux_clks[] __initconst = {
55 MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1), 55 MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1),
56 MUX_A(CLK_ARM_CLK, "arm_clk", mout_armclk_p, 56 MUX(CLK_ARM_CLK, "arm_clk", mout_armclk_p, CPU_CLK_STATUS, 0, 1),
57 CPU_CLK_STATUS, 0, 1, "armclk"),
58}; 57};
59 58
60/* divider clocks */ 59/* divider clocks */
@@ -117,6 +116,13 @@ static const struct samsung_pll_clock exynos5440_plls[] __initconst = {
117 PLL(pll_2550x, CLK_CPLLB, "cpllb", "xtal", 0, 0x50, NULL), 116 PLL(pll_2550x, CLK_CPLLB, "cpllb", "xtal", 0, 0x50, NULL),
118}; 117};
119 118
119/*
120 * Clock aliases for legacy clkdev look-up.
121 */
122static const struct samsung_clock_alias exynos5440_aliases[] __initconst = {
123 ALIAS(CLK_ARM_CLK, NULL, "armclk"),
124};
125
120/* register exynos5440 clocks */ 126/* register exynos5440 clocks */
121static void __init exynos5440_clk_init(struct device_node *np) 127static void __init exynos5440_clk_init(struct device_node *np)
122{ 128{
@@ -147,6 +153,8 @@ static void __init exynos5440_clk_init(struct device_node *np)
147 ARRAY_SIZE(exynos5440_div_clks)); 153 ARRAY_SIZE(exynos5440_div_clks));
148 samsung_clk_register_gate(ctx, exynos5440_gate_clks, 154 samsung_clk_register_gate(ctx, exynos5440_gate_clks,
149 ARRAY_SIZE(exynos5440_gate_clks)); 155 ARRAY_SIZE(exynos5440_gate_clks));
156 samsung_clk_register_alias(ctx, exynos5440_aliases,
157 ARRAY_SIZE(exynos5440_aliases));
150 158
151 samsung_clk_of_add_provider(np, ctx); 159 samsung_clk_of_add_provider(np, ctx);
152 160
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 037c61484098..1c4c7a3039f1 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -1388,7 +1388,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
1388 pll->lock_reg = base + pll_clk->lock_offset; 1388 pll->lock_reg = base + pll_clk->lock_offset;
1389 pll->con_reg = base + pll_clk->con_offset; 1389 pll->con_reg = base + pll_clk->con_offset;
1390 1390
1391 ret = clk_hw_register(NULL, &pll->hw); 1391 ret = clk_hw_register(ctx->dev, &pll->hw);
1392 if (ret) { 1392 if (ret) {
1393 pr_err("%s: failed to register pll clock %s : %d\n", 1393 pr_err("%s: failed to register pll clock %s : %d\n",
1394 __func__, pll_clk->name, ret); 1394 __func__, pll_clk->name, ret);
@@ -1397,15 +1397,6 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
1397 } 1397 }
1398 1398
1399 samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id); 1399 samsung_clk_add_lookup(ctx, &pll->hw, pll_clk->id);
1400
1401 if (!pll_clk->alias)
1402 return;
1403
1404 ret = clk_hw_register_clkdev(&pll->hw, pll_clk->alias,
1405 pll_clk->dev_name);
1406 if (ret)
1407 pr_err("%s: failed to register lookup for %s : %d",
1408 __func__, pll_clk->name, ret);
1409} 1400}
1410 1401
1411void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx, 1402void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
diff --git a/drivers/clk/samsung/clk-s3c2443.c b/drivers/clk/samsung/clk-s3c2443.c
index abb935c42916..d94b85a42356 100644
--- a/drivers/clk/samsung/clk-s3c2443.c
+++ b/drivers/clk/samsung/clk-s3c2443.c
@@ -117,8 +117,8 @@ struct samsung_mux_clock s3c2443_common_muxes[] __initdata = {
117 MUX(0, "epllref", epllref_p, CLKSRC, 7, 2), 117 MUX(0, "epllref", epllref_p, CLKSRC, 7, 2),
118 MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1), 118 MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1),
119 MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1), 119 MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1),
120 MUX_A(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1, "msysclk"), 120 MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
121 MUX_A(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1, "armclk"), 121 MUX(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1),
122 MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2), 122 MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2),
123}; 123};
124 124
@@ -189,6 +189,10 @@ struct samsung_gate_clock s3c2443_common_gates[] __initdata = {
189}; 189};
190 190
191struct samsung_clock_alias s3c2443_common_aliases[] __initdata = { 191struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
192 ALIAS(MSYSCLK, NULL, "msysclk"),
193 ALIAS(ARMCLK, NULL, "armclk"),
194 ALIAS(MPLL, NULL, "mpll"),
195 ALIAS(EPLL, NULL, "epll"),
192 ALIAS(HCLK, NULL, "hclk"), 196 ALIAS(HCLK, NULL, "hclk"),
193 ALIAS(HCLK_SSMC, NULL, "nand"), 197 ALIAS(HCLK_SSMC, NULL, "nand"),
194 ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"), 198 ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
@@ -221,9 +225,9 @@ struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
221/* S3C2416 specific clocks */ 225/* S3C2416 specific clocks */
222 226
223static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = { 227static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = {
224 [mpll] = PLL(pll_6552_s3c2416, 0, "mpll", "mpllref", 228 [mpll] = PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref",
225 LOCKCON0, MPLLCON, NULL), 229 LOCKCON0, MPLLCON, NULL),
226 [epll] = PLL(pll_6553, 0, "epll", "epllref", 230 [epll] = PLL(pll_6553, EPLL, "epll", "epllref",
227 LOCKCON1, EPLLCON, NULL), 231 LOCKCON1, EPLLCON, NULL),
228}; 232};
229 233
@@ -275,9 +279,9 @@ struct samsung_clock_alias s3c2416_aliases[] __initdata = {
275/* S3C2443 specific clocks */ 279/* S3C2443 specific clocks */
276 280
277static struct samsung_pll_clock s3c2443_pll_clks[] __initdata = { 281static struct samsung_pll_clock s3c2443_pll_clks[] __initdata = {
278 [mpll] = PLL(pll_3000, 0, "mpll", "mpllref", 282 [mpll] = PLL(pll_3000, MPLL, "mpll", "mpllref",
279 LOCKCON0, MPLLCON, NULL), 283 LOCKCON0, MPLLCON, NULL),
280 [epll] = PLL(pll_2126, 0, "epll", "epllref", 284 [epll] = PLL(pll_2126, EPLL, "epll", "epllref",
281 LOCKCON1, EPLLCON, NULL), 285 LOCKCON1, EPLLCON, NULL),
282}; 286};
283 287
diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c
index 7ce0fa86c5ff..8634884aa11c 100644
--- a/drivers/clk/samsung/clk.c
+++ b/drivers/clk/samsung/clk.c
@@ -134,7 +134,7 @@ void __init samsung_clk_register_fixed_rate(struct samsung_clk_provider *ctx,
134 unsigned int idx, ret; 134 unsigned int idx, ret;
135 135
136 for (idx = 0; idx < nr_clk; idx++, list++) { 136 for (idx = 0; idx < nr_clk; idx++, list++) {
137 clk_hw = clk_hw_register_fixed_rate(NULL, list->name, 137 clk_hw = clk_hw_register_fixed_rate(ctx->dev, list->name,
138 list->parent_name, list->flags, list->fixed_rate); 138 list->parent_name, list->flags, list->fixed_rate);
139 if (IS_ERR(clk_hw)) { 139 if (IS_ERR(clk_hw)) {
140 pr_err("%s: failed to register clock %s\n", __func__, 140 pr_err("%s: failed to register clock %s\n", __func__,
@@ -163,7 +163,7 @@ void __init samsung_clk_register_fixed_factor(struct samsung_clk_provider *ctx,
163 unsigned int idx; 163 unsigned int idx;
164 164
165 for (idx = 0; idx < nr_clk; idx++, list++) { 165 for (idx = 0; idx < nr_clk; idx++, list++) {
166 clk_hw = clk_hw_register_fixed_factor(NULL, list->name, 166 clk_hw = clk_hw_register_fixed_factor(ctx->dev, list->name,
167 list->parent_name, list->flags, list->mult, list->div); 167 list->parent_name, list->flags, list->mult, list->div);
168 if (IS_ERR(clk_hw)) { 168 if (IS_ERR(clk_hw)) {
169 pr_err("%s: failed to register clock %s\n", __func__, 169 pr_err("%s: failed to register clock %s\n", __func__,
@@ -181,10 +181,10 @@ void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
181 unsigned int nr_clk) 181 unsigned int nr_clk)
182{ 182{
183 struct clk_hw *clk_hw; 183 struct clk_hw *clk_hw;
184 unsigned int idx, ret; 184 unsigned int idx;
185 185
186 for (idx = 0; idx < nr_clk; idx++, list++) { 186 for (idx = 0; idx < nr_clk; idx++, list++) {
187 clk_hw = clk_hw_register_mux(NULL, list->name, 187 clk_hw = clk_hw_register_mux(ctx->dev, list->name,
188 list->parent_names, list->num_parents, list->flags, 188 list->parent_names, list->num_parents, list->flags,
189 ctx->reg_base + list->offset, 189 ctx->reg_base + list->offset,
190 list->shift, list->width, list->mux_flags, &ctx->lock); 190 list->shift, list->width, list->mux_flags, &ctx->lock);
@@ -195,15 +195,6 @@ void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
195 } 195 }
196 196
197 samsung_clk_add_lookup(ctx, clk_hw, list->id); 197 samsung_clk_add_lookup(ctx, clk_hw, list->id);
198
199 /* register a clock lookup only if a clock alias is specified */
200 if (list->alias) {
201 ret = clk_hw_register_clkdev(clk_hw, list->alias,
202 list->dev_name);
203 if (ret)
204 pr_err("%s: failed to register lookup %s\n",
205 __func__, list->alias);
206 }
207 } 198 }
208} 199}
209 200
@@ -213,17 +204,17 @@ void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
213 unsigned int nr_clk) 204 unsigned int nr_clk)
214{ 205{
215 struct clk_hw *clk_hw; 206 struct clk_hw *clk_hw;
216 unsigned int idx, ret; 207 unsigned int idx;
217 208
218 for (idx = 0; idx < nr_clk; idx++, list++) { 209 for (idx = 0; idx < nr_clk; idx++, list++) {
219 if (list->table) 210 if (list->table)
220 clk_hw = clk_hw_register_divider_table(NULL, 211 clk_hw = clk_hw_register_divider_table(ctx->dev,
221 list->name, list->parent_name, list->flags, 212 list->name, list->parent_name, list->flags,
222 ctx->reg_base + list->offset, 213 ctx->reg_base + list->offset,
223 list->shift, list->width, list->div_flags, 214 list->shift, list->width, list->div_flags,
224 list->table, &ctx->lock); 215 list->table, &ctx->lock);
225 else 216 else
226 clk_hw = clk_hw_register_divider(NULL, list->name, 217 clk_hw = clk_hw_register_divider(ctx->dev, list->name,
227 list->parent_name, list->flags, 218 list->parent_name, list->flags,
228 ctx->reg_base + list->offset, list->shift, 219 ctx->reg_base + list->offset, list->shift,
229 list->width, list->div_flags, &ctx->lock); 220 list->width, list->div_flags, &ctx->lock);
@@ -234,15 +225,6 @@ void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
234 } 225 }
235 226
236 samsung_clk_add_lookup(ctx, clk_hw, list->id); 227 samsung_clk_add_lookup(ctx, clk_hw, list->id);
237
238 /* register a clock lookup only if a clock alias is specified */
239 if (list->alias) {
240 ret = clk_hw_register_clkdev(clk_hw, list->alias,
241 list->dev_name);
242 if (ret)
243 pr_err("%s: failed to register lookup %s\n",
244 __func__, list->alias);
245 }
246 } 228 }
247} 229}
248 230
@@ -252,10 +234,10 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
252 unsigned int nr_clk) 234 unsigned int nr_clk)
253{ 235{
254 struct clk_hw *clk_hw; 236 struct clk_hw *clk_hw;
255 unsigned int idx, ret; 237 unsigned int idx;
256 238
257 for (idx = 0; idx < nr_clk; idx++, list++) { 239 for (idx = 0; idx < nr_clk; idx++, list++) {
258 clk_hw = clk_hw_register_gate(NULL, list->name, list->parent_name, 240 clk_hw = clk_hw_register_gate(ctx->dev, list->name, list->parent_name,
259 list->flags, ctx->reg_base + list->offset, 241 list->flags, ctx->reg_base + list->offset,
260 list->bit_idx, list->gate_flags, &ctx->lock); 242 list->bit_idx, list->gate_flags, &ctx->lock);
261 if (IS_ERR(clk_hw)) { 243 if (IS_ERR(clk_hw)) {
@@ -264,15 +246,6 @@ void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
264 continue; 246 continue;
265 } 247 }
266 248
267 /* register a clock lookup only if a clock alias is specified */
268 if (list->alias) {
269 ret = clk_hw_register_clkdev(clk_hw, list->alias,
270 list->dev_name);
271 if (ret)
272 pr_err("%s: failed to register lookup %s\n",
273 __func__, list->alias);
274 }
275
276 samsung_clk_add_lookup(ctx, clk_hw, list->id); 249 samsung_clk_add_lookup(ctx, clk_hw, list->id);
277 } 250 }
278} 251}
diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h
index b8ca0dd3a38b..3880d2f9d582 100644
--- a/drivers/clk/samsung/clk.h
+++ b/drivers/clk/samsung/clk.h
@@ -24,6 +24,7 @@
24 */ 24 */
25struct samsung_clk_provider { 25struct samsung_clk_provider {
26 void __iomem *reg_base; 26 void __iomem *reg_base;
27 struct device *dev;
27 spinlock_t lock; 28 spinlock_t lock;
28 /* clk_data must be the last entry due to variable lenght 'hws' array */ 29 /* clk_data must be the last entry due to variable lenght 'hws' array */
29 struct clk_hw_onecell_data clk_data; 30 struct clk_hw_onecell_data clk_data;
@@ -106,7 +107,6 @@ struct samsung_fixed_factor_clock {
106/** 107/**
107 * struct samsung_mux_clock: information about mux clock 108 * struct samsung_mux_clock: information about mux clock
108 * @id: platform specific id of the clock. 109 * @id: platform specific id of the clock.
109 * @dev_name: name of the device to which this clock belongs.
110 * @name: name of this mux clock. 110 * @name: name of this mux clock.
111 * @parent_names: array of pointer to parent clock names. 111 * @parent_names: array of pointer to parent clock names.
112 * @num_parents: number of parents listed in @parent_names. 112 * @num_parents: number of parents listed in @parent_names.
@@ -115,11 +115,9 @@ struct samsung_fixed_factor_clock {
115 * @shift: starting bit location of the mux control bit-field in @reg. 115 * @shift: starting bit location of the mux control bit-field in @reg.
116 * @width: width of the mux control bit-field in @reg. 116 * @width: width of the mux control bit-field in @reg.
117 * @mux_flags: flags for mux-type clock. 117 * @mux_flags: flags for mux-type clock.
118 * @alias: optional clock alias name to be assigned to this clock.
119 */ 118 */
120struct samsung_mux_clock { 119struct samsung_mux_clock {
121 unsigned int id; 120 unsigned int id;
122 const char *dev_name;
123 const char *name; 121 const char *name;
124 const char *const *parent_names; 122 const char *const *parent_names;
125 u8 num_parents; 123 u8 num_parents;
@@ -128,13 +126,11 @@ struct samsung_mux_clock {
128 u8 shift; 126 u8 shift;
129 u8 width; 127 u8 width;
130 u8 mux_flags; 128 u8 mux_flags;
131 const char *alias;
132}; 129};
133 130
134#define __MUX(_id, dname, cname, pnames, o, s, w, f, mf, a) \ 131#define __MUX(_id, cname, pnames, o, s, w, f, mf) \
135 { \ 132 { \
136 .id = _id, \ 133 .id = _id, \
137 .dev_name = dname, \
138 .name = cname, \ 134 .name = cname, \
139 .parent_names = pnames, \ 135 .parent_names = pnames, \
140 .num_parents = ARRAY_SIZE(pnames), \ 136 .num_parents = ARRAY_SIZE(pnames), \
@@ -143,36 +139,26 @@ struct samsung_mux_clock {
143 .shift = s, \ 139 .shift = s, \
144 .width = w, \ 140 .width = w, \
145 .mux_flags = mf, \ 141 .mux_flags = mf, \
146 .alias = a, \
147 } 142 }
148 143
149#define MUX(_id, cname, pnames, o, s, w) \ 144#define MUX(_id, cname, pnames, o, s, w) \
150 __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, NULL) 145 __MUX(_id, cname, pnames, o, s, w, 0, 0)
151
152#define MUX_A(_id, cname, pnames, o, s, w, a) \
153 __MUX(_id, NULL, cname, pnames, o, s, w, 0, 0, a)
154 146
155#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \ 147#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
156 __MUX(_id, NULL, cname, pnames, o, s, w, f, mf, NULL) 148 __MUX(_id, cname, pnames, o, s, w, f, mf)
157
158#define MUX_FA(_id, cname, pnames, o, s, w, f, mf, a) \
159 __MUX(_id, NULL, cname, pnames, o, s, w, f, mf, a)
160 149
161/** 150/**
162 * @id: platform specific id of the clock. 151 * @id: platform specific id of the clock.
163 * struct samsung_div_clock: information about div clock 152 * struct samsung_div_clock: information about div clock
164 * @dev_name: name of the device to which this clock belongs.
165 * @name: name of this div clock. 153 * @name: name of this div clock.
166 * @parent_name: name of the parent clock. 154 * @parent_name: name of the parent clock.
167 * @flags: optional flags for basic clock. 155 * @flags: optional flags for basic clock.
168 * @offset: offset of the register for configuring the div. 156 * @offset: offset of the register for configuring the div.
169 * @shift: starting bit location of the div control bit-field in @reg. 157 * @shift: starting bit location of the div control bit-field in @reg.
170 * @div_flags: flags for div-type clock. 158 * @div_flags: flags for div-type clock.
171 * @alias: optional clock alias name to be assigned to this clock.
172 */ 159 */
173struct samsung_div_clock { 160struct samsung_div_clock {
174 unsigned int id; 161 unsigned int id;
175 const char *dev_name;
176 const char *name; 162 const char *name;
177 const char *parent_name; 163 const char *parent_name;
178 unsigned long flags; 164 unsigned long flags;
@@ -180,14 +166,12 @@ struct samsung_div_clock {
180 u8 shift; 166 u8 shift;
181 u8 width; 167 u8 width;
182 u8 div_flags; 168 u8 div_flags;
183 const char *alias;
184 struct clk_div_table *table; 169 struct clk_div_table *table;
185}; 170};
186 171
187#define __DIV(_id, dname, cname, pname, o, s, w, f, df, a, t) \ 172#define __DIV(_id, cname, pname, o, s, w, f, df, t) \
188 { \ 173 { \
189 .id = _id, \ 174 .id = _id, \
190 .dev_name = dname, \
191 .name = cname, \ 175 .name = cname, \
192 .parent_name = pname, \ 176 .parent_name = pname, \
193 .flags = f, \ 177 .flags = f, \
@@ -195,70 +179,51 @@ struct samsung_div_clock {
195 .shift = s, \ 179 .shift = s, \
196 .width = w, \ 180 .width = w, \
197 .div_flags = df, \ 181 .div_flags = df, \
198 .alias = a, \
199 .table = t, \ 182 .table = t, \
200 } 183 }
201 184
202#define DIV(_id, cname, pname, o, s, w) \ 185#define DIV(_id, cname, pname, o, s, w) \
203 __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, NULL) 186 __DIV(_id, cname, pname, o, s, w, 0, 0, NULL)
204
205#define DIV_A(_id, cname, pname, o, s, w, a) \
206 __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, a, NULL)
207 187
208#define DIV_F(_id, cname, pname, o, s, w, f, df) \ 188#define DIV_F(_id, cname, pname, o, s, w, f, df) \
209 __DIV(_id, NULL, cname, pname, o, s, w, f, df, NULL, NULL) 189 __DIV(_id, cname, pname, o, s, w, f, df, NULL)
210 190
211#define DIV_T(_id, cname, pname, o, s, w, t) \ 191#define DIV_T(_id, cname, pname, o, s, w, t) \
212 __DIV(_id, NULL, cname, pname, o, s, w, 0, 0, NULL, t) 192 __DIV(_id, cname, pname, o, s, w, 0, 0, t)
213 193
214/** 194/**
215 * struct samsung_gate_clock: information about gate clock 195 * struct samsung_gate_clock: information about gate clock
216 * @id: platform specific id of the clock. 196 * @id: platform specific id of the clock.
217 * @dev_name: name of the device to which this clock belongs.
218 * @name: name of this gate clock. 197 * @name: name of this gate clock.
219 * @parent_name: name of the parent clock. 198 * @parent_name: name of the parent clock.
220 * @flags: optional flags for basic clock. 199 * @flags: optional flags for basic clock.
221 * @offset: offset of the register for configuring the gate. 200 * @offset: offset of the register for configuring the gate.
222 * @bit_idx: bit index of the gate control bit-field in @reg. 201 * @bit_idx: bit index of the gate control bit-field in @reg.
223 * @gate_flags: flags for gate-type clock. 202 * @gate_flags: flags for gate-type clock.
224 * @alias: optional clock alias name to be assigned to this clock.
225 */ 203 */
226struct samsung_gate_clock { 204struct samsung_gate_clock {
227 unsigned int id; 205 unsigned int id;
228 const char *dev_name;
229 const char *name; 206 const char *name;
230 const char *parent_name; 207 const char *parent_name;
231 unsigned long flags; 208 unsigned long flags;
232 unsigned long offset; 209 unsigned long offset;
233 u8 bit_idx; 210 u8 bit_idx;
234 u8 gate_flags; 211 u8 gate_flags;
235 const char *alias;
236}; 212};
237 213
238#define __GATE(_id, dname, cname, pname, o, b, f, gf, a) \ 214#define __GATE(_id, cname, pname, o, b, f, gf) \
239 { \ 215 { \
240 .id = _id, \ 216 .id = _id, \
241 .dev_name = dname, \
242 .name = cname, \ 217 .name = cname, \
243 .parent_name = pname, \ 218 .parent_name = pname, \
244 .flags = f, \ 219 .flags = f, \
245 .offset = o, \ 220 .offset = o, \
246 .bit_idx = b, \ 221 .bit_idx = b, \
247 .gate_flags = gf, \ 222 .gate_flags = gf, \
248 .alias = a, \
249 } 223 }
250 224
251#define GATE(_id, cname, pname, o, b, f, gf) \ 225#define GATE(_id, cname, pname, o, b, f, gf) \
252 __GATE(_id, NULL, cname, pname, o, b, f, gf, NULL) 226 __GATE(_id, cname, pname, o, b, f, gf)
253
254#define GATE_A(_id, cname, pname, o, b, f, gf, a) \
255 __GATE(_id, NULL, cname, pname, o, b, f, gf, a)
256
257#define GATE_D(_id, dname, cname, pname, o, b, f, gf) \
258 __GATE(_id, dname, cname, pname, o, b, f, gf, NULL)
259
260#define GATE_DA(_id, dname, cname, pname, o, b, f, gf, a) \
261 __GATE(_id, dname, cname, pname, o, b, f, gf, a)
262 227
263#define PNAME(x) static const char * const x[] __initconst 228#define PNAME(x) static const char * const x[] __initconst
264 229
@@ -275,18 +240,15 @@ struct samsung_clk_reg_dump {
275/** 240/**
276 * struct samsung_pll_clock: information about pll clock 241 * struct samsung_pll_clock: information about pll clock
277 * @id: platform specific id of the clock. 242 * @id: platform specific id of the clock.
278 * @dev_name: name of the device to which this clock belongs.
279 * @name: name of this pll clock. 243 * @name: name of this pll clock.
280 * @parent_name: name of the parent clock. 244 * @parent_name: name of the parent clock.
281 * @flags: optional flags for basic clock. 245 * @flags: optional flags for basic clock.
282 * @con_offset: offset of the register for configuring the PLL. 246 * @con_offset: offset of the register for configuring the PLL.
283 * @lock_offset: offset of the register for locking the PLL. 247 * @lock_offset: offset of the register for locking the PLL.
284 * @type: Type of PLL to be registered. 248 * @type: Type of PLL to be registered.
285 * @alias: optional clock alias name to be assigned to this clock.
286 */ 249 */
287struct samsung_pll_clock { 250struct samsung_pll_clock {
288 unsigned int id; 251 unsigned int id;
289 const char *dev_name;
290 const char *name; 252 const char *name;
291 const char *parent_name; 253 const char *parent_name;
292 unsigned long flags; 254 unsigned long flags;
@@ -294,31 +256,23 @@ struct samsung_pll_clock {
294 int lock_offset; 256 int lock_offset;
295 enum samsung_pll_type type; 257 enum samsung_pll_type type;
296 const struct samsung_pll_rate_table *rate_table; 258 const struct samsung_pll_rate_table *rate_table;
297 const char *alias;
298}; 259};
299 260
300#define __PLL(_typ, _id, _dname, _name, _pname, _flags, _lock, _con, \ 261#define __PLL(_typ, _id, _name, _pname, _flags, _lock, _con, _rtable) \
301 _rtable, _alias) \
302 { \ 262 { \
303 .id = _id, \ 263 .id = _id, \
304 .type = _typ, \ 264 .type = _typ, \
305 .dev_name = _dname, \
306 .name = _name, \ 265 .name = _name, \
307 .parent_name = _pname, \ 266 .parent_name = _pname, \
308 .flags = CLK_GET_RATE_NOCACHE, \ 267 .flags = _flags, \
309 .con_offset = _con, \ 268 .con_offset = _con, \
310 .lock_offset = _lock, \ 269 .lock_offset = _lock, \
311 .rate_table = _rtable, \ 270 .rate_table = _rtable, \
312 .alias = _alias, \
313 } 271 }
314 272
315#define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable) \ 273#define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable) \
316 __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \ 274 __PLL(_typ, _id, _name, _pname, CLK_GET_RATE_NOCACHE, _lock, \
317 _lock, _con, _rtable, _name) 275 _con, _rtable)
318
319#define PLL_A(_typ, _id, _name, _pname, _lock, _con, _alias, _rtable) \
320 __PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \
321 _lock, _con, _rtable, _alias)
322 276
323struct samsung_clock_reg_cache { 277struct samsung_clock_reg_cache {
324 struct list_head node; 278 struct list_head node;
@@ -352,6 +306,12 @@ struct samsung_cmu_info {
352 /* list and number of clocks registers */ 306 /* list and number of clocks registers */
353 const unsigned long *clk_regs; 307 const unsigned long *clk_regs;
354 unsigned int nr_clk_regs; 308 unsigned int nr_clk_regs;
309
310 /* list and number of clocks registers to set before suspend */
311 const struct samsung_clk_reg_dump *suspend_regs;
312 unsigned int nr_suspend_regs;
313 /* name of the parent clock needed for CMU register access */
314 const char *clk_name;
355}; 315};
356 316
357extern struct samsung_clk_provider *__init samsung_clk_init( 317extern struct samsung_clk_provider *__init samsung_clk_init(
diff --git a/drivers/clk/sirf/clk-atlas6.c b/drivers/clk/sirf/clk-atlas6.c
index 665fa681b2e1..0cd11e6893af 100644
--- a/drivers/clk/sirf/clk-atlas6.c
+++ b/drivers/clk/sirf/clk-atlas6.c
@@ -42,7 +42,7 @@ static struct clk_dmn clk_mmc45 = {
42 }, 42 },
43}; 43};
44 44
45static struct clk_init_data clk_nand_init = { 45static const struct clk_init_data clk_nand_init = {
46 .name = "nand", 46 .name = "nand",
47 .ops = &dmn_ops, 47 .ops = &dmn_ops,
48 .parent_names = dmn_clk_parents, 48 .parent_names = dmn_clk_parents,
diff --git a/drivers/clk/sirf/clk-atlas7.c b/drivers/clk/sirf/clk-atlas7.c
index d0c6c9a2d06a..be012b4bab46 100644
--- a/drivers/clk/sirf/clk-atlas7.c
+++ b/drivers/clk/sirf/clk-atlas7.c
@@ -392,7 +392,7 @@ static const char * const pll_clk_parents[] = {
392 "xin", 392 "xin",
393}; 393};
394 394
395static struct clk_init_data clk_cpupll_init = { 395static const struct clk_init_data clk_cpupll_init = {
396 .name = "cpupll_vco", 396 .name = "cpupll_vco",
397 .ops = &ab_pll_ops, 397 .ops = &ab_pll_ops,
398 .parent_names = pll_clk_parents, 398 .parent_names = pll_clk_parents,
@@ -406,7 +406,7 @@ static struct clk_pll clk_cpupll = {
406 }, 406 },
407}; 407};
408 408
409static struct clk_init_data clk_mempll_init = { 409static const struct clk_init_data clk_mempll_init = {
410 .name = "mempll_vco", 410 .name = "mempll_vco",
411 .ops = &ab_pll_ops, 411 .ops = &ab_pll_ops,
412 .parent_names = pll_clk_parents, 412 .parent_names = pll_clk_parents,
@@ -420,7 +420,7 @@ static struct clk_pll clk_mempll = {
420 }, 420 },
421}; 421};
422 422
423static struct clk_init_data clk_sys0pll_init = { 423static const struct clk_init_data clk_sys0pll_init = {
424 .name = "sys0pll_vco", 424 .name = "sys0pll_vco",
425 .ops = &ab_pll_ops, 425 .ops = &ab_pll_ops,
426 .parent_names = pll_clk_parents, 426 .parent_names = pll_clk_parents,
@@ -434,7 +434,7 @@ static struct clk_pll clk_sys0pll = {
434 }, 434 },
435}; 435};
436 436
437static struct clk_init_data clk_sys1pll_init = { 437static const struct clk_init_data clk_sys1pll_init = {
438 .name = "sys1pll_vco", 438 .name = "sys1pll_vco",
439 .ops = &ab_pll_ops, 439 .ops = &ab_pll_ops,
440 .parent_names = pll_clk_parents, 440 .parent_names = pll_clk_parents,
@@ -448,7 +448,7 @@ static struct clk_pll clk_sys1pll = {
448 }, 448 },
449}; 449};
450 450
451static struct clk_init_data clk_sys2pll_init = { 451static const struct clk_init_data clk_sys2pll_init = {
452 .name = "sys2pll_vco", 452 .name = "sys2pll_vco",
453 .ops = &ab_pll_ops, 453 .ops = &ab_pll_ops,
454 .parent_names = pll_clk_parents, 454 .parent_names = pll_clk_parents,
@@ -462,7 +462,7 @@ static struct clk_pll clk_sys2pll = {
462 }, 462 },
463}; 463};
464 464
465static struct clk_init_data clk_sys3pll_init = { 465static const struct clk_init_data clk_sys3pll_init = {
466 .name = "sys3pll_vco", 466 .name = "sys3pll_vco",
467 .ops = &ab_pll_ops, 467 .ops = &ab_pll_ops,
468 .parent_names = pll_clk_parents, 468 .parent_names = pll_clk_parents,
@@ -596,7 +596,7 @@ static const char * const audiodto_clk_parents[] = {
596 "sys3pll_clk1", 596 "sys3pll_clk1",
597}; 597};
598 598
599static struct clk_init_data clk_audiodto_init = { 599static const struct clk_init_data clk_audiodto_init = {
600 .name = "audio_dto", 600 .name = "audio_dto",
601 .ops = &dto_ops, 601 .ops = &dto_ops,
602 .parent_names = audiodto_clk_parents, 602 .parent_names = audiodto_clk_parents,
@@ -617,7 +617,7 @@ static const char * const disp0dto_clk_parents[] = {
617 "sys3pll_clk1", 617 "sys3pll_clk1",
618}; 618};
619 619
620static struct clk_init_data clk_disp0dto_init = { 620static const struct clk_init_data clk_disp0dto_init = {
621 .name = "disp0_dto", 621 .name = "disp0_dto",
622 .ops = &dto_ops, 622 .ops = &dto_ops,
623 .parent_names = disp0dto_clk_parents, 623 .parent_names = disp0dto_clk_parents,
@@ -638,7 +638,7 @@ static const char * const disp1dto_clk_parents[] = {
638 "sys3pll_clk1", 638 "sys3pll_clk1",
639}; 639};
640 640
641static struct clk_init_data clk_disp1dto_init = { 641static const struct clk_init_data clk_disp1dto_init = {
642 .name = "disp1_dto", 642 .name = "disp1_dto",
643 .ops = &dto_ops, 643 .ops = &dto_ops,
644 .parent_names = disp1dto_clk_parents, 644 .parent_names = disp1dto_clk_parents,
diff --git a/drivers/clk/sirf/clk-common.c b/drivers/clk/sirf/clk-common.c
index 77e1e2491689..d8f9efa5129a 100644
--- a/drivers/clk/sirf/clk-common.c
+++ b/drivers/clk/sirf/clk-common.c
@@ -184,7 +184,7 @@ static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw,
184 return clk_hw_get_rate(parent_clk); 184 return clk_hw_get_rate(parent_clk);
185} 185}
186 186
187static struct clk_ops std_pll_ops = { 187static const struct clk_ops std_pll_ops = {
188 .recalc_rate = pll_clk_recalc_rate, 188 .recalc_rate = pll_clk_recalc_rate,
189 .round_rate = pll_clk_round_rate, 189 .round_rate = pll_clk_round_rate,
190 .set_rate = pll_clk_set_rate, 190 .set_rate = pll_clk_set_rate,
@@ -194,21 +194,21 @@ static const char * const pll_clk_parents[] = {
194 "osc", 194 "osc",
195}; 195};
196 196
197static struct clk_init_data clk_pll1_init = { 197static const struct clk_init_data clk_pll1_init = {
198 .name = "pll1", 198 .name = "pll1",
199 .ops = &std_pll_ops, 199 .ops = &std_pll_ops,
200 .parent_names = pll_clk_parents, 200 .parent_names = pll_clk_parents,
201 .num_parents = ARRAY_SIZE(pll_clk_parents), 201 .num_parents = ARRAY_SIZE(pll_clk_parents),
202}; 202};
203 203
204static struct clk_init_data clk_pll2_init = { 204static const struct clk_init_data clk_pll2_init = {
205 .name = "pll2", 205 .name = "pll2",
206 .ops = &std_pll_ops, 206 .ops = &std_pll_ops,
207 .parent_names = pll_clk_parents, 207 .parent_names = pll_clk_parents,
208 .num_parents = ARRAY_SIZE(pll_clk_parents), 208 .num_parents = ARRAY_SIZE(pll_clk_parents),
209}; 209};
210 210
211static struct clk_init_data clk_pll3_init = { 211static const struct clk_init_data clk_pll3_init = {
212 .name = "pll3", 212 .name = "pll3",
213 .ops = &std_pll_ops, 213 .ops = &std_pll_ops,
214 .parent_names = pll_clk_parents, 214 .parent_names = pll_clk_parents,
@@ -265,13 +265,13 @@ static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long pa
265 return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ; 265 return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ;
266} 266}
267 267
268static struct clk_ops usb_pll_ops = { 268static const struct clk_ops usb_pll_ops = {
269 .enable = usb_pll_clk_enable, 269 .enable = usb_pll_clk_enable,
270 .disable = usb_pll_clk_disable, 270 .disable = usb_pll_clk_disable,
271 .recalc_rate = usb_pll_clk_recalc_rate, 271 .recalc_rate = usb_pll_clk_recalc_rate,
272}; 272};
273 273
274static struct clk_init_data clk_usb_pll_init = { 274static const struct clk_init_data clk_usb_pll_init = {
275 .name = "usb_pll", 275 .name = "usb_pll",
276 .ops = &usb_pll_ops, 276 .ops = &usb_pll_ops,
277 .parent_names = pll_clk_parents, 277 .parent_names = pll_clk_parents,
@@ -437,7 +437,7 @@ static int cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
437 return ret2 ? ret2 : ret1; 437 return ret2 ? ret2 : ret1;
438} 438}
439 439
440static struct clk_ops msi_ops = { 440static const struct clk_ops msi_ops = {
441 .set_rate = dmn_clk_set_rate, 441 .set_rate = dmn_clk_set_rate,
442 .round_rate = dmn_clk_round_rate, 442 .round_rate = dmn_clk_round_rate,
443 .recalc_rate = dmn_clk_recalc_rate, 443 .recalc_rate = dmn_clk_recalc_rate,
@@ -445,7 +445,7 @@ static struct clk_ops msi_ops = {
445 .get_parent = dmn_clk_get_parent, 445 .get_parent = dmn_clk_get_parent,
446}; 446};
447 447
448static struct clk_init_data clk_mem_init = { 448static const struct clk_init_data clk_mem_init = {
449 .name = "mem", 449 .name = "mem",
450 .ops = &msi_ops, 450 .ops = &msi_ops,
451 .parent_names = dmn_clk_parents, 451 .parent_names = dmn_clk_parents,
@@ -459,7 +459,7 @@ static struct clk_dmn clk_mem = {
459 }, 459 },
460}; 460};
461 461
462static struct clk_init_data clk_sys_init = { 462static const struct clk_init_data clk_sys_init = {
463 .name = "sys", 463 .name = "sys",
464 .ops = &msi_ops, 464 .ops = &msi_ops,
465 .parent_names = dmn_clk_parents, 465 .parent_names = dmn_clk_parents,
@@ -474,7 +474,7 @@ static struct clk_dmn clk_sys = {
474 }, 474 },
475}; 475};
476 476
477static struct clk_init_data clk_io_init = { 477static const struct clk_init_data clk_io_init = {
478 .name = "io", 478 .name = "io",
479 .ops = &msi_ops, 479 .ops = &msi_ops,
480 .parent_names = dmn_clk_parents, 480 .parent_names = dmn_clk_parents,
@@ -488,7 +488,7 @@ static struct clk_dmn clk_io = {
488 }, 488 },
489}; 489};
490 490
491static struct clk_ops cpu_ops = { 491static const struct clk_ops cpu_ops = {
492 .set_parent = dmn_clk_set_parent, 492 .set_parent = dmn_clk_set_parent,
493 .get_parent = dmn_clk_get_parent, 493 .get_parent = dmn_clk_get_parent,
494 .set_rate = cpu_clk_set_rate, 494 .set_rate = cpu_clk_set_rate,
@@ -496,7 +496,7 @@ static struct clk_ops cpu_ops = {
496 .recalc_rate = cpu_clk_recalc_rate, 496 .recalc_rate = cpu_clk_recalc_rate,
497}; 497};
498 498
499static struct clk_init_data clk_cpu_init = { 499static const struct clk_init_data clk_cpu_init = {
500 .name = "cpu", 500 .name = "cpu",
501 .ops = &cpu_ops, 501 .ops = &cpu_ops,
502 .parent_names = dmn_clk_parents, 502 .parent_names = dmn_clk_parents,
@@ -511,7 +511,7 @@ static struct clk_dmn clk_cpu = {
511 }, 511 },
512}; 512};
513 513
514static struct clk_ops dmn_ops = { 514static const struct clk_ops dmn_ops = {
515 .is_enabled = std_clk_is_enabled, 515 .is_enabled = std_clk_is_enabled,
516 .enable = std_clk_enable, 516 .enable = std_clk_enable,
517 .disable = std_clk_disable, 517 .disable = std_clk_disable,
@@ -524,7 +524,7 @@ static struct clk_ops dmn_ops = {
524 524
525/* dsp, gfx, mm, lcd and vpp domain */ 525/* dsp, gfx, mm, lcd and vpp domain */
526 526
527static struct clk_init_data clk_dsp_init = { 527static const struct clk_init_data clk_dsp_init = {
528 .name = "dsp", 528 .name = "dsp",
529 .ops = &dmn_ops, 529 .ops = &dmn_ops,
530 .parent_names = dmn_clk_parents, 530 .parent_names = dmn_clk_parents,
@@ -539,7 +539,7 @@ static struct clk_dmn clk_dsp = {
539 }, 539 },
540}; 540};
541 541
542static struct clk_init_data clk_gfx_init = { 542static const struct clk_init_data clk_gfx_init = {
543 .name = "gfx", 543 .name = "gfx",
544 .ops = &dmn_ops, 544 .ops = &dmn_ops,
545 .parent_names = dmn_clk_parents, 545 .parent_names = dmn_clk_parents,
@@ -554,7 +554,7 @@ static struct clk_dmn clk_gfx = {
554 }, 554 },
555}; 555};
556 556
557static struct clk_init_data clk_mm_init = { 557static const struct clk_init_data clk_mm_init = {
558 .name = "mm", 558 .name = "mm",
559 .ops = &dmn_ops, 559 .ops = &dmn_ops,
560 .parent_names = dmn_clk_parents, 560 .parent_names = dmn_clk_parents,
@@ -574,7 +574,7 @@ static struct clk_dmn clk_mm = {
574 */ 574 */
575#define clk_gfx2d clk_mm 575#define clk_gfx2d clk_mm
576 576
577static struct clk_init_data clk_lcd_init = { 577static const struct clk_init_data clk_lcd_init = {
578 .name = "lcd", 578 .name = "lcd",
579 .ops = &dmn_ops, 579 .ops = &dmn_ops,
580 .parent_names = dmn_clk_parents, 580 .parent_names = dmn_clk_parents,
@@ -589,7 +589,7 @@ static struct clk_dmn clk_lcd = {
589 }, 589 },
590}; 590};
591 591
592static struct clk_init_data clk_vpp_init = { 592static const struct clk_init_data clk_vpp_init = {
593 .name = "vpp", 593 .name = "vpp",
594 .ops = &dmn_ops, 594 .ops = &dmn_ops,
595 .parent_names = dmn_clk_parents, 595 .parent_names = dmn_clk_parents,
@@ -604,21 +604,21 @@ static struct clk_dmn clk_vpp = {
604 }, 604 },
605}; 605};
606 606
607static struct clk_init_data clk_mmc01_init = { 607static const struct clk_init_data clk_mmc01_init = {
608 .name = "mmc01", 608 .name = "mmc01",
609 .ops = &dmn_ops, 609 .ops = &dmn_ops,
610 .parent_names = dmn_clk_parents, 610 .parent_names = dmn_clk_parents,
611 .num_parents = ARRAY_SIZE(dmn_clk_parents), 611 .num_parents = ARRAY_SIZE(dmn_clk_parents),
612}; 612};
613 613
614static struct clk_init_data clk_mmc23_init = { 614static const struct clk_init_data clk_mmc23_init = {
615 .name = "mmc23", 615 .name = "mmc23",
616 .ops = &dmn_ops, 616 .ops = &dmn_ops,
617 .parent_names = dmn_clk_parents, 617 .parent_names = dmn_clk_parents,
618 .num_parents = ARRAY_SIZE(dmn_clk_parents), 618 .num_parents = ARRAY_SIZE(dmn_clk_parents),
619}; 619};
620 620
621static struct clk_init_data clk_mmc45_init = { 621static const struct clk_init_data clk_mmc45_init = {
622 .name = "mmc45", 622 .name = "mmc45",
623 .ops = &dmn_ops, 623 .ops = &dmn_ops,
624 .parent_names = dmn_clk_parents, 624 .parent_names = dmn_clk_parents,
@@ -679,13 +679,13 @@ static const char * const std_clk_io_parents[] = {
679 "io", 679 "io",
680}; 680};
681 681
682static struct clk_ops ios_ops = { 682static const struct clk_ops ios_ops = {
683 .is_enabled = std_clk_is_enabled, 683 .is_enabled = std_clk_is_enabled,
684 .enable = std_clk_enable, 684 .enable = std_clk_enable,
685 .disable = std_clk_disable, 685 .disable = std_clk_disable,
686}; 686};
687 687
688static struct clk_init_data clk_cphif_init = { 688static const struct clk_init_data clk_cphif_init = {
689 .name = "cphif", 689 .name = "cphif",
690 .ops = &ios_ops, 690 .ops = &ios_ops,
691 .parent_names = std_clk_io_parents, 691 .parent_names = std_clk_io_parents,
@@ -699,7 +699,7 @@ static struct clk_std clk_cphif = {
699 }, 699 },
700}; 700};
701 701
702static struct clk_init_data clk_dmac0_init = { 702static const struct clk_init_data clk_dmac0_init = {
703 .name = "dmac0", 703 .name = "dmac0",
704 .ops = &ios_ops, 704 .ops = &ios_ops,
705 .parent_names = std_clk_io_parents, 705 .parent_names = std_clk_io_parents,
@@ -713,7 +713,7 @@ static struct clk_std clk_dmac0 = {
713 }, 713 },
714}; 714};
715 715
716static struct clk_init_data clk_dmac1_init = { 716static const struct clk_init_data clk_dmac1_init = {
717 .name = "dmac1", 717 .name = "dmac1",
718 .ops = &ios_ops, 718 .ops = &ios_ops,
719 .parent_names = std_clk_io_parents, 719 .parent_names = std_clk_io_parents,
@@ -727,7 +727,7 @@ static struct clk_std clk_dmac1 = {
727 }, 727 },
728}; 728};
729 729
730static struct clk_init_data clk_audio_init = { 730static const struct clk_init_data clk_audio_init = {
731 .name = "audio", 731 .name = "audio",
732 .ops = &ios_ops, 732 .ops = &ios_ops,
733 .parent_names = std_clk_io_parents, 733 .parent_names = std_clk_io_parents,
@@ -741,7 +741,7 @@ static struct clk_std clk_audio = {
741 }, 741 },
742}; 742};
743 743
744static struct clk_init_data clk_uart0_init = { 744static const struct clk_init_data clk_uart0_init = {
745 .name = "uart0", 745 .name = "uart0",
746 .ops = &ios_ops, 746 .ops = &ios_ops,
747 .parent_names = std_clk_io_parents, 747 .parent_names = std_clk_io_parents,
@@ -755,7 +755,7 @@ static struct clk_std clk_uart0 = {
755 }, 755 },
756}; 756};
757 757
758static struct clk_init_data clk_uart1_init = { 758static const struct clk_init_data clk_uart1_init = {
759 .name = "uart1", 759 .name = "uart1",
760 .ops = &ios_ops, 760 .ops = &ios_ops,
761 .parent_names = std_clk_io_parents, 761 .parent_names = std_clk_io_parents,
@@ -769,7 +769,7 @@ static struct clk_std clk_uart1 = {
769 }, 769 },
770}; 770};
771 771
772static struct clk_init_data clk_uart2_init = { 772static const struct clk_init_data clk_uart2_init = {
773 .name = "uart2", 773 .name = "uart2",
774 .ops = &ios_ops, 774 .ops = &ios_ops,
775 .parent_names = std_clk_io_parents, 775 .parent_names = std_clk_io_parents,
@@ -783,7 +783,7 @@ static struct clk_std clk_uart2 = {
783 }, 783 },
784}; 784};
785 785
786static struct clk_init_data clk_usp0_init = { 786static const struct clk_init_data clk_usp0_init = {
787 .name = "usp0", 787 .name = "usp0",
788 .ops = &ios_ops, 788 .ops = &ios_ops,
789 .parent_names = std_clk_io_parents, 789 .parent_names = std_clk_io_parents,
@@ -797,7 +797,7 @@ static struct clk_std clk_usp0 = {
797 }, 797 },
798}; 798};
799 799
800static struct clk_init_data clk_usp1_init = { 800static const struct clk_init_data clk_usp1_init = {
801 .name = "usp1", 801 .name = "usp1",
802 .ops = &ios_ops, 802 .ops = &ios_ops,
803 .parent_names = std_clk_io_parents, 803 .parent_names = std_clk_io_parents,
@@ -811,7 +811,7 @@ static struct clk_std clk_usp1 = {
811 }, 811 },
812}; 812};
813 813
814static struct clk_init_data clk_usp2_init = { 814static const struct clk_init_data clk_usp2_init = {
815 .name = "usp2", 815 .name = "usp2",
816 .ops = &ios_ops, 816 .ops = &ios_ops,
817 .parent_names = std_clk_io_parents, 817 .parent_names = std_clk_io_parents,
@@ -825,7 +825,7 @@ static struct clk_std clk_usp2 = {
825 }, 825 },
826}; 826};
827 827
828static struct clk_init_data clk_vip_init = { 828static const struct clk_init_data clk_vip_init = {
829 .name = "vip", 829 .name = "vip",
830 .ops = &ios_ops, 830 .ops = &ios_ops,
831 .parent_names = std_clk_io_parents, 831 .parent_names = std_clk_io_parents,
@@ -839,7 +839,7 @@ static struct clk_std clk_vip = {
839 }, 839 },
840}; 840};
841 841
842static struct clk_init_data clk_spi0_init = { 842static const struct clk_init_data clk_spi0_init = {
843 .name = "spi0", 843 .name = "spi0",
844 .ops = &ios_ops, 844 .ops = &ios_ops,
845 .parent_names = std_clk_io_parents, 845 .parent_names = std_clk_io_parents,
@@ -853,7 +853,7 @@ static struct clk_std clk_spi0 = {
853 }, 853 },
854}; 854};
855 855
856static struct clk_init_data clk_spi1_init = { 856static const struct clk_init_data clk_spi1_init = {
857 .name = "spi1", 857 .name = "spi1",
858 .ops = &ios_ops, 858 .ops = &ios_ops,
859 .parent_names = std_clk_io_parents, 859 .parent_names = std_clk_io_parents,
@@ -867,7 +867,7 @@ static struct clk_std clk_spi1 = {
867 }, 867 },
868}; 868};
869 869
870static struct clk_init_data clk_tsc_init = { 870static const struct clk_init_data clk_tsc_init = {
871 .name = "tsc", 871 .name = "tsc",
872 .ops = &ios_ops, 872 .ops = &ios_ops,
873 .parent_names = std_clk_io_parents, 873 .parent_names = std_clk_io_parents,
@@ -881,7 +881,7 @@ static struct clk_std clk_tsc = {
881 }, 881 },
882}; 882};
883 883
884static struct clk_init_data clk_i2c0_init = { 884static const struct clk_init_data clk_i2c0_init = {
885 .name = "i2c0", 885 .name = "i2c0",
886 .ops = &ios_ops, 886 .ops = &ios_ops,
887 .parent_names = std_clk_io_parents, 887 .parent_names = std_clk_io_parents,
@@ -895,7 +895,7 @@ static struct clk_std clk_i2c0 = {
895 }, 895 },
896}; 896};
897 897
898static struct clk_init_data clk_i2c1_init = { 898static const struct clk_init_data clk_i2c1_init = {
899 .name = "i2c1", 899 .name = "i2c1",
900 .ops = &ios_ops, 900 .ops = &ios_ops,
901 .parent_names = std_clk_io_parents, 901 .parent_names = std_clk_io_parents,
@@ -909,7 +909,7 @@ static struct clk_std clk_i2c1 = {
909 }, 909 },
910}; 910};
911 911
912static struct clk_init_data clk_pwmc_init = { 912static const struct clk_init_data clk_pwmc_init = {
913 .name = "pwmc", 913 .name = "pwmc",
914 .ops = &ios_ops, 914 .ops = &ios_ops,
915 .parent_names = std_clk_io_parents, 915 .parent_names = std_clk_io_parents,
@@ -923,7 +923,7 @@ static struct clk_std clk_pwmc = {
923 }, 923 },
924}; 924};
925 925
926static struct clk_init_data clk_efuse_init = { 926static const struct clk_init_data clk_efuse_init = {
927 .name = "efuse", 927 .name = "efuse",
928 .ops = &ios_ops, 928 .ops = &ios_ops,
929 .parent_names = std_clk_io_parents, 929 .parent_names = std_clk_io_parents,
@@ -937,7 +937,7 @@ static struct clk_std clk_efuse = {
937 }, 937 },
938}; 938};
939 939
940static struct clk_init_data clk_pulse_init = { 940static const struct clk_init_data clk_pulse_init = {
941 .name = "pulse", 941 .name = "pulse",
942 .ops = &ios_ops, 942 .ops = &ios_ops,
943 .parent_names = std_clk_io_parents, 943 .parent_names = std_clk_io_parents,
@@ -955,7 +955,7 @@ static const char * const std_clk_dsp_parents[] = {
955 "dsp", 955 "dsp",
956}; 956};
957 957
958static struct clk_init_data clk_gps_init = { 958static const struct clk_init_data clk_gps_init = {
959 .name = "gps", 959 .name = "gps",
960 .ops = &ios_ops, 960 .ops = &ios_ops,
961 .parent_names = std_clk_dsp_parents, 961 .parent_names = std_clk_dsp_parents,
@@ -969,7 +969,7 @@ static struct clk_std clk_gps = {
969 }, 969 },
970}; 970};
971 971
972static struct clk_init_data clk_mf_init = { 972static const struct clk_init_data clk_mf_init = {
973 .name = "mf", 973 .name = "mf",
974 .ops = &ios_ops, 974 .ops = &ios_ops,
975 .parent_names = std_clk_io_parents, 975 .parent_names = std_clk_io_parents,
@@ -987,7 +987,7 @@ static const char * const std_clk_sys_parents[] = {
987 "sys", 987 "sys",
988}; 988};
989 989
990static struct clk_init_data clk_security_init = { 990static const struct clk_init_data clk_security_init = {
991 .name = "security", 991 .name = "security",
992 .ops = &ios_ops, 992 .ops = &ios_ops,
993 .parent_names = std_clk_sys_parents, 993 .parent_names = std_clk_sys_parents,
@@ -1005,7 +1005,7 @@ static const char * const std_clk_usb_parents[] = {
1005 "usb_pll", 1005 "usb_pll",
1006}; 1006};
1007 1007
1008static struct clk_init_data clk_usb0_init = { 1008static const struct clk_init_data clk_usb0_init = {
1009 .name = "usb0", 1009 .name = "usb0",
1010 .ops = &ios_ops, 1010 .ops = &ios_ops,
1011 .parent_names = std_clk_usb_parents, 1011 .parent_names = std_clk_usb_parents,
@@ -1019,7 +1019,7 @@ static struct clk_std clk_usb0 = {
1019 }, 1019 },
1020}; 1020};
1021 1021
1022static struct clk_init_data clk_usb1_init = { 1022static const struct clk_init_data clk_usb1_init = {
1023 .name = "usb1", 1023 .name = "usb1",
1024 .ops = &ios_ops, 1024 .ops = &ios_ops,
1025 .parent_names = std_clk_usb_parents, 1025 .parent_names = std_clk_usb_parents,
diff --git a/drivers/clk/sirf/clk-prima2.c b/drivers/clk/sirf/clk-prima2.c
index aac1c8ec151a..2f824320c318 100644
--- a/drivers/clk/sirf/clk-prima2.c
+++ b/drivers/clk/sirf/clk-prima2.c
@@ -42,7 +42,7 @@ static struct clk_dmn clk_mmc45 = {
42 }, 42 },
43}; 43};
44 44
45static struct clk_init_data clk_nand_init = { 45static const struct clk_init_data clk_nand_init = {
46 .name = "nand", 46 .name = "nand",
47 .ops = &ios_ops, 47 .ops = &ios_ops,
48 .parent_names = std_clk_io_parents, 48 .parent_names = std_clk_io_parents,
diff --git a/drivers/clk/spear/clk-aux-synth.c b/drivers/clk/spear/clk-aux-synth.c
index f271c350ef94..906410413bc1 100644
--- a/drivers/clk/spear/clk-aux-synth.c
+++ b/drivers/clk/spear/clk-aux-synth.c
@@ -29,7 +29,7 @@
29 29
30#define to_clk_aux(_hw) container_of(_hw, struct clk_aux, hw) 30#define to_clk_aux(_hw) container_of(_hw, struct clk_aux, hw)
31 31
32static struct aux_clk_masks default_aux_masks = { 32static const struct aux_clk_masks default_aux_masks = {
33 .eq_sel_mask = AUX_EQ_SEL_MASK, 33 .eq_sel_mask = AUX_EQ_SEL_MASK,
34 .eq_sel_shift = AUX_EQ_SEL_SHIFT, 34 .eq_sel_shift = AUX_EQ_SEL_SHIFT,
35 .eq1_mask = AUX_EQ1_SEL, 35 .eq1_mask = AUX_EQ1_SEL,
@@ -128,7 +128,7 @@ static int clk_aux_set_rate(struct clk_hw *hw, unsigned long drate,
128 return 0; 128 return 0;
129} 129}
130 130
131static struct clk_ops clk_aux_ops = { 131static const struct clk_ops clk_aux_ops = {
132 .recalc_rate = clk_aux_recalc_rate, 132 .recalc_rate = clk_aux_recalc_rate,
133 .round_rate = clk_aux_round_rate, 133 .round_rate = clk_aux_round_rate,
134 .set_rate = clk_aux_set_rate, 134 .set_rate = clk_aux_set_rate,
@@ -136,7 +136,7 @@ static struct clk_ops clk_aux_ops = {
136 136
137struct clk *clk_register_aux(const char *aux_name, const char *gate_name, 137struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
138 const char *parent_name, unsigned long flags, void __iomem *reg, 138 const char *parent_name, unsigned long flags, void __iomem *reg,
139 struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, 139 const struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
140 u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk) 140 u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk)
141{ 141{
142 struct clk_aux *aux; 142 struct clk_aux *aux;
@@ -149,10 +149,8 @@ struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
149 } 149 }
150 150
151 aux = kzalloc(sizeof(*aux), GFP_KERNEL); 151 aux = kzalloc(sizeof(*aux), GFP_KERNEL);
152 if (!aux) { 152 if (!aux)
153 pr_err("could not allocate aux clk\n");
154 return ERR_PTR(-ENOMEM); 153 return ERR_PTR(-ENOMEM);
155 }
156 154
157 /* struct clk_aux assignments */ 155 /* struct clk_aux assignments */
158 if (!masks) 156 if (!masks)
diff --git a/drivers/clk/spear/clk-frac-synth.c b/drivers/clk/spear/clk-frac-synth.c
index 58d678b5b40a..229c96daece6 100644
--- a/drivers/clk/spear/clk-frac-synth.c
+++ b/drivers/clk/spear/clk-frac-synth.c
@@ -116,7 +116,7 @@ static int clk_frac_set_rate(struct clk_hw *hw, unsigned long drate,
116 return 0; 116 return 0;
117} 117}
118 118
119static struct clk_ops clk_frac_ops = { 119static const struct clk_ops clk_frac_ops = {
120 .recalc_rate = clk_frac_recalc_rate, 120 .recalc_rate = clk_frac_recalc_rate,
121 .round_rate = clk_frac_round_rate, 121 .round_rate = clk_frac_round_rate,
122 .set_rate = clk_frac_set_rate, 122 .set_rate = clk_frac_set_rate,
@@ -136,10 +136,8 @@ struct clk *clk_register_frac(const char *name, const char *parent_name,
136 } 136 }
137 137
138 frac = kzalloc(sizeof(*frac), GFP_KERNEL); 138 frac = kzalloc(sizeof(*frac), GFP_KERNEL);
139 if (!frac) { 139 if (!frac)
140 pr_err("could not allocate frac clk\n");
141 return ERR_PTR(-ENOMEM); 140 return ERR_PTR(-ENOMEM);
142 }
143 141
144 /* struct clk_frac assignments */ 142 /* struct clk_frac assignments */
145 frac->reg = reg; 143 frac->reg = reg;
diff --git a/drivers/clk/spear/clk-gpt-synth.c b/drivers/clk/spear/clk-gpt-synth.c
index 1a722e99e76e..28262f422562 100644
--- a/drivers/clk/spear/clk-gpt-synth.c
+++ b/drivers/clk/spear/clk-gpt-synth.c
@@ -105,7 +105,7 @@ static int clk_gpt_set_rate(struct clk_hw *hw, unsigned long drate,
105 return 0; 105 return 0;
106} 106}
107 107
108static struct clk_ops clk_gpt_ops = { 108static const struct clk_ops clk_gpt_ops = {
109 .recalc_rate = clk_gpt_recalc_rate, 109 .recalc_rate = clk_gpt_recalc_rate,
110 .round_rate = clk_gpt_round_rate, 110 .round_rate = clk_gpt_round_rate,
111 .set_rate = clk_gpt_set_rate, 111 .set_rate = clk_gpt_set_rate,
@@ -125,10 +125,8 @@ struct clk *clk_register_gpt(const char *name, const char *parent_name, unsigned
125 } 125 }
126 126
127 gpt = kzalloc(sizeof(*gpt), GFP_KERNEL); 127 gpt = kzalloc(sizeof(*gpt), GFP_KERNEL);
128 if (!gpt) { 128 if (!gpt)
129 pr_err("could not allocate gpt clk\n");
130 return ERR_PTR(-ENOMEM); 129 return ERR_PTR(-ENOMEM);
131 }
132 130
133 /* struct clk_gpt assignments */ 131 /* struct clk_gpt assignments */
134 gpt->reg = reg; 132 gpt->reg = reg;
diff --git a/drivers/clk/spear/clk-vco-pll.c b/drivers/clk/spear/clk-vco-pll.c
index dc21ca4601aa..c08dec30bfa6 100644
--- a/drivers/clk/spear/clk-vco-pll.c
+++ b/drivers/clk/spear/clk-vco-pll.c
@@ -165,7 +165,7 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long drate,
165 return 0; 165 return 0;
166} 166}
167 167
168static struct clk_ops clk_pll_ops = { 168static const struct clk_ops clk_pll_ops = {
169 .recalc_rate = clk_pll_recalc_rate, 169 .recalc_rate = clk_pll_recalc_rate,
170 .round_rate = clk_pll_round_rate, 170 .round_rate = clk_pll_round_rate,
171 .set_rate = clk_pll_set_rate, 171 .set_rate = clk_pll_set_rate,
@@ -266,7 +266,7 @@ static int clk_vco_set_rate(struct clk_hw *hw, unsigned long drate,
266 return 0; 266 return 0;
267} 267}
268 268
269static struct clk_ops clk_vco_ops = { 269static const struct clk_ops clk_vco_ops = {
270 .recalc_rate = clk_vco_recalc_rate, 270 .recalc_rate = clk_vco_recalc_rate,
271 .round_rate = clk_vco_round_rate, 271 .round_rate = clk_vco_round_rate,
272 .set_rate = clk_vco_set_rate, 272 .set_rate = clk_vco_set_rate,
@@ -292,16 +292,12 @@ struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
292 } 292 }
293 293
294 vco = kzalloc(sizeof(*vco), GFP_KERNEL); 294 vco = kzalloc(sizeof(*vco), GFP_KERNEL);
295 if (!vco) { 295 if (!vco)
296 pr_err("could not allocate vco clk\n");
297 return ERR_PTR(-ENOMEM); 296 return ERR_PTR(-ENOMEM);
298 }
299 297
300 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 298 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
301 if (!pll) { 299 if (!pll)
302 pr_err("could not allocate pll clk\n");
303 goto free_vco; 300 goto free_vco;
304 }
305 301
306 /* struct clk_vco assignments */ 302 /* struct clk_vco assignments */
307 vco->mode_reg = mode_reg; 303 vco->mode_reg = mode_reg;
diff --git a/drivers/clk/spear/clk.h b/drivers/clk/spear/clk.h
index 9834944f08b1..af0e25f496c1 100644
--- a/drivers/clk/spear/clk.h
+++ b/drivers/clk/spear/clk.h
@@ -49,7 +49,7 @@ struct aux_rate_tbl {
49struct clk_aux { 49struct clk_aux {
50 struct clk_hw hw; 50 struct clk_hw hw;
51 void __iomem *reg; 51 void __iomem *reg;
52 struct aux_clk_masks *masks; 52 const struct aux_clk_masks *masks;
53 struct aux_rate_tbl *rtbl; 53 struct aux_rate_tbl *rtbl;
54 u8 rtbl_cnt; 54 u8 rtbl_cnt;
55 spinlock_t *lock; 55 spinlock_t *lock;
@@ -112,7 +112,7 @@ typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate,
112/* clk register routines */ 112/* clk register routines */
113struct clk *clk_register_aux(const char *aux_name, const char *gate_name, 113struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
114 const char *parent_name, unsigned long flags, void __iomem *reg, 114 const char *parent_name, unsigned long flags, void __iomem *reg,
115 struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl, 115 const struct aux_clk_masks *masks, struct aux_rate_tbl *rtbl,
116 u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk); 116 u8 rtbl_cnt, spinlock_t *lock, struct clk **gate_clk);
117struct clk *clk_register_frac(const char *name, const char *parent_name, 117struct clk *clk_register_frac(const char *name, const char *parent_name,
118 unsigned long flags, void __iomem *reg, 118 unsigned long flags, void __iomem *reg,
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index 2f86e3f94efa..591248c9a88e 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -284,7 +284,7 @@ static struct frac_rate_tbl clcd_rtbl[] = {
284}; 284};
285 285
286/* i2s prescaler1 masks */ 286/* i2s prescaler1 masks */
287static struct aux_clk_masks i2s_prs1_masks = { 287static const struct aux_clk_masks i2s_prs1_masks = {
288 .eq_sel_mask = AUX_EQ_SEL_MASK, 288 .eq_sel_mask = AUX_EQ_SEL_MASK,
289 .eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT, 289 .eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT,
290 .eq1_mask = AUX_EQ1_SEL, 290 .eq1_mask = AUX_EQ1_SEL,
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index cbb19a90f2d6..e5bc8c828cf0 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -323,7 +323,7 @@ static struct frac_rate_tbl clcd_rtbl[] = {
323}; 323};
324 324
325/* i2s prescaler1 masks */ 325/* i2s prescaler1 masks */
326static struct aux_clk_masks i2s_prs1_masks = { 326static const struct aux_clk_masks i2s_prs1_masks = {
327 .eq_sel_mask = AUX_EQ_SEL_MASK, 327 .eq_sel_mask = AUX_EQ_SEL_MASK,
328 .eq_sel_shift = SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT, 328 .eq_sel_shift = SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT,
329 .eq1_mask = AUX_EQ1_SEL, 329 .eq1_mask = AUX_EQ1_SEL,
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index d1c2fa93ddd9..4141c3fe08ae 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -11,6 +11,7 @@ lib-$(CONFIG_SUNXI_CCU) += ccu_gate.o
11lib-$(CONFIG_SUNXI_CCU) += ccu_mux.o 11lib-$(CONFIG_SUNXI_CCU) += ccu_mux.o
12lib-$(CONFIG_SUNXI_CCU) += ccu_mult.o 12lib-$(CONFIG_SUNXI_CCU) += ccu_mult.o
13lib-$(CONFIG_SUNXI_CCU) += ccu_phase.o 13lib-$(CONFIG_SUNXI_CCU) += ccu_phase.o
14lib-$(CONFIG_SUNXI_CCU) += ccu_sdm.o
14 15
15# Multi-factor clocks 16# Multi-factor clocks
16lib-$(CONFIG_SUNXI_CCU) += ccu_nk.o 17lib-$(CONFIG_SUNXI_CCU) += ccu_nk.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
index 286b0049b7b6..ffa5dac221e4 100644
--- a/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
+++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.c
@@ -28,6 +28,7 @@
28#include "ccu_nkmp.h" 28#include "ccu_nkmp.h"
29#include "ccu_nm.h" 29#include "ccu_nm.h"
30#include "ccu_phase.h" 30#include "ccu_phase.h"
31#include "ccu_sdm.h"
31 32
32#include "ccu-sun4i-a10.h" 33#include "ccu-sun4i-a10.h"
33 34
@@ -51,16 +52,29 @@ static struct ccu_nkmp pll_core_clk = {
51 * the base (2x, 4x and 8x), and one variable divider (the one true 52 * the base (2x, 4x and 8x), and one variable divider (the one true
52 * pll audio). 53 * pll audio).
53 * 54 *
54 * We don't have any need for the variable divider for now, so we just 55 * With sigma-delta modulation for fractional-N on the audio PLL,
55 * hardcode it to match with the clock names. 56 * we have to use specific dividers. This means the variable divider
57 * can no longer be used, as the audio codec requests the exact clock
58 * rates we support through this mechanism. So we now hard code the
59 * variable divider to 1. This means the clock rates will no longer
60 * match the clock names.
56 */ 61 */
57#define SUN4I_PLL_AUDIO_REG 0x008 62#define SUN4I_PLL_AUDIO_REG 0x008
63
64static struct ccu_sdm_setting pll_audio_sdm_table[] = {
65 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
66 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
67};
68
58static struct ccu_nm pll_audio_base_clk = { 69static struct ccu_nm pll_audio_base_clk = {
59 .enable = BIT(31), 70 .enable = BIT(31),
60 .n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0), 71 .n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
61 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0), 72 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
73 .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,
74 0x00c, BIT(31)),
62 .common = { 75 .common = {
63 .reg = 0x008, 76 .reg = 0x008,
77 .features = CCU_FEATURE_SIGMA_DELTA_MOD,
64 .hw.init = CLK_HW_INIT("pll-audio-base", 78 .hw.init = CLK_HW_INIT("pll-audio-base",
65 "hosc", 79 "hosc",
66 &ccu_nm_ops, 80 &ccu_nm_ops,
@@ -223,7 +237,7 @@ static struct ccu_mux cpu_clk = {
223 .hw.init = CLK_HW_INIT_PARENTS("cpu", 237 .hw.init = CLK_HW_INIT_PARENTS("cpu",
224 cpu_parents, 238 cpu_parents,
225 &ccu_mux_ops, 239 &ccu_mux_ops,
226 CLK_IS_CRITICAL), 240 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
227 } 241 }
228}; 242};
229 243
@@ -1021,9 +1035,9 @@ static struct ccu_common *sun4i_sun7i_ccu_clks[] = {
1021 &out_b_clk.common 1035 &out_b_clk.common
1022}; 1036};
1023 1037
1024/* Post-divider for pll-audio is hardcoded to 4 */ 1038/* Post-divider for pll-audio is hardcoded to 1 */
1025static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", 1039static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
1026 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); 1040 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
1027static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", 1041static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
1028 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); 1042 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
1029static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", 1043static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
@@ -1420,10 +1434,10 @@ static void __init sun4i_ccu_init(struct device_node *node,
1420 return; 1434 return;
1421 } 1435 }
1422 1436
1423 /* Force the PLL-Audio-1x divider to 4 */ 1437 /* Force the PLL-Audio-1x divider to 1 */
1424 val = readl(reg + SUN4I_PLL_AUDIO_REG); 1438 val = readl(reg + SUN4I_PLL_AUDIO_REG);
1425 val &= ~GENMASK(29, 26); 1439 val &= ~GENMASK(29, 26);
1426 writel(val | (4 << 26), reg + SUN4I_PLL_AUDIO_REG); 1440 writel(val | (1 << 26), reg + SUN4I_PLL_AUDIO_REG);
1427 1441
1428 /* 1442 /*
1429 * Use the peripheral PLL6 as the AHB parent, instead of CPU / 1443 * Use the peripheral PLL6 as the AHB parent, instead of CPU /
diff --git a/drivers/clk/sunxi-ng/ccu-sun4i-a10.h b/drivers/clk/sunxi-ng/ccu-sun4i-a10.h
index c5947c7c050e..23c908ad509f 100644
--- a/drivers/clk/sunxi-ng/ccu-sun4i-a10.h
+++ b/drivers/clk/sunxi-ng/ccu-sun4i-a10.h
@@ -29,7 +29,7 @@
29#define CLK_PLL_AUDIO_4X 6 29#define CLK_PLL_AUDIO_4X 6
30#define CLK_PLL_AUDIO_8X 7 30#define CLK_PLL_AUDIO_8X 7
31#define CLK_PLL_VIDEO0 8 31#define CLK_PLL_VIDEO0 8
32#define CLK_PLL_VIDEO0_2X 9 32/* The PLL_VIDEO0_2X clock is exported */
33#define CLK_PLL_VE 10 33#define CLK_PLL_VE 10
34#define CLK_PLL_DDR_BASE 11 34#define CLK_PLL_DDR_BASE 11
35#define CLK_PLL_DDR 12 35#define CLK_PLL_DDR 12
@@ -38,7 +38,7 @@
38#define CLK_PLL_PERIPH 15 38#define CLK_PLL_PERIPH 15
39#define CLK_PLL_PERIPH_SATA 16 39#define CLK_PLL_PERIPH_SATA 16
40#define CLK_PLL_VIDEO1 17 40#define CLK_PLL_VIDEO1 17
41#define CLK_PLL_VIDEO1_2X 18 41/* The PLL_VIDEO1_2X clock is exported */
42#define CLK_PLL_GPU 19 42#define CLK_PLL_GPU 19
43 43
44/* The CPU clock is exported */ 44/* The CPU clock is exported */
diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.c b/drivers/clk/sunxi-ng/ccu-sun5i.c
index ab9e850b3707..fa2c2dd77102 100644
--- a/drivers/clk/sunxi-ng/ccu-sun5i.c
+++ b/drivers/clk/sunxi-ng/ccu-sun5i.c
@@ -26,6 +26,7 @@
26#include "ccu_nkmp.h" 26#include "ccu_nkmp.h"
27#include "ccu_nm.h" 27#include "ccu_nm.h"
28#include "ccu_phase.h" 28#include "ccu_phase.h"
29#include "ccu_sdm.h"
29 30
30#include "ccu-sun5i.h" 31#include "ccu-sun5i.h"
31 32
@@ -49,11 +50,20 @@ static struct ccu_nkmp pll_core_clk = {
49 * the base (2x, 4x and 8x), and one variable divider (the one true 50 * the base (2x, 4x and 8x), and one variable divider (the one true
50 * pll audio). 51 * pll audio).
51 * 52 *
52 * We don't have any need for the variable divider for now, so we just 53 * With sigma-delta modulation for fractional-N on the audio PLL,
53 * hardcode it to match with the clock names 54 * we have to use specific dividers. This means the variable divider
55 * can no longer be used, as the audio codec requests the exact clock
56 * rates we support through this mechanism. So we now hard code the
57 * variable divider to 1. This means the clock rates will no longer
58 * match the clock names.
54 */ 59 */
55#define SUN5I_PLL_AUDIO_REG 0x008 60#define SUN5I_PLL_AUDIO_REG 0x008
56 61
62static struct ccu_sdm_setting pll_audio_sdm_table[] = {
63 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
64 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
65};
66
57static struct ccu_nm pll_audio_base_clk = { 67static struct ccu_nm pll_audio_base_clk = {
58 .enable = BIT(31), 68 .enable = BIT(31),
59 .n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0), 69 .n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
@@ -63,8 +73,11 @@ static struct ccu_nm pll_audio_base_clk = {
63 * offset 73 * offset
64 */ 74 */
65 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0), 75 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
76 .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,
77 0x00c, BIT(31)),
66 .common = { 78 .common = {
67 .reg = 0x008, 79 .reg = 0x008,
80 .features = CCU_FEATURE_SIGMA_DELTA_MOD,
68 .hw.init = CLK_HW_INIT("pll-audio-base", 81 .hw.init = CLK_HW_INIT("pll-audio-base",
69 "hosc", 82 "hosc",
70 &ccu_nm_ops, 83 &ccu_nm_ops,
@@ -597,9 +610,9 @@ static struct ccu_common *sun5i_a10s_ccu_clks[] = {
597 &iep_clk.common, 610 &iep_clk.common,
598}; 611};
599 612
600/* We hardcode the divider to 4 for now */ 613/* We hardcode the divider to 1 for now */
601static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", 614static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
602 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); 615 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
603static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", 616static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
604 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); 617 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
605static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", 618static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
@@ -980,10 +993,10 @@ static void __init sun5i_ccu_init(struct device_node *node,
980 return; 993 return;
981 } 994 }
982 995
983 /* Force the PLL-Audio-1x divider to 4 */ 996 /* Force the PLL-Audio-1x divider to 1 */
984 val = readl(reg + SUN5I_PLL_AUDIO_REG); 997 val = readl(reg + SUN5I_PLL_AUDIO_REG);
985 val &= ~GENMASK(19, 16); 998 val &= ~GENMASK(29, 26);
986 writel(val | (3 << 16), reg + SUN5I_PLL_AUDIO_REG); 999 writel(val | (0 << 26), reg + SUN5I_PLL_AUDIO_REG);
987 1000
988 /* 1001 /*
989 * Use the peripheral PLL as the AHB parent, instead of CPU / 1002 * Use the peripheral PLL as the AHB parent, instead of CPU /
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
index 8af434815fba..72b16ed1012b 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
@@ -31,6 +31,7 @@
31#include "ccu_nkmp.h" 31#include "ccu_nkmp.h"
32#include "ccu_nm.h" 32#include "ccu_nm.h"
33#include "ccu_phase.h" 33#include "ccu_phase.h"
34#include "ccu_sdm.h"
34 35
35#include "ccu-sun6i-a31.h" 36#include "ccu-sun6i-a31.h"
36 37
@@ -48,18 +49,29 @@ static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
48 * the base (2x, 4x and 8x), and one variable divider (the one true 49 * the base (2x, 4x and 8x), and one variable divider (the one true
49 * pll audio). 50 * pll audio).
50 * 51 *
51 * We don't have any need for the variable divider for now, so we just 52 * With sigma-delta modulation for fractional-N on the audio PLL,
52 * hardcode it to match with the clock names 53 * we have to use specific dividers. This means the variable divider
54 * can no longer be used, as the audio codec requests the exact clock
55 * rates we support through this mechanism. So we now hard code the
56 * variable divider to 1. This means the clock rates will no longer
57 * match the clock names.
53 */ 58 */
54#define SUN6I_A31_PLL_AUDIO_REG 0x008 59#define SUN6I_A31_PLL_AUDIO_REG 0x008
55 60
56static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 61static struct ccu_sdm_setting pll_audio_sdm_table[] = {
57 "osc24M", 0x008, 62 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
58 8, 7, /* N */ 63 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
59 0, 5, /* M */ 64};
60 BIT(31), /* gate */ 65
61 BIT(28), /* lock */ 66static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
62 CLK_SET_RATE_UNGATE); 67 "osc24M", 0x008,
68 8, 7, /* N */
69 0, 5, /* M */
70 pll_audio_sdm_table, BIT(24),
71 0x284, BIT(31),
72 BIT(31), /* gate */
73 BIT(28), /* lock */
74 CLK_SET_RATE_UNGATE);
63 75
64static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", 76static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
65 "osc24M", 0x010, 77 "osc24M", 0x010,
@@ -608,7 +620,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", lcd_ch1_parents,
608 0x150, 0, 4, 24, 2, BIT(31), 620 0x150, 0, 4, 24, 2, BIT(31),
609 CLK_SET_RATE_PARENT); 621 CLK_SET_RATE_PARENT);
610 622
611static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(30), 0); 623static SUNXI_CCU_GATE(hdmi_ddc_clk, "ddc", "osc24M", 0x150, BIT(30), 0);
612 624
613static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0); 625static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
614 626
@@ -950,9 +962,9 @@ static struct ccu_common *sun6i_a31_ccu_clks[] = {
950 &out_c_clk.common, 962 &out_c_clk.common,
951}; 963};
952 964
953/* We hardcode the divider to 4 for now */ 965/* We hardcode the divider to 1 for now */
954static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", 966static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
955 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); 967 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
956static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", 968static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
957 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); 969 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
958static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", 970static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
@@ -1221,10 +1233,10 @@ static void __init sun6i_a31_ccu_setup(struct device_node *node)
1221 return; 1233 return;
1222 } 1234 }
1223 1235
1224 /* Force the PLL-Audio-1x divider to 4 */ 1236 /* Force the PLL-Audio-1x divider to 1 */
1225 val = readl(reg + SUN6I_A31_PLL_AUDIO_REG); 1237 val = readl(reg + SUN6I_A31_PLL_AUDIO_REG);
1226 val &= ~GENMASK(19, 16); 1238 val &= ~GENMASK(19, 16);
1227 writel(val | (3 << 16), reg + SUN6I_A31_PLL_AUDIO_REG); 1239 writel(val | (0 << 16), reg + SUN6I_A31_PLL_AUDIO_REG);
1228 1240
1229 /* Force PLL-MIPI to MIPI mode */ 1241 /* Force PLL-MIPI to MIPI mode */
1230 val = readl(reg + SUN6I_A31_PLL_MIPI_REG); 1242 val = readl(reg + SUN6I_A31_PLL_MIPI_REG);
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.h b/drivers/clk/sunxi-ng/ccu-sun6i-a31.h
index 4e434011e9e7..27e6ad4133ab 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.h
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.h
@@ -27,7 +27,9 @@
27#define CLK_PLL_AUDIO_4X 4 27#define CLK_PLL_AUDIO_4X 4
28#define CLK_PLL_AUDIO_8X 5 28#define CLK_PLL_AUDIO_8X 5
29#define CLK_PLL_VIDEO0 6 29#define CLK_PLL_VIDEO0 6
30#define CLK_PLL_VIDEO0_2X 7 30
31/* The PLL_VIDEO0_2X clock is exported */
32
31#define CLK_PLL_VE 8 33#define CLK_PLL_VE 8
32#define CLK_PLL_DDR 9 34#define CLK_PLL_DDR 9
33 35
@@ -35,7 +37,9 @@
35 37
36#define CLK_PLL_PERIPH_2X 11 38#define CLK_PLL_PERIPH_2X 11
37#define CLK_PLL_VIDEO1 12 39#define CLK_PLL_VIDEO1 12
38#define CLK_PLL_VIDEO1_2X 13 40
41/* The PLL_VIDEO1_2X clock is exported */
42
39#define CLK_PLL_GPU 14 43#define CLK_PLL_GPU 14
40#define CLK_PLL_MIPI 15 44#define CLK_PLL_MIPI 15
41#define CLK_PLL9 16 45#define CLK_PLL9 16
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
index d93b452f0df9..a4fa2945f230 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a23.c
@@ -26,6 +26,7 @@
26#include "ccu_nkmp.h" 26#include "ccu_nkmp.h"
27#include "ccu_nm.h" 27#include "ccu_nm.h"
28#include "ccu_phase.h" 28#include "ccu_phase.h"
29#include "ccu_sdm.h"
29 30
30#include "ccu-sun8i-a23-a33.h" 31#include "ccu-sun8i-a23-a33.h"
31 32
@@ -52,18 +53,29 @@ static struct ccu_nkmp pll_cpux_clk = {
52 * the base (2x, 4x and 8x), and one variable divider (the one true 53 * the base (2x, 4x and 8x), and one variable divider (the one true
53 * pll audio). 54 * pll audio).
54 * 55 *
55 * We don't have any need for the variable divider for now, so we just 56 * With sigma-delta modulation for fractional-N on the audio PLL,
56 * hardcode it to match with the clock names 57 * we have to use specific dividers. This means the variable divider
58 * can no longer be used, as the audio codec requests the exact clock
59 * rates we support through this mechanism. So we now hard code the
60 * variable divider to 1. This means the clock rates will no longer
61 * match the clock names.
57 */ 62 */
58#define SUN8I_A23_PLL_AUDIO_REG 0x008 63#define SUN8I_A23_PLL_AUDIO_REG 0x008
59 64
60static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 65static struct ccu_sdm_setting pll_audio_sdm_table[] = {
61 "osc24M", 0x008, 66 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
62 8, 7, /* N */ 67 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
63 0, 5, /* M */ 68};
64 BIT(31), /* gate */ 69
65 BIT(28), /* lock */ 70static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
66 CLK_SET_RATE_UNGATE); 71 "osc24M", 0x008,
72 8, 7, /* N */
73 0, 5, /* M */
74 pll_audio_sdm_table, BIT(24),
75 0x284, BIT(31),
76 BIT(31), /* gate */
77 BIT(28), /* lock */
78 CLK_SET_RATE_UNGATE);
67 79
68static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video", 80static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
69 "osc24M", 0x010, 81 "osc24M", 0x010,
@@ -538,9 +550,9 @@ static struct ccu_common *sun8i_a23_ccu_clks[] = {
538 &ats_clk.common, 550 &ats_clk.common,
539}; 551};
540 552
541/* We hardcode the divider to 4 for now */ 553/* We hardcode the divider to 1 for now */
542static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", 554static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
543 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); 555 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
544static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", 556static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
545 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); 557 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
546static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", 558static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
@@ -720,10 +732,10 @@ static void __init sun8i_a23_ccu_setup(struct device_node *node)
720 return; 732 return;
721 } 733 }
722 734
723 /* Force the PLL-Audio-1x divider to 4 */ 735 /* Force the PLL-Audio-1x divider to 1 */
724 val = readl(reg + SUN8I_A23_PLL_AUDIO_REG); 736 val = readl(reg + SUN8I_A23_PLL_AUDIO_REG);
725 val &= ~GENMASK(19, 16); 737 val &= ~GENMASK(19, 16);
726 writel(val | (3 << 16), reg + SUN8I_A23_PLL_AUDIO_REG); 738 writel(val | (0 << 16), reg + SUN8I_A23_PLL_AUDIO_REG);
727 739
728 /* Force PLL-MIPI to MIPI mode */ 740 /* Force PLL-MIPI to MIPI mode */
729 val = readl(reg + SUN8I_A23_PLL_MIPI_REG); 741 val = readl(reg + SUN8I_A23_PLL_MIPI_REG);
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
index e43acebdfbcd..5cedcd0d8be8 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
@@ -354,9 +354,9 @@ static SUNXI_CCU_GATE(bus_tdm_clk, "bus-tdm", "apb1",
354static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 354static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
355 0x06c, BIT(0), 0); 355 0x06c, BIT(0), 0);
356static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 356static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
357 0x06c, BIT(0), 0); 357 0x06c, BIT(1), 0);
358static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 358static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
359 0x06c, BIT(0), 0); 359 0x06c, BIT(2), 0);
360static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 360static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
361 0x06c, BIT(16), 0); 361 0x06c, BIT(16), 0);
362static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 362static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
@@ -506,7 +506,7 @@ static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
506 csi_mclk_parents, csi_mclk_table, 506 csi_mclk_parents, csi_mclk_table,
507 0x134, 507 0x134,
508 0, 5, /* M */ 508 0, 5, /* M */
509 10, 3, /* mux */ 509 8, 3, /* mux */
510 BIT(15), /* gate */ 510 BIT(15), /* gate */
511 0); 511 0);
512 512
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 5cdaf52669e4..5cc9d9952121 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -41,11 +41,16 @@ static SUNXI_CCU_GATE(wb_clk, "wb", "wb-div",
41 41
42static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4, 42static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4,
43 CLK_SET_RATE_PARENT); 43 CLK_SET_RATE_PARENT);
44static SUNXI_CCU_M(mixer1_div_clk, "mixer1-div", "de", 0x0c, 4, 4,
45 CLK_SET_RATE_PARENT);
46static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4, 44static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4,
47 CLK_SET_RATE_PARENT); 45 CLK_SET_RATE_PARENT);
48 46
47static SUNXI_CCU_M(mixer0_div_a83_clk, "mixer0-div", "pll-de", 0x0c, 0, 4,
48 CLK_SET_RATE_PARENT);
49static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4,
50 CLK_SET_RATE_PARENT);
51static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4,
52 CLK_SET_RATE_PARENT);
53
49static struct ccu_common *sun8i_a83t_de2_clks[] = { 54static struct ccu_common *sun8i_a83t_de2_clks[] = {
50 &mixer0_clk.common, 55 &mixer0_clk.common,
51 &mixer1_clk.common, 56 &mixer1_clk.common,
@@ -55,9 +60,9 @@ static struct ccu_common *sun8i_a83t_de2_clks[] = {
55 &bus_mixer1_clk.common, 60 &bus_mixer1_clk.common,
56 &bus_wb_clk.common, 61 &bus_wb_clk.common,
57 62
58 &mixer0_div_clk.common, 63 &mixer0_div_a83_clk.common,
59 &mixer1_div_clk.common, 64 &mixer1_div_a83_clk.common,
60 &wb_div_clk.common, 65 &wb_div_a83_clk.common,
61}; 66};
62 67
63static struct ccu_common *sun8i_v3s_de2_clks[] = { 68static struct ccu_common *sun8i_v3s_de2_clks[] = {
@@ -81,9 +86,9 @@ static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
81 [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw, 86 [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw,
82 [CLK_BUS_WB] = &bus_wb_clk.common.hw, 87 [CLK_BUS_WB] = &bus_wb_clk.common.hw,
83 88
84 [CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw, 89 [CLK_MIXER0_DIV] = &mixer0_div_a83_clk.common.hw,
85 [CLK_MIXER1_DIV] = &mixer1_div_clk.common.hw, 90 [CLK_MIXER1_DIV] = &mixer1_div_a83_clk.common.hw,
86 [CLK_WB_DIV] = &wb_div_clk.common.hw, 91 [CLK_WB_DIV] = &wb_div_a83_clk.common.hw,
87 }, 92 },
88 .num = CLK_NUMBER, 93 .num = CLK_NUMBER,
89}; 94};
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 1729ff6a5aae..29bc0566b776 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -26,6 +26,7 @@
26#include "ccu_nkmp.h" 26#include "ccu_nkmp.h"
27#include "ccu_nm.h" 27#include "ccu_nm.h"
28#include "ccu_phase.h" 28#include "ccu_phase.h"
29#include "ccu_sdm.h"
29 30
30#include "ccu-sun8i-h3.h" 31#include "ccu-sun8i-h3.h"
31 32
@@ -37,25 +38,36 @@ static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
37 16, 2, /* P */ 38 16, 2, /* P */
38 BIT(31), /* gate */ 39 BIT(31), /* gate */
39 BIT(28), /* lock */ 40 BIT(28), /* lock */
40 0); 41 CLK_SET_RATE_UNGATE);
41 42
42/* 43/*
43 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from 44 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
44 * the base (2x, 4x and 8x), and one variable divider (the one true 45 * the base (2x, 4x and 8x), and one variable divider (the one true
45 * pll audio). 46 * pll audio).
46 * 47 *
47 * We don't have any need for the variable divider for now, so we just 48 * With sigma-delta modulation for fractional-N on the audio PLL,
48 * hardcode it to match with the clock names 49 * we have to use specific dividers. This means the variable divider
50 * can no longer be used, as the audio codec requests the exact clock
51 * rates we support through this mechanism. So we now hard code the
52 * variable divider to 1. This means the clock rates will no longer
53 * match the clock names.
49 */ 54 */
50#define SUN8I_H3_PLL_AUDIO_REG 0x008 55#define SUN8I_H3_PLL_AUDIO_REG 0x008
51 56
52static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 57static struct ccu_sdm_setting pll_audio_sdm_table[] = {
53 "osc24M", 0x008, 58 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
54 8, 7, /* N */ 59 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
55 0, 5, /* M */ 60};
56 BIT(31), /* gate */ 61
57 BIT(28), /* lock */ 62static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
58 0); 63 "osc24M", 0x008,
64 8, 7, /* N */
65 0, 5, /* M */
66 pll_audio_sdm_table, BIT(24),
67 0x284, BIT(31),
68 BIT(31), /* gate */
69 BIT(28), /* lock */
70 CLK_SET_RATE_UNGATE);
59 71
60static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video", 72static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
61 "osc24M", 0x0010, 73 "osc24M", 0x0010,
@@ -67,7 +79,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
67 297000000, /* frac rate 1 */ 79 297000000, /* frac rate 1 */
68 BIT(31), /* gate */ 80 BIT(31), /* gate */
69 BIT(28), /* lock */ 81 BIT(28), /* lock */
70 0); 82 CLK_SET_RATE_UNGATE);
71 83
72static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", 84static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
73 "osc24M", 0x0018, 85 "osc24M", 0x0018,
@@ -79,7 +91,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
79 297000000, /* frac rate 1 */ 91 297000000, /* frac rate 1 */
80 BIT(31), /* gate */ 92 BIT(31), /* gate */
81 BIT(28), /* lock */ 93 BIT(28), /* lock */
82 0); 94 CLK_SET_RATE_UNGATE);
83 95
84static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr", 96static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
85 "osc24M", 0x020, 97 "osc24M", 0x020,
@@ -88,7 +100,7 @@ static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
88 0, 2, /* M */ 100 0, 2, /* M */
89 BIT(31), /* gate */ 101 BIT(31), /* gate */
90 BIT(28), /* lock */ 102 BIT(28), /* lock */
91 0); 103 CLK_SET_RATE_UNGATE);
92 104
93static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0", 105static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
94 "osc24M", 0x028, 106 "osc24M", 0x028,
@@ -97,7 +109,7 @@ static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
97 BIT(31), /* gate */ 109 BIT(31), /* gate */
98 BIT(28), /* lock */ 110 BIT(28), /* lock */
99 2, /* post-div */ 111 2, /* post-div */
100 0); 112 CLK_SET_RATE_UNGATE);
101 113
102static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", 114static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
103 "osc24M", 0x0038, 115 "osc24M", 0x0038,
@@ -109,7 +121,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
109 297000000, /* frac rate 1 */ 121 297000000, /* frac rate 1 */
110 BIT(31), /* gate */ 122 BIT(31), /* gate */
111 BIT(28), /* lock */ 123 BIT(28), /* lock */
112 0); 124 CLK_SET_RATE_UNGATE);
113 125
114static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1", 126static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
115 "osc24M", 0x044, 127 "osc24M", 0x044,
@@ -118,7 +130,7 @@ static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
118 BIT(31), /* gate */ 130 BIT(31), /* gate */
119 BIT(28), /* lock */ 131 BIT(28), /* lock */
120 2, /* post-div */ 132 2, /* post-div */
121 0); 133 CLK_SET_RATE_UNGATE);
122 134
123static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", 135static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
124 "osc24M", 0x0048, 136 "osc24M", 0x0048,
@@ -130,7 +142,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
130 297000000, /* frac rate 1 */ 142 297000000, /* frac rate 1 */
131 BIT(31), /* gate */ 143 BIT(31), /* gate */
132 BIT(28), /* lock */ 144 BIT(28), /* lock */
133 0); 145 CLK_SET_RATE_UNGATE);
134 146
135static const char * const cpux_parents[] = { "osc32k", "osc24M", 147static const char * const cpux_parents[] = { "osc32k", "osc24M",
136 "pll-cpux" , "pll-cpux" }; 148 "pll-cpux" , "pll-cpux" };
@@ -484,7 +496,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
484 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); 496 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
485 497
486static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", 498static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
487 0x1a0, 0, 3, BIT(31), 0); 499 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
488 500
489static struct ccu_common *sun8i_h3_ccu_clks[] = { 501static struct ccu_common *sun8i_h3_ccu_clks[] = {
490 &pll_cpux_clk.common, 502 &pll_cpux_clk.common,
@@ -707,9 +719,9 @@ static struct ccu_common *sun50i_h5_ccu_clks[] = {
707 &gpu_clk.common, 719 &gpu_clk.common,
708}; 720};
709 721
710/* We hardcode the divider to 4 for now */ 722/* We hardcode the divider to 1 for now */
711static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", 723static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
712 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); 724 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
713static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", 725static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
714 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); 726 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
715static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", 727static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
@@ -1129,10 +1141,10 @@ static void __init sunxi_h3_h5_ccu_init(struct device_node *node,
1129 return; 1141 return;
1130 } 1142 }
1131 1143
1132 /* Force the PLL-Audio-1x divider to 4 */ 1144 /* Force the PLL-Audio-1x divider to 1 */
1133 val = readl(reg + SUN8I_H3_PLL_AUDIO_REG); 1145 val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
1134 val &= ~GENMASK(19, 16); 1146 val &= ~GENMASK(19, 16);
1135 writel(val | (3 << 16), reg + SUN8I_H3_PLL_AUDIO_REG); 1147 writel(val | (0 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
1136 1148
1137 sunxi_ccu_probe(node, reg, desc); 1149 sunxi_ccu_probe(node, reg, desc);
1138 1150
diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h
index cadd1a9f93b6..5d684ce77c54 100644
--- a/drivers/clk/sunxi-ng/ccu_common.h
+++ b/drivers/clk/sunxi-ng/ccu_common.h
@@ -24,6 +24,7 @@
24#define CCU_FEATURE_ALL_PREDIV BIT(4) 24#define CCU_FEATURE_ALL_PREDIV BIT(4)
25#define CCU_FEATURE_LOCK_REG BIT(5) 25#define CCU_FEATURE_LOCK_REG BIT(5)
26#define CCU_FEATURE_MMC_TIMING_SWITCH BIT(6) 26#define CCU_FEATURE_MMC_TIMING_SWITCH BIT(6)
27#define CCU_FEATURE_SIGMA_DELTA_MOD BIT(7)
27 28
28/* MMC timing mode switch bit */ 29/* MMC timing mode switch bit */
29#define CCU_MMC_NEW_TIMING_MODE BIT(30) 30#define CCU_MMC_NEW_TIMING_MODE BIT(30)
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
index a32158e8f2e3..7620aa973a6e 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.c
+++ b/drivers/clk/sunxi-ng/ccu_nm.c
@@ -90,6 +90,14 @@ static unsigned long ccu_nm_recalc_rate(struct clk_hw *hw,
90 if (!m) 90 if (!m)
91 m++; 91 m++;
92 92
93 if (ccu_sdm_helper_is_enabled(&nm->common, &nm->sdm)) {
94 unsigned long rate =
95 ccu_sdm_helper_read_rate(&nm->common, &nm->sdm,
96 m, n);
97 if (rate)
98 return rate;
99 }
100
93 return parent_rate * n / m; 101 return parent_rate * n / m;
94} 102}
95 103
@@ -99,6 +107,12 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
99 struct ccu_nm *nm = hw_to_ccu_nm(hw); 107 struct ccu_nm *nm = hw_to_ccu_nm(hw);
100 struct _ccu_nm _nm; 108 struct _ccu_nm _nm;
101 109
110 if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate))
111 return rate;
112
113 if (ccu_sdm_helper_has_rate(&nm->common, &nm->sdm, rate))
114 return rate;
115
102 _nm.min_n = nm->n.min ?: 1; 116 _nm.min_n = nm->n.min ?: 1;
103 _nm.max_n = nm->n.max ?: 1 << nm->n.width; 117 _nm.max_n = nm->n.max ?: 1 << nm->n.width;
104 _nm.min_m = 1; 118 _nm.min_m = 1;
@@ -140,7 +154,16 @@ static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate,
140 _nm.min_m = 1; 154 _nm.min_m = 1;
141 _nm.max_m = nm->m.max ?: 1 << nm->m.width; 155 _nm.max_m = nm->m.max ?: 1 << nm->m.width;
142 156
143 ccu_nm_find_best(parent_rate, rate, &_nm); 157 if (ccu_sdm_helper_has_rate(&nm->common, &nm->sdm, rate)) {
158 ccu_sdm_helper_enable(&nm->common, &nm->sdm, rate);
159
160 /* Sigma delta modulation requires specific N and M factors */
161 ccu_sdm_helper_get_factors(&nm->common, &nm->sdm, rate,
162 &_nm.m, &_nm.n);
163 } else {
164 ccu_sdm_helper_disable(&nm->common, &nm->sdm);
165 ccu_nm_find_best(parent_rate, rate, &_nm);
166 }
144 167
145 spin_lock_irqsave(nm->common.lock, flags); 168 spin_lock_irqsave(nm->common.lock, flags);
146 169
diff --git a/drivers/clk/sunxi-ng/ccu_nm.h b/drivers/clk/sunxi-ng/ccu_nm.h
index e87fd186da78..c623b0c7a23c 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.h
+++ b/drivers/clk/sunxi-ng/ccu_nm.h
@@ -20,6 +20,7 @@
20#include "ccu_div.h" 20#include "ccu_div.h"
21#include "ccu_frac.h" 21#include "ccu_frac.h"
22#include "ccu_mult.h" 22#include "ccu_mult.h"
23#include "ccu_sdm.h"
23 24
24/* 25/*
25 * struct ccu_nm - Definition of an N-M clock 26 * struct ccu_nm - Definition of an N-M clock
@@ -33,10 +34,34 @@ struct ccu_nm {
33 struct ccu_mult_internal n; 34 struct ccu_mult_internal n;
34 struct ccu_div_internal m; 35 struct ccu_div_internal m;
35 struct ccu_frac_internal frac; 36 struct ccu_frac_internal frac;
37 struct ccu_sdm_internal sdm;
36 38
37 struct ccu_common common; 39 struct ccu_common common;
38}; 40};
39 41
42#define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \
43 _nshift, _nwidth, \
44 _mshift, _mwidth, \
45 _sdm_table, _sdm_en, \
46 _sdm_reg, _sdm_reg_en, \
47 _gate, _lock, _flags) \
48 struct ccu_nm _struct = { \
49 .enable = _gate, \
50 .lock = _lock, \
51 .n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
52 .m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
53 .sdm = _SUNXI_CCU_SDM(_sdm_table, _sdm_en, \
54 _sdm_reg, _sdm_reg_en),\
55 .common = { \
56 .reg = _reg, \
57 .features = CCU_FEATURE_SIGMA_DELTA_MOD, \
58 .hw.init = CLK_HW_INIT(_name, \
59 _parent, \
60 &ccu_nm_ops, \
61 _flags), \
62 }, \
63 }
64
40#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ 65#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \
41 _nshift, _nwidth, \ 66 _nshift, _nwidth, \
42 _mshift, _mwidth, \ 67 _mshift, _mwidth, \
diff --git a/drivers/clk/sunxi-ng/ccu_reset.c b/drivers/clk/sunxi-ng/ccu_reset.c
index 1dc4e98ea802..b67149143554 100644
--- a/drivers/clk/sunxi-ng/ccu_reset.c
+++ b/drivers/clk/sunxi-ng/ccu_reset.c
@@ -60,8 +60,22 @@ static int ccu_reset_reset(struct reset_controller_dev *rcdev,
60 return 0; 60 return 0;
61} 61}
62 62
63static int ccu_reset_status(struct reset_controller_dev *rcdev,
64 unsigned long id)
65{
66 struct ccu_reset *ccu = rcdev_to_ccu_reset(rcdev);
67 const struct ccu_reset_map *map = &ccu->reset_map[id];
68
69 /*
70 * The reset control API expects 0 if reset is not asserted,
71 * which is the opposite of what our hardware uses.
72 */
73 return !(map->bit & readl(ccu->base + map->reg));
74}
75
63const struct reset_control_ops ccu_reset_ops = { 76const struct reset_control_ops ccu_reset_ops = {
64 .assert = ccu_reset_assert, 77 .assert = ccu_reset_assert,
65 .deassert = ccu_reset_deassert, 78 .deassert = ccu_reset_deassert,
66 .reset = ccu_reset_reset, 79 .reset = ccu_reset_reset,
80 .status = ccu_reset_status,
67}; 81};
diff --git a/drivers/clk/sunxi-ng/ccu_sdm.c b/drivers/clk/sunxi-ng/ccu_sdm.c
new file mode 100644
index 000000000000..3b3dc9bdf2b0
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_sdm.c
@@ -0,0 +1,158 @@
1/*
2 * Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 */
9
10#include <linux/clk-provider.h>
11#include <linux/spinlock.h>
12
13#include "ccu_sdm.h"
14
15bool ccu_sdm_helper_is_enabled(struct ccu_common *common,
16 struct ccu_sdm_internal *sdm)
17{
18 if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD))
19 return false;
20
21 if (sdm->enable && !(readl(common->base + common->reg) & sdm->enable))
22 return false;
23
24 return !!(readl(common->base + sdm->tuning_reg) & sdm->tuning_enable);
25}
26
27void ccu_sdm_helper_enable(struct ccu_common *common,
28 struct ccu_sdm_internal *sdm,
29 unsigned long rate)
30{
31 unsigned long flags;
32 unsigned int i;
33 u32 reg;
34
35 if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD))
36 return;
37
38 /* Set the pattern */
39 for (i = 0; i < sdm->table_size; i++)
40 if (sdm->table[i].rate == rate)
41 writel(sdm->table[i].pattern,
42 common->base + sdm->tuning_reg);
43
44 /* Make sure SDM is enabled */
45 spin_lock_irqsave(common->lock, flags);
46 reg = readl(common->base + sdm->tuning_reg);
47 writel(reg | sdm->tuning_enable, common->base + sdm->tuning_reg);
48 spin_unlock_irqrestore(common->lock, flags);
49
50 spin_lock_irqsave(common->lock, flags);
51 reg = readl(common->base + common->reg);
52 writel(reg | sdm->enable, common->base + common->reg);
53 spin_unlock_irqrestore(common->lock, flags);
54}
55
56void ccu_sdm_helper_disable(struct ccu_common *common,
57 struct ccu_sdm_internal *sdm)
58{
59 unsigned long flags;
60 u32 reg;
61
62 if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD))
63 return;
64
65 spin_lock_irqsave(common->lock, flags);
66 reg = readl(common->base + common->reg);
67 writel(reg & ~sdm->enable, common->base + common->reg);
68 spin_unlock_irqrestore(common->lock, flags);
69
70 spin_lock_irqsave(common->lock, flags);
71 reg = readl(common->base + sdm->tuning_reg);
72 writel(reg & ~sdm->tuning_enable, common->base + sdm->tuning_reg);
73 spin_unlock_irqrestore(common->lock, flags);
74}
75
76/*
77 * Sigma delta modulation provides a way to do fractional-N frequency
78 * synthesis, in essence allowing the PLL to output any frequency
79 * within its operational range. On earlier SoCs such as the A10/A20,
80 * some PLLs support this. On later SoCs, all PLLs support this.
81 *
82 * The datasheets do not explain what the "wave top" and "wave bottom"
83 * parameters mean or do, nor how to calculate the effective output
84 * frequency. The only examples (and real world usage) are for the audio
85 * PLL to generate 24.576 and 22.5792 MHz clock rates used by the audio
86 * peripherals. The author lacks the underlying domain knowledge to
87 * pursue this.
88 *
89 * The goal and function of the following code is to support the two
90 * clock rates used by the audio subsystem, allowing for proper audio
91 * playback and capture without any pitch or speed changes.
92 */
93bool ccu_sdm_helper_has_rate(struct ccu_common *common,
94 struct ccu_sdm_internal *sdm,
95 unsigned long rate)
96{
97 unsigned int i;
98
99 if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD))
100 return false;
101
102 for (i = 0; i < sdm->table_size; i++)
103 if (sdm->table[i].rate == rate)
104 return true;
105
106 return false;
107}
108
109unsigned long ccu_sdm_helper_read_rate(struct ccu_common *common,
110 struct ccu_sdm_internal *sdm,
111 u32 m, u32 n)
112{
113 unsigned int i;
114 u32 reg;
115
116 pr_debug("%s: Read sigma-delta modulation setting\n",
117 clk_hw_get_name(&common->hw));
118
119 if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD))
120 return 0;
121
122 pr_debug("%s: clock is sigma-delta modulated\n",
123 clk_hw_get_name(&common->hw));
124
125 reg = readl(common->base + sdm->tuning_reg);
126
127 pr_debug("%s: pattern reg is 0x%x",
128 clk_hw_get_name(&common->hw), reg);
129
130 for (i = 0; i < sdm->table_size; i++)
131 if (sdm->table[i].pattern == reg &&
132 sdm->table[i].m == m && sdm->table[i].n == n)
133 return sdm->table[i].rate;
134
135 /* We can't calculate the effective clock rate, so just fail. */
136 return 0;
137}
138
139int ccu_sdm_helper_get_factors(struct ccu_common *common,
140 struct ccu_sdm_internal *sdm,
141 unsigned long rate,
142 unsigned long *m, unsigned long *n)
143{
144 unsigned int i;
145
146 if (!(common->features & CCU_FEATURE_SIGMA_DELTA_MOD))
147 return -EINVAL;
148
149 for (i = 0; i < sdm->table_size; i++)
150 if (sdm->table[i].rate == rate) {
151 *m = sdm->table[i].m;
152 *n = sdm->table[i].n;
153 return 0;
154 }
155
156 /* nothing found */
157 return -EINVAL;
158}
diff --git a/drivers/clk/sunxi-ng/ccu_sdm.h b/drivers/clk/sunxi-ng/ccu_sdm.h
new file mode 100644
index 000000000000..2a9b4a2584d6
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu_sdm.h
@@ -0,0 +1,80 @@
1/*
2 * Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _CCU_SDM_H
15#define _CCU_SDM_H
16
17#include <linux/clk-provider.h>
18
19#include "ccu_common.h"
20
21struct ccu_sdm_setting {
22 unsigned long rate;
23
24 /*
25 * XXX We don't know what the step and bottom register fields
26 * mean. Just copy the whole register value from the vendor
27 * kernel for now.
28 */
29 u32 pattern;
30
31 /*
32 * M and N factors here should be the values used in
33 * calculation, not the raw values written to registers
34 */
35 u32 m;
36 u32 n;
37};
38
39struct ccu_sdm_internal {
40 struct ccu_sdm_setting *table;
41 u32 table_size;
42 /* early SoCs don't have the SDM enable bit in the PLL register */
43 u32 enable;
44 /* second enable bit in tuning register */
45 u32 tuning_enable;
46 u16 tuning_reg;
47};
48
49#define _SUNXI_CCU_SDM(_table, _enable, \
50 _reg, _reg_enable) \
51 { \
52 .table = _table, \
53 .table_size = ARRAY_SIZE(_table), \
54 .enable = _enable, \
55 .tuning_enable = _reg_enable, \
56 .tuning_reg = _reg, \
57 }
58
59bool ccu_sdm_helper_is_enabled(struct ccu_common *common,
60 struct ccu_sdm_internal *sdm);
61void ccu_sdm_helper_enable(struct ccu_common *common,
62 struct ccu_sdm_internal *sdm,
63 unsigned long rate);
64void ccu_sdm_helper_disable(struct ccu_common *common,
65 struct ccu_sdm_internal *sdm);
66
67bool ccu_sdm_helper_has_rate(struct ccu_common *common,
68 struct ccu_sdm_internal *sdm,
69 unsigned long rate);
70
71unsigned long ccu_sdm_helper_read_rate(struct ccu_common *common,
72 struct ccu_sdm_internal *sdm,
73 u32 m, u32 n);
74
75int ccu_sdm_helper_get_factors(struct ccu_common *common,
76 struct ccu_sdm_internal *sdm,
77 unsigned long rate,
78 unsigned long *m, unsigned long *n);
79
80#endif
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index dfe5e3e32d28..856fef65433b 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -276,13 +276,11 @@ void sunxi_factors_unregister(struct device_node *node, struct clk *clk)
276{ 276{
277 struct clk_hw *hw = __clk_get_hw(clk); 277 struct clk_hw *hw = __clk_get_hw(clk);
278 struct clk_factors *factors; 278 struct clk_factors *factors;
279 const char *name;
280 279
281 if (!hw) 280 if (!hw)
282 return; 281 return;
283 282
284 factors = to_clk_factors(hw); 283 factors = to_clk_factors(hw);
285 name = clk_hw_get_name(hw);
286 284
287 of_clk_del_provider(node); 285 of_clk_del_provider(node);
288 /* TODO: The composite clock stuff will leak a bit here. */ 286 /* TODO: The composite clock stuff will leak a bit here. */
diff --git a/drivers/clk/sunxi/clk-sun9i-mmc.c b/drivers/clk/sunxi/clk-sun9i-mmc.c
index 6041bdba2e97..a1a634253d6f 100644
--- a/drivers/clk/sunxi/clk-sun9i-mmc.c
+++ b/drivers/clk/sunxi/clk-sun9i-mmc.c
@@ -124,7 +124,7 @@ static int sun9i_a80_mmc_config_clk_probe(struct platform_device *pdev)
124 return PTR_ERR(data->clk); 124 return PTR_ERR(data->clk);
125 } 125 }
126 126
127 data->reset = devm_reset_control_get(&pdev->dev, NULL); 127 data->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
128 if (IS_ERR(data->reset)) { 128 if (IS_ERR(data->reset)) {
129 dev_err(&pdev->dev, "Could not get reset control\n"); 129 dev_err(&pdev->dev, "Could not get reset control\n");
130 return PTR_ERR(data->reset); 130 return PTR_ERR(data->reset);
diff --git a/drivers/clk/tegra/clk-bpmp.c b/drivers/clk/tegra/clk-bpmp.c
index 638ace64033b..a896692b74ec 100644
--- a/drivers/clk/tegra/clk-bpmp.c
+++ b/drivers/clk/tegra/clk-bpmp.c
@@ -55,6 +55,7 @@ struct tegra_bpmp_clk_message {
55 struct { 55 struct {
56 void *data; 56 void *data;
57 size_t size; 57 size_t size;
58 int ret;
58 } rx; 59 } rx;
59}; 60};
60 61
@@ -64,6 +65,7 @@ static int tegra_bpmp_clk_transfer(struct tegra_bpmp *bpmp,
64 struct mrq_clk_request request; 65 struct mrq_clk_request request;
65 struct tegra_bpmp_message msg; 66 struct tegra_bpmp_message msg;
66 void *req = &request; 67 void *req = &request;
68 int err;
67 69
68 memset(&request, 0, sizeof(request)); 70 memset(&request, 0, sizeof(request));
69 request.cmd_and_id = (clk->cmd << 24) | clk->id; 71 request.cmd_and_id = (clk->cmd << 24) | clk->id;
@@ -84,7 +86,13 @@ static int tegra_bpmp_clk_transfer(struct tegra_bpmp *bpmp,
84 msg.rx.data = clk->rx.data; 86 msg.rx.data = clk->rx.data;
85 msg.rx.size = clk->rx.size; 87 msg.rx.size = clk->rx.size;
86 88
87 return tegra_bpmp_transfer(bpmp, &msg); 89 err = tegra_bpmp_transfer(bpmp, &msg);
90 if (err < 0)
91 return err;
92 else if (msg.rx.ret < 0)
93 return -EINVAL;
94
95 return 0;
88} 96}
89 97
90static int tegra_bpmp_clk_prepare(struct clk_hw *hw) 98static int tegra_bpmp_clk_prepare(struct clk_hw *hw)
@@ -414,11 +422,8 @@ static int tegra_bpmp_probe_clocks(struct tegra_bpmp *bpmp,
414 struct tegra_bpmp_clk_info *info = &clocks[count]; 422 struct tegra_bpmp_clk_info *info = &clocks[count];
415 423
416 err = tegra_bpmp_clk_get_info(bpmp, id, info); 424 err = tegra_bpmp_clk_get_info(bpmp, id, info);
417 if (err < 0) { 425 if (err < 0)
418 dev_err(bpmp->dev, "failed to query clock %u: %d\n",
419 id, err);
420 continue; 426 continue;
421 }
422 427
423 if (info->num_parents >= U8_MAX) { 428 if (info->num_parents >= U8_MAX) {
424 dev_err(bpmp->dev, 429 dev_err(bpmp->dev,
diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
index 2c44aeb0b97c..0a7deee74eea 100644
--- a/drivers/clk/tegra/clk-dfll.c
+++ b/drivers/clk/tegra/clk-dfll.c
@@ -1728,10 +1728,10 @@ EXPORT_SYMBOL(tegra_dfll_register);
1728 * @pdev: DFLL platform_device * 1728 * @pdev: DFLL platform_device *
1729 * 1729 *
1730 * Unbind this driver from the DFLL hardware device represented by 1730 * Unbind this driver from the DFLL hardware device represented by
1731 * @pdev. The DFLL must be disabled for this to succeed. Returns 0 1731 * @pdev. The DFLL must be disabled for this to succeed. Returns a
1732 * upon success or -EBUSY if the DFLL is still active. 1732 * soc pointer upon success or -EBUSY if the DFLL is still active.
1733 */ 1733 */
1734int tegra_dfll_unregister(struct platform_device *pdev) 1734struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev)
1735{ 1735{
1736 struct tegra_dfll *td = platform_get_drvdata(pdev); 1736 struct tegra_dfll *td = platform_get_drvdata(pdev);
1737 1737
@@ -1739,7 +1739,7 @@ int tegra_dfll_unregister(struct platform_device *pdev)
1739 if (td->mode != DFLL_DISABLED) { 1739 if (td->mode != DFLL_DISABLED) {
1740 dev_err(&pdev->dev, 1740 dev_err(&pdev->dev,
1741 "must disable DFLL before removing driver\n"); 1741 "must disable DFLL before removing driver\n");
1742 return -EBUSY; 1742 return ERR_PTR(-EBUSY);
1743 } 1743 }
1744 1744
1745 debugfs_remove_recursive(td->debugfs_dir); 1745 debugfs_remove_recursive(td->debugfs_dir);
@@ -1753,6 +1753,6 @@ int tegra_dfll_unregister(struct platform_device *pdev)
1753 1753
1754 reset_control_assert(td->dvco_rst); 1754 reset_control_assert(td->dvco_rst);
1755 1755
1756 return 0; 1756 return td->soc;
1757} 1757}
1758EXPORT_SYMBOL(tegra_dfll_unregister); 1758EXPORT_SYMBOL(tegra_dfll_unregister);
diff --git a/drivers/clk/tegra/clk-dfll.h b/drivers/clk/tegra/clk-dfll.h
index ed2ad888268f..83352c8078f2 100644
--- a/drivers/clk/tegra/clk-dfll.h
+++ b/drivers/clk/tegra/clk-dfll.h
@@ -43,7 +43,7 @@ struct tegra_dfll_soc_data {
43 43
44int tegra_dfll_register(struct platform_device *pdev, 44int tegra_dfll_register(struct platform_device *pdev,
45 struct tegra_dfll_soc_data *soc); 45 struct tegra_dfll_soc_data *soc);
46int tegra_dfll_unregister(struct platform_device *pdev); 46struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev);
47int tegra_dfll_runtime_suspend(struct device *dev); 47int tegra_dfll_runtime_suspend(struct device *dev);
48int tegra_dfll_runtime_resume(struct device *dev); 48int tegra_dfll_runtime_resume(struct device *dev);
49 49
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index 11ee5f9ce99e..b616e33c5255 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -13,6 +13,7 @@ enum clk_id {
13 tegra_clk_amx, 13 tegra_clk_amx,
14 tegra_clk_amx1, 14 tegra_clk_amx1,
15 tegra_clk_apb2ape, 15 tegra_clk_apb2ape,
16 tegra_clk_ahbdma,
16 tegra_clk_apbdma, 17 tegra_clk_apbdma,
17 tegra_clk_apbif, 18 tegra_clk_apbif,
18 tegra_clk_ape, 19 tegra_clk_ape,
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index cf80831de79d..9475c00b7cf9 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -203,3 +203,11 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
203 return _tegra_clk_register_periph(name, parent_names, num_parents, 203 return _tegra_clk_register_periph(name, parent_names, num_parents,
204 periph, clk_base, offset, CLK_SET_RATE_PARENT); 204 periph, clk_base, offset, CLK_SET_RATE_PARENT);
205} 205}
206
207struct clk *tegra_clk_register_periph_data(void __iomem *clk_base,
208 struct tegra_periph_init_data *init)
209{
210 return _tegra_clk_register_periph(init->name, init->p.parent_names,
211 init->num_parents, &init->periph,
212 clk_base, init->offset, init->flags);
213}
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 848255cc0209..c02711927d79 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -129,7 +129,6 @@
129#define CLK_SOURCE_NVDEC 0x698 129#define CLK_SOURCE_NVDEC 0x698
130#define CLK_SOURCE_NVJPG 0x69c 130#define CLK_SOURCE_NVJPG 0x69c
131#define CLK_SOURCE_APE 0x6c0 131#define CLK_SOURCE_APE 0x6c0
132#define CLK_SOURCE_SOR1 0x410
133#define CLK_SOURCE_SDMMC_LEGACY 0x694 132#define CLK_SOURCE_SDMMC_LEGACY 0x694
134#define CLK_SOURCE_QSPI 0x6c4 133#define CLK_SOURCE_QSPI 0x6c4
135#define CLK_SOURCE_VI_I2C 0x6c8 134#define CLK_SOURCE_VI_I2C 0x6c8
@@ -278,7 +277,6 @@ static DEFINE_SPINLOCK(PLLP_OUTA_lock);
278static DEFINE_SPINLOCK(PLLP_OUTB_lock); 277static DEFINE_SPINLOCK(PLLP_OUTB_lock);
279static DEFINE_SPINLOCK(PLLP_OUTC_lock); 278static DEFINE_SPINLOCK(PLLP_OUTC_lock);
280static DEFINE_SPINLOCK(sor0_lock); 279static DEFINE_SPINLOCK(sor0_lock);
281static DEFINE_SPINLOCK(sor1_lock);
282 280
283#define MUX_I2S_SPDIF(_id) \ 281#define MUX_I2S_SPDIF(_id) \
284static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \ 282static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { "pll_a_out0", \
@@ -604,18 +602,6 @@ static u32 mux_pllp_plld_plld2_clkm_idx[] = {
604 [0] = 0, [1] = 2, [2] = 5, [3] = 6 602 [0] = 0, [1] = 2, [2] = 5, [3] = 6
605}; 603};
606 604
607static const char *mux_sor_safe_sor1_brick_sor1_src[] = {
608 /*
609 * Bit 0 of the mux selects sor1_brick, irrespective of bit 1, so the
610 * sor1_brick parent appears twice in the list below. This is merely
611 * to support clk_get_parent() if firmware happened to set these bits
612 * to 0b11. While not an invalid setting, code should always set the
613 * bits to 0b01 to select sor1_brick.
614 */
615 "sor_safe", "sor1_brick", "sor1_src", "sor1_brick"
616};
617#define mux_sor_safe_sor1_brick_sor1_src_idx NULL
618
619static const char *mux_pllp_pllre_clkm[] = { 605static const char *mux_pllp_pllre_clkm[] = {
620 "pll_p", "pll_re_out1", "clk_m" 606 "pll_p", "pll_re_out1", "clk_m"
621}; 607};
@@ -804,8 +790,6 @@ static struct tegra_periph_init_data periph_clks[] = {
804 MUX8("nvdec", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec), 790 MUX8("nvdec", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec),
805 MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg), 791 MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg),
806 MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape), 792 MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape),
807 MUX8_NOGATE_LOCK("sor1_src", mux_pllp_plld_plld2_clkm, CLK_SOURCE_SOR1, tegra_clk_sor1_src, &sor1_lock),
808 NODIV("sor1", mux_sor_safe_sor1_brick_sor1_src, CLK_SOURCE_SOR1, 14, MASK(2), 183, 0, tegra_clk_sor1, &sor1_lock),
809 MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy), 793 MUX8("sdmmc_legacy", mux_pllp_out3_clkm_pllp_pllc4, CLK_SOURCE_SDMMC_LEGACY, 193, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_sdmmc_legacy),
810 MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi), 794 MUX8("qspi", mux_pllp_pllc_pllc_out1_pllc4_out2_pllc4_out1_clkm_pllc4_out0, CLK_SOURCE_QSPI, 211, TEGRA_PERIPH_ON_APB, tegra_clk_qspi),
811 I2C("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, tegra_clk_vi_i2c), 795 I2C("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, tegra_clk_vi_i2c),
@@ -823,7 +807,8 @@ static struct tegra_periph_init_data gate_clks[] = {
823 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL), 807 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),
824 GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0), 808 GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
825 GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0), 809 GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
826 GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0), 810 GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0),
811 GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0),
827 GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0), 812 GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
828 GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0), 813 GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
829 GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0), 814 GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
@@ -927,10 +912,7 @@ static void __init periph_clk_init(void __iomem *clk_base,
927 continue; 912 continue;
928 913
929 data->periph.gate.regs = bank; 914 data->periph.gate.regs = bank;
930 clk = tegra_clk_register_periph(data->name, 915 clk = tegra_clk_register_periph_data(clk_base, data);
931 data->p.parent_names, data->num_parents,
932 &data->periph, clk_base, data->offset,
933 data->flags);
934 *dt_clk = clk; 916 *dt_clk = clk;
935 } 917 }
936} 918}
diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c
index 4f6fd307cb70..10047107c1dc 100644
--- a/drivers/clk/tegra/clk-tegra-super-gen4.c
+++ b/drivers/clk/tegra/clk-tegra-super-gen4.c
@@ -166,7 +166,7 @@ static void __init tegra_sclk_init(void __iomem *clk_base,
166 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, 166 clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
167 &sysrate_lock); 167 &sysrate_lock);
168 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT | 168 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT |
169 CLK_IGNORE_UNUSED, clk_base + SYSTEM_CLK_RATE, 169 CLK_IS_CRITICAL, clk_base + SYSTEM_CLK_RATE,
170 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock); 170 3, CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
171 *dt_clk = clk; 171 *dt_clk = clk;
172} 172}
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index fd1a99c05c2d..63087d17c3e2 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -1092,9 +1092,7 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
1092 1092
1093 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 1093 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1094 data = &tegra_periph_clk_list[i]; 1094 data = &tegra_periph_clk_list[i];
1095 clk = tegra_clk_register_periph(data->name, 1095 clk = tegra_clk_register_periph_data(clk_base, data);
1096 data->p.parent_names, data->num_parents,
1097 &data->periph, clk_base, data->offset, data->flags);
1098 clks[data->clk_id] = clk; 1096 clks[data->clk_id] = clk;
1099 } 1097 }
1100 1098
diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
index ad1c1cc829cb..269d3595758b 100644
--- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
+++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
@@ -125,19 +125,17 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
125 return err; 125 return err;
126 } 126 }
127 127
128 platform_set_drvdata(pdev, soc);
129
130 return 0; 128 return 0;
131} 129}
132 130
133static int tegra124_dfll_fcpu_remove(struct platform_device *pdev) 131static int tegra124_dfll_fcpu_remove(struct platform_device *pdev)
134{ 132{
135 struct tegra_dfll_soc_data *soc = platform_get_drvdata(pdev); 133 struct tegra_dfll_soc_data *soc;
136 int err;
137 134
138 err = tegra_dfll_unregister(pdev); 135 soc = tegra_dfll_unregister(pdev);
139 if (err < 0) 136 if (IS_ERR(soc))
140 dev_err(&pdev->dev, "failed to unregister DFLL: %d\n", err); 137 dev_err(&pdev->dev, "failed to unregister DFLL: %ld\n",
138 PTR_ERR(soc));
141 139
142 tegra_cvb_remove_opp_table(soc->dev, soc->cvb, soc->max_freq); 140 tegra_cvb_remove_opp_table(soc->dev, soc->cvb, soc->max_freq);
143 141
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 837e5cbd60e9..cbd5a2e5c569 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -522,6 +522,8 @@ static struct tegra_devclk devclks[] __initdata = {
522}; 522};
523 523
524static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = { 524static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
525 [tegra_clk_ahbdma] = { .dt_id = TEGRA20_CLK_AHBDMA, .present = true },
526 [tegra_clk_apbdma] = { .dt_id = TEGRA20_CLK_APBDMA, .present = true },
525 [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true }, 527 [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true },
526 [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true }, 528 [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true },
527 [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true }, 529 [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true },
@@ -806,11 +808,6 @@ static void __init tegra20_periph_clk_init(void)
806 clk_base, 0, 3, periph_clk_enb_refcnt); 808 clk_base, 0, 3, periph_clk_enb_refcnt);
807 clks[TEGRA20_CLK_AC97] = clk; 809 clks[TEGRA20_CLK_AC97] = clk;
808 810
809 /* apbdma */
810 clk = tegra_clk_register_periph_gate("apbdma", "pclk", 0, clk_base,
811 0, 34, periph_clk_enb_refcnt);
812 clks[TEGRA20_CLK_APBDMA] = clk;
813
814 /* emc */ 811 /* emc */
815 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 812 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
816 ARRAY_SIZE(mux_pllmcp_clkm), 813 ARRAY_SIZE(mux_pllmcp_clkm),
@@ -850,9 +847,7 @@ static void __init tegra20_periph_clk_init(void)
850 847
851 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 848 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
852 data = &tegra_periph_clk_list[i]; 849 data = &tegra_periph_clk_list[i];
853 clk = tegra_clk_register_periph(data->name, data->p.parent_names, 850 clk = tegra_clk_register_periph_data(clk_base, data);
854 data->num_parents, &data->periph,
855 clk_base, data->offset, data->flags);
856 clks[data->clk_id] = clk; 851 clks[data->clk_id] = clk;
857 } 852 }
858 853
@@ -1025,7 +1020,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
1025 { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 }, 1020 { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 },
1026 { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 }, 1021 { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 },
1027 { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1 }, 1022 { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1 },
1028 { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1 }, 1023 { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 216000000, 1 },
1029 { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1 }, 1024 { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1 },
1030 { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1 }, 1025 { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
1031 { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1 }, 1026 { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1 },
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 6d7a613f2656..9e6260869eb9 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -40,6 +40,7 @@
40 40
41#define CLK_SOURCE_CSITE 0x1d4 41#define CLK_SOURCE_CSITE 0x1d4
42#define CLK_SOURCE_EMC 0x19c 42#define CLK_SOURCE_EMC 0x19c
43#define CLK_SOURCE_SOR1 0x410
43 44
44#define PLLC_BASE 0x80 45#define PLLC_BASE 0x80
45#define PLLC_OUT 0x84 46#define PLLC_OUT 0x84
@@ -264,6 +265,7 @@ static DEFINE_SPINLOCK(pll_d_lock);
264static DEFINE_SPINLOCK(pll_e_lock); 265static DEFINE_SPINLOCK(pll_e_lock);
265static DEFINE_SPINLOCK(pll_re_lock); 266static DEFINE_SPINLOCK(pll_re_lock);
266static DEFINE_SPINLOCK(pll_u_lock); 267static DEFINE_SPINLOCK(pll_u_lock);
268static DEFINE_SPINLOCK(sor1_lock);
267static DEFINE_SPINLOCK(emc_lock); 269static DEFINE_SPINLOCK(emc_lock);
268 270
269/* possible OSC frequencies in Hz */ 271/* possible OSC frequencies in Hz */
@@ -2566,8 +2568,8 @@ static int tegra210_enable_pllu(void)
2566 reg |= PLL_ENABLE; 2568 reg |= PLL_ENABLE;
2567 writel(reg, clk_base + PLLU_BASE); 2569 writel(reg, clk_base + PLLU_BASE);
2568 2570
2569 readl_relaxed_poll_timeout(clk_base + PLLU_BASE, reg, 2571 readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg,
2570 reg & PLL_BASE_LOCK, 2, 1000); 2572 reg & PLL_BASE_LOCK, 2, 1000);
2571 if (!(reg & PLL_BASE_LOCK)) { 2573 if (!(reg & PLL_BASE_LOCK)) {
2572 pr_err("Timed out waiting for PLL_U to lock\n"); 2574 pr_err("Timed out waiting for PLL_U to lock\n");
2573 return -ETIMEDOUT; 2575 return -ETIMEDOUT;
@@ -2628,10 +2630,35 @@ static int tegra210_init_pllu(void)
2628 return 0; 2630 return 0;
2629} 2631}
2630 2632
2633static const char * const sor1_out_parents[] = {
2634 /*
2635 * Bit 0 of the mux selects sor1_pad_clkout, irrespective of bit 1, so
2636 * the sor1_pad_clkout parent appears twice in the list below. This is
2637 * merely to support clk_get_parent() if firmware happened to set
2638 * these bits to 0b11. While not an invalid setting, code should
2639 * always set the bits to 0b01 to select sor1_pad_clkout.
2640 */
2641 "sor_safe", "sor1_pad_clkout", "sor1", "sor1_pad_clkout",
2642};
2643
2644static const char * const sor1_parents[] = {
2645 "pll_p", "pll_d_out0", "pll_d2_out0", "clk_m",
2646};
2647
2648static u32 sor1_parents_idx[] = { 0, 2, 5, 6 };
2649
2650static struct tegra_periph_init_data tegra210_periph[] = {
2651 TEGRA_INIT_DATA_TABLE("sor1", NULL, NULL, sor1_parents,
2652 CLK_SOURCE_SOR1, 29, 0x7, 0, 0, 8, 1,
2653 TEGRA_DIVIDER_ROUND_UP, 183, 0, tegra_clk_sor1,
2654 sor1_parents_idx, 0, &sor1_lock),
2655};
2656
2631static __init void tegra210_periph_clk_init(void __iomem *clk_base, 2657static __init void tegra210_periph_clk_init(void __iomem *clk_base,
2632 void __iomem *pmc_base) 2658 void __iomem *pmc_base)
2633{ 2659{
2634 struct clk *clk; 2660 struct clk *clk;
2661 unsigned int i;
2635 2662
2636 /* xusb_ss_div2 */ 2663 /* xusb_ss_div2 */
2637 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, 2664 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
@@ -2650,6 +2677,12 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
2650 1, 17, 207); 2677 1, 17, 207);
2651 clks[TEGRA210_CLK_DPAUX1] = clk; 2678 clks[TEGRA210_CLK_DPAUX1] = clk;
2652 2679
2680 clk = clk_register_mux_table(NULL, "sor1_out", sor1_out_parents,
2681 ARRAY_SIZE(sor1_out_parents), 0,
2682 clk_base + CLK_SOURCE_SOR1, 14, 0x3,
2683 0, NULL, &sor1_lock);
2684 clks[TEGRA210_CLK_SOR1_OUT] = clk;
2685
2653 /* pll_d_dsi_out */ 2686 /* pll_d_dsi_out */
2654 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0, 2687 clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
2655 clk_base + PLLD_MISC0, 21, 0, &pll_d_lock); 2688 clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);
@@ -2694,6 +2727,20 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
2694 0, NULL); 2727 0, NULL);
2695 clks[TEGRA210_CLK_ACLK] = clk; 2728 clks[TEGRA210_CLK_ACLK] = clk;
2696 2729
2730 for (i = 0; i < ARRAY_SIZE(tegra210_periph); i++) {
2731 struct tegra_periph_init_data *init = &tegra210_periph[i];
2732 struct clk **clkp;
2733
2734 clkp = tegra_lookup_dt_id(init->clk_id, tegra210_clks);
2735 if (!clkp) {
2736 pr_warn("clock %u not found\n", init->clk_id);
2737 continue;
2738 }
2739
2740 clk = tegra_clk_register_periph_data(clk_base, init);
2741 *clkp = clk;
2742 }
2743
2697 tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params); 2744 tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params);
2698} 2745}
2699 2746
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index a2d163f759b4..bee84c554932 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -359,7 +359,7 @@ static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
359}; 359};
360 360
361/* PLL parameters */ 361/* PLL parameters */
362static struct tegra_clk_pll_params pll_c_params = { 362static struct tegra_clk_pll_params pll_c_params __ro_after_init = {
363 .input_min = 2000000, 363 .input_min = 2000000,
364 .input_max = 31000000, 364 .input_max = 31000000,
365 .cf_min = 1000000, 365 .cf_min = 1000000,
@@ -388,7 +388,7 @@ static struct div_nmp pllm_nmp = {
388 .override_divp_shift = 15, 388 .override_divp_shift = 15,
389}; 389};
390 390
391static struct tegra_clk_pll_params pll_m_params = { 391static struct tegra_clk_pll_params pll_m_params __ro_after_init = {
392 .input_min = 2000000, 392 .input_min = 2000000,
393 .input_max = 31000000, 393 .input_max = 31000000,
394 .cf_min = 1000000, 394 .cf_min = 1000000,
@@ -409,7 +409,7 @@ static struct tegra_clk_pll_params pll_m_params = {
409 TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_FIXED, 409 TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_FIXED,
410}; 410};
411 411
412static struct tegra_clk_pll_params pll_p_params = { 412static struct tegra_clk_pll_params pll_p_params __ro_after_init = {
413 .input_min = 2000000, 413 .input_min = 2000000,
414 .input_max = 31000000, 414 .input_max = 31000000,
415 .cf_min = 1000000, 415 .cf_min = 1000000,
@@ -444,7 +444,7 @@ static struct tegra_clk_pll_params pll_a_params = {
444 TEGRA_PLL_HAS_LOCK_ENABLE, 444 TEGRA_PLL_HAS_LOCK_ENABLE,
445}; 445};
446 446
447static struct tegra_clk_pll_params pll_d_params = { 447static struct tegra_clk_pll_params pll_d_params __ro_after_init = {
448 .input_min = 2000000, 448 .input_min = 2000000,
449 .input_max = 40000000, 449 .input_max = 40000000,
450 .cf_min = 1000000, 450 .cf_min = 1000000,
@@ -461,7 +461,7 @@ static struct tegra_clk_pll_params pll_d_params = {
461 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 461 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
462}; 462};
463 463
464static struct tegra_clk_pll_params pll_d2_params = { 464static struct tegra_clk_pll_params pll_d2_params __ro_after_init = {
465 .input_min = 2000000, 465 .input_min = 2000000,
466 .input_max = 40000000, 466 .input_max = 40000000,
467 .cf_min = 1000000, 467 .cf_min = 1000000,
@@ -478,7 +478,7 @@ static struct tegra_clk_pll_params pll_d2_params = {
478 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 478 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
479}; 479};
480 480
481static struct tegra_clk_pll_params pll_u_params = { 481static struct tegra_clk_pll_params pll_u_params __ro_after_init = {
482 .input_min = 2000000, 482 .input_min = 2000000,
483 .input_max = 40000000, 483 .input_max = 40000000,
484 .cf_min = 1000000, 484 .cf_min = 1000000,
@@ -496,7 +496,7 @@ static struct tegra_clk_pll_params pll_u_params = {
496 TEGRA_PLL_HAS_LOCK_ENABLE, 496 TEGRA_PLL_HAS_LOCK_ENABLE,
497}; 497};
498 498
499static struct tegra_clk_pll_params pll_x_params = { 499static struct tegra_clk_pll_params pll_x_params __ro_after_init = {
500 .input_min = 2000000, 500 .input_min = 2000000,
501 .input_max = 31000000, 501 .input_max = 31000000,
502 .cf_min = 1000000, 502 .cf_min = 1000000,
@@ -513,7 +513,7 @@ static struct tegra_clk_pll_params pll_x_params = {
513 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, 513 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
514}; 514};
515 515
516static struct tegra_clk_pll_params pll_e_params = { 516static struct tegra_clk_pll_params pll_e_params __ro_after_init = {
517 .input_min = 12000000, 517 .input_min = 12000000,
518 .input_max = 216000000, 518 .input_max = 216000000,
519 .cf_min = 12000000, 519 .cf_min = 12000000,
@@ -788,6 +788,7 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
788 [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true }, 788 [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },
789 [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true }, 789 [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },
790 [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true }, 790 [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },
791 [tegra_clk_ahbdma] = { .dt_id = TEGRA30_CLK_AHBDMA, .present = true },
791 [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true }, 792 [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },
792 [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true }, 793 [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },
793 [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true }, 794 [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },
@@ -964,7 +965,7 @@ static void __init tegra30_super_clk_init(void)
964 * U71 divider of cclk_lp. 965 * U71 divider of cclk_lp.
965 */ 966 */
966 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3", 967 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
967 clk_base + SUPER_CCLKG_DIVIDER, 0, 968 clk_base + SUPER_CCLKLP_DIVIDER, 0,
968 TEGRA_DIVIDER_INT, 16, 8, 1, NULL); 969 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
969 clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL); 970 clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
970 971
@@ -1079,9 +1080,7 @@ static void __init tegra30_periph_clk_init(void)
1079 1080
1080 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) { 1081 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1081 data = &tegra_periph_clk_list[i]; 1082 data = &tegra_periph_clk_list[i];
1082 clk = tegra_clk_register_periph(data->name, data->p.parent_names, 1083 clk = tegra_clk_register_periph_data(clk_base, data);
1083 data->num_parents, &data->periph,
1084 clk_base, data->offset, data->flags);
1085 clks[data->clk_id] = clk; 1084 clks[data->clk_id] = clk;
1086 } 1085 }
1087 1086
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 872f1189ad7f..3b2763df51c2 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -662,6 +662,9 @@ struct tegra_periph_init_data {
662 _clk_num, _gate_flags, _clk_id,\ 662 _clk_num, _gate_flags, _clk_id,\
663 NULL, 0, NULL) 663 NULL, 0, NULL)
664 664
665struct clk *tegra_clk_register_periph_data(void __iomem *clk_base,
666 struct tegra_periph_init_data *init);
667
665/** 668/**
666 * struct clk_super_mux - super clock 669 * struct clk_super_mux - super clock
667 * 670 *
diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c
index 13eb04f72389..148815470431 100644
--- a/drivers/clk/ti/clk-dra7-atl.c
+++ b/drivers/clk/ti/clk-dra7-atl.c
@@ -274,8 +274,7 @@ static int of_dra7_atl_clk_probe(struct platform_device *pdev)
274 274
275 /* Get configuration for the ATL instances */ 275 /* Get configuration for the ATL instances */
276 snprintf(prop, sizeof(prop), "atl%u", i); 276 snprintf(prop, sizeof(prop), "atl%u", i);
277 of_node_get(node); 277 cfg_node = of_get_child_by_name(node, prop);
278 cfg_node = of_find_node_by_name(node, prop);
279 if (cfg_node) { 278 if (cfg_node) {
280 ret = of_property_read_u32(cfg_node, "bws", 279 ret = of_property_read_u32(cfg_node, "bws",
281 &cdesc->bws); 280 &cdesc->bws);
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
index 88f04a4cb890..77f93f6d2806 100644
--- a/drivers/clk/ti/divider.c
+++ b/drivers/clk/ti/divider.c
@@ -292,10 +292,8 @@ static struct clk *_register_divider(struct device *dev, const char *name,
292 292
293 /* allocate the divider */ 293 /* allocate the divider */
294 div = kzalloc(sizeof(*div), GFP_KERNEL); 294 div = kzalloc(sizeof(*div), GFP_KERNEL);
295 if (!div) { 295 if (!div)
296 pr_err("%s: could not allocate divider clk\n", __func__);
297 return ERR_PTR(-ENOMEM); 296 return ERR_PTR(-ENOMEM);
298 }
299 297
300 init.name = name; 298 init.name = name;
301 init.ops = &ti_clk_divider_ops; 299 init.ops = &ti_clk_divider_ops;
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
index 18c267b38461..d4705803f3d3 100644
--- a/drivers/clk/ti/mux.c
+++ b/drivers/clk/ti/mux.c
@@ -108,10 +108,8 @@ static struct clk *_register_mux(struct device *dev, const char *name,
108 108
109 /* allocate the mux */ 109 /* allocate the mux */
110 mux = kzalloc(sizeof(*mux), GFP_KERNEL); 110 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
111 if (!mux) { 111 if (!mux)
112 pr_err("%s: could not allocate mux clk\n", __func__);
113 return ERR_PTR(-ENOMEM); 112 return ERR_PTR(-ENOMEM);
114 }
115 113
116 init.name = name; 114 init.name = name;
117 init.ops = &ti_clk_mux_ops; 115 init.ops = &ti_clk_mux_ops;
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
index 16e4d303f535..badc478a86c6 100644
--- a/drivers/clk/uniphier/clk-uniphier-mio.c
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -13,6 +13,8 @@
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15 15
16#include <linux/stddef.h>
17
16#include "clk-uniphier.h" 18#include "clk-uniphier.h"
17 19
18#define UNIPHIER_MIO_CLK_SD_FIXED \ 20#define UNIPHIER_MIO_CLK_SD_FIXED \
@@ -73,15 +75,12 @@
73#define UNIPHIER_MIO_CLK_USB2_PHY(idx, ch) \ 75#define UNIPHIER_MIO_CLK_USB2_PHY(idx, ch) \
74 UNIPHIER_CLK_GATE("usb2" #ch "-phy", (idx), "usb2", 0x20 + 0x200 * (ch), 29) 76 UNIPHIER_CLK_GATE("usb2" #ch "-phy", (idx), "usb2", 0x20 + 0x200 * (ch), 29)
75 77
76#define UNIPHIER_MIO_CLK_DMAC(idx) \
77 UNIPHIER_CLK_GATE("miodmac", (idx), "stdmac", 0x20, 25)
78
79const struct uniphier_clk_data uniphier_ld4_mio_clk_data[] = { 78const struct uniphier_clk_data uniphier_ld4_mio_clk_data[] = {
80 UNIPHIER_MIO_CLK_SD_FIXED, 79 UNIPHIER_MIO_CLK_SD_FIXED,
81 UNIPHIER_MIO_CLK_SD(0, 0), 80 UNIPHIER_MIO_CLK_SD(0, 0),
82 UNIPHIER_MIO_CLK_SD(1, 1), 81 UNIPHIER_MIO_CLK_SD(1, 1),
83 UNIPHIER_MIO_CLK_SD(2, 2), 82 UNIPHIER_MIO_CLK_SD(2, 2),
84 UNIPHIER_MIO_CLK_DMAC(7), 83 UNIPHIER_CLK_GATE("miodmac", 7, NULL, 0x20, 25),
85 UNIPHIER_MIO_CLK_USB2(8, 0), 84 UNIPHIER_MIO_CLK_USB2(8, 0),
86 UNIPHIER_MIO_CLK_USB2(9, 1), 85 UNIPHIER_MIO_CLK_USB2(9, 1),
87 UNIPHIER_MIO_CLK_USB2(10, 2), 86 UNIPHIER_MIO_CLK_USB2(10, 2),
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index 07f3b91a7daf..d244e724e198 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -123,7 +123,7 @@ const struct uniphier_clk_data uniphier_sld8_sys_clk_data[] = {
123const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = { 123const struct uniphier_clk_data uniphier_pro5_sys_clk_data[] = {
124 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */ 124 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 120, 1), /* 2400 MHz */
125 UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */ 125 UNIPHIER_CLK_FACTOR("dapll1", -1, "ref", 128, 1), /* 2560 MHz */
126 UNIPHIER_CLK_FACTOR("dapll2", -1, "ref", 144, 125), /* 2949.12 MHz */ 126 UNIPHIER_CLK_FACTOR("dapll2", -1, "dapll1", 144, 125), /* 2949.12 MHz */
127 UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40), 127 UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
128 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48), 128 UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
129 UNIPHIER_PRO5_SYS_CLK_NAND(2), 129 UNIPHIER_PRO5_SYS_CLK_NAND(2),
diff --git a/drivers/clk/ux500/clk-prcc.c b/drivers/clk/ux500/clk-prcc.c
index f50592775c9d..7cfb59c9136d 100644
--- a/drivers/clk/ux500/clk-prcc.c
+++ b/drivers/clk/ux500/clk-prcc.c
@@ -107,11 +107,9 @@ static struct clk *clk_reg_prcc(const char *name,
107 return ERR_PTR(-EINVAL); 107 return ERR_PTR(-EINVAL);
108 } 108 }
109 109
110 clk = kzalloc(sizeof(struct clk_prcc), GFP_KERNEL); 110 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
111 if (!clk) { 111 if (!clk)
112 pr_err("clk_prcc: %s could not allocate clk\n", __func__);
113 return ERR_PTR(-ENOMEM); 112 return ERR_PTR(-ENOMEM);
114 }
115 113
116 clk->base = ioremap(phy_base, SZ_4K); 114 clk->base = ioremap(phy_base, SZ_4K);
117 if (!clk->base) 115 if (!clk->base)
diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c
index 6e3e16b2e5ca..9d1f2d4550ad 100644
--- a/drivers/clk/ux500/clk-prcmu.c
+++ b/drivers/clk/ux500/clk-prcmu.c
@@ -258,11 +258,9 @@ static struct clk *clk_reg_prcmu(const char *name,
258 return ERR_PTR(-EINVAL); 258 return ERR_PTR(-EINVAL);
259 } 259 }
260 260
261 clk = kzalloc(sizeof(struct clk_prcmu), GFP_KERNEL); 261 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
262 if (!clk) { 262 if (!clk)
263 pr_err("clk_prcmu: %s could not allocate clk\n", __func__);
264 return ERR_PTR(-ENOMEM); 263 return ERR_PTR(-ENOMEM);
265 }
266 264
267 clk->cg_sel = cg_sel; 265 clk->cg_sel = cg_sel;
268 clk->is_prepared = 1; 266 clk->is_prepared = 1;
diff --git a/drivers/clk/ux500/clk-sysctrl.c b/drivers/clk/ux500/clk-sysctrl.c
index 8a4e93ce1e42..7c0403b733ae 100644
--- a/drivers/clk/ux500/clk-sysctrl.c
+++ b/drivers/clk/ux500/clk-sysctrl.c
@@ -139,11 +139,9 @@ static struct clk *clk_reg_sysctrl(struct device *dev,
139 return ERR_PTR(-EINVAL); 139 return ERR_PTR(-EINVAL);
140 } 140 }
141 141
142 clk = devm_kzalloc(dev, sizeof(struct clk_sysctrl), GFP_KERNEL); 142 clk = devm_kzalloc(dev, sizeof(*clk), GFP_KERNEL);
143 if (!clk) { 143 if (!clk)
144 dev_err(dev, "clk_sysctrl: could not allocate clk\n");
145 return ERR_PTR(-ENOMEM); 144 return ERR_PTR(-ENOMEM);
146 }
147 145
148 /* set main clock registers */ 146 /* set main clock registers */
149 clk->reg_sel[0] = reg_sel[0]; 147 clk->reg_sel[0] = reg_sel[0];
diff --git a/drivers/clk/versatile/clk-icst.c b/drivers/clk/versatile/clk-icst.c
index 09fbe66f1f11..dafe7a45875d 100644
--- a/drivers/clk/versatile/clk-icst.c
+++ b/drivers/clk/versatile/clk-icst.c
@@ -359,16 +359,13 @@ static struct clk *icst_clk_setup(struct device *dev,
359 struct clk_init_data init; 359 struct clk_init_data init;
360 struct icst_params *pclone; 360 struct icst_params *pclone;
361 361
362 icst = kzalloc(sizeof(struct clk_icst), GFP_KERNEL); 362 icst = kzalloc(sizeof(*icst), GFP_KERNEL);
363 if (!icst) { 363 if (!icst)
364 pr_err("could not allocate ICST clock!\n");
365 return ERR_PTR(-ENOMEM); 364 return ERR_PTR(-ENOMEM);
366 }
367 365
368 pclone = kmemdup(desc->params, sizeof(*pclone), GFP_KERNEL); 366 pclone = kmemdup(desc->params, sizeof(*pclone), GFP_KERNEL);
369 if (!pclone) { 367 if (!pclone) {
370 kfree(icst); 368 kfree(icst);
371 pr_err("could not clone ICST params\n");
372 return ERR_PTR(-ENOMEM); 369 return ERR_PTR(-ENOMEM);
373 } 370 }
374 371
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index c40111f36d5e..e9f9d400c322 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -272,4 +272,39 @@
272/* must be greater than maximal clock id */ 272/* must be greater than maximal clock id */
273#define CLK_NR_CLKS 461 273#define CLK_NR_CLKS 461
274 274
275/* Exynos4x12 ISP clocks */
276#define CLK_ISP_FIMC_ISP 1
277#define CLK_ISP_FIMC_DRC 2
278#define CLK_ISP_FIMC_FD 3
279#define CLK_ISP_FIMC_LITE0 4
280#define CLK_ISP_FIMC_LITE1 5
281#define CLK_ISP_MCUISP 6
282#define CLK_ISP_GICISP 7
283#define CLK_ISP_SMMU_ISP 8
284#define CLK_ISP_SMMU_DRC 9
285#define CLK_ISP_SMMU_FD 10
286#define CLK_ISP_SMMU_LITE0 11
287#define CLK_ISP_SMMU_LITE1 12
288#define CLK_ISP_PPMUISPMX 13
289#define CLK_ISP_PPMUISPX 14
290#define CLK_ISP_MCUCTL_ISP 15
291#define CLK_ISP_MPWM_ISP 16
292#define CLK_ISP_I2C0_ISP 17
293#define CLK_ISP_I2C1_ISP 18
294#define CLK_ISP_MTCADC_ISP 19
295#define CLK_ISP_PWM_ISP 20
296#define CLK_ISP_WDT_ISP 21
297#define CLK_ISP_UART_ISP 22
298#define CLK_ISP_ASYNCAXIM 23
299#define CLK_ISP_SMMU_ISPCX 24
300#define CLK_ISP_SPI0_ISP 25
301#define CLK_ISP_SPI1_ISP 26
302
303#define CLK_ISP_DIV_ISP0 27
304#define CLK_ISP_DIV_ISP1 28
305#define CLK_ISP_DIV_MCUISP0 29
306#define CLK_ISP_DIV_MCUISP1 30
307
308#define CLK_NR_ISP_CLKS 31
309
275#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ 310#endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 8c92528aa48a..8ba99a5e3fd3 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -114,5 +114,16 @@
114#define CLKID_SD_EMMC_A_CLK0 119 114#define CLKID_SD_EMMC_A_CLK0 119
115#define CLKID_SD_EMMC_B_CLK0 122 115#define CLKID_SD_EMMC_B_CLK0 122
116#define CLKID_SD_EMMC_C_CLK0 125 116#define CLKID_SD_EMMC_C_CLK0 125
117#define CLKID_VPU_0_SEL 126
118#define CLKID_VPU_0 128
119#define CLKID_VPU_1_SEL 129
120#define CLKID_VPU_1 131
121#define CLKID_VPU 132
122#define CLKID_VAPB_0_SEL 133
123#define CLKID_VAPB_0 135
124#define CLKID_VAPB_1_SEL 136
125#define CLKID_VAPB_1 138
126#define CLKID_VAPB_SEL 139
127#define CLKID_VAPB 140
117 128
118#endif /* __GXBB_CLKC_H */ 129#endif /* __GXBB_CLKC_H */
diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
index de62a83b6c80..e2f99ae72d5c 100644
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -80,10 +80,10 @@
80#define IMX7D_ARM_M4_ROOT_SRC 67 80#define IMX7D_ARM_M4_ROOT_SRC 67
81#define IMX7D_ARM_M4_ROOT_CG 68 81#define IMX7D_ARM_M4_ROOT_CG 68
82#define IMX7D_ARM_M4_ROOT_DIV 69 82#define IMX7D_ARM_M4_ROOT_DIV 69
83#define IMX7D_ARM_M0_ROOT_CLK 70 83#define IMX7D_ARM_M0_ROOT_CLK 70 /* unused */
84#define IMX7D_ARM_M0_ROOT_SRC 71 84#define IMX7D_ARM_M0_ROOT_SRC 71 /* unused */
85#define IMX7D_ARM_M0_ROOT_CG 72 85#define IMX7D_ARM_M0_ROOT_CG 72 /* unused */
86#define IMX7D_ARM_M0_ROOT_DIV 73 86#define IMX7D_ARM_M0_ROOT_DIV 73 /* unused */
87#define IMX7D_MAIN_AXI_ROOT_CLK 74 87#define IMX7D_MAIN_AXI_ROOT_CLK 74
88#define IMX7D_MAIN_AXI_ROOT_SRC 75 88#define IMX7D_MAIN_AXI_ROOT_SRC 75
89#define IMX7D_MAIN_AXI_ROOT_CG 76 89#define IMX7D_MAIN_AXI_ROOT_CG 76
diff --git a/include/dt-bindings/clock/mt2712-clk.h b/include/dt-bindings/clock/mt2712-clk.h
new file mode 100644
index 000000000000..48a8e797a617
--- /dev/null
+++ b/include/dt-bindings/clock/mt2712-clk.h
@@ -0,0 +1,427 @@
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Weiyi Lu <weiyi.lu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef _DT_BINDINGS_CLK_MT2712_H
16#define _DT_BINDINGS_CLK_MT2712_H
17
18/* APMIXEDSYS */
19
20#define CLK_APMIXED_MAINPLL 0
21#define CLK_APMIXED_UNIVPLL 1
22#define CLK_APMIXED_VCODECPLL 2
23#define CLK_APMIXED_VENCPLL 3
24#define CLK_APMIXED_APLL1 4
25#define CLK_APMIXED_APLL2 5
26#define CLK_APMIXED_LVDSPLL 6
27#define CLK_APMIXED_LVDSPLL2 7
28#define CLK_APMIXED_MSDCPLL 8
29#define CLK_APMIXED_MSDCPLL2 9
30#define CLK_APMIXED_TVDPLL 10
31#define CLK_APMIXED_MMPLL 11
32#define CLK_APMIXED_ARMCA35PLL 12
33#define CLK_APMIXED_ARMCA72PLL 13
34#define CLK_APMIXED_ETHERPLL 14
35#define CLK_APMIXED_NR_CLK 15
36
37/* TOPCKGEN */
38
39#define CLK_TOP_ARMCA35PLL 0
40#define CLK_TOP_ARMCA35PLL_600M 1
41#define CLK_TOP_ARMCA35PLL_400M 2
42#define CLK_TOP_ARMCA72PLL 3
43#define CLK_TOP_SYSPLL 4
44#define CLK_TOP_SYSPLL_D2 5
45#define CLK_TOP_SYSPLL1_D2 6
46#define CLK_TOP_SYSPLL1_D4 7
47#define CLK_TOP_SYSPLL1_D8 8
48#define CLK_TOP_SYSPLL1_D16 9
49#define CLK_TOP_SYSPLL_D3 10
50#define CLK_TOP_SYSPLL2_D2 11
51#define CLK_TOP_SYSPLL2_D4 12
52#define CLK_TOP_SYSPLL_D5 13
53#define CLK_TOP_SYSPLL3_D2 14
54#define CLK_TOP_SYSPLL3_D4 15
55#define CLK_TOP_SYSPLL_D7 16
56#define CLK_TOP_SYSPLL4_D2 17
57#define CLK_TOP_SYSPLL4_D4 18
58#define CLK_TOP_UNIVPLL 19
59#define CLK_TOP_UNIVPLL_D7 20
60#define CLK_TOP_UNIVPLL_D26 21
61#define CLK_TOP_UNIVPLL_D52 22
62#define CLK_TOP_UNIVPLL_D104 23
63#define CLK_TOP_UNIVPLL_D208 24
64#define CLK_TOP_UNIVPLL_D2 25
65#define CLK_TOP_UNIVPLL1_D2 26
66#define CLK_TOP_UNIVPLL1_D4 27
67#define CLK_TOP_UNIVPLL1_D8 28
68#define CLK_TOP_UNIVPLL_D3 29
69#define CLK_TOP_UNIVPLL2_D2 30
70#define CLK_TOP_UNIVPLL2_D4 31
71#define CLK_TOP_UNIVPLL2_D8 32
72#define CLK_TOP_UNIVPLL_D5 33
73#define CLK_TOP_UNIVPLL3_D2 34
74#define CLK_TOP_UNIVPLL3_D4 35
75#define CLK_TOP_UNIVPLL3_D8 36
76#define CLK_TOP_F_MP0_PLL1 37
77#define CLK_TOP_F_MP0_PLL2 38
78#define CLK_TOP_F_BIG_PLL1 39
79#define CLK_TOP_F_BIG_PLL2 40
80#define CLK_TOP_F_BUS_PLL1 41
81#define CLK_TOP_F_BUS_PLL2 42
82#define CLK_TOP_APLL1 43
83#define CLK_TOP_APLL1_D2 44
84#define CLK_TOP_APLL1_D4 45
85#define CLK_TOP_APLL1_D8 46
86#define CLK_TOP_APLL1_D16 47
87#define CLK_TOP_APLL2 48
88#define CLK_TOP_APLL2_D2 49
89#define CLK_TOP_APLL2_D4 50
90#define CLK_TOP_APLL2_D8 51
91#define CLK_TOP_APLL2_D16 52
92#define CLK_TOP_LVDSPLL 53
93#define CLK_TOP_LVDSPLL_D2 54
94#define CLK_TOP_LVDSPLL_D4 55
95#define CLK_TOP_LVDSPLL_D8 56
96#define CLK_TOP_LVDSPLL2 57
97#define CLK_TOP_LVDSPLL2_D2 58
98#define CLK_TOP_LVDSPLL2_D4 59
99#define CLK_TOP_LVDSPLL2_D8 60
100#define CLK_TOP_ETHERPLL_125M 61
101#define CLK_TOP_ETHERPLL_50M 62
102#define CLK_TOP_CVBS 63
103#define CLK_TOP_CVBS_D2 64
104#define CLK_TOP_SYS_26M 65
105#define CLK_TOP_MMPLL 66
106#define CLK_TOP_MMPLL_D2 67
107#define CLK_TOP_VENCPLL 68
108#define CLK_TOP_VENCPLL_D2 69
109#define CLK_TOP_VCODECPLL 70
110#define CLK_TOP_VCODECPLL_D2 71
111#define CLK_TOP_TVDPLL 72
112#define CLK_TOP_TVDPLL_D2 73
113#define CLK_TOP_TVDPLL_D4 74
114#define CLK_TOP_TVDPLL_D8 75
115#define CLK_TOP_TVDPLL_429M 76
116#define CLK_TOP_TVDPLL_429M_D2 77
117#define CLK_TOP_TVDPLL_429M_D4 78
118#define CLK_TOP_MSDCPLL 79
119#define CLK_TOP_MSDCPLL_D2 80
120#define CLK_TOP_MSDCPLL_D4 81
121#define CLK_TOP_MSDCPLL2 82
122#define CLK_TOP_MSDCPLL2_D2 83
123#define CLK_TOP_MSDCPLL2_D4 84
124#define CLK_TOP_CLK26M_D2 85
125#define CLK_TOP_D2A_ULCLK_6P5M 86
126#define CLK_TOP_VPLL3_DPIX 87
127#define CLK_TOP_VPLL_DPIX 88
128#define CLK_TOP_LTEPLL_FS26M 89
129#define CLK_TOP_DMPLL 90
130#define CLK_TOP_DSI0_LNTC 91
131#define CLK_TOP_DSI1_LNTC 92
132#define CLK_TOP_LVDSTX3_CLKDIG_CTS 93
133#define CLK_TOP_LVDSTX_CLKDIG_CTS 94
134#define CLK_TOP_CLKRTC_EXT 95
135#define CLK_TOP_CLKRTC_INT 96
136#define CLK_TOP_CSI0 97
137#define CLK_TOP_CVBSPLL 98
138#define CLK_TOP_AXI_SEL 99
139#define CLK_TOP_MEM_SEL 100
140#define CLK_TOP_MM_SEL 101
141#define CLK_TOP_PWM_SEL 102
142#define CLK_TOP_VDEC_SEL 103
143#define CLK_TOP_VENC_SEL 104
144#define CLK_TOP_MFG_SEL 105
145#define CLK_TOP_CAMTG_SEL 106
146#define CLK_TOP_UART_SEL 107
147#define CLK_TOP_SPI_SEL 108
148#define CLK_TOP_USB20_SEL 109
149#define CLK_TOP_USB30_SEL 110
150#define CLK_TOP_MSDC50_0_HCLK_SEL 111
151#define CLK_TOP_MSDC50_0_SEL 112
152#define CLK_TOP_MSDC30_1_SEL 113
153#define CLK_TOP_MSDC30_2_SEL 114
154#define CLK_TOP_MSDC30_3_SEL 115
155#define CLK_TOP_AUDIO_SEL 116
156#define CLK_TOP_AUD_INTBUS_SEL 117
157#define CLK_TOP_PMICSPI_SEL 118
158#define CLK_TOP_DPILVDS1_SEL 119
159#define CLK_TOP_ATB_SEL 120
160#define CLK_TOP_NR_SEL 121
161#define CLK_TOP_NFI2X_SEL 122
162#define CLK_TOP_IRDA_SEL 123
163#define CLK_TOP_CCI400_SEL 124
164#define CLK_TOP_AUD_1_SEL 125
165#define CLK_TOP_AUD_2_SEL 126
166#define CLK_TOP_MEM_MFG_IN_AS_SEL 127
167#define CLK_TOP_AXI_MFG_IN_AS_SEL 128
168#define CLK_TOP_SCAM_SEL 129
169#define CLK_TOP_NFIECC_SEL 130
170#define CLK_TOP_PE2_MAC_P0_SEL 131
171#define CLK_TOP_PE2_MAC_P1_SEL 132
172#define CLK_TOP_DPILVDS_SEL 133
173#define CLK_TOP_MSDC50_3_HCLK_SEL 134
174#define CLK_TOP_HDCP_SEL 135
175#define CLK_TOP_HDCP_24M_SEL 136
176#define CLK_TOP_RTC_SEL 137
177#define CLK_TOP_SPINOR_SEL 138
178#define CLK_TOP_APLL_SEL 139
179#define CLK_TOP_APLL2_SEL 140
180#define CLK_TOP_A1SYS_HP_SEL 141
181#define CLK_TOP_A2SYS_HP_SEL 142
182#define CLK_TOP_ASM_L_SEL 143
183#define CLK_TOP_ASM_M_SEL 144
184#define CLK_TOP_ASM_H_SEL 145
185#define CLK_TOP_I2SO1_SEL 146
186#define CLK_TOP_I2SO2_SEL 147
187#define CLK_TOP_I2SO3_SEL 148
188#define CLK_TOP_TDMO0_SEL 149
189#define CLK_TOP_TDMO1_SEL 150
190#define CLK_TOP_I2SI1_SEL 151
191#define CLK_TOP_I2SI2_SEL 152
192#define CLK_TOP_I2SI3_SEL 153
193#define CLK_TOP_ETHER_125M_SEL 154
194#define CLK_TOP_ETHER_50M_SEL 155
195#define CLK_TOP_JPGDEC_SEL 156
196#define CLK_TOP_SPISLV_SEL 157
197#define CLK_TOP_ETHER_50M_RMII_SEL 158
198#define CLK_TOP_CAM2TG_SEL 159
199#define CLK_TOP_DI_SEL 160
200#define CLK_TOP_TVD_SEL 161
201#define CLK_TOP_I2C_SEL 162
202#define CLK_TOP_PWM_INFRA_SEL 163
203#define CLK_TOP_MSDC0P_AES_SEL 164
204#define CLK_TOP_CMSYS_SEL 165
205#define CLK_TOP_GCPU_SEL 166
206#define CLK_TOP_AUD_APLL1_SEL 167
207#define CLK_TOP_AUD_APLL2_SEL 168
208#define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 169
209#define CLK_TOP_APLL_DIV0 170
210#define CLK_TOP_APLL_DIV1 171
211#define CLK_TOP_APLL_DIV2 172
212#define CLK_TOP_APLL_DIV3 173
213#define CLK_TOP_APLL_DIV4 174
214#define CLK_TOP_APLL_DIV5 175
215#define CLK_TOP_APLL_DIV6 176
216#define CLK_TOP_APLL_DIV7 177
217#define CLK_TOP_APLL_DIV_PDN0 178
218#define CLK_TOP_APLL_DIV_PDN1 179
219#define CLK_TOP_APLL_DIV_PDN2 180
220#define CLK_TOP_APLL_DIV_PDN3 181
221#define CLK_TOP_APLL_DIV_PDN4 182
222#define CLK_TOP_APLL_DIV_PDN5 183
223#define CLK_TOP_APLL_DIV_PDN6 184
224#define CLK_TOP_APLL_DIV_PDN7 185
225#define CLK_TOP_NR_CLK 186
226
227/* INFRACFG */
228
229#define CLK_INFRA_DBGCLK 0
230#define CLK_INFRA_GCE 1
231#define CLK_INFRA_M4U 2
232#define CLK_INFRA_KP 3
233#define CLK_INFRA_AO_SPI0 4
234#define CLK_INFRA_AO_SPI1 5
235#define CLK_INFRA_AO_UART5 6
236#define CLK_INFRA_NR_CLK 7
237
238/* PERICFG */
239
240#define CLK_PERI_NFI 0
241#define CLK_PERI_THERM 1
242#define CLK_PERI_PWM0 2
243#define CLK_PERI_PWM1 3
244#define CLK_PERI_PWM2 4
245#define CLK_PERI_PWM3 5
246#define CLK_PERI_PWM4 6
247#define CLK_PERI_PWM5 7
248#define CLK_PERI_PWM6 8
249#define CLK_PERI_PWM7 9
250#define CLK_PERI_PWM 10
251#define CLK_PERI_AP_DMA 11
252#define CLK_PERI_MSDC30_0 12
253#define CLK_PERI_MSDC30_1 13
254#define CLK_PERI_MSDC30_2 14
255#define CLK_PERI_MSDC30_3 15
256#define CLK_PERI_UART0 16
257#define CLK_PERI_UART1 17
258#define CLK_PERI_UART2 18
259#define CLK_PERI_UART3 19
260#define CLK_PERI_I2C0 20
261#define CLK_PERI_I2C1 21
262#define CLK_PERI_I2C2 22
263#define CLK_PERI_I2C3 23
264#define CLK_PERI_I2C4 24
265#define CLK_PERI_AUXADC 25
266#define CLK_PERI_SPI0 26
267#define CLK_PERI_SPI 27
268#define CLK_PERI_I2C5 28
269#define CLK_PERI_SPI2 29
270#define CLK_PERI_SPI3 30
271#define CLK_PERI_SPI5 31
272#define CLK_PERI_UART4 32
273#define CLK_PERI_SFLASH 33
274#define CLK_PERI_GMAC 34
275#define CLK_PERI_PCIE0 35
276#define CLK_PERI_PCIE1 36
277#define CLK_PERI_GMAC_PCLK 37
278#define CLK_PERI_MSDC50_0_EN 38
279#define CLK_PERI_MSDC30_1_EN 39
280#define CLK_PERI_MSDC30_2_EN 40
281#define CLK_PERI_MSDC30_3_EN 41
282#define CLK_PERI_MSDC50_0_HCLK_EN 42
283#define CLK_PERI_MSDC50_3_HCLK_EN 43
284#define CLK_PERI_NR_CLK 44
285
286/* MCUCFG */
287
288#define CLK_MCU_MP0_SEL 0
289#define CLK_MCU_MP2_SEL 1
290#define CLK_MCU_BUS_SEL 2
291#define CLK_MCU_NR_CLK 3
292
293/* MFGCFG */
294
295#define CLK_MFG_BG3D 0
296#define CLK_MFG_NR_CLK 1
297
298/* MMSYS */
299
300#define CLK_MM_SMI_COMMON 0
301#define CLK_MM_SMI_LARB0 1
302#define CLK_MM_CAM_MDP 2
303#define CLK_MM_MDP_RDMA0 3
304#define CLK_MM_MDP_RDMA1 4
305#define CLK_MM_MDP_RSZ0 5
306#define CLK_MM_MDP_RSZ1 6
307#define CLK_MM_MDP_RSZ2 7
308#define CLK_MM_MDP_TDSHP0 8
309#define CLK_MM_MDP_TDSHP1 9
310#define CLK_MM_MDP_CROP 10
311#define CLK_MM_MDP_WDMA 11
312#define CLK_MM_MDP_WROT0 12
313#define CLK_MM_MDP_WROT1 13
314#define CLK_MM_FAKE_ENG 14
315#define CLK_MM_MUTEX_32K 15
316#define CLK_MM_DISP_OVL0 16
317#define CLK_MM_DISP_OVL1 17
318#define CLK_MM_DISP_RDMA0 18
319#define CLK_MM_DISP_RDMA1 19
320#define CLK_MM_DISP_RDMA2 20
321#define CLK_MM_DISP_WDMA0 21
322#define CLK_MM_DISP_WDMA1 22
323#define CLK_MM_DISP_COLOR0 23
324#define CLK_MM_DISP_COLOR1 24
325#define CLK_MM_DISP_AAL 25
326#define CLK_MM_DISP_GAMMA 26
327#define CLK_MM_DISP_UFOE 27
328#define CLK_MM_DISP_SPLIT0 28
329#define CLK_MM_DISP_OD 29
330#define CLK_MM_DISP_PWM0_MM 30
331#define CLK_MM_DISP_PWM0_26M 31
332#define CLK_MM_DISP_PWM1_MM 32
333#define CLK_MM_DISP_PWM1_26M 33
334#define CLK_MM_DSI0_ENGINE 34
335#define CLK_MM_DSI0_DIGITAL 35
336#define CLK_MM_DSI1_ENGINE 36
337#define CLK_MM_DSI1_DIGITAL 37
338#define CLK_MM_DPI_PIXEL 38
339#define CLK_MM_DPI_ENGINE 39
340#define CLK_MM_DPI1_PIXEL 40
341#define CLK_MM_DPI1_ENGINE 41
342#define CLK_MM_LVDS_PIXEL 42
343#define CLK_MM_LVDS_CTS 43
344#define CLK_MM_SMI_LARB4 44
345#define CLK_MM_SMI_COMMON1 45
346#define CLK_MM_SMI_LARB5 46
347#define CLK_MM_MDP_RDMA2 47
348#define CLK_MM_MDP_TDSHP2 48
349#define CLK_MM_DISP_OVL2 49
350#define CLK_MM_DISP_WDMA2 50
351#define CLK_MM_DISP_COLOR2 51
352#define CLK_MM_DISP_AAL1 52
353#define CLK_MM_DISP_OD1 53
354#define CLK_MM_LVDS1_PIXEL 54
355#define CLK_MM_LVDS1_CTS 55
356#define CLK_MM_SMI_LARB7 56
357#define CLK_MM_MDP_RDMA3 57
358#define CLK_MM_MDP_WROT2 58
359#define CLK_MM_DSI2 59
360#define CLK_MM_DSI2_DIGITAL 60
361#define CLK_MM_DSI3 61
362#define CLK_MM_DSI3_DIGITAL 62
363#define CLK_MM_NR_CLK 63
364
365/* IMGSYS */
366
367#define CLK_IMG_SMI_LARB2 0
368#define CLK_IMG_SENINF_SCAM_EN 1
369#define CLK_IMG_SENINF_CAM_EN 2
370#define CLK_IMG_CAM_SV_EN 3
371#define CLK_IMG_CAM_SV1_EN 4
372#define CLK_IMG_CAM_SV2_EN 5
373#define CLK_IMG_NR_CLK 6
374
375/* BDPSYS */
376
377#define CLK_BDP_BRIDGE_B 0
378#define CLK_BDP_BRIDGE_DRAM 1
379#define CLK_BDP_LARB_DRAM 2
380#define CLK_BDP_WR_CHANNEL_VDI_PXL 3
381#define CLK_BDP_WR_CHANNEL_VDI_DRAM 4
382#define CLK_BDP_WR_CHANNEL_VDI_B 5
383#define CLK_BDP_MT_B 6
384#define CLK_BDP_DISPFMT_27M 7
385#define CLK_BDP_DISPFMT_27M_VDOUT 8
386#define CLK_BDP_DISPFMT_27_74_74 9
387#define CLK_BDP_DISPFMT_2FS 10
388#define CLK_BDP_DISPFMT_2FS_2FS74_148 11
389#define CLK_BDP_DISPFMT_B 12
390#define CLK_BDP_VDO_DRAM 13
391#define CLK_BDP_VDO_2FS 14
392#define CLK_BDP_VDO_B 15
393#define CLK_BDP_WR_CHANNEL_DI_PXL 16
394#define CLK_BDP_WR_CHANNEL_DI_DRAM 17
395#define CLK_BDP_WR_CHANNEL_DI_B 18
396#define CLK_BDP_NR_AGENT 19
397#define CLK_BDP_NR_DRAM 20
398#define CLK_BDP_NR_B 21
399#define CLK_BDP_BRIDGE_RT_B 22
400#define CLK_BDP_BRIDGE_RT_DRAM 23
401#define CLK_BDP_LARB_RT_DRAM 24
402#define CLK_BDP_TVD_TDC 25
403#define CLK_BDP_TVD_54 26
404#define CLK_BDP_TVD_CBUS 27
405#define CLK_BDP_NR_CLK 28
406
407/* VDECSYS */
408
409#define CLK_VDEC_CKEN 0
410#define CLK_VDEC_LARB1_CKEN 1
411#define CLK_VDEC_IMGRZ_CKEN 2
412#define CLK_VDEC_NR_CLK 3
413
414/* VENCSYS */
415
416#define CLK_VENC_SMI_COMMON_CON 0
417#define CLK_VENC_VENC 1
418#define CLK_VENC_SMI_LARB6 2
419#define CLK_VENC_NR_CLK 3
420
421/* JPGDECSYS */
422
423#define CLK_JPGDEC_JPGDEC1 0
424#define CLK_JPGDEC_JPGDEC 1
425#define CLK_JPGDEC_NR_CLK 2
426
427#endif /* _DT_BINDINGS_CLK_MT2712_H */
diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h
new file mode 100644
index 000000000000..3e514ed51d15
--- /dev/null
+++ b/include/dt-bindings/clock/mt7622-clk.h
@@ -0,0 +1,289 @@
1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Chen Zhong <chen.zhong@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef _DT_BINDINGS_CLK_MT7622_H
16#define _DT_BINDINGS_CLK_MT7622_H
17
18/* TOPCKGEN */
19
20#define CLK_TOP_TO_U2_PHY 0
21#define CLK_TOP_TO_U2_PHY_1P 1
22#define CLK_TOP_PCIE0_PIPE_EN 2
23#define CLK_TOP_PCIE1_PIPE_EN 3
24#define CLK_TOP_SSUSB_TX250M 4
25#define CLK_TOP_SSUSB_EQ_RX250M 5
26#define CLK_TOP_SSUSB_CDR_REF 6
27#define CLK_TOP_SSUSB_CDR_FB 7
28#define CLK_TOP_SATA_ASIC 8
29#define CLK_TOP_SATA_RBC 9
30#define CLK_TOP_TO_USB3_SYS 10
31#define CLK_TOP_P1_1MHZ 11
32#define CLK_TOP_4MHZ 12
33#define CLK_TOP_P0_1MHZ 13
34#define CLK_TOP_TXCLK_SRC_PRE 14
35#define CLK_TOP_RTC 15
36#define CLK_TOP_MEMPLL 16
37#define CLK_TOP_DMPLL 17
38#define CLK_TOP_SYSPLL_D2 18
39#define CLK_TOP_SYSPLL1_D2 19
40#define CLK_TOP_SYSPLL1_D4 20
41#define CLK_TOP_SYSPLL1_D8 21
42#define CLK_TOP_SYSPLL2_D4 22
43#define CLK_TOP_SYSPLL2_D8 23
44#define CLK_TOP_SYSPLL_D5 24
45#define CLK_TOP_SYSPLL3_D2 25
46#define CLK_TOP_SYSPLL3_D4 26
47#define CLK_TOP_SYSPLL4_D2 27
48#define CLK_TOP_SYSPLL4_D4 28
49#define CLK_TOP_SYSPLL4_D16 29
50#define CLK_TOP_UNIVPLL 30
51#define CLK_TOP_UNIVPLL_D2 31
52#define CLK_TOP_UNIVPLL1_D2 32
53#define CLK_TOP_UNIVPLL1_D4 33
54#define CLK_TOP_UNIVPLL1_D8 34
55#define CLK_TOP_UNIVPLL1_D16 35
56#define CLK_TOP_UNIVPLL2_D2 36
57#define CLK_TOP_UNIVPLL2_D4 37
58#define CLK_TOP_UNIVPLL2_D8 38
59#define CLK_TOP_UNIVPLL2_D16 39
60#define CLK_TOP_UNIVPLL_D5 40
61#define CLK_TOP_UNIVPLL3_D2 41
62#define CLK_TOP_UNIVPLL3_D4 42
63#define CLK_TOP_UNIVPLL3_D16 43
64#define CLK_TOP_UNIVPLL_D7 44
65#define CLK_TOP_UNIVPLL_D80_D4 45
66#define CLK_TOP_UNIV48M 46
67#define CLK_TOP_SGMIIPLL 47
68#define CLK_TOP_SGMIIPLL_D2 48
69#define CLK_TOP_AUD1PLL 49
70#define CLK_TOP_AUD2PLL 50
71#define CLK_TOP_AUD_I2S2_MCK 51
72#define CLK_TOP_TO_USB3_REF 52
73#define CLK_TOP_PCIE1_MAC_EN 53
74#define CLK_TOP_PCIE0_MAC_EN 54
75#define CLK_TOP_ETH_500M 55
76#define CLK_TOP_AXI_SEL 56
77#define CLK_TOP_MEM_SEL 57
78#define CLK_TOP_DDRPHYCFG_SEL 58
79#define CLK_TOP_ETH_SEL 59
80#define CLK_TOP_PWM_SEL 60
81#define CLK_TOP_F10M_REF_SEL 61
82#define CLK_TOP_NFI_INFRA_SEL 62
83#define CLK_TOP_FLASH_SEL 63
84#define CLK_TOP_UART_SEL 64
85#define CLK_TOP_SPI0_SEL 65
86#define CLK_TOP_SPI1_SEL 66
87#define CLK_TOP_MSDC50_0_SEL 67
88#define CLK_TOP_MSDC30_0_SEL 68
89#define CLK_TOP_MSDC30_1_SEL 69
90#define CLK_TOP_A1SYS_HP_SEL 70
91#define CLK_TOP_A2SYS_HP_SEL 71
92#define CLK_TOP_INTDIR_SEL 72
93#define CLK_TOP_AUD_INTBUS_SEL 73
94#define CLK_TOP_PMICSPI_SEL 74
95#define CLK_TOP_SCP_SEL 75
96#define CLK_TOP_ATB_SEL 76
97#define CLK_TOP_HIF_SEL 77
98#define CLK_TOP_AUDIO_SEL 78
99#define CLK_TOP_U2_SEL 79
100#define CLK_TOP_AUD1_SEL 80
101#define CLK_TOP_AUD2_SEL 81
102#define CLK_TOP_IRRX_SEL 82
103#define CLK_TOP_IRTX_SEL 83
104#define CLK_TOP_ASM_L_SEL 84
105#define CLK_TOP_ASM_M_SEL 85
106#define CLK_TOP_ASM_H_SEL 86
107#define CLK_TOP_APLL1_SEL 87
108#define CLK_TOP_APLL2_SEL 88
109#define CLK_TOP_I2S0_MCK_SEL 89
110#define CLK_TOP_I2S1_MCK_SEL 90
111#define CLK_TOP_I2S2_MCK_SEL 91
112#define CLK_TOP_I2S3_MCK_SEL 92
113#define CLK_TOP_APLL1_DIV 93
114#define CLK_TOP_APLL2_DIV 94
115#define CLK_TOP_I2S0_MCK_DIV 95
116#define CLK_TOP_I2S1_MCK_DIV 96
117#define CLK_TOP_I2S2_MCK_DIV 97
118#define CLK_TOP_I2S3_MCK_DIV 98
119#define CLK_TOP_A1SYS_HP_DIV 99
120#define CLK_TOP_A2SYS_HP_DIV 100
121#define CLK_TOP_APLL1_DIV_PD 101
122#define CLK_TOP_APLL2_DIV_PD 102
123#define CLK_TOP_I2S0_MCK_DIV_PD 103
124#define CLK_TOP_I2S1_MCK_DIV_PD 104
125#define CLK_TOP_I2S2_MCK_DIV_PD 105
126#define CLK_TOP_I2S3_MCK_DIV_PD 106
127#define CLK_TOP_A1SYS_HP_DIV_PD 107
128#define CLK_TOP_A2SYS_HP_DIV_PD 108
129#define CLK_TOP_NR_CLK 109
130
131/* INFRACFG */
132
133#define CLK_INFRA_MUX1_SEL 0
134#define CLK_INFRA_DBGCLK_PD 1
135#define CLK_INFRA_AUDIO_PD 2
136#define CLK_INFRA_IRRX_PD 3
137#define CLK_INFRA_APXGPT_PD 4
138#define CLK_INFRA_PMIC_PD 5
139#define CLK_INFRA_TRNG 6
140#define CLK_INFRA_NR_CLK 7
141
142/* PERICFG */
143
144#define CLK_PERIBUS_SEL 0
145#define CLK_PERI_THERM_PD 1
146#define CLK_PERI_PWM1_PD 2
147#define CLK_PERI_PWM2_PD 3
148#define CLK_PERI_PWM3_PD 4
149#define CLK_PERI_PWM4_PD 5
150#define CLK_PERI_PWM5_PD 6
151#define CLK_PERI_PWM6_PD 7
152#define CLK_PERI_PWM7_PD 8
153#define CLK_PERI_PWM_PD 9
154#define CLK_PERI_AP_DMA_PD 10
155#define CLK_PERI_MSDC30_0_PD 11
156#define CLK_PERI_MSDC30_1_PD 12
157#define CLK_PERI_UART0_PD 13
158#define CLK_PERI_UART1_PD 14
159#define CLK_PERI_UART2_PD 15
160#define CLK_PERI_UART3_PD 16
161#define CLK_PERI_UART4_PD 17
162#define CLK_PERI_BTIF_PD 18
163#define CLK_PERI_I2C0_PD 19
164#define CLK_PERI_I2C1_PD 20
165#define CLK_PERI_I2C2_PD 21
166#define CLK_PERI_SPI1_PD 22
167#define CLK_PERI_AUXADC_PD 23
168#define CLK_PERI_SPI0_PD 24
169#define CLK_PERI_SNFI_PD 25
170#define CLK_PERI_NFI_PD 26
171#define CLK_PERI_NFIECC_PD 27
172#define CLK_PERI_FLASH_PD 28
173#define CLK_PERI_IRTX_PD 29
174#define CLK_PERI_NR_CLK 30
175
176/* APMIXEDSYS */
177
178#define CLK_APMIXED_ARMPLL 0
179#define CLK_APMIXED_MAINPLL 1
180#define CLK_APMIXED_UNIV2PLL 2
181#define CLK_APMIXED_ETH1PLL 3
182#define CLK_APMIXED_ETH2PLL 4
183#define CLK_APMIXED_AUD1PLL 5
184#define CLK_APMIXED_AUD2PLL 6
185#define CLK_APMIXED_TRGPLL 7
186#define CLK_APMIXED_SGMIPLL 8
187#define CLK_APMIXED_MAIN_CORE_EN 9
188#define CLK_APMIXED_NR_CLK 10
189
190/* AUDIOSYS */
191
192#define CLK_AUDIO_AFE 0
193#define CLK_AUDIO_HDMI 1
194#define CLK_AUDIO_SPDF 2
195#define CLK_AUDIO_APLL 3
196#define CLK_AUDIO_I2SIN1 4
197#define CLK_AUDIO_I2SIN2 5
198#define CLK_AUDIO_I2SIN3 6
199#define CLK_AUDIO_I2SIN4 7
200#define CLK_AUDIO_I2SO1 8
201#define CLK_AUDIO_I2SO2 9
202#define CLK_AUDIO_I2SO3 10
203#define CLK_AUDIO_I2SO4 11
204#define CLK_AUDIO_ASRCI1 12
205#define CLK_AUDIO_ASRCI2 13
206#define CLK_AUDIO_ASRCO1 14
207#define CLK_AUDIO_ASRCO2 15
208#define CLK_AUDIO_INTDIR 16
209#define CLK_AUDIO_A1SYS 17
210#define CLK_AUDIO_A2SYS 18
211#define CLK_AUDIO_UL1 19
212#define CLK_AUDIO_UL2 20
213#define CLK_AUDIO_UL3 21
214#define CLK_AUDIO_UL4 22
215#define CLK_AUDIO_UL5 23
216#define CLK_AUDIO_UL6 24
217#define CLK_AUDIO_DL1 25
218#define CLK_AUDIO_DL2 26
219#define CLK_AUDIO_DL3 27
220#define CLK_AUDIO_DL4 28
221#define CLK_AUDIO_DL5 29
222#define CLK_AUDIO_DL6 30
223#define CLK_AUDIO_DLMCH 31
224#define CLK_AUDIO_ARB1 32
225#define CLK_AUDIO_AWB 33
226#define CLK_AUDIO_AWB2 34
227#define CLK_AUDIO_DAI 35
228#define CLK_AUDIO_MOD 36
229#define CLK_AUDIO_ASRCI3 37
230#define CLK_AUDIO_ASRCI4 38
231#define CLK_AUDIO_ASRCO3 39
232#define CLK_AUDIO_ASRCO4 40
233#define CLK_AUDIO_MEM_ASRC1 41
234#define CLK_AUDIO_MEM_ASRC2 42
235#define CLK_AUDIO_MEM_ASRC3 43
236#define CLK_AUDIO_MEM_ASRC4 44
237#define CLK_AUDIO_MEM_ASRC5 45
238#define CLK_AUDIO_NR_CLK 46
239
240/* SSUSBSYS */
241
242#define CLK_SSUSB_U2_PHY_1P_EN 0
243#define CLK_SSUSB_U2_PHY_EN 1
244#define CLK_SSUSB_REF_EN 2
245#define CLK_SSUSB_SYS_EN 3
246#define CLK_SSUSB_MCU_EN 4
247#define CLK_SSUSB_DMA_EN 5
248#define CLK_SSUSB_NR_CLK 6
249
250/* PCIESYS */
251
252#define CLK_PCIE_P1_AUX_EN 0
253#define CLK_PCIE_P1_OBFF_EN 1
254#define CLK_PCIE_P1_AHB_EN 2
255#define CLK_PCIE_P1_AXI_EN 3
256#define CLK_PCIE_P1_MAC_EN 4
257#define CLK_PCIE_P1_PIPE_EN 5
258#define CLK_PCIE_P0_AUX_EN 6
259#define CLK_PCIE_P0_OBFF_EN 7
260#define CLK_PCIE_P0_AHB_EN 8
261#define CLK_PCIE_P0_AXI_EN 9
262#define CLK_PCIE_P0_MAC_EN 10
263#define CLK_PCIE_P0_PIPE_EN 11
264#define CLK_SATA_AHB_EN 12
265#define CLK_SATA_AXI_EN 13
266#define CLK_SATA_ASIC_EN 14
267#define CLK_SATA_RBC_EN 15
268#define CLK_SATA_PM_EN 16
269#define CLK_PCIE_NR_CLK 17
270
271/* ETHSYS */
272
273#define CLK_ETH_HSDMA_EN 0
274#define CLK_ETH_ESW_EN 1
275#define CLK_ETH_GP2_EN 2
276#define CLK_ETH_GP1_EN 3
277#define CLK_ETH_GP0_EN 4
278#define CLK_ETH_NR_CLK 5
279
280/* SGMIISYS */
281
282#define CLK_SGMII_TX250M_EN 0
283#define CLK_SGMII_RX250M_EN 1
284#define CLK_SGMII_CDR_REF 2
285#define CLK_SGMII_CDR_FB 3
286#define CLK_SGMII_NR_CLK 4
287
288#endif /* _DT_BINDINGS_CLK_MT7622_H */
289
diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h
index 96b63c00249e..b8337a5fa347 100644
--- a/include/dt-bindings/clock/qcom,rpmcc.h
+++ b/include/dt-bindings/clock/qcom,rpmcc.h
@@ -37,6 +37,9 @@
37#define RPM_SYS_FABRIC_A_CLK 19 37#define RPM_SYS_FABRIC_A_CLK 19
38#define RPM_SFPB_CLK 20 38#define RPM_SFPB_CLK 20
39#define RPM_SFPB_A_CLK 21 39#define RPM_SFPB_A_CLK 21
40#define RPM_SMI_CLK 22
41#define RPM_SMI_A_CLK 23
42#define RPM_PLL4_CLK 24
40 43
41/* SMD RPM clocks */ 44/* SMD RPM clocks */
42#define RPM_SMD_XO_CLK_SRC 0 45#define RPM_SMD_XO_CLK_SRC 0
@@ -101,5 +104,19 @@
101#define RPM_SMD_CXO_A1_A_PIN 59 104#define RPM_SMD_CXO_A1_A_PIN 59
102#define RPM_SMD_CXO_A2_PIN 60 105#define RPM_SMD_CXO_A2_PIN 60
103#define RPM_SMD_CXO_A2_A_PIN 61 106#define RPM_SMD_CXO_A2_A_PIN 61
107#define RPM_SMD_AGGR1_NOC_CLK 62
108#define RPM_SMD_AGGR1_NOC_A_CLK 63
109#define RPM_SMD_AGGR2_NOC_CLK 64
110#define RPM_SMD_AGGR2_NOC_A_CLK 65
111#define RPM_SMD_MMAXI_CLK 66
112#define RPM_SMD_MMAXI_A_CLK 67
113#define RPM_SMD_IPA_CLK 68
114#define RPM_SMD_IPA_A_CLK 69
115#define RPM_SMD_CE1_CLK 70
116#define RPM_SMD_CE1_A_CLK 71
117#define RPM_SMD_DIV_CLK3 72
118#define RPM_SMD_DIV_A_CLK3 73
119#define RPM_SMD_LN_BB_CLK 74
120#define RPM_SMD_LN_BB_A_CLK 75
104 121
105#endif 122#endif
diff --git a/include/dt-bindings/clock/r8a77970-cpg-mssr.h b/include/dt-bindings/clock/r8a77970-cpg-mssr.h
new file mode 100644
index 000000000000..4146395595b1
--- /dev/null
+++ b/include/dt-bindings/clock/r8a77970-cpg-mssr.h
@@ -0,0 +1,48 @@
1/*
2 * Copyright (C) 2016 Renesas Electronics Corp.
3 * Copyright (C) 2017 Cogent Embedded, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10#ifndef __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
11#define __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__
12
13#include <dt-bindings/clock/renesas-cpg-mssr.h>
14
15/* r8a77970 CPG Core Clocks */
16#define R8A77970_CLK_Z2 0
17#define R8A77970_CLK_ZR 1
18#define R8A77970_CLK_ZTR 2
19#define R8A77970_CLK_ZTRD2 3
20#define R8A77970_CLK_ZT 4
21#define R8A77970_CLK_ZX 5
22#define R8A77970_CLK_S1D1 6
23#define R8A77970_CLK_S1D2 7
24#define R8A77970_CLK_S1D4 8
25#define R8A77970_CLK_S2D1 9
26#define R8A77970_CLK_S2D2 10
27#define R8A77970_CLK_S2D4 11
28#define R8A77970_CLK_LB 12
29#define R8A77970_CLK_CL 13
30#define R8A77970_CLK_ZB3 14
31#define R8A77970_CLK_ZB3D2 15
32#define R8A77970_CLK_DDR 16
33#define R8A77970_CLK_CR 17
34#define R8A77970_CLK_CRD2 18
35#define R8A77970_CLK_SD0H 19
36#define R8A77970_CLK_SD0 20
37#define R8A77970_CLK_RPC 21
38#define R8A77970_CLK_RPCD2 22
39#define R8A77970_CLK_MSO 23
40#define R8A77970_CLK_CANFD 24
41#define R8A77970_CLK_CSI0 25
42#define R8A77970_CLK_FRAY 26
43#define R8A77970_CLK_CP 27
44#define R8A77970_CLK_CPEX 28
45#define R8A77970_CLK_R 29
46#define R8A77970_CLK_OSC 30
47
48#endif /* __DT_BINDINGS_CLOCK_R8A77970_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/s3c2443.h b/include/dt-bindings/clock/s3c2443.h
index 37e66b054d64..f3ba68a25ecb 100644
--- a/include/dt-bindings/clock/s3c2443.h
+++ b/include/dt-bindings/clock/s3c2443.h
@@ -26,6 +26,8 @@
26#define ARMCLK 4 26#define ARMCLK 4
27#define HCLK 5 27#define HCLK 5
28#define PCLK 6 28#define PCLK 6
29#define MPLL 7
30#define EPLL 8
29 31
30/* Special clocks */ 32/* Special clocks */
31#define SCLK_HSSPI0 16 33#define SCLK_HSSPI0 16
diff --git a/include/dt-bindings/clock/sun4i-a10-ccu.h b/include/dt-bindings/clock/sun4i-a10-ccu.h
index c5a53f38d654..e4fa61be5c75 100644
--- a/include/dt-bindings/clock/sun4i-a10-ccu.h
+++ b/include/dt-bindings/clock/sun4i-a10-ccu.h
@@ -43,6 +43,8 @@
43#define _DT_BINDINGS_CLK_SUN4I_A10_H_ 43#define _DT_BINDINGS_CLK_SUN4I_A10_H_
44 44
45#define CLK_HOSC 1 45#define CLK_HOSC 1
46#define CLK_PLL_VIDEO0_2X 9
47#define CLK_PLL_VIDEO1_2X 18
46#define CLK_CPU 20 48#define CLK_CPU 20
47 49
48/* AHB Gates */ 50/* AHB Gates */
diff --git a/include/dt-bindings/clock/sun6i-a31-ccu.h b/include/dt-bindings/clock/sun6i-a31-ccu.h
index 4482530fb6f5..c5d13340184a 100644
--- a/include/dt-bindings/clock/sun6i-a31-ccu.h
+++ b/include/dt-bindings/clock/sun6i-a31-ccu.h
@@ -43,8 +43,12 @@
43#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_ 43#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_
44#define _DT_BINDINGS_CLK_SUN6I_A31_H_ 44#define _DT_BINDINGS_CLK_SUN6I_A31_H_
45 45
46#define CLK_PLL_VIDEO0_2X 7
47
46#define CLK_PLL_PERIPH 10 48#define CLK_PLL_PERIPH 10
47 49
50#define CLK_PLL_VIDEO1_2X 13
51
48#define CLK_CPU 18 52#define CLK_CPU 18
49 53
50#define CLK_AHB1_MIPIDSI 23 54#define CLK_AHB1_MIPIDSI 23
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 5100ec1b5d55..7c925e6211f1 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -682,10 +682,10 @@ struct clk_gpio {
682 682
683extern const struct clk_ops clk_gpio_gate_ops; 683extern const struct clk_ops clk_gpio_gate_ops;
684struct clk *clk_register_gpio_gate(struct device *dev, const char *name, 684struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
685 const char *parent_name, unsigned gpio, bool active_low, 685 const char *parent_name, struct gpio_desc *gpiod,
686 unsigned long flags); 686 unsigned long flags);
687struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name, 687struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name,
688 const char *parent_name, unsigned gpio, bool active_low, 688 const char *parent_name, struct gpio_desc *gpiod,
689 unsigned long flags); 689 unsigned long flags);
690void clk_hw_unregister_gpio_gate(struct clk_hw *hw); 690void clk_hw_unregister_gpio_gate(struct clk_hw *hw);
691 691
@@ -701,11 +701,11 @@ void clk_hw_unregister_gpio_gate(struct clk_hw *hw);
701 701
702extern const struct clk_ops clk_gpio_mux_ops; 702extern const struct clk_ops clk_gpio_mux_ops;
703struct clk *clk_register_gpio_mux(struct device *dev, const char *name, 703struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
704 const char * const *parent_names, u8 num_parents, unsigned gpio, 704 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
705 bool active_low, unsigned long flags); 705 unsigned long flags);
706struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name, 706struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name,
707 const char * const *parent_names, u8 num_parents, unsigned gpio, 707 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
708 bool active_low, unsigned long flags); 708 unsigned long flags);
709void clk_hw_unregister_gpio_mux(struct clk_hw *hw); 709void clk_hw_unregister_gpio_mux(struct clk_hw *hw);
710 710
711/** 711/**
@@ -815,7 +815,12 @@ int of_clk_add_hw_provider(struct device_node *np,
815 struct clk_hw *(*get)(struct of_phandle_args *clkspec, 815 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
816 void *data), 816 void *data),
817 void *data); 817 void *data);
818int devm_of_clk_add_hw_provider(struct device *dev,
819 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
820 void *data),
821 void *data);
818void of_clk_del_provider(struct device_node *np); 822void of_clk_del_provider(struct device_node *np);
823void devm_of_clk_del_provider(struct device *dev);
819struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, 824struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
820 void *data); 825 void *data);
821struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, 826struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
@@ -847,7 +852,15 @@ static inline int of_clk_add_hw_provider(struct device_node *np,
847{ 852{
848 return 0; 853 return 0;
849} 854}
855static inline int devm_of_clk_add_hw_provider(struct device *dev,
856 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
857 void *data),
858 void *data)
859{
860 return 0;
861}
850static inline void of_clk_del_provider(struct device_node *np) {} 862static inline void of_clk_del_provider(struct device_node *np) {}
863static inline void devm_of_clk_del_provider(struct device *dev) {}
851static inline struct clk *of_clk_src_simple_get( 864static inline struct clk *of_clk_src_simple_get(
852 struct of_phandle_args *clkspec, void *data) 865 struct of_phandle_args *clkspec, void *data)
853{ 866{
diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h
index 4eff6e68600d..9f5c6e53f3a5 100644
--- a/include/linux/soc/qcom/smd-rpm.h
+++ b/include/linux/soc/qcom/smd-rpm.h
@@ -27,6 +27,10 @@ struct qcom_smd_rpm;
27#define QCOM_SMD_RPM_SMPB 0x62706d73 27#define QCOM_SMD_RPM_SMPB 0x62706d73
28#define QCOM_SMD_RPM_SPDM 0x63707362 28#define QCOM_SMD_RPM_SPDM 0x63707362
29#define QCOM_SMD_RPM_VSA 0x00617376 29#define QCOM_SMD_RPM_VSA 0x00617376
30#define QCOM_SMD_RPM_MMAXI_CLK 0x69786d6d
31#define QCOM_SMD_RPM_IPA_CLK 0x617069
32#define QCOM_SMD_RPM_CE_CLK 0x6563
33#define QCOM_SMD_RPM_AGGR_CLK 0x72676761
30 34
31int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm, 35int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,
32 int state, 36 int state,
diff --git a/include/soc/at91/atmel-sfr.h b/include/soc/at91/atmel-sfr.h
index 506ea8ffda19..482337af06b8 100644
--- a/include/soc/at91/atmel-sfr.h
+++ b/include/soc/at91/atmel-sfr.h
@@ -17,6 +17,7 @@
17/* 0x08 ~ 0x0c: Reserved */ 17/* 0x08 ~ 0x0c: Reserved */
18#define AT91_SFR_OHCIICR 0x10 /* OHCI INT Configuration Register */ 18#define AT91_SFR_OHCIICR 0x10 /* OHCI INT Configuration Register */
19#define AT91_SFR_OHCIISR 0x14 /* OHCI INT Status Register */ 19#define AT91_SFR_OHCIISR 0x14 /* OHCI INT Status Register */
20#define AT91_SFR_UTMICKTRIM 0x30 /* UTMI Clock Trimming Register */
20#define AT91_SFR_I2SCLKSEL 0x90 /* I2SC Register */ 21#define AT91_SFR_I2SCLKSEL 0x90 /* I2SC Register */
21 22
22/* Field definitions */ 23/* Field definitions */
@@ -28,5 +29,6 @@
28 AT91_OHCIICR_SUSPEND_B | \ 29 AT91_OHCIICR_SUSPEND_B | \
29 AT91_OHCIICR_SUSPEND_C) 30 AT91_OHCIICR_SUSPEND_C)
30 31
32#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0)
31 33
32#endif /* _LINUX_MFD_SYSCON_ATMEL_SFR_H */ 34#endif /* _LINUX_MFD_SYSCON_ATMEL_SFR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-10 19:11:11 -0400