summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--Documentation/devicetree/bindings/ata/marvell.txt2
-rw-r--r--Documentation/devicetree/bindings/ata/sata_rcar.txt18
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi2
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-ata.h56
-rw-r--r--drivers/ata/ahci.c62
-rw-r--r--drivers/ata/ahci_imx.c242
-rw-r--r--drivers/ata/ata_generic.c7
-rw-r--r--drivers/ata/libahci.c4
-rw-r--r--drivers/ata/libata-core.c27
-rw-r--r--drivers/ata/libata-eh.c5
-rw-r--r--drivers/ata/libata-scsi.c18
-rw-r--r--drivers/ata/pata_samsung_cf.c43
-rw-r--r--drivers/ata/sata_highbank.c1
-rw-r--r--drivers/ata/sata_mv.c52
-rw-r--r--drivers/ata/sata_rcar.c118
-rw-r--r--include/linux/libata.h2
16 files changed, 458 insertions, 201 deletions
diff --git a/Documentation/devicetree/bindings/ata/marvell.txt b/Documentation/devicetree/bindings/ata/marvell.txt
index b5cdd20cde9c..1c8351604d38 100644
--- a/Documentation/devicetree/bindings/ata/marvell.txt
+++ b/Documentation/devicetree/bindings/ata/marvell.txt
@@ -1,7 +1,7 @@
1* Marvell Orion SATA 1* Marvell Orion SATA
2 2
3Required Properties: 3Required Properties:
4- compatibility : "marvell,orion-sata" 4- compatibility : "marvell,orion-sata" or "marvell,armada-370-sata"
5- reg : Address range of controller 5- reg : Address range of controller
6- interrupts : Interrupt controller is using 6- interrupts : Interrupt controller is using
7- nr-ports : Number of SATA ports in use. 7- nr-ports : Number of SATA ports in use.
diff --git a/Documentation/devicetree/bindings/ata/sata_rcar.txt b/Documentation/devicetree/bindings/ata/sata_rcar.txt
new file mode 100644
index 000000000000..1e6111333fa8
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/sata_rcar.txt
@@ -0,0 +1,18 @@
1* Renesas R-Car SATA
2
3Required properties:
4- compatible : should contain one of the following:
5 - "renesas,sata-r8a7779" for R-Car H1
6 - "renesas,sata-r8a7790" for R-Car H2
7 - "renesas,sata-r8a7791" for R-Car M2
8- reg : address and length of the SATA registers;
9- interrupts : must consist of one interrupt specifier.
10
11Example:
12
13sata: sata@fc600000 {
14 compatible = "renesas,sata-r8a7779";
15 reg = <0xfc600000 0x2000>;
16 interrupt-parent = <&gic>;
17 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
18};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 7f10f627ae5b..80ffacd128f8 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -152,7 +152,7 @@
152 }; 152 };
153 153
154 sata@a0000 { 154 sata@a0000 {
155 compatible = "marvell,orion-sata"; 155 compatible = "marvell,armada-370-sata";
156 reg = <0xa0000 0x5000>; 156 reg = <0xa0000 0x5000>;
157 interrupts = <55>; 157 interrupts = <55>;
158 clocks = <&gateclk 15>, <&gateclk 30>; 158 clocks = <&gateclk 15>, <&gateclk 30>;
diff --git a/arch/arm/plat-samsung/include/plat/regs-ata.h b/arch/arm/plat-samsung/include/plat/regs-ata.h
deleted file mode 100644
index f5df92fdae26..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-ata.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/* linux/arch/arm/plat-samsung/include/plat/regs-ata.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Samsung CF-ATA register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_PLAT_REGS_ATA_H
14#define __ASM_PLAT_REGS_ATA_H __FILE__
15
16#define S3C_CFATA_REG(x) (x)
17
18#define S3C_CFATA_MUX S3C_CFATA_REG(0x0)
19
20#define S3C_ATA_CTRL S3C_CFATA_REG(0x0)
21#define S3C_ATA_STATUS S3C_CFATA_REG(0x4)
22#define S3C_ATA_CMD S3C_CFATA_REG(0x8)
23#define S3C_ATA_SWRST S3C_CFATA_REG(0xc)
24#define S3C_ATA_IRQ S3C_CFATA_REG(0x10)
25#define S3C_ATA_IRQ_MSK S3C_CFATA_REG(0x14)
26#define S3C_ATA_CFG S3C_CFATA_REG(0x18)
27
28#define S3C_ATA_MDMA_TIME S3C_CFATA_REG(0x28)
29#define S3C_ATA_PIO_TIME S3C_CFATA_REG(0x2c)
30#define S3C_ATA_UDMA_TIME S3C_CFATA_REG(0x30)
31#define S3C_ATA_XFR_NUM S3C_CFATA_REG(0x34)
32#define S3C_ATA_XFR_CNT S3C_CFATA_REG(0x38)
33#define S3C_ATA_TBUF_START S3C_CFATA_REG(0x3c)
34#define S3C_ATA_TBUF_SIZE S3C_CFATA_REG(0x40)
35#define S3C_ATA_SBUF_START S3C_CFATA_REG(0x44)
36#define S3C_ATA_SBUF_SIZE S3C_CFATA_REG(0x48)
37#define S3C_ATA_CADR_TBUF S3C_CFATA_REG(0x4c)
38#define S3C_ATA_CADR_SBUF S3C_CFATA_REG(0x50)
39#define S3C_ATA_PIO_DTR S3C_CFATA_REG(0x54)
40#define S3C_ATA_PIO_FED S3C_CFATA_REG(0x58)
41#define S3C_ATA_PIO_SCR S3C_CFATA_REG(0x5c)
42#define S3C_ATA_PIO_LLR S3C_CFATA_REG(0x60)
43#define S3C_ATA_PIO_LMR S3C_CFATA_REG(0x64)
44#define S3C_ATA_PIO_LHR S3C_CFATA_REG(0x68)
45#define S3C_ATA_PIO_DVR S3C_CFATA_REG(0x6c)
46#define S3C_ATA_PIO_CSD S3C_CFATA_REG(0x70)
47#define S3C_ATA_PIO_DAD S3C_CFATA_REG(0x74)
48#define S3C_ATA_PIO_READY S3C_CFATA_REG(0x78)
49#define S3C_ATA_PIO_RDATA S3C_CFATA_REG(0x7c)
50
51#define S3C_CFATA_MUX_TRUEIDE 0x01
52
53#define S3C_ATA_CFG_SWAP 0x40
54#define S3C_ATA_CFG_IORDYEN 0x02
55
56#endif /* __ASM_PLAT_REGS_ATA_H */
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index e3a92a6da39a..74911c2cb1dd 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -83,6 +83,8 @@ enum board_ids {
83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); 83static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, 84static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline); 85 unsigned long deadline);
86static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
87static bool is_mcp89_apple(struct pci_dev *pdev);
86static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, 88static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline); 89 unsigned long deadline);
88#ifdef CONFIG_PM 90#ifdef CONFIG_PM
@@ -664,6 +666,10 @@ static int ahci_pci_device_resume(struct pci_dev *pdev)
664 if (rc) 666 if (rc)
665 return rc; 667 return rc;
666 668
669 /* Apple BIOS helpfully mangles the registers on resume */
670 if (is_mcp89_apple(pdev))
671 ahci_mcp89_apple_enable(pdev);
672
667 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { 673 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
668 rc = ahci_pci_reset_controller(host); 674 rc = ahci_pci_reset_controller(host);
669 if (rc) 675 if (rc)
@@ -780,6 +786,48 @@ static void ahci_p5wdh_workaround(struct ata_host *host)
780 } 786 }
781} 787}
782 788
789/*
790 * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
791 * booting in BIOS compatibility mode. We restore the registers but not ID.
792 */
793static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
794{
795 u32 val;
796
797 printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
798
799 pci_read_config_dword(pdev, 0xf8, &val);
800 val |= 1 << 0x1b;
801 /* the following changes the device ID, but appears not to affect function */
802 /* val = (val & ~0xf0000000) | 0x80000000; */
803 pci_write_config_dword(pdev, 0xf8, val);
804
805 pci_read_config_dword(pdev, 0x54c, &val);
806 val |= 1 << 0xc;
807 pci_write_config_dword(pdev, 0x54c, val);
808
809 pci_read_config_dword(pdev, 0x4a4, &val);
810 val &= 0xff;
811 val |= 0x01060100;
812 pci_write_config_dword(pdev, 0x4a4, val);
813
814 pci_read_config_dword(pdev, 0x54c, &val);
815 val &= ~(1 << 0xc);
816 pci_write_config_dword(pdev, 0x54c, val);
817
818 pci_read_config_dword(pdev, 0xf8, &val);
819 val &= ~(1 << 0x1b);
820 pci_write_config_dword(pdev, 0xf8, val);
821}
822
823static bool is_mcp89_apple(struct pci_dev *pdev)
824{
825 return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
826 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
827 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
828 pdev->subsystem_device == 0xcb89;
829}
830
783/* only some SB600 ahci controllers can do 64bit DMA */ 831/* only some SB600 ahci controllers can do 64bit DMA */
784static bool ahci_sb600_enable_64bit(struct pci_dev *pdev) 832static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
785{ 833{
@@ -1100,7 +1148,7 @@ static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1100{} 1148{}
1101#endif 1149#endif
1102 1150
1103int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv) 1151static int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1104{ 1152{
1105 int rc; 1153 int rc;
1106 unsigned int maxvec; 1154 unsigned int maxvec;
@@ -1212,15 +1260,9 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1212 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable) 1260 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1213 return -ENODEV; 1261 return -ENODEV;
1214 1262
1215 /* 1263 /* Apple BIOS on MCP89 prevents us using AHCI */
1216 * For some reason, MCP89 on MacBook 7,1 doesn't work with 1264 if (is_mcp89_apple(pdev))
1217 * ahci, use ata_generic instead. 1265 ahci_mcp89_apple_enable(pdev);
1218 */
1219 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1220 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1221 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1222 pdev->subsystem_device == 0xcb89)
1223 return -ENODEV;
1224 1266
1225 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode. 1267 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1226 * At the moment, we can only use the AHCI mode. Let the users know 1268 * At the moment, we can only use the AHCI mode. Let the users know
diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c
index 3e23e9941dad..dd4d6f74d7bd 100644
--- a/drivers/ata/ahci_imx.c
+++ b/drivers/ata/ahci_imx.c
@@ -34,10 +34,21 @@ enum {
34 HOST_TIMER1MS = 0xe0, /* Timer 1-ms */ 34 HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
35}; 35};
36 36
37enum ahci_imx_type {
38 AHCI_IMX53,
39 AHCI_IMX6Q,
40};
41
37struct imx_ahci_priv { 42struct imx_ahci_priv {
38 struct platform_device *ahci_pdev; 43 struct platform_device *ahci_pdev;
44 enum ahci_imx_type type;
45
46 /* i.MX53 clock */
47 struct clk *sata_gate_clk;
48 /* Common clock */
39 struct clk *sata_ref_clk; 49 struct clk *sata_ref_clk;
40 struct clk *ahb_clk; 50 struct clk *ahb_clk;
51
41 struct regmap *gpr; 52 struct regmap *gpr;
42 bool no_device; 53 bool no_device;
43 bool first_time; 54 bool first_time;
@@ -47,6 +58,59 @@ static int ahci_imx_hotplug;
47module_param_named(hotplug, ahci_imx_hotplug, int, 0644); 58module_param_named(hotplug, ahci_imx_hotplug, int, 0644);
48MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)"); 59MODULE_PARM_DESC(hotplug, "AHCI IMX hot-plug support (0=Don't support, 1=support)");
49 60
61static int imx_sata_clock_enable(struct device *dev)
62{
63 struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
64 int ret;
65
66 if (imxpriv->type == AHCI_IMX53) {
67 ret = clk_prepare_enable(imxpriv->sata_gate_clk);
68 if (ret < 0) {
69 dev_err(dev, "prepare-enable sata_gate clock err:%d\n",
70 ret);
71 return ret;
72 }
73 }
74
75 ret = clk_prepare_enable(imxpriv->sata_ref_clk);
76 if (ret < 0) {
77 dev_err(dev, "prepare-enable sata_ref clock err:%d\n",
78 ret);
79 goto clk_err;
80 }
81
82 if (imxpriv->type == AHCI_IMX6Q) {
83 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
84 IMX6Q_GPR13_SATA_MPLL_CLK_EN,
85 IMX6Q_GPR13_SATA_MPLL_CLK_EN);
86 }
87
88 usleep_range(1000, 2000);
89
90 return 0;
91
92clk_err:
93 if (imxpriv->type == AHCI_IMX53)
94 clk_disable_unprepare(imxpriv->sata_gate_clk);
95 return ret;
96}
97
98static void imx_sata_clock_disable(struct device *dev)
99{
100 struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
101
102 if (imxpriv->type == AHCI_IMX6Q) {
103 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
104 IMX6Q_GPR13_SATA_MPLL_CLK_EN,
105 !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
106 }
107
108 clk_disable_unprepare(imxpriv->sata_ref_clk);
109
110 if (imxpriv->type == AHCI_IMX53)
111 clk_disable_unprepare(imxpriv->sata_gate_clk);
112}
113
50static void ahci_imx_error_handler(struct ata_port *ap) 114static void ahci_imx_error_handler(struct ata_port *ap)
51{ 115{
52 u32 reg_val; 116 u32 reg_val;
@@ -72,16 +136,29 @@ static void ahci_imx_error_handler(struct ata_port *ap)
72 */ 136 */
73 reg_val = readl(mmio + PORT_PHY_CTL); 137 reg_val = readl(mmio + PORT_PHY_CTL);
74 writel(reg_val | PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL); 138 writel(reg_val | PORT_PHY_CTL_PDDQ_LOC, mmio + PORT_PHY_CTL);
75 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, 139 imx_sata_clock_disable(ap->dev);
76 IMX6Q_GPR13_SATA_MPLL_CLK_EN,
77 !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
78 clk_disable_unprepare(imxpriv->sata_ref_clk);
79 imxpriv->no_device = true; 140 imxpriv->no_device = true;
80} 141}
81 142
143static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
144 unsigned long deadline)
145{
146 struct ata_port *ap = link->ap;
147 struct imx_ahci_priv *imxpriv = dev_get_drvdata(ap->dev->parent);
148 int ret = -EIO;
149
150 if (imxpriv->type == AHCI_IMX53)
151 ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
152 else if (imxpriv->type == AHCI_IMX6Q)
153 ret = ahci_ops.softreset(link, class, deadline);
154
155 return ret;
156}
157
82static struct ata_port_operations ahci_imx_ops = { 158static struct ata_port_operations ahci_imx_ops = {
83 .inherits = &ahci_platform_ops, 159 .inherits = &ahci_platform_ops,
84 .error_handler = ahci_imx_error_handler, 160 .error_handler = ahci_imx_error_handler,
161 .softreset = ahci_imx_softreset,
85}; 162};
86 163
87static const struct ata_port_info ahci_imx_port_info = { 164static const struct ata_port_info ahci_imx_port_info = {
@@ -91,52 +168,15 @@ static const struct ata_port_info ahci_imx_port_info = {
91 .port_ops = &ahci_imx_ops, 168 .port_ops = &ahci_imx_ops,
92}; 169};
93 170
94static int imx6q_sata_init(struct device *dev, void __iomem *mmio) 171static int imx_sata_init(struct device *dev, void __iomem *mmio)
95{ 172{
96 int ret = 0; 173 int ret = 0;
97 unsigned int reg_val; 174 unsigned int reg_val;
98 struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent); 175 struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
99 176
100 imxpriv->gpr = 177 ret = imx_sata_clock_enable(dev);
101 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 178 if (ret < 0)
102 if (IS_ERR(imxpriv->gpr)) {
103 dev_err(dev, "failed to find fsl,imx6q-iomux-gpr regmap\n");
104 return PTR_ERR(imxpriv->gpr);
105 }
106
107 ret = clk_prepare_enable(imxpriv->sata_ref_clk);
108 if (ret < 0) {
109 dev_err(dev, "prepare-enable sata_ref clock err:%d\n", ret);
110 return ret; 179 return ret;
111 }
112
113 /*
114 * set PHY Paremeters, two steps to configure the GPR13,
115 * one write for rest of parameters, mask of first write
116 * is 0x07ffffff, and the other one write for setting
117 * the mpll_clk_en.
118 */
119 regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK
120 | IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK
121 | IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK
122 | IMX6Q_GPR13_SATA_SPD_MODE_MASK
123 | IMX6Q_GPR13_SATA_MPLL_SS_EN
124 | IMX6Q_GPR13_SATA_TX_ATTEN_MASK
125 | IMX6Q_GPR13_SATA_TX_BOOST_MASK
126 | IMX6Q_GPR13_SATA_TX_LVL_MASK
127 | IMX6Q_GPR13_SATA_MPLL_CLK_EN
128 | IMX6Q_GPR13_SATA_TX_EDGE_RATE
129 , IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB
130 | IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M
131 | IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F
132 | IMX6Q_GPR13_SATA_SPD_MODE_3P0G
133 | IMX6Q_GPR13_SATA_MPLL_SS_EN
134 | IMX6Q_GPR13_SATA_TX_ATTEN_9_16
135 | IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB
136 | IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
137 regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
138 IMX6Q_GPR13_SATA_MPLL_CLK_EN);
139 usleep_range(100, 200);
140 180
141 /* 181 /*
142 * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL, 182 * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
@@ -162,13 +202,9 @@ static int imx6q_sata_init(struct device *dev, void __iomem *mmio)
162 return 0; 202 return 0;
163} 203}
164 204
165static void imx6q_sata_exit(struct device *dev) 205static void imx_sata_exit(struct device *dev)
166{ 206{
167 struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent); 207 imx_sata_clock_disable(dev);
168
169 regmap_update_bits(imxpriv->gpr, 0x34, IMX6Q_GPR13_SATA_MPLL_CLK_EN,
170 !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
171 clk_disable_unprepare(imxpriv->sata_ref_clk);
172} 208}
173 209
174static int imx_ahci_suspend(struct device *dev) 210static int imx_ahci_suspend(struct device *dev)
@@ -179,12 +215,8 @@ static int imx_ahci_suspend(struct device *dev)
179 * If no_device is set, The CLKs had been gated off in the 215 * If no_device is set, The CLKs had been gated off in the
180 * initialization so don't do it again here. 216 * initialization so don't do it again here.
181 */ 217 */
182 if (!imxpriv->no_device) { 218 if (!imxpriv->no_device)
183 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, 219 imx_sata_clock_disable(dev);
184 IMX6Q_GPR13_SATA_MPLL_CLK_EN,
185 !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
186 clk_disable_unprepare(imxpriv->sata_ref_clk);
187 }
188 220
189 return 0; 221 return 0;
190} 222}
@@ -192,34 +224,26 @@ static int imx_ahci_suspend(struct device *dev)
192static int imx_ahci_resume(struct device *dev) 224static int imx_ahci_resume(struct device *dev)
193{ 225{
194 struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent); 226 struct imx_ahci_priv *imxpriv = dev_get_drvdata(dev->parent);
195 int ret; 227 int ret = 0;
196
197 if (!imxpriv->no_device) {
198 ret = clk_prepare_enable(imxpriv->sata_ref_clk);
199 if (ret < 0) {
200 dev_err(dev, "pre-enable sata_ref clock err:%d\n", ret);
201 return ret;
202 }
203 228
204 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, 229 if (!imxpriv->no_device)
205 IMX6Q_GPR13_SATA_MPLL_CLK_EN, 230 ret = imx_sata_clock_enable(dev);
206 IMX6Q_GPR13_SATA_MPLL_CLK_EN);
207 usleep_range(1000, 2000);
208 }
209 231
210 return 0; 232 return ret;
211} 233}
212 234
213static struct ahci_platform_data imx6q_sata_pdata = { 235static struct ahci_platform_data imx_sata_pdata = {
214 .init = imx6q_sata_init, 236 .init = imx_sata_init,
215 .exit = imx6q_sata_exit, 237 .exit = imx_sata_exit,
216 .ata_port_info = &ahci_imx_port_info, 238 .ata_port_info = &ahci_imx_port_info,
217 .suspend = imx_ahci_suspend, 239 .suspend = imx_ahci_suspend,
218 .resume = imx_ahci_resume, 240 .resume = imx_ahci_resume,
241
219}; 242};
220 243
221static const struct of_device_id imx_ahci_of_match[] = { 244static const struct of_device_id imx_ahci_of_match[] = {
222 { .compatible = "fsl,imx6q-ahci", .data = &imx6q_sata_pdata}, 245 { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
246 { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
223 {}, 247 {},
224}; 248};
225MODULE_DEVICE_TABLE(of, imx_ahci_of_match); 249MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
@@ -229,12 +253,20 @@ static int imx_ahci_probe(struct platform_device *pdev)
229 struct device *dev = &pdev->dev; 253 struct device *dev = &pdev->dev;
230 struct resource *mem, *irq, res[2]; 254 struct resource *mem, *irq, res[2];
231 const struct of_device_id *of_id; 255 const struct of_device_id *of_id;
256 enum ahci_imx_type type;
232 const struct ahci_platform_data *pdata = NULL; 257 const struct ahci_platform_data *pdata = NULL;
233 struct imx_ahci_priv *imxpriv; 258 struct imx_ahci_priv *imxpriv;
234 struct device *ahci_dev; 259 struct device *ahci_dev;
235 struct platform_device *ahci_pdev; 260 struct platform_device *ahci_pdev;
236 int ret; 261 int ret;
237 262
263 of_id = of_match_device(imx_ahci_of_match, dev);
264 if (!of_id)
265 return -EINVAL;
266
267 type = (enum ahci_imx_type)of_id->data;
268 pdata = &imx_sata_pdata;
269
238 imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL); 270 imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
239 if (!imxpriv) { 271 if (!imxpriv) {
240 dev_err(dev, "can't alloc ahci_host_priv\n"); 272 dev_err(dev, "can't alloc ahci_host_priv\n");
@@ -250,6 +282,8 @@ static int imx_ahci_probe(struct platform_device *pdev)
250 282
251 imxpriv->no_device = false; 283 imxpriv->no_device = false;
252 imxpriv->first_time = true; 284 imxpriv->first_time = true;
285 imxpriv->type = type;
286
253 imxpriv->ahb_clk = devm_clk_get(dev, "ahb"); 287 imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
254 if (IS_ERR(imxpriv->ahb_clk)) { 288 if (IS_ERR(imxpriv->ahb_clk)) {
255 dev_err(dev, "can't get ahb clock.\n"); 289 dev_err(dev, "can't get ahb clock.\n");
@@ -257,6 +291,15 @@ static int imx_ahci_probe(struct platform_device *pdev)
257 goto err_out; 291 goto err_out;
258 } 292 }
259 293
294 if (type == AHCI_IMX53) {
295 imxpriv->sata_gate_clk = devm_clk_get(dev, "sata_gate");
296 if (IS_ERR(imxpriv->sata_gate_clk)) {
297 dev_err(dev, "can't get sata_gate clock.\n");
298 ret = PTR_ERR(imxpriv->sata_gate_clk);
299 goto err_out;
300 }
301 }
302
260 imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref"); 303 imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
261 if (IS_ERR(imxpriv->sata_ref_clk)) { 304 if (IS_ERR(imxpriv->sata_ref_clk)) {
262 dev_err(dev, "can't get sata_ref clock.\n"); 305 dev_err(dev, "can't get sata_ref clock.\n");
@@ -267,14 +310,6 @@ static int imx_ahci_probe(struct platform_device *pdev)
267 imxpriv->ahci_pdev = ahci_pdev; 310 imxpriv->ahci_pdev = ahci_pdev;
268 platform_set_drvdata(pdev, imxpriv); 311 platform_set_drvdata(pdev, imxpriv);
269 312
270 of_id = of_match_device(imx_ahci_of_match, dev);
271 if (of_id) {
272 pdata = of_id->data;
273 } else {
274 ret = -EINVAL;
275 goto err_out;
276 }
277
278 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 313 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
279 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 314 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
280 if (!mem || !irq) { 315 if (!mem || !irq) {
@@ -290,6 +325,43 @@ static int imx_ahci_probe(struct platform_device *pdev)
290 ahci_dev->dma_mask = &ahci_dev->coherent_dma_mask; 325 ahci_dev->dma_mask = &ahci_dev->coherent_dma_mask;
291 ahci_dev->of_node = dev->of_node; 326 ahci_dev->of_node = dev->of_node;
292 327
328 if (type == AHCI_IMX6Q) {
329 imxpriv->gpr = syscon_regmap_lookup_by_compatible(
330 "fsl,imx6q-iomuxc-gpr");
331 if (IS_ERR(imxpriv->gpr)) {
332 dev_err(dev,
333 "failed to find fsl,imx6q-iomux-gpr regmap\n");
334 ret = PTR_ERR(imxpriv->gpr);
335 goto err_out;
336 }
337
338 /*
339 * Set PHY Paremeters, two steps to configure the GPR13,
340 * one write for rest of parameters, mask of first write
341 * is 0x07fffffe, and the other one write for setting
342 * the mpll_clk_en happens in imx_sata_clock_enable().
343 */
344 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
345 IMX6Q_GPR13_SATA_RX_EQ_VAL_MASK |
346 IMX6Q_GPR13_SATA_RX_LOS_LVL_MASK |
347 IMX6Q_GPR13_SATA_RX_DPLL_MODE_MASK |
348 IMX6Q_GPR13_SATA_SPD_MODE_MASK |
349 IMX6Q_GPR13_SATA_MPLL_SS_EN |
350 IMX6Q_GPR13_SATA_TX_ATTEN_MASK |
351 IMX6Q_GPR13_SATA_TX_BOOST_MASK |
352 IMX6Q_GPR13_SATA_TX_LVL_MASK |
353 IMX6Q_GPR13_SATA_MPLL_CLK_EN |
354 IMX6Q_GPR13_SATA_TX_EDGE_RATE,
355 IMX6Q_GPR13_SATA_RX_EQ_VAL_3_0_DB |
356 IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M |
357 IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
358 IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
359 IMX6Q_GPR13_SATA_MPLL_SS_EN |
360 IMX6Q_GPR13_SATA_TX_ATTEN_9_16 |
361 IMX6Q_GPR13_SATA_TX_BOOST_3_33_DB |
362 IMX6Q_GPR13_SATA_TX_LVL_1_025_V);
363 }
364
293 ret = platform_device_add_resources(ahci_pdev, res, 2); 365 ret = platform_device_add_resources(ahci_pdev, res, 2);
294 if (ret) 366 if (ret)
295 goto err_out; 367 goto err_out;
diff --git a/drivers/ata/ata_generic.c b/drivers/ata/ata_generic.c
index f8f38a08abc5..7d196656adb5 100644
--- a/drivers/ata/ata_generic.c
+++ b/drivers/ata/ata_generic.c
@@ -221,13 +221,6 @@ static struct pci_device_id ata_generic[] = {
221 { PCI_DEVICE(PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C558), }, 221 { PCI_DEVICE(PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C558), },
222 { PCI_DEVICE(PCI_VENDOR_ID_CENATEK,PCI_DEVICE_ID_CENATEK_IDE), 222 { PCI_DEVICE(PCI_VENDOR_ID_CENATEK,PCI_DEVICE_ID_CENATEK_IDE),
223 .driver_data = ATA_GEN_FORCE_DMA }, 223 .driver_data = ATA_GEN_FORCE_DMA },
224 /*
225 * For some reason, MCP89 on MacBook 7,1 doesn't work with
226 * ahci, use ata_generic instead.
227 */
228 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA,
229 PCI_VENDOR_ID_APPLE, 0xcb89,
230 .driver_data = ATA_GEN_FORCE_DMA },
231#if !defined(CONFIG_PATA_TOSHIBA) && !defined(CONFIG_PATA_TOSHIBA_MODULE) 224#if !defined(CONFIG_PATA_TOSHIBA) && !defined(CONFIG_PATA_TOSHIBA_MODULE)
232 { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_1), }, 225 { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_1), },
233 { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_2), }, 226 { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_2), },
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
index c482f8cadd7a..36605abe5a67 100644
--- a/drivers/ata/libahci.c
+++ b/drivers/ata/libahci.c
@@ -1764,7 +1764,7 @@ static void ahci_handle_port_interrupt(struct ata_port *ap,
1764 } 1764 }
1765} 1765}
1766 1766
1767void ahci_port_intr(struct ata_port *ap) 1767static void ahci_port_intr(struct ata_port *ap)
1768{ 1768{
1769 void __iomem *port_mmio = ahci_port_base(ap); 1769 void __iomem *port_mmio = ahci_port_base(ap);
1770 u32 status; 1770 u32 status;
@@ -1797,7 +1797,7 @@ irqreturn_t ahci_thread_fn(int irq, void *dev_instance)
1797} 1797}
1798EXPORT_SYMBOL_GPL(ahci_thread_fn); 1798EXPORT_SYMBOL_GPL(ahci_thread_fn);
1799 1799
1800void ahci_hw_port_interrupt(struct ata_port *ap) 1800static void ahci_hw_port_interrupt(struct ata_port *ap)
1801{ 1801{
1802 void __iomem *port_mmio = ahci_port_base(ap); 1802 void __iomem *port_mmio = ahci_port_base(ap);
1803 struct ahci_port_priv *pp = ap->private_data; 1803 struct ahci_port_priv *pp = ap->private_data;
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 1393a5890ed5..1a3dbd1b196e 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -2222,6 +2222,16 @@ int ata_dev_configure(struct ata_device *dev)
2222 if (rc) 2222 if (rc)
2223 return rc; 2223 return rc;
2224 2224
2225 /* some WD SATA-1 drives have issues with LPM, turn on NOLPM for them */
2226 if ((dev->horkage & ATA_HORKAGE_WD_BROKEN_LPM) &&
2227 (id[ATA_ID_SATA_CAPABILITY] & 0xe) == 0x2)
2228 dev->horkage |= ATA_HORKAGE_NOLPM;
2229
2230 if (dev->horkage & ATA_HORKAGE_NOLPM) {
2231 ata_dev_warn(dev, "LPM support broken, forcing max_power\n");
2232 dev->link->ap->target_lpm_policy = ATA_LPM_MAX_POWER;
2233 }
2234
2225 /* let ACPI work its magic */ 2235 /* let ACPI work its magic */
2226 rc = ata_acpi_on_devcfg(dev); 2236 rc = ata_acpi_on_devcfg(dev);
2227 if (rc) 2237 if (rc)
@@ -4216,6 +4226,23 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
4216 { "Micron_M500*", NULL, ATA_HORKAGE_NO_NCQ_TRIM, }, 4226 { "Micron_M500*", NULL, ATA_HORKAGE_NO_NCQ_TRIM, },
4217 { "Crucial_CT???M500SSD1", NULL, ATA_HORKAGE_NO_NCQ_TRIM, }, 4227 { "Crucial_CT???M500SSD1", NULL, ATA_HORKAGE_NO_NCQ_TRIM, },
4218 4228
4229 /*
4230 * Some WD SATA-I drives spin up and down erratically when the link
4231 * is put into the slumber mode. We don't have full list of the
4232 * affected devices. Disable LPM if the device matches one of the
4233 * known prefixes and is SATA-1. As a side effect LPM partial is
4234 * lost too.
4235 *
4236 * https://bugzilla.kernel.org/show_bug.cgi?id=57211
4237 */
4238 { "WDC WD800JD-*", NULL, ATA_HORKAGE_WD_BROKEN_LPM },
4239 { "WDC WD1200JD-*", NULL, ATA_HORKAGE_WD_BROKEN_LPM },
4240 { "WDC WD1600JD-*", NULL, ATA_HORKAGE_WD_BROKEN_LPM },
4241 { "WDC WD2000JD-*", NULL, ATA_HORKAGE_WD_BROKEN_LPM },
4242 { "WDC WD2500JD-*", NULL, ATA_HORKAGE_WD_BROKEN_LPM },
4243 { "WDC WD3000JD-*", NULL, ATA_HORKAGE_WD_BROKEN_LPM },
4244 { "WDC WD3200JD-*", NULL, ATA_HORKAGE_WD_BROKEN_LPM },
4245
4219 /* End Marker */ 4246 /* End Marker */
4220 { } 4247 { }
4221}; 4248};
diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c
index 92d7797223be..6d8757008318 100644
--- a/drivers/ata/libata-eh.c
+++ b/drivers/ata/libata-eh.c
@@ -2402,7 +2402,7 @@ static void ata_eh_link_report(struct ata_link *link)
2402 struct ata_port *ap = link->ap; 2402 struct ata_port *ap = link->ap;
2403 struct ata_eh_context *ehc = &link->eh_context; 2403 struct ata_eh_context *ehc = &link->eh_context;
2404 const char *frozen, *desc; 2404 const char *frozen, *desc;
2405 char tries_buf[6]; 2405 char tries_buf[6] = "";
2406 int tag, nr_failed = 0; 2406 int tag, nr_failed = 0;
2407 2407
2408 if (ehc->i.flags & ATA_EHI_QUIET) 2408 if (ehc->i.flags & ATA_EHI_QUIET)
@@ -2433,9 +2433,8 @@ static void ata_eh_link_report(struct ata_link *link)
2433 if (ap->pflags & ATA_PFLAG_FROZEN) 2433 if (ap->pflags & ATA_PFLAG_FROZEN)
2434 frozen = " frozen"; 2434 frozen = " frozen";
2435 2435
2436 memset(tries_buf, 0, sizeof(tries_buf));
2437 if (ap->eh_tries < ATA_EH_MAX_TRIES) 2436 if (ap->eh_tries < ATA_EH_MAX_TRIES)
2438 snprintf(tries_buf, sizeof(tries_buf) - 1, " t%d", 2437 snprintf(tries_buf, sizeof(tries_buf), " t%d",
2439 ap->eh_tries); 2438 ap->eh_tries);
2440 2439
2441 if (ehc->i.dev) { 2440 if (ehc->i.dev) {
diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c
index 377eb889f555..ef8567de6a75 100644
--- a/drivers/ata/libata-scsi.c
+++ b/drivers/ata/libata-scsi.c
@@ -111,12 +111,14 @@ static const char *ata_lpm_policy_names[] = {
111 [ATA_LPM_MIN_POWER] = "min_power", 111 [ATA_LPM_MIN_POWER] = "min_power",
112}; 112};
113 113
114static ssize_t ata_scsi_lpm_store(struct device *dev, 114static ssize_t ata_scsi_lpm_store(struct device *device,
115 struct device_attribute *attr, 115 struct device_attribute *attr,
116 const char *buf, size_t count) 116 const char *buf, size_t count)
117{ 117{
118 struct Scsi_Host *shost = class_to_shost(dev); 118 struct Scsi_Host *shost = class_to_shost(device);
119 struct ata_port *ap = ata_shost_to_port(shost); 119 struct ata_port *ap = ata_shost_to_port(shost);
120 struct ata_link *link;
121 struct ata_device *dev;
120 enum ata_lpm_policy policy; 122 enum ata_lpm_policy policy;
121 unsigned long flags; 123 unsigned long flags;
122 124
@@ -132,10 +134,20 @@ static ssize_t ata_scsi_lpm_store(struct device *dev,
132 return -EINVAL; 134 return -EINVAL;
133 135
134 spin_lock_irqsave(ap->lock, flags); 136 spin_lock_irqsave(ap->lock, flags);
137
138 ata_for_each_link(link, ap, EDGE) {
139 ata_for_each_dev(dev, &ap->link, ENABLED) {
140 if (dev->horkage & ATA_HORKAGE_NOLPM) {
141 count = -EOPNOTSUPP;
142 goto out_unlock;
143 }
144 }
145 }
146
135 ap->target_lpm_policy = policy; 147 ap->target_lpm_policy = policy;
136 ata_port_schedule_eh(ap); 148 ata_port_schedule_eh(ap);
149out_unlock:
137 spin_unlock_irqrestore(ap->lock, flags); 150 spin_unlock_irqrestore(ap->lock, flags);
138
139 return count; 151 return count;
140} 152}
141 153
diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c
index 898e544a7ae8..a79566d05666 100644
--- a/drivers/ata/pata_samsung_cf.c
+++ b/drivers/ata/pata_samsung_cf.c
@@ -24,11 +24,34 @@
24#include <linux/slab.h> 24#include <linux/slab.h>
25 25
26#include <linux/platform_data/ata-samsung_cf.h> 26#include <linux/platform_data/ata-samsung_cf.h>
27#include <plat/regs-ata.h>
28 27
29#define DRV_NAME "pata_samsung_cf" 28#define DRV_NAME "pata_samsung_cf"
30#define DRV_VERSION "0.1" 29#define DRV_VERSION "0.1"
31 30
31#define S3C_CFATA_REG(x) (x)
32#define S3C_CFATA_MUX S3C_CFATA_REG(0x0)
33#define S3C_ATA_CTRL S3C_CFATA_REG(0x0)
34#define S3C_ATA_CMD S3C_CFATA_REG(0x8)
35#define S3C_ATA_IRQ S3C_CFATA_REG(0x10)
36#define S3C_ATA_IRQ_MSK S3C_CFATA_REG(0x14)
37#define S3C_ATA_CFG S3C_CFATA_REG(0x18)
38
39#define S3C_ATA_PIO_TIME S3C_CFATA_REG(0x2c)
40#define S3C_ATA_PIO_DTR S3C_CFATA_REG(0x54)
41#define S3C_ATA_PIO_FED S3C_CFATA_REG(0x58)
42#define S3C_ATA_PIO_SCR S3C_CFATA_REG(0x5c)
43#define S3C_ATA_PIO_LLR S3C_CFATA_REG(0x60)
44#define S3C_ATA_PIO_LMR S3C_CFATA_REG(0x64)
45#define S3C_ATA_PIO_LHR S3C_CFATA_REG(0x68)
46#define S3C_ATA_PIO_DVR S3C_CFATA_REG(0x6c)
47#define S3C_ATA_PIO_CSD S3C_CFATA_REG(0x70)
48#define S3C_ATA_PIO_DAD S3C_CFATA_REG(0x74)
49#define S3C_ATA_PIO_RDATA S3C_CFATA_REG(0x7c)
50
51#define S3C_CFATA_MUX_TRUEIDE 0x01
52#define S3C_ATA_CFG_SWAP 0x40
53#define S3C_ATA_CFG_IORDYEN 0x02
54
32enum s3c_cpu_type { 55enum s3c_cpu_type {
33 TYPE_S3C64XX, 56 TYPE_S3C64XX,
34 TYPE_S5PC100, 57 TYPE_S5PC100,
@@ -495,22 +518,10 @@ static int __init pata_s3c_probe(struct platform_device *pdev)
495 info->irq = platform_get_irq(pdev, 0); 518 info->irq = platform_get_irq(pdev, 0);
496 519
497 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 520 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
498 if (res == NULL) {
499 dev_err(dev, "failed to get mem resource\n");
500 return -EINVAL;
501 }
502
503 if (!devm_request_mem_region(dev, res->start,
504 resource_size(res), DRV_NAME)) {
505 dev_err(dev, "error requesting register region\n");
506 return -EBUSY;
507 }
508 521
509 info->ide_addr = devm_ioremap(dev, res->start, resource_size(res)); 522 info->ide_addr = devm_ioremap_resource(dev, res);
510 if (!info->ide_addr) { 523 if (IS_ERR(info->ide_addr))
511 dev_err(dev, "failed to map IO base address\n"); 524 return PTR_ERR(info->ide_addr);
512 return -ENOMEM;
513 }
514 525
515 info->clk = devm_clk_get(&pdev->dev, "cfcon"); 526 info->clk = devm_clk_get(&pdev->dev, "cfcon");
516 if (IS_ERR(info->clk)) { 527 if (IS_ERR(info->clk)) {
diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
index ea3b3dc10f33..870b11eadc6d 100644
--- a/drivers/ata/sata_highbank.c
+++ b/drivers/ata/sata_highbank.c
@@ -29,7 +29,6 @@
29#include <linux/of_address.h> 29#include <linux/of_address.h>
30#include <linux/platform_device.h> 30#include <linux/platform_device.h>
31#include <linux/libata.h> 31#include <linux/libata.h>
32#include <linux/ahci_platform.h>
33#include <linux/interrupt.h> 32#include <linux/interrupt.h>
34#include <linux/delay.h> 33#include <linux/delay.h>
35#include <linux/export.h> 34#include <linux/export.h>
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c
index 56be31819897..20a7517bd339 100644
--- a/drivers/ata/sata_mv.c
+++ b/drivers/ata/sata_mv.c
@@ -60,6 +60,7 @@
60#include <linux/dma-mapping.h> 60#include <linux/dma-mapping.h>
61#include <linux/device.h> 61#include <linux/device.h>
62#include <linux/clk.h> 62#include <linux/clk.h>
63#include <linux/phy/phy.h>
63#include <linux/platform_device.h> 64#include <linux/platform_device.h>
64#include <linux/ata_platform.h> 65#include <linux/ata_platform.h>
65#include <linux/mbus.h> 66#include <linux/mbus.h>
@@ -304,6 +305,7 @@ enum {
304 MV5_LTMODE = 0x30, 305 MV5_LTMODE = 0x30,
305 MV5_PHY_CTL = 0x0C, 306 MV5_PHY_CTL = 0x0C,
306 SATA_IFCFG = 0x050, 307 SATA_IFCFG = 0x050,
308 LP_PHY_CTL = 0x058,
307 309
308 MV_M2_PREAMP_MASK = 0x7e0, 310 MV_M2_PREAMP_MASK = 0x7e0,
309 311
@@ -431,6 +433,7 @@ enum {
431 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ 433 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
432 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */ 434 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
433 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */ 435 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
436 MV_HP_FIX_LP_PHY_CTL = (1 << 13), /* fix speed in LP_PHY_CTL ? */
434 437
435 /* Port private flags (pp_flags) */ 438 /* Port private flags (pp_flags) */
436 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ 439 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
@@ -563,6 +566,12 @@ struct mv_host_priv {
563 struct clk *clk; 566 struct clk *clk;
564 struct clk **port_clks; 567 struct clk **port_clks;
565 /* 568 /*
569 * Some devices have a SATA PHY which can be enabled/disabled
570 * in order to save power. These are optional: if the platform
571 * devices does not have any phy, they won't be used.
572 */
573 struct phy **port_phys;
574 /*
566 * These consistent DMA memory pools give us guaranteed 575 * These consistent DMA memory pools give us guaranteed
567 * alignment for hardware-accessed data structures, 576 * alignment for hardware-accessed data structures,
568 * and less memory waste in accomplishing the alignment. 577 * and less memory waste in accomplishing the alignment.
@@ -1358,6 +1367,7 @@ static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
1358 1367
1359 if (ofs != 0xffffffffU) { 1368 if (ofs != 0xffffffffU) {
1360 void __iomem *addr = mv_ap_base(link->ap) + ofs; 1369 void __iomem *addr = mv_ap_base(link->ap) + ofs;
1370 struct mv_host_priv *hpriv = link->ap->host->private_data;
1361 if (sc_reg_in == SCR_CONTROL) { 1371 if (sc_reg_in == SCR_CONTROL) {
1362 /* 1372 /*
1363 * Workaround for 88SX60x1 FEr SATA#26: 1373 * Workaround for 88SX60x1 FEr SATA#26:
@@ -1374,6 +1384,18 @@ static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
1374 */ 1384 */
1375 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1) 1385 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
1376 val |= 0xf000; 1386 val |= 0xf000;
1387
1388 if (hpriv->hp_flags & MV_HP_FIX_LP_PHY_CTL) {
1389 void __iomem *lp_phy_addr =
1390 mv_ap_base(link->ap) + LP_PHY_CTL;
1391 /*
1392 * Set PHY speed according to SControl speed.
1393 */
1394 if ((val & 0xf0) == 0x10)
1395 writelfl(0x7, lp_phy_addr);
1396 else
1397 writelfl(0x227, lp_phy_addr);
1398 }
1377 } 1399 }
1378 writelfl(val, addr); 1400 writelfl(val, addr);
1379 return 0; 1401 return 0;
@@ -4076,6 +4098,11 @@ static int mv_platform_probe(struct platform_device *pdev)
4076 GFP_KERNEL); 4098 GFP_KERNEL);
4077 if (!hpriv->port_clks) 4099 if (!hpriv->port_clks)
4078 return -ENOMEM; 4100 return -ENOMEM;
4101 hpriv->port_phys = devm_kzalloc(&pdev->dev,
4102 sizeof(struct phy *) * n_ports,
4103 GFP_KERNEL);
4104 if (!hpriv->port_phys)
4105 return -ENOMEM;
4079 host->private_data = hpriv; 4106 host->private_data = hpriv;
4080 hpriv->n_ports = n_ports; 4107 hpriv->n_ports = n_ports;
4081 hpriv->board_idx = chip_soc; 4108 hpriv->board_idx = chip_soc;
@@ -4097,6 +4124,17 @@ static int mv_platform_probe(struct platform_device *pdev)
4097 hpriv->port_clks[port] = clk_get(&pdev->dev, port_number); 4124 hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);
4098 if (!IS_ERR(hpriv->port_clks[port])) 4125 if (!IS_ERR(hpriv->port_clks[port]))
4099 clk_prepare_enable(hpriv->port_clks[port]); 4126 clk_prepare_enable(hpriv->port_clks[port]);
4127
4128 sprintf(port_number, "port%d", port);
4129 hpriv->port_phys[port] = devm_phy_get(&pdev->dev, port_number);
4130 if (IS_ERR(hpriv->port_phys[port])) {
4131 rc = PTR_ERR(hpriv->port_phys[port]);
4132 hpriv->port_phys[port] = NULL;
4133 if ((rc != -EPROBE_DEFER) && (rc != -ENODEV))
4134 dev_warn(&pdev->dev, "error getting phy");
4135 goto err;
4136 } else
4137 phy_power_on(hpriv->port_phys[port]);
4100 } 4138 }
4101 4139
4102 /* 4140 /*
@@ -4110,6 +4148,15 @@ static int mv_platform_probe(struct platform_device *pdev)
4110 if (rc) 4148 if (rc)
4111 goto err; 4149 goto err;
4112 4150
4151 /*
4152 * To allow disk hotplug on Armada 370/XP SoCs, the PHY speed must be
4153 * updated in the LP_PHY_CTL register.
4154 */
4155 if (pdev->dev.of_node &&
4156 of_device_is_compatible(pdev->dev.of_node,
4157 "marvell,armada-370-sata"))
4158 hpriv->hp_flags |= MV_HP_FIX_LP_PHY_CTL;
4159
4113 /* initialize adapter */ 4160 /* initialize adapter */
4114 rc = mv_init_host(host); 4161 rc = mv_init_host(host);
4115 if (rc) 4162 if (rc)
@@ -4132,6 +4179,8 @@ err:
4132 clk_disable_unprepare(hpriv->port_clks[port]); 4179 clk_disable_unprepare(hpriv->port_clks[port]);
4133 clk_put(hpriv->port_clks[port]); 4180 clk_put(hpriv->port_clks[port]);
4134 } 4181 }
4182 if (hpriv->port_phys[port])
4183 phy_power_off(hpriv->port_phys[port]);
4135 } 4184 }
4136 4185
4137 return rc; 4186 return rc;
@@ -4161,6 +4210,8 @@ static int mv_platform_remove(struct platform_device *pdev)
4161 clk_disable_unprepare(hpriv->port_clks[port]); 4210 clk_disable_unprepare(hpriv->port_clks[port]);
4162 clk_put(hpriv->port_clks[port]); 4211 clk_put(hpriv->port_clks[port]);
4163 } 4212 }
4213 if (hpriv->port_phys[port])
4214 phy_power_off(hpriv->port_phys[port]);
4164 } 4215 }
4165 return 0; 4216 return 0;
4166} 4217}
@@ -4209,6 +4260,7 @@ static int mv_platform_resume(struct platform_device *pdev)
4209 4260
4210#ifdef CONFIG_OF 4261#ifdef CONFIG_OF
4211static struct of_device_id mv_sata_dt_ids[] = { 4262static struct of_device_id mv_sata_dt_ids[] = {
4263 { .compatible = "marvell,armada-370-sata", },
4212 { .compatible = "marvell,orion-sata", }, 4264 { .compatible = "marvell,orion-sata", },
4213 {}, 4265 {},
4214}; 4266};
diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c
index 1dae9a9009f7..2b25bd83fc9d 100644
--- a/drivers/ata/sata_rcar.c
+++ b/drivers/ata/sata_rcar.c
@@ -15,6 +15,7 @@
15#include <linux/module.h> 15#include <linux/module.h>
16#include <linux/ata.h> 16#include <linux/ata.h>
17#include <linux/libata.h> 17#include <linux/libata.h>
18#include <linux/of_device.h>
18#include <linux/platform_device.h> 19#include <linux/platform_device.h>
19#include <linux/clk.h> 20#include <linux/clk.h>
20#include <linux/err.h> 21#include <linux/err.h>
@@ -123,12 +124,37 @@
123 124
124#define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFEUL 125#define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFEUL
125 126
127/* Gen2 Physical Layer Control Registers */
128#define RCAR_GEN2_PHY_CTL1_REG 0x1704
129#define RCAR_GEN2_PHY_CTL1 0x34180002
130#define RCAR_GEN2_PHY_CTL1_SS 0xC180 /* Spread Spectrum */
131
132#define RCAR_GEN2_PHY_CTL2_REG 0x170C
133#define RCAR_GEN2_PHY_CTL2 0x00002303
134
135#define RCAR_GEN2_PHY_CTL3_REG 0x171C
136#define RCAR_GEN2_PHY_CTL3 0x000B0194
137
138#define RCAR_GEN2_PHY_CTL4_REG 0x1724
139#define RCAR_GEN2_PHY_CTL4 0x00030994
140
141#define RCAR_GEN2_PHY_CTL5_REG 0x1740
142#define RCAR_GEN2_PHY_CTL5 0x03004001
143#define RCAR_GEN2_PHY_CTL5_DC BIT(1) /* DC connection */
144#define RCAR_GEN2_PHY_CTL5_TR BIT(2) /* Termination Resistor */
145
146enum sata_rcar_type {
147 RCAR_GEN1_SATA,
148 RCAR_GEN2_SATA,
149};
150
126struct sata_rcar_priv { 151struct sata_rcar_priv {
127 void __iomem *base; 152 void __iomem *base;
128 struct clk *clk; 153 struct clk *clk;
154 enum sata_rcar_type type;
129}; 155};
130 156
131static void sata_rcar_phy_initialize(struct sata_rcar_priv *priv) 157static void sata_rcar_gen1_phy_preinit(struct sata_rcar_priv *priv)
132{ 158{
133 void __iomem *base = priv->base; 159 void __iomem *base = priv->base;
134 160
@@ -141,8 +167,8 @@ static void sata_rcar_phy_initialize(struct sata_rcar_priv *priv)
141 iowrite32(0, base + SATAPHYRESET_REG); 167 iowrite32(0, base + SATAPHYRESET_REG);
142} 168}
143 169
144static void sata_rcar_phy_write(struct sata_rcar_priv *priv, u16 reg, u32 val, 170static void sata_rcar_gen1_phy_write(struct sata_rcar_priv *priv, u16 reg,
145 int group) 171 u32 val, int group)
146{ 172{
147 void __iomem *base = priv->base; 173 void __iomem *base = priv->base;
148 int timeout; 174 int timeout;
@@ -170,6 +196,29 @@ static void sata_rcar_phy_write(struct sata_rcar_priv *priv, u16 reg, u32 val,
170 iowrite32(0, base + SATAPHYADDR_REG); 196 iowrite32(0, base + SATAPHYADDR_REG);
171} 197}
172 198
199static void sata_rcar_gen1_phy_init(struct sata_rcar_priv *priv)
200{
201 sata_rcar_gen1_phy_preinit(priv);
202 sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0);
203 sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1);
204 sata_rcar_gen1_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0);
205 sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0);
206 sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1);
207 sata_rcar_gen1_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0);
208}
209
210static void sata_rcar_gen2_phy_init(struct sata_rcar_priv *priv)
211{
212 void __iomem *base = priv->base;
213
214 iowrite32(RCAR_GEN2_PHY_CTL1, base + RCAR_GEN2_PHY_CTL1_REG);
215 iowrite32(RCAR_GEN2_PHY_CTL2, base + RCAR_GEN2_PHY_CTL2_REG);
216 iowrite32(RCAR_GEN2_PHY_CTL3, base + RCAR_GEN2_PHY_CTL3_REG);
217 iowrite32(RCAR_GEN2_PHY_CTL4, base + RCAR_GEN2_PHY_CTL4_REG);
218 iowrite32(RCAR_GEN2_PHY_CTL5 | RCAR_GEN2_PHY_CTL5_DC |
219 RCAR_GEN2_PHY_CTL5_TR, base + RCAR_GEN2_PHY_CTL5_REG);
220}
221
173static void sata_rcar_freeze(struct ata_port *ap) 222static void sata_rcar_freeze(struct ata_port *ap)
174{ 223{
175 struct sata_rcar_priv *priv = ap->host->private_data; 224 struct sata_rcar_priv *priv = ap->host->private_data;
@@ -738,13 +787,17 @@ static void sata_rcar_init_controller(struct ata_host *host)
738 u32 val; 787 u32 val;
739 788
740 /* reset and setup phy */ 789 /* reset and setup phy */
741 sata_rcar_phy_initialize(priv); 790 switch (priv->type) {
742 sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0); 791 case RCAR_GEN1_SATA:
743 sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1); 792 sata_rcar_gen1_phy_init(priv);
744 sata_rcar_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0); 793 break;
745 sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0); 794 case RCAR_GEN2_SATA:
746 sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1); 795 sata_rcar_gen2_phy_init(priv);
747 sata_rcar_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0); 796 break;
797 default:
798 dev_warn(host->dev, "SATA phy is not initialized\n");
799 break;
800 }
748 801
749 /* SATA-IP reset state */ 802 /* SATA-IP reset state */
750 val = ioread32(base + ATAPI_CONTROL1_REG); 803 val = ioread32(base + ATAPI_CONTROL1_REG);
@@ -770,8 +823,40 @@ static void sata_rcar_init_controller(struct ata_host *host)
770 iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG); 823 iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
771} 824}
772 825
826static struct of_device_id sata_rcar_match[] = {
827 {
828 /* Deprecated by "renesas,sata-r8a7779" */
829 .compatible = "renesas,rcar-sata",
830 .data = (void *)RCAR_GEN1_SATA,
831 },
832 {
833 .compatible = "renesas,sata-r8a7779",
834 .data = (void *)RCAR_GEN1_SATA,
835 },
836 {
837 .compatible = "renesas,sata-r8a7790",
838 .data = (void *)RCAR_GEN2_SATA
839 },
840 {
841 .compatible = "renesas,sata-r8a7791",
842 .data = (void *)RCAR_GEN2_SATA
843 },
844 { },
845};
846MODULE_DEVICE_TABLE(of, sata_rcar_match);
847
848static const struct platform_device_id sata_rcar_id_table[] = {
849 { "sata_rcar", RCAR_GEN1_SATA }, /* Deprecated by "sata-r8a7779" */
850 { "sata-r8a7779", RCAR_GEN1_SATA },
851 { "sata-r8a7790", RCAR_GEN2_SATA },
852 { "sata-r8a7791", RCAR_GEN2_SATA },
853 { },
854};
855MODULE_DEVICE_TABLE(platform, sata_rcar_id_table);
856
773static int sata_rcar_probe(struct platform_device *pdev) 857static int sata_rcar_probe(struct platform_device *pdev)
774{ 858{
859 const struct of_device_id *of_id;
775 struct ata_host *host; 860 struct ata_host *host;
776 struct sata_rcar_priv *priv; 861 struct sata_rcar_priv *priv;
777 struct resource *mem; 862 struct resource *mem;
@@ -787,6 +872,12 @@ static int sata_rcar_probe(struct platform_device *pdev)
787 if (!priv) 872 if (!priv)
788 return -ENOMEM; 873 return -ENOMEM;
789 874
875 of_id = of_match_device(sata_rcar_match, &pdev->dev);
876 if (of_id)
877 priv->type = (enum sata_rcar_type)of_id->data;
878 else
879 priv->type = platform_get_device_id(pdev)->driver_data;
880
790 priv->clk = devm_clk_get(&pdev->dev, NULL); 881 priv->clk = devm_clk_get(&pdev->dev, NULL);
791 if (IS_ERR(priv->clk)) { 882 if (IS_ERR(priv->clk)) {
792 dev_err(&pdev->dev, "failed to get access to sata clock\n"); 883 dev_err(&pdev->dev, "failed to get access to sata clock\n");
@@ -892,15 +983,10 @@ static const struct dev_pm_ops sata_rcar_pm_ops = {
892}; 983};
893#endif 984#endif
894 985
895static struct of_device_id sata_rcar_match[] = {
896 { .compatible = "renesas,rcar-sata", },
897 {},
898};
899MODULE_DEVICE_TABLE(of, sata_rcar_match);
900
901static struct platform_driver sata_rcar_driver = { 986static struct platform_driver sata_rcar_driver = {
902 .probe = sata_rcar_probe, 987 .probe = sata_rcar_probe,
903 .remove = sata_rcar_remove, 988 .remove = sata_rcar_remove,
989 .id_table = sata_rcar_id_table,
904 .driver = { 990 .driver = {
905 .name = DRV_NAME, 991 .name = DRV_NAME,
906 .owner = THIS_MODULE, 992 .owner = THIS_MODULE,
diff --git a/include/linux/libata.h b/include/linux/libata.h
index 9b503376738f..bec6dbe939a0 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -419,6 +419,8 @@ enum {
419 ATA_HORKAGE_MAX_SEC_LBA48 = (1 << 17), /* Set max sects to 65535 */ 419 ATA_HORKAGE_MAX_SEC_LBA48 = (1 << 17), /* Set max sects to 65535 */
420 ATA_HORKAGE_ATAPI_DMADIR = (1 << 18), /* device requires dmadir */ 420 ATA_HORKAGE_ATAPI_DMADIR = (1 << 18), /* device requires dmadir */
421 ATA_HORKAGE_NO_NCQ_TRIM = (1 << 19), /* don't use queued TRIM */ 421 ATA_HORKAGE_NO_NCQ_TRIM = (1 << 19), /* don't use queued TRIM */
422 ATA_HORKAGE_NOLPM = (1 << 20), /* don't use LPM */
423 ATA_HORKAGE_WD_BROKEN_LPM = (1 << 21), /* some WDs have broken LPM */
422 424
423 /* DMA mask for user DMA control: User visible values; DO NOT 425 /* DMA mask for user DMA control: User visible values; DO NOT
424 renumber */ 426 renumber */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-12 18:52:37 -0400