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-rw-r--r--Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt42
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt22
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc.txt21
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt7
-rw-r--r--drivers/clk/clk.c6
-rw-r--r--drivers/clk/ingenic/jz4725b-cgu.c2
-rw-r--r--drivers/clk/ingenic/jz4740-cgu.c11
-rw-r--r--drivers/clk/ingenic/jz4770-cgu.c2
-rw-r--r--drivers/clk/ingenic/jz4780-cgu.c2
-rw-r--r--drivers/clk/mediatek/Kconfig56
-rw-r--r--drivers/clk/mediatek/Makefile9
-rw-r--r--drivers/clk/mediatek/clk-gate.c5
-rw-r--r--drivers/clk/mediatek/clk-gate.h3
-rw-r--r--drivers/clk/mediatek/clk-mt6779-aud.c117
-rw-r--r--drivers/clk/mediatek/clk-mt6779-cam.c66
-rw-r--r--drivers/clk/mediatek/clk-mt6779-img.c58
-rw-r--r--drivers/clk/mediatek/clk-mt6779-ipe.c60
-rw-r--r--drivers/clk/mediatek/clk-mt6779-mfg.c55
-rw-r--r--drivers/clk/mediatek/clk-mt6779-mm.c113
-rw-r--r--drivers/clk/mediatek/clk-mt6779-vdec.c67
-rw-r--r--drivers/clk/mediatek/clk-mt6779-venc.c58
-rw-r--r--drivers/clk/mediatek/clk-mt6779.c1315
-rw-r--r--drivers/clk/mediatek/clk-mt8183-mfgcfg.c7
-rw-r--r--drivers/clk/mediatek/clk-mt8183.c44
-rw-r--r--drivers/clk/mediatek/clk-mtk.c16
-rw-r--r--drivers/clk/mediatek/clk-mtk.h8
-rw-r--r--drivers/clk/mediatek/reset.c56
-rw-r--r--drivers/clk/meson/Kconfig11
-rw-r--r--drivers/clk/meson/Makefile2
-rw-r--r--drivers/clk/meson/axg-aoclk.c63
-rw-r--r--drivers/clk/meson/axg-audio.c344
-rw-r--r--drivers/clk/meson/axg-audio.h1
-rw-r--r--drivers/clk/meson/axg.c207
-rw-r--r--drivers/clk/meson/clk-cpu-dyndiv.c73
-rw-r--r--drivers/clk/meson/clk-cpu-dyndiv.h20
-rw-r--r--drivers/clk/meson/clk-input.c49
-rw-r--r--drivers/clk/meson/clk-input.h19
-rw-r--r--drivers/clk/meson/clk-regmap.h12
-rw-r--r--drivers/clk/meson/g12a-aoclk.c81
-rw-r--r--drivers/clk/meson/g12a.c2168
-rw-r--r--drivers/clk/meson/g12a.h25
-rw-r--r--drivers/clk/meson/gxbb-aoclk.c55
-rw-r--r--drivers/clk/meson/gxbb.c657
-rw-r--r--drivers/clk/meson/meson-aoclk.c37
-rw-r--r--drivers/clk/meson/meson-aoclk.h8
-rw-r--r--drivers/clk/meson/meson-eeclk.c10
-rw-r--r--drivers/clk/meson/meson-eeclk.h2
-rw-r--r--drivers/clk/meson/meson8b.c710
-rw-r--r--drivers/clk/mvebu/Kconfig8
-rw-r--r--drivers/clk/mvebu/Makefile2
-rw-r--r--drivers/clk/mvebu/ap-cpu-clk.c356
-rw-r--r--drivers/clk/mvebu/ap806-system-controller.c178
-rw-r--r--drivers/clk/mvebu/armada_ap_cp_helper.c30
-rw-r--r--drivers/clk/mvebu/armada_ap_cp_helper.h11
-rw-r--r--drivers/clk/mvebu/cp110-system-controller.c32
-rw-r--r--drivers/clk/qcom/Kconfig9
-rw-r--r--drivers/clk/qcom/Makefile1
-rw-r--r--drivers/clk/qcom/clk-alpha-pll.c236
-rw-r--r--drivers/clk/qcom/clk-alpha-pll.h7
-rw-r--r--drivers/clk/qcom/clk-rcg2.c2
-rw-r--r--drivers/clk/qcom/clk-rpmh.c38
-rw-r--r--drivers/clk/qcom/common.c20
-rw-r--r--drivers/clk/qcom/common.h2
-rw-r--r--drivers/clk/qcom/gcc-ipq8074.c2
-rw-r--r--drivers/clk/qcom/gcc-msm8998.c4
-rw-r--r--drivers/clk/qcom/gcc-qcs404.c34
-rw-r--r--drivers/clk/qcom/gcc-sdm660.c2
-rw-r--r--drivers/clk/qcom/gcc-sdm845.c4
-rw-r--r--drivers/clk/qcom/gcc-sm8150.c3588
-rw-r--r--drivers/clk/qcom/lpasscc-sdm845.c23
-rw-r--r--drivers/clk/qcom/turingcc-qcs404.c2
-rw-r--r--include/dt-bindings/clock/g12a-clkc.h6
-rw-r--r--include/dt-bindings/clock/mt6779-clk.h436
-rw-r--r--include/dt-bindings/clock/mt8183-clk.h4
-rw-r--r--include/dt-bindings/clock/qcom,gcc-qcs404.h3
-rw-r--r--include/dt-bindings/clock/qcom,gcc-sm8150.h243
-rw-r--r--include/dt-bindings/reset-controller/mt8183-resets.h81
-rw-r--r--include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h38
-rw-r--r--include/linux/clk-provider.h1
92 files changed, 10772 insertions, 1426 deletions
diff --git a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
index 7b8b8eb0191f..26410fbb85be 100644
--- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
@@ -18,17 +18,19 @@ Clocks:
18------- 18-------
19 19
20 20
21The Device Tree node representing the AP806 system controller provides 21The Device Tree node representing the AP806/AP807 system controller
22a number of clocks: 22provides a number of clocks:
23 23
24 - 0: clock of CPU cluster 0 24 - 0: reference clock of CPU cluster 0
25 - 1: clock of CPU cluster 1 25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz 26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL 27 - 3: MSS clock, derived from the fixed PLL
28 28
29Required properties: 29Required properties:
30 30
31 - compatible: must be: "marvell,ap806-clock" 31 - compatible: must be one of:
32 * "marvell,ap806-clock"
33 * "marvell,ap807-clock"
32 - #clock-cells: must be set to 1 34 - #clock-cells: must be set to 1
33 35
34Pinctrl: 36Pinctrl:
@@ -143,3 +145,33 @@ ap_syscon1: system-controller@6f8000 {
143 #thermal-sensor-cells = <1>; 145 #thermal-sensor-cells = <1>;
144 }; 146 };
145}; 147};
148
149Cluster clocks:
150---------------
151
152Device Tree Clock bindings for cluster clock of Marvell
153AP806/AP807. Each cluster contain up to 2 CPUs running at the same
154frequency.
155
156Required properties:
157 - compatible: must be one of:
158 * "marvell,ap806-cpu-clock"
159 * "marvell,ap807-cpu-clock"
160- #clock-cells : should be set to 1.
161
162- clocks : shall be the input parent clock(s) phandle for the clock
163 (one per cluster)
164
165- reg: register range associated with the cluster clocks
166
167ap_syscon1: system-controller@6f8000 {
168 compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd";
169 reg = <0x6f8000 0x1000>;
170
171 cpu_clk: clock-cpu@278 {
172 compatible = "marvell,ap806-cpu-clock";
173 clocks = <&ap_clk 0>, <&ap_clk 1>;
174 #clock-cells = <1>;
175 reg = <0x278 0xa30>;
176 };
177};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
index 161e63a6c254..ff000ccade78 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
@@ -8,6 +8,7 @@ Required Properties:
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-apmixedsys" 9 - "mediatek,mt2701-apmixedsys"
10 - "mediatek,mt2712-apmixedsys", "syscon" 10 - "mediatek,mt2712-apmixedsys", "syscon"
11 - "mediatek,mt6779-apmixedsys", "syscon"
11 - "mediatek,mt6797-apmixedsys" 12 - "mediatek,mt6797-apmixedsys"
12 - "mediatek,mt7622-apmixedsys" 13 - "mediatek,mt7622-apmixedsys"
13 - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys" 14 - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
index 07c9d813465c..e4ca7b703123 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
@@ -7,6 +7,7 @@ Required Properties:
7 7
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-audsys", "syscon" 9 - "mediatek,mt2701-audsys", "syscon"
10 - "mediatek,mt6779-audio", "syscon"
10 - "mediatek,mt7622-audsys", "syscon" 11 - "mediatek,mt7622-audsys", "syscon"
11 - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon" 12 - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
12 - "mediatek,mt8183-audiosys", "syscon" 13 - "mediatek,mt8183-audiosys", "syscon"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
index d8930f64aa98..1f4aaa15a37e 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
@@ -6,6 +6,7 @@ The MediaTek camsys controller provides various clocks to the system.
6Required Properties: 6Required Properties:
7 7
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt6779-camsys", "syscon"
9 - "mediatek,mt8183-camsys", "syscon" 10 - "mediatek,mt8183-camsys", "syscon"
10- #clock-cells: Must be 1 11- #clock-cells: Must be 1
11 12
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
index e3bc4a1e7a6e..2b693e343c56 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
@@ -8,6 +8,7 @@ Required Properties:
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-imgsys", "syscon" 9 - "mediatek,mt2701-imgsys", "syscon"
10 - "mediatek,mt2712-imgsys", "syscon" 10 - "mediatek,mt2712-imgsys", "syscon"
11 - "mediatek,mt6779-imgsys", "syscon"
11 - "mediatek,mt6797-imgsys", "syscon" 12 - "mediatek,mt6797-imgsys", "syscon"
12 - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon" 13 - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
13 - "mediatek,mt8173-imgsys", "syscon" 14 - "mediatek,mt8173-imgsys", "syscon"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
index a90913988d7e..db2f4fd754e7 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
@@ -9,6 +9,7 @@ Required Properties:
9- compatible: Should be one of: 9- compatible: Should be one of:
10 - "mediatek,mt2701-infracfg", "syscon" 10 - "mediatek,mt2701-infracfg", "syscon"
11 - "mediatek,mt2712-infracfg", "syscon" 11 - "mediatek,mt2712-infracfg", "syscon"
12 - "mediatek,mt6779-infracfg_ao", "syscon"
12 - "mediatek,mt6797-infracfg", "syscon" 13 - "mediatek,mt6797-infracfg", "syscon"
13 - "mediatek,mt7622-infracfg", "syscon" 14 - "mediatek,mt7622-infracfg", "syscon"
14 - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" 15 - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt
new file mode 100644
index 000000000000..2ce889b023d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt
@@ -0,0 +1,22 @@
1Mediatek ipesys controller
2============================
3
4The Mediatek ipesys controller provides various clocks to the system.
5
6Required Properties:
7
8- compatible: Should be one of:
9 - "mediatek,mt6779-ipesys", "syscon"
10- #clock-cells: Must be 1
11
12The ipesys controller uses the common clk binding from
13Documentation/devicetree/bindings/clock/clock-bindings.txt
14The available clocks are defined in dt-bindings/clock/mt*-clk.h.
15
16Example:
17
18ipesys: clock-controller@1b000000 {
19 compatible = "mediatek,mt6779-ipesys", "syscon";
20 reg = <0 0x1b000000 0 0x1000>;
21 #clock-cells = <1>;
22};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
index 72787e7dd227..ad5f9d2f6818 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
@@ -7,6 +7,7 @@ Required Properties:
7 7
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2712-mfgcfg", "syscon" 9 - "mediatek,mt2712-mfgcfg", "syscon"
10 - "mediatek,mt6779-mfgcfg", "syscon"
10 - "mediatek,mt8183-mfgcfg", "syscon" 11 - "mediatek,mt8183-mfgcfg", "syscon"
11- #clock-cells: Must be 1 12- #clock-cells: Must be 1
12 13
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
index 545eab717c96..301eefbe1618 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
@@ -8,6 +8,7 @@ Required Properties:
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-mmsys", "syscon" 9 - "mediatek,mt2701-mmsys", "syscon"
10 - "mediatek,mt2712-mmsys", "syscon" 10 - "mediatek,mt2712-mmsys", "syscon"
11 - "mediatek,mt6779-mmsys", "syscon"
11 - "mediatek,mt6797-mmsys", "syscon" 12 - "mediatek,mt6797-mmsys", "syscon"
12 - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon" 13 - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
13 - "mediatek,mt8173-mmsys", "syscon" 14 - "mediatek,mt8173-mmsys", "syscon"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
index 4c7e478117a0..ecf027a9003a 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
@@ -14,6 +14,7 @@ Required Properties:
14 - "mediatek,mt7629-pericfg", "syscon" 14 - "mediatek,mt7629-pericfg", "syscon"
15 - "mediatek,mt8135-pericfg", "syscon" 15 - "mediatek,mt8135-pericfg", "syscon"
16 - "mediatek,mt8173-pericfg", "syscon" 16 - "mediatek,mt8173-pericfg", "syscon"
17 - "mediatek,mt8183-pericfg", "syscon"
17- #clock-cells: Must be 1 18- #clock-cells: Must be 1
18- #reset-cells: Must be 1 19- #reset-cells: Must be 1
19 20
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
index a023b8338960..0293d693ce0c 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
@@ -8,6 +8,7 @@ Required Properties:
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-topckgen" 9 - "mediatek,mt2701-topckgen"
10 - "mediatek,mt2712-topckgen", "syscon" 10 - "mediatek,mt2712-topckgen", "syscon"
11 - "mediatek,mt6779-topckgen", "syscon"
11 - "mediatek,mt6797-topckgen" 12 - "mediatek,mt6797-topckgen"
12 - "mediatek,mt7622-topckgen" 13 - "mediatek,mt7622-topckgen"
13 - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen" 14 - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
index 57176bb8dbb5..7894558b7a1c 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
@@ -8,6 +8,7 @@ Required Properties:
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-vdecsys", "syscon" 9 - "mediatek,mt2701-vdecsys", "syscon"
10 - "mediatek,mt2712-vdecsys", "syscon" 10 - "mediatek,mt2712-vdecsys", "syscon"
11 - "mediatek,mt6779-vdecsys", "syscon"
11 - "mediatek,mt6797-vdecsys", "syscon" 12 - "mediatek,mt6797-vdecsys", "syscon"
12 - "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon" 13 - "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
13 - "mediatek,mt8173-vdecsys", "syscon" 14 - "mediatek,mt8173-vdecsys", "syscon"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
index c9faa6269087..6a6a14e15cd7 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
@@ -7,6 +7,7 @@ Required Properties:
7 7
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2712-vencsys", "syscon" 9 - "mediatek,mt2712-vencsys", "syscon"
10 - "mediatek,mt6779-vencsys", "syscon"
10 - "mediatek,mt6797-vencsys", "syscon" 11 - "mediatek,mt6797-vencsys", "syscon"
11 - "mediatek,mt8173-vencsys", "syscon" 12 - "mediatek,mt8173-vencsys", "syscon"
12 - "mediatek,mt8183-vencsys", "syscon" 13 - "mediatek,mt8183-vencsys", "syscon"
diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
index 0f777749f4f1..b3957d10d241 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
@@ -22,6 +22,7 @@ Required Properties:
22 components. 22 components.
23- resets : phandle of the internal reset line 23- resets : phandle of the internal reset line
24- #clock-cells : should be 1. 24- #clock-cells : should be 1.
25- #reset-cells : should be 1 on the g12a (and following) soc family
25 26
26Each clock is assigned an identifier and client nodes can use this identifier 27Each clock is assigned an identifier and client nodes can use this identifier
27to specify the clock which they consume. All available clocks are defined as 28to specify the clock which they consume. All available clocks are defined as
diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
index 6eaa52092313..7ccecd5c02c1 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
@@ -11,6 +11,7 @@ Required Properties:
11 "amlogic,axg-clkc" for AXG SoC. 11 "amlogic,axg-clkc" for AXG SoC.
12 "amlogic,g12a-clkc" for G12A SoC. 12 "amlogic,g12a-clkc" for G12A SoC.
13 "amlogic,g12b-clkc" for G12B SoC. 13 "amlogic,g12b-clkc" for G12B SoC.
14 "amlogic,sm1-clkc" for SM1 SoC.
14- clocks : list of clock phandle, one for each entry clock-names. 15- clocks : list of clock phandle, one for each entry clock-names.
15- clock-names : should contain the following: 16- clock-names : should contain the following:
16 * "xtal": the platform xtal 17 * "xtal": the platform xtal
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 8661c3cd3ccf..d14362ad4132 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -23,6 +23,7 @@ Required properties :
23 "qcom,gcc-sdm630" 23 "qcom,gcc-sdm630"
24 "qcom,gcc-sdm660" 24 "qcom,gcc-sdm660"
25 "qcom,gcc-sdm845" 25 "qcom,gcc-sdm845"
26 "qcom,gcc-sm8150"
26 27
27- reg : shall contain base register location and length 28- reg : shall contain base register location and length
28- #clock-cells : shall contain 1 29- #clock-cells : shall contain 1
@@ -38,6 +39,13 @@ Documentation/devicetree/bindings/thermal/qcom-tsens.txt
38- protected-clocks : Protected clock specifier list as per common clock 39- protected-clocks : Protected clock specifier list as per common clock
39 binding. 40 binding.
40 41
42For SM8150 only:
43 - clocks: a list of phandles and clock-specifier pairs,
44 one for each entry in clock-names.
45 - clock-names: "bi_tcxo" (required)
46 "sleep_clk" (optional)
47 "aud_ref_clock" (optional)
48
41Example: 49Example:
42 clock-controller@900000 { 50 clock-controller@900000 {
43 compatible = "qcom,gcc-msm8960"; 51 compatible = "qcom,gcc-msm8960";
@@ -71,3 +79,16 @@ Example of GCC with protected-clocks properties:
71 <GCC_LPASS_Q6_AXI_CLK>, 79 <GCC_LPASS_Q6_AXI_CLK>,
72 <GCC_LPASS_SWAY_CLK>; 80 <GCC_LPASS_SWAY_CLK>;
73 }; 81 };
82
83Example of GCC with clocks
84 gcc: clock-controller@100000 {
85 compatible = "qcom,gcc-sm8150";
86 reg = <0x00100000 0x1f0000>;
87 #clock-cells = <1>;
88 #reset-cells = <1>;
89 #power-domain-cells = <1>;
90 clock-names = "bi_tcxo",
91 "sleep_clk";
92 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
93 <&sleep_clk>;
94 };
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt b/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt
index 3c007653da31..365bbde599b1 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt
@@ -6,9 +6,14 @@ some Qualcomm Technologies Inc. SoCs. It accepts clock requests from
6other hardware subsystems via RSC to control clocks. 6other hardware subsystems via RSC to control clocks.
7 7
8Required properties : 8Required properties :
9- compatible : shall contain "qcom,sdm845-rpmh-clk" 9- compatible : must be one of:
10 "qcom,sdm845-rpmh-clk"
11 "qcom,sm8150-rpmh-clk"
10 12
11- #clock-cells : must contain 1 13- #clock-cells : must contain 1
14- clocks: a list of phandles and clock-specifier pairs,
15 one for each entry in clock-names.
16- clock-names: Parent board clock: "xo".
12 17
13Example : 18Example :
14 19
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 7783c25fb407..1b291a6e169b 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -2489,6 +2489,12 @@ runtime_put:
2489 return ret; 2489 return ret;
2490} 2490}
2491 2491
2492int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *parent)
2493{
2494 return clk_core_set_parent_nolock(hw->core, parent->core);
2495}
2496EXPORT_SYMBOL_GPL(clk_hw_set_parent);
2497
2492/** 2498/**
2493 * clk_set_parent - switch the parent of a mux clk 2499 * clk_set_parent - switch the parent of a mux clk
2494 * @clk: the mux clk whose input we are switching 2500 * @clk: the mux clk whose input we are switching
diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c
index 2642d36d1e2c..a3b4635f6278 100644
--- a/drivers/clk/ingenic/jz4725b-cgu.c
+++ b/drivers/clk/ingenic/jz4725b-cgu.c
@@ -257,4 +257,4 @@ static void __init jz4725b_cgu_init(struct device_node *np)
257 257
258 ingenic_cgu_register_syscore_ops(cgu); 258 ingenic_cgu_register_syscore_ops(cgu);
259} 259}
260CLK_OF_DECLARE(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init); 260CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init);
diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index 4c0a20949c2c..978f32dd424a 100644
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -53,6 +53,10 @@ static const u8 jz4740_cgu_cpccr_div_table[] = {
53 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 53 1, 2, 3, 4, 6, 8, 12, 16, 24, 32,
54}; 54};
55 55
56static const u8 jz4740_cgu_pll_half_div_table[] = {
57 2, 1,
58};
59
56static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { 60static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
57 61
58 /* External clocks */ 62 /* External clocks */
@@ -86,7 +90,10 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
86 [JZ4740_CLK_PLL_HALF] = { 90 [JZ4740_CLK_PLL_HALF] = {
87 "pll half", CGU_CLK_DIV, 91 "pll half", CGU_CLK_DIV,
88 .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, 92 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
89 .div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1 }, 93 .div = {
94 CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
95 jz4740_cgu_pll_half_div_table,
96 },
90 }, 97 },
91 98
92 [JZ4740_CLK_CCLK] = { 99 [JZ4740_CLK_CCLK] = {
@@ -241,4 +248,4 @@ static void __init jz4740_cgu_init(struct device_node *np)
241 248
242 ingenic_cgu_register_syscore_ops(cgu); 249 ingenic_cgu_register_syscore_ops(cgu);
243} 250}
244CLK_OF_DECLARE(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init); 251CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);
diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c
index eebc1bea3841..956dd653a43d 100644
--- a/drivers/clk/ingenic/jz4770-cgu.c
+++ b/drivers/clk/ingenic/jz4770-cgu.c
@@ -443,4 +443,4 @@ static void __init jz4770_cgu_init(struct device_node *np)
443} 443}
444 444
445/* We only probe via devicetree, no need for a platform driver */ 445/* We only probe via devicetree, no need for a platform driver */
446CLK_OF_DECLARE(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init); 446CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init);
diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c
index 8c67f89df25e..ea905ff72bf0 100644
--- a/drivers/clk/ingenic/jz4780-cgu.c
+++ b/drivers/clk/ingenic/jz4780-cgu.c
@@ -725,4 +725,4 @@ static void __init jz4780_cgu_init(struct device_node *np)
725 725
726 ingenic_cgu_register_syscore_ops(cgu); 726 ingenic_cgu_register_syscore_ops(cgu);
727} 727}
728CLK_OF_DECLARE(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init); 728CLK_OF_DECLARE_DRIVER(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init);
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index ce3d9b300bab..7efc3617bbd5 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -117,6 +117,62 @@ config COMMON_CLK_MT2712_VENCSYS
117 ---help--- 117 ---help---
118 This driver supports MediaTek MT2712 vencsys clocks. 118 This driver supports MediaTek MT2712 vencsys clocks.
119 119
120config COMMON_CLK_MT6779
121 bool "Clock driver for MediaTek MT6779"
122 depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
123 select COMMON_CLK_MEDIATEK
124 default ARCH_MEDIATEK && ARM64
125 help
126 This driver supports MediaTek MT6779 basic clocks.
127
128config COMMON_CLK_MT6779_MMSYS
129 bool "Clock driver for MediaTek MT6779 mmsys"
130 depends on COMMON_CLK_MT6779
131 help
132 This driver supports MediaTek MT6779 mmsys clocks.
133
134config COMMON_CLK_MT6779_IMGSYS
135 bool "Clock driver for MediaTek MT6779 imgsys"
136 depends on COMMON_CLK_MT6779
137 help
138 This driver supports MediaTek MT6779 imgsys clocks.
139
140config COMMON_CLK_MT6779_IPESYS
141 bool "Clock driver for MediaTek MT6779 ipesys"
142 depends on COMMON_CLK_MT6779
143 help
144 This driver supports MediaTek MT6779 ipesys clocks.
145
146config COMMON_CLK_MT6779_CAMSYS
147 bool "Clock driver for MediaTek MT6779 camsys"
148 depends on COMMON_CLK_MT6779
149 help
150 This driver supports MediaTek MT6779 camsys clocks.
151
152config COMMON_CLK_MT6779_VDECSYS
153 bool "Clock driver for MediaTek MT6779 vdecsys"
154 depends on COMMON_CLK_MT6779
155 help
156 This driver supports MediaTek MT6779 vdecsys clocks.
157
158config COMMON_CLK_MT6779_VENCSYS
159 bool "Clock driver for MediaTek MT6779 vencsys"
160 depends on COMMON_CLK_MT6779
161 help
162 This driver supports MediaTek MT6779 vencsys clocks.
163
164config COMMON_CLK_MT6779_MFGCFG
165 bool "Clock driver for MediaTek MT6779 mfgcfg"
166 depends on COMMON_CLK_MT6779
167 help
168 This driver supports MediaTek MT6779 mfgcfg clocks.
169
170config COMMON_CLK_MT6779_AUDSYS
171 bool "Clock driver for Mediatek MT6779 audsys"
172 depends on COMMON_CLK_MT6779
173 help
174 This driver supports Mediatek MT6779 audsys clocks.
175
120config COMMON_CLK_MT6797 176config COMMON_CLK_MT6797
121 bool "Clock driver for MediaTek MT6797" 177 bool "Clock driver for MediaTek MT6797"
122 depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST 178 depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 672de0099eef..8cdb76a5cd71 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -1,6 +1,15 @@
1# SPDX-License-Identifier: GPL-2.0 1# SPDX-License-Identifier: GPL-2.0
2obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o 2obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
3 3
4obj-$(CONFIG_COMMON_CLK_MT6779) += clk-mt6779.o
5obj-$(CONFIG_COMMON_CLK_MT6779_MMSYS) += clk-mt6779-mm.o
6obj-$(CONFIG_COMMON_CLK_MT6779_IMGSYS) += clk-mt6779-img.o
7obj-$(CONFIG_COMMON_CLK_MT6779_IPESYS) += clk-mt6779-ipe.o
8obj-$(CONFIG_COMMON_CLK_MT6779_CAMSYS) += clk-mt6779-cam.o
9obj-$(CONFIG_COMMON_CLK_MT6779_VDECSYS) += clk-mt6779-vdec.o
10obj-$(CONFIG_COMMON_CLK_MT6779_VENCSYS) += clk-mt6779-venc.o
11obj-$(CONFIG_COMMON_CLK_MT6779_MFGCFG) += clk-mt6779-mfg.o
12obj-$(CONFIG_COMMON_CLK_MT6779_AUDSYS) += clk-mt6779-aud.o
4obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o 13obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
5obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o 14obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
6obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o 15obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index 803bf0ae1fd6..a35cf0b22150 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -150,7 +150,8 @@ struct clk *mtk_clk_register_gate(
150 int sta_ofs, 150 int sta_ofs,
151 u8 bit, 151 u8 bit,
152 const struct clk_ops *ops, 152 const struct clk_ops *ops,
153 unsigned long flags) 153 unsigned long flags,
154 struct device *dev)
154{ 155{
155 struct mtk_clk_gate *cg; 156 struct mtk_clk_gate *cg;
156 struct clk *clk; 157 struct clk *clk;
@@ -174,7 +175,7 @@ struct clk *mtk_clk_register_gate(
174 175
175 cg->hw.init = &init; 176 cg->hw.init = &init;
176 177
177 clk = clk_register(NULL, &cg->hw); 178 clk = clk_register(dev, &cg->hw);
178 if (IS_ERR(clk)) 179 if (IS_ERR(clk))
179 kfree(cg); 180 kfree(cg);
180 181
diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
index e05c73697485..3c3329ec54b7 100644
--- a/drivers/clk/mediatek/clk-gate.h
+++ b/drivers/clk/mediatek/clk-gate.h
@@ -40,7 +40,8 @@ struct clk *mtk_clk_register_gate(
40 int sta_ofs, 40 int sta_ofs,
41 u8 bit, 41 u8 bit,
42 const struct clk_ops *ops, 42 const struct clk_ops *ops,
43 unsigned long flags); 43 unsigned long flags,
44 struct device *dev);
44 45
45#define GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, \ 46#define GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, \
46 _ops, _flags) { \ 47 _ops, _flags) { \
diff --git a/drivers/clk/mediatek/clk-mt6779-aud.c b/drivers/clk/mediatek/clk-mt6779-aud.c
new file mode 100644
index 000000000000..11b209f95e25
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-aud.c
@@ -0,0 +1,117 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/of.h>
9#include <linux/of_address.h>
10#include <linux/of_device.h>
11#include <linux/platform_device.h>
12
13#include "clk-mtk.h"
14#include "clk-gate.h"
15
16#include <dt-bindings/clock/mt6779-clk.h>
17
18static const struct mtk_gate_regs audio0_cg_regs = {
19 .set_ofs = 0x0,
20 .clr_ofs = 0x0,
21 .sta_ofs = 0x0,
22};
23
24static const struct mtk_gate_regs audio1_cg_regs = {
25 .set_ofs = 0x4,
26 .clr_ofs = 0x4,
27 .sta_ofs = 0x4,
28};
29
30#define GATE_AUDIO0(_id, _name, _parent, _shift) \
31 GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
32 &mtk_clk_gate_ops_no_setclr)
33#define GATE_AUDIO1(_id, _name, _parent, _shift) \
34 GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, \
35 &mtk_clk_gate_ops_no_setclr)
36
37static const struct mtk_gate audio_clks[] = {
38 /* AUDIO0 */
39 GATE_AUDIO0(CLK_AUD_AFE, "aud_afe", "audio_sel", 2),
40 GATE_AUDIO0(CLK_AUD_22M, "aud_22m", "aud_eng1_sel", 8),
41 GATE_AUDIO0(CLK_AUD_24M, "aud_24m", "aud_eng2_sel", 9),
42 GATE_AUDIO0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner",
43 "aud_eng2_sel", 18),
44 GATE_AUDIO0(CLK_AUD_APLL_TUNER, "aud_apll_tuner",
45 "aud_eng1_sel", 19),
46 GATE_AUDIO0(CLK_AUD_TDM, "aud_tdm", "aud_eng1_sel", 20),
47 GATE_AUDIO0(CLK_AUD_ADC, "aud_adc", "audio_sel", 24),
48 GATE_AUDIO0(CLK_AUD_DAC, "aud_dac", "audio_sel", 25),
49 GATE_AUDIO0(CLK_AUD_DAC_PREDIS, "aud_dac_predis",
50 "audio_sel", 26),
51 GATE_AUDIO0(CLK_AUD_TML, "aud_tml", "audio_sel", 27),
52 GATE_AUDIO0(CLK_AUD_NLE, "aud_nle", "audio_sel", 28),
53 /* AUDIO1 */
54 GATE_AUDIO1(CLK_AUD_I2S1_BCLK_SW, "aud_i2s1_bclk",
55 "audio_sel", 4),
56 GATE_AUDIO1(CLK_AUD_I2S2_BCLK_SW, "aud_i2s2_bclk",
57 "audio_sel", 5),
58 GATE_AUDIO1(CLK_AUD_I2S3_BCLK_SW, "aud_i2s3_bclk",
59 "audio_sel", 6),
60 GATE_AUDIO1(CLK_AUD_I2S4_BCLK_SW, "aud_i2s4_bclk",
61 "audio_sel", 7),
62 GATE_AUDIO1(CLK_AUD_I2S5_BCLK_SW, "aud_i2s5_bclk",
63 "audio_sel", 8),
64 GATE_AUDIO1(CLK_AUD_CONN_I2S_ASRC, "aud_conn_i2s",
65 "audio_sel", 12),
66 GATE_AUDIO1(CLK_AUD_GENERAL1_ASRC, "aud_general1",
67 "audio_sel", 13),
68 GATE_AUDIO1(CLK_AUD_GENERAL2_ASRC, "aud_general2",
69 "audio_sel", 14),
70 GATE_AUDIO1(CLK_AUD_DAC_HIRES, "aud_dac_hires",
71 "audio_h_sel", 15),
72 GATE_AUDIO1(CLK_AUD_ADC_HIRES, "aud_adc_hires",
73 "audio_h_sel", 16),
74 GATE_AUDIO1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml",
75 "audio_h_sel", 17),
76 GATE_AUDIO1(CLK_AUD_PDN_ADDA6_ADC, "aud_pdn_adda6_adc",
77 "audio_sel", 20),
78 GATE_AUDIO1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires",
79 "audio_h_sel",
80 21),
81 GATE_AUDIO1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "audio_sel",
82 28),
83 GATE_AUDIO1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis",
84 "audio_sel", 29),
85 GATE_AUDIO1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml",
86 "audio_sel", 30),
87 GATE_AUDIO1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires",
88 "audio_h_sel", 31),
89};
90
91static const struct of_device_id of_match_clk_mt6779_aud[] = {
92 { .compatible = "mediatek,mt6779-audio", },
93 {}
94};
95
96static int clk_mt6779_aud_probe(struct platform_device *pdev)
97{
98 struct clk_onecell_data *clk_data;
99 struct device_node *node = pdev->dev.of_node;
100
101 clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
102
103 mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
104 clk_data);
105
106 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
107}
108
109static struct platform_driver clk_mt6779_aud_drv = {
110 .probe = clk_mt6779_aud_probe,
111 .driver = {
112 .name = "clk-mt6779-aud",
113 .of_match_table = of_match_clk_mt6779_aud,
114 },
115};
116
117builtin_platform_driver(clk_mt6779_aud_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-cam.c b/drivers/clk/mediatek/clk-mt6779-cam.c
new file mode 100644
index 000000000000..244d4208b7fb
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-cam.c
@@ -0,0 +1,66 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9#include <dt-bindings/clock/mt6779-clk.h>
10
11#include "clk-mtk.h"
12#include "clk-gate.h"
13
14static const struct mtk_gate_regs cam_cg_regs = {
15 .set_ofs = 0x0004,
16 .clr_ofs = 0x0008,
17 .sta_ofs = 0x0000,
18};
19
20#define GATE_CAM(_id, _name, _parent, _shift) \
21 GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, \
22 &mtk_clk_gate_ops_setclr)
23
24static const struct mtk_gate cam_clks[] = {
25 GATE_CAM(CLK_CAM_LARB10, "camsys_larb10", "cam_sel", 0),
26 GATE_CAM(CLK_CAM_DFP_VAD, "camsys_dfp_vad", "cam_sel", 1),
27 GATE_CAM(CLK_CAM_LARB11, "camsys_larb11", "cam_sel", 2),
28 GATE_CAM(CLK_CAM_LARB9, "camsys_larb9", "cam_sel", 3),
29 GATE_CAM(CLK_CAM_CAM, "camsys_cam", "cam_sel", 6),
30 GATE_CAM(CLK_CAM_CAMTG, "camsys_camtg", "cam_sel", 7),
31 GATE_CAM(CLK_CAM_SENINF, "camsys_seninf", "cam_sel", 8),
32 GATE_CAM(CLK_CAM_CAMSV0, "camsys_camsv0", "cam_sel", 9),
33 GATE_CAM(CLK_CAM_CAMSV1, "camsys_camsv1", "cam_sel", 10),
34 GATE_CAM(CLK_CAM_CAMSV2, "camsys_camsv2", "cam_sel", 11),
35 GATE_CAM(CLK_CAM_CAMSV3, "camsys_camsv3", "cam_sel", 12),
36 GATE_CAM(CLK_CAM_CCU, "camsys_ccu", "cam_sel", 13),
37 GATE_CAM(CLK_CAM_FAKE_ENG, "camsys_fake_eng", "cam_sel", 14),
38};
39
40static const struct of_device_id of_match_clk_mt6779_cam[] = {
41 { .compatible = "mediatek,mt6779-camsys", },
42 {}
43};
44
45static int clk_mt6779_cam_probe(struct platform_device *pdev)
46{
47 struct clk_onecell_data *clk_data;
48 struct device_node *node = pdev->dev.of_node;
49
50 clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
51
52 mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks),
53 clk_data);
54
55 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
56}
57
58static struct platform_driver clk_mt6779_cam_drv = {
59 .probe = clk_mt6779_cam_probe,
60 .driver = {
61 .name = "clk-mt6779-cam",
62 .of_match_table = of_match_clk_mt6779_cam,
63 },
64};
65
66builtin_platform_driver(clk_mt6779_cam_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-img.c b/drivers/clk/mediatek/clk-mt6779-img.c
new file mode 100644
index 000000000000..26292a45c613
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-img.c
@@ -0,0 +1,58 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9#include <dt-bindings/clock/mt6779-clk.h>
10
11#include "clk-mtk.h"
12#include "clk-gate.h"
13
14static const struct mtk_gate_regs img_cg_regs = {
15 .set_ofs = 0x0004,
16 .clr_ofs = 0x0008,
17 .sta_ofs = 0x0000,
18};
19
20#define GATE_IMG(_id, _name, _parent, _shift) \
21 GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, \
22 &mtk_clk_gate_ops_setclr)
23
24static const struct mtk_gate img_clks[] = {
25 GATE_IMG(CLK_IMG_LARB5, "imgsys_larb5", "img_sel", 0),
26 GATE_IMG(CLK_IMG_LARB6, "imgsys_larb6", "img_sel", 1),
27 GATE_IMG(CLK_IMG_DIP, "imgsys_dip", "img_sel", 2),
28 GATE_IMG(CLK_IMG_MFB, "imgsys_mfb", "img_sel", 6),
29 GATE_IMG(CLK_IMG_WPE_A, "imgsys_wpe_a", "img_sel", 7),
30};
31
32static const struct of_device_id of_match_clk_mt6779_img[] = {
33 { .compatible = "mediatek,mt6779-imgsys", },
34 {}
35};
36
37static int clk_mt6779_img_probe(struct platform_device *pdev)
38{
39 struct clk_onecell_data *clk_data;
40 struct device_node *node = pdev->dev.of_node;
41
42 clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
43
44 mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
45 clk_data);
46
47 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
48}
49
50static struct platform_driver clk_mt6779_img_drv = {
51 .probe = clk_mt6779_img_probe,
52 .driver = {
53 .name = "clk-mt6779-img",
54 .of_match_table = of_match_clk_mt6779_img,
55 },
56};
57
58builtin_platform_driver(clk_mt6779_img_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-ipe.c b/drivers/clk/mediatek/clk-mt6779-ipe.c
new file mode 100644
index 000000000000..bb519075639c
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-ipe.c
@@ -0,0 +1,60 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9#include <dt-bindings/clock/mt6779-clk.h>
10
11#include "clk-mtk.h"
12#include "clk-gate.h"
13
14static const struct mtk_gate_regs ipe_cg_regs = {
15 .set_ofs = 0x0004,
16 .clr_ofs = 0x0008,
17 .sta_ofs = 0x0000,
18};
19
20#define GATE_IPE(_id, _name, _parent, _shift) \
21 GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, \
22 &mtk_clk_gate_ops_setclr)
23
24static const struct mtk_gate ipe_clks[] = {
25 GATE_IPE(CLK_IPE_LARB7, "ipe_larb7", "ipe_sel", 0),
26 GATE_IPE(CLK_IPE_LARB8, "ipe_larb8", "ipe_sel", 1),
27 GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "ipe_sel", 2),
28 GATE_IPE(CLK_IPE_FD, "ipe_fd", "ipe_sel", 3),
29 GATE_IPE(CLK_IPE_FE, "ipe_fe", "ipe_sel", 4),
30 GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "ipe_sel", 5),
31 GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "ipe_sel", 6),
32};
33
34static const struct of_device_id of_match_clk_mt6779_ipe[] = {
35 { .compatible = "mediatek,mt6779-ipesys", },
36 {}
37};
38
39static int clk_mt6779_ipe_probe(struct platform_device *pdev)
40{
41 struct clk_onecell_data *clk_data;
42 struct device_node *node = pdev->dev.of_node;
43
44 clk_data = mtk_alloc_clk_data(CLK_IPE_NR_CLK);
45
46 mtk_clk_register_gates(node, ipe_clks, ARRAY_SIZE(ipe_clks),
47 clk_data);
48
49 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
50}
51
52static struct platform_driver clk_mt6779_ipe_drv = {
53 .probe = clk_mt6779_ipe_probe,
54 .driver = {
55 .name = "clk-mt6779-ipe",
56 .of_match_table = of_match_clk_mt6779_ipe,
57 },
58};
59
60builtin_platform_driver(clk_mt6779_ipe_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-mfg.c b/drivers/clk/mediatek/clk-mt6779-mfg.c
new file mode 100644
index 000000000000..c6ee2a89c070
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-mfg.c
@@ -0,0 +1,55 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9
10#include "clk-mtk.h"
11#include "clk-gate.h"
12
13#include <dt-bindings/clock/mt6779-clk.h>
14
15static const struct mtk_gate_regs mfg_cg_regs = {
16 .set_ofs = 0x4,
17 .clr_ofs = 0x8,
18 .sta_ofs = 0x0,
19};
20
21#define GATE_MFG(_id, _name, _parent, _shift) \
22 GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \
23 &mtk_clk_gate_ops_setclr)
24
25static const struct mtk_gate mfg_clks[] = {
26 GATE_MFG(CLK_MFGCFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
27};
28
29static int clk_mt6779_mfg_probe(struct platform_device *pdev)
30{
31 struct clk_onecell_data *clk_data;
32 struct device_node *node = pdev->dev.of_node;
33
34 clk_data = mtk_alloc_clk_data(CLK_MFGCFG_NR_CLK);
35
36 mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
37 clk_data);
38
39 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
40}
41
42static const struct of_device_id of_match_clk_mt6779_mfg[] = {
43 { .compatible = "mediatek,mt6779-mfgcfg", },
44 {}
45};
46
47static struct platform_driver clk_mt6779_mfg_drv = {
48 .probe = clk_mt6779_mfg_probe,
49 .driver = {
50 .name = "clk-mt6779-mfg",
51 .of_match_table = of_match_clk_mt6779_mfg,
52 },
53};
54
55builtin_platform_driver(clk_mt6779_mfg_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-mm.c b/drivers/clk/mediatek/clk-mt6779-mm.c
new file mode 100644
index 000000000000..fb5fbb8e3e41
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-mm.c
@@ -0,0 +1,113 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9#include <dt-bindings/clock/mt6779-clk.h>
10
11#include "clk-mtk.h"
12#include "clk-gate.h"
13
14static const struct mtk_gate_regs mm0_cg_regs = {
15 .set_ofs = 0x0104,
16 .clr_ofs = 0x0108,
17 .sta_ofs = 0x0100,
18};
19
20static const struct mtk_gate_regs mm1_cg_regs = {
21 .set_ofs = 0x0114,
22 .clr_ofs = 0x0118,
23 .sta_ofs = 0x0110,
24};
25
26#define GATE_MM0(_id, _name, _parent, _shift) \
27 GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, \
28 &mtk_clk_gate_ops_setclr)
29#define GATE_MM1(_id, _name, _parent, _shift) \
30 GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \
31 &mtk_clk_gate_ops_setclr)
32
33static const struct mtk_gate mm_clks[] = {
34 /* MM0 */
35 GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
36 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
37 GATE_MM0(CLK_MM_SMI_LARB1, "mm_smi_larb1", "mm_sel", 2),
38 GATE_MM0(CLK_MM_GALS_COMM0, "mm_gals_comm0", "mm_sel", 3),
39 GATE_MM0(CLK_MM_GALS_COMM1, "mm_gals_comm1", "mm_sel", 4),
40 GATE_MM0(CLK_MM_GALS_CCU2MM, "mm_gals_ccu2mm", "mm_sel", 5),
41 GATE_MM0(CLK_MM_GALS_IPU12MM, "mm_gals_ipu12mm", "mm_sel", 6),
42 GATE_MM0(CLK_MM_GALS_IMG2MM, "mm_gals_img2mm", "mm_sel", 7),
43 GATE_MM0(CLK_MM_GALS_CAM2MM, "mm_gals_cam2mm", "mm_sel", 8),
44 GATE_MM0(CLK_MM_GALS_IPU2MM, "mm_gals_ipu2mm", "mm_sel", 9),
45 GATE_MM0(CLK_MM_MDP_DL_TXCK, "mm_mdp_dl_txck", "mm_sel", 10),
46 GATE_MM0(CLK_MM_IPU_DL_TXCK, "mm_ipu_dl_txck", "mm_sel", 11),
47 GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 12),
48 GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 13),
49 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 14),
50 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 15),
51 GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 16),
52 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17),
53 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 18),
54 GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 19),
55 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 20),
56 GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 21),
57 GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 22),
58 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23),
59 GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 24),
60 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25),
61 GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 26),
62 GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_sel", 27),
63 GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_sel", 28),
64 GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_sel", 29),
65 GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_sel", 30),
66 GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
67 /* MM1 */
68 GATE_MM1(CLK_MM_DSI0_MM_CK, "mm_dsi0_mmck", "mm_sel", 0),
69 GATE_MM1(CLK_MM_DSI0_IF_CK, "mm_dsi0_ifck", "mm_sel", 1),
70 GATE_MM1(CLK_MM_DPI_MM_CK, "mm_dpi_mmck", "mm_sel", 2),
71 GATE_MM1(CLK_MM_DPI_IF_CK, "mm_dpi_ifck", "dpi0_sel", 3),
72 GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 4),
73 GATE_MM1(CLK_MM_MDP_DL_RX_CK, "mm_mdp_dl_rxck", "mm_sel", 5),
74 GATE_MM1(CLK_MM_IPU_DL_RX_CK, "mm_ipu_dl_rxck", "mm_sel", 6),
75 GATE_MM1(CLK_MM_26M, "mm_26m", "f_f26m_ck", 7),
76 GATE_MM1(CLK_MM_MM_R2Y, "mm_mmsys_r2y", "mm_sel", 8),
77 GATE_MM1(CLK_MM_DISP_RSZ, "mm_disp_rsz", "mm_sel", 9),
78 GATE_MM1(CLK_MM_MDP_AAL, "mm_mdp_aal", "mm_sel", 10),
79 GATE_MM1(CLK_MM_MDP_HDR, "mm_mdp_hdr", "mm_sel", 11),
80 GATE_MM1(CLK_MM_DBI_MM_CK, "mm_dbi_mmck", "mm_sel", 12),
81 GATE_MM1(CLK_MM_DBI_IF_CK, "mm_dbi_ifck", "dpi0_sel", 13),
82 GATE_MM1(CLK_MM_DISP_POSTMASK0, "mm_disp_pm0", "mm_sel", 14),
83 GATE_MM1(CLK_MM_DISP_HRT_BW, "mm_disp_hrt_bw", "mm_sel", 15),
84 GATE_MM1(CLK_MM_DISP_OVL_FBDC, "mm_disp_ovl_fbdc", "mm_sel", 16),
85};
86
87static const struct of_device_id of_match_clk_mt6779_mm[] = {
88 { .compatible = "mediatek,mt6779-mmsys", },
89 {}
90};
91
92static int clk_mt6779_mm_probe(struct platform_device *pdev)
93{
94 struct clk_onecell_data *clk_data;
95 struct device_node *node = pdev->dev.of_node;
96
97 clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
98
99 mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
100 clk_data);
101
102 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
103}
104
105static struct platform_driver clk_mt6779_mm_drv = {
106 .probe = clk_mt6779_mm_probe,
107 .driver = {
108 .name = "clk-mt6779-mm",
109 .of_match_table = of_match_clk_mt6779_mm,
110 },
111};
112
113builtin_platform_driver(clk_mt6779_mm_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-vdec.c b/drivers/clk/mediatek/clk-mt6779-vdec.c
new file mode 100644
index 000000000000..1900da2586a1
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-vdec.c
@@ -0,0 +1,67 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9
10#include "clk-mtk.h"
11#include "clk-gate.h"
12
13#include <dt-bindings/clock/mt6779-clk.h>
14
15static const struct mtk_gate_regs vdec0_cg_regs = {
16 .set_ofs = 0x0000,
17 .clr_ofs = 0x0004,
18 .sta_ofs = 0x0000,
19};
20
21static const struct mtk_gate_regs vdec1_cg_regs = {
22 .set_ofs = 0x0008,
23 .clr_ofs = 0x000c,
24 .sta_ofs = 0x0008,
25};
26
27#define GATE_VDEC0_I(_id, _name, _parent, _shift) \
28 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
29 &mtk_clk_gate_ops_setclr_inv)
30#define GATE_VDEC1_I(_id, _name, _parent, _shift) \
31 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
32 &mtk_clk_gate_ops_setclr_inv)
33
34static const struct mtk_gate vdec_clks[] = {
35 /* VDEC0 */
36 GATE_VDEC0_I(CLK_VDEC_VDEC, "vdec_cken", "vdec_sel", 0),
37 /* VDEC1 */
38 GATE_VDEC1_I(CLK_VDEC_LARB1, "vdec_larb1_cken", "vdec_sel", 0),
39};
40
41static const struct of_device_id of_match_clk_mt6779_vdec[] = {
42 { .compatible = "mediatek,mt6779-vdecsys", },
43 {}
44};
45
46static int clk_mt6779_vdec_probe(struct platform_device *pdev)
47{
48 struct clk_onecell_data *clk_data;
49 struct device_node *node = pdev->dev.of_node;
50
51 clk_data = mtk_alloc_clk_data(CLK_VDEC_GCON_NR_CLK);
52
53 mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
54 clk_data);
55
56 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
57}
58
59static struct platform_driver clk_mt6779_vdec_drv = {
60 .probe = clk_mt6779_vdec_probe,
61 .driver = {
62 .name = "clk-mt6779-vdec",
63 .of_match_table = of_match_clk_mt6779_vdec,
64 },
65};
66
67builtin_platform_driver(clk_mt6779_vdec_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-venc.c b/drivers/clk/mediatek/clk-mt6779-venc.c
new file mode 100644
index 000000000000..b41d1f859edc
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-venc.c
@@ -0,0 +1,58 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9
10#include "clk-mtk.h"
11#include "clk-gate.h"
12
13#include <dt-bindings/clock/mt6779-clk.h>
14
15static const struct mtk_gate_regs venc_cg_regs = {
16 .set_ofs = 0x0004,
17 .clr_ofs = 0x0008,
18 .sta_ofs = 0x0000,
19};
20
21#define GATE_VENC_I(_id, _name, _parent, _shift) \
22 GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, \
23 &mtk_clk_gate_ops_setclr_inv)
24
25static const struct mtk_gate venc_clks[] = {
26 GATE_VENC_I(CLK_VENC_GCON_LARB, "venc_larb", "venc_sel", 0),
27 GATE_VENC_I(CLK_VENC_GCON_VENC, "venc_venc", "venc_sel", 4),
28 GATE_VENC_I(CLK_VENC_GCON_JPGENC, "venc_jpgenc", "venc_sel", 8),
29 GATE_VENC_I(CLK_VENC_GCON_GALS, "venc_gals", "venc_sel", 28),
30};
31
32static const struct of_device_id of_match_clk_mt6779_venc[] = {
33 { .compatible = "mediatek,mt6779-vencsys", },
34 {}
35};
36
37static int clk_mt6779_venc_probe(struct platform_device *pdev)
38{
39 struct clk_onecell_data *clk_data;
40 struct device_node *node = pdev->dev.of_node;
41
42 clk_data = mtk_alloc_clk_data(CLK_VENC_GCON_NR_CLK);
43
44 mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
45 clk_data);
46
47 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
48}
49
50static struct platform_driver clk_mt6779_venc_drv = {
51 .probe = clk_mt6779_venc_probe,
52 .driver = {
53 .name = "clk-mt6779-venc",
54 .of_match_table = of_match_clk_mt6779_venc,
55 },
56};
57
58builtin_platform_driver(clk_mt6779_venc_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
new file mode 100644
index 000000000000..608a9a6621a3
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779.c
@@ -0,0 +1,1315 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/of.h>
8#include <linux/of_address.h>
9#include <linux/of_device.h>
10#include <linux/platform_device.h>
11
12#include "clk-mtk.h"
13#include "clk-mux.h"
14#include "clk-gate.h"
15
16#include <dt-bindings/clock/mt6779-clk.h>
17
18static DEFINE_SPINLOCK(mt6779_clk_lock);
19
20static const struct mtk_fixed_clk top_fixed_clks[] = {
21 FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000),
22};
23
24static const struct mtk_fixed_factor top_divs[] = {
25 FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2),
26 FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2),
27 FACTOR(CLK_TOP_MAINPLL_CK, "mainpll_ck", "mainpll", 1, 1),
28 FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll_ck", 1, 2),
29 FACTOR(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2),
30 FACTOR(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4),
31 FACTOR(CLK_TOP_MAINPLL_D2_D8, "mainpll_d2_d8", "mainpll_d2", 1, 8),
32 FACTOR(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16),
33 FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
34 FACTOR(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2),
35 FACTOR(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4),
36 FACTOR(CLK_TOP_MAINPLL_D3_D8, "mainpll_d3_d8", "mainpll_d3", 1, 8),
37 FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
38 FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
39 FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
40 FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
41 FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
42 FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
43 FACTOR(CLK_TOP_UNIVPLL_CK, "univpll", "univ2pll", 1, 2),
44 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
45 FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2),
46 FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4),
47 FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 8),
48 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
49 FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2),
50 FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4),
51 FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8),
52 FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 16),
53 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
54 FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
55 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
56 FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
57 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
58 FACTOR(CLK_TOP_UNIVP_192M_CK, "univpll_192m_ck", "univ2pll", 1, 13),
59 FACTOR(CLK_TOP_UNIVP_192M_D2, "univpll_192m_d2", "univpll_192m_ck",
60 1, 2),
61 FACTOR(CLK_TOP_UNIVP_192M_D4, "univpll_192m_d4", "univpll_192m_ck",
62 1, 4),
63 FACTOR(CLK_TOP_UNIVP_192M_D8, "univpll_192m_d8", "univpll_192m_ck",
64 1, 8),
65 FACTOR(CLK_TOP_UNIVP_192M_D16, "univpll_192m_d16", "univpll_192m_ck",
66 1, 16),
67 FACTOR(CLK_TOP_UNIVP_192M_D32, "univpll_192m_d32", "univpll_192m_ck",
68 1, 32),
69 FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
70 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
71 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
72 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
73 FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
74 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
75 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
76 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
77 FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
78 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
79 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
80 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
81 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
82 FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 1),
83 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
84 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
85 FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
86 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
87 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
88 FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
89 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
90 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
91 FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
92 FACTOR(CLK_TOP_ADSPPLL_CK, "adsppll_ck", "adsppll", 1, 1),
93 FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
94 FACTOR(CLK_TOP_ADSPPLL_D5, "adsppll_d5", "adsppll", 1, 5),
95 FACTOR(CLK_TOP_ADSPPLL_D6, "adsppll_d6", "adsppll", 1, 6),
96 FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
97 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
98 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
99 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
100 FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
101 FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 1),
102 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 2),
103 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 4),
104 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 8),
105 FACTOR(CLK_TOP_OSC_D10, "osc_d10", "osc", 1, 10),
106 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 16),
107 FACTOR(CLK_TOP_AD_OSC2_CK, "ad_osc2_ck", "osc2", 1, 1),
108 FACTOR(CLK_TOP_OSC2_D2, "osc2_d2", "osc2", 1, 2),
109 FACTOR(CLK_TOP_OSC2_D3, "osc2_d3", "osc2", 1, 3),
110 FACTOR(CLK_TOP_TVDPLL_MAINPLL_D2_CK, "tvdpll_mainpll_d2_ck",
111 "tvdpll", 1, 1),
112 FACTOR(CLK_TOP_FMEM_466M_CK, "fmem_466m_ck", "fmem", 1, 1),
113};
114
115static const char * const axi_parents[] = {
116 "clk26m",
117 "mainpll_d2_d4",
118 "mainpll_d7",
119 "osc_d4"
120};
121
122static const char * const mm_parents[] = {
123 "clk26m",
124 "tvdpll_mainpll_d2_ck",
125 "mmpll_d7",
126 "mmpll_d5_d2",
127 "mainpll_d2_d2",
128 "mainpll_d3_d2"
129};
130
131static const char * const scp_parents[] = {
132 "clk26m",
133 "univpll_d2_d8",
134 "mainpll_d2_d4",
135 "mainpll_d3",
136 "univpll_d3",
137 "ad_osc2_ck",
138 "osc2_d2",
139 "osc2_d3"
140};
141
142static const char * const img_parents[] = {
143 "clk26m",
144 "mainpll_d2",
145 "mainpll_d2",
146 "univpll_d3",
147 "mainpll_d3",
148 "mmpll_d5_d2",
149 "tvdpll_mainpll_d2_ck",
150 "mainpll_d5"
151};
152
153static const char * const ipe_parents[] = {
154 "clk26m",
155 "mainpll_d2",
156 "mmpll_d7",
157 "univpll_d3",
158 "mainpll_d3",
159 "mmpll_d5_d2",
160 "mainpll_d2_d2",
161 "mainpll_d5"
162};
163
164static const char * const dpe_parents[] = {
165 "clk26m",
166 "mainpll_d2",
167 "mmpll_d7",
168 "univpll_d3",
169 "mainpll_d3",
170 "mmpll_d5_d2",
171 "mainpll_d2_d2",
172 "mainpll_d5"
173};
174
175static const char * const cam_parents[] = {
176 "clk26m",
177 "mainpll_d2",
178 "mmpll_d6",
179 "mainpll_d3",
180 "mmpll_d7",
181 "univpll_d3",
182 "mmpll_d5_d2",
183 "adsppll_d5",
184 "tvdpll_mainpll_d2_ck",
185 "univpll_d3_d2"
186};
187
188static const char * const ccu_parents[] = {
189 "clk26m",
190 "mainpll_d2",
191 "mmpll_d6",
192 "mainpll_d3",
193 "mmpll_d7",
194 "univpll_d3",
195 "mmpll_d5_d2",
196 "mainpll_d2_d2",
197 "adsppll_d5",
198 "univpll_d3_d2"
199};
200
201static const char * const dsp_parents[] = {
202 "clk26m",
203 "univpll_d3_d8",
204 "univpll_d3_d4",
205 "mainpll_d2_d4",
206 "univpll_d3_d2",
207 "mainpll_d2_d2",
208 "univpll_d2_d2",
209 "mainpll_d3",
210 "univpll_d3",
211 "mmpll_d7",
212 "mmpll_d6",
213 "adsppll_d5",
214 "tvdpll_ck",
215 "tvdpll_mainpll_d2_ck",
216 "univpll_d2",
217 "adsppll_d4"
218};
219
220static const char * const dsp1_parents[] = {
221 "clk26m",
222 "univpll_d3_d8",
223 "univpll_d3_d4",
224 "mainpll_d2_d4",
225 "univpll_d3_d2",
226 "mainpll_d2_d2",
227 "univpll_d2_d2",
228 "mainpll_d3",
229 "univpll_d3",
230 "mmpll_d7",
231 "mmpll_d6",
232 "adsppll_d5",
233 "tvdpll_ck",
234 "tvdpll_mainpll_d2_ck",
235 "univpll_d2",
236 "adsppll_d4"
237};
238
239static const char * const dsp2_parents[] = {
240 "clk26m",
241 "univpll_d3_d8",
242 "univpll_d3_d4",
243 "mainpll_d2_d4",
244 "univpll_d3_d2",
245 "mainpll_d2_d2",
246 "univpll_d2_d2",
247 "mainpll_d3",
248 "univpll_d3",
249 "mmpll_d7",
250 "mmpll_d6",
251 "adsppll_d5",
252 "tvdpll_ck",
253 "tvdpll_mainpll_d2_ck",
254 "univpll_d2",
255 "adsppll_d4"
256};
257
258static const char * const dsp3_parents[] = {
259 "clk26m",
260 "univpll_d3_d8",
261 "mainpll_d2_d4",
262 "univpll_d3_d2",
263 "mainpll_d2_d2",
264 "univpll_d2_d2",
265 "mainpll_d3",
266 "univpll_d3",
267 "mmpll_d7",
268 "mmpll_d6",
269 "mainpll_d2",
270 "tvdpll_ck",
271 "tvdpll_mainpll_d2_ck",
272 "univpll_d2",
273 "adsppll_d4",
274 "mmpll_d4"
275};
276
277static const char * const ipu_if_parents[] = {
278 "clk26m",
279 "univpll_d3_d8",
280 "univpll_d3_d4",
281 "mainpll_d2_d4",
282 "univpll_d3_d2",
283 "mainpll_d2_d2",
284 "univpll_d2_d2",
285 "mainpll_d3",
286 "univpll_d3",
287 "mmpll_d7",
288 "mmpll_d6",
289 "adsppll_d5",
290 "tvdpll_ck",
291 "tvdpll_mainpll_d2_ck",
292 "univpll_d2",
293 "adsppll_d4"
294};
295
296static const char * const mfg_parents[] = {
297 "clk26m",
298 "mfgpll_ck",
299 "univpll_d3",
300 "mainpll_d5"
301};
302
303static const char * const f52m_mfg_parents[] = {
304 "clk26m",
305 "univpll_d3_d2",
306 "univpll_d3_d4",
307 "univpll_d3_d8"
308};
309
310static const char * const camtg_parents[] = {
311 "clk26m",
312 "univpll_192m_d8",
313 "univpll_d3_d8",
314 "univpll_192m_d4",
315 "univpll_d3_d16",
316 "csw_f26m_ck_d2",
317 "univpll_192m_d16",
318 "univpll_192m_d32"
319};
320
321static const char * const camtg2_parents[] = {
322 "clk26m",
323 "univpll_192m_d8",
324 "univpll_d3_d8",
325 "univpll_192m_d4",
326 "univpll_d3_d16",
327 "csw_f26m_ck_d2",
328 "univpll_192m_d16",
329 "univpll_192m_d32"
330};
331
332static const char * const camtg3_parents[] = {
333 "clk26m",
334 "univpll_192m_d8",
335 "univpll_d3_d8",
336 "univpll_192m_d4",
337 "univpll_d3_d16",
338 "csw_f26m_ck_d2",
339 "univpll_192m_d16",
340 "univpll_192m_d32"
341};
342
343static const char * const camtg4_parents[] = {
344 "clk26m",
345 "univpll_192m_d8",
346 "univpll_d3_d8",
347 "univpll_192m_d4",
348 "univpll_d3_d16",
349 "csw_f26m_ck_d2",
350 "univpll_192m_d16",
351 "univpll_192m_d32"
352};
353
354static const char * const uart_parents[] = {
355 "clk26m",
356 "univpll_d3_d8"
357};
358
359static const char * const spi_parents[] = {
360 "clk26m",
361 "mainpll_d5_d2",
362 "mainpll_d3_d4",
363 "msdcpll_d4"
364};
365
366static const char * const msdc50_hclk_parents[] = {
367 "clk26m",
368 "mainpll_d2_d2",
369 "mainpll_d3_d2"
370};
371
372static const char * const msdc50_0_parents[] = {
373 "clk26m",
374 "msdcpll_ck",
375 "msdcpll_d2",
376 "univpll_d2_d4",
377 "mainpll_d3_d2",
378 "univpll_d2_d2"
379};
380
381static const char * const msdc30_1_parents[] = {
382 "clk26m",
383 "univpll_d3_d2",
384 "mainpll_d3_d2",
385 "mainpll_d7",
386 "msdcpll_d2"
387};
388
389static const char * const audio_parents[] = {
390 "clk26m",
391 "mainpll_d5_d4",
392 "mainpll_d7_d4",
393 "mainpll_d2_d16"
394};
395
396static const char * const aud_intbus_parents[] = {
397 "clk26m",
398 "mainpll_d2_d4",
399 "mainpll_d7_d2"
400};
401
402static const char * const fpwrap_ulposc_parents[] = {
403 "osc_d10",
404 "clk26m",
405 "osc_d4",
406 "osc_d8",
407 "osc_d16"
408};
409
410static const char * const atb_parents[] = {
411 "clk26m",
412 "mainpll_d2_d2",
413 "mainpll_d5"
414};
415
416static const char * const sspm_parents[] = {
417 "clk26m",
418 "univpll_d2_d4",
419 "mainpll_d2_d2",
420 "univpll_d2_d2",
421 "mainpll_d3"
422};
423
424static const char * const dpi0_parents[] = {
425 "clk26m",
426 "tvdpll_d2",
427 "tvdpll_d4",
428 "tvdpll_d8",
429 "tvdpll_d16"
430};
431
432static const char * const scam_parents[] = {
433 "clk26m",
434 "mainpll_d5_d2"
435};
436
437static const char * const disppwm_parents[] = {
438 "clk26m",
439 "univpll_d3_d4",
440 "osc_d2",
441 "osc_d4",
442 "osc_d16"
443};
444
445static const char * const usb_top_parents[] = {
446 "clk26m",
447 "univpll_d5_d4",
448 "univpll_d3_d4",
449 "univpll_d5_d2"
450};
451
452static const char * const ssusb_top_xhci_parents[] = {
453 "clk26m",
454 "univpll_d5_d4",
455 "univpll_d3_d4",
456 "univpll_d5_d2"
457};
458
459static const char * const spm_parents[] = {
460 "clk26m",
461 "osc_d8",
462 "mainpll_d2_d8"
463};
464
465static const char * const i2c_parents[] = {
466 "clk26m",
467 "mainpll_d2_d8",
468 "univpll_d5_d2"
469};
470
471static const char * const seninf_parents[] = {
472 "clk26m",
473 "univpll_d7",
474 "univpll_d3_d2",
475 "univpll_d2_d2",
476 "mainpll_d3",
477 "mmpll_d4_d2",
478 "mmpll_d7",
479 "mmpll_d6"
480};
481
482static const char * const seninf1_parents[] = {
483 "clk26m",
484 "univpll_d7",
485 "univpll_d3_d2",
486 "univpll_d2_d2",
487 "mainpll_d3",
488 "mmpll_d4_d2",
489 "mmpll_d7",
490 "mmpll_d6"
491};
492
493static const char * const seninf2_parents[] = {
494 "clk26m",
495 "univpll_d7",
496 "univpll_d3_d2",
497 "univpll_d2_d2",
498 "mainpll_d3",
499 "mmpll_d4_d2",
500 "mmpll_d7",
501 "mmpll_d6"
502};
503
504static const char * const dxcc_parents[] = {
505 "clk26m",
506 "mainpll_d2_d2",
507 "mainpll_d2_d4",
508 "mainpll_d2_d8"
509};
510
511static const char * const aud_engen1_parents[] = {
512 "clk26m",
513 "apll1_d2",
514 "apll1_d4",
515 "apll1_d8"
516};
517
518static const char * const aud_engen2_parents[] = {
519 "clk26m",
520 "apll2_d2",
521 "apll2_d4",
522 "apll2_d8"
523};
524
525static const char * const faes_ufsfde_parents[] = {
526 "clk26m",
527 "mainpll_d2",
528 "mainpll_d2_d2",
529 "mainpll_d3",
530 "mainpll_d2_d4",
531 "univpll_d3"
532};
533
534static const char * const fufs_parents[] = {
535 "clk26m",
536 "mainpll_d2_d4",
537 "mainpll_d2_d8",
538 "mainpll_d2_d16"
539};
540
541static const char * const aud_1_parents[] = {
542 "clk26m",
543 "apll1_ck"
544};
545
546static const char * const aud_2_parents[] = {
547 "clk26m",
548 "apll2_ck"
549};
550
551static const char * const adsp_parents[] = {
552 "clk26m",
553 "mainpll_d3",
554 "univpll_d2_d4",
555 "univpll_d2",
556 "mmpll_d4",
557 "adsppll_d4",
558 "adsppll_d6"
559};
560
561static const char * const dpmaif_parents[] = {
562 "clk26m",
563 "univpll_d2_d4",
564 "mainpll_d3",
565 "mainpll_d2_d2",
566 "univpll_d2_d2",
567 "univpll_d3"
568};
569
570static const char * const venc_parents[] = {
571 "clk26m",
572 "mmpll_d7",
573 "mainpll_d3",
574 "univpll_d2_d2",
575 "mainpll_d2_d2",
576 "univpll_d3",
577 "mmpll_d6",
578 "mainpll_d5",
579 "mainpll_d3_d2",
580 "mmpll_d4_d2",
581 "univpll_d2_d4",
582 "mmpll_d5",
583 "univpll_192m_d2"
584
585};
586
587static const char * const vdec_parents[] = {
588 "clk26m",
589 "univpll_d2_d4",
590 "mainpll_d3",
591 "univpll_d2_d2",
592 "mainpll_d2_d2",
593 "univpll_d3",
594 "univpll_d5",
595 "univpll_d5_d2",
596 "mainpll_d2",
597 "univpll_d2",
598 "univpll_192m_d2"
599};
600
601static const char * const camtm_parents[] = {
602 "clk26m",
603 "univpll_d7",
604 "univpll_d3_d2",
605 "univpll_d2_d2"
606};
607
608static const char * const pwm_parents[] = {
609 "clk26m",
610 "univpll_d2_d8"
611};
612
613static const char * const audio_h_parents[] = {
614 "clk26m",
615 "univpll_d7",
616 "apll1_ck",
617 "apll2_ck"
618};
619
620static const char * const camtg5_parents[] = {
621 "clk26m",
622 "univpll_192m_d8",
623 "univpll_d3_d8",
624 "univpll_192m_d4",
625 "univpll_d3_d16",
626 "csw_f26m_ck_d2",
627 "univpll_192m_d16",
628 "univpll_192m_d32"
629};
630
631/*
632 * CRITICAL CLOCK:
633 * axi_sel is the main bus clock of whole SOC.
634 * spm_sel is the clock of the always-on co-processor.
635 * sspm_sel is the clock of the always-on co-processor.
636 */
637static const struct mtk_mux top_muxes[] = {
638 /* CLK_CFG_0 */
639 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "axi_sel", axi_parents,
640 0x20, 0x24, 0x28, 0, 2, 7,
641 0x004, 0, CLK_IS_CRITICAL),
642 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM, "mm_sel", mm_parents,
643 0x20, 0x24, 0x28, 8, 3, 15, 0x004, 1),
644 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP, "scp_sel", scp_parents,
645 0x20, 0x24, 0x28, 16, 3, 23, 0x004, 2),
646 /* CLK_CFG_1 */
647 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "img_sel", img_parents,
648 0x30, 0x34, 0x38, 0, 3, 7, 0x004, 4),
649 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "ipe_sel", ipe_parents,
650 0x30, 0x34, 0x38, 8, 3, 15, 0x004, 5),
651 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE, "dpe_sel", dpe_parents,
652 0x30, 0x34, 0x38, 16, 3, 23, 0x004, 6),
653 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "cam_sel", cam_parents,
654 0x30, 0x34, 0x38, 24, 4, 31, 0x004, 7),
655 /* CLK_CFG_2 */
656 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "ccu_sel", ccu_parents,
657 0x40, 0x44, 0x48, 0, 4, 7, 0x004, 8),
658 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "dsp_sel", dsp_parents,
659 0x40, 0x44, 0x48, 8, 4, 15, 0x004, 9),
660 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "dsp1_sel", dsp1_parents,
661 0x40, 0x44, 0x48, 16, 4, 23, 0x004, 10),
662 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "dsp2_sel", dsp2_parents,
663 0x40, 0x44, 0x48, 24, 4, 31, 0x004, 11),
664 /* CLK_CFG_3 */
665 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "dsp3_sel", dsp3_parents,
666 0x50, 0x54, 0x58, 0, 4, 7, 0x004, 12),
667 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF, "ipu_if_sel", ipu_if_parents,
668 0x50, 0x54, 0x58, 8, 4, 15, 0x004, 13),
669 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "mfg_sel", mfg_parents,
670 0x50, 0x54, 0x58, 16, 2, 23, 0x004, 14),
671 MUX_GATE_CLR_SET_UPD(CLK_TOP_F52M_MFG, "f52m_mfg_sel",
672 f52m_mfg_parents, 0x50, 0x54, 0x58,
673 24, 2, 31, 0x004, 15),
674 /* CLK_CFG_4 */
675 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "camtg_sel", camtg_parents,
676 0x60, 0x64, 0x68, 0, 3, 7, 0x004, 16),
677 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "camtg2_sel", camtg2_parents,
678 0x60, 0x64, 0x68, 8, 3, 15, 0x004, 17),
679 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "camtg3_sel", camtg3_parents,
680 0x60, 0x64, 0x68, 16, 3, 23, 0x004, 18),
681 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "camtg4_sel", camtg4_parents,
682 0x60, 0x64, 0x68, 24, 3, 31, 0x004, 19),
683 /* CLK_CFG_5 */
684 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "uart_sel", uart_parents,
685 0x70, 0x74, 0x78, 0, 1, 7, 0x004, 20),
686 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "spi_sel", spi_parents,
687 0x70, 0x74, 0x78, 8, 2, 15, 0x004, 21),
688 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel",
689 msdc50_hclk_parents, 0x70, 0x74, 0x78,
690 16, 2, 23, 0x004, 22),
691 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "msdc50_0_sel",
692 msdc50_0_parents, 0x70, 0x74, 0x78,
693 24, 3, 31, 0x004, 23),
694 /* CLK_CFG_6 */
695 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "msdc30_1_sel",
696 msdc30_1_parents, 0x80, 0x84, 0x88,
697 0, 3, 7, 0x004, 24),
698 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD, "audio_sel", audio_parents,
699 0x80, 0x84, 0x88, 8, 2, 15, 0x004, 25),
700 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "aud_intbus_sel",
701 aud_intbus_parents, 0x80, 0x84, 0x88,
702 16, 2, 23, 0x004, 26),
703 MUX_GATE_CLR_SET_UPD(CLK_TOP_FPWRAP_ULPOSC, "fpwrap_ulposc_sel",
704 fpwrap_ulposc_parents, 0x80, 0x84, 0x88,
705 24, 3, 31, 0x004, 27),
706 /* CLK_CFG_7 */
707 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "atb_sel", atb_parents,
708 0x90, 0x94, 0x98, 0, 2, 7, 0x004, 28),
709 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "sspm_sel", sspm_parents,
710 0x90, 0x94, 0x98, 8, 3, 15,
711 0x004, 29, CLK_IS_CRITICAL),
712 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0, "dpi0_sel", dpi0_parents,
713 0x90, 0x94, 0x98, 16, 3, 23, 0x004, 30),
714 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM, "scam_sel", scam_parents,
715 0x90, 0x94, 0x98, 24, 1, 31, 0x004, 0),
716 /* CLK_CFG_8 */
717 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM, "disppwm_sel",
718 disppwm_parents, 0xa0, 0xa4, 0xa8,
719 0, 3, 7, 0x008, 1),
720 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "usb_top_sel",
721 usb_top_parents, 0xa0, 0xa4, 0xa8,
722 8, 2, 15, 0x008, 2),
723 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel",
724 ssusb_top_xhci_parents, 0xa0, 0xa4, 0xa8,
725 16, 2, 23, 0x008, 3),
726 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "spm_sel", spm_parents,
727 0xa0, 0xa4, 0xa8, 24, 2, 31,
728 0x008, 4, CLK_IS_CRITICAL),
729 /* CLK_CFG_9 */
730 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "i2c_sel", i2c_parents,
731 0xb0, 0xb4, 0xb8, 0, 2, 7, 0x008, 5),
732 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "seninf_sel", seninf_parents,
733 0xb0, 0xb4, 0xb8, 8, 2, 15, 0x008, 6),
734 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "seninf1_sel",
735 seninf1_parents, 0xb0, 0xb4, 0xb8,
736 16, 2, 23, 0x008, 7),
737 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "seninf2_sel",
738 seninf2_parents, 0xb0, 0xb4, 0xb8,
739 24, 2, 31, 0x008, 8),
740 /* CLK_CFG_10 */
741 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "dxcc_sel", dxcc_parents,
742 0xc0, 0xc4, 0xc8, 0, 2, 7, 0x008, 9),
743 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG1, "aud_eng1_sel",
744 aud_engen1_parents, 0xc0, 0xc4, 0xc8,
745 8, 2, 15, 0x008, 10),
746 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG2, "aud_eng2_sel",
747 aud_engen2_parents, 0xc0, 0xc4, 0xc8,
748 16, 2, 23, 0x008, 11),
749 MUX_GATE_CLR_SET_UPD(CLK_TOP_FAES_UFSFDE, "faes_ufsfde_sel",
750 faes_ufsfde_parents, 0xc0, 0xc4, 0xc8,
751 24, 3, 31,
752 0x008, 12),
753 /* CLK_CFG_11 */
754 MUX_GATE_CLR_SET_UPD(CLK_TOP_FUFS, "fufs_sel", fufs_parents,
755 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x008, 13),
756 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1, "aud_1_sel", aud_1_parents,
757 0xd0, 0xd4, 0xd8, 8, 1, 15, 0x008, 14),
758 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2, "aud_2_sel", aud_2_parents,
759 0xd0, 0xd4, 0xd8, 16, 1, 23, 0x008, 15),
760 MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "adsp_sel", adsp_parents,
761 0xd0, 0xd4, 0xd8, 24, 3, 31, 0x008, 16),
762 /* CLK_CFG_12 */
763 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF, "dpmaif_sel", dpmaif_parents,
764 0xe0, 0xe4, 0xe8, 0, 3, 7, 0x008, 17),
765 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "venc_sel", venc_parents,
766 0xe0, 0xe4, 0xe8, 8, 4, 15, 0x008, 18),
767 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "vdec_sel", vdec_parents,
768 0xe0, 0xe4, 0xe8, 16, 4, 23, 0x008, 19),
769 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "camtm_sel", camtm_parents,
770 0xe0, 0xe4, 0xe8, 24, 2, 31, 0x004, 20),
771 /* CLK_CFG_13 */
772 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "pwm_sel", pwm_parents,
773 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x008, 21),
774 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_H, "audio_h_sel",
775 audio_h_parents, 0xf0, 0xf4, 0xf8,
776 8, 2, 15, 0x008, 22),
777 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "camtg5_sel", camtg5_parents,
778 0xf0, 0xf4, 0xf8, 24, 3, 31, 0x008, 24),
779};
780
781static const char * const i2s0_m_ck_parents[] = {
782 "aud_1_sel",
783 "aud_2_sel"
784};
785
786static const char * const i2s1_m_ck_parents[] = {
787 "aud_1_sel",
788 "aud_2_sel"
789};
790
791static const char * const i2s2_m_ck_parents[] = {
792 "aud_1_sel",
793 "aud_2_sel"
794};
795
796static const char * const i2s3_m_ck_parents[] = {
797 "aud_1_sel",
798 "aud_2_sel"
799};
800
801static const char * const i2s4_m_ck_parents[] = {
802 "aud_1_sel",
803 "aud_2_sel"
804};
805
806static const char * const i2s5_m_ck_parents[] = {
807 "aud_1_sel",
808 "aud_2_sel"
809};
810
811static const struct mtk_composite top_aud_muxes[] = {
812 MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents,
813 0x320, 8, 1),
814 MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents,
815 0x320, 9, 1),
816 MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents,
817 0x320, 10, 1),
818 MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents,
819 0x320, 11, 1),
820 MUX(CLK_TOP_I2S4_M_SEL, "i2s4_m_ck_sel", i2s4_m_ck_parents,
821 0x320, 12, 1),
822 MUX(CLK_TOP_I2S5_M_SEL, "i2s5_m_ck_sel", i2s5_m_ck_parents,
823 0x328, 20, 1),
824};
825
826static struct mtk_composite top_aud_divs[] = {
827 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2s0_m_ck_sel",
828 0x320, 2, 0x324, 8, 0),
829 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "i2s1_m_ck_sel",
830 0x320, 3, 0x324, 8, 8),
831 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "i2s2_m_ck_sel",
832 0x320, 4, 0x324, 8, 16),
833 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "i2s3_m_ck_sel",
834 0x320, 5, 0x324, 8, 24),
835 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "i2s4_m_ck_sel",
836 0x320, 6, 0x328, 8, 0),
837 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4",
838 0x320, 7, 0x328, 8, 8),
839 DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "i2s5_m_ck_sel",
840 0x328, 16, 0x328, 4, 28),
841};
842
843static const struct mtk_gate_regs infra0_cg_regs = {
844 .set_ofs = 0x80,
845 .clr_ofs = 0x84,
846 .sta_ofs = 0x90,
847};
848
849static const struct mtk_gate_regs infra1_cg_regs = {
850 .set_ofs = 0x88,
851 .clr_ofs = 0x8c,
852 .sta_ofs = 0x94,
853};
854
855static const struct mtk_gate_regs infra2_cg_regs = {
856 .set_ofs = 0xa4,
857 .clr_ofs = 0xa8,
858 .sta_ofs = 0xac,
859};
860
861static const struct mtk_gate_regs infra3_cg_regs = {
862 .set_ofs = 0xc0,
863 .clr_ofs = 0xc4,
864 .sta_ofs = 0xc8,
865};
866
867#define GATE_INFRA0(_id, _name, _parent, _shift) \
868 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \
869 &mtk_clk_gate_ops_setclr)
870#define GATE_INFRA1(_id, _name, _parent, _shift) \
871 GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \
872 &mtk_clk_gate_ops_setclr)
873#define GATE_INFRA2(_id, _name, _parent, _shift) \
874 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \
875 &mtk_clk_gate_ops_setclr)
876#define GATE_INFRA3(_id, _name, _parent, _shift) \
877 GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \
878 &mtk_clk_gate_ops_setclr)
879
880static const struct mtk_gate infra_clks[] = {
881 /* INFRA0 */
882 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr",
883 "axi_sel", 0),
884 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap",
885 "axi_sel", 1),
886 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md",
887 "axi_sel", 2),
888 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn",
889 "axi_sel", 3),
890 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp",
891 "axi_sel", 4),
892 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej",
893 "f_f26m_ck", 5),
894 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt",
895 "axi_sel", 6),
896 GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb",
897 "axi_sel", 8),
898 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce",
899 "axi_sel", 9),
900 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm",
901 "axi_sel", 10),
902 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0",
903 "i2c_sel", 11),
904 GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1",
905 "i2c_sel", 12),
906 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2",
907 "i2c_sel", 13),
908 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3",
909 "i2c_sel", 14),
910 GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk",
911 "pwm_sel", 15),
912 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1",
913 "pwm_sel", 16),
914 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2",
915 "pwm_sel", 17),
916 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3",
917 "pwm_sel", 18),
918 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4",
919 "pwm_sel", 19),
920 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
921 "pwm_sel", 21),
922 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
923 "uart_sel", 23),
924 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
925 "uart_sel", 24),
926 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3",
927 "uart_sel", 25),
928 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m",
929 "axi_sel", 27),
930 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc",
931 "axi_sel", 28),
932 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif",
933 "axi_sel", 31),
934 /* INFRA1 */
935 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0",
936 "spi_sel", 1),
937 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0",
938 "msdc50_hclk_sel", 2),
939 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1",
940 "axi_sel", 4),
941 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2",
942 "axi_sel", 5),
943 GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck",
944 "msdc50_0_sel", 6),
945 GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc",
946 "f_f26m_ck", 7),
947 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu",
948 "axi_sel", 8),
949 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng",
950 "axi_sel", 9),
951 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc",
952 "f_f26m_ck", 10),
953 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum",
954 "axi_sel", 11),
955 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap",
956 "axi_sel", 12),
957 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md",
958 "axi_sel", 13),
959 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md",
960 "f_f26m_ck", 14),
961 GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck",
962 "msdc30_1_sel", 16),
963 GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck",
964 "msdc30_2_sel", 17),
965 GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma",
966 "axi_sel", 18),
967 GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu",
968 "axi_sel", 19),
969 GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc",
970 "axi_sel", 20),
971 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap",
972 "axi_sel", 23),
973 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys",
974 "axi_sel", 24),
975 GATE_INFRA1(CLK_INFRA_AUD, "infra_audio",
976 "axi_sel", 25),
977 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md",
978 "axi_sel", 26),
979 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core",
980 "dxcc_sel", 27),
981 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao",
982 "dxcc_sel", 28),
983 GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk",
984 "axi_sel", 30),
985 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
986 "f_f26m_ck", 31),
987 /* INFRA2 */
988 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx",
989 "f_f26m_ck", 0),
990 GATE_INFRA2(CLK_INFRA_USB, "infra_usb",
991 "usb_top_sel", 1),
992 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm",
993 "axi_sel", 2),
994 GATE_INFRA2(CLK_INFRA_AUD_26M_BCLK,
995 "infracfg_ao_audio_26m_bclk", "f_f26m_ck", 4),
996 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1",
997 "spi_sel", 6),
998 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4",
999 "i2c_sel", 7),
1000 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share",
1001 "f_f26m_ck", 8),
1002 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2",
1003 "spi_sel", 9),
1004 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3",
1005 "spi_sel", 10),
1006 GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck",
1007 "fufs_sel", 11),
1008 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick",
1009 "fufs_sel", 12),
1010 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck",
1011 "fufs_sel", 13),
1012 GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk",
1013 "axi_sel", 14),
1014 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist",
1015 "axi_sel", 16),
1016 GATE_INFRA2(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk",
1017 "axi_sel", 17),
1018 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5",
1019 "i2c_sel", 18),
1020 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter",
1021 "i2c_sel", 19),
1022 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm",
1023 "i2c_sel", 20),
1024 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter",
1025 "i2c_sel", 21),
1026 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm",
1027 "i2c_sel", 22),
1028 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter",
1029 "i2c_sel", 23),
1030 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm",
1031 "i2c_sel", 24),
1032 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4",
1033 "spi_sel", 25),
1034 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5",
1035 "spi_sel", 26),
1036 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma",
1037 "axi_sel", 27),
1038 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs",
1039 "fufs_sel", 28),
1040 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde",
1041 "faes_ufsfde_sel", 29),
1042 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick",
1043 "fufs_sel", 30),
1044 GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci",
1045 "ssusb_top_xhci_sel", 31),
1046 /* INFRA3 */
1047 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self",
1048 "msdc50_0_sel", 0),
1049 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self",
1050 "msdc50_0_sel", 1),
1051 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self",
1052 "msdc50_0_sel", 2),
1053 GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self",
1054 "f_f26m_ck", 3),
1055 GATE_INFRA3(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self",
1056 "f_f26m_ck", 4),
1057 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi",
1058 "axi_sel", 5),
1059 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6",
1060 "i2c_sel", 6),
1061 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0",
1062 "msdc50_hclk_sel", 7),
1063 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0",
1064 "msdc50_hclk_sel", 8),
1065 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap",
1066 "axi_sel", 16),
1067 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md",
1068 "axi_sel", 17),
1069 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap",
1070 "axi_sel", 18),
1071 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md",
1072 "axi_sel", 19),
1073 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m",
1074 "f_f26m_ck", 20),
1075 GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk",
1076 "axi_sel", 21),
1077 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7",
1078 "i2c_sel", 22),
1079 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8",
1080 "i2c_sel", 23),
1081 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc",
1082 "msdc50_0_sel", 24),
1083 GATE_INFRA3(CLK_INFRA_DPMAIF_CK, "infra_dpmaif",
1084 "dpmaif_sel", 26),
1085 GATE_INFRA3(CLK_INFRA_FADSP, "infra_fadsp",
1086 "adsp_sel", 27),
1087 GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap",
1088 "axi_sel", 28),
1089 GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md",
1090 "axi_sel", 29),
1091 GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6",
1092 "spi_sel", 30),
1093 GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7",
1094 "spi_sel", 31),
1095};
1096
1097static const struct mtk_gate_regs apmixed_cg_regs = {
1098 .set_ofs = 0x20,
1099 .clr_ofs = 0x20,
1100 .sta_ofs = 0x20,
1101};
1102
1103#define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
1104 GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \
1105 _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
1106
1107#define GATE_APMIXED(_id, _name, _parent, _shift) \
1108 GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
1109
1110/*
1111 * CRITICAL CLOCK:
1112 * apmixed_appll26m is the toppest clock gate of all PLLs.
1113 */
1114static const struct mtk_gate apmixed_clks[] = {
1115 GATE_APMIXED(CLK_APMIXED_SSUSB26M, "apmixed_ssusb26m",
1116 "f_f26m_ck", 4),
1117 GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL26M, "apmixed_appll26m",
1118 "f_f26m_ck", 5, CLK_IS_CRITICAL),
1119 GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m",
1120 "f_f26m_ck", 6),
1121 GATE_APMIXED(CLK_APMIXED_MDPLLGP26M, "apmixed_mdpll26m",
1122 "f_f26m_ck", 7),
1123 GATE_APMIXED(CLK_APMIXED_MM_F26M, "apmixed_mmsys26m",
1124 "f_f26m_ck", 8),
1125 GATE_APMIXED(CLK_APMIXED_UFS26M, "apmixed_ufs26m",
1126 "f_f26m_ck", 9),
1127 GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m",
1128 "f_f26m_ck", 11),
1129 GATE_APMIXED(CLK_APMIXED_MEMPLL26M, "apmixed_mempll26m",
1130 "f_f26m_ck", 13),
1131 GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
1132 "f_f26m_ck", 14),
1133 GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m",
1134 "f_f26m_ck", 16),
1135 GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m",
1136 "f_f26m_ck", 17),
1137};
1138
1139#define MT6779_PLL_FMAX (3800UL * MHZ)
1140#define MT6779_PLL_FMIN (1500UL * MHZ)
1141
1142#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1143 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
1144 _pd_shift, _tuner_reg, _tuner_en_reg, \
1145 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1146 _pcw_chg_reg, _div_table) { \
1147 .id = _id, \
1148 .name = _name, \
1149 .reg = _reg, \
1150 .pwr_reg = _pwr_reg, \
1151 .en_mask = _en_mask, \
1152 .flags = _flags, \
1153 .rst_bar_mask = _rst_bar_mask, \
1154 .fmax = MT6779_PLL_FMAX, \
1155 .fmin = MT6779_PLL_FMIN, \
1156 .pcwbits = _pcwbits, \
1157 .pcwibits = _pcwibits, \
1158 .pd_reg = _pd_reg, \
1159 .pd_shift = _pd_shift, \
1160 .tuner_reg = _tuner_reg, \
1161 .tuner_en_reg = _tuner_en_reg, \
1162 .tuner_en_bit = _tuner_en_bit, \
1163 .pcw_reg = _pcw_reg, \
1164 .pcw_shift = _pcw_shift, \
1165 .pcw_chg_reg = _pcw_chg_reg, \
1166 .div_table = _div_table, \
1167 }
1168
1169#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1170 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
1171 _pd_shift, _tuner_reg, _tuner_en_reg, \
1172 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1173 _pcw_chg_reg) \
1174 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1175 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
1176 _pd_shift, _tuner_reg, _tuner_en_reg, \
1177 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1178 _pcw_chg_reg, NULL)
1179
1180static const struct mtk_pll_data plls[] = {
1181 PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, BIT(0),
1182 PLL_AO, 0, 22, 8, 0x0204, 24, 0, 0, 0, 0x0204, 0, 0),
1183 PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, BIT(0),
1184 PLL_AO, 0, 22, 8, 0x0214, 24, 0, 0, 0, 0x0214, 0, 0),
1185 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, BIT(0),
1186 PLL_AO, 0, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0, 0),
1187 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, BIT(0),
1188 (HAVE_RST_BAR), BIT(24), 22, 8, 0x0234, 24, 0, 0, 0,
1189 0x0234, 0, 0),
1190 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, BIT(0),
1191 (HAVE_RST_BAR), BIT(24), 22, 8, 0x0244, 24,
1192 0, 0, 0, 0x0244, 0, 0),
1193 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, BIT(0),
1194 0, 0, 22, 8, 0x0254, 24, 0, 0, 0, 0x0254, 0, 0),
1195 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, BIT(0),
1196 0, 0, 22, 8, 0x0264, 24, 0, 0, 0, 0x0264, 0, 0),
1197 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, BIT(0),
1198 0, 0, 22, 8, 0x0274, 24, 0, 0, 0, 0x0274, 0, 0),
1199 PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, BIT(0),
1200 (HAVE_RST_BAR), BIT(23), 22, 8, 0x02b4, 24,
1201 0, 0, 0, 0x02b4, 0, 0),
1202 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, BIT(0),
1203 (HAVE_RST_BAR), BIT(23), 22, 8, 0x0284, 24,
1204 0, 0, 0, 0x0284, 0, 0),
1205 PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, BIT(0),
1206 0, 0, 32, 8, 0x02C0, 1, 0, 0x14, 0, 0x02C4, 0, 0x2C0),
1207 PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, BIT(0),
1208 0, 0, 32, 8, 0x02D4, 1, 0, 0x14, 1, 0x02D8, 0, 0x02D4),
1209};
1210
1211static int clk_mt6779_apmixed_probe(struct platform_device *pdev)
1212{
1213 struct clk_onecell_data *clk_data;
1214 struct device_node *node = pdev->dev.of_node;
1215
1216 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1217
1218 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1219
1220 mtk_clk_register_gates(node, apmixed_clks,
1221 ARRAY_SIZE(apmixed_clks), clk_data);
1222
1223 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1224}
1225
1226static int clk_mt6779_top_probe(struct platform_device *pdev)
1227{
1228 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1229 void __iomem *base;
1230 struct clk_onecell_data *clk_data;
1231 struct device_node *node = pdev->dev.of_node;
1232
1233 base = devm_ioremap_resource(&pdev->dev, res);
1234 if (IS_ERR(base))
1235 return PTR_ERR(base);
1236
1237 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1238
1239 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1240 clk_data);
1241
1242 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
1243
1244 mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
1245 node, &mt6779_clk_lock, clk_data);
1246
1247 mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes),
1248 base, &mt6779_clk_lock, clk_data);
1249
1250 mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
1251 base, &mt6779_clk_lock, clk_data);
1252
1253 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1254}
1255
1256static int clk_mt6779_infra_probe(struct platform_device *pdev)
1257{
1258 struct clk_onecell_data *clk_data;
1259 struct device_node *node = pdev->dev.of_node;
1260
1261 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1262
1263 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
1264 clk_data);
1265
1266 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1267}
1268
1269static const struct of_device_id of_match_clk_mt6779[] = {
1270 {
1271 .compatible = "mediatek,mt6779-apmixed",
1272 .data = clk_mt6779_apmixed_probe,
1273 }, {
1274 .compatible = "mediatek,mt6779-topckgen",
1275 .data = clk_mt6779_top_probe,
1276 }, {
1277 .compatible = "mediatek,mt6779-infracfg_ao",
1278 .data = clk_mt6779_infra_probe,
1279 }, {
1280 /* sentinel */
1281 }
1282};
1283
1284static int clk_mt6779_probe(struct platform_device *pdev)
1285{
1286 int (*clk_probe)(struct platform_device *pdev);
1287 int r;
1288
1289 clk_probe = of_device_get_match_data(&pdev->dev);
1290 if (!clk_probe)
1291 return -EINVAL;
1292
1293 r = clk_probe(pdev);
1294 if (r)
1295 dev_err(&pdev->dev,
1296 "could not register clock provider: %s: %d\n",
1297 pdev->name, r);
1298
1299 return r;
1300}
1301
1302static struct platform_driver clk_mt6779_drv = {
1303 .probe = clk_mt6779_probe,
1304 .driver = {
1305 .name = "clk-mt6779",
1306 .of_match_table = of_match_clk_mt6779,
1307 },
1308};
1309
1310static int __init clk_mt6779_init(void)
1311{
1312 return platform_driver_register(&clk_mt6779_drv);
1313}
1314
1315arch_initcall(clk_mt6779_init);
diff --git a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
index 99a6b020833e..37b4162c5882 100644
--- a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
+++ b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
@@ -5,6 +5,7 @@
5 5
6#include <linux/clk-provider.h> 6#include <linux/clk-provider.h>
7#include <linux/platform_device.h> 7#include <linux/platform_device.h>
8#include <linux/pm_runtime.h>
8 9
9#include "clk-mtk.h" 10#include "clk-mtk.h"
10#include "clk-gate.h" 11#include "clk-gate.h"
@@ -30,10 +31,12 @@ static int clk_mt8183_mfg_probe(struct platform_device *pdev)
30 struct clk_onecell_data *clk_data; 31 struct clk_onecell_data *clk_data;
31 struct device_node *node = pdev->dev.of_node; 32 struct device_node *node = pdev->dev.of_node;
32 33
34 pm_runtime_enable(&pdev->dev);
35
33 clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK); 36 clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
34 37
35 mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks), 38 mtk_clk_register_gates_with_dev(node, mfg_clks, ARRAY_SIZE(mfg_clks),
36 clk_data); 39 clk_data, &pdev->dev);
37 40
38 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 41 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
39} 42}
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 1aa5f4059251..7e7452e56694 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -17,6 +17,9 @@
17 17
18#include <dt-bindings/clock/mt8183-clk.h> 18#include <dt-bindings/clock/mt8183-clk.h>
19 19
20/* Infra global controller reset set register */
21#define INFRA_RST0_SET_OFFSET 0x120
22
20static DEFINE_SPINLOCK(mt8183_clk_lock); 23static DEFINE_SPINLOCK(mt8183_clk_lock);
21 24
22static const struct mtk_fixed_clk top_fixed_clks[] = { 25static const struct mtk_fixed_clk top_fixed_clks[] = {
@@ -999,6 +1002,20 @@ static const struct mtk_gate infra_clks[] = {
999 "msdc50_0_sel", 24), 1002 "msdc50_0_sel", 24),
1000}; 1003};
1001 1004
1005static const struct mtk_gate_regs peri_cg_regs = {
1006 .set_ofs = 0x20c,
1007 .clr_ofs = 0x20c,
1008 .sta_ofs = 0x20c,
1009};
1010
1011#define GATE_PERI(_id, _name, _parent, _shift) \
1012 GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \
1013 &mtk_clk_gate_ops_no_setclr_inv)
1014
1015static const struct mtk_gate peri_clks[] = {
1016 GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31),
1017};
1018
1002static const struct mtk_gate_regs apmixed_cg_regs = { 1019static const struct mtk_gate_regs apmixed_cg_regs = {
1003 .set_ofs = 0x20, 1020 .set_ofs = 0x20,
1004 .clr_ofs = 0x20, 1021 .clr_ofs = 0x20,
@@ -1185,12 +1202,36 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
1185{ 1202{
1186 struct clk_onecell_data *clk_data; 1203 struct clk_onecell_data *clk_data;
1187 struct device_node *node = pdev->dev.of_node; 1204 struct device_node *node = pdev->dev.of_node;
1205 int r;
1188 1206
1189 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 1207 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1190 1208
1191 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 1209 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
1192 clk_data); 1210 clk_data);
1193 1211
1212 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1213 if (r) {
1214 dev_err(&pdev->dev,
1215 "%s(): could not register clock provider: %d\n",
1216 __func__, r);
1217 return r;
1218 }
1219
1220 mtk_register_reset_controller_set_clr(node, 4, INFRA_RST0_SET_OFFSET);
1221
1222 return r;
1223}
1224
1225static int clk_mt8183_peri_probe(struct platform_device *pdev)
1226{
1227 struct clk_onecell_data *clk_data;
1228 struct device_node *node = pdev->dev.of_node;
1229
1230 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
1231
1232 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
1233 clk_data);
1234
1194 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1235 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1195} 1236}
1196 1237
@@ -1224,6 +1265,9 @@ static const struct of_device_id of_match_clk_mt8183[] = {
1224 .compatible = "mediatek,mt8183-infracfg", 1265 .compatible = "mediatek,mt8183-infracfg",
1225 .data = clk_mt8183_infra_probe, 1266 .data = clk_mt8183_infra_probe,
1226 }, { 1267 }, {
1268 .compatible = "mediatek,mt8183-pericfg",
1269 .data = clk_mt8183_peri_probe,
1270 }, {
1227 .compatible = "mediatek,mt8183-mcucfg", 1271 .compatible = "mediatek,mt8183-mcucfg",
1228 .data = clk_mt8183_mcu_probe, 1272 .data = clk_mt8183_mcu_probe,
1229 }, { 1273 }, {
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index d28790c74919..cec1c8a27211 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -12,6 +12,7 @@
12#include <linux/delay.h> 12#include <linux/delay.h>
13#include <linux/clkdev.h> 13#include <linux/clkdev.h>
14#include <linux/mfd/syscon.h> 14#include <linux/mfd/syscon.h>
15#include <linux/device.h>
15 16
16#include "clk-mtk.h" 17#include "clk-mtk.h"
17#include "clk-gate.h" 18#include "clk-gate.h"
@@ -93,9 +94,10 @@ void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
93 } 94 }
94} 95}
95 96
96int mtk_clk_register_gates(struct device_node *node, 97int mtk_clk_register_gates_with_dev(struct device_node *node,
97 const struct mtk_gate *clks, 98 const struct mtk_gate *clks,
98 int num, struct clk_onecell_data *clk_data) 99 int num, struct clk_onecell_data *clk_data,
100 struct device *dev)
99{ 101{
100 int i; 102 int i;
101 struct clk *clk; 103 struct clk *clk;
@@ -122,7 +124,7 @@ int mtk_clk_register_gates(struct device_node *node,
122 gate->regs->set_ofs, 124 gate->regs->set_ofs,
123 gate->regs->clr_ofs, 125 gate->regs->clr_ofs,
124 gate->regs->sta_ofs, 126 gate->regs->sta_ofs,
125 gate->shift, gate->ops, gate->flags); 127 gate->shift, gate->ops, gate->flags, dev);
126 128
127 if (IS_ERR(clk)) { 129 if (IS_ERR(clk)) {
128 pr_err("Failed to register clk %s: %ld\n", 130 pr_err("Failed to register clk %s: %ld\n",
@@ -136,6 +138,14 @@ int mtk_clk_register_gates(struct device_node *node,
136 return 0; 138 return 0;
137} 139}
138 140
141int mtk_clk_register_gates(struct device_node *node,
142 const struct mtk_gate *clks,
143 int num, struct clk_onecell_data *clk_data)
144{
145 return mtk_clk_register_gates_with_dev(node,
146 clks, num, clk_data, NULL);
147}
148
139struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, 149struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
140 void __iomem *base, spinlock_t *lock) 150 void __iomem *base, spinlock_t *lock)
141{ 151{
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 733a11d1de94..c3d6756b0c7e 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -169,6 +169,11 @@ int mtk_clk_register_gates(struct device_node *node,
169 const struct mtk_gate *clks, int num, 169 const struct mtk_gate *clks, int num,
170 struct clk_onecell_data *clk_data); 170 struct clk_onecell_data *clk_data);
171 171
172int mtk_clk_register_gates_with_dev(struct device_node *node,
173 const struct mtk_gate *clks,
174 int num, struct clk_onecell_data *clk_data,
175 struct device *dev);
176
172struct mtk_clk_divider { 177struct mtk_clk_divider {
173 int id; 178 int id;
174 const char *name; 179 const char *name;
@@ -240,4 +245,7 @@ struct clk *mtk_clk_register_ref2usb_tx(const char *name,
240void mtk_register_reset_controller(struct device_node *np, 245void mtk_register_reset_controller(struct device_node *np,
241 unsigned int num_regs, int regofs); 246 unsigned int num_regs, int regofs);
242 247
248void mtk_register_reset_controller_set_clr(struct device_node *np,
249 unsigned int num_regs, int regofs);
250
243#endif /* __DRV_CLK_MTK_H */ 251#endif /* __DRV_CLK_MTK_H */
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index d8376b92349e..cb939c071b0c 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -19,6 +19,24 @@ struct mtk_reset {
19 struct reset_controller_dev rcdev; 19 struct reset_controller_dev rcdev;
20}; 20};
21 21
22static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
23 unsigned long id)
24{
25 struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
26 unsigned int reg = data->regofs + ((id / 32) << 4);
27
28 return regmap_write(data->regmap, reg, 1);
29}
30
31static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
32 unsigned long id)
33{
34 struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
35 unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4;
36
37 return regmap_write(data->regmap, reg, 1);
38}
39
22static int mtk_reset_assert(struct reset_controller_dev *rcdev, 40static int mtk_reset_assert(struct reset_controller_dev *rcdev,
23 unsigned long id) 41 unsigned long id)
24{ 42{
@@ -49,14 +67,32 @@ static int mtk_reset(struct reset_controller_dev *rcdev,
49 return mtk_reset_deassert(rcdev, id); 67 return mtk_reset_deassert(rcdev, id);
50} 68}
51 69
70static int mtk_reset_set_clr(struct reset_controller_dev *rcdev,
71 unsigned long id)
72{
73 int ret;
74
75 ret = mtk_reset_assert_set_clr(rcdev, id);
76 if (ret)
77 return ret;
78 return mtk_reset_deassert_set_clr(rcdev, id);
79}
80
52static const struct reset_control_ops mtk_reset_ops = { 81static const struct reset_control_ops mtk_reset_ops = {
53 .assert = mtk_reset_assert, 82 .assert = mtk_reset_assert,
54 .deassert = mtk_reset_deassert, 83 .deassert = mtk_reset_deassert,
55 .reset = mtk_reset, 84 .reset = mtk_reset,
56}; 85};
57 86
58void mtk_register_reset_controller(struct device_node *np, 87static const struct reset_control_ops mtk_reset_ops_set_clr = {
59 unsigned int num_regs, int regofs) 88 .assert = mtk_reset_assert_set_clr,
89 .deassert = mtk_reset_deassert_set_clr,
90 .reset = mtk_reset_set_clr,
91};
92
93static void mtk_register_reset_controller_common(struct device_node *np,
94 unsigned int num_regs, int regofs,
95 const struct reset_control_ops *reset_ops)
60{ 96{
61 struct mtk_reset *data; 97 struct mtk_reset *data;
62 int ret; 98 int ret;
@@ -77,7 +113,7 @@ void mtk_register_reset_controller(struct device_node *np,
77 data->regofs = regofs; 113 data->regofs = regofs;
78 data->rcdev.owner = THIS_MODULE; 114 data->rcdev.owner = THIS_MODULE;
79 data->rcdev.nr_resets = num_regs * 32; 115 data->rcdev.nr_resets = num_regs * 32;
80 data->rcdev.ops = &mtk_reset_ops; 116 data->rcdev.ops = reset_ops;
81 data->rcdev.of_node = np; 117 data->rcdev.of_node = np;
82 118
83 ret = reset_controller_register(&data->rcdev); 119 ret = reset_controller_register(&data->rcdev);
@@ -87,3 +123,17 @@ void mtk_register_reset_controller(struct device_node *np,
87 return; 123 return;
88 } 124 }
89} 125}
126
127void mtk_register_reset_controller(struct device_node *np,
128 unsigned int num_regs, int regofs)
129{
130 mtk_register_reset_controller_common(np, num_regs, regofs,
131 &mtk_reset_ops);
132}
133
134void mtk_register_reset_controller_set_clr(struct device_node *np,
135 unsigned int num_regs, int regofs)
136{
137 mtk_register_reset_controller_common(np, num_regs, regofs,
138 &mtk_reset_ops_set_clr);
139}
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index a6b20e123e0c..dabeb435d067 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -1,7 +1,4 @@
1# SPDX-License-Identifier: GPL-2.0-only 1# SPDX-License-Identifier: GPL-2.0-only
2config COMMON_CLK_MESON_INPUT
3 tristate
4
5config COMMON_CLK_MESON_REGMAP 2config COMMON_CLK_MESON_REGMAP
6 tristate 3 tristate
7 select REGMAP 4 select REGMAP
@@ -33,13 +30,15 @@ config COMMON_CLK_MESON_VID_PLL_DIV
33config COMMON_CLK_MESON_AO_CLKC 30config COMMON_CLK_MESON_AO_CLKC
34 tristate 31 tristate
35 select COMMON_CLK_MESON_REGMAP 32 select COMMON_CLK_MESON_REGMAP
36 select COMMON_CLK_MESON_INPUT
37 select RESET_CONTROLLER 33 select RESET_CONTROLLER
38 34
39config COMMON_CLK_MESON_EE_CLKC 35config COMMON_CLK_MESON_EE_CLKC
40 tristate 36 tristate
41 select COMMON_CLK_MESON_REGMAP 37 select COMMON_CLK_MESON_REGMAP
42 select COMMON_CLK_MESON_INPUT 38
39config COMMON_CLK_MESON_CPU_DYNDIV
40 tristate
41 select COMMON_CLK_MESON_REGMAP
43 42
44config COMMON_CLK_MESON8B 43config COMMON_CLK_MESON8B
45 bool 44 bool
@@ -86,7 +85,6 @@ config COMMON_CLK_AXG
86config COMMON_CLK_AXG_AUDIO 85config COMMON_CLK_AXG_AUDIO
87 tristate "Meson AXG Audio Clock Controller Driver" 86 tristate "Meson AXG Audio Clock Controller Driver"
88 depends on ARCH_MESON 87 depends on ARCH_MESON
89 select COMMON_CLK_MESON_INPUT
90 select COMMON_CLK_MESON_REGMAP 88 select COMMON_CLK_MESON_REGMAP
91 select COMMON_CLK_MESON_PHASE 89 select COMMON_CLK_MESON_PHASE
92 select COMMON_CLK_MESON_SCLK_DIV 90 select COMMON_CLK_MESON_SCLK_DIV
@@ -104,6 +102,7 @@ config COMMON_CLK_G12A
104 select COMMON_CLK_MESON_PLL 102 select COMMON_CLK_MESON_PLL
105 select COMMON_CLK_MESON_AO_CLKC 103 select COMMON_CLK_MESON_AO_CLKC
106 select COMMON_CLK_MESON_EE_CLKC 104 select COMMON_CLK_MESON_EE_CLKC
105 select COMMON_CLK_MESON_CPU_DYNDIV
107 select MFD_SYSCON 106 select MFD_SYSCON
108 help 107 help
109 Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2 108 Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index bc35a4efd6b7..3939f218587a 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -2,9 +2,9 @@
2# Amlogic clock drivers 2# Amlogic clock drivers
3 3
4obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o 4obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
5obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
5obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o 6obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
6obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) += meson-eeclk.o 7obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) += meson-eeclk.o
7obj-$(CONFIG_COMMON_CLK_MESON_INPUT) += clk-input.o
8obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o 8obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o
9obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o 9obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o
10obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o 10obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
index 0086f31288eb..b488b40c9d0e 100644
--- a/drivers/clk/meson/axg-aoclk.c
+++ b/drivers/clk/meson/axg-aoclk.c
@@ -18,8 +18,6 @@
18#include "clk-regmap.h" 18#include "clk-regmap.h"
19#include "clk-dualdiv.h" 19#include "clk-dualdiv.h"
20 20
21#define IN_PREFIX "ao-in-"
22
23/* 21/*
24 * AO Configuration Clock registers offsets 22 * AO Configuration Clock registers offsets
25 * Register offsets from the data sheet must be multiplied by 4. 23 * Register offsets from the data sheet must be multiplied by 4.
@@ -42,7 +40,9 @@ static struct clk_regmap axg_aoclk_##_name = { \
42 .hw.init = &(struct clk_init_data) { \ 40 .hw.init = &(struct clk_init_data) { \
43 .name = "axg_ao_" #_name, \ 41 .name = "axg_ao_" #_name, \
44 .ops = &clk_regmap_gate_ops, \ 42 .ops = &clk_regmap_gate_ops, \
45 .parent_names = (const char *[]){ IN_PREFIX "mpeg-clk" }, \ 43 .parent_data = &(const struct clk_parent_data) { \
44 .fw_name = "mpeg-clk", \
45 }, \
46 .num_parents = 1, \ 46 .num_parents = 1, \
47 .flags = CLK_IGNORE_UNUSED, \ 47 .flags = CLK_IGNORE_UNUSED, \
48 }, \ 48 }, \
@@ -64,7 +64,9 @@ static struct clk_regmap axg_aoclk_cts_oscin = {
64 .hw.init = &(struct clk_init_data){ 64 .hw.init = &(struct clk_init_data){
65 .name = "cts_oscin", 65 .name = "cts_oscin",
66 .ops = &clk_regmap_gate_ro_ops, 66 .ops = &clk_regmap_gate_ro_ops,
67 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 67 .parent_data = &(const struct clk_parent_data) {
68 .fw_name = "xtal",
69 },
68 .num_parents = 1, 70 .num_parents = 1,
69 }, 71 },
70}; 72};
@@ -77,7 +79,9 @@ static struct clk_regmap axg_aoclk_32k_pre = {
77 .hw.init = &(struct clk_init_data){ 79 .hw.init = &(struct clk_init_data){
78 .name = "axg_ao_32k_pre", 80 .name = "axg_ao_32k_pre",
79 .ops = &clk_regmap_gate_ops, 81 .ops = &clk_regmap_gate_ops,
80 .parent_names = (const char *[]){ "cts_oscin" }, 82 .parent_hws = (const struct clk_hw *[]) {
83 &axg_aoclk_cts_oscin.hw
84 },
81 .num_parents = 1, 85 .num_parents = 1,
82 }, 86 },
83}; 87};
@@ -124,7 +128,9 @@ static struct clk_regmap axg_aoclk_32k_div = {
124 .hw.init = &(struct clk_init_data){ 128 .hw.init = &(struct clk_init_data){
125 .name = "axg_ao_32k_div", 129 .name = "axg_ao_32k_div",
126 .ops = &meson_clk_dualdiv_ops, 130 .ops = &meson_clk_dualdiv_ops,
127 .parent_names = (const char *[]){ "axg_ao_32k_pre" }, 131 .parent_hws = (const struct clk_hw *[]) {
132 &axg_aoclk_32k_pre.hw
133 },
128 .num_parents = 1, 134 .num_parents = 1,
129 }, 135 },
130}; 136};
@@ -139,8 +145,10 @@ static struct clk_regmap axg_aoclk_32k_sel = {
139 .hw.init = &(struct clk_init_data){ 145 .hw.init = &(struct clk_init_data){
140 .name = "axg_ao_32k_sel", 146 .name = "axg_ao_32k_sel",
141 .ops = &clk_regmap_mux_ops, 147 .ops = &clk_regmap_mux_ops,
142 .parent_names = (const char *[]){ "axg_ao_32k_div", 148 .parent_hws = (const struct clk_hw *[]) {
143 "axg_ao_32k_pre" }, 149 &axg_aoclk_32k_div.hw,
150 &axg_aoclk_32k_pre.hw,
151 },
144 .num_parents = 2, 152 .num_parents = 2,
145 .flags = CLK_SET_RATE_PARENT, 153 .flags = CLK_SET_RATE_PARENT,
146 }, 154 },
@@ -154,7 +162,9 @@ static struct clk_regmap axg_aoclk_32k = {
154 .hw.init = &(struct clk_init_data){ 162 .hw.init = &(struct clk_init_data){
155 .name = "axg_ao_32k", 163 .name = "axg_ao_32k",
156 .ops = &clk_regmap_gate_ops, 164 .ops = &clk_regmap_gate_ops,
157 .parent_names = (const char *[]){ "axg_ao_32k_sel" }, 165 .parent_hws = (const struct clk_hw *[]) {
166 &axg_aoclk_32k_sel.hw
167 },
158 .num_parents = 1, 168 .num_parents = 1,
159 .flags = CLK_SET_RATE_PARENT, 169 .flags = CLK_SET_RATE_PARENT,
160 }, 170 },
@@ -170,8 +180,10 @@ static struct clk_regmap axg_aoclk_cts_rtc_oscin = {
170 .hw.init = &(struct clk_init_data){ 180 .hw.init = &(struct clk_init_data){
171 .name = "axg_ao_cts_rtc_oscin", 181 .name = "axg_ao_cts_rtc_oscin",
172 .ops = &clk_regmap_mux_ops, 182 .ops = &clk_regmap_mux_ops,
173 .parent_names = (const char *[]){ "axg_ao_32k", 183 .parent_data = (const struct clk_parent_data []) {
174 IN_PREFIX "ext_32k-0" }, 184 { .hw = &axg_aoclk_32k.hw },
185 { .fw_name = "ext_32k-0", },
186 },
175 .num_parents = 2, 187 .num_parents = 2,
176 .flags = CLK_SET_RATE_PARENT, 188 .flags = CLK_SET_RATE_PARENT,
177 }, 189 },
@@ -187,8 +199,10 @@ static struct clk_regmap axg_aoclk_clk81 = {
187 .hw.init = &(struct clk_init_data){ 199 .hw.init = &(struct clk_init_data){
188 .name = "axg_ao_clk81", 200 .name = "axg_ao_clk81",
189 .ops = &clk_regmap_mux_ro_ops, 201 .ops = &clk_regmap_mux_ro_ops,
190 .parent_names = (const char *[]){ IN_PREFIX "mpeg-clk", 202 .parent_data = (const struct clk_parent_data []) {
191 "axg_ao_cts_rtc_oscin"}, 203 { .fw_name = "mpeg-clk", },
204 { .hw = &axg_aoclk_cts_rtc_oscin.hw },
205 },
192 .num_parents = 2, 206 .num_parents = 2,
193 .flags = CLK_SET_RATE_PARENT, 207 .flags = CLK_SET_RATE_PARENT,
194 }, 208 },
@@ -203,8 +217,10 @@ static struct clk_regmap axg_aoclk_saradc_mux = {
203 .hw.init = &(struct clk_init_data){ 217 .hw.init = &(struct clk_init_data){
204 .name = "axg_ao_saradc_mux", 218 .name = "axg_ao_saradc_mux",
205 .ops = &clk_regmap_mux_ops, 219 .ops = &clk_regmap_mux_ops,
206 .parent_names = (const char *[]){ IN_PREFIX "xtal", 220 .parent_data = (const struct clk_parent_data []) {
207 "axg_ao_clk81" }, 221 { .fw_name = "xtal", },
222 { .hw = &axg_aoclk_clk81.hw },
223 },
208 .num_parents = 2, 224 .num_parents = 2,
209 }, 225 },
210}; 226};
@@ -218,7 +234,9 @@ static struct clk_regmap axg_aoclk_saradc_div = {
218 .hw.init = &(struct clk_init_data){ 234 .hw.init = &(struct clk_init_data){
219 .name = "axg_ao_saradc_div", 235 .name = "axg_ao_saradc_div",
220 .ops = &clk_regmap_divider_ops, 236 .ops = &clk_regmap_divider_ops,
221 .parent_names = (const char *[]){ "axg_ao_saradc_mux" }, 237 .parent_hws = (const struct clk_hw *[]) {
238 &axg_aoclk_saradc_mux.hw
239 },
222 .num_parents = 1, 240 .num_parents = 1,
223 .flags = CLK_SET_RATE_PARENT, 241 .flags = CLK_SET_RATE_PARENT,
224 }, 242 },
@@ -232,7 +250,9 @@ static struct clk_regmap axg_aoclk_saradc_gate = {
232 .hw.init = &(struct clk_init_data){ 250 .hw.init = &(struct clk_init_data){
233 .name = "axg_ao_saradc_gate", 251 .name = "axg_ao_saradc_gate",
234 .ops = &clk_regmap_gate_ops, 252 .ops = &clk_regmap_gate_ops,
235 .parent_names = (const char *[]){ "axg_ao_saradc_div" }, 253 .parent_hws = (const struct clk_hw *[]) {
254 &axg_aoclk_saradc_div.hw
255 },
236 .num_parents = 1, 256 .num_parents = 1,
237 .flags = CLK_SET_RATE_PARENT, 257 .flags = CLK_SET_RATE_PARENT,
238 }, 258 },
@@ -290,12 +310,6 @@ static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
290 .num = NR_CLKS, 310 .num = NR_CLKS,
291}; 311};
292 312
293static const struct meson_aoclk_input axg_aoclk_inputs[] = {
294 { .name = "xtal", .required = true },
295 { .name = "mpeg-clk", .required = true },
296 { .name = "ext-32k-0", .required = false },
297};
298
299static const struct meson_aoclk_data axg_aoclkc_data = { 313static const struct meson_aoclk_data axg_aoclkc_data = {
300 .reset_reg = AO_RTI_GEN_CNTL_REG0, 314 .reset_reg = AO_RTI_GEN_CNTL_REG0,
301 .num_reset = ARRAY_SIZE(axg_aoclk_reset), 315 .num_reset = ARRAY_SIZE(axg_aoclk_reset),
@@ -303,9 +317,6 @@ static const struct meson_aoclk_data axg_aoclkc_data = {
303 .num_clks = ARRAY_SIZE(axg_aoclk_regmap), 317 .num_clks = ARRAY_SIZE(axg_aoclk_regmap),
304 .clks = axg_aoclk_regmap, 318 .clks = axg_aoclk_regmap,
305 .hw_data = &axg_aoclk_onecell_data, 319 .hw_data = &axg_aoclk_onecell_data,
306 .inputs = axg_aoclk_inputs,
307 .num_inputs = ARRAY_SIZE(axg_aoclk_inputs),
308 .input_prefix = IN_PREFIX,
309}; 320};
310 321
311static const struct of_device_id axg_aoclkc_match_table[] = { 322static const struct of_device_id axg_aoclkc_match_table[] = {
diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index 8028ff6f6610..6be9df1efce5 100644
--- a/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
@@ -12,10 +12,10 @@
12#include <linux/platform_device.h> 12#include <linux/platform_device.h>
13#include <linux/regmap.h> 13#include <linux/regmap.h>
14#include <linux/reset.h> 14#include <linux/reset.h>
15#include <linux/reset-controller.h>
15#include <linux/slab.h> 16#include <linux/slab.h>
16 17
17#include "axg-audio.h" 18#include "axg-audio.h"
18#include "clk-input.h"
19#include "clk-regmap.h" 19#include "clk-regmap.h"
20#include "clk-phase.h" 20#include "clk-phase.h"
21#include "sclk-div.h" 21#include "sclk-div.h"
@@ -24,7 +24,7 @@
24#define AUD_SLV_SCLK_COUNT 10 24#define AUD_SLV_SCLK_COUNT 10
25#define AUD_SLV_LRCLK_COUNT 10 25#define AUD_SLV_LRCLK_COUNT 10
26 26
27#define AUD_GATE(_name, _reg, _bit, _pname, _iflags) \ 27#define AUD_GATE(_name, _reg, _bit, _phws, _iflags) \
28struct clk_regmap aud_##_name = { \ 28struct clk_regmap aud_##_name = { \
29 .data = &(struct clk_regmap_gate_data){ \ 29 .data = &(struct clk_regmap_gate_data){ \
30 .offset = (_reg), \ 30 .offset = (_reg), \
@@ -33,13 +33,13 @@ struct clk_regmap aud_##_name = { \
33 .hw.init = &(struct clk_init_data) { \ 33 .hw.init = &(struct clk_init_data) { \
34 .name = "aud_"#_name, \ 34 .name = "aud_"#_name, \
35 .ops = &clk_regmap_gate_ops, \ 35 .ops = &clk_regmap_gate_ops, \
36 .parent_names = (const char *[]){ _pname }, \ 36 .parent_hws = (const struct clk_hw *[]) { &_phws.hw }, \
37 .num_parents = 1, \ 37 .num_parents = 1, \
38 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ 38 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
39 }, \ 39 }, \
40} 40}
41 41
42#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pnames, _iflags) \ 42#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags) \
43struct clk_regmap aud_##_name = { \ 43struct clk_regmap aud_##_name = { \
44 .data = &(struct clk_regmap_mux_data){ \ 44 .data = &(struct clk_regmap_mux_data){ \
45 .offset = (_reg), \ 45 .offset = (_reg), \
@@ -50,13 +50,13 @@ struct clk_regmap aud_##_name = { \
50 .hw.init = &(struct clk_init_data){ \ 50 .hw.init = &(struct clk_init_data){ \
51 .name = "aud_"#_name, \ 51 .name = "aud_"#_name, \
52 .ops = &clk_regmap_mux_ops, \ 52 .ops = &clk_regmap_mux_ops, \
53 .parent_names = (_pnames), \ 53 .parent_data = _pdata, \
54 .num_parents = ARRAY_SIZE(_pnames), \ 54 .num_parents = ARRAY_SIZE(_pdata), \
55 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ 55 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
56 }, \ 56 }, \
57} 57}
58 58
59#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) \ 59#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _phws, _iflags) \
60struct clk_regmap aud_##_name = { \ 60struct clk_regmap aud_##_name = { \
61 .data = &(struct clk_regmap_div_data){ \ 61 .data = &(struct clk_regmap_div_data){ \
62 .offset = (_reg), \ 62 .offset = (_reg), \
@@ -67,15 +67,27 @@ struct clk_regmap aud_##_name = { \
67 .hw.init = &(struct clk_init_data){ \ 67 .hw.init = &(struct clk_init_data){ \
68 .name = "aud_"#_name, \ 68 .name = "aud_"#_name, \
69 .ops = &clk_regmap_divider_ops, \ 69 .ops = &clk_regmap_divider_ops, \
70 .parent_names = (const char *[]) { _pname }, \ 70 .parent_hws = (const struct clk_hw *[]) { &_phws.hw }, \
71 .num_parents = 1, \ 71 .num_parents = 1, \
72 .flags = (_iflags), \ 72 .flags = (_iflags), \
73 }, \ 73 }, \
74} 74}
75 75
76#define AUD_PCLK_GATE(_name, _bit) \ 76#define AUD_PCLK_GATE(_name, _bit) \
77 AUD_GATE(_name, AUDIO_CLK_GATE_EN, _bit, "audio_pclk", 0) 77struct clk_regmap aud_##_name = { \
78 78 .data = &(struct clk_regmap_gate_data){ \
79 .offset = (AUDIO_CLK_GATE_EN), \
80 .bit_idx = (_bit), \
81 }, \
82 .hw.init = &(struct clk_init_data) { \
83 .name = "aud_"#_name, \
84 .ops = &clk_regmap_gate_ops, \
85 .parent_data = &(const struct clk_parent_data) { \
86 .fw_name = "pclk", \
87 }, \
88 .num_parents = 1, \
89 }, \
90}
79/* Audio peripheral clocks */ 91/* Audio peripheral clocks */
80static AUD_PCLK_GATE(ddr_arb, 0); 92static AUD_PCLK_GATE(ddr_arb, 0);
81static AUD_PCLK_GATE(pdm, 1); 93static AUD_PCLK_GATE(pdm, 1);
@@ -100,14 +112,20 @@ static AUD_PCLK_GATE(power_detect, 19);
100static AUD_PCLK_GATE(spdifout_b, 21); 112static AUD_PCLK_GATE(spdifout_b, 21);
101 113
102/* Audio Master Clocks */ 114/* Audio Master Clocks */
103static const char * const mst_mux_parent_names[] = { 115static const struct clk_parent_data mst_mux_parent_data[] = {
104 "aud_mst_in0", "aud_mst_in1", "aud_mst_in2", "aud_mst_in3", 116 { .fw_name = "mst_in0", },
105 "aud_mst_in4", "aud_mst_in5", "aud_mst_in6", "aud_mst_in7", 117 { .fw_name = "mst_in1", },
118 { .fw_name = "mst_in2", },
119 { .fw_name = "mst_in3", },
120 { .fw_name = "mst_in4", },
121 { .fw_name = "mst_in5", },
122 { .fw_name = "mst_in6", },
123 { .fw_name = "mst_in7", },
106}; 124};
107 125
108#define AUD_MST_MUX(_name, _reg, _flag) \ 126#define AUD_MST_MUX(_name, _reg, _flag) \
109 AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \ 127 AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \
110 mst_mux_parent_names, CLK_SET_RATE_PARENT) 128 mst_mux_parent_data, 0)
111 129
112#define AUD_MST_MCLK_MUX(_name, _reg) \ 130#define AUD_MST_MCLK_MUX(_name, _reg) \
113 AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST) 131 AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
@@ -129,7 +147,7 @@ static AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
129 147
130#define AUD_MST_DIV(_name, _reg, _flag) \ 148#define AUD_MST_DIV(_name, _reg, _flag) \
131 AUD_DIV(_name##_div, _reg, 0, 16, _flag, \ 149 AUD_DIV(_name##_div, _reg, 0, 16, _flag, \
132 "aud_"#_name"_sel", CLK_SET_RATE_PARENT) \ 150 aud_##_name##_sel, CLK_SET_RATE_PARENT) \
133 151
134#define AUD_MST_MCLK_DIV(_name, _reg) \ 152#define AUD_MST_MCLK_DIV(_name, _reg) \
135 AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST) 153 AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
@@ -150,7 +168,7 @@ static AUD_MST_SYS_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
150static AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL); 168static AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
151 169
152#define AUD_MST_MCLK_GATE(_name, _reg) \ 170#define AUD_MST_MCLK_GATE(_name, _reg) \
153 AUD_GATE(_name, _reg, 31, "aud_"#_name"_div", \ 171 AUD_GATE(_name, _reg, 31, aud_##_name##_div, \
154 CLK_SET_RATE_PARENT) 172 CLK_SET_RATE_PARENT)
155 173
156static AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL); 174static AUD_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);
@@ -168,7 +186,7 @@ static AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
168/* Sample Clocks */ 186/* Sample Clocks */
169#define AUD_MST_SCLK_PRE_EN(_name, _reg) \ 187#define AUD_MST_SCLK_PRE_EN(_name, _reg) \
170 AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \ 188 AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31, \
171 "aud_mst_"#_name"_mclk", 0) 189 aud_mst_##_name##_mclk, 0)
172 190
173static AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0); 191static AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
174static AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0); 192static AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
@@ -178,7 +196,7 @@ static AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
178static AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0); 196static AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
179 197
180#define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \ 198#define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width, \
181 _hi_shift, _hi_width, _pname, _iflags) \ 199 _hi_shift, _hi_width, _phws, _iflags) \
182struct clk_regmap aud_##_name = { \ 200struct clk_regmap aud_##_name = { \
183 .data = &(struct meson_sclk_div_data) { \ 201 .data = &(struct meson_sclk_div_data) { \
184 .div = { \ 202 .div = { \
@@ -195,7 +213,7 @@ struct clk_regmap aud_##_name = { \
195 .hw.init = &(struct clk_init_data) { \ 213 .hw.init = &(struct clk_init_data) { \
196 .name = "aud_"#_name, \ 214 .name = "aud_"#_name, \
197 .ops = &meson_sclk_div_ops, \ 215 .ops = &meson_sclk_div_ops, \
198 .parent_names = (const char *[]) { _pname }, \ 216 .parent_hws = (const struct clk_hw *[]) { &_phws.hw }, \
199 .num_parents = 1, \ 217 .num_parents = 1, \
200 .flags = (_iflags), \ 218 .flags = (_iflags), \
201 }, \ 219 }, \
@@ -203,7 +221,7 @@ struct clk_regmap aud_##_name = { \
203 221
204#define AUD_MST_SCLK_DIV(_name, _reg) \ 222#define AUD_MST_SCLK_DIV(_name, _reg) \
205 AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \ 223 AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0, \
206 "aud_mst_"#_name"_sclk_pre_en", \ 224 aud_mst_##_name##_sclk_pre_en, \
207 CLK_SET_RATE_PARENT) 225 CLK_SET_RATE_PARENT)
208 226
209static AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0); 227static AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
@@ -214,8 +232,8 @@ static AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
214static AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0); 232static AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
215 233
216#define AUD_MST_SCLK_POST_EN(_name, _reg) \ 234#define AUD_MST_SCLK_POST_EN(_name, _reg) \
217 AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \ 235 AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30, \
218 "aud_mst_"#_name"_sclk_div", CLK_SET_RATE_PARENT) 236 aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT)
219 237
220static AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0); 238static AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
221static AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0); 239static AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
@@ -224,8 +242,8 @@ static AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
224static AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0); 242static AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
225static AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0); 243static AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
226 244
227#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ 245#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \
228 _pname, _iflags) \ 246 _phws, _iflags) \
229struct clk_regmap aud_##_name = { \ 247struct clk_regmap aud_##_name = { \
230 .data = &(struct meson_clk_triphase_data) { \ 248 .data = &(struct meson_clk_triphase_data) { \
231 .ph0 = { \ 249 .ph0 = { \
@@ -247,7 +265,7 @@ struct clk_regmap aud_##_name = { \
247 .hw.init = &(struct clk_init_data) { \ 265 .hw.init = &(struct clk_init_data) { \
248 .name = "aud_"#_name, \ 266 .name = "aud_"#_name, \
249 .ops = &meson_clk_triphase_ops, \ 267 .ops = &meson_clk_triphase_ops, \
250 .parent_names = (const char *[]) { _pname }, \ 268 .parent_hws = (const struct clk_hw *[]) { &_phws.hw }, \
251 .num_parents = 1, \ 269 .num_parents = 1, \
252 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \ 270 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags), \
253 }, \ 271 }, \
@@ -255,7 +273,7 @@ struct clk_regmap aud_##_name = { \
255 273
256#define AUD_MST_SCLK(_name, _reg) \ 274#define AUD_MST_SCLK(_name, _reg) \
257 AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \ 275 AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4, \
258 "aud_mst_"#_name"_sclk_post_en", CLK_SET_RATE_PARENT) 276 aud_mst_##_name##_sclk_post_en, CLK_SET_RATE_PARENT)
259 277
260static AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1); 278static AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
261static AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1); 279static AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
@@ -266,7 +284,7 @@ static AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
266 284
267#define AUD_MST_LRCLK_DIV(_name, _reg) \ 285#define AUD_MST_LRCLK_DIV(_name, _reg) \
268 AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \ 286 AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10, \
269 "aud_mst_"#_name"_sclk_post_en", 0) \ 287 aud_mst_##_name##_sclk_post_en, 0) \
270 288
271static AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0); 289static AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
272static AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0); 290static AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
@@ -277,7 +295,7 @@ static AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
277 295
278#define AUD_MST_LRCLK(_name, _reg) \ 296#define AUD_MST_LRCLK(_name, _reg) \
279 AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \ 297 AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5, \
280 "aud_mst_"#_name"_lrclk_div", CLK_SET_RATE_PARENT) 298 aud_mst_##_name##_lrclk_div, CLK_SET_RATE_PARENT)
281 299
282static AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1); 300static AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
283static AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1); 301static AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
@@ -286,19 +304,29 @@ static AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
286static AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1); 304static AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
287static AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1); 305static AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
288 306
289static const char * const tdm_sclk_parent_names[] = { 307static const struct clk_parent_data tdm_sclk_parent_data[] = {
290 "aud_mst_a_sclk", "aud_mst_b_sclk", "aud_mst_c_sclk", 308 { .hw = &aud_mst_a_sclk.hw, },
291 "aud_mst_d_sclk", "aud_mst_e_sclk", "aud_mst_f_sclk", 309 { .hw = &aud_mst_b_sclk.hw, },
292 "aud_slv_sclk0", "aud_slv_sclk1", "aud_slv_sclk2", 310 { .hw = &aud_mst_c_sclk.hw, },
293 "aud_slv_sclk3", "aud_slv_sclk4", "aud_slv_sclk5", 311 { .hw = &aud_mst_d_sclk.hw, },
294 "aud_slv_sclk6", "aud_slv_sclk7", "aud_slv_sclk8", 312 { .hw = &aud_mst_e_sclk.hw, },
295 "aud_slv_sclk9" 313 { .hw = &aud_mst_f_sclk.hw, },
314 { .fw_name = "slv_sclk0", },
315 { .fw_name = "slv_sclk1", },
316 { .fw_name = "slv_sclk2", },
317 { .fw_name = "slv_sclk3", },
318 { .fw_name = "slv_sclk4", },
319 { .fw_name = "slv_sclk5", },
320 { .fw_name = "slv_sclk6", },
321 { .fw_name = "slv_sclk7", },
322 { .fw_name = "slv_sclk8", },
323 { .fw_name = "slv_sclk9", },
296}; 324};
297 325
298#define AUD_TDM_SCLK_MUX(_name, _reg) \ 326#define AUD_TDM_SCLK_MUX(_name, _reg) \
299 AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \ 327 AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24, \
300 CLK_MUX_ROUND_CLOSEST, \ 328 CLK_MUX_ROUND_CLOSEST, \
301 tdm_sclk_parent_names, 0) 329 tdm_sclk_parent_data, 0)
302 330
303static AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL); 331static AUD_TDM_SCLK_MUX(in_a, AUDIO_CLK_TDMIN_A_CTRL);
304static AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL); 332static AUD_TDM_SCLK_MUX(in_b, AUDIO_CLK_TDMIN_B_CTRL);
@@ -310,7 +338,7 @@ static AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
310 338
311#define AUD_TDM_SCLK_PRE_EN(_name, _reg) \ 339#define AUD_TDM_SCLK_PRE_EN(_name, _reg) \
312 AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \ 340 AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31, \
313 "aud_tdm"#_name"_sclk_sel", CLK_SET_RATE_PARENT) 341 aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT)
314 342
315static AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL); 343static AUD_TDM_SCLK_PRE_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
316static AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL); 344static AUD_TDM_SCLK_PRE_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
@@ -322,7 +350,7 @@ static AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
322 350
323#define AUD_TDM_SCLK_POST_EN(_name, _reg) \ 351#define AUD_TDM_SCLK_POST_EN(_name, _reg) \
324 AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \ 352 AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30, \
325 "aud_tdm"#_name"_sclk_pre_en", CLK_SET_RATE_PARENT) 353 aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT)
326 354
327static AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL); 355static AUD_TDM_SCLK_POST_EN(in_a, AUDIO_CLK_TDMIN_A_CTRL);
328static AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL); 356static AUD_TDM_SCLK_POST_EN(in_b, AUDIO_CLK_TDMIN_B_CTRL);
@@ -344,8 +372,9 @@ static AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
344 .hw.init = &(struct clk_init_data) { \ 372 .hw.init = &(struct clk_init_data) { \
345 .name = "aud_tdm"#_name"_sclk", \ 373 .name = "aud_tdm"#_name"_sclk", \
346 .ops = &meson_clk_phase_ops, \ 374 .ops = &meson_clk_phase_ops, \
347 .parent_names = (const char *[]) \ 375 .parent_hws = (const struct clk_hw *[]) { \
348 { "aud_tdm"#_name"_sclk_post_en" }, \ 376 &aud_tdm##_name##_sclk_post_en.hw \
377 }, \
349 .num_parents = 1, \ 378 .num_parents = 1, \
350 .flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT, \ 379 .flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT, \
351 }, \ 380 }, \
@@ -359,19 +388,29 @@ static AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
359static AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL); 388static AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
360static AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL); 389static AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
361 390
362static const char * const tdm_lrclk_parent_names[] = { 391static const struct clk_parent_data tdm_lrclk_parent_data[] = {
363 "aud_mst_a_lrclk", "aud_mst_b_lrclk", "aud_mst_c_lrclk", 392 { .hw = &aud_mst_a_lrclk.hw, },
364 "aud_mst_d_lrclk", "aud_mst_e_lrclk", "aud_mst_f_lrclk", 393 { .hw = &aud_mst_b_lrclk.hw, },
365 "aud_slv_lrclk0", "aud_slv_lrclk1", "aud_slv_lrclk2", 394 { .hw = &aud_mst_c_lrclk.hw, },
366 "aud_slv_lrclk3", "aud_slv_lrclk4", "aud_slv_lrclk5", 395 { .hw = &aud_mst_d_lrclk.hw, },
367 "aud_slv_lrclk6", "aud_slv_lrclk7", "aud_slv_lrclk8", 396 { .hw = &aud_mst_e_lrclk.hw, },
368 "aud_slv_lrclk9" 397 { .hw = &aud_mst_f_lrclk.hw, },
398 { .fw_name = "slv_lrclk0", },
399 { .fw_name = "slv_lrclk1", },
400 { .fw_name = "slv_lrclk2", },
401 { .fw_name = "slv_lrclk3", },
402 { .fw_name = "slv_lrclk4", },
403 { .fw_name = "slv_lrclk5", },
404 { .fw_name = "slv_lrclk6", },
405 { .fw_name = "slv_lrclk7", },
406 { .fw_name = "slv_lrclk8", },
407 { .fw_name = "slv_lrclk9", },
369}; 408};
370 409
371#define AUD_TDM_LRLCK(_name, _reg) \ 410#define AUD_TDM_LRLCK(_name, _reg) \
372 AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \ 411 AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20, \
373 CLK_MUX_ROUND_CLOSEST, \ 412 CLK_MUX_ROUND_CLOSEST, \
374 tdm_lrclk_parent_names, 0) 413 tdm_lrclk_parent_data, 0)
375 414
376static AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL); 415static AUD_TDM_LRLCK(in_a, AUDIO_CLK_TDMIN_A_CTRL);
377static AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL); 416static AUD_TDM_LRLCK(in_b, AUDIO_CLK_TDMIN_B_CTRL);
@@ -386,39 +425,51 @@ static AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
386 AUD_MUX(tdm_##_name, _reg, 0x7, _shift, 0, _parents, \ 425 AUD_MUX(tdm_##_name, _reg, 0x7, _shift, 0, _parents, \
387 CLK_SET_RATE_NO_REPARENT) 426 CLK_SET_RATE_NO_REPARENT)
388 427
389static const char * const mclk_pad_ctrl_parent_names[] = { 428static const struct clk_parent_data mclk_pad_ctrl_parent_data[] = {
390 "aud_mst_a_mclk", "aud_mst_b_mclk", "aud_mst_c_mclk", 429 { .hw = &aud_mst_a_mclk.hw },
391 "aud_mst_d_mclk", "aud_mst_e_mclk", "aud_mst_f_mclk", 430 { .hw = &aud_mst_b_mclk.hw },
431 { .hw = &aud_mst_c_mclk.hw },
432 { .hw = &aud_mst_d_mclk.hw },
433 { .hw = &aud_mst_e_mclk.hw },
434 { .hw = &aud_mst_f_mclk.hw },
392}; 435};
393 436
394static AUD_TDM_PAD_CTRL(mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0, 437static AUD_TDM_PAD_CTRL(mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0,
395 mclk_pad_ctrl_parent_names); 438 mclk_pad_ctrl_parent_data);
396static AUD_TDM_PAD_CTRL(mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4, 439static AUD_TDM_PAD_CTRL(mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4,
397 mclk_pad_ctrl_parent_names); 440 mclk_pad_ctrl_parent_data);
398 441
399static const char * const lrclk_pad_ctrl_parent_names[] = { 442static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = {
400 "aud_mst_a_lrclk", "aud_mst_b_lrclk", "aud_mst_c_lrclk", 443 { .hw = &aud_mst_a_lrclk.hw },
401 "aud_mst_d_lrclk", "aud_mst_e_lrclk", "aud_mst_f_lrclk", 444 { .hw = &aud_mst_b_lrclk.hw },
445 { .hw = &aud_mst_c_lrclk.hw },
446 { .hw = &aud_mst_d_lrclk.hw },
447 { .hw = &aud_mst_e_lrclk.hw },
448 { .hw = &aud_mst_f_lrclk.hw },
402}; 449};
403 450
404static AUD_TDM_PAD_CTRL(lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16, 451static AUD_TDM_PAD_CTRL(lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16,
405 lrclk_pad_ctrl_parent_names); 452 lrclk_pad_ctrl_parent_data);
406static AUD_TDM_PAD_CTRL(lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20, 453static AUD_TDM_PAD_CTRL(lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20,
407 lrclk_pad_ctrl_parent_names); 454 lrclk_pad_ctrl_parent_data);
408static AUD_TDM_PAD_CTRL(lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24, 455static AUD_TDM_PAD_CTRL(lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24,
409 lrclk_pad_ctrl_parent_names); 456 lrclk_pad_ctrl_parent_data);
410 457
411static const char * const sclk_pad_ctrl_parent_names[] = { 458static const struct clk_parent_data sclk_pad_ctrl_parent_data[] = {
412 "aud_mst_a_sclk", "aud_mst_b_sclk", "aud_mst_c_sclk", 459 { .hw = &aud_mst_a_sclk.hw },
413 "aud_mst_d_sclk", "aud_mst_e_sclk", "aud_mst_f_sclk", 460 { .hw = &aud_mst_b_sclk.hw },
461 { .hw = &aud_mst_c_sclk.hw },
462 { .hw = &aud_mst_d_sclk.hw },
463 { .hw = &aud_mst_e_sclk.hw },
464 { .hw = &aud_mst_f_sclk.hw },
414}; 465};
415 466
416static AUD_TDM_PAD_CTRL(sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0, 467static AUD_TDM_PAD_CTRL(sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0,
417 sclk_pad_ctrl_parent_names); 468 sclk_pad_ctrl_parent_data);
418static AUD_TDM_PAD_CTRL(sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4, 469static AUD_TDM_PAD_CTRL(sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4,
419 sclk_pad_ctrl_parent_names); 470 sclk_pad_ctrl_parent_data);
420static AUD_TDM_PAD_CTRL(sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8, 471static AUD_TDM_PAD_CTRL(sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8,
421 sclk_pad_ctrl_parent_names); 472 sclk_pad_ctrl_parent_data);
422 473
423/* 474/*
424 * Array of all clocks provided by this provider 475 * Array of all clocks provided by this provider
@@ -868,54 +919,84 @@ static int devm_clk_get_enable(struct device *dev, char *id)
868 return 0; 919 return 0;
869} 920}
870 921
871static int axg_register_clk_hw_input(struct device *dev, 922struct axg_audio_reset_data {
872 const char *name) 923 struct reset_controller_dev rstc;
924 struct regmap *map;
925 unsigned int offset;
926};
927
928static void axg_audio_reset_reg_and_bit(struct axg_audio_reset_data *rst,
929 unsigned long id,
930 unsigned int *reg,
931 unsigned int *bit)
932{
933 unsigned int stride = regmap_get_reg_stride(rst->map);
934
935 *reg = (id / (stride * BITS_PER_BYTE)) * stride;
936 *reg += rst->offset;
937 *bit = id % (stride * BITS_PER_BYTE);
938}
939
940static int axg_audio_reset_update(struct reset_controller_dev *rcdev,
941 unsigned long id, bool assert)
873{ 942{
874 char *clk_name; 943 struct axg_audio_reset_data *rst =
875 struct clk_hw *hw; 944 container_of(rcdev, struct axg_audio_reset_data, rstc);
876 int err = 0; 945 unsigned int offset, bit;
877 946
878 clk_name = kasprintf(GFP_KERNEL, "aud_%s", name); 947 axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
879 if (!clk_name)
880 return -ENOMEM;
881 948
882 hw = meson_clk_hw_register_input(dev, name, clk_name, 0); 949 regmap_update_bits(rst->map, offset, BIT(bit),
883 if (IS_ERR(hw)) { 950 assert ? BIT(bit) : 0);
884 /* It is ok if an input clock is missing */
885 if (PTR_ERR(hw) == -ENOENT) {
886 dev_dbg(dev, "%s not provided", name);
887 } else {
888 err = PTR_ERR(hw);
889 if (err != -EPROBE_DEFER)
890 dev_err(dev, "failed to get %s clock", name);
891 }
892 }
893 951
894 kfree(clk_name); 952 return 0;
895 return err;
896} 953}
897 954
898static int axg_register_clk_hw_inputs(struct device *dev, 955static int axg_audio_reset_status(struct reset_controller_dev *rcdev,
899 const char *basename, 956 unsigned long id)
900 unsigned int count)
901{ 957{
902 char *name; 958 struct axg_audio_reset_data *rst =
903 int i, ret; 959 container_of(rcdev, struct axg_audio_reset_data, rstc);
960 unsigned int val, offset, bit;
904 961
905 for (i = 0; i < count; i++) { 962 axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
906 name = kasprintf(GFP_KERNEL, "%s%d", basename, i);
907 if (!name)
908 return -ENOMEM;
909 963
910 ret = axg_register_clk_hw_input(dev, name); 964 regmap_read(rst->map, offset, &val);
911 kfree(name);
912 if (ret)
913 return ret;
914 }
915 965
916 return 0; 966 return !!(val & BIT(bit));
917} 967}
918 968
969static int axg_audio_reset_assert(struct reset_controller_dev *rcdev,
970 unsigned long id)
971{
972 return axg_audio_reset_update(rcdev, id, true);
973}
974
975static int axg_audio_reset_deassert(struct reset_controller_dev *rcdev,
976 unsigned long id)
977{
978 return axg_audio_reset_update(rcdev, id, false);
979}
980
981static int axg_audio_reset_toggle(struct reset_controller_dev *rcdev,
982 unsigned long id)
983{
984 int ret;
985
986 ret = axg_audio_reset_assert(rcdev, id);
987 if (ret)
988 return ret;
989
990 return axg_audio_reset_deassert(rcdev, id);
991}
992
993static const struct reset_control_ops axg_audio_rstc_ops = {
994 .assert = axg_audio_reset_assert,
995 .deassert = axg_audio_reset_deassert,
996 .reset = axg_audio_reset_toggle,
997 .status = axg_audio_reset_status,
998};
999
919static const struct regmap_config axg_audio_regmap_cfg = { 1000static const struct regmap_config axg_audio_regmap_cfg = {
920 .reg_bits = 32, 1001 .reg_bits = 32,
921 .val_bits = 32, 1002 .val_bits = 32,
@@ -925,12 +1006,15 @@ static const struct regmap_config axg_audio_regmap_cfg = {
925 1006
926struct audioclk_data { 1007struct audioclk_data {
927 struct clk_hw_onecell_data *hw_onecell_data; 1008 struct clk_hw_onecell_data *hw_onecell_data;
1009 unsigned int reset_offset;
1010 unsigned int reset_num;
928}; 1011};
929 1012
930static int axg_audio_clkc_probe(struct platform_device *pdev) 1013static int axg_audio_clkc_probe(struct platform_device *pdev)
931{ 1014{
932 struct device *dev = &pdev->dev; 1015 struct device *dev = &pdev->dev;
933 const struct audioclk_data *data; 1016 const struct audioclk_data *data;
1017 struct axg_audio_reset_data *rst;
934 struct regmap *map; 1018 struct regmap *map;
935 struct resource *res; 1019 struct resource *res;
936 void __iomem *regs; 1020 void __iomem *regs;
@@ -963,29 +1047,6 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
963 return ret; 1047 return ret;
964 } 1048 }
965 1049
966 /* Register the peripheral input clock */
967 hw = meson_clk_hw_register_input(dev, "pclk", "audio_pclk", 0);
968 if (IS_ERR(hw))
969 return PTR_ERR(hw);
970
971 /* Register optional input master clocks */
972 ret = axg_register_clk_hw_inputs(dev, "mst_in",
973 AUD_MST_IN_COUNT);
974 if (ret)
975 return ret;
976
977 /* Register optional input slave sclks */
978 ret = axg_register_clk_hw_inputs(dev, "slv_sclk",
979 AUD_SLV_SCLK_COUNT);
980 if (ret)
981 return ret;
982
983 /* Register optional input slave lrclks */
984 ret = axg_register_clk_hw_inputs(dev, "slv_lrclk",
985 AUD_SLV_LRCLK_COUNT);
986 if (ret)
987 return ret;
988
989 /* Populate regmap for the regmap backed clocks */ 1050 /* Populate regmap for the regmap backed clocks */
990 for (i = 0; i < ARRAY_SIZE(aud_clk_regmaps); i++) 1051 for (i = 0; i < ARRAY_SIZE(aud_clk_regmaps); i++)
991 aud_clk_regmaps[i]->map = map; 1052 aud_clk_regmaps[i]->map = map;
@@ -1005,8 +1066,27 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
1005 } 1066 }
1006 } 1067 }
1007 1068
1008 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, 1069 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1009 data->hw_onecell_data); 1070 data->hw_onecell_data);
1071 if (ret)
1072 return ret;
1073
1074 /* Stop here if there is no reset */
1075 if (!data->reset_num)
1076 return 0;
1077
1078 rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
1079 if (!rst)
1080 return -ENOMEM;
1081
1082 rst->map = map;
1083 rst->offset = data->reset_offset;
1084 rst->rstc.nr_resets = data->reset_num;
1085 rst->rstc.ops = &axg_audio_rstc_ops;
1086 rst->rstc.of_node = dev->of_node;
1087 rst->rstc.owner = THIS_MODULE;
1088
1089 return devm_reset_controller_register(dev, &rst->rstc);
1010} 1090}
1011 1091
1012static const struct audioclk_data axg_audioclk_data = { 1092static const struct audioclk_data axg_audioclk_data = {
@@ -1015,6 +1095,8 @@ static const struct audioclk_data axg_audioclk_data = {
1015 1095
1016static const struct audioclk_data g12a_audioclk_data = { 1096static const struct audioclk_data g12a_audioclk_data = {
1017 .hw_onecell_data = &g12a_audio_hw_onecell_data, 1097 .hw_onecell_data = &g12a_audio_hw_onecell_data,
1098 .reset_offset = AUDIO_SW_RESET,
1099 .reset_num = 26,
1018}; 1100};
1019 1101
1020static const struct of_device_id clkc_match_table[] = { 1102static const struct of_device_id clkc_match_table[] = {
diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h
index 5d972d55d6c7..c00e28b2e1a9 100644
--- a/drivers/clk/meson/axg-audio.h
+++ b/drivers/clk/meson/axg-audio.h
@@ -22,6 +22,7 @@
22#define AUDIO_MCLK_F_CTRL 0x018 22#define AUDIO_MCLK_F_CTRL 0x018
23#define AUDIO_MST_PAD_CTRL0 0x01c 23#define AUDIO_MST_PAD_CTRL0 0x01c
24#define AUDIO_MST_PAD_CTRL1 0x020 24#define AUDIO_MST_PAD_CTRL1 0x020
25#define AUDIO_SW_RESET 0x024
25#define AUDIO_MST_A_SCLK_CTRL0 0x040 26#define AUDIO_MST_A_SCLK_CTRL0 0x040
26#define AUDIO_MST_A_SCLK_CTRL1 0x044 27#define AUDIO_MST_A_SCLK_CTRL1 0x044
27#define AUDIO_MST_B_SCLK_CTRL0 0x048 28#define AUDIO_MST_B_SCLK_CTRL0 0x048
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 3ddd0efc9ee0..13fc0006f63d 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -14,7 +14,6 @@
14#include <linux/of_device.h> 14#include <linux/of_device.h>
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16 16
17#include "clk-input.h"
18#include "clk-regmap.h" 17#include "clk-regmap.h"
19#include "clk-pll.h" 18#include "clk-pll.h"
20#include "clk-mpll.h" 19#include "clk-mpll.h"
@@ -59,7 +58,9 @@ static struct clk_regmap axg_fixed_pll_dco = {
59 .hw.init = &(struct clk_init_data){ 58 .hw.init = &(struct clk_init_data){
60 .name = "fixed_pll_dco", 59 .name = "fixed_pll_dco",
61 .ops = &meson_clk_pll_ro_ops, 60 .ops = &meson_clk_pll_ro_ops,
62 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 61 .parent_data = &(const struct clk_parent_data) {
62 .fw_name = "xtal",
63 },
63 .num_parents = 1, 64 .num_parents = 1,
64 }, 65 },
65}; 66};
@@ -74,7 +75,9 @@ static struct clk_regmap axg_fixed_pll = {
74 .hw.init = &(struct clk_init_data){ 75 .hw.init = &(struct clk_init_data){
75 .name = "fixed_pll", 76 .name = "fixed_pll",
76 .ops = &clk_regmap_divider_ro_ops, 77 .ops = &clk_regmap_divider_ro_ops,
77 .parent_names = (const char *[]){ "fixed_pll_dco" }, 78 .parent_hws = (const struct clk_hw *[]) {
79 &axg_fixed_pll_dco.hw
80 },
78 .num_parents = 1, 81 .num_parents = 1,
79 /* 82 /*
80 * This clock won't ever change at runtime so 83 * This clock won't ever change at runtime so
@@ -114,7 +117,9 @@ static struct clk_regmap axg_sys_pll_dco = {
114 .hw.init = &(struct clk_init_data){ 117 .hw.init = &(struct clk_init_data){
115 .name = "sys_pll_dco", 118 .name = "sys_pll_dco",
116 .ops = &meson_clk_pll_ro_ops, 119 .ops = &meson_clk_pll_ro_ops,
117 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 120 .parent_data = &(const struct clk_parent_data) {
121 .fw_name = "xtal",
122 },
118 .num_parents = 1, 123 .num_parents = 1,
119 }, 124 },
120}; 125};
@@ -129,7 +134,9 @@ static struct clk_regmap axg_sys_pll = {
129 .hw.init = &(struct clk_init_data){ 134 .hw.init = &(struct clk_init_data){
130 .name = "sys_pll", 135 .name = "sys_pll",
131 .ops = &clk_regmap_divider_ro_ops, 136 .ops = &clk_regmap_divider_ro_ops,
132 .parent_names = (const char *[]){ "sys_pll_dco" }, 137 .parent_hws = (const struct clk_hw *[]) {
138 &axg_sys_pll_dco.hw
139 },
133 .num_parents = 1, 140 .num_parents = 1,
134 .flags = CLK_SET_RATE_PARENT, 141 .flags = CLK_SET_RATE_PARENT,
135 }, 142 },
@@ -215,7 +222,9 @@ static struct clk_regmap axg_gp0_pll_dco = {
215 .hw.init = &(struct clk_init_data){ 222 .hw.init = &(struct clk_init_data){
216 .name = "gp0_pll_dco", 223 .name = "gp0_pll_dco",
217 .ops = &meson_clk_pll_ops, 224 .ops = &meson_clk_pll_ops,
218 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 225 .parent_data = &(const struct clk_parent_data) {
226 .fw_name = "xtal",
227 },
219 .num_parents = 1, 228 .num_parents = 1,
220 }, 229 },
221}; 230};
@@ -230,7 +239,9 @@ static struct clk_regmap axg_gp0_pll = {
230 .hw.init = &(struct clk_init_data){ 239 .hw.init = &(struct clk_init_data){
231 .name = "gp0_pll", 240 .name = "gp0_pll",
232 .ops = &clk_regmap_divider_ops, 241 .ops = &clk_regmap_divider_ops,
233 .parent_names = (const char *[]){ "gp0_pll_dco" }, 242 .parent_hws = (const struct clk_hw *[]) {
243 &axg_gp0_pll_dco.hw
244 },
234 .num_parents = 1, 245 .num_parents = 1,
235 .flags = CLK_SET_RATE_PARENT, 246 .flags = CLK_SET_RATE_PARENT,
236 }, 247 },
@@ -284,7 +295,9 @@ static struct clk_regmap axg_hifi_pll_dco = {
284 .hw.init = &(struct clk_init_data){ 295 .hw.init = &(struct clk_init_data){
285 .name = "hifi_pll_dco", 296 .name = "hifi_pll_dco",
286 .ops = &meson_clk_pll_ops, 297 .ops = &meson_clk_pll_ops,
287 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 298 .parent_data = &(const struct clk_parent_data) {
299 .fw_name = "xtal",
300 },
288 .num_parents = 1, 301 .num_parents = 1,
289 }, 302 },
290}; 303};
@@ -299,7 +312,9 @@ static struct clk_regmap axg_hifi_pll = {
299 .hw.init = &(struct clk_init_data){ 312 .hw.init = &(struct clk_init_data){
300 .name = "hifi_pll", 313 .name = "hifi_pll",
301 .ops = &clk_regmap_divider_ops, 314 .ops = &clk_regmap_divider_ops,
302 .parent_names = (const char *[]){ "hifi_pll_dco" }, 315 .parent_hws = (const struct clk_hw *[]) {
316 &axg_hifi_pll_dco.hw
317 },
303 .num_parents = 1, 318 .num_parents = 1,
304 .flags = CLK_SET_RATE_PARENT, 319 .flags = CLK_SET_RATE_PARENT,
305 }, 320 },
@@ -311,7 +326,7 @@ static struct clk_fixed_factor axg_fclk_div2_div = {
311 .hw.init = &(struct clk_init_data){ 326 .hw.init = &(struct clk_init_data){
312 .name = "fclk_div2_div", 327 .name = "fclk_div2_div",
313 .ops = &clk_fixed_factor_ops, 328 .ops = &clk_fixed_factor_ops,
314 .parent_names = (const char *[]){ "fixed_pll" }, 329 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
315 .num_parents = 1, 330 .num_parents = 1,
316 }, 331 },
317}; 332};
@@ -324,7 +339,9 @@ static struct clk_regmap axg_fclk_div2 = {
324 .hw.init = &(struct clk_init_data){ 339 .hw.init = &(struct clk_init_data){
325 .name = "fclk_div2", 340 .name = "fclk_div2",
326 .ops = &clk_regmap_gate_ops, 341 .ops = &clk_regmap_gate_ops,
327 .parent_names = (const char *[]){ "fclk_div2_div" }, 342 .parent_hws = (const struct clk_hw *[]) {
343 &axg_fclk_div2_div.hw
344 },
328 .num_parents = 1, 345 .num_parents = 1,
329 .flags = CLK_IS_CRITICAL, 346 .flags = CLK_IS_CRITICAL,
330 }, 347 },
@@ -336,7 +353,7 @@ static struct clk_fixed_factor axg_fclk_div3_div = {
336 .hw.init = &(struct clk_init_data){ 353 .hw.init = &(struct clk_init_data){
337 .name = "fclk_div3_div", 354 .name = "fclk_div3_div",
338 .ops = &clk_fixed_factor_ops, 355 .ops = &clk_fixed_factor_ops,
339 .parent_names = (const char *[]){ "fixed_pll" }, 356 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
340 .num_parents = 1, 357 .num_parents = 1,
341 }, 358 },
342}; 359};
@@ -349,7 +366,9 @@ static struct clk_regmap axg_fclk_div3 = {
349 .hw.init = &(struct clk_init_data){ 366 .hw.init = &(struct clk_init_data){
350 .name = "fclk_div3", 367 .name = "fclk_div3",
351 .ops = &clk_regmap_gate_ops, 368 .ops = &clk_regmap_gate_ops,
352 .parent_names = (const char *[]){ "fclk_div3_div" }, 369 .parent_hws = (const struct clk_hw *[]) {
370 &axg_fclk_div3_div.hw
371 },
353 .num_parents = 1, 372 .num_parents = 1,
354 /* 373 /*
355 * FIXME: 374 * FIXME:
@@ -372,7 +391,7 @@ static struct clk_fixed_factor axg_fclk_div4_div = {
372 .hw.init = &(struct clk_init_data){ 391 .hw.init = &(struct clk_init_data){
373 .name = "fclk_div4_div", 392 .name = "fclk_div4_div",
374 .ops = &clk_fixed_factor_ops, 393 .ops = &clk_fixed_factor_ops,
375 .parent_names = (const char *[]){ "fixed_pll" }, 394 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
376 .num_parents = 1, 395 .num_parents = 1,
377 }, 396 },
378}; 397};
@@ -385,7 +404,9 @@ static struct clk_regmap axg_fclk_div4 = {
385 .hw.init = &(struct clk_init_data){ 404 .hw.init = &(struct clk_init_data){
386 .name = "fclk_div4", 405 .name = "fclk_div4",
387 .ops = &clk_regmap_gate_ops, 406 .ops = &clk_regmap_gate_ops,
388 .parent_names = (const char *[]){ "fclk_div4_div" }, 407 .parent_hws = (const struct clk_hw *[]) {
408 &axg_fclk_div4_div.hw
409 },
389 .num_parents = 1, 410 .num_parents = 1,
390 }, 411 },
391}; 412};
@@ -396,7 +417,7 @@ static struct clk_fixed_factor axg_fclk_div5_div = {
396 .hw.init = &(struct clk_init_data){ 417 .hw.init = &(struct clk_init_data){
397 .name = "fclk_div5_div", 418 .name = "fclk_div5_div",
398 .ops = &clk_fixed_factor_ops, 419 .ops = &clk_fixed_factor_ops,
399 .parent_names = (const char *[]){ "fixed_pll" }, 420 .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
400 .num_parents = 1, 421 .num_parents = 1,
401 }, 422 },
402}; 423};
@@ -409,7 +430,9 @@ static struct clk_regmap axg_fclk_div5 = {
409 .hw.init = &(struct clk_init_data){ 430 .hw.init = &(struct clk_init_data){
410 .name = "fclk_div5", 431 .name = "fclk_div5",
411 .ops = &clk_regmap_gate_ops, 432 .ops = &clk_regmap_gate_ops,
412 .parent_names = (const char *[]){ "fclk_div5_div" }, 433 .parent_hws = (const struct clk_hw *[]) {
434 &axg_fclk_div5_div.hw
435 },
413 .num_parents = 1, 436 .num_parents = 1,
414 }, 437 },
415}; 438};
@@ -420,7 +443,9 @@ static struct clk_fixed_factor axg_fclk_div7_div = {
420 .hw.init = &(struct clk_init_data){ 443 .hw.init = &(struct clk_init_data){
421 .name = "fclk_div7_div", 444 .name = "fclk_div7_div",
422 .ops = &clk_fixed_factor_ops, 445 .ops = &clk_fixed_factor_ops,
423 .parent_names = (const char *[]){ "fixed_pll" }, 446 .parent_hws = (const struct clk_hw *[]) {
447 &axg_fixed_pll.hw
448 },
424 .num_parents = 1, 449 .num_parents = 1,
425 }, 450 },
426}; 451};
@@ -433,7 +458,9 @@ static struct clk_regmap axg_fclk_div7 = {
433 .hw.init = &(struct clk_init_data){ 458 .hw.init = &(struct clk_init_data){
434 .name = "fclk_div7", 459 .name = "fclk_div7",
435 .ops = &clk_regmap_gate_ops, 460 .ops = &clk_regmap_gate_ops,
436 .parent_names = (const char *[]){ "fclk_div7_div" }, 461 .parent_hws = (const struct clk_hw *[]) {
462 &axg_fclk_div7_div.hw
463 },
437 .num_parents = 1, 464 .num_parents = 1,
438 }, 465 },
439}; 466};
@@ -447,7 +474,9 @@ static struct clk_regmap axg_mpll_prediv = {
447 .hw.init = &(struct clk_init_data){ 474 .hw.init = &(struct clk_init_data){
448 .name = "mpll_prediv", 475 .name = "mpll_prediv",
449 .ops = &clk_regmap_divider_ro_ops, 476 .ops = &clk_regmap_divider_ro_ops,
450 .parent_names = (const char *[]){ "fixed_pll" }, 477 .parent_hws = (const struct clk_hw *[]) {
478 &axg_fixed_pll.hw
479 },
451 .num_parents = 1, 480 .num_parents = 1,
452 }, 481 },
453}; 482};
@@ -480,7 +509,9 @@ static struct clk_regmap axg_mpll0_div = {
480 .hw.init = &(struct clk_init_data){ 509 .hw.init = &(struct clk_init_data){
481 .name = "mpll0_div", 510 .name = "mpll0_div",
482 .ops = &meson_clk_mpll_ops, 511 .ops = &meson_clk_mpll_ops,
483 .parent_names = (const char *[]){ "mpll_prediv" }, 512 .parent_hws = (const struct clk_hw *[]) {
513 &axg_mpll_prediv.hw
514 },
484 .num_parents = 1, 515 .num_parents = 1,
485 }, 516 },
486}; 517};
@@ -493,7 +524,9 @@ static struct clk_regmap axg_mpll0 = {
493 .hw.init = &(struct clk_init_data){ 524 .hw.init = &(struct clk_init_data){
494 .name = "mpll0", 525 .name = "mpll0",
495 .ops = &clk_regmap_gate_ops, 526 .ops = &clk_regmap_gate_ops,
496 .parent_names = (const char *[]){ "mpll0_div" }, 527 .parent_hws = (const struct clk_hw *[]) {
528 &axg_mpll0_div.hw
529 },
497 .num_parents = 1, 530 .num_parents = 1,
498 .flags = CLK_SET_RATE_PARENT, 531 .flags = CLK_SET_RATE_PARENT,
499 }, 532 },
@@ -527,7 +560,9 @@ static struct clk_regmap axg_mpll1_div = {
527 .hw.init = &(struct clk_init_data){ 560 .hw.init = &(struct clk_init_data){
528 .name = "mpll1_div", 561 .name = "mpll1_div",
529 .ops = &meson_clk_mpll_ops, 562 .ops = &meson_clk_mpll_ops,
530 .parent_names = (const char *[]){ "mpll_prediv" }, 563 .parent_hws = (const struct clk_hw *[]) {
564 &axg_mpll_prediv.hw
565 },
531 .num_parents = 1, 566 .num_parents = 1,
532 }, 567 },
533}; 568};
@@ -540,7 +575,9 @@ static struct clk_regmap axg_mpll1 = {
540 .hw.init = &(struct clk_init_data){ 575 .hw.init = &(struct clk_init_data){
541 .name = "mpll1", 576 .name = "mpll1",
542 .ops = &clk_regmap_gate_ops, 577 .ops = &clk_regmap_gate_ops,
543 .parent_names = (const char *[]){ "mpll1_div" }, 578 .parent_hws = (const struct clk_hw *[]) {
579 &axg_mpll1_div.hw
580 },
544 .num_parents = 1, 581 .num_parents = 1,
545 .flags = CLK_SET_RATE_PARENT, 582 .flags = CLK_SET_RATE_PARENT,
546 }, 583 },
@@ -579,7 +616,9 @@ static struct clk_regmap axg_mpll2_div = {
579 .hw.init = &(struct clk_init_data){ 616 .hw.init = &(struct clk_init_data){
580 .name = "mpll2_div", 617 .name = "mpll2_div",
581 .ops = &meson_clk_mpll_ops, 618 .ops = &meson_clk_mpll_ops,
582 .parent_names = (const char *[]){ "mpll_prediv" }, 619 .parent_hws = (const struct clk_hw *[]) {
620 &axg_mpll_prediv.hw
621 },
583 .num_parents = 1, 622 .num_parents = 1,
584 }, 623 },
585}; 624};
@@ -592,7 +631,9 @@ static struct clk_regmap axg_mpll2 = {
592 .hw.init = &(struct clk_init_data){ 631 .hw.init = &(struct clk_init_data){
593 .name = "mpll2", 632 .name = "mpll2",
594 .ops = &clk_regmap_gate_ops, 633 .ops = &clk_regmap_gate_ops,
595 .parent_names = (const char *[]){ "mpll2_div" }, 634 .parent_hws = (const struct clk_hw *[]) {
635 &axg_mpll2_div.hw
636 },
596 .num_parents = 1, 637 .num_parents = 1,
597 .flags = CLK_SET_RATE_PARENT, 638 .flags = CLK_SET_RATE_PARENT,
598 }, 639 },
@@ -626,7 +667,9 @@ static struct clk_regmap axg_mpll3_div = {
626 .hw.init = &(struct clk_init_data){ 667 .hw.init = &(struct clk_init_data){
627 .name = "mpll3_div", 668 .name = "mpll3_div",
628 .ops = &meson_clk_mpll_ops, 669 .ops = &meson_clk_mpll_ops,
629 .parent_names = (const char *[]){ "mpll_prediv" }, 670 .parent_hws = (const struct clk_hw *[]) {
671 &axg_mpll_prediv.hw
672 },
630 .num_parents = 1, 673 .num_parents = 1,
631 }, 674 },
632}; 675};
@@ -639,7 +682,9 @@ static struct clk_regmap axg_mpll3 = {
639 .hw.init = &(struct clk_init_data){ 682 .hw.init = &(struct clk_init_data){
640 .name = "mpll3", 683 .name = "mpll3",
641 .ops = &clk_regmap_gate_ops, 684 .ops = &clk_regmap_gate_ops,
642 .parent_names = (const char *[]){ "mpll3_div" }, 685 .parent_hws = (const struct clk_hw *[]) {
686 &axg_mpll3_div.hw
687 },
643 .num_parents = 1, 688 .num_parents = 1,
644 .flags = CLK_SET_RATE_PARENT, 689 .flags = CLK_SET_RATE_PARENT,
645 }, 690 },
@@ -702,7 +747,9 @@ static struct clk_regmap axg_pcie_pll_dco = {
702 .hw.init = &(struct clk_init_data){ 747 .hw.init = &(struct clk_init_data){
703 .name = "pcie_pll_dco", 748 .name = "pcie_pll_dco",
704 .ops = &meson_clk_pll_ops, 749 .ops = &meson_clk_pll_ops,
705 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 750 .parent_data = &(const struct clk_parent_data) {
751 .fw_name = "xtal",
752 },
706 .num_parents = 1, 753 .num_parents = 1,
707 }, 754 },
708}; 755};
@@ -717,7 +764,9 @@ static struct clk_regmap axg_pcie_pll_od = {
717 .hw.init = &(struct clk_init_data){ 764 .hw.init = &(struct clk_init_data){
718 .name = "pcie_pll_od", 765 .name = "pcie_pll_od",
719 .ops = &clk_regmap_divider_ops, 766 .ops = &clk_regmap_divider_ops,
720 .parent_names = (const char *[]){ "pcie_pll_dco" }, 767 .parent_hws = (const struct clk_hw *[]) {
768 &axg_pcie_pll_dco.hw
769 },
721 .num_parents = 1, 770 .num_parents = 1,
722 .flags = CLK_SET_RATE_PARENT, 771 .flags = CLK_SET_RATE_PARENT,
723 }, 772 },
@@ -733,7 +782,9 @@ static struct clk_regmap axg_pcie_pll = {
733 .hw.init = &(struct clk_init_data){ 782 .hw.init = &(struct clk_init_data){
734 .name = "pcie_pll", 783 .name = "pcie_pll",
735 .ops = &clk_regmap_divider_ops, 784 .ops = &clk_regmap_divider_ops,
736 .parent_names = (const char *[]){ "pcie_pll_od" }, 785 .parent_hws = (const struct clk_hw *[]) {
786 &axg_pcie_pll_od.hw
787 },
737 .num_parents = 1, 788 .num_parents = 1,
738 .flags = CLK_SET_RATE_PARENT, 789 .flags = CLK_SET_RATE_PARENT,
739 }, 790 },
@@ -750,7 +801,7 @@ static struct clk_regmap axg_pcie_mux = {
750 .hw.init = &(struct clk_init_data){ 801 .hw.init = &(struct clk_init_data){
751 .name = "pcie_mux", 802 .name = "pcie_mux",
752 .ops = &clk_regmap_mux_ops, 803 .ops = &clk_regmap_mux_ops,
753 .parent_names = (const char *[]){ "pcie_pll" }, 804 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_pll.hw },
754 .num_parents = 1, 805 .num_parents = 1,
755 .flags = CLK_SET_RATE_PARENT, 806 .flags = CLK_SET_RATE_PARENT,
756 }, 807 },
@@ -767,7 +818,7 @@ static struct clk_regmap axg_pcie_ref = {
767 .hw.init = &(struct clk_init_data){ 818 .hw.init = &(struct clk_init_data){
768 .name = "pcie_ref", 819 .name = "pcie_ref",
769 .ops = &clk_regmap_mux_ops, 820 .ops = &clk_regmap_mux_ops,
770 .parent_names = (const char *[]){ "pcie_mux" }, 821 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_mux.hw },
771 .num_parents = 1, 822 .num_parents = 1,
772 .flags = CLK_SET_RATE_PARENT, 823 .flags = CLK_SET_RATE_PARENT,
773 }, 824 },
@@ -781,7 +832,7 @@ static struct clk_regmap axg_pcie_cml_en0 = {
781 .hw.init = &(struct clk_init_data) { 832 .hw.init = &(struct clk_init_data) {
782 .name = "pcie_cml_en0", 833 .name = "pcie_cml_en0",
783 .ops = &clk_regmap_gate_ops, 834 .ops = &clk_regmap_gate_ops,
784 .parent_names = (const char *[]){ "pcie_ref" }, 835 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
785 .num_parents = 1, 836 .num_parents = 1,
786 .flags = CLK_SET_RATE_PARENT, 837 .flags = CLK_SET_RATE_PARENT,
787 838
@@ -796,16 +847,21 @@ static struct clk_regmap axg_pcie_cml_en1 = {
796 .hw.init = &(struct clk_init_data) { 847 .hw.init = &(struct clk_init_data) {
797 .name = "pcie_cml_en1", 848 .name = "pcie_cml_en1",
798 .ops = &clk_regmap_gate_ops, 849 .ops = &clk_regmap_gate_ops,
799 .parent_names = (const char *[]){ "pcie_ref" }, 850 .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
800 .num_parents = 1, 851 .num_parents = 1,
801 .flags = CLK_SET_RATE_PARENT, 852 .flags = CLK_SET_RATE_PARENT,
802 }, 853 },
803}; 854};
804 855
805static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 856static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
806static const char * const clk81_parent_names[] = { 857static const struct clk_parent_data clk81_parent_data[] = {
807 IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", 858 { .fw_name = "xtal", },
808 "fclk_div3", "fclk_div5" 859 { .hw = &axg_fclk_div7.hw },
860 { .hw = &axg_mpll1.hw },
861 { .hw = &axg_mpll2.hw },
862 { .hw = &axg_fclk_div4.hw },
863 { .hw = &axg_fclk_div3.hw },
864 { .hw = &axg_fclk_div5.hw },
809}; 865};
810 866
811static struct clk_regmap axg_mpeg_clk_sel = { 867static struct clk_regmap axg_mpeg_clk_sel = {
@@ -818,8 +874,8 @@ static struct clk_regmap axg_mpeg_clk_sel = {
818 .hw.init = &(struct clk_init_data){ 874 .hw.init = &(struct clk_init_data){
819 .name = "mpeg_clk_sel", 875 .name = "mpeg_clk_sel",
820 .ops = &clk_regmap_mux_ro_ops, 876 .ops = &clk_regmap_mux_ro_ops,
821 .parent_names = clk81_parent_names, 877 .parent_data = clk81_parent_data,
822 .num_parents = ARRAY_SIZE(clk81_parent_names), 878 .num_parents = ARRAY_SIZE(clk81_parent_data),
823 }, 879 },
824}; 880};
825 881
@@ -832,7 +888,9 @@ static struct clk_regmap axg_mpeg_clk_div = {
832 .hw.init = &(struct clk_init_data){ 888 .hw.init = &(struct clk_init_data){
833 .name = "mpeg_clk_div", 889 .name = "mpeg_clk_div",
834 .ops = &clk_regmap_divider_ops, 890 .ops = &clk_regmap_divider_ops,
835 .parent_names = (const char *[]){ "mpeg_clk_sel" }, 891 .parent_hws = (const struct clk_hw *[]) {
892 &axg_mpeg_clk_sel.hw
893 },
836 .num_parents = 1, 894 .num_parents = 1,
837 .flags = CLK_SET_RATE_PARENT, 895 .flags = CLK_SET_RATE_PARENT,
838 }, 896 },
@@ -846,15 +904,20 @@ static struct clk_regmap axg_clk81 = {
846 .hw.init = &(struct clk_init_data){ 904 .hw.init = &(struct clk_init_data){
847 .name = "clk81", 905 .name = "clk81",
848 .ops = &clk_regmap_gate_ops, 906 .ops = &clk_regmap_gate_ops,
849 .parent_names = (const char *[]){ "mpeg_clk_div" }, 907 .parent_hws = (const struct clk_hw *[]) {
908 &axg_mpeg_clk_div.hw
909 },
850 .num_parents = 1, 910 .num_parents = 1,
851 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), 911 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
852 }, 912 },
853}; 913};
854 914
855static const char * const axg_sd_emmc_clk0_parent_names[] = { 915static const struct clk_parent_data axg_sd_emmc_clk0_parent_data[] = {
856 IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7", 916 { .fw_name = "xtal", },
857 917 { .hw = &axg_fclk_div2.hw },
918 { .hw = &axg_fclk_div3.hw },
919 { .hw = &axg_fclk_div5.hw },
920 { .hw = &axg_fclk_div7.hw },
858 /* 921 /*
859 * Following these parent clocks, we should also have had mpll2, mpll3 922 * Following these parent clocks, we should also have had mpll2, mpll3
860 * and gp0_pll but these clocks are too precious to be used here. All 923 * and gp0_pll but these clocks are too precious to be used here. All
@@ -873,8 +936,8 @@ static struct clk_regmap axg_sd_emmc_b_clk0_sel = {
873 .hw.init = &(struct clk_init_data) { 936 .hw.init = &(struct clk_init_data) {
874 .name = "sd_emmc_b_clk0_sel", 937 .name = "sd_emmc_b_clk0_sel",
875 .ops = &clk_regmap_mux_ops, 938 .ops = &clk_regmap_mux_ops,
876 .parent_names = axg_sd_emmc_clk0_parent_names, 939 .parent_data = axg_sd_emmc_clk0_parent_data,
877 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names), 940 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
878 .flags = CLK_SET_RATE_PARENT, 941 .flags = CLK_SET_RATE_PARENT,
879 }, 942 },
880}; 943};
@@ -889,7 +952,9 @@ static struct clk_regmap axg_sd_emmc_b_clk0_div = {
889 .hw.init = &(struct clk_init_data) { 952 .hw.init = &(struct clk_init_data) {
890 .name = "sd_emmc_b_clk0_div", 953 .name = "sd_emmc_b_clk0_div",
891 .ops = &clk_regmap_divider_ops, 954 .ops = &clk_regmap_divider_ops,
892 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, 955 .parent_hws = (const struct clk_hw *[]) {
956 &axg_sd_emmc_b_clk0_sel.hw
957 },
893 .num_parents = 1, 958 .num_parents = 1,
894 .flags = CLK_SET_RATE_PARENT, 959 .flags = CLK_SET_RATE_PARENT,
895 }, 960 },
@@ -903,7 +968,9 @@ static struct clk_regmap axg_sd_emmc_b_clk0 = {
903 .hw.init = &(struct clk_init_data){ 968 .hw.init = &(struct clk_init_data){
904 .name = "sd_emmc_b_clk0", 969 .name = "sd_emmc_b_clk0",
905 .ops = &clk_regmap_gate_ops, 970 .ops = &clk_regmap_gate_ops,
906 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" }, 971 .parent_hws = (const struct clk_hw *[]) {
972 &axg_sd_emmc_b_clk0_div.hw
973 },
907 .num_parents = 1, 974 .num_parents = 1,
908 .flags = CLK_SET_RATE_PARENT, 975 .flags = CLK_SET_RATE_PARENT,
909 }, 976 },
@@ -919,8 +986,8 @@ static struct clk_regmap axg_sd_emmc_c_clk0_sel = {
919 .hw.init = &(struct clk_init_data) { 986 .hw.init = &(struct clk_init_data) {
920 .name = "sd_emmc_c_clk0_sel", 987 .name = "sd_emmc_c_clk0_sel",
921 .ops = &clk_regmap_mux_ops, 988 .ops = &clk_regmap_mux_ops,
922 .parent_names = axg_sd_emmc_clk0_parent_names, 989 .parent_data = axg_sd_emmc_clk0_parent_data,
923 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names), 990 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
924 .flags = CLK_SET_RATE_PARENT, 991 .flags = CLK_SET_RATE_PARENT,
925 }, 992 },
926}; 993};
@@ -935,7 +1002,9 @@ static struct clk_regmap axg_sd_emmc_c_clk0_div = {
935 .hw.init = &(struct clk_init_data) { 1002 .hw.init = &(struct clk_init_data) {
936 .name = "sd_emmc_c_clk0_div", 1003 .name = "sd_emmc_c_clk0_div",
937 .ops = &clk_regmap_divider_ops, 1004 .ops = &clk_regmap_divider_ops,
938 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, 1005 .parent_hws = (const struct clk_hw *[]) {
1006 &axg_sd_emmc_c_clk0_sel.hw
1007 },
939 .num_parents = 1, 1008 .num_parents = 1,
940 .flags = CLK_SET_RATE_PARENT, 1009 .flags = CLK_SET_RATE_PARENT,
941 }, 1010 },
@@ -949,7 +1018,9 @@ static struct clk_regmap axg_sd_emmc_c_clk0 = {
949 .hw.init = &(struct clk_init_data){ 1018 .hw.init = &(struct clk_init_data){
950 .name = "sd_emmc_c_clk0", 1019 .name = "sd_emmc_c_clk0",
951 .ops = &clk_regmap_gate_ops, 1020 .ops = &clk_regmap_gate_ops,
952 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" }, 1021 .parent_hws = (const struct clk_hw *[]) {
1022 &axg_sd_emmc_c_clk0_div.hw
1023 },
953 .num_parents = 1, 1024 .num_parents = 1,
954 .flags = CLK_SET_RATE_PARENT, 1025 .flags = CLK_SET_RATE_PARENT,
955 }, 1026 },
@@ -957,9 +1028,18 @@ static struct clk_regmap axg_sd_emmc_c_clk0 = {
957 1028
958static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8, 1029static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
959 9, 10, 11, 13, 14, }; 1030 9, 10, 11, 13, 14, };
960static const char * const gen_clk_parent_names[] = { 1031static const struct clk_parent_data gen_clk_parent_data[] = {
961 IN_PREFIX "xtal", "hifi_pll", "mpll0", "mpll1", "mpll2", "mpll3", 1032 { .fw_name = "xtal", },
962 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll", 1033 { .hw = &axg_hifi_pll.hw },
1034 { .hw = &axg_mpll0.hw },
1035 { .hw = &axg_mpll1.hw },
1036 { .hw = &axg_mpll2.hw },
1037 { .hw = &axg_mpll3.hw },
1038 { .hw = &axg_fclk_div4.hw },
1039 { .hw = &axg_fclk_div3.hw },
1040 { .hw = &axg_fclk_div5.hw },
1041 { .hw = &axg_fclk_div7.hw },
1042 { .hw = &axg_gp0_pll.hw },
963}; 1043};
964 1044
965static struct clk_regmap axg_gen_clk_sel = { 1045static struct clk_regmap axg_gen_clk_sel = {
@@ -978,8 +1058,8 @@ static struct clk_regmap axg_gen_clk_sel = {
978 * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4, 1058 * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,
979 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll 1059 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
980 */ 1060 */
981 .parent_names = gen_clk_parent_names, 1061 .parent_data = gen_clk_parent_data,
982 .num_parents = ARRAY_SIZE(gen_clk_parent_names), 1062 .num_parents = ARRAY_SIZE(gen_clk_parent_data),
983 }, 1063 },
984}; 1064};
985 1065
@@ -992,7 +1072,9 @@ static struct clk_regmap axg_gen_clk_div = {
992 .hw.init = &(struct clk_init_data){ 1072 .hw.init = &(struct clk_init_data){
993 .name = "gen_clk_div", 1073 .name = "gen_clk_div",
994 .ops = &clk_regmap_divider_ops, 1074 .ops = &clk_regmap_divider_ops,
995 .parent_names = (const char *[]){ "gen_clk_sel" }, 1075 .parent_hws = (const struct clk_hw *[]) {
1076 &axg_gen_clk_sel.hw
1077 },
996 .num_parents = 1, 1078 .num_parents = 1,
997 .flags = CLK_SET_RATE_PARENT, 1079 .flags = CLK_SET_RATE_PARENT,
998 }, 1080 },
@@ -1006,12 +1088,17 @@ static struct clk_regmap axg_gen_clk = {
1006 .hw.init = &(struct clk_init_data){ 1088 .hw.init = &(struct clk_init_data){
1007 .name = "gen_clk", 1089 .name = "gen_clk",
1008 .ops = &clk_regmap_gate_ops, 1090 .ops = &clk_regmap_gate_ops,
1009 .parent_names = (const char *[]){ "gen_clk_div" }, 1091 .parent_hws = (const struct clk_hw *[]) {
1092 &axg_gen_clk_div.hw
1093 },
1010 .num_parents = 1, 1094 .num_parents = 1,
1011 .flags = CLK_SET_RATE_PARENT, 1095 .flags = CLK_SET_RATE_PARENT,
1012 }, 1096 },
1013}; 1097};
1014 1098
1099#define MESON_GATE(_name, _reg, _bit) \
1100 MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw)
1101
1015/* Everything Else (EE) domain gates */ 1102/* Everything Else (EE) domain gates */
1016static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0); 1103static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
1017static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2); 1104static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
diff --git a/drivers/clk/meson/clk-cpu-dyndiv.c b/drivers/clk/meson/clk-cpu-dyndiv.c
new file mode 100644
index 000000000000..36976927fe82
--- /dev/null
+++ b/drivers/clk/meson/clk-cpu-dyndiv.c
@@ -0,0 +1,73 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2019 BayLibre, SAS.
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/module.h>
9
10#include "clk-regmap.h"
11#include "clk-cpu-dyndiv.h"
12
13static inline struct meson_clk_cpu_dyndiv_data *
14meson_clk_cpu_dyndiv_data(struct clk_regmap *clk)
15{
16 return (struct meson_clk_cpu_dyndiv_data *)clk->data;
17}
18
19static unsigned long meson_clk_cpu_dyndiv_recalc_rate(struct clk_hw *hw,
20 unsigned long prate)
21{
22 struct clk_regmap *clk = to_clk_regmap(hw);
23 struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);
24
25 return divider_recalc_rate(hw, prate,
26 meson_parm_read(clk->map, &data->div),
27 NULL, 0, data->div.width);
28}
29
30static long meson_clk_cpu_dyndiv_round_rate(struct clk_hw *hw,
31 unsigned long rate,
32 unsigned long *prate)
33{
34 struct clk_regmap *clk = to_clk_regmap(hw);
35 struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);
36
37 return divider_round_rate(hw, rate, prate, NULL, data->div.width, 0);
38}
39
40static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate,
41 unsigned long parent_rate)
42{
43 struct clk_regmap *clk = to_clk_regmap(hw);
44 struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);
45 unsigned int val;
46 int ret;
47
48 ret = divider_get_val(rate, parent_rate, NULL, data->div.width, 0);
49 if (ret < 0)
50 return ret;
51
52 val = (unsigned int)ret << data->div.shift;
53
54 /* Write the SYS_CPU_DYN_ENABLE bit before changing the divider */
55 meson_parm_write(clk->map, &data->dyn, 1);
56
57 /* Update the divider while removing the SYS_CPU_DYN_ENABLE bit */
58 return regmap_update_bits(clk->map, data->div.reg_off,
59 SETPMASK(data->div.width, data->div.shift) |
60 SETPMASK(data->dyn.width, data->dyn.shift),
61 val);
62};
63
64const struct clk_ops meson_clk_cpu_dyndiv_ops = {
65 .recalc_rate = meson_clk_cpu_dyndiv_recalc_rate,
66 .round_rate = meson_clk_cpu_dyndiv_round_rate,
67 .set_rate = meson_clk_cpu_dyndiv_set_rate,
68};
69EXPORT_SYMBOL_GPL(meson_clk_cpu_dyndiv_ops);
70
71MODULE_DESCRIPTION("Amlogic CPU Dynamic Clock divider");
72MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
73MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/meson/clk-cpu-dyndiv.h b/drivers/clk/meson/clk-cpu-dyndiv.h
new file mode 100644
index 000000000000..f4908404792e
--- /dev/null
+++ b/drivers/clk/meson/clk-cpu-dyndiv.h
@@ -0,0 +1,20 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2019 BayLibre, SAS.
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 */
6
7#ifndef __MESON_CLK_CPU_DYNDIV_H
8#define __MESON_CLK_CPU_DYNDIV_H
9
10#include <linux/clk-provider.h>
11#include "parm.h"
12
13struct meson_clk_cpu_dyndiv_data {
14 struct parm div;
15 struct parm dyn;
16};
17
18extern const struct clk_ops meson_clk_cpu_dyndiv_ops;
19
20#endif /* __MESON_CLK_CPU_DYNDIV_H */
diff --git a/drivers/clk/meson/clk-input.c b/drivers/clk/meson/clk-input.c
deleted file mode 100644
index 086226e9dba6..000000000000
--- a/drivers/clk/meson/clk-input.c
+++ /dev/null
@@ -1,49 +0,0 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (c) 2018 BayLibre, SAS.
4 * Author: Jerome Brunet <jbrunet@baylibre.com>
5 */
6
7#include <linux/clk.h>
8#include <linux/clk-provider.h>
9#include <linux/device.h>
10#include <linux/module.h>
11#include "clk-input.h"
12
13static const struct clk_ops meson_clk_no_ops = {};
14
15struct clk_hw *meson_clk_hw_register_input(struct device *dev,
16 const char *of_name,
17 const char *clk_name,
18 unsigned long flags)
19{
20 struct clk *parent_clk = devm_clk_get(dev, of_name);
21 struct clk_init_data init;
22 const char *parent_name;
23 struct clk_hw *hw;
24 int ret;
25
26 if (IS_ERR(parent_clk))
27 return (struct clk_hw *)parent_clk;
28
29 hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL);
30 if (!hw)
31 return ERR_PTR(-ENOMEM);
32
33 parent_name = __clk_get_name(parent_clk);
34 init.name = clk_name;
35 init.ops = &meson_clk_no_ops;
36 init.flags = flags;
37 init.parent_names = &parent_name;
38 init.num_parents = 1;
39 hw->init = &init;
40
41 ret = devm_clk_hw_register(dev, hw);
42
43 return ret ? ERR_PTR(ret) : hw;
44}
45EXPORT_SYMBOL_GPL(meson_clk_hw_register_input);
46
47MODULE_DESCRIPTION("Amlogic clock input helper");
48MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
49MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/meson/clk-input.h b/drivers/clk/meson/clk-input.h
deleted file mode 100644
index 4a541b9685a6..000000000000
--- a/drivers/clk/meson/clk-input.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2019 BayLibre, SAS.
4 * Author: Jerome Brunet <jbrunet@baylibre.com>
5 */
6
7#ifndef __MESON_CLK_INPUT_H
8#define __MESON_CLK_INPUT_H
9
10#include <linux/clk-provider.h>
11
12struct device;
13
14struct clk_hw *meson_clk_hw_register_input(struct device *dev,
15 const char *of_name,
16 const char *clk_name,
17 unsigned long flags);
18
19#endif /* __MESON_CLK_INPUT_H */
diff --git a/drivers/clk/meson/clk-regmap.h b/drivers/clk/meson/clk-regmap.h
index 1dd0abe3ba91..c4a39604cffd 100644
--- a/drivers/clk/meson/clk-regmap.h
+++ b/drivers/clk/meson/clk-regmap.h
@@ -111,7 +111,7 @@ clk_get_regmap_mux_data(struct clk_regmap *clk)
111extern const struct clk_ops clk_regmap_mux_ops; 111extern const struct clk_ops clk_regmap_mux_ops;
112extern const struct clk_ops clk_regmap_mux_ro_ops; 112extern const struct clk_ops clk_regmap_mux_ro_ops;
113 113
114#define __MESON_GATE(_name, _reg, _bit, _ops) \ 114#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \
115struct clk_regmap _name = { \ 115struct clk_regmap _name = { \
116 .data = &(struct clk_regmap_gate_data){ \ 116 .data = &(struct clk_regmap_gate_data){ \
117 .offset = (_reg), \ 117 .offset = (_reg), \
@@ -120,15 +120,15 @@ struct clk_regmap _name = { \
120 .hw.init = &(struct clk_init_data) { \ 120 .hw.init = &(struct clk_init_data) { \
121 .name = #_name, \ 121 .name = #_name, \
122 .ops = _ops, \ 122 .ops = _ops, \
123 .parent_names = (const char *[]){ "clk81" }, \ 123 .parent_hws = (const struct clk_hw *[]) { _pname }, \
124 .num_parents = 1, \ 124 .num_parents = 1, \
125 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ 125 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
126 }, \ 126 }, \
127} 127}
128 128
129#define MESON_GATE(_name, _reg, _bit) \ 129#define MESON_PCLK(_name, _reg, _bit, _pname) \
130 __MESON_GATE(_name, _reg, _bit, &clk_regmap_gate_ops) 130 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname)
131 131
132#define MESON_GATE_RO(_name, _reg, _bit) \ 132#define MESON_PCLK_RO(_name, _reg, _bit, _pname) \
133 __MESON_GATE(_name, _reg, _bit, &clk_regmap_gate_ro_ops) 133 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname)
134#endif /* __CLK_REGMAP_H */ 134#endif /* __CLK_REGMAP_H */
diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c
index 1994e735396b..62499563e4f5 100644
--- a/drivers/clk/meson/g12a-aoclk.c
+++ b/drivers/clk/meson/g12a-aoclk.c
@@ -18,8 +18,6 @@
18#include "clk-regmap.h" 18#include "clk-regmap.h"
19#include "clk-dualdiv.h" 19#include "clk-dualdiv.h"
20 20
21#define IN_PREFIX "ao-in-"
22
23/* 21/*
24 * AO Configuration Clock registers offsets 22 * AO Configuration Clock registers offsets
25 * Register offsets from the data sheet must be multiplied by 4. 23 * Register offsets from the data sheet must be multiplied by 4.
@@ -51,7 +49,9 @@ static struct clk_regmap g12a_aoclk_##_name = { \
51 .hw.init = &(struct clk_init_data) { \ 49 .hw.init = &(struct clk_init_data) { \
52 .name = "g12a_ao_" #_name, \ 50 .name = "g12a_ao_" #_name, \
53 .ops = &clk_regmap_gate_ops, \ 51 .ops = &clk_regmap_gate_ops, \
54 .parent_names = (const char *[]){ IN_PREFIX "mpeg-clk" }, \ 52 .parent_data = &(const struct clk_parent_data) { \
53 .fw_name = "mpeg-clk", \
54 }, \
55 .num_parents = 1, \ 55 .num_parents = 1, \
56 .flags = CLK_IGNORE_UNUSED, \ 56 .flags = CLK_IGNORE_UNUSED, \
57 }, \ 57 }, \
@@ -81,7 +81,9 @@ static struct clk_regmap g12a_aoclk_cts_oscin = {
81 .hw.init = &(struct clk_init_data){ 81 .hw.init = &(struct clk_init_data){
82 .name = "cts_oscin", 82 .name = "cts_oscin",
83 .ops = &clk_regmap_gate_ro_ops, 83 .ops = &clk_regmap_gate_ro_ops,
84 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 84 .parent_data = &(const struct clk_parent_data) {
85 .fw_name = "xtal",
86 },
85 .num_parents = 1, 87 .num_parents = 1,
86 }, 88 },
87}; 89};
@@ -106,7 +108,9 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_pre = {
106 .hw.init = &(struct clk_init_data){ 108 .hw.init = &(struct clk_init_data){
107 .name = "g12a_ao_32k_by_oscin_pre", 109 .name = "g12a_ao_32k_by_oscin_pre",
108 .ops = &clk_regmap_gate_ops, 110 .ops = &clk_regmap_gate_ops,
109 .parent_names = (const char *[]){ "cts_oscin" }, 111 .parent_hws = (const struct clk_hw *[]) {
112 &g12a_aoclk_cts_oscin.hw
113 },
110 .num_parents = 1, 114 .num_parents = 1,
111 }, 115 },
112}; 116};
@@ -143,7 +147,9 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_div = {
143 .hw.init = &(struct clk_init_data){ 147 .hw.init = &(struct clk_init_data){
144 .name = "g12a_ao_32k_by_oscin_div", 148 .name = "g12a_ao_32k_by_oscin_div",
145 .ops = &meson_clk_dualdiv_ops, 149 .ops = &meson_clk_dualdiv_ops,
146 .parent_names = (const char *[]){ "g12a_ao_32k_by_oscin_pre" }, 150 .parent_hws = (const struct clk_hw *[]) {
151 &g12a_aoclk_32k_by_oscin_pre.hw
152 },
147 .num_parents = 1, 153 .num_parents = 1,
148 }, 154 },
149}; 155};
@@ -158,8 +164,10 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_sel = {
158 .hw.init = &(struct clk_init_data){ 164 .hw.init = &(struct clk_init_data){
159 .name = "g12a_ao_32k_by_oscin_sel", 165 .name = "g12a_ao_32k_by_oscin_sel",
160 .ops = &clk_regmap_mux_ops, 166 .ops = &clk_regmap_mux_ops,
161 .parent_names = (const char *[]){ "g12a_ao_32k_by_oscin_div", 167 .parent_hws = (const struct clk_hw *[]) {
162 "g12a_ao_32k_by_oscin_pre" }, 168 &g12a_aoclk_32k_by_oscin_div.hw,
169 &g12a_aoclk_32k_by_oscin_pre.hw,
170 },
163 .num_parents = 2, 171 .num_parents = 2,
164 .flags = CLK_SET_RATE_PARENT, 172 .flags = CLK_SET_RATE_PARENT,
165 }, 173 },
@@ -173,7 +181,9 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin = {
173 .hw.init = &(struct clk_init_data){ 181 .hw.init = &(struct clk_init_data){
174 .name = "g12a_ao_32k_by_oscin", 182 .name = "g12a_ao_32k_by_oscin",
175 .ops = &clk_regmap_gate_ops, 183 .ops = &clk_regmap_gate_ops,
176 .parent_names = (const char *[]){ "g12a_ao_32k_by_oscin_sel" }, 184 .parent_hws = (const struct clk_hw *[]) {
185 &g12a_aoclk_32k_by_oscin_sel.hw
186 },
177 .num_parents = 1, 187 .num_parents = 1,
178 .flags = CLK_SET_RATE_PARENT, 188 .flags = CLK_SET_RATE_PARENT,
179 }, 189 },
@@ -189,7 +199,9 @@ static struct clk_regmap g12a_aoclk_cec_pre = {
189 .hw.init = &(struct clk_init_data){ 199 .hw.init = &(struct clk_init_data){
190 .name = "g12a_ao_cec_pre", 200 .name = "g12a_ao_cec_pre",
191 .ops = &clk_regmap_gate_ops, 201 .ops = &clk_regmap_gate_ops,
192 .parent_names = (const char *[]){ "cts_oscin" }, 202 .parent_hws = (const struct clk_hw *[]) {
203 &g12a_aoclk_cts_oscin.hw
204 },
193 .num_parents = 1, 205 .num_parents = 1,
194 }, 206 },
195}; 207};
@@ -226,7 +238,9 @@ static struct clk_regmap g12a_aoclk_cec_div = {
226 .hw.init = &(struct clk_init_data){ 238 .hw.init = &(struct clk_init_data){
227 .name = "g12a_ao_cec_div", 239 .name = "g12a_ao_cec_div",
228 .ops = &meson_clk_dualdiv_ops, 240 .ops = &meson_clk_dualdiv_ops,
229 .parent_names = (const char *[]){ "g12a_ao_cec_pre" }, 241 .parent_hws = (const struct clk_hw *[]) {
242 &g12a_aoclk_cec_pre.hw
243 },
230 .num_parents = 1, 244 .num_parents = 1,
231 }, 245 },
232}; 246};
@@ -241,8 +255,10 @@ static struct clk_regmap g12a_aoclk_cec_sel = {
241 .hw.init = &(struct clk_init_data){ 255 .hw.init = &(struct clk_init_data){
242 .name = "g12a_ao_cec_sel", 256 .name = "g12a_ao_cec_sel",
243 .ops = &clk_regmap_mux_ops, 257 .ops = &clk_regmap_mux_ops,
244 .parent_names = (const char *[]){ "g12a_ao_cec_div", 258 .parent_hws = (const struct clk_hw *[]) {
245 "g12a_ao_cec_pre" }, 259 &g12a_aoclk_cec_div.hw,
260 &g12a_aoclk_cec_pre.hw,
261 },
246 .num_parents = 2, 262 .num_parents = 2,
247 .flags = CLK_SET_RATE_PARENT, 263 .flags = CLK_SET_RATE_PARENT,
248 }, 264 },
@@ -256,7 +272,9 @@ static struct clk_regmap g12a_aoclk_cec = {
256 .hw.init = &(struct clk_init_data){ 272 .hw.init = &(struct clk_init_data){
257 .name = "g12a_ao_cec", 273 .name = "g12a_ao_cec",
258 .ops = &clk_regmap_gate_ops, 274 .ops = &clk_regmap_gate_ops,
259 .parent_names = (const char *[]){ "g12a_ao_cec_sel" }, 275 .parent_hws = (const struct clk_hw *[]) {
276 &g12a_aoclk_cec_sel.hw
277 },
260 .num_parents = 1, 278 .num_parents = 1,
261 .flags = CLK_SET_RATE_PARENT, 279 .flags = CLK_SET_RATE_PARENT,
262 }, 280 },
@@ -272,8 +290,10 @@ static struct clk_regmap g12a_aoclk_cts_rtc_oscin = {
272 .hw.init = &(struct clk_init_data){ 290 .hw.init = &(struct clk_init_data){
273 .name = "g12a_ao_cts_rtc_oscin", 291 .name = "g12a_ao_cts_rtc_oscin",
274 .ops = &clk_regmap_mux_ops, 292 .ops = &clk_regmap_mux_ops,
275 .parent_names = (const char *[]){ "g12a_ao_32k_by_oscin", 293 .parent_data = (const struct clk_parent_data []) {
276 IN_PREFIX "ext_32k-0" }, 294 { .hw = &g12a_aoclk_32k_by_oscin.hw },
295 { .fw_name = "ext-32k-0", },
296 },
277 .num_parents = 2, 297 .num_parents = 2,
278 .flags = CLK_SET_RATE_PARENT, 298 .flags = CLK_SET_RATE_PARENT,
279 }, 299 },
@@ -289,8 +309,10 @@ static struct clk_regmap g12a_aoclk_clk81 = {
289 .hw.init = &(struct clk_init_data){ 309 .hw.init = &(struct clk_init_data){
290 .name = "g12a_ao_clk81", 310 .name = "g12a_ao_clk81",
291 .ops = &clk_regmap_mux_ro_ops, 311 .ops = &clk_regmap_mux_ro_ops,
292 .parent_names = (const char *[]){ IN_PREFIX "mpeg-clk", 312 .parent_data = (const struct clk_parent_data []) {
293 "g12a_ao_cts_rtc_oscin"}, 313 { .fw_name = "mpeg-clk", },
314 { .hw = &g12a_aoclk_cts_rtc_oscin.hw },
315 },
294 .num_parents = 2, 316 .num_parents = 2,
295 .flags = CLK_SET_RATE_PARENT, 317 .flags = CLK_SET_RATE_PARENT,
296 }, 318 },
@@ -305,8 +327,10 @@ static struct clk_regmap g12a_aoclk_saradc_mux = {
305 .hw.init = &(struct clk_init_data){ 327 .hw.init = &(struct clk_init_data){
306 .name = "g12a_ao_saradc_mux", 328 .name = "g12a_ao_saradc_mux",
307 .ops = &clk_regmap_mux_ops, 329 .ops = &clk_regmap_mux_ops,
308 .parent_names = (const char *[]){ IN_PREFIX "xtal", 330 .parent_data = (const struct clk_parent_data []) {
309 "g12a_ao_clk81" }, 331 { .fw_name = "xtal", },
332 { .hw = &g12a_aoclk_clk81.hw },
333 },
310 .num_parents = 2, 334 .num_parents = 2,
311 }, 335 },
312}; 336};
@@ -320,7 +344,9 @@ static struct clk_regmap g12a_aoclk_saradc_div = {
320 .hw.init = &(struct clk_init_data){ 344 .hw.init = &(struct clk_init_data){
321 .name = "g12a_ao_saradc_div", 345 .name = "g12a_ao_saradc_div",
322 .ops = &clk_regmap_divider_ops, 346 .ops = &clk_regmap_divider_ops,
323 .parent_names = (const char *[]){ "g12a_ao_saradc_mux" }, 347 .parent_hws = (const struct clk_hw *[]) {
348 &g12a_aoclk_saradc_mux.hw
349 },
324 .num_parents = 1, 350 .num_parents = 1,
325 .flags = CLK_SET_RATE_PARENT, 351 .flags = CLK_SET_RATE_PARENT,
326 }, 352 },
@@ -334,7 +360,9 @@ static struct clk_regmap g12a_aoclk_saradc_gate = {
334 .hw.init = &(struct clk_init_data){ 360 .hw.init = &(struct clk_init_data){
335 .name = "g12a_ao_saradc_gate", 361 .name = "g12a_ao_saradc_gate",
336 .ops = &clk_regmap_gate_ops, 362 .ops = &clk_regmap_gate_ops,
337 .parent_names = (const char *[]){ "g12a_ao_saradc_div" }, 363 .parent_hws = (const struct clk_hw *[]) {
364 &g12a_aoclk_saradc_div.hw
365 },
338 .num_parents = 1, 366 .num_parents = 1,
339 .flags = CLK_SET_RATE_PARENT, 367 .flags = CLK_SET_RATE_PARENT,
340 }, 368 },
@@ -417,12 +445,6 @@ static const struct clk_hw_onecell_data g12a_aoclk_onecell_data = {
417 .num = NR_CLKS, 445 .num = NR_CLKS,
418}; 446};
419 447
420static const struct meson_aoclk_input g12a_aoclk_inputs[] = {
421 { .name = "xtal", .required = true },
422 { .name = "mpeg-clk", .required = true },
423 { .name = "ext-32k-0", .required = false },
424};
425
426static const struct meson_aoclk_data g12a_aoclkc_data = { 448static const struct meson_aoclk_data g12a_aoclkc_data = {
427 .reset_reg = AO_RTI_GEN_CNTL_REG0, 449 .reset_reg = AO_RTI_GEN_CNTL_REG0,
428 .num_reset = ARRAY_SIZE(g12a_aoclk_reset), 450 .num_reset = ARRAY_SIZE(g12a_aoclk_reset),
@@ -430,9 +452,6 @@ static const struct meson_aoclk_data g12a_aoclkc_data = {
430 .num_clks = ARRAY_SIZE(g12a_aoclk_regmap), 452 .num_clks = ARRAY_SIZE(g12a_aoclk_regmap),
431 .clks = g12a_aoclk_regmap, 453 .clks = g12a_aoclk_regmap,
432 .hw_data = &g12a_aoclk_onecell_data, 454 .hw_data = &g12a_aoclk_onecell_data,
433 .inputs = g12a_aoclk_inputs,
434 .num_inputs = ARRAY_SIZE(g12a_aoclk_inputs),
435 .input_prefix = IN_PREFIX,
436}; 455};
437 456
438static const struct of_device_id g12a_aoclkc_match_table[] = { 457static const struct of_device_id g12a_aoclkc_match_table[] = {
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index db1c4ed9d54e..ea4c791f106d 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -14,11 +14,12 @@
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/of_device.h> 15#include <linux/of_device.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/clk.h>
17 18
18#include "clk-input.h"
19#include "clk-mpll.h" 19#include "clk-mpll.h"
20#include "clk-pll.h" 20#include "clk-pll.h"
21#include "clk-regmap.h" 21#include "clk-regmap.h"
22#include "clk-cpu-dyndiv.h"
22#include "vid-pll-div.h" 23#include "vid-pll-div.h"
23#include "meson-eeclk.h" 24#include "meson-eeclk.h"
24#include "g12a.h" 25#include "g12a.h"
@@ -61,7 +62,9 @@ static struct clk_regmap g12a_fixed_pll_dco = {
61 .hw.init = &(struct clk_init_data){ 62 .hw.init = &(struct clk_init_data){
62 .name = "fixed_pll_dco", 63 .name = "fixed_pll_dco",
63 .ops = &meson_clk_pll_ro_ops, 64 .ops = &meson_clk_pll_ro_ops,
64 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 65 .parent_data = &(const struct clk_parent_data) {
66 .fw_name = "xtal",
67 },
65 .num_parents = 1, 68 .num_parents = 1,
66 }, 69 },
67}; 70};
@@ -76,7 +79,9 @@ static struct clk_regmap g12a_fixed_pll = {
76 .hw.init = &(struct clk_init_data){ 79 .hw.init = &(struct clk_init_data){
77 .name = "fixed_pll", 80 .name = "fixed_pll",
78 .ops = &clk_regmap_divider_ro_ops, 81 .ops = &clk_regmap_divider_ro_ops,
79 .parent_names = (const char *[]){ "fixed_pll_dco" }, 82 .parent_hws = (const struct clk_hw *[]) {
83 &g12a_fixed_pll_dco.hw
84 },
80 .num_parents = 1, 85 .num_parents = 1,
81 /* 86 /*
82 * This clock won't ever change at runtime so 87 * This clock won't ever change at runtime so
@@ -85,16 +90,9 @@ static struct clk_regmap g12a_fixed_pll = {
85 }, 90 },
86}; 91};
87 92
88/* 93static const struct pll_mult_range g12a_sys_pll_mult_range = {
89 * Internal sys pll emulation configuration parameters 94 .min = 128,
90 */ 95 .max = 250,
91static const struct reg_sequence g12a_sys_init_regs[] = {
92 { .reg = HHI_SYS_PLL_CNTL1, .def = 0x00000000 },
93 { .reg = HHI_SYS_PLL_CNTL2, .def = 0x00000000 },
94 { .reg = HHI_SYS_PLL_CNTL3, .def = 0x48681c00 },
95 { .reg = HHI_SYS_PLL_CNTL4, .def = 0x88770290 },
96 { .reg = HHI_SYS_PLL_CNTL5, .def = 0x39272000 },
97 { .reg = HHI_SYS_PLL_CNTL6, .def = 0x56540000 },
98}; 96};
99 97
100static struct clk_regmap g12a_sys_pll_dco = { 98static struct clk_regmap g12a_sys_pll_dco = {
@@ -124,14 +122,17 @@ static struct clk_regmap g12a_sys_pll_dco = {
124 .shift = 29, 122 .shift = 29,
125 .width = 1, 123 .width = 1,
126 }, 124 },
127 .init_regs = g12a_sys_init_regs, 125 .range = &g12a_sys_pll_mult_range,
128 .init_count = ARRAY_SIZE(g12a_sys_init_regs),
129 }, 126 },
130 .hw.init = &(struct clk_init_data){ 127 .hw.init = &(struct clk_init_data){
131 .name = "sys_pll_dco", 128 .name = "sys_pll_dco",
132 .ops = &meson_clk_pll_ro_ops, 129 .ops = &meson_clk_pll_ops,
133 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 130 .parent_data = &(const struct clk_parent_data) {
131 .fw_name = "xtal",
132 },
134 .num_parents = 1, 133 .num_parents = 1,
134 /* This clock feeds the CPU, avoid disabling it */
135 .flags = CLK_IS_CRITICAL,
135 }, 136 },
136}; 137};
137 138
@@ -144,9 +145,12 @@ static struct clk_regmap g12a_sys_pll = {
144 }, 145 },
145 .hw.init = &(struct clk_init_data){ 146 .hw.init = &(struct clk_init_data){
146 .name = "sys_pll", 147 .name = "sys_pll",
147 .ops = &clk_regmap_divider_ro_ops, 148 .ops = &clk_regmap_divider_ops,
148 .parent_names = (const char *[]){ "sys_pll_dco" }, 149 .parent_hws = (const struct clk_hw *[]) {
150 &g12a_sys_pll_dco.hw
151 },
149 .num_parents = 1, 152 .num_parents = 1,
153 .flags = CLK_SET_RATE_PARENT,
150 }, 154 },
151}; 155};
152 156
@@ -177,12 +181,17 @@ static struct clk_regmap g12b_sys1_pll_dco = {
177 .shift = 29, 181 .shift = 29,
178 .width = 1, 182 .width = 1,
179 }, 183 },
184 .range = &g12a_sys_pll_mult_range,
180 }, 185 },
181 .hw.init = &(struct clk_init_data){ 186 .hw.init = &(struct clk_init_data){
182 .name = "sys1_pll_dco", 187 .name = "sys1_pll_dco",
183 .ops = &meson_clk_pll_ro_ops, 188 .ops = &meson_clk_pll_ops,
184 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 189 .parent_data = &(const struct clk_parent_data) {
190 .fw_name = "xtal",
191 },
185 .num_parents = 1, 192 .num_parents = 1,
193 /* This clock feeds the CPU, avoid disabling it */
194 .flags = CLK_IS_CRITICAL,
186 }, 195 },
187}; 196};
188 197
@@ -195,9 +204,12 @@ static struct clk_regmap g12b_sys1_pll = {
195 }, 204 },
196 .hw.init = &(struct clk_init_data){ 205 .hw.init = &(struct clk_init_data){
197 .name = "sys1_pll", 206 .name = "sys1_pll",
198 .ops = &clk_regmap_divider_ro_ops, 207 .ops = &clk_regmap_divider_ops,
199 .parent_names = (const char *[]){ "sys1_pll_dco" }, 208 .parent_hws = (const struct clk_hw *[]) {
209 &g12b_sys1_pll_dco.hw
210 },
200 .num_parents = 1, 211 .num_parents = 1,
212 .flags = CLK_SET_RATE_PARENT,
201 }, 213 },
202}; 214};
203 215
@@ -209,7 +221,7 @@ static struct clk_regmap g12a_sys_pll_div16_en = {
209 .hw.init = &(struct clk_init_data) { 221 .hw.init = &(struct clk_init_data) {
210 .name = "sys_pll_div16_en", 222 .name = "sys_pll_div16_en",
211 .ops = &clk_regmap_gate_ro_ops, 223 .ops = &clk_regmap_gate_ro_ops,
212 .parent_names = (const char *[]){ "sys_pll" }, 224 .parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },
213 .num_parents = 1, 225 .num_parents = 1,
214 /* 226 /*
215 * This clock is used to debug the sys_pll range 227 * This clock is used to debug the sys_pll range
@@ -226,7 +238,9 @@ static struct clk_regmap g12b_sys1_pll_div16_en = {
226 .hw.init = &(struct clk_init_data) { 238 .hw.init = &(struct clk_init_data) {
227 .name = "sys1_pll_div16_en", 239 .name = "sys1_pll_div16_en",
228 .ops = &clk_regmap_gate_ro_ops, 240 .ops = &clk_regmap_gate_ro_ops,
229 .parent_names = (const char *[]){ "sys1_pll" }, 241 .parent_hws = (const struct clk_hw *[]) {
242 &g12b_sys1_pll.hw
243 },
230 .num_parents = 1, 244 .num_parents = 1,
231 /* 245 /*
232 * This clock is used to debug the sys_pll range 246 * This clock is used to debug the sys_pll range
@@ -241,7 +255,9 @@ static struct clk_fixed_factor g12a_sys_pll_div16 = {
241 .hw.init = &(struct clk_init_data){ 255 .hw.init = &(struct clk_init_data){
242 .name = "sys_pll_div16", 256 .name = "sys_pll_div16",
243 .ops = &clk_fixed_factor_ops, 257 .ops = &clk_fixed_factor_ops,
244 .parent_names = (const char *[]){ "sys_pll_div16_en" }, 258 .parent_hws = (const struct clk_hw *[]) {
259 &g12a_sys_pll_div16_en.hw
260 },
245 .num_parents = 1, 261 .num_parents = 1,
246 }, 262 },
247}; 263};
@@ -252,11 +268,75 @@ static struct clk_fixed_factor g12b_sys1_pll_div16 = {
252 .hw.init = &(struct clk_init_data){ 268 .hw.init = &(struct clk_init_data){
253 .name = "sys1_pll_div16", 269 .name = "sys1_pll_div16",
254 .ops = &clk_fixed_factor_ops, 270 .ops = &clk_fixed_factor_ops,
255 .parent_names = (const char *[]){ "sys1_pll_div16_en" }, 271 .parent_hws = (const struct clk_hw *[]) {
272 &g12b_sys1_pll_div16_en.hw
273 },
274 .num_parents = 1,
275 },
276};
277
278static struct clk_fixed_factor g12a_fclk_div2_div = {
279 .mult = 1,
280 .div = 2,
281 .hw.init = &(struct clk_init_data){
282 .name = "fclk_div2_div",
283 .ops = &clk_fixed_factor_ops,
284 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
285 .num_parents = 1,
286 },
287};
288
289static struct clk_regmap g12a_fclk_div2 = {
290 .data = &(struct clk_regmap_gate_data){
291 .offset = HHI_FIX_PLL_CNTL1,
292 .bit_idx = 24,
293 },
294 .hw.init = &(struct clk_init_data){
295 .name = "fclk_div2",
296 .ops = &clk_regmap_gate_ops,
297 .parent_hws = (const struct clk_hw *[]) {
298 &g12a_fclk_div2_div.hw
299 },
300 .num_parents = 1,
301 },
302};
303
304static struct clk_fixed_factor g12a_fclk_div3_div = {
305 .mult = 1,
306 .div = 3,
307 .hw.init = &(struct clk_init_data){
308 .name = "fclk_div3_div",
309 .ops = &clk_fixed_factor_ops,
310 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
256 .num_parents = 1, 311 .num_parents = 1,
257 }, 312 },
258}; 313};
259 314
315static struct clk_regmap g12a_fclk_div3 = {
316 .data = &(struct clk_regmap_gate_data){
317 .offset = HHI_FIX_PLL_CNTL1,
318 .bit_idx = 20,
319 },
320 .hw.init = &(struct clk_init_data){
321 .name = "fclk_div3",
322 .ops = &clk_regmap_gate_ops,
323 .parent_hws = (const struct clk_hw *[]) {
324 &g12a_fclk_div3_div.hw
325 },
326 .num_parents = 1,
327 /*
328 * This clock is used by the resident firmware and is required
329 * by the platform to operate correctly.
330 * Until the following condition are met, we need this clock to
331 * be marked as critical:
332 * a) Mark the clock used by a firmware resource, if possible
333 * b) CCF has a clock hand-off mechanism to make the sure the
334 * clock stays on until the proper driver comes along
335 */
336 .flags = CLK_IS_CRITICAL,
337 },
338};
339
260/* Datasheet names this field as "premux0" */ 340/* Datasheet names this field as "premux0" */
261static struct clk_regmap g12a_cpu_clk_premux0 = { 341static struct clk_regmap g12a_cpu_clk_premux0 = {
262 .data = &(struct clk_regmap_mux_data){ 342 .data = &(struct clk_regmap_mux_data){
@@ -266,26 +346,61 @@ static struct clk_regmap g12a_cpu_clk_premux0 = {
266 }, 346 },
267 .hw.init = &(struct clk_init_data){ 347 .hw.init = &(struct clk_init_data){
268 .name = "cpu_clk_dyn0_sel", 348 .name = "cpu_clk_dyn0_sel",
269 .ops = &clk_regmap_mux_ro_ops, 349 .ops = &clk_regmap_mux_ops,
270 .parent_names = (const char *[]){ IN_PREFIX "xtal", 350 .parent_data = (const struct clk_parent_data []) {
271 "fclk_div2", 351 { .fw_name = "xtal", },
272 "fclk_div3" }, 352 { .hw = &g12a_fclk_div2.hw },
353 { .hw = &g12a_fclk_div3.hw },
354 },
355 .num_parents = 3,
356 /* This sub-tree is used a parking clock */
357 .flags = CLK_SET_RATE_NO_REPARENT,
358 },
359};
360
361/* Datasheet names this field as "premux1" */
362static struct clk_regmap g12a_cpu_clk_premux1 = {
363 .data = &(struct clk_regmap_mux_data){
364 .offset = HHI_SYS_CPU_CLK_CNTL0,
365 .mask = 0x3,
366 .shift = 16,
367 },
368 .hw.init = &(struct clk_init_data){
369 .name = "cpu_clk_dyn1_sel",
370 .ops = &clk_regmap_mux_ops,
371 .parent_data = (const struct clk_parent_data []) {
372 { .fw_name = "xtal", },
373 { .hw = &g12a_fclk_div2.hw },
374 { .hw = &g12a_fclk_div3.hw },
375 },
273 .num_parents = 3, 376 .num_parents = 3,
377 /* This sub-tree is used a parking clock */
378 .flags = CLK_SET_RATE_NO_REPARENT
274 }, 379 },
275}; 380};
276 381
277/* Datasheet names this field as "mux0_divn_tcnt" */ 382/* Datasheet names this field as "mux0_divn_tcnt" */
278static struct clk_regmap g12a_cpu_clk_mux0_div = { 383static struct clk_regmap g12a_cpu_clk_mux0_div = {
279 .data = &(struct clk_regmap_div_data){ 384 .data = &(struct meson_clk_cpu_dyndiv_data){
280 .offset = HHI_SYS_CPU_CLK_CNTL0, 385 .div = {
281 .shift = 4, 386 .reg_off = HHI_SYS_CPU_CLK_CNTL0,
282 .width = 6, 387 .shift = 4,
388 .width = 6,
389 },
390 .dyn = {
391 .reg_off = HHI_SYS_CPU_CLK_CNTL0,
392 .shift = 26,
393 .width = 1,
394 },
283 }, 395 },
284 .hw.init = &(struct clk_init_data){ 396 .hw.init = &(struct clk_init_data){
285 .name = "cpu_clk_dyn0_div", 397 .name = "cpu_clk_dyn0_div",
286 .ops = &clk_regmap_divider_ro_ops, 398 .ops = &meson_clk_cpu_dyndiv_ops,
287 .parent_names = (const char *[]){ "cpu_clk_dyn0_sel" }, 399 .parent_hws = (const struct clk_hw *[]) {
400 &g12a_cpu_clk_premux0.hw
401 },
288 .num_parents = 1, 402 .num_parents = 1,
403 .flags = CLK_SET_RATE_PARENT,
289 }, 404 },
290}; 405};
291 406
@@ -298,27 +413,13 @@ static struct clk_regmap g12a_cpu_clk_postmux0 = {
298 }, 413 },
299 .hw.init = &(struct clk_init_data){ 414 .hw.init = &(struct clk_init_data){
300 .name = "cpu_clk_dyn0", 415 .name = "cpu_clk_dyn0",
301 .ops = &clk_regmap_mux_ro_ops, 416 .ops = &clk_regmap_mux_ops,
302 .parent_names = (const char *[]){ "cpu_clk_dyn0_sel", 417 .parent_hws = (const struct clk_hw *[]) {
303 "cpu_clk_dyn0_div" }, 418 &g12a_cpu_clk_premux0.hw,
419 &g12a_cpu_clk_mux0_div.hw,
420 },
304 .num_parents = 2, 421 .num_parents = 2,
305 }, 422 .flags = CLK_SET_RATE_PARENT,
306};
307
308/* Datasheet names this field as "premux1" */
309static struct clk_regmap g12a_cpu_clk_premux1 = {
310 .data = &(struct clk_regmap_mux_data){
311 .offset = HHI_SYS_CPU_CLK_CNTL0,
312 .mask = 0x3,
313 .shift = 16,
314 },
315 .hw.init = &(struct clk_init_data){
316 .name = "cpu_clk_dyn1_sel",
317 .ops = &clk_regmap_mux_ro_ops,
318 .parent_names = (const char *[]){ IN_PREFIX "xtal",
319 "fclk_div2",
320 "fclk_div3" },
321 .num_parents = 3,
322 }, 423 },
323}; 424};
324 425
@@ -332,7 +433,9 @@ static struct clk_regmap g12a_cpu_clk_mux1_div = {
332 .hw.init = &(struct clk_init_data){ 433 .hw.init = &(struct clk_init_data){
333 .name = "cpu_clk_dyn1_div", 434 .name = "cpu_clk_dyn1_div",
334 .ops = &clk_regmap_divider_ro_ops, 435 .ops = &clk_regmap_divider_ro_ops,
335 .parent_names = (const char *[]){ "cpu_clk_dyn1_sel" }, 436 .parent_hws = (const struct clk_hw *[]) {
437 &g12a_cpu_clk_premux1.hw
438 },
336 .num_parents = 1, 439 .num_parents = 1,
337 }, 440 },
338}; 441};
@@ -346,10 +449,14 @@ static struct clk_regmap g12a_cpu_clk_postmux1 = {
346 }, 449 },
347 .hw.init = &(struct clk_init_data){ 450 .hw.init = &(struct clk_init_data){
348 .name = "cpu_clk_dyn1", 451 .name = "cpu_clk_dyn1",
349 .ops = &clk_regmap_mux_ro_ops, 452 .ops = &clk_regmap_mux_ops,
350 .parent_names = (const char *[]){ "cpu_clk_dyn1_sel", 453 .parent_hws = (const struct clk_hw *[]) {
351 "cpu_clk_dyn1_div" }, 454 &g12a_cpu_clk_premux1.hw,
455 &g12a_cpu_clk_mux1_div.hw,
456 },
352 .num_parents = 2, 457 .num_parents = 2,
458 /* This sub-tree is used a parking clock */
459 .flags = CLK_SET_RATE_NO_REPARENT,
353 }, 460 },
354}; 461};
355 462
@@ -362,10 +469,13 @@ static struct clk_regmap g12a_cpu_clk_dyn = {
362 }, 469 },
363 .hw.init = &(struct clk_init_data){ 470 .hw.init = &(struct clk_init_data){
364 .name = "cpu_clk_dyn", 471 .name = "cpu_clk_dyn",
365 .ops = &clk_regmap_mux_ro_ops, 472 .ops = &clk_regmap_mux_ops,
366 .parent_names = (const char *[]){ "cpu_clk_dyn0", 473 .parent_hws = (const struct clk_hw *[]) {
367 "cpu_clk_dyn1" }, 474 &g12a_cpu_clk_postmux0.hw,
475 &g12a_cpu_clk_postmux1.hw,
476 },
368 .num_parents = 2, 477 .num_parents = 2,
478 .flags = CLK_SET_RATE_PARENT,
369 }, 479 },
370}; 480};
371 481
@@ -378,10 +488,13 @@ static struct clk_regmap g12a_cpu_clk = {
378 }, 488 },
379 .hw.init = &(struct clk_init_data){ 489 .hw.init = &(struct clk_init_data){
380 .name = "cpu_clk", 490 .name = "cpu_clk",
381 .ops = &clk_regmap_mux_ro_ops, 491 .ops = &clk_regmap_mux_ops,
382 .parent_names = (const char *[]){ "cpu_clk_dyn", 492 .parent_hws = (const struct clk_hw *[]) {
383 "sys_pll" }, 493 &g12a_cpu_clk_dyn.hw,
494 &g12a_sys_pll.hw,
495 },
384 .num_parents = 2, 496 .num_parents = 2,
497 .flags = CLK_SET_RATE_PARENT,
385 }, 498 },
386}; 499};
387 500
@@ -394,10 +507,13 @@ static struct clk_regmap g12b_cpu_clk = {
394 }, 507 },
395 .hw.init = &(struct clk_init_data){ 508 .hw.init = &(struct clk_init_data){
396 .name = "cpu_clk", 509 .name = "cpu_clk",
397 .ops = &clk_regmap_mux_ro_ops, 510 .ops = &clk_regmap_mux_ops,
398 .parent_names = (const char *[]){ "cpu_clk_dyn", 511 .parent_hws = (const struct clk_hw *[]) {
399 "sys1_pll" }, 512 &g12a_cpu_clk_dyn.hw,
513 &g12b_sys1_pll.hw
514 },
400 .num_parents = 2, 515 .num_parents = 2,
516 .flags = CLK_SET_RATE_PARENT,
401 }, 517 },
402}; 518};
403 519
@@ -410,26 +526,38 @@ static struct clk_regmap g12b_cpub_clk_premux0 = {
410 }, 526 },
411 .hw.init = &(struct clk_init_data){ 527 .hw.init = &(struct clk_init_data){
412 .name = "cpub_clk_dyn0_sel", 528 .name = "cpub_clk_dyn0_sel",
413 .ops = &clk_regmap_mux_ro_ops, 529 .ops = &clk_regmap_mux_ops,
414 .parent_names = (const char *[]){ IN_PREFIX "xtal", 530 .parent_data = (const struct clk_parent_data []) {
415 "fclk_div2", 531 { .fw_name = "xtal", },
416 "fclk_div3" }, 532 { .hw = &g12a_fclk_div2.hw },
533 { .hw = &g12a_fclk_div3.hw },
534 },
417 .num_parents = 3, 535 .num_parents = 3,
418 }, 536 },
419}; 537};
420 538
421/* Datasheet names this field as "mux0_divn_tcnt" */ 539/* Datasheet names this field as "mux0_divn_tcnt" */
422static struct clk_regmap g12b_cpub_clk_mux0_div = { 540static struct clk_regmap g12b_cpub_clk_mux0_div = {
423 .data = &(struct clk_regmap_div_data){ 541 .data = &(struct meson_clk_cpu_dyndiv_data){
424 .offset = HHI_SYS_CPUB_CLK_CNTL, 542 .div = {
425 .shift = 4, 543 .reg_off = HHI_SYS_CPUB_CLK_CNTL,
426 .width = 6, 544 .shift = 4,
545 .width = 6,
546 },
547 .dyn = {
548 .reg_off = HHI_SYS_CPUB_CLK_CNTL,
549 .shift = 26,
550 .width = 1,
551 },
427 }, 552 },
428 .hw.init = &(struct clk_init_data){ 553 .hw.init = &(struct clk_init_data){
429 .name = "cpub_clk_dyn0_div", 554 .name = "cpub_clk_dyn0_div",
430 .ops = &clk_regmap_divider_ro_ops, 555 .ops = &meson_clk_cpu_dyndiv_ops,
431 .parent_names = (const char *[]){ "cpub_clk_dyn0_sel" }, 556 .parent_hws = (const struct clk_hw *[]) {
557 &g12b_cpub_clk_premux0.hw
558 },
432 .num_parents = 1, 559 .num_parents = 1,
560 .flags = CLK_SET_RATE_PARENT,
433 }, 561 },
434}; 562};
435 563
@@ -442,10 +570,13 @@ static struct clk_regmap g12b_cpub_clk_postmux0 = {
442 }, 570 },
443 .hw.init = &(struct clk_init_data){ 571 .hw.init = &(struct clk_init_data){
444 .name = "cpub_clk_dyn0", 572 .name = "cpub_clk_dyn0",
445 .ops = &clk_regmap_mux_ro_ops, 573 .ops = &clk_regmap_mux_ops,
446 .parent_names = (const char *[]){ "cpub_clk_dyn0_sel", 574 .parent_hws = (const struct clk_hw *[]) {
447 "cpub_clk_dyn0_div" }, 575 &g12b_cpub_clk_premux0.hw,
576 &g12b_cpub_clk_mux0_div.hw
577 },
448 .num_parents = 2, 578 .num_parents = 2,
579 .flags = CLK_SET_RATE_PARENT,
449 }, 580 },
450}; 581};
451 582
@@ -458,11 +589,15 @@ static struct clk_regmap g12b_cpub_clk_premux1 = {
458 }, 589 },
459 .hw.init = &(struct clk_init_data){ 590 .hw.init = &(struct clk_init_data){
460 .name = "cpub_clk_dyn1_sel", 591 .name = "cpub_clk_dyn1_sel",
461 .ops = &clk_regmap_mux_ro_ops, 592 .ops = &clk_regmap_mux_ops,
462 .parent_names = (const char *[]){ IN_PREFIX "xtal", 593 .parent_data = (const struct clk_parent_data []) {
463 "fclk_div2", 594 { .fw_name = "xtal", },
464 "fclk_div3" }, 595 { .hw = &g12a_fclk_div2.hw },
596 { .hw = &g12a_fclk_div3.hw },
597 },
465 .num_parents = 3, 598 .num_parents = 3,
599 /* This sub-tree is used a parking clock */
600 .flags = CLK_SET_RATE_NO_REPARENT,
466 }, 601 },
467}; 602};
468 603
@@ -476,7 +611,9 @@ static struct clk_regmap g12b_cpub_clk_mux1_div = {
476 .hw.init = &(struct clk_init_data){ 611 .hw.init = &(struct clk_init_data){
477 .name = "cpub_clk_dyn1_div", 612 .name = "cpub_clk_dyn1_div",
478 .ops = &clk_regmap_divider_ro_ops, 613 .ops = &clk_regmap_divider_ro_ops,
479 .parent_names = (const char *[]){ "cpub_clk_dyn1_sel" }, 614 .parent_hws = (const struct clk_hw *[]) {
615 &g12b_cpub_clk_premux1.hw
616 },
480 .num_parents = 1, 617 .num_parents = 1,
481 }, 618 },
482}; 619};
@@ -490,10 +627,14 @@ static struct clk_regmap g12b_cpub_clk_postmux1 = {
490 }, 627 },
491 .hw.init = &(struct clk_init_data){ 628 .hw.init = &(struct clk_init_data){
492 .name = "cpub_clk_dyn1", 629 .name = "cpub_clk_dyn1",
493 .ops = &clk_regmap_mux_ro_ops, 630 .ops = &clk_regmap_mux_ops,
494 .parent_names = (const char *[]){ "cpub_clk_dyn1_sel", 631 .parent_hws = (const struct clk_hw *[]) {
495 "cpub_clk_dyn1_div" }, 632 &g12b_cpub_clk_premux1.hw,
633 &g12b_cpub_clk_mux1_div.hw
634 },
496 .num_parents = 2, 635 .num_parents = 2,
636 /* This sub-tree is used a parking clock */
637 .flags = CLK_SET_RATE_NO_REPARENT,
497 }, 638 },
498}; 639};
499 640
@@ -506,10 +647,13 @@ static struct clk_regmap g12b_cpub_clk_dyn = {
506 }, 647 },
507 .hw.init = &(struct clk_init_data){ 648 .hw.init = &(struct clk_init_data){
508 .name = "cpub_clk_dyn", 649 .name = "cpub_clk_dyn",
509 .ops = &clk_regmap_mux_ro_ops, 650 .ops = &clk_regmap_mux_ops,
510 .parent_names = (const char *[]){ "cpub_clk_dyn0", 651 .parent_hws = (const struct clk_hw *[]) {
511 "cpub_clk_dyn1" }, 652 &g12b_cpub_clk_postmux0.hw,
653 &g12b_cpub_clk_postmux1.hw
654 },
512 .num_parents = 2, 655 .num_parents = 2,
656 .flags = CLK_SET_RATE_PARENT,
513 }, 657 },
514}; 658};
515 659
@@ -522,13 +666,447 @@ static struct clk_regmap g12b_cpub_clk = {
522 }, 666 },
523 .hw.init = &(struct clk_init_data){ 667 .hw.init = &(struct clk_init_data){
524 .name = "cpub_clk", 668 .name = "cpub_clk",
669 .ops = &clk_regmap_mux_ops,
670 .parent_hws = (const struct clk_hw *[]) {
671 &g12b_cpub_clk_dyn.hw,
672 &g12a_sys_pll.hw
673 },
674 .num_parents = 2,
675 .flags = CLK_SET_RATE_PARENT,
676 },
677};
678
679static struct clk_regmap sm1_gp1_pll;
680
681/* Datasheet names this field as "premux0" */
682static struct clk_regmap sm1_dsu_clk_premux0 = {
683 .data = &(struct clk_regmap_mux_data){
684 .offset = HHI_SYS_CPU_CLK_CNTL5,
685 .mask = 0x3,
686 .shift = 0,
687 },
688 .hw.init = &(struct clk_init_data){
689 .name = "dsu_clk_dyn0_sel",
690 .ops = &clk_regmap_mux_ro_ops,
691 .parent_data = (const struct clk_parent_data []) {
692 { .fw_name = "xtal", },
693 { .hw = &g12a_fclk_div2.hw },
694 { .hw = &g12a_fclk_div3.hw },
695 { .hw = &sm1_gp1_pll.hw },
696 },
697 .num_parents = 4,
698 },
699};
700
701/* Datasheet names this field as "premux1" */
702static struct clk_regmap sm1_dsu_clk_premux1 = {
703 .data = &(struct clk_regmap_mux_data){
704 .offset = HHI_SYS_CPU_CLK_CNTL5,
705 .mask = 0x3,
706 .shift = 16,
707 },
708 .hw.init = &(struct clk_init_data){
709 .name = "dsu_clk_dyn1_sel",
525 .ops = &clk_regmap_mux_ro_ops, 710 .ops = &clk_regmap_mux_ro_ops,
526 .parent_names = (const char *[]){ "cpub_clk_dyn", 711 .parent_data = (const struct clk_parent_data []) {
527 "sys_pll" }, 712 { .fw_name = "xtal", },
713 { .hw = &g12a_fclk_div2.hw },
714 { .hw = &g12a_fclk_div3.hw },
715 { .hw = &sm1_gp1_pll.hw },
716 },
717 .num_parents = 4,
718 },
719};
720
721/* Datasheet names this field as "Mux0_divn_tcnt" */
722static struct clk_regmap sm1_dsu_clk_mux0_div = {
723 .data = &(struct clk_regmap_div_data){
724 .offset = HHI_SYS_CPU_CLK_CNTL5,
725 .shift = 4,
726 .width = 6,
727 },
728 .hw.init = &(struct clk_init_data){
729 .name = "dsu_clk_dyn0_div",
730 .ops = &clk_regmap_divider_ro_ops,
731 .parent_hws = (const struct clk_hw *[]) {
732 &sm1_dsu_clk_premux0.hw
733 },
734 .num_parents = 1,
735 },
736};
737
738/* Datasheet names this field as "postmux0" */
739static struct clk_regmap sm1_dsu_clk_postmux0 = {
740 .data = &(struct clk_regmap_mux_data){
741 .offset = HHI_SYS_CPU_CLK_CNTL5,
742 .mask = 0x1,
743 .shift = 2,
744 },
745 .hw.init = &(struct clk_init_data){
746 .name = "dsu_clk_dyn0",
747 .ops = &clk_regmap_mux_ro_ops,
748 .parent_hws = (const struct clk_hw *[]) {
749 &sm1_dsu_clk_premux0.hw,
750 &sm1_dsu_clk_mux0_div.hw,
751 },
528 .num_parents = 2, 752 .num_parents = 2,
529 }, 753 },
530}; 754};
531 755
756/* Datasheet names this field as "Mux1_divn_tcnt" */
757static struct clk_regmap sm1_dsu_clk_mux1_div = {
758 .data = &(struct clk_regmap_div_data){
759 .offset = HHI_SYS_CPU_CLK_CNTL5,
760 .shift = 20,
761 .width = 6,
762 },
763 .hw.init = &(struct clk_init_data){
764 .name = "dsu_clk_dyn1_div",
765 .ops = &clk_regmap_divider_ro_ops,
766 .parent_hws = (const struct clk_hw *[]) {
767 &sm1_dsu_clk_premux1.hw
768 },
769 .num_parents = 1,
770 },
771};
772
773/* Datasheet names this field as "postmux1" */
774static struct clk_regmap sm1_dsu_clk_postmux1 = {
775 .data = &(struct clk_regmap_mux_data){
776 .offset = HHI_SYS_CPU_CLK_CNTL5,
777 .mask = 0x1,
778 .shift = 18,
779 },
780 .hw.init = &(struct clk_init_data){
781 .name = "dsu_clk_dyn1",
782 .ops = &clk_regmap_mux_ro_ops,
783 .parent_hws = (const struct clk_hw *[]) {
784 &sm1_dsu_clk_premux1.hw,
785 &sm1_dsu_clk_mux1_div.hw,
786 },
787 .num_parents = 2,
788 },
789};
790
791/* Datasheet names this field as "Final_dyn_mux_sel" */
792static struct clk_regmap sm1_dsu_clk_dyn = {
793 .data = &(struct clk_regmap_mux_data){
794 .offset = HHI_SYS_CPU_CLK_CNTL5,
795 .mask = 0x1,
796 .shift = 10,
797 },
798 .hw.init = &(struct clk_init_data){
799 .name = "dsu_clk_dyn",
800 .ops = &clk_regmap_mux_ro_ops,
801 .parent_hws = (const struct clk_hw *[]) {
802 &sm1_dsu_clk_postmux0.hw,
803 &sm1_dsu_clk_postmux1.hw,
804 },
805 .num_parents = 2,
806 },
807};
808
809/* Datasheet names this field as "Final_mux_sel" */
810static struct clk_regmap sm1_dsu_final_clk = {
811 .data = &(struct clk_regmap_mux_data){
812 .offset = HHI_SYS_CPU_CLK_CNTL5,
813 .mask = 0x1,
814 .shift = 11,
815 },
816 .hw.init = &(struct clk_init_data){
817 .name = "dsu_clk_final",
818 .ops = &clk_regmap_mux_ro_ops,
819 .parent_hws = (const struct clk_hw *[]) {
820 &sm1_dsu_clk_dyn.hw,
821 &g12a_sys_pll.hw,
822 },
823 .num_parents = 2,
824 },
825};
826
827/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 0 */
828static struct clk_regmap sm1_cpu1_clk = {
829 .data = &(struct clk_regmap_mux_data){
830 .offset = HHI_SYS_CPU_CLK_CNTL6,
831 .mask = 0x1,
832 .shift = 24,
833 },
834 .hw.init = &(struct clk_init_data){
835 .name = "cpu1_clk",
836 .ops = &clk_regmap_mux_ro_ops,
837 .parent_hws = (const struct clk_hw *[]) {
838 &g12a_cpu_clk.hw,
839 /* This CPU also have a dedicated clock tree */
840 },
841 .num_parents = 1,
842 },
843};
844
845/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 1 */
846static struct clk_regmap sm1_cpu2_clk = {
847 .data = &(struct clk_regmap_mux_data){
848 .offset = HHI_SYS_CPU_CLK_CNTL6,
849 .mask = 0x1,
850 .shift = 25,
851 },
852 .hw.init = &(struct clk_init_data){
853 .name = "cpu2_clk",
854 .ops = &clk_regmap_mux_ro_ops,
855 .parent_hws = (const struct clk_hw *[]) {
856 &g12a_cpu_clk.hw,
857 /* This CPU also have a dedicated clock tree */
858 },
859 .num_parents = 1,
860 },
861};
862
863/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 2 */
864static struct clk_regmap sm1_cpu3_clk = {
865 .data = &(struct clk_regmap_mux_data){
866 .offset = HHI_SYS_CPU_CLK_CNTL6,
867 .mask = 0x1,
868 .shift = 26,
869 },
870 .hw.init = &(struct clk_init_data){
871 .name = "cpu3_clk",
872 .ops = &clk_regmap_mux_ro_ops,
873 .parent_hws = (const struct clk_hw *[]) {
874 &g12a_cpu_clk.hw,
875 /* This CPU also have a dedicated clock tree */
876 },
877 .num_parents = 1,
878 },
879};
880
881/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */
882static struct clk_regmap sm1_dsu_clk = {
883 .data = &(struct clk_regmap_mux_data){
884 .offset = HHI_SYS_CPU_CLK_CNTL6,
885 .mask = 0x1,
886 .shift = 27,
887 },
888 .hw.init = &(struct clk_init_data){
889 .name = "dsu_clk",
890 .ops = &clk_regmap_mux_ro_ops,
891 .parent_hws = (const struct clk_hw *[]) {
892 &g12a_cpu_clk.hw,
893 &sm1_dsu_final_clk.hw,
894 },
895 .num_parents = 2,
896 },
897};
898
899static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb,
900 unsigned long event, void *data)
901{
902 if (event == POST_RATE_CHANGE || event == PRE_RATE_CHANGE) {
903 /* Wait for clock propagation before/after changing the mux */
904 udelay(100);
905 return NOTIFY_OK;
906 }
907
908 return NOTIFY_DONE;
909}
910
911static struct notifier_block g12a_cpu_clk_mux_nb = {
912 .notifier_call = g12a_cpu_clk_mux_notifier_cb,
913};
914
915struct g12a_cpu_clk_postmux_nb_data {
916 struct notifier_block nb;
917 struct clk_hw *xtal;
918 struct clk_hw *cpu_clk_dyn;
919 struct clk_hw *cpu_clk_postmux0;
920 struct clk_hw *cpu_clk_postmux1;
921 struct clk_hw *cpu_clk_premux1;
922};
923
924static int g12a_cpu_clk_postmux_notifier_cb(struct notifier_block *nb,
925 unsigned long event, void *data)
926{
927 struct g12a_cpu_clk_postmux_nb_data *nb_data =
928 container_of(nb, struct g12a_cpu_clk_postmux_nb_data, nb);
929
930 switch (event) {
931 case PRE_RATE_CHANGE:
932 /*
933 * This notifier means cpu_clk_postmux0 clock will be changed
934 * to feed cpu_clk, this is the current path :
935 * cpu_clk
936 * \- cpu_clk_dyn
937 * \- cpu_clk_postmux0
938 * \- cpu_clk_muxX_div
939 * \- cpu_clk_premux0
940 * \- fclk_div3 or fclk_div2
941 * OR
942 * \- cpu_clk_premux0
943 * \- fclk_div3 or fclk_div2
944 */
945
946 /* Setup cpu_clk_premux1 to xtal */
947 clk_hw_set_parent(nb_data->cpu_clk_premux1,
948 nb_data->xtal);
949
950 /* Setup cpu_clk_postmux1 to bypass divider */
951 clk_hw_set_parent(nb_data->cpu_clk_postmux1,
952 nb_data->cpu_clk_premux1);
953
954 /* Switch to parking clk on cpu_clk_postmux1 */
955 clk_hw_set_parent(nb_data->cpu_clk_dyn,
956 nb_data->cpu_clk_postmux1);
957
958 /*
959 * Now, cpu_clk is 24MHz in the current path :
960 * cpu_clk
961 * \- cpu_clk_dyn
962 * \- cpu_clk_postmux1
963 * \- cpu_clk_premux1
964 * \- xtal
965 */
966
967 udelay(100);
968
969 return NOTIFY_OK;
970
971 case POST_RATE_CHANGE:
972 /*
973 * The cpu_clk_postmux0 has ben updated, now switch back
974 * cpu_clk_dyn to cpu_clk_postmux0 and take the changes
975 * in account.
976 */
977
978 /* Configure cpu_clk_dyn back to cpu_clk_postmux0 */
979 clk_hw_set_parent(nb_data->cpu_clk_dyn,
980 nb_data->cpu_clk_postmux0);
981
982 /*
983 * new path :
984 * cpu_clk
985 * \- cpu_clk_dyn
986 * \- cpu_clk_postmux0
987 * \- cpu_clk_muxX_div
988 * \- cpu_clk_premux0
989 * \- fclk_div3 or fclk_div2
990 * OR
991 * \- cpu_clk_premux0
992 * \- fclk_div3 or fclk_div2
993 */
994
995 udelay(100);
996
997 return NOTIFY_OK;
998
999 default:
1000 return NOTIFY_DONE;
1001 }
1002}
1003
1004static struct g12a_cpu_clk_postmux_nb_data g12a_cpu_clk_postmux0_nb_data = {
1005 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1006 .cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw,
1007 .cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw,
1008 .cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw,
1009 .nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
1010};
1011
1012static struct g12a_cpu_clk_postmux_nb_data g12b_cpub_clk_postmux0_nb_data = {
1013 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1014 .cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw,
1015 .cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw,
1016 .cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw,
1017 .nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
1018};
1019
1020struct g12a_sys_pll_nb_data {
1021 struct notifier_block nb;
1022 struct clk_hw *sys_pll;
1023 struct clk_hw *cpu_clk;
1024 struct clk_hw *cpu_clk_dyn;
1025};
1026
1027static int g12a_sys_pll_notifier_cb(struct notifier_block *nb,
1028 unsigned long event, void *data)
1029{
1030 struct g12a_sys_pll_nb_data *nb_data =
1031 container_of(nb, struct g12a_sys_pll_nb_data, nb);
1032
1033 switch (event) {
1034 case PRE_RATE_CHANGE:
1035 /*
1036 * This notifier means sys_pll clock will be changed
1037 * to feed cpu_clk, this the current path :
1038 * cpu_clk
1039 * \- sys_pll
1040 * \- sys_pll_dco
1041 */
1042
1043 /* Configure cpu_clk to use cpu_clk_dyn */
1044 clk_hw_set_parent(nb_data->cpu_clk,
1045 nb_data->cpu_clk_dyn);
1046
1047 /*
1048 * Now, cpu_clk uses the dyn path
1049 * cpu_clk
1050 * \- cpu_clk_dyn
1051 * \- cpu_clk_dynX
1052 * \- cpu_clk_dynX_sel
1053 * \- cpu_clk_dynX_div
1054 * \- xtal/fclk_div2/fclk_div3
1055 * \- xtal/fclk_div2/fclk_div3
1056 */
1057
1058 udelay(100);
1059
1060 return NOTIFY_OK;
1061
1062 case POST_RATE_CHANGE:
1063 /*
1064 * The sys_pll has ben updated, now switch back cpu_clk to
1065 * sys_pll
1066 */
1067
1068 /* Configure cpu_clk to use sys_pll */
1069 clk_hw_set_parent(nb_data->cpu_clk,
1070 nb_data->sys_pll);
1071
1072 udelay(100);
1073
1074 /* new path :
1075 * cpu_clk
1076 * \- sys_pll
1077 * \- sys_pll_dco
1078 */
1079
1080 return NOTIFY_OK;
1081
1082 default:
1083 return NOTIFY_DONE;
1084 }
1085}
1086
1087static struct g12a_sys_pll_nb_data g12a_sys_pll_nb_data = {
1088 .sys_pll = &g12a_sys_pll.hw,
1089 .cpu_clk = &g12a_cpu_clk.hw,
1090 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1091 .nb.notifier_call = g12a_sys_pll_notifier_cb,
1092};
1093
1094/* G12B first CPU cluster uses sys1_pll */
1095static struct g12a_sys_pll_nb_data g12b_cpu_clk_sys1_pll_nb_data = {
1096 .sys_pll = &g12b_sys1_pll.hw,
1097 .cpu_clk = &g12b_cpu_clk.hw,
1098 .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
1099 .nb.notifier_call = g12a_sys_pll_notifier_cb,
1100};
1101
1102/* G12B second CPU cluster uses sys_pll */
1103static struct g12a_sys_pll_nb_data g12b_cpub_clk_sys_pll_nb_data = {
1104 .sys_pll = &g12a_sys_pll.hw,
1105 .cpu_clk = &g12b_cpub_clk.hw,
1106 .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
1107 .nb.notifier_call = g12a_sys_pll_notifier_cb,
1108};
1109
532static struct clk_regmap g12a_cpu_clk_div16_en = { 1110static struct clk_regmap g12a_cpu_clk_div16_en = {
533 .data = &(struct clk_regmap_gate_data){ 1111 .data = &(struct clk_regmap_gate_data){
534 .offset = HHI_SYS_CPU_CLK_CNTL1, 1112 .offset = HHI_SYS_CPU_CLK_CNTL1,
@@ -537,7 +1115,9 @@ static struct clk_regmap g12a_cpu_clk_div16_en = {
537 .hw.init = &(struct clk_init_data) { 1115 .hw.init = &(struct clk_init_data) {
538 .name = "cpu_clk_div16_en", 1116 .name = "cpu_clk_div16_en",
539 .ops = &clk_regmap_gate_ro_ops, 1117 .ops = &clk_regmap_gate_ro_ops,
540 .parent_names = (const char *[]){ "cpu_clk" }, 1118 .parent_hws = (const struct clk_hw *[]) {
1119 &g12a_cpu_clk.hw
1120 },
541 .num_parents = 1, 1121 .num_parents = 1,
542 /* 1122 /*
543 * This clock is used to debug the cpu_clk range 1123 * This clock is used to debug the cpu_clk range
@@ -554,7 +1134,9 @@ static struct clk_regmap g12b_cpub_clk_div16_en = {
554 .hw.init = &(struct clk_init_data) { 1134 .hw.init = &(struct clk_init_data) {
555 .name = "cpub_clk_div16_en", 1135 .name = "cpub_clk_div16_en",
556 .ops = &clk_regmap_gate_ro_ops, 1136 .ops = &clk_regmap_gate_ro_ops,
557 .parent_names = (const char *[]){ "cpub_clk" }, 1137 .parent_hws = (const struct clk_hw *[]) {
1138 &g12b_cpub_clk.hw
1139 },
558 .num_parents = 1, 1140 .num_parents = 1,
559 /* 1141 /*
560 * This clock is used to debug the cpu_clk range 1142 * This clock is used to debug the cpu_clk range
@@ -569,7 +1151,9 @@ static struct clk_fixed_factor g12a_cpu_clk_div16 = {
569 .hw.init = &(struct clk_init_data){ 1151 .hw.init = &(struct clk_init_data){
570 .name = "cpu_clk_div16", 1152 .name = "cpu_clk_div16",
571 .ops = &clk_fixed_factor_ops, 1153 .ops = &clk_fixed_factor_ops,
572 .parent_names = (const char *[]){ "cpu_clk_div16_en" }, 1154 .parent_hws = (const struct clk_hw *[]) {
1155 &g12a_cpu_clk_div16_en.hw
1156 },
573 .num_parents = 1, 1157 .num_parents = 1,
574 }, 1158 },
575}; 1159};
@@ -580,7 +1164,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div16 = {
580 .hw.init = &(struct clk_init_data){ 1164 .hw.init = &(struct clk_init_data){
581 .name = "cpub_clk_div16", 1165 .name = "cpub_clk_div16",
582 .ops = &clk_fixed_factor_ops, 1166 .ops = &clk_fixed_factor_ops,
583 .parent_names = (const char *[]){ "cpub_clk_div16_en" }, 1167 .parent_hws = (const struct clk_hw *[]) {
1168 &g12b_cpub_clk_div16_en.hw
1169 },
584 .num_parents = 1, 1170 .num_parents = 1,
585 }, 1171 },
586}; 1172};
@@ -595,7 +1181,7 @@ static struct clk_regmap g12a_cpu_clk_apb_div = {
595 .hw.init = &(struct clk_init_data){ 1181 .hw.init = &(struct clk_init_data){
596 .name = "cpu_clk_apb_div", 1182 .name = "cpu_clk_apb_div",
597 .ops = &clk_regmap_divider_ro_ops, 1183 .ops = &clk_regmap_divider_ro_ops,
598 .parent_names = (const char *[]){ "cpu_clk" }, 1184 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
599 .num_parents = 1, 1185 .num_parents = 1,
600 }, 1186 },
601}; 1187};
@@ -608,7 +1194,9 @@ static struct clk_regmap g12a_cpu_clk_apb = {
608 .hw.init = &(struct clk_init_data) { 1194 .hw.init = &(struct clk_init_data) {
609 .name = "cpu_clk_apb", 1195 .name = "cpu_clk_apb",
610 .ops = &clk_regmap_gate_ro_ops, 1196 .ops = &clk_regmap_gate_ro_ops,
611 .parent_names = (const char *[]){ "cpu_clk_apb_div" }, 1197 .parent_hws = (const struct clk_hw *[]) {
1198 &g12a_cpu_clk_apb_div.hw
1199 },
612 .num_parents = 1, 1200 .num_parents = 1,
613 /* 1201 /*
614 * This clock is set by the ROM monitor code, 1202 * This clock is set by the ROM monitor code,
@@ -627,7 +1215,7 @@ static struct clk_regmap g12a_cpu_clk_atb_div = {
627 .hw.init = &(struct clk_init_data){ 1215 .hw.init = &(struct clk_init_data){
628 .name = "cpu_clk_atb_div", 1216 .name = "cpu_clk_atb_div",
629 .ops = &clk_regmap_divider_ro_ops, 1217 .ops = &clk_regmap_divider_ro_ops,
630 .parent_names = (const char *[]){ "cpu_clk" }, 1218 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
631 .num_parents = 1, 1219 .num_parents = 1,
632 }, 1220 },
633}; 1221};
@@ -640,7 +1228,9 @@ static struct clk_regmap g12a_cpu_clk_atb = {
640 .hw.init = &(struct clk_init_data) { 1228 .hw.init = &(struct clk_init_data) {
641 .name = "cpu_clk_atb", 1229 .name = "cpu_clk_atb",
642 .ops = &clk_regmap_gate_ro_ops, 1230 .ops = &clk_regmap_gate_ro_ops,
643 .parent_names = (const char *[]){ "cpu_clk_atb_div" }, 1231 .parent_hws = (const struct clk_hw *[]) {
1232 &g12a_cpu_clk_atb_div.hw
1233 },
644 .num_parents = 1, 1234 .num_parents = 1,
645 /* 1235 /*
646 * This clock is set by the ROM monitor code, 1236 * This clock is set by the ROM monitor code,
@@ -659,7 +1249,7 @@ static struct clk_regmap g12a_cpu_clk_axi_div = {
659 .hw.init = &(struct clk_init_data){ 1249 .hw.init = &(struct clk_init_data){
660 .name = "cpu_clk_axi_div", 1250 .name = "cpu_clk_axi_div",
661 .ops = &clk_regmap_divider_ro_ops, 1251 .ops = &clk_regmap_divider_ro_ops,
662 .parent_names = (const char *[]){ "cpu_clk" }, 1252 .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
663 .num_parents = 1, 1253 .num_parents = 1,
664 }, 1254 },
665}; 1255};
@@ -672,7 +1262,9 @@ static struct clk_regmap g12a_cpu_clk_axi = {
672 .hw.init = &(struct clk_init_data) { 1262 .hw.init = &(struct clk_init_data) {
673 .name = "cpu_clk_axi", 1263 .name = "cpu_clk_axi",
674 .ops = &clk_regmap_gate_ro_ops, 1264 .ops = &clk_regmap_gate_ro_ops,
675 .parent_names = (const char *[]){ "cpu_clk_axi_div" }, 1265 .parent_hws = (const struct clk_hw *[]) {
1266 &g12a_cpu_clk_axi_div.hw
1267 },
676 .num_parents = 1, 1268 .num_parents = 1,
677 /* 1269 /*
678 * This clock is set by the ROM monitor code, 1270 * This clock is set by the ROM monitor code,
@@ -691,7 +1283,17 @@ static struct clk_regmap g12a_cpu_clk_trace_div = {
691 .hw.init = &(struct clk_init_data){ 1283 .hw.init = &(struct clk_init_data){
692 .name = "cpu_clk_trace_div", 1284 .name = "cpu_clk_trace_div",
693 .ops = &clk_regmap_divider_ro_ops, 1285 .ops = &clk_regmap_divider_ro_ops,
694 .parent_names = (const char *[]){ "cpu_clk" }, 1286 .parent_data = &(const struct clk_parent_data) {
1287 /*
1288 * Note:
1289 * G12A and G12B have different cpu_clks (with
1290 * different struct clk_hw). We fallback to the global
1291 * naming string mechanism so cpu_clk_trace_div picks
1292 * up the appropriate one.
1293 */
1294 .name = "cpu_clk",
1295 .index = -1,
1296 },
695 .num_parents = 1, 1297 .num_parents = 1,
696 }, 1298 },
697}; 1299};
@@ -704,7 +1306,9 @@ static struct clk_regmap g12a_cpu_clk_trace = {
704 .hw.init = &(struct clk_init_data) { 1306 .hw.init = &(struct clk_init_data) {
705 .name = "cpu_clk_trace", 1307 .name = "cpu_clk_trace",
706 .ops = &clk_regmap_gate_ro_ops, 1308 .ops = &clk_regmap_gate_ro_ops,
707 .parent_names = (const char *[]){ "cpu_clk_trace_div" }, 1309 .parent_hws = (const struct clk_hw *[]) {
1310 &g12a_cpu_clk_trace_div.hw
1311 },
708 .num_parents = 1, 1312 .num_parents = 1,
709 /* 1313 /*
710 * This clock is set by the ROM monitor code, 1314 * This clock is set by the ROM monitor code,
@@ -719,7 +1323,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div2 = {
719 .hw.init = &(struct clk_init_data){ 1323 .hw.init = &(struct clk_init_data){
720 .name = "cpub_clk_div2", 1324 .name = "cpub_clk_div2",
721 .ops = &clk_fixed_factor_ops, 1325 .ops = &clk_fixed_factor_ops,
722 .parent_names = (const char *[]){ "cpub_clk" }, 1326 .parent_hws = (const struct clk_hw *[]) {
1327 &g12b_cpub_clk.hw
1328 },
723 .num_parents = 1, 1329 .num_parents = 1,
724 }, 1330 },
725}; 1331};
@@ -730,7 +1336,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div3 = {
730 .hw.init = &(struct clk_init_data){ 1336 .hw.init = &(struct clk_init_data){
731 .name = "cpub_clk_div3", 1337 .name = "cpub_clk_div3",
732 .ops = &clk_fixed_factor_ops, 1338 .ops = &clk_fixed_factor_ops,
733 .parent_names = (const char *[]){ "cpub_clk" }, 1339 .parent_hws = (const struct clk_hw *[]) {
1340 &g12b_cpub_clk.hw
1341 },
734 .num_parents = 1, 1342 .num_parents = 1,
735 }, 1343 },
736}; 1344};
@@ -741,7 +1349,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div4 = {
741 .hw.init = &(struct clk_init_data){ 1349 .hw.init = &(struct clk_init_data){
742 .name = "cpub_clk_div4", 1350 .name = "cpub_clk_div4",
743 .ops = &clk_fixed_factor_ops, 1351 .ops = &clk_fixed_factor_ops,
744 .parent_names = (const char *[]){ "cpub_clk" }, 1352 .parent_hws = (const struct clk_hw *[]) {
1353 &g12b_cpub_clk.hw
1354 },
745 .num_parents = 1, 1355 .num_parents = 1,
746 }, 1356 },
747}; 1357};
@@ -752,7 +1362,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div5 = {
752 .hw.init = &(struct clk_init_data){ 1362 .hw.init = &(struct clk_init_data){
753 .name = "cpub_clk_div5", 1363 .name = "cpub_clk_div5",
754 .ops = &clk_fixed_factor_ops, 1364 .ops = &clk_fixed_factor_ops,
755 .parent_names = (const char *[]){ "cpub_clk" }, 1365 .parent_hws = (const struct clk_hw *[]) {
1366 &g12b_cpub_clk.hw
1367 },
756 .num_parents = 1, 1368 .num_parents = 1,
757 }, 1369 },
758}; 1370};
@@ -763,7 +1375,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div6 = {
763 .hw.init = &(struct clk_init_data){ 1375 .hw.init = &(struct clk_init_data){
764 .name = "cpub_clk_div6", 1376 .name = "cpub_clk_div6",
765 .ops = &clk_fixed_factor_ops, 1377 .ops = &clk_fixed_factor_ops,
766 .parent_names = (const char *[]){ "cpub_clk" }, 1378 .parent_hws = (const struct clk_hw *[]) {
1379 &g12b_cpub_clk.hw
1380 },
767 .num_parents = 1, 1381 .num_parents = 1,
768 }, 1382 },
769}; 1383};
@@ -774,7 +1388,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div7 = {
774 .hw.init = &(struct clk_init_data){ 1388 .hw.init = &(struct clk_init_data){
775 .name = "cpub_clk_div7", 1389 .name = "cpub_clk_div7",
776 .ops = &clk_fixed_factor_ops, 1390 .ops = &clk_fixed_factor_ops,
777 .parent_names = (const char *[]){ "cpub_clk" }, 1391 .parent_hws = (const struct clk_hw *[]) {
1392 &g12b_cpub_clk.hw
1393 },
778 .num_parents = 1, 1394 .num_parents = 1,
779 }, 1395 },
780}; 1396};
@@ -785,7 +1401,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div8 = {
785 .hw.init = &(struct clk_init_data){ 1401 .hw.init = &(struct clk_init_data){
786 .name = "cpub_clk_div8", 1402 .name = "cpub_clk_div8",
787 .ops = &clk_fixed_factor_ops, 1403 .ops = &clk_fixed_factor_ops,
788 .parent_names = (const char *[]){ "cpub_clk" }, 1404 .parent_hws = (const struct clk_hw *[]) {
1405 &g12b_cpub_clk.hw
1406 },
789 .num_parents = 1, 1407 .num_parents = 1,
790 }, 1408 },
791}; 1409};
@@ -801,13 +1419,15 @@ static struct clk_regmap g12b_cpub_clk_apb_sel = {
801 .hw.init = &(struct clk_init_data){ 1419 .hw.init = &(struct clk_init_data){
802 .name = "cpub_clk_apb_sel", 1420 .name = "cpub_clk_apb_sel",
803 .ops = &clk_regmap_mux_ro_ops, 1421 .ops = &clk_regmap_mux_ro_ops,
804 .parent_names = (const char *[]){ "cpub_clk_div2", 1422 .parent_hws = (const struct clk_hw *[]) {
805 "cpub_clk_div3", 1423 &g12b_cpub_clk_div2.hw,
806 "cpub_clk_div4", 1424 &g12b_cpub_clk_div3.hw,
807 "cpub_clk_div5", 1425 &g12b_cpub_clk_div4.hw,
808 "cpub_clk_div6", 1426 &g12b_cpub_clk_div5.hw,
809 "cpub_clk_div7", 1427 &g12b_cpub_clk_div6.hw,
810 "cpub_clk_div8" }, 1428 &g12b_cpub_clk_div7.hw,
1429 &g12b_cpub_clk_div8.hw
1430 },
811 .num_parents = 7, 1431 .num_parents = 7,
812 }, 1432 },
813}; 1433};
@@ -821,7 +1441,9 @@ static struct clk_regmap g12b_cpub_clk_apb = {
821 .hw.init = &(struct clk_init_data) { 1441 .hw.init = &(struct clk_init_data) {
822 .name = "cpub_clk_apb", 1442 .name = "cpub_clk_apb",
823 .ops = &clk_regmap_gate_ro_ops, 1443 .ops = &clk_regmap_gate_ro_ops,
824 .parent_names = (const char *[]){ "cpub_clk_apb_sel" }, 1444 .parent_hws = (const struct clk_hw *[]) {
1445 &g12b_cpub_clk_apb_sel.hw
1446 },
825 .num_parents = 1, 1447 .num_parents = 1,
826 /* 1448 /*
827 * This clock is set by the ROM monitor code, 1449 * This clock is set by the ROM monitor code,
@@ -840,13 +1462,15 @@ static struct clk_regmap g12b_cpub_clk_atb_sel = {
840 .hw.init = &(struct clk_init_data){ 1462 .hw.init = &(struct clk_init_data){
841 .name = "cpub_clk_atb_sel", 1463 .name = "cpub_clk_atb_sel",
842 .ops = &clk_regmap_mux_ro_ops, 1464 .ops = &clk_regmap_mux_ro_ops,
843 .parent_names = (const char *[]){ "cpub_clk_div2", 1465 .parent_hws = (const struct clk_hw *[]) {
844 "cpub_clk_div3", 1466 &g12b_cpub_clk_div2.hw,
845 "cpub_clk_div4", 1467 &g12b_cpub_clk_div3.hw,
846 "cpub_clk_div5", 1468 &g12b_cpub_clk_div4.hw,
847 "cpub_clk_div6", 1469 &g12b_cpub_clk_div5.hw,
848 "cpub_clk_div7", 1470 &g12b_cpub_clk_div6.hw,
849 "cpub_clk_div8" }, 1471 &g12b_cpub_clk_div7.hw,
1472 &g12b_cpub_clk_div8.hw
1473 },
850 .num_parents = 7, 1474 .num_parents = 7,
851 }, 1475 },
852}; 1476};
@@ -860,7 +1484,9 @@ static struct clk_regmap g12b_cpub_clk_atb = {
860 .hw.init = &(struct clk_init_data) { 1484 .hw.init = &(struct clk_init_data) {
861 .name = "cpub_clk_atb", 1485 .name = "cpub_clk_atb",
862 .ops = &clk_regmap_gate_ro_ops, 1486 .ops = &clk_regmap_gate_ro_ops,
863 .parent_names = (const char *[]){ "cpub_clk_atb_sel" }, 1487 .parent_hws = (const struct clk_hw *[]) {
1488 &g12b_cpub_clk_atb_sel.hw
1489 },
864 .num_parents = 1, 1490 .num_parents = 1,
865 /* 1491 /*
866 * This clock is set by the ROM monitor code, 1492 * This clock is set by the ROM monitor code,
@@ -879,13 +1505,15 @@ static struct clk_regmap g12b_cpub_clk_axi_sel = {
879 .hw.init = &(struct clk_init_data){ 1505 .hw.init = &(struct clk_init_data){
880 .name = "cpub_clk_axi_sel", 1506 .name = "cpub_clk_axi_sel",
881 .ops = &clk_regmap_mux_ro_ops, 1507 .ops = &clk_regmap_mux_ro_ops,
882 .parent_names = (const char *[]){ "cpub_clk_div2", 1508 .parent_hws = (const struct clk_hw *[]) {
883 "cpub_clk_div3", 1509 &g12b_cpub_clk_div2.hw,
884 "cpub_clk_div4", 1510 &g12b_cpub_clk_div3.hw,
885 "cpub_clk_div5", 1511 &g12b_cpub_clk_div4.hw,
886 "cpub_clk_div6", 1512 &g12b_cpub_clk_div5.hw,
887 "cpub_clk_div7", 1513 &g12b_cpub_clk_div6.hw,
888 "cpub_clk_div8" }, 1514 &g12b_cpub_clk_div7.hw,
1515 &g12b_cpub_clk_div8.hw
1516 },
889 .num_parents = 7, 1517 .num_parents = 7,
890 }, 1518 },
891}; 1519};
@@ -899,7 +1527,9 @@ static struct clk_regmap g12b_cpub_clk_axi = {
899 .hw.init = &(struct clk_init_data) { 1527 .hw.init = &(struct clk_init_data) {
900 .name = "cpub_clk_axi", 1528 .name = "cpub_clk_axi",
901 .ops = &clk_regmap_gate_ro_ops, 1529 .ops = &clk_regmap_gate_ro_ops,
902 .parent_names = (const char *[]){ "cpub_clk_axi_sel" }, 1530 .parent_hws = (const struct clk_hw *[]) {
1531 &g12b_cpub_clk_axi_sel.hw
1532 },
903 .num_parents = 1, 1533 .num_parents = 1,
904 /* 1534 /*
905 * This clock is set by the ROM monitor code, 1535 * This clock is set by the ROM monitor code,
@@ -918,13 +1548,15 @@ static struct clk_regmap g12b_cpub_clk_trace_sel = {
918 .hw.init = &(struct clk_init_data){ 1548 .hw.init = &(struct clk_init_data){
919 .name = "cpub_clk_trace_sel", 1549 .name = "cpub_clk_trace_sel",
920 .ops = &clk_regmap_mux_ro_ops, 1550 .ops = &clk_regmap_mux_ro_ops,
921 .parent_names = (const char *[]){ "cpub_clk_div2", 1551 .parent_hws = (const struct clk_hw *[]) {
922 "cpub_clk_div3", 1552 &g12b_cpub_clk_div2.hw,
923 "cpub_clk_div4", 1553 &g12b_cpub_clk_div3.hw,
924 "cpub_clk_div5", 1554 &g12b_cpub_clk_div4.hw,
925 "cpub_clk_div6", 1555 &g12b_cpub_clk_div5.hw,
926 "cpub_clk_div7", 1556 &g12b_cpub_clk_div6.hw,
927 "cpub_clk_div8" }, 1557 &g12b_cpub_clk_div7.hw,
1558 &g12b_cpub_clk_div8.hw
1559 },
928 .num_parents = 7, 1560 .num_parents = 7,
929 }, 1561 },
930}; 1562};
@@ -938,7 +1570,9 @@ static struct clk_regmap g12b_cpub_clk_trace = {
938 .hw.init = &(struct clk_init_data) { 1570 .hw.init = &(struct clk_init_data) {
939 .name = "cpub_clk_trace", 1571 .name = "cpub_clk_trace",
940 .ops = &clk_regmap_gate_ro_ops, 1572 .ops = &clk_regmap_gate_ro_ops,
941 .parent_names = (const char *[]){ "cpub_clk_trace_sel" }, 1573 .parent_hws = (const struct clk_hw *[]) {
1574 &g12b_cpub_clk_trace_sel.hw
1575 },
942 .num_parents = 1, 1576 .num_parents = 1,
943 /* 1577 /*
944 * This clock is set by the ROM monitor code, 1578 * This clock is set by the ROM monitor code,
@@ -1003,7 +1637,9 @@ static struct clk_regmap g12a_gp0_pll_dco = {
1003 .hw.init = &(struct clk_init_data){ 1637 .hw.init = &(struct clk_init_data){
1004 .name = "gp0_pll_dco", 1638 .name = "gp0_pll_dco",
1005 .ops = &meson_clk_pll_ops, 1639 .ops = &meson_clk_pll_ops,
1006 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 1640 .parent_data = &(const struct clk_parent_data) {
1641 .fw_name = "xtal",
1642 },
1007 .num_parents = 1, 1643 .num_parents = 1,
1008 }, 1644 },
1009}; 1645};
@@ -1019,12 +1655,77 @@ static struct clk_regmap g12a_gp0_pll = {
1019 .hw.init = &(struct clk_init_data){ 1655 .hw.init = &(struct clk_init_data){
1020 .name = "gp0_pll", 1656 .name = "gp0_pll",
1021 .ops = &clk_regmap_divider_ops, 1657 .ops = &clk_regmap_divider_ops,
1022 .parent_names = (const char *[]){ "gp0_pll_dco" }, 1658 .parent_hws = (const struct clk_hw *[]) {
1659 &g12a_gp0_pll_dco.hw
1660 },
1023 .num_parents = 1, 1661 .num_parents = 1,
1024 .flags = CLK_SET_RATE_PARENT, 1662 .flags = CLK_SET_RATE_PARENT,
1025 }, 1663 },
1026}; 1664};
1027 1665
1666static struct clk_regmap sm1_gp1_pll_dco = {
1667 .data = &(struct meson_clk_pll_data){
1668 .en = {
1669 .reg_off = HHI_GP1_PLL_CNTL0,
1670 .shift = 28,
1671 .width = 1,
1672 },
1673 .m = {
1674 .reg_off = HHI_GP1_PLL_CNTL0,
1675 .shift = 0,
1676 .width = 8,
1677 },
1678 .n = {
1679 .reg_off = HHI_GP1_PLL_CNTL0,
1680 .shift = 10,
1681 .width = 5,
1682 },
1683 .frac = {
1684 .reg_off = HHI_GP1_PLL_CNTL1,
1685 .shift = 0,
1686 .width = 17,
1687 },
1688 .l = {
1689 .reg_off = HHI_GP1_PLL_CNTL0,
1690 .shift = 31,
1691 .width = 1,
1692 },
1693 .rst = {
1694 .reg_off = HHI_GP1_PLL_CNTL0,
1695 .shift = 29,
1696 .width = 1,
1697 },
1698 },
1699 .hw.init = &(struct clk_init_data){
1700 .name = "gp1_pll_dco",
1701 .ops = &meson_clk_pll_ro_ops,
1702 .parent_data = &(const struct clk_parent_data) {
1703 .fw_name = "xtal",
1704 },
1705 .num_parents = 1,
1706 /* This clock feeds the DSU, avoid disabling it */
1707 .flags = CLK_IS_CRITICAL,
1708 },
1709};
1710
1711static struct clk_regmap sm1_gp1_pll = {
1712 .data = &(struct clk_regmap_div_data){
1713 .offset = HHI_GP1_PLL_CNTL0,
1714 .shift = 16,
1715 .width = 3,
1716 .flags = (CLK_DIVIDER_POWER_OF_TWO |
1717 CLK_DIVIDER_ROUND_CLOSEST),
1718 },
1719 .hw.init = &(struct clk_init_data){
1720 .name = "gp1_pll",
1721 .ops = &clk_regmap_divider_ro_ops,
1722 .parent_hws = (const struct clk_hw *[]) {
1723 &sm1_gp1_pll_dco.hw
1724 },
1725 .num_parents = 1,
1726 },
1727};
1728
1028/* 1729/*
1029 * Internal hifi pll emulation configuration parameters 1730 * Internal hifi pll emulation configuration parameters
1030 */ 1731 */
@@ -1077,7 +1778,9 @@ static struct clk_regmap g12a_hifi_pll_dco = {
1077 .hw.init = &(struct clk_init_data){ 1778 .hw.init = &(struct clk_init_data){
1078 .name = "hifi_pll_dco", 1779 .name = "hifi_pll_dco",
1079 .ops = &meson_clk_pll_ops, 1780 .ops = &meson_clk_pll_ops,
1080 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 1781 .parent_data = &(const struct clk_parent_data) {
1782 .fw_name = "xtal",
1783 },
1081 .num_parents = 1, 1784 .num_parents = 1,
1082 }, 1785 },
1083}; 1786};
@@ -1093,7 +1796,9 @@ static struct clk_regmap g12a_hifi_pll = {
1093 .hw.init = &(struct clk_init_data){ 1796 .hw.init = &(struct clk_init_data){
1094 .name = "hifi_pll", 1797 .name = "hifi_pll",
1095 .ops = &clk_regmap_divider_ops, 1798 .ops = &clk_regmap_divider_ops,
1096 .parent_names = (const char *[]){ "hifi_pll_dco" }, 1799 .parent_hws = (const struct clk_hw *[]) {
1800 &g12a_hifi_pll_dco.hw
1801 },
1097 .num_parents = 1, 1802 .num_parents = 1,
1098 .flags = CLK_SET_RATE_PARENT, 1803 .flags = CLK_SET_RATE_PARENT,
1099 }, 1804 },
@@ -1164,7 +1869,9 @@ static struct clk_regmap g12a_pcie_pll_dco = {
1164 .hw.init = &(struct clk_init_data){ 1869 .hw.init = &(struct clk_init_data){
1165 .name = "pcie_pll_dco", 1870 .name = "pcie_pll_dco",
1166 .ops = &meson_clk_pcie_pll_ops, 1871 .ops = &meson_clk_pcie_pll_ops,
1167 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 1872 .parent_data = &(const struct clk_parent_data) {
1873 .fw_name = "xtal",
1874 },
1168 .num_parents = 1, 1875 .num_parents = 1,
1169 }, 1876 },
1170}; 1877};
@@ -1175,7 +1882,9 @@ static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
1175 .hw.init = &(struct clk_init_data){ 1882 .hw.init = &(struct clk_init_data){
1176 .name = "pcie_pll_dco_div2", 1883 .name = "pcie_pll_dco_div2",
1177 .ops = &clk_fixed_factor_ops, 1884 .ops = &clk_fixed_factor_ops,
1178 .parent_names = (const char *[]){ "pcie_pll_dco" }, 1885 .parent_hws = (const struct clk_hw *[]) {
1886 &g12a_pcie_pll_dco.hw
1887 },
1179 .num_parents = 1, 1888 .num_parents = 1,
1180 .flags = CLK_SET_RATE_PARENT, 1889 .flags = CLK_SET_RATE_PARENT,
1181 }, 1890 },
@@ -1193,7 +1902,9 @@ static struct clk_regmap g12a_pcie_pll_od = {
1193 .hw.init = &(struct clk_init_data){ 1902 .hw.init = &(struct clk_init_data){
1194 .name = "pcie_pll_od", 1903 .name = "pcie_pll_od",
1195 .ops = &clk_regmap_divider_ops, 1904 .ops = &clk_regmap_divider_ops,
1196 .parent_names = (const char *[]){ "pcie_pll_dco_div2" }, 1905 .parent_hws = (const struct clk_hw *[]) {
1906 &g12a_pcie_pll_dco_div2.hw
1907 },
1197 .num_parents = 1, 1908 .num_parents = 1,
1198 .flags = CLK_SET_RATE_PARENT, 1909 .flags = CLK_SET_RATE_PARENT,
1199 }, 1910 },
@@ -1205,7 +1916,9 @@ static struct clk_fixed_factor g12a_pcie_pll = {
1205 .hw.init = &(struct clk_init_data){ 1916 .hw.init = &(struct clk_init_data){
1206 .name = "pcie_pll_pll", 1917 .name = "pcie_pll_pll",
1207 .ops = &clk_fixed_factor_ops, 1918 .ops = &clk_fixed_factor_ops,
1208 .parent_names = (const char *[]){ "pcie_pll_od" }, 1919 .parent_hws = (const struct clk_hw *[]) {
1920 &g12a_pcie_pll_od.hw
1921 },
1209 .num_parents = 1, 1922 .num_parents = 1,
1210 .flags = CLK_SET_RATE_PARENT, 1923 .flags = CLK_SET_RATE_PARENT,
1211 }, 1924 },
@@ -1247,7 +1960,9 @@ static struct clk_regmap g12a_hdmi_pll_dco = {
1247 .hw.init = &(struct clk_init_data){ 1960 .hw.init = &(struct clk_init_data){
1248 .name = "hdmi_pll_dco", 1961 .name = "hdmi_pll_dco",
1249 .ops = &meson_clk_pll_ro_ops, 1962 .ops = &meson_clk_pll_ro_ops,
1250 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 1963 .parent_data = &(const struct clk_parent_data) {
1964 .fw_name = "xtal",
1965 },
1251 .num_parents = 1, 1966 .num_parents = 1,
1252 /* 1967 /*
1253 * Display directly handle hdmi pll registers ATM, we need 1968 * Display directly handle hdmi pll registers ATM, we need
@@ -1267,7 +1982,9 @@ static struct clk_regmap g12a_hdmi_pll_od = {
1267 .hw.init = &(struct clk_init_data){ 1982 .hw.init = &(struct clk_init_data){
1268 .name = "hdmi_pll_od", 1983 .name = "hdmi_pll_od",
1269 .ops = &clk_regmap_divider_ro_ops, 1984 .ops = &clk_regmap_divider_ro_ops,
1270 .parent_names = (const char *[]){ "hdmi_pll_dco" }, 1985 .parent_hws = (const struct clk_hw *[]) {
1986 &g12a_hdmi_pll_dco.hw
1987 },
1271 .num_parents = 1, 1988 .num_parents = 1,
1272 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 1989 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
1273 }, 1990 },
@@ -1283,7 +2000,9 @@ static struct clk_regmap g12a_hdmi_pll_od2 = {
1283 .hw.init = &(struct clk_init_data){ 2000 .hw.init = &(struct clk_init_data){
1284 .name = "hdmi_pll_od2", 2001 .name = "hdmi_pll_od2",
1285 .ops = &clk_regmap_divider_ro_ops, 2002 .ops = &clk_regmap_divider_ro_ops,
1286 .parent_names = (const char *[]){ "hdmi_pll_od" }, 2003 .parent_hws = (const struct clk_hw *[]) {
2004 &g12a_hdmi_pll_od.hw
2005 },
1287 .num_parents = 1, 2006 .num_parents = 1,
1288 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 2007 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
1289 }, 2008 },
@@ -1299,77 +2018,21 @@ static struct clk_regmap g12a_hdmi_pll = {
1299 .hw.init = &(struct clk_init_data){ 2018 .hw.init = &(struct clk_init_data){
1300 .name = "hdmi_pll", 2019 .name = "hdmi_pll",
1301 .ops = &clk_regmap_divider_ro_ops, 2020 .ops = &clk_regmap_divider_ro_ops,
1302 .parent_names = (const char *[]){ "hdmi_pll_od2" }, 2021 .parent_hws = (const struct clk_hw *[]) {
2022 &g12a_hdmi_pll_od2.hw
2023 },
1303 .num_parents = 1, 2024 .num_parents = 1,
1304 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 2025 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
1305 }, 2026 },
1306}; 2027};
1307 2028
1308static struct clk_fixed_factor g12a_fclk_div2_div = {
1309 .mult = 1,
1310 .div = 2,
1311 .hw.init = &(struct clk_init_data){
1312 .name = "fclk_div2_div",
1313 .ops = &clk_fixed_factor_ops,
1314 .parent_names = (const char *[]){ "fixed_pll" },
1315 .num_parents = 1,
1316 },
1317};
1318
1319static struct clk_regmap g12a_fclk_div2 = {
1320 .data = &(struct clk_regmap_gate_data){
1321 .offset = HHI_FIX_PLL_CNTL1,
1322 .bit_idx = 24,
1323 },
1324 .hw.init = &(struct clk_init_data){
1325 .name = "fclk_div2",
1326 .ops = &clk_regmap_gate_ops,
1327 .parent_names = (const char *[]){ "fclk_div2_div" },
1328 .num_parents = 1,
1329 },
1330};
1331
1332static struct clk_fixed_factor g12a_fclk_div3_div = {
1333 .mult = 1,
1334 .div = 3,
1335 .hw.init = &(struct clk_init_data){
1336 .name = "fclk_div3_div",
1337 .ops = &clk_fixed_factor_ops,
1338 .parent_names = (const char *[]){ "fixed_pll" },
1339 .num_parents = 1,
1340 },
1341};
1342
1343static struct clk_regmap g12a_fclk_div3 = {
1344 .data = &(struct clk_regmap_gate_data){
1345 .offset = HHI_FIX_PLL_CNTL1,
1346 .bit_idx = 20,
1347 },
1348 .hw.init = &(struct clk_init_data){
1349 .name = "fclk_div3",
1350 .ops = &clk_regmap_gate_ops,
1351 .parent_names = (const char *[]){ "fclk_div3_div" },
1352 .num_parents = 1,
1353 /*
1354 * This clock is used by the resident firmware and is required
1355 * by the platform to operate correctly.
1356 * Until the following condition are met, we need this clock to
1357 * be marked as critical:
1358 * a) Mark the clock used by a firmware resource, if possible
1359 * b) CCF has a clock hand-off mechanism to make the sure the
1360 * clock stays on until the proper driver comes along
1361 */
1362 .flags = CLK_IS_CRITICAL,
1363 },
1364};
1365
1366static struct clk_fixed_factor g12a_fclk_div4_div = { 2029static struct clk_fixed_factor g12a_fclk_div4_div = {
1367 .mult = 1, 2030 .mult = 1,
1368 .div = 4, 2031 .div = 4,
1369 .hw.init = &(struct clk_init_data){ 2032 .hw.init = &(struct clk_init_data){
1370 .name = "fclk_div4_div", 2033 .name = "fclk_div4_div",
1371 .ops = &clk_fixed_factor_ops, 2034 .ops = &clk_fixed_factor_ops,
1372 .parent_names = (const char *[]){ "fixed_pll" }, 2035 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
1373 .num_parents = 1, 2036 .num_parents = 1,
1374 }, 2037 },
1375}; 2038};
@@ -1382,7 +2045,9 @@ static struct clk_regmap g12a_fclk_div4 = {
1382 .hw.init = &(struct clk_init_data){ 2045 .hw.init = &(struct clk_init_data){
1383 .name = "fclk_div4", 2046 .name = "fclk_div4",
1384 .ops = &clk_regmap_gate_ops, 2047 .ops = &clk_regmap_gate_ops,
1385 .parent_names = (const char *[]){ "fclk_div4_div" }, 2048 .parent_hws = (const struct clk_hw *[]) {
2049 &g12a_fclk_div4_div.hw
2050 },
1386 .num_parents = 1, 2051 .num_parents = 1,
1387 }, 2052 },
1388}; 2053};
@@ -1393,7 +2058,7 @@ static struct clk_fixed_factor g12a_fclk_div5_div = {
1393 .hw.init = &(struct clk_init_data){ 2058 .hw.init = &(struct clk_init_data){
1394 .name = "fclk_div5_div", 2059 .name = "fclk_div5_div",
1395 .ops = &clk_fixed_factor_ops, 2060 .ops = &clk_fixed_factor_ops,
1396 .parent_names = (const char *[]){ "fixed_pll" }, 2061 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
1397 .num_parents = 1, 2062 .num_parents = 1,
1398 }, 2063 },
1399}; 2064};
@@ -1406,7 +2071,9 @@ static struct clk_regmap g12a_fclk_div5 = {
1406 .hw.init = &(struct clk_init_data){ 2071 .hw.init = &(struct clk_init_data){
1407 .name = "fclk_div5", 2072 .name = "fclk_div5",
1408 .ops = &clk_regmap_gate_ops, 2073 .ops = &clk_regmap_gate_ops,
1409 .parent_names = (const char *[]){ "fclk_div5_div" }, 2074 .parent_hws = (const struct clk_hw *[]) {
2075 &g12a_fclk_div5_div.hw
2076 },
1410 .num_parents = 1, 2077 .num_parents = 1,
1411 }, 2078 },
1412}; 2079};
@@ -1417,7 +2084,7 @@ static struct clk_fixed_factor g12a_fclk_div7_div = {
1417 .hw.init = &(struct clk_init_data){ 2084 .hw.init = &(struct clk_init_data){
1418 .name = "fclk_div7_div", 2085 .name = "fclk_div7_div",
1419 .ops = &clk_fixed_factor_ops, 2086 .ops = &clk_fixed_factor_ops,
1420 .parent_names = (const char *[]){ "fixed_pll" }, 2087 .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
1421 .num_parents = 1, 2088 .num_parents = 1,
1422 }, 2089 },
1423}; 2090};
@@ -1430,7 +2097,9 @@ static struct clk_regmap g12a_fclk_div7 = {
1430 .hw.init = &(struct clk_init_data){ 2097 .hw.init = &(struct clk_init_data){
1431 .name = "fclk_div7", 2098 .name = "fclk_div7",
1432 .ops = &clk_regmap_gate_ops, 2099 .ops = &clk_regmap_gate_ops,
1433 .parent_names = (const char *[]){ "fclk_div7_div" }, 2100 .parent_hws = (const struct clk_hw *[]) {
2101 &g12a_fclk_div7_div.hw
2102 },
1434 .num_parents = 1, 2103 .num_parents = 1,
1435 }, 2104 },
1436}; 2105};
@@ -1441,7 +2110,9 @@ static struct clk_fixed_factor g12a_fclk_div2p5_div = {
1441 .hw.init = &(struct clk_init_data){ 2110 .hw.init = &(struct clk_init_data){
1442 .name = "fclk_div2p5_div", 2111 .name = "fclk_div2p5_div",
1443 .ops = &clk_fixed_factor_ops, 2112 .ops = &clk_fixed_factor_ops,
1444 .parent_names = (const char *[]){ "fixed_pll_dco" }, 2113 .parent_hws = (const struct clk_hw *[]) {
2114 &g12a_fixed_pll_dco.hw
2115 },
1445 .num_parents = 1, 2116 .num_parents = 1,
1446 }, 2117 },
1447}; 2118};
@@ -1454,7 +2125,9 @@ static struct clk_regmap g12a_fclk_div2p5 = {
1454 .hw.init = &(struct clk_init_data){ 2125 .hw.init = &(struct clk_init_data){
1455 .name = "fclk_div2p5", 2126 .name = "fclk_div2p5",
1456 .ops = &clk_regmap_gate_ops, 2127 .ops = &clk_regmap_gate_ops,
1457 .parent_names = (const char *[]){ "fclk_div2p5_div" }, 2128 .parent_hws = (const struct clk_hw *[]) {
2129 &g12a_fclk_div2p5_div.hw
2130 },
1458 .num_parents = 1, 2131 .num_parents = 1,
1459 }, 2132 },
1460}; 2133};
@@ -1465,7 +2138,9 @@ static struct clk_fixed_factor g12a_mpll_50m_div = {
1465 .hw.init = &(struct clk_init_data){ 2138 .hw.init = &(struct clk_init_data){
1466 .name = "mpll_50m_div", 2139 .name = "mpll_50m_div",
1467 .ops = &clk_fixed_factor_ops, 2140 .ops = &clk_fixed_factor_ops,
1468 .parent_names = (const char *[]){ "fixed_pll_dco" }, 2141 .parent_hws = (const struct clk_hw *[]) {
2142 &g12a_fixed_pll_dco.hw
2143 },
1469 .num_parents = 1, 2144 .num_parents = 1,
1470 }, 2145 },
1471}; 2146};
@@ -1479,8 +2154,10 @@ static struct clk_regmap g12a_mpll_50m = {
1479 .hw.init = &(struct clk_init_data){ 2154 .hw.init = &(struct clk_init_data){
1480 .name = "mpll_50m", 2155 .name = "mpll_50m",
1481 .ops = &clk_regmap_mux_ro_ops, 2156 .ops = &clk_regmap_mux_ro_ops,
1482 .parent_names = (const char *[]){ IN_PREFIX "xtal", 2157 .parent_data = (const struct clk_parent_data []) {
1483 "mpll_50m_div" }, 2158 { .fw_name = "xtal", },
2159 { .hw = &g12a_mpll_50m_div.hw },
2160 },
1484 .num_parents = 2, 2161 .num_parents = 2,
1485 }, 2162 },
1486}; 2163};
@@ -1491,7 +2168,9 @@ static struct clk_fixed_factor g12a_mpll_prediv = {
1491 .hw.init = &(struct clk_init_data){ 2168 .hw.init = &(struct clk_init_data){
1492 .name = "mpll_prediv", 2169 .name = "mpll_prediv",
1493 .ops = &clk_fixed_factor_ops, 2170 .ops = &clk_fixed_factor_ops,
1494 .parent_names = (const char *[]){ "fixed_pll_dco" }, 2171 .parent_hws = (const struct clk_hw *[]) {
2172 &g12a_fixed_pll_dco.hw
2173 },
1495 .num_parents = 1, 2174 .num_parents = 1,
1496 }, 2175 },
1497}; 2176};
@@ -1529,7 +2208,9 @@ static struct clk_regmap g12a_mpll0_div = {
1529 .hw.init = &(struct clk_init_data){ 2208 .hw.init = &(struct clk_init_data){
1530 .name = "mpll0_div", 2209 .name = "mpll0_div",
1531 .ops = &meson_clk_mpll_ops, 2210 .ops = &meson_clk_mpll_ops,
1532 .parent_names = (const char *[]){ "mpll_prediv" }, 2211 .parent_hws = (const struct clk_hw *[]) {
2212 &g12a_mpll_prediv.hw
2213 },
1533 .num_parents = 1, 2214 .num_parents = 1,
1534 }, 2215 },
1535}; 2216};
@@ -1542,7 +2223,7 @@ static struct clk_regmap g12a_mpll0 = {
1542 .hw.init = &(struct clk_init_data){ 2223 .hw.init = &(struct clk_init_data){
1543 .name = "mpll0", 2224 .name = "mpll0",
1544 .ops = &clk_regmap_gate_ops, 2225 .ops = &clk_regmap_gate_ops,
1545 .parent_names = (const char *[]){ "mpll0_div" }, 2226 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },
1546 .num_parents = 1, 2227 .num_parents = 1,
1547 .flags = CLK_SET_RATE_PARENT, 2228 .flags = CLK_SET_RATE_PARENT,
1548 }, 2229 },
@@ -1581,7 +2262,9 @@ static struct clk_regmap g12a_mpll1_div = {
1581 .hw.init = &(struct clk_init_data){ 2262 .hw.init = &(struct clk_init_data){
1582 .name = "mpll1_div", 2263 .name = "mpll1_div",
1583 .ops = &meson_clk_mpll_ops, 2264 .ops = &meson_clk_mpll_ops,
1584 .parent_names = (const char *[]){ "mpll_prediv" }, 2265 .parent_hws = (const struct clk_hw *[]) {
2266 &g12a_mpll_prediv.hw
2267 },
1585 .num_parents = 1, 2268 .num_parents = 1,
1586 }, 2269 },
1587}; 2270};
@@ -1594,7 +2277,7 @@ static struct clk_regmap g12a_mpll1 = {
1594 .hw.init = &(struct clk_init_data){ 2277 .hw.init = &(struct clk_init_data){
1595 .name = "mpll1", 2278 .name = "mpll1",
1596 .ops = &clk_regmap_gate_ops, 2279 .ops = &clk_regmap_gate_ops,
1597 .parent_names = (const char *[]){ "mpll1_div" }, 2280 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },
1598 .num_parents = 1, 2281 .num_parents = 1,
1599 .flags = CLK_SET_RATE_PARENT, 2282 .flags = CLK_SET_RATE_PARENT,
1600 }, 2283 },
@@ -1633,7 +2316,9 @@ static struct clk_regmap g12a_mpll2_div = {
1633 .hw.init = &(struct clk_init_data){ 2316 .hw.init = &(struct clk_init_data){
1634 .name = "mpll2_div", 2317 .name = "mpll2_div",
1635 .ops = &meson_clk_mpll_ops, 2318 .ops = &meson_clk_mpll_ops,
1636 .parent_names = (const char *[]){ "mpll_prediv" }, 2319 .parent_hws = (const struct clk_hw *[]) {
2320 &g12a_mpll_prediv.hw
2321 },
1637 .num_parents = 1, 2322 .num_parents = 1,
1638 }, 2323 },
1639}; 2324};
@@ -1646,7 +2331,7 @@ static struct clk_regmap g12a_mpll2 = {
1646 .hw.init = &(struct clk_init_data){ 2331 .hw.init = &(struct clk_init_data){
1647 .name = "mpll2", 2332 .name = "mpll2",
1648 .ops = &clk_regmap_gate_ops, 2333 .ops = &clk_regmap_gate_ops,
1649 .parent_names = (const char *[]){ "mpll2_div" }, 2334 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },
1650 .num_parents = 1, 2335 .num_parents = 1,
1651 .flags = CLK_SET_RATE_PARENT, 2336 .flags = CLK_SET_RATE_PARENT,
1652 }, 2337 },
@@ -1685,7 +2370,9 @@ static struct clk_regmap g12a_mpll3_div = {
1685 .hw.init = &(struct clk_init_data){ 2370 .hw.init = &(struct clk_init_data){
1686 .name = "mpll3_div", 2371 .name = "mpll3_div",
1687 .ops = &meson_clk_mpll_ops, 2372 .ops = &meson_clk_mpll_ops,
1688 .parent_names = (const char *[]){ "mpll_prediv" }, 2373 .parent_hws = (const struct clk_hw *[]) {
2374 &g12a_mpll_prediv.hw
2375 },
1689 .num_parents = 1, 2376 .num_parents = 1,
1690 }, 2377 },
1691}; 2378};
@@ -1698,16 +2385,21 @@ static struct clk_regmap g12a_mpll3 = {
1698 .hw.init = &(struct clk_init_data){ 2385 .hw.init = &(struct clk_init_data){
1699 .name = "mpll3", 2386 .name = "mpll3",
1700 .ops = &clk_regmap_gate_ops, 2387 .ops = &clk_regmap_gate_ops,
1701 .parent_names = (const char *[]){ "mpll3_div" }, 2388 .parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },
1702 .num_parents = 1, 2389 .num_parents = 1,
1703 .flags = CLK_SET_RATE_PARENT, 2390 .flags = CLK_SET_RATE_PARENT,
1704 }, 2391 },
1705}; 2392};
1706 2393
1707static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 2394static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
1708static const char * const clk81_parent_names[] = { 2395static const struct clk_parent_data clk81_parent_data[] = {
1709 IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", 2396 { .fw_name = "xtal", },
1710 "fclk_div3", "fclk_div5" 2397 { .hw = &g12a_fclk_div7.hw },
2398 { .hw = &g12a_mpll1.hw },
2399 { .hw = &g12a_mpll2.hw },
2400 { .hw = &g12a_fclk_div4.hw },
2401 { .hw = &g12a_fclk_div3.hw },
2402 { .hw = &g12a_fclk_div5.hw },
1711}; 2403};
1712 2404
1713static struct clk_regmap g12a_mpeg_clk_sel = { 2405static struct clk_regmap g12a_mpeg_clk_sel = {
@@ -1720,8 +2412,8 @@ static struct clk_regmap g12a_mpeg_clk_sel = {
1720 .hw.init = &(struct clk_init_data){ 2412 .hw.init = &(struct clk_init_data){
1721 .name = "mpeg_clk_sel", 2413 .name = "mpeg_clk_sel",
1722 .ops = &clk_regmap_mux_ro_ops, 2414 .ops = &clk_regmap_mux_ro_ops,
1723 .parent_names = clk81_parent_names, 2415 .parent_data = clk81_parent_data,
1724 .num_parents = ARRAY_SIZE(clk81_parent_names), 2416 .num_parents = ARRAY_SIZE(clk81_parent_data),
1725 }, 2417 },
1726}; 2418};
1727 2419
@@ -1734,7 +2426,9 @@ static struct clk_regmap g12a_mpeg_clk_div = {
1734 .hw.init = &(struct clk_init_data){ 2426 .hw.init = &(struct clk_init_data){
1735 .name = "mpeg_clk_div", 2427 .name = "mpeg_clk_div",
1736 .ops = &clk_regmap_divider_ops, 2428 .ops = &clk_regmap_divider_ops,
1737 .parent_names = (const char *[]){ "mpeg_clk_sel" }, 2429 .parent_hws = (const struct clk_hw *[]) {
2430 &g12a_mpeg_clk_sel.hw
2431 },
1738 .num_parents = 1, 2432 .num_parents = 1,
1739 .flags = CLK_SET_RATE_PARENT, 2433 .flags = CLK_SET_RATE_PARENT,
1740 }, 2434 },
@@ -1748,15 +2442,20 @@ static struct clk_regmap g12a_clk81 = {
1748 .hw.init = &(struct clk_init_data){ 2442 .hw.init = &(struct clk_init_data){
1749 .name = "clk81", 2443 .name = "clk81",
1750 .ops = &clk_regmap_gate_ops, 2444 .ops = &clk_regmap_gate_ops,
1751 .parent_names = (const char *[]){ "mpeg_clk_div" }, 2445 .parent_hws = (const struct clk_hw *[]) {
2446 &g12a_mpeg_clk_div.hw
2447 },
1752 .num_parents = 1, 2448 .num_parents = 1,
1753 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL), 2449 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
1754 }, 2450 },
1755}; 2451};
1756 2452
1757static const char * const g12a_sd_emmc_clk0_parent_names[] = { 2453static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] = {
1758 IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7", 2454 { .fw_name = "xtal", },
1759 2455 { .hw = &g12a_fclk_div2.hw },
2456 { .hw = &g12a_fclk_div3.hw },
2457 { .hw = &g12a_fclk_div5.hw },
2458 { .hw = &g12a_fclk_div7.hw },
1760 /* 2459 /*
1761 * Following these parent clocks, we should also have had mpll2, mpll3 2460 * Following these parent clocks, we should also have had mpll2, mpll3
1762 * and gp0_pll but these clocks are too precious to be used here. All 2461 * and gp0_pll but these clocks are too precious to be used here. All
@@ -1775,8 +2474,8 @@ static struct clk_regmap g12a_sd_emmc_a_clk0_sel = {
1775 .hw.init = &(struct clk_init_data) { 2474 .hw.init = &(struct clk_init_data) {
1776 .name = "sd_emmc_a_clk0_sel", 2475 .name = "sd_emmc_a_clk0_sel",
1777 .ops = &clk_regmap_mux_ops, 2476 .ops = &clk_regmap_mux_ops,
1778 .parent_names = g12a_sd_emmc_clk0_parent_names, 2477 .parent_data = g12a_sd_emmc_clk0_parent_data,
1779 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names), 2478 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
1780 .flags = CLK_SET_RATE_PARENT, 2479 .flags = CLK_SET_RATE_PARENT,
1781 }, 2480 },
1782}; 2481};
@@ -1790,7 +2489,9 @@ static struct clk_regmap g12a_sd_emmc_a_clk0_div = {
1790 .hw.init = &(struct clk_init_data) { 2489 .hw.init = &(struct clk_init_data) {
1791 .name = "sd_emmc_a_clk0_div", 2490 .name = "sd_emmc_a_clk0_div",
1792 .ops = &clk_regmap_divider_ops, 2491 .ops = &clk_regmap_divider_ops,
1793 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" }, 2492 .parent_hws = (const struct clk_hw *[]) {
2493 &g12a_sd_emmc_a_clk0_sel.hw
2494 },
1794 .num_parents = 1, 2495 .num_parents = 1,
1795 .flags = CLK_SET_RATE_PARENT, 2496 .flags = CLK_SET_RATE_PARENT,
1796 }, 2497 },
@@ -1804,7 +2505,9 @@ static struct clk_regmap g12a_sd_emmc_a_clk0 = {
1804 .hw.init = &(struct clk_init_data){ 2505 .hw.init = &(struct clk_init_data){
1805 .name = "sd_emmc_a_clk0", 2506 .name = "sd_emmc_a_clk0",
1806 .ops = &clk_regmap_gate_ops, 2507 .ops = &clk_regmap_gate_ops,
1807 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" }, 2508 .parent_hws = (const struct clk_hw *[]) {
2509 &g12a_sd_emmc_a_clk0_div.hw
2510 },
1808 .num_parents = 1, 2511 .num_parents = 1,
1809 .flags = CLK_SET_RATE_PARENT, 2512 .flags = CLK_SET_RATE_PARENT,
1810 }, 2513 },
@@ -1820,8 +2523,8 @@ static struct clk_regmap g12a_sd_emmc_b_clk0_sel = {
1820 .hw.init = &(struct clk_init_data) { 2523 .hw.init = &(struct clk_init_data) {
1821 .name = "sd_emmc_b_clk0_sel", 2524 .name = "sd_emmc_b_clk0_sel",
1822 .ops = &clk_regmap_mux_ops, 2525 .ops = &clk_regmap_mux_ops,
1823 .parent_names = g12a_sd_emmc_clk0_parent_names, 2526 .parent_data = g12a_sd_emmc_clk0_parent_data,
1824 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names), 2527 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
1825 .flags = CLK_SET_RATE_PARENT, 2528 .flags = CLK_SET_RATE_PARENT,
1826 }, 2529 },
1827}; 2530};
@@ -1835,7 +2538,9 @@ static struct clk_regmap g12a_sd_emmc_b_clk0_div = {
1835 .hw.init = &(struct clk_init_data) { 2538 .hw.init = &(struct clk_init_data) {
1836 .name = "sd_emmc_b_clk0_div", 2539 .name = "sd_emmc_b_clk0_div",
1837 .ops = &clk_regmap_divider_ops, 2540 .ops = &clk_regmap_divider_ops,
1838 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, 2541 .parent_hws = (const struct clk_hw *[]) {
2542 &g12a_sd_emmc_b_clk0_sel.hw
2543 },
1839 .num_parents = 1, 2544 .num_parents = 1,
1840 .flags = CLK_SET_RATE_PARENT, 2545 .flags = CLK_SET_RATE_PARENT,
1841 }, 2546 },
@@ -1849,7 +2554,9 @@ static struct clk_regmap g12a_sd_emmc_b_clk0 = {
1849 .hw.init = &(struct clk_init_data){ 2554 .hw.init = &(struct clk_init_data){
1850 .name = "sd_emmc_b_clk0", 2555 .name = "sd_emmc_b_clk0",
1851 .ops = &clk_regmap_gate_ops, 2556 .ops = &clk_regmap_gate_ops,
1852 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" }, 2557 .parent_hws = (const struct clk_hw *[]) {
2558 &g12a_sd_emmc_b_clk0_div.hw
2559 },
1853 .num_parents = 1, 2560 .num_parents = 1,
1854 .flags = CLK_SET_RATE_PARENT, 2561 .flags = CLK_SET_RATE_PARENT,
1855 }, 2562 },
@@ -1865,8 +2572,8 @@ static struct clk_regmap g12a_sd_emmc_c_clk0_sel = {
1865 .hw.init = &(struct clk_init_data) { 2572 .hw.init = &(struct clk_init_data) {
1866 .name = "sd_emmc_c_clk0_sel", 2573 .name = "sd_emmc_c_clk0_sel",
1867 .ops = &clk_regmap_mux_ops, 2574 .ops = &clk_regmap_mux_ops,
1868 .parent_names = g12a_sd_emmc_clk0_parent_names, 2575 .parent_data = g12a_sd_emmc_clk0_parent_data,
1869 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names), 2576 .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
1870 .flags = CLK_SET_RATE_PARENT, 2577 .flags = CLK_SET_RATE_PARENT,
1871 }, 2578 },
1872}; 2579};
@@ -1880,7 +2587,9 @@ static struct clk_regmap g12a_sd_emmc_c_clk0_div = {
1880 .hw.init = &(struct clk_init_data) { 2587 .hw.init = &(struct clk_init_data) {
1881 .name = "sd_emmc_c_clk0_div", 2588 .name = "sd_emmc_c_clk0_div",
1882 .ops = &clk_regmap_divider_ops, 2589 .ops = &clk_regmap_divider_ops,
1883 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, 2590 .parent_hws = (const struct clk_hw *[]) {
2591 &g12a_sd_emmc_c_clk0_sel.hw
2592 },
1884 .num_parents = 1, 2593 .num_parents = 1,
1885 .flags = CLK_SET_RATE_PARENT, 2594 .flags = CLK_SET_RATE_PARENT,
1886 }, 2595 },
@@ -1894,17 +2603,89 @@ static struct clk_regmap g12a_sd_emmc_c_clk0 = {
1894 .hw.init = &(struct clk_init_data){ 2603 .hw.init = &(struct clk_init_data){
1895 .name = "sd_emmc_c_clk0", 2604 .name = "sd_emmc_c_clk0",
1896 .ops = &clk_regmap_gate_ops, 2605 .ops = &clk_regmap_gate_ops,
1897 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" }, 2606 .parent_hws = (const struct clk_hw *[]) {
2607 &g12a_sd_emmc_c_clk0_div.hw
2608 },
1898 .num_parents = 1, 2609 .num_parents = 1,
1899 .flags = CLK_SET_RATE_PARENT, 2610 .flags = CLK_SET_RATE_PARENT,
1900 }, 2611 },
1901}; 2612};
1902 2613
2614/* Video Clocks */
2615
2616static struct clk_regmap g12a_vid_pll_div = {
2617 .data = &(struct meson_vid_pll_div_data){
2618 .val = {
2619 .reg_off = HHI_VID_PLL_CLK_DIV,
2620 .shift = 0,
2621 .width = 15,
2622 },
2623 .sel = {
2624 .reg_off = HHI_VID_PLL_CLK_DIV,
2625 .shift = 16,
2626 .width = 2,
2627 },
2628 },
2629 .hw.init = &(struct clk_init_data) {
2630 .name = "vid_pll_div",
2631 .ops = &meson_vid_pll_div_ro_ops,
2632 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },
2633 .num_parents = 1,
2634 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2635 },
2636};
2637
2638static const struct clk_hw *g12a_vid_pll_parent_hws[] = {
2639 &g12a_vid_pll_div.hw,
2640 &g12a_hdmi_pll.hw,
2641};
2642
2643static struct clk_regmap g12a_vid_pll_sel = {
2644 .data = &(struct clk_regmap_mux_data){
2645 .offset = HHI_VID_PLL_CLK_DIV,
2646 .mask = 0x1,
2647 .shift = 18,
2648 },
2649 .hw.init = &(struct clk_init_data){
2650 .name = "vid_pll_sel",
2651 .ops = &clk_regmap_mux_ops,
2652 /*
2653 * bit 18 selects from 2 possible parents:
2654 * vid_pll_div or hdmi_pll
2655 */
2656 .parent_hws = g12a_vid_pll_parent_hws,
2657 .num_parents = ARRAY_SIZE(g12a_vid_pll_parent_hws),
2658 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2659 },
2660};
2661
2662static struct clk_regmap g12a_vid_pll = {
2663 .data = &(struct clk_regmap_gate_data){
2664 .offset = HHI_VID_PLL_CLK_DIV,
2665 .bit_idx = 19,
2666 },
2667 .hw.init = &(struct clk_init_data) {
2668 .name = "vid_pll",
2669 .ops = &clk_regmap_gate_ops,
2670 .parent_hws = (const struct clk_hw *[]) {
2671 &g12a_vid_pll_sel.hw
2672 },
2673 .num_parents = 1,
2674 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2675 },
2676};
2677
1903/* VPU Clock */ 2678/* VPU Clock */
1904 2679
1905static const char * const g12a_vpu_parent_names[] = { 2680static const struct clk_hw *g12a_vpu_parent_hws[] = {
1906 "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7", 2681 &g12a_fclk_div3.hw,
1907 "mpll1", "vid_pll", "hifi_pll", "gp0_pll", 2682 &g12a_fclk_div4.hw,
2683 &g12a_fclk_div5.hw,
2684 &g12a_fclk_div7.hw,
2685 &g12a_mpll1.hw,
2686 &g12a_vid_pll.hw,
2687 &g12a_hifi_pll.hw,
2688 &g12a_gp0_pll.hw,
1908}; 2689};
1909 2690
1910static struct clk_regmap g12a_vpu_0_sel = { 2691static struct clk_regmap g12a_vpu_0_sel = {
@@ -1916,8 +2697,8 @@ static struct clk_regmap g12a_vpu_0_sel = {
1916 .hw.init = &(struct clk_init_data){ 2697 .hw.init = &(struct clk_init_data){
1917 .name = "vpu_0_sel", 2698 .name = "vpu_0_sel",
1918 .ops = &clk_regmap_mux_ops, 2699 .ops = &clk_regmap_mux_ops,
1919 .parent_names = g12a_vpu_parent_names, 2700 .parent_hws = g12a_vpu_parent_hws,
1920 .num_parents = ARRAY_SIZE(g12a_vpu_parent_names), 2701 .num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
1921 .flags = CLK_SET_RATE_NO_REPARENT, 2702 .flags = CLK_SET_RATE_NO_REPARENT,
1922 }, 2703 },
1923}; 2704};
@@ -1931,7 +2712,7 @@ static struct clk_regmap g12a_vpu_0_div = {
1931 .hw.init = &(struct clk_init_data){ 2712 .hw.init = &(struct clk_init_data){
1932 .name = "vpu_0_div", 2713 .name = "vpu_0_div",
1933 .ops = &clk_regmap_divider_ops, 2714 .ops = &clk_regmap_divider_ops,
1934 .parent_names = (const char *[]){ "vpu_0_sel" }, 2715 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },
1935 .num_parents = 1, 2716 .num_parents = 1,
1936 .flags = CLK_SET_RATE_PARENT, 2717 .flags = CLK_SET_RATE_PARENT,
1937 }, 2718 },
@@ -1945,7 +2726,7 @@ static struct clk_regmap g12a_vpu_0 = {
1945 .hw.init = &(struct clk_init_data) { 2726 .hw.init = &(struct clk_init_data) {
1946 .name = "vpu_0", 2727 .name = "vpu_0",
1947 .ops = &clk_regmap_gate_ops, 2728 .ops = &clk_regmap_gate_ops,
1948 .parent_names = (const char *[]){ "vpu_0_div" }, 2729 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },
1949 .num_parents = 1, 2730 .num_parents = 1,
1950 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2731 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1951 }, 2732 },
@@ -1960,8 +2741,8 @@ static struct clk_regmap g12a_vpu_1_sel = {
1960 .hw.init = &(struct clk_init_data){ 2741 .hw.init = &(struct clk_init_data){
1961 .name = "vpu_1_sel", 2742 .name = "vpu_1_sel",
1962 .ops = &clk_regmap_mux_ops, 2743 .ops = &clk_regmap_mux_ops,
1963 .parent_names = g12a_vpu_parent_names, 2744 .parent_hws = g12a_vpu_parent_hws,
1964 .num_parents = ARRAY_SIZE(g12a_vpu_parent_names), 2745 .num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
1965 .flags = CLK_SET_RATE_NO_REPARENT, 2746 .flags = CLK_SET_RATE_NO_REPARENT,
1966 }, 2747 },
1967}; 2748};
@@ -1975,7 +2756,7 @@ static struct clk_regmap g12a_vpu_1_div = {
1975 .hw.init = &(struct clk_init_data){ 2756 .hw.init = &(struct clk_init_data){
1976 .name = "vpu_1_div", 2757 .name = "vpu_1_div",
1977 .ops = &clk_regmap_divider_ops, 2758 .ops = &clk_regmap_divider_ops,
1978 .parent_names = (const char *[]){ "vpu_1_sel" }, 2759 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },
1979 .num_parents = 1, 2760 .num_parents = 1,
1980 .flags = CLK_SET_RATE_PARENT, 2761 .flags = CLK_SET_RATE_PARENT,
1981 }, 2762 },
@@ -1989,7 +2770,7 @@ static struct clk_regmap g12a_vpu_1 = {
1989 .hw.init = &(struct clk_init_data) { 2770 .hw.init = &(struct clk_init_data) {
1990 .name = "vpu_1", 2771 .name = "vpu_1",
1991 .ops = &clk_regmap_gate_ops, 2772 .ops = &clk_regmap_gate_ops,
1992 .parent_names = (const char *[]){ "vpu_1_div" }, 2773 .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },
1993 .num_parents = 1, 2774 .num_parents = 1,
1994 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2775 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1995 }, 2776 },
@@ -2008,7 +2789,10 @@ static struct clk_regmap g12a_vpu = {
2008 * bit 31 selects from 2 possible parents: 2789 * bit 31 selects from 2 possible parents:
2009 * vpu_0 or vpu_1 2790 * vpu_0 or vpu_1
2010 */ 2791 */
2011 .parent_names = (const char *[]){ "vpu_0", "vpu_1" }, 2792 .parent_hws = (const struct clk_hw *[]) {
2793 &g12a_vpu_0.hw,
2794 &g12a_vpu_1.hw,
2795 },
2012 .num_parents = 2, 2796 .num_parents = 2,
2013 .flags = CLK_SET_RATE_NO_REPARENT, 2797 .flags = CLK_SET_RATE_NO_REPARENT,
2014 }, 2798 },
@@ -2016,9 +2800,14 @@ static struct clk_regmap g12a_vpu = {
2016 2800
2017/* VDEC clocks */ 2801/* VDEC clocks */
2018 2802
2019static const char * const g12a_vdec_parent_names[] = { 2803static const struct clk_hw *g12a_vdec_parent_hws[] = {
2020 "fclk_div2p5", "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7", 2804 &g12a_fclk_div2p5.hw,
2021 "hifi_pll", "gp0_pll", 2805 &g12a_fclk_div3.hw,
2806 &g12a_fclk_div4.hw,
2807 &g12a_fclk_div5.hw,
2808 &g12a_fclk_div7.hw,
2809 &g12a_hifi_pll.hw,
2810 &g12a_gp0_pll.hw,
2022}; 2811};
2023 2812
2024static struct clk_regmap g12a_vdec_1_sel = { 2813static struct clk_regmap g12a_vdec_1_sel = {
@@ -2031,8 +2820,8 @@ static struct clk_regmap g12a_vdec_1_sel = {
2031 .hw.init = &(struct clk_init_data){ 2820 .hw.init = &(struct clk_init_data){
2032 .name = "vdec_1_sel", 2821 .name = "vdec_1_sel",
2033 .ops = &clk_regmap_mux_ops, 2822 .ops = &clk_regmap_mux_ops,
2034 .parent_names = g12a_vdec_parent_names, 2823 .parent_hws = g12a_vdec_parent_hws,
2035 .num_parents = ARRAY_SIZE(g12a_vdec_parent_names), 2824 .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2036 .flags = CLK_SET_RATE_PARENT, 2825 .flags = CLK_SET_RATE_PARENT,
2037 }, 2826 },
2038}; 2827};
@@ -2047,7 +2836,9 @@ static struct clk_regmap g12a_vdec_1_div = {
2047 .hw.init = &(struct clk_init_data){ 2836 .hw.init = &(struct clk_init_data){
2048 .name = "vdec_1_div", 2837 .name = "vdec_1_div",
2049 .ops = &clk_regmap_divider_ops, 2838 .ops = &clk_regmap_divider_ops,
2050 .parent_names = (const char *[]){ "vdec_1_sel" }, 2839 .parent_hws = (const struct clk_hw *[]) {
2840 &g12a_vdec_1_sel.hw
2841 },
2051 .num_parents = 1, 2842 .num_parents = 1,
2052 .flags = CLK_SET_RATE_PARENT, 2843 .flags = CLK_SET_RATE_PARENT,
2053 }, 2844 },
@@ -2061,7 +2852,9 @@ static struct clk_regmap g12a_vdec_1 = {
2061 .hw.init = &(struct clk_init_data) { 2852 .hw.init = &(struct clk_init_data) {
2062 .name = "vdec_1", 2853 .name = "vdec_1",
2063 .ops = &clk_regmap_gate_ops, 2854 .ops = &clk_regmap_gate_ops,
2064 .parent_names = (const char *[]){ "vdec_1_div" }, 2855 .parent_hws = (const struct clk_hw *[]) {
2856 &g12a_vdec_1_div.hw
2857 },
2065 .num_parents = 1, 2858 .num_parents = 1,
2066 .flags = CLK_SET_RATE_PARENT, 2859 .flags = CLK_SET_RATE_PARENT,
2067 }, 2860 },
@@ -2077,8 +2870,8 @@ static struct clk_regmap g12a_vdec_hevcf_sel = {
2077 .hw.init = &(struct clk_init_data){ 2870 .hw.init = &(struct clk_init_data){
2078 .name = "vdec_hevcf_sel", 2871 .name = "vdec_hevcf_sel",
2079 .ops = &clk_regmap_mux_ops, 2872 .ops = &clk_regmap_mux_ops,
2080 .parent_names = g12a_vdec_parent_names, 2873 .parent_hws = g12a_vdec_parent_hws,
2081 .num_parents = ARRAY_SIZE(g12a_vdec_parent_names), 2874 .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2082 .flags = CLK_SET_RATE_PARENT, 2875 .flags = CLK_SET_RATE_PARENT,
2083 }, 2876 },
2084}; 2877};
@@ -2093,7 +2886,9 @@ static struct clk_regmap g12a_vdec_hevcf_div = {
2093 .hw.init = &(struct clk_init_data){ 2886 .hw.init = &(struct clk_init_data){
2094 .name = "vdec_hevcf_div", 2887 .name = "vdec_hevcf_div",
2095 .ops = &clk_regmap_divider_ops, 2888 .ops = &clk_regmap_divider_ops,
2096 .parent_names = (const char *[]){ "vdec_hevcf_sel" }, 2889 .parent_hws = (const struct clk_hw *[]) {
2890 &g12a_vdec_hevcf_sel.hw
2891 },
2097 .num_parents = 1, 2892 .num_parents = 1,
2098 .flags = CLK_SET_RATE_PARENT, 2893 .flags = CLK_SET_RATE_PARENT,
2099 }, 2894 },
@@ -2107,7 +2902,9 @@ static struct clk_regmap g12a_vdec_hevcf = {
2107 .hw.init = &(struct clk_init_data) { 2902 .hw.init = &(struct clk_init_data) {
2108 .name = "vdec_hevcf", 2903 .name = "vdec_hevcf",
2109 .ops = &clk_regmap_gate_ops, 2904 .ops = &clk_regmap_gate_ops,
2110 .parent_names = (const char *[]){ "vdec_hevcf_div" }, 2905 .parent_hws = (const struct clk_hw *[]) {
2906 &g12a_vdec_hevcf_div.hw
2907 },
2111 .num_parents = 1, 2908 .num_parents = 1,
2112 .flags = CLK_SET_RATE_PARENT, 2909 .flags = CLK_SET_RATE_PARENT,
2113 }, 2910 },
@@ -2123,8 +2920,8 @@ static struct clk_regmap g12a_vdec_hevc_sel = {
2123 .hw.init = &(struct clk_init_data){ 2920 .hw.init = &(struct clk_init_data){
2124 .name = "vdec_hevc_sel", 2921 .name = "vdec_hevc_sel",
2125 .ops = &clk_regmap_mux_ops, 2922 .ops = &clk_regmap_mux_ops,
2126 .parent_names = g12a_vdec_parent_names, 2923 .parent_hws = g12a_vdec_parent_hws,
2127 .num_parents = ARRAY_SIZE(g12a_vdec_parent_names), 2924 .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
2128 .flags = CLK_SET_RATE_PARENT, 2925 .flags = CLK_SET_RATE_PARENT,
2129 }, 2926 },
2130}; 2927};
@@ -2139,7 +2936,9 @@ static struct clk_regmap g12a_vdec_hevc_div = {
2139 .hw.init = &(struct clk_init_data){ 2936 .hw.init = &(struct clk_init_data){
2140 .name = "vdec_hevc_div", 2937 .name = "vdec_hevc_div",
2141 .ops = &clk_regmap_divider_ops, 2938 .ops = &clk_regmap_divider_ops,
2142 .parent_names = (const char *[]){ "vdec_hevc_sel" }, 2939 .parent_hws = (const struct clk_hw *[]) {
2940 &g12a_vdec_hevc_sel.hw
2941 },
2143 .num_parents = 1, 2942 .num_parents = 1,
2144 .flags = CLK_SET_RATE_PARENT, 2943 .flags = CLK_SET_RATE_PARENT,
2145 }, 2944 },
@@ -2153,7 +2952,9 @@ static struct clk_regmap g12a_vdec_hevc = {
2153 .hw.init = &(struct clk_init_data) { 2952 .hw.init = &(struct clk_init_data) {
2154 .name = "vdec_hevc", 2953 .name = "vdec_hevc",
2155 .ops = &clk_regmap_gate_ops, 2954 .ops = &clk_regmap_gate_ops,
2156 .parent_names = (const char *[]){ "vdec_hevc_div" }, 2955 .parent_hws = (const struct clk_hw *[]) {
2956 &g12a_vdec_hevc_div.hw
2957 },
2157 .num_parents = 1, 2958 .num_parents = 1,
2158 .flags = CLK_SET_RATE_PARENT, 2959 .flags = CLK_SET_RATE_PARENT,
2159 }, 2960 },
@@ -2161,9 +2962,15 @@ static struct clk_regmap g12a_vdec_hevc = {
2161 2962
2162/* VAPB Clock */ 2963/* VAPB Clock */
2163 2964
2164static const char * const g12a_vapb_parent_names[] = { 2965static const struct clk_hw *g12a_vapb_parent_hws[] = {
2165 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", 2966 &g12a_fclk_div4.hw,
2166 "mpll1", "vid_pll", "mpll2", "fclk_div2p5", 2967 &g12a_fclk_div3.hw,
2968 &g12a_fclk_div5.hw,
2969 &g12a_fclk_div7.hw,
2970 &g12a_mpll1.hw,
2971 &g12a_vid_pll.hw,
2972 &g12a_mpll2.hw,
2973 &g12a_fclk_div2p5.hw,
2167}; 2974};
2168 2975
2169static struct clk_regmap g12a_vapb_0_sel = { 2976static struct clk_regmap g12a_vapb_0_sel = {
@@ -2175,8 +2982,8 @@ static struct clk_regmap g12a_vapb_0_sel = {
2175 .hw.init = &(struct clk_init_data){ 2982 .hw.init = &(struct clk_init_data){
2176 .name = "vapb_0_sel", 2983 .name = "vapb_0_sel",
2177 .ops = &clk_regmap_mux_ops, 2984 .ops = &clk_regmap_mux_ops,
2178 .parent_names = g12a_vapb_parent_names, 2985 .parent_hws = g12a_vapb_parent_hws,
2179 .num_parents = ARRAY_SIZE(g12a_vapb_parent_names), 2986 .num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
2180 .flags = CLK_SET_RATE_NO_REPARENT, 2987 .flags = CLK_SET_RATE_NO_REPARENT,
2181 }, 2988 },
2182}; 2989};
@@ -2190,7 +2997,9 @@ static struct clk_regmap g12a_vapb_0_div = {
2190 .hw.init = &(struct clk_init_data){ 2997 .hw.init = &(struct clk_init_data){
2191 .name = "vapb_0_div", 2998 .name = "vapb_0_div",
2192 .ops = &clk_regmap_divider_ops, 2999 .ops = &clk_regmap_divider_ops,
2193 .parent_names = (const char *[]){ "vapb_0_sel" }, 3000 .parent_hws = (const struct clk_hw *[]) {
3001 &g12a_vapb_0_sel.hw
3002 },
2194 .num_parents = 1, 3003 .num_parents = 1,
2195 .flags = CLK_SET_RATE_PARENT, 3004 .flags = CLK_SET_RATE_PARENT,
2196 }, 3005 },
@@ -2204,7 +3013,9 @@ static struct clk_regmap g12a_vapb_0 = {
2204 .hw.init = &(struct clk_init_data) { 3013 .hw.init = &(struct clk_init_data) {
2205 .name = "vapb_0", 3014 .name = "vapb_0",
2206 .ops = &clk_regmap_gate_ops, 3015 .ops = &clk_regmap_gate_ops,
2207 .parent_names = (const char *[]){ "vapb_0_div" }, 3016 .parent_hws = (const struct clk_hw *[]) {
3017 &g12a_vapb_0_div.hw
3018 },
2208 .num_parents = 1, 3019 .num_parents = 1,
2209 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3020 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2210 }, 3021 },
@@ -2219,8 +3030,8 @@ static struct clk_regmap g12a_vapb_1_sel = {
2219 .hw.init = &(struct clk_init_data){ 3030 .hw.init = &(struct clk_init_data){
2220 .name = "vapb_1_sel", 3031 .name = "vapb_1_sel",
2221 .ops = &clk_regmap_mux_ops, 3032 .ops = &clk_regmap_mux_ops,
2222 .parent_names = g12a_vapb_parent_names, 3033 .parent_hws = g12a_vapb_parent_hws,
2223 .num_parents = ARRAY_SIZE(g12a_vapb_parent_names), 3034 .num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
2224 .flags = CLK_SET_RATE_NO_REPARENT, 3035 .flags = CLK_SET_RATE_NO_REPARENT,
2225 }, 3036 },
2226}; 3037};
@@ -2234,7 +3045,9 @@ static struct clk_regmap g12a_vapb_1_div = {
2234 .hw.init = &(struct clk_init_data){ 3045 .hw.init = &(struct clk_init_data){
2235 .name = "vapb_1_div", 3046 .name = "vapb_1_div",
2236 .ops = &clk_regmap_divider_ops, 3047 .ops = &clk_regmap_divider_ops,
2237 .parent_names = (const char *[]){ "vapb_1_sel" }, 3048 .parent_hws = (const struct clk_hw *[]) {
3049 &g12a_vapb_1_sel.hw
3050 },
2238 .num_parents = 1, 3051 .num_parents = 1,
2239 .flags = CLK_SET_RATE_PARENT, 3052 .flags = CLK_SET_RATE_PARENT,
2240 }, 3053 },
@@ -2248,7 +3061,9 @@ static struct clk_regmap g12a_vapb_1 = {
2248 .hw.init = &(struct clk_init_data) { 3061 .hw.init = &(struct clk_init_data) {
2249 .name = "vapb_1", 3062 .name = "vapb_1",
2250 .ops = &clk_regmap_gate_ops, 3063 .ops = &clk_regmap_gate_ops,
2251 .parent_names = (const char *[]){ "vapb_1_div" }, 3064 .parent_hws = (const struct clk_hw *[]) {
3065 &g12a_vapb_1_div.hw
3066 },
2252 .num_parents = 1, 3067 .num_parents = 1,
2253 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3068 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2254 }, 3069 },
@@ -2267,7 +3082,10 @@ static struct clk_regmap g12a_vapb_sel = {
2267 * bit 31 selects from 2 possible parents: 3082 * bit 31 selects from 2 possible parents:
2268 * vapb_0 or vapb_1 3083 * vapb_0 or vapb_1
2269 */ 3084 */
2270 .parent_names = (const char *[]){ "vapb_0", "vapb_1" }, 3085 .parent_hws = (const struct clk_hw *[]) {
3086 &g12a_vapb_0.hw,
3087 &g12a_vapb_1.hw,
3088 },
2271 .num_parents = 2, 3089 .num_parents = 2,
2272 .flags = CLK_SET_RATE_NO_REPARENT, 3090 .flags = CLK_SET_RATE_NO_REPARENT,
2273 }, 3091 },
@@ -2281,75 +3099,21 @@ static struct clk_regmap g12a_vapb = {
2281 .hw.init = &(struct clk_init_data) { 3099 .hw.init = &(struct clk_init_data) {
2282 .name = "vapb", 3100 .name = "vapb",
2283 .ops = &clk_regmap_gate_ops, 3101 .ops = &clk_regmap_gate_ops,
2284 .parent_names = (const char *[]){ "vapb_sel" }, 3102 .parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },
2285 .num_parents = 1,
2286 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2287 },
2288};
2289
2290/* Video Clocks */
2291
2292static struct clk_regmap g12a_vid_pll_div = {
2293 .data = &(struct meson_vid_pll_div_data){
2294 .val = {
2295 .reg_off = HHI_VID_PLL_CLK_DIV,
2296 .shift = 0,
2297 .width = 15,
2298 },
2299 .sel = {
2300 .reg_off = HHI_VID_PLL_CLK_DIV,
2301 .shift = 16,
2302 .width = 2,
2303 },
2304 },
2305 .hw.init = &(struct clk_init_data) {
2306 .name = "vid_pll_div",
2307 .ops = &meson_vid_pll_div_ro_ops,
2308 .parent_names = (const char *[]){ "hdmi_pll" },
2309 .num_parents = 1,
2310 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2311 },
2312};
2313
2314static const char * const g12a_vid_pll_parent_names[] = { "vid_pll_div",
2315 "hdmi_pll" };
2316
2317static struct clk_regmap g12a_vid_pll_sel = {
2318 .data = &(struct clk_regmap_mux_data){
2319 .offset = HHI_VID_PLL_CLK_DIV,
2320 .mask = 0x1,
2321 .shift = 18,
2322 },
2323 .hw.init = &(struct clk_init_data){
2324 .name = "vid_pll_sel",
2325 .ops = &clk_regmap_mux_ops,
2326 /*
2327 * bit 18 selects from 2 possible parents:
2328 * vid_pll_div or hdmi_pll
2329 */
2330 .parent_names = g12a_vid_pll_parent_names,
2331 .num_parents = ARRAY_SIZE(g12a_vid_pll_parent_names),
2332 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2333 },
2334};
2335
2336static struct clk_regmap g12a_vid_pll = {
2337 .data = &(struct clk_regmap_gate_data){
2338 .offset = HHI_VID_PLL_CLK_DIV,
2339 .bit_idx = 19,
2340 },
2341 .hw.init = &(struct clk_init_data) {
2342 .name = "vid_pll",
2343 .ops = &clk_regmap_gate_ops,
2344 .parent_names = (const char *[]){ "vid_pll_sel" },
2345 .num_parents = 1, 3103 .num_parents = 1,
2346 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3104 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2347 }, 3105 },
2348}; 3106};
2349 3107
2350static const char * const g12a_vclk_parent_names[] = { 3108static const struct clk_hw *g12a_vclk_parent_hws[] = {
2351 "vid_pll", "gp0_pll", "hifi_pll", "mpll1", "fclk_div3", "fclk_div4", 3109 &g12a_vid_pll.hw,
2352 "fclk_div5", "fclk_div7" 3110 &g12a_gp0_pll.hw,
3111 &g12a_hifi_pll.hw,
3112 &g12a_mpll1.hw,
3113 &g12a_fclk_div3.hw,
3114 &g12a_fclk_div4.hw,
3115 &g12a_fclk_div5.hw,
3116 &g12a_fclk_div7.hw,
2353}; 3117};
2354 3118
2355static struct clk_regmap g12a_vclk_sel = { 3119static struct clk_regmap g12a_vclk_sel = {
@@ -2361,8 +3125,8 @@ static struct clk_regmap g12a_vclk_sel = {
2361 .hw.init = &(struct clk_init_data){ 3125 .hw.init = &(struct clk_init_data){
2362 .name = "vclk_sel", 3126 .name = "vclk_sel",
2363 .ops = &clk_regmap_mux_ops, 3127 .ops = &clk_regmap_mux_ops,
2364 .parent_names = g12a_vclk_parent_names, 3128 .parent_hws = g12a_vclk_parent_hws,
2365 .num_parents = ARRAY_SIZE(g12a_vclk_parent_names), 3129 .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
2366 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 3130 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2367 }, 3131 },
2368}; 3132};
@@ -2376,8 +3140,8 @@ static struct clk_regmap g12a_vclk2_sel = {
2376 .hw.init = &(struct clk_init_data){ 3140 .hw.init = &(struct clk_init_data){
2377 .name = "vclk2_sel", 3141 .name = "vclk2_sel",
2378 .ops = &clk_regmap_mux_ops, 3142 .ops = &clk_regmap_mux_ops,
2379 .parent_names = g12a_vclk_parent_names, 3143 .parent_hws = g12a_vclk_parent_hws,
2380 .num_parents = ARRAY_SIZE(g12a_vclk_parent_names), 3144 .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
2381 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 3145 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2382 }, 3146 },
2383}; 3147};
@@ -2390,7 +3154,7 @@ static struct clk_regmap g12a_vclk_input = {
2390 .hw.init = &(struct clk_init_data) { 3154 .hw.init = &(struct clk_init_data) {
2391 .name = "vclk_input", 3155 .name = "vclk_input",
2392 .ops = &clk_regmap_gate_ops, 3156 .ops = &clk_regmap_gate_ops,
2393 .parent_names = (const char *[]){ "vclk_sel" }, 3157 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },
2394 .num_parents = 1, 3158 .num_parents = 1,
2395 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3159 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2396 }, 3160 },
@@ -2404,7 +3168,7 @@ static struct clk_regmap g12a_vclk2_input = {
2404 .hw.init = &(struct clk_init_data) { 3168 .hw.init = &(struct clk_init_data) {
2405 .name = "vclk2_input", 3169 .name = "vclk2_input",
2406 .ops = &clk_regmap_gate_ops, 3170 .ops = &clk_regmap_gate_ops,
2407 .parent_names = (const char *[]){ "vclk2_sel" }, 3171 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
2408 .num_parents = 1, 3172 .num_parents = 1,
2409 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3173 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2410 }, 3174 },
@@ -2419,7 +3183,9 @@ static struct clk_regmap g12a_vclk_div = {
2419 .hw.init = &(struct clk_init_data){ 3183 .hw.init = &(struct clk_init_data){
2420 .name = "vclk_div", 3184 .name = "vclk_div",
2421 .ops = &clk_regmap_divider_ops, 3185 .ops = &clk_regmap_divider_ops,
2422 .parent_names = (const char *[]){ "vclk_input" }, 3186 .parent_hws = (const struct clk_hw *[]) {
3187 &g12a_vclk_input.hw
3188 },
2423 .num_parents = 1, 3189 .num_parents = 1,
2424 .flags = CLK_GET_RATE_NOCACHE, 3190 .flags = CLK_GET_RATE_NOCACHE,
2425 }, 3191 },
@@ -2434,7 +3200,9 @@ static struct clk_regmap g12a_vclk2_div = {
2434 .hw.init = &(struct clk_init_data){ 3200 .hw.init = &(struct clk_init_data){
2435 .name = "vclk2_div", 3201 .name = "vclk2_div",
2436 .ops = &clk_regmap_divider_ops, 3202 .ops = &clk_regmap_divider_ops,
2437 .parent_names = (const char *[]){ "vclk2_input" }, 3203 .parent_hws = (const struct clk_hw *[]) {
3204 &g12a_vclk2_input.hw
3205 },
2438 .num_parents = 1, 3206 .num_parents = 1,
2439 .flags = CLK_GET_RATE_NOCACHE, 3207 .flags = CLK_GET_RATE_NOCACHE,
2440 }, 3208 },
@@ -2448,7 +3216,7 @@ static struct clk_regmap g12a_vclk = {
2448 .hw.init = &(struct clk_init_data) { 3216 .hw.init = &(struct clk_init_data) {
2449 .name = "vclk", 3217 .name = "vclk",
2450 .ops = &clk_regmap_gate_ops, 3218 .ops = &clk_regmap_gate_ops,
2451 .parent_names = (const char *[]){ "vclk_div" }, 3219 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },
2452 .num_parents = 1, 3220 .num_parents = 1,
2453 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3221 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2454 }, 3222 },
@@ -2462,7 +3230,7 @@ static struct clk_regmap g12a_vclk2 = {
2462 .hw.init = &(struct clk_init_data) { 3230 .hw.init = &(struct clk_init_data) {
2463 .name = "vclk2", 3231 .name = "vclk2",
2464 .ops = &clk_regmap_gate_ops, 3232 .ops = &clk_regmap_gate_ops,
2465 .parent_names = (const char *[]){ "vclk2_div" }, 3233 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
2466 .num_parents = 1, 3234 .num_parents = 1,
2467 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3235 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2468 }, 3236 },
@@ -2476,7 +3244,7 @@ static struct clk_regmap g12a_vclk_div1 = {
2476 .hw.init = &(struct clk_init_data) { 3244 .hw.init = &(struct clk_init_data) {
2477 .name = "vclk_div1", 3245 .name = "vclk_div1",
2478 .ops = &clk_regmap_gate_ops, 3246 .ops = &clk_regmap_gate_ops,
2479 .parent_names = (const char *[]){ "vclk" }, 3247 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
2480 .num_parents = 1, 3248 .num_parents = 1,
2481 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3249 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2482 }, 3250 },
@@ -2490,7 +3258,7 @@ static struct clk_regmap g12a_vclk_div2_en = {
2490 .hw.init = &(struct clk_init_data) { 3258 .hw.init = &(struct clk_init_data) {
2491 .name = "vclk_div2_en", 3259 .name = "vclk_div2_en",
2492 .ops = &clk_regmap_gate_ops, 3260 .ops = &clk_regmap_gate_ops,
2493 .parent_names = (const char *[]){ "vclk" }, 3261 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
2494 .num_parents = 1, 3262 .num_parents = 1,
2495 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3263 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2496 }, 3264 },
@@ -2504,7 +3272,7 @@ static struct clk_regmap g12a_vclk_div4_en = {
2504 .hw.init = &(struct clk_init_data) { 3272 .hw.init = &(struct clk_init_data) {
2505 .name = "vclk_div4_en", 3273 .name = "vclk_div4_en",
2506 .ops = &clk_regmap_gate_ops, 3274 .ops = &clk_regmap_gate_ops,
2507 .parent_names = (const char *[]){ "vclk" }, 3275 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
2508 .num_parents = 1, 3276 .num_parents = 1,
2509 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3277 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2510 }, 3278 },
@@ -2518,7 +3286,7 @@ static struct clk_regmap g12a_vclk_div6_en = {
2518 .hw.init = &(struct clk_init_data) { 3286 .hw.init = &(struct clk_init_data) {
2519 .name = "vclk_div6_en", 3287 .name = "vclk_div6_en",
2520 .ops = &clk_regmap_gate_ops, 3288 .ops = &clk_regmap_gate_ops,
2521 .parent_names = (const char *[]){ "vclk" }, 3289 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
2522 .num_parents = 1, 3290 .num_parents = 1,
2523 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3291 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2524 }, 3292 },
@@ -2532,7 +3300,7 @@ static struct clk_regmap g12a_vclk_div12_en = {
2532 .hw.init = &(struct clk_init_data) { 3300 .hw.init = &(struct clk_init_data) {
2533 .name = "vclk_div12_en", 3301 .name = "vclk_div12_en",
2534 .ops = &clk_regmap_gate_ops, 3302 .ops = &clk_regmap_gate_ops,
2535 .parent_names = (const char *[]){ "vclk" }, 3303 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
2536 .num_parents = 1, 3304 .num_parents = 1,
2537 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3305 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2538 }, 3306 },
@@ -2546,7 +3314,7 @@ static struct clk_regmap g12a_vclk2_div1 = {
2546 .hw.init = &(struct clk_init_data) { 3314 .hw.init = &(struct clk_init_data) {
2547 .name = "vclk2_div1", 3315 .name = "vclk2_div1",
2548 .ops = &clk_regmap_gate_ops, 3316 .ops = &clk_regmap_gate_ops,
2549 .parent_names = (const char *[]){ "vclk2" }, 3317 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
2550 .num_parents = 1, 3318 .num_parents = 1,
2551 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3319 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2552 }, 3320 },
@@ -2560,7 +3328,7 @@ static struct clk_regmap g12a_vclk2_div2_en = {
2560 .hw.init = &(struct clk_init_data) { 3328 .hw.init = &(struct clk_init_data) {
2561 .name = "vclk2_div2_en", 3329 .name = "vclk2_div2_en",
2562 .ops = &clk_regmap_gate_ops, 3330 .ops = &clk_regmap_gate_ops,
2563 .parent_names = (const char *[]){ "vclk2" }, 3331 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
2564 .num_parents = 1, 3332 .num_parents = 1,
2565 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3333 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2566 }, 3334 },
@@ -2574,7 +3342,7 @@ static struct clk_regmap g12a_vclk2_div4_en = {
2574 .hw.init = &(struct clk_init_data) { 3342 .hw.init = &(struct clk_init_data) {
2575 .name = "vclk2_div4_en", 3343 .name = "vclk2_div4_en",
2576 .ops = &clk_regmap_gate_ops, 3344 .ops = &clk_regmap_gate_ops,
2577 .parent_names = (const char *[]){ "vclk2" }, 3345 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
2578 .num_parents = 1, 3346 .num_parents = 1,
2579 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3347 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2580 }, 3348 },
@@ -2588,7 +3356,7 @@ static struct clk_regmap g12a_vclk2_div6_en = {
2588 .hw.init = &(struct clk_init_data) { 3356 .hw.init = &(struct clk_init_data) {
2589 .name = "vclk2_div6_en", 3357 .name = "vclk2_div6_en",
2590 .ops = &clk_regmap_gate_ops, 3358 .ops = &clk_regmap_gate_ops,
2591 .parent_names = (const char *[]){ "vclk2" }, 3359 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
2592 .num_parents = 1, 3360 .num_parents = 1,
2593 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3361 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2594 }, 3362 },
@@ -2602,7 +3370,7 @@ static struct clk_regmap g12a_vclk2_div12_en = {
2602 .hw.init = &(struct clk_init_data) { 3370 .hw.init = &(struct clk_init_data) {
2603 .name = "vclk2_div12_en", 3371 .name = "vclk2_div12_en",
2604 .ops = &clk_regmap_gate_ops, 3372 .ops = &clk_regmap_gate_ops,
2605 .parent_names = (const char *[]){ "vclk2" }, 3373 .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
2606 .num_parents = 1, 3374 .num_parents = 1,
2607 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3375 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2608 }, 3376 },
@@ -2614,7 +3382,9 @@ static struct clk_fixed_factor g12a_vclk_div2 = {
2614 .hw.init = &(struct clk_init_data){ 3382 .hw.init = &(struct clk_init_data){
2615 .name = "vclk_div2", 3383 .name = "vclk_div2",
2616 .ops = &clk_fixed_factor_ops, 3384 .ops = &clk_fixed_factor_ops,
2617 .parent_names = (const char *[]){ "vclk_div2_en" }, 3385 .parent_hws = (const struct clk_hw *[]) {
3386 &g12a_vclk_div2_en.hw
3387 },
2618 .num_parents = 1, 3388 .num_parents = 1,
2619 }, 3389 },
2620}; 3390};
@@ -2625,7 +3395,9 @@ static struct clk_fixed_factor g12a_vclk_div4 = {
2625 .hw.init = &(struct clk_init_data){ 3395 .hw.init = &(struct clk_init_data){
2626 .name = "vclk_div4", 3396 .name = "vclk_div4",
2627 .ops = &clk_fixed_factor_ops, 3397 .ops = &clk_fixed_factor_ops,
2628 .parent_names = (const char *[]){ "vclk_div4_en" }, 3398 .parent_hws = (const struct clk_hw *[]) {
3399 &g12a_vclk_div4_en.hw
3400 },
2629 .num_parents = 1, 3401 .num_parents = 1,
2630 }, 3402 },
2631}; 3403};
@@ -2636,7 +3408,9 @@ static struct clk_fixed_factor g12a_vclk_div6 = {
2636 .hw.init = &(struct clk_init_data){ 3408 .hw.init = &(struct clk_init_data){
2637 .name = "vclk_div6", 3409 .name = "vclk_div6",
2638 .ops = &clk_fixed_factor_ops, 3410 .ops = &clk_fixed_factor_ops,
2639 .parent_names = (const char *[]){ "vclk_div6_en" }, 3411 .parent_hws = (const struct clk_hw *[]) {
3412 &g12a_vclk_div6_en.hw
3413 },
2640 .num_parents = 1, 3414 .num_parents = 1,
2641 }, 3415 },
2642}; 3416};
@@ -2647,7 +3421,9 @@ static struct clk_fixed_factor g12a_vclk_div12 = {
2647 .hw.init = &(struct clk_init_data){ 3421 .hw.init = &(struct clk_init_data){
2648 .name = "vclk_div12", 3422 .name = "vclk_div12",
2649 .ops = &clk_fixed_factor_ops, 3423 .ops = &clk_fixed_factor_ops,
2650 .parent_names = (const char *[]){ "vclk_div12_en" }, 3424 .parent_hws = (const struct clk_hw *[]) {
3425 &g12a_vclk_div12_en.hw
3426 },
2651 .num_parents = 1, 3427 .num_parents = 1,
2652 }, 3428 },
2653}; 3429};
@@ -2658,7 +3434,9 @@ static struct clk_fixed_factor g12a_vclk2_div2 = {
2658 .hw.init = &(struct clk_init_data){ 3434 .hw.init = &(struct clk_init_data){
2659 .name = "vclk2_div2", 3435 .name = "vclk2_div2",
2660 .ops = &clk_fixed_factor_ops, 3436 .ops = &clk_fixed_factor_ops,
2661 .parent_names = (const char *[]){ "vclk2_div2_en" }, 3437 .parent_hws = (const struct clk_hw *[]) {
3438 &g12a_vclk2_div2_en.hw
3439 },
2662 .num_parents = 1, 3440 .num_parents = 1,
2663 }, 3441 },
2664}; 3442};
@@ -2669,7 +3447,9 @@ static struct clk_fixed_factor g12a_vclk2_div4 = {
2669 .hw.init = &(struct clk_init_data){ 3447 .hw.init = &(struct clk_init_data){
2670 .name = "vclk2_div4", 3448 .name = "vclk2_div4",
2671 .ops = &clk_fixed_factor_ops, 3449 .ops = &clk_fixed_factor_ops,
2672 .parent_names = (const char *[]){ "vclk2_div4_en" }, 3450 .parent_hws = (const struct clk_hw *[]) {
3451 &g12a_vclk2_div4_en.hw
3452 },
2673 .num_parents = 1, 3453 .num_parents = 1,
2674 }, 3454 },
2675}; 3455};
@@ -2680,7 +3460,9 @@ static struct clk_fixed_factor g12a_vclk2_div6 = {
2680 .hw.init = &(struct clk_init_data){ 3460 .hw.init = &(struct clk_init_data){
2681 .name = "vclk2_div6", 3461 .name = "vclk2_div6",
2682 .ops = &clk_fixed_factor_ops, 3462 .ops = &clk_fixed_factor_ops,
2683 .parent_names = (const char *[]){ "vclk2_div6_en" }, 3463 .parent_hws = (const struct clk_hw *[]) {
3464 &g12a_vclk2_div6_en.hw
3465 },
2684 .num_parents = 1, 3466 .num_parents = 1,
2685 }, 3467 },
2686}; 3468};
@@ -2691,16 +3473,25 @@ static struct clk_fixed_factor g12a_vclk2_div12 = {
2691 .hw.init = &(struct clk_init_data){ 3473 .hw.init = &(struct clk_init_data){
2692 .name = "vclk2_div12", 3474 .name = "vclk2_div12",
2693 .ops = &clk_fixed_factor_ops, 3475 .ops = &clk_fixed_factor_ops,
2694 .parent_names = (const char *[]){ "vclk2_div12_en" }, 3476 .parent_hws = (const struct clk_hw *[]) {
3477 &g12a_vclk2_div12_en.hw
3478 },
2695 .num_parents = 1, 3479 .num_parents = 1,
2696 }, 3480 },
2697}; 3481};
2698 3482
2699static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 3483static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2700static const char * const g12a_cts_parent_names[] = { 3484static const struct clk_hw *g12a_cts_parent_hws[] = {
2701 "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6", 3485 &g12a_vclk_div1.hw,
2702 "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4", 3486 &g12a_vclk_div2.hw,
2703 "vclk2_div6", "vclk2_div12" 3487 &g12a_vclk_div4.hw,
3488 &g12a_vclk_div6.hw,
3489 &g12a_vclk_div12.hw,
3490 &g12a_vclk2_div1.hw,
3491 &g12a_vclk2_div2.hw,
3492 &g12a_vclk2_div4.hw,
3493 &g12a_vclk2_div6.hw,
3494 &g12a_vclk2_div12.hw,
2704}; 3495};
2705 3496
2706static struct clk_regmap g12a_cts_enci_sel = { 3497static struct clk_regmap g12a_cts_enci_sel = {
@@ -2713,8 +3504,8 @@ static struct clk_regmap g12a_cts_enci_sel = {
2713 .hw.init = &(struct clk_init_data){ 3504 .hw.init = &(struct clk_init_data){
2714 .name = "cts_enci_sel", 3505 .name = "cts_enci_sel",
2715 .ops = &clk_regmap_mux_ops, 3506 .ops = &clk_regmap_mux_ops,
2716 .parent_names = g12a_cts_parent_names, 3507 .parent_hws = g12a_cts_parent_hws,
2717 .num_parents = ARRAY_SIZE(g12a_cts_parent_names), 3508 .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
2718 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 3509 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2719 }, 3510 },
2720}; 3511};
@@ -2729,8 +3520,8 @@ static struct clk_regmap g12a_cts_encp_sel = {
2729 .hw.init = &(struct clk_init_data){ 3520 .hw.init = &(struct clk_init_data){
2730 .name = "cts_encp_sel", 3521 .name = "cts_encp_sel",
2731 .ops = &clk_regmap_mux_ops, 3522 .ops = &clk_regmap_mux_ops,
2732 .parent_names = g12a_cts_parent_names, 3523 .parent_hws = g12a_cts_parent_hws,
2733 .num_parents = ARRAY_SIZE(g12a_cts_parent_names), 3524 .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
2734 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 3525 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2735 }, 3526 },
2736}; 3527};
@@ -2745,18 +3536,25 @@ static struct clk_regmap g12a_cts_vdac_sel = {
2745 .hw.init = &(struct clk_init_data){ 3536 .hw.init = &(struct clk_init_data){
2746 .name = "cts_vdac_sel", 3537 .name = "cts_vdac_sel",
2747 .ops = &clk_regmap_mux_ops, 3538 .ops = &clk_regmap_mux_ops,
2748 .parent_names = g12a_cts_parent_names, 3539 .parent_hws = g12a_cts_parent_hws,
2749 .num_parents = ARRAY_SIZE(g12a_cts_parent_names), 3540 .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
2750 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 3541 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2751 }, 3542 },
2752}; 3543};
2753 3544
2754/* TOFIX: add support for cts_tcon */ 3545/* TOFIX: add support for cts_tcon */
2755static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 3546static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2756static const char * const g12a_cts_hdmi_tx_parent_names[] = { 3547static const struct clk_hw *g12a_cts_hdmi_tx_parent_hws[] = {
2757 "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6", 3548 &g12a_vclk_div1.hw,
2758 "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4", 3549 &g12a_vclk_div2.hw,
2759 "vclk2_div6", "vclk2_div12" 3550 &g12a_vclk_div4.hw,
3551 &g12a_vclk_div6.hw,
3552 &g12a_vclk_div12.hw,
3553 &g12a_vclk2_div1.hw,
3554 &g12a_vclk2_div2.hw,
3555 &g12a_vclk2_div4.hw,
3556 &g12a_vclk2_div6.hw,
3557 &g12a_vclk2_div12.hw,
2760}; 3558};
2761 3559
2762static struct clk_regmap g12a_hdmi_tx_sel = { 3560static struct clk_regmap g12a_hdmi_tx_sel = {
@@ -2769,8 +3567,8 @@ static struct clk_regmap g12a_hdmi_tx_sel = {
2769 .hw.init = &(struct clk_init_data){ 3567 .hw.init = &(struct clk_init_data){
2770 .name = "hdmi_tx_sel", 3568 .name = "hdmi_tx_sel",
2771 .ops = &clk_regmap_mux_ops, 3569 .ops = &clk_regmap_mux_ops,
2772 .parent_names = g12a_cts_hdmi_tx_parent_names, 3570 .parent_hws = g12a_cts_hdmi_tx_parent_hws,
2773 .num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_names), 3571 .num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_hws),
2774 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 3572 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2775 }, 3573 },
2776}; 3574};
@@ -2783,7 +3581,9 @@ static struct clk_regmap g12a_cts_enci = {
2783 .hw.init = &(struct clk_init_data) { 3581 .hw.init = &(struct clk_init_data) {
2784 .name = "cts_enci", 3582 .name = "cts_enci",
2785 .ops = &clk_regmap_gate_ops, 3583 .ops = &clk_regmap_gate_ops,
2786 .parent_names = (const char *[]){ "cts_enci_sel" }, 3584 .parent_hws = (const struct clk_hw *[]) {
3585 &g12a_cts_enci_sel.hw
3586 },
2787 .num_parents = 1, 3587 .num_parents = 1,
2788 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3588 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2789 }, 3589 },
@@ -2797,7 +3597,9 @@ static struct clk_regmap g12a_cts_encp = {
2797 .hw.init = &(struct clk_init_data) { 3597 .hw.init = &(struct clk_init_data) {
2798 .name = "cts_encp", 3598 .name = "cts_encp",
2799 .ops = &clk_regmap_gate_ops, 3599 .ops = &clk_regmap_gate_ops,
2800 .parent_names = (const char *[]){ "cts_encp_sel" }, 3600 .parent_hws = (const struct clk_hw *[]) {
3601 &g12a_cts_encp_sel.hw
3602 },
2801 .num_parents = 1, 3603 .num_parents = 1,
2802 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3604 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2803 }, 3605 },
@@ -2811,7 +3613,9 @@ static struct clk_regmap g12a_cts_vdac = {
2811 .hw.init = &(struct clk_init_data) { 3613 .hw.init = &(struct clk_init_data) {
2812 .name = "cts_vdac", 3614 .name = "cts_vdac",
2813 .ops = &clk_regmap_gate_ops, 3615 .ops = &clk_regmap_gate_ops,
2814 .parent_names = (const char *[]){ "cts_vdac_sel" }, 3616 .parent_hws = (const struct clk_hw *[]) {
3617 &g12a_cts_vdac_sel.hw
3618 },
2815 .num_parents = 1, 3619 .num_parents = 1,
2816 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3620 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2817 }, 3621 },
@@ -2825,7 +3629,9 @@ static struct clk_regmap g12a_hdmi_tx = {
2825 .hw.init = &(struct clk_init_data) { 3629 .hw.init = &(struct clk_init_data) {
2826 .name = "hdmi_tx", 3630 .name = "hdmi_tx",
2827 .ops = &clk_regmap_gate_ops, 3631 .ops = &clk_regmap_gate_ops,
2828 .parent_names = (const char *[]){ "hdmi_tx_sel" }, 3632 .parent_hws = (const struct clk_hw *[]) {
3633 &g12a_hdmi_tx_sel.hw
3634 },
2829 .num_parents = 1, 3635 .num_parents = 1,
2830 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3636 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2831 }, 3637 },
@@ -2833,8 +3639,11 @@ static struct clk_regmap g12a_hdmi_tx = {
2833 3639
2834/* HDMI Clocks */ 3640/* HDMI Clocks */
2835 3641
2836static const char * const g12a_hdmi_parent_names[] = { 3642static const struct clk_parent_data g12a_hdmi_parent_data[] = {
2837 IN_PREFIX "xtal", "fclk_div4", "fclk_div3", "fclk_div5" 3643 { .fw_name = "xtal", },
3644 { .hw = &g12a_fclk_div4.hw },
3645 { .hw = &g12a_fclk_div3.hw },
3646 { .hw = &g12a_fclk_div5.hw },
2838}; 3647};
2839 3648
2840static struct clk_regmap g12a_hdmi_sel = { 3649static struct clk_regmap g12a_hdmi_sel = {
@@ -2847,8 +3656,8 @@ static struct clk_regmap g12a_hdmi_sel = {
2847 .hw.init = &(struct clk_init_data){ 3656 .hw.init = &(struct clk_init_data){
2848 .name = "hdmi_sel", 3657 .name = "hdmi_sel",
2849 .ops = &clk_regmap_mux_ops, 3658 .ops = &clk_regmap_mux_ops,
2850 .parent_names = g12a_hdmi_parent_names, 3659 .parent_data = g12a_hdmi_parent_data,
2851 .num_parents = ARRAY_SIZE(g12a_hdmi_parent_names), 3660 .num_parents = ARRAY_SIZE(g12a_hdmi_parent_data),
2852 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 3661 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2853 }, 3662 },
2854}; 3663};
@@ -2862,7 +3671,7 @@ static struct clk_regmap g12a_hdmi_div = {
2862 .hw.init = &(struct clk_init_data){ 3671 .hw.init = &(struct clk_init_data){
2863 .name = "hdmi_div", 3672 .name = "hdmi_div",
2864 .ops = &clk_regmap_divider_ops, 3673 .ops = &clk_regmap_divider_ops,
2865 .parent_names = (const char *[]){ "hdmi_sel" }, 3674 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },
2866 .num_parents = 1, 3675 .num_parents = 1,
2867 .flags = CLK_GET_RATE_NOCACHE, 3676 .flags = CLK_GET_RATE_NOCACHE,
2868 }, 3677 },
@@ -2876,7 +3685,7 @@ static struct clk_regmap g12a_hdmi = {
2876 .hw.init = &(struct clk_init_data) { 3685 .hw.init = &(struct clk_init_data) {
2877 .name = "hdmi", 3686 .name = "hdmi",
2878 .ops = &clk_regmap_gate_ops, 3687 .ops = &clk_regmap_gate_ops,
2879 .parent_names = (const char *[]){ "hdmi_div" }, 3688 .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },
2880 .num_parents = 1, 3689 .num_parents = 1,
2881 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 3690 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2882 }, 3691 },
@@ -2886,10 +3695,15 @@ static struct clk_regmap g12a_hdmi = {
2886 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1) 3695 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
2887 * muxed by a glitch-free switch. 3696 * muxed by a glitch-free switch.
2888 */ 3697 */
2889 3698static const struct clk_parent_data g12a_mali_0_1_parent_data[] = {
2890static const char * const g12a_mali_0_1_parent_names[] = { 3699 { .fw_name = "xtal", },
2891 IN_PREFIX "xtal", "gp0_pll", "hihi_pll", "fclk_div2p5", 3700 { .hw = &g12a_gp0_pll.hw },
2892 "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7" 3701 { .hw = &g12a_hifi_pll.hw },
3702 { .hw = &g12a_fclk_div2p5.hw },
3703 { .hw = &g12a_fclk_div3.hw },
3704 { .hw = &g12a_fclk_div4.hw },
3705 { .hw = &g12a_fclk_div5.hw },
3706 { .hw = &g12a_fclk_div7.hw },
2893}; 3707};
2894 3708
2895static struct clk_regmap g12a_mali_0_sel = { 3709static struct clk_regmap g12a_mali_0_sel = {
@@ -2901,7 +3715,7 @@ static struct clk_regmap g12a_mali_0_sel = {
2901 .hw.init = &(struct clk_init_data){ 3715 .hw.init = &(struct clk_init_data){
2902 .name = "mali_0_sel", 3716 .name = "mali_0_sel",
2903 .ops = &clk_regmap_mux_ops, 3717 .ops = &clk_regmap_mux_ops,
2904 .parent_names = g12a_mali_0_1_parent_names, 3718 .parent_data = g12a_mali_0_1_parent_data,
2905 .num_parents = 8, 3719 .num_parents = 8,
2906 .flags = CLK_SET_RATE_NO_REPARENT, 3720 .flags = CLK_SET_RATE_NO_REPARENT,
2907 }, 3721 },
@@ -2916,7 +3730,9 @@ static struct clk_regmap g12a_mali_0_div = {
2916 .hw.init = &(struct clk_init_data){ 3730 .hw.init = &(struct clk_init_data){
2917 .name = "mali_0_div", 3731 .name = "mali_0_div",
2918 .ops = &clk_regmap_divider_ops, 3732 .ops = &clk_regmap_divider_ops,
2919 .parent_names = (const char *[]){ "mali_0_sel" }, 3733 .parent_hws = (const struct clk_hw *[]) {
3734 &g12a_mali_0_sel.hw
3735 },
2920 .num_parents = 1, 3736 .num_parents = 1,
2921 .flags = CLK_SET_RATE_NO_REPARENT, 3737 .flags = CLK_SET_RATE_NO_REPARENT,
2922 }, 3738 },
@@ -2930,7 +3746,9 @@ static struct clk_regmap g12a_mali_0 = {
2930 .hw.init = &(struct clk_init_data){ 3746 .hw.init = &(struct clk_init_data){
2931 .name = "mali_0", 3747 .name = "mali_0",
2932 .ops = &clk_regmap_gate_ops, 3748 .ops = &clk_regmap_gate_ops,
2933 .parent_names = (const char *[]){ "mali_0_div" }, 3749 .parent_hws = (const struct clk_hw *[]) {
3750 &g12a_mali_0_div.hw
3751 },
2934 .num_parents = 1, 3752 .num_parents = 1,
2935 .flags = CLK_SET_RATE_PARENT, 3753 .flags = CLK_SET_RATE_PARENT,
2936 }, 3754 },
@@ -2945,7 +3763,7 @@ static struct clk_regmap g12a_mali_1_sel = {
2945 .hw.init = &(struct clk_init_data){ 3763 .hw.init = &(struct clk_init_data){
2946 .name = "mali_1_sel", 3764 .name = "mali_1_sel",
2947 .ops = &clk_regmap_mux_ops, 3765 .ops = &clk_regmap_mux_ops,
2948 .parent_names = g12a_mali_0_1_parent_names, 3766 .parent_data = g12a_mali_0_1_parent_data,
2949 .num_parents = 8, 3767 .num_parents = 8,
2950 .flags = CLK_SET_RATE_NO_REPARENT, 3768 .flags = CLK_SET_RATE_NO_REPARENT,
2951 }, 3769 },
@@ -2960,7 +3778,9 @@ static struct clk_regmap g12a_mali_1_div = {
2960 .hw.init = &(struct clk_init_data){ 3778 .hw.init = &(struct clk_init_data){
2961 .name = "mali_1_div", 3779 .name = "mali_1_div",
2962 .ops = &clk_regmap_divider_ops, 3780 .ops = &clk_regmap_divider_ops,
2963 .parent_names = (const char *[]){ "mali_1_sel" }, 3781 .parent_hws = (const struct clk_hw *[]) {
3782 &g12a_mali_1_sel.hw
3783 },
2964 .num_parents = 1, 3784 .num_parents = 1,
2965 .flags = CLK_SET_RATE_NO_REPARENT, 3785 .flags = CLK_SET_RATE_NO_REPARENT,
2966 }, 3786 },
@@ -2974,14 +3794,17 @@ static struct clk_regmap g12a_mali_1 = {
2974 .hw.init = &(struct clk_init_data){ 3794 .hw.init = &(struct clk_init_data){
2975 .name = "mali_1", 3795 .name = "mali_1",
2976 .ops = &clk_regmap_gate_ops, 3796 .ops = &clk_regmap_gate_ops,
2977 .parent_names = (const char *[]){ "mali_1_div" }, 3797 .parent_hws = (const struct clk_hw *[]) {
3798 &g12a_mali_1_div.hw
3799 },
2978 .num_parents = 1, 3800 .num_parents = 1,
2979 .flags = CLK_SET_RATE_PARENT, 3801 .flags = CLK_SET_RATE_PARENT,
2980 }, 3802 },
2981}; 3803};
2982 3804
2983static const char * const g12a_mali_parent_names[] = { 3805static const struct clk_hw *g12a_mali_parent_hws[] = {
2984 "mali_0", "mali_1" 3806 &g12a_mali_0.hw,
3807 &g12a_mali_1.hw,
2985}; 3808};
2986 3809
2987static struct clk_regmap g12a_mali = { 3810static struct clk_regmap g12a_mali = {
@@ -2993,7 +3816,7 @@ static struct clk_regmap g12a_mali = {
2993 .hw.init = &(struct clk_init_data){ 3816 .hw.init = &(struct clk_init_data){
2994 .name = "mali", 3817 .name = "mali",
2995 .ops = &clk_regmap_mux_ops, 3818 .ops = &clk_regmap_mux_ops,
2996 .parent_names = g12a_mali_parent_names, 3819 .parent_hws = g12a_mali_parent_hws,
2997 .num_parents = 2, 3820 .num_parents = 2,
2998 .flags = CLK_SET_RATE_NO_REPARENT, 3821 .flags = CLK_SET_RATE_NO_REPARENT,
2999 }, 3822 },
@@ -3008,7 +3831,9 @@ static struct clk_regmap g12a_ts_div = {
3008 .hw.init = &(struct clk_init_data){ 3831 .hw.init = &(struct clk_init_data){
3009 .name = "ts_div", 3832 .name = "ts_div",
3010 .ops = &clk_regmap_divider_ro_ops, 3833 .ops = &clk_regmap_divider_ro_ops,
3011 .parent_names = (const char *[]){ "xtal" }, 3834 .parent_data = &(const struct clk_parent_data) {
3835 .fw_name = "xtal",
3836 },
3012 .num_parents = 1, 3837 .num_parents = 1,
3013 }, 3838 },
3014}; 3839};
@@ -3021,11 +3846,19 @@ static struct clk_regmap g12a_ts = {
3021 .hw.init = &(struct clk_init_data){ 3846 .hw.init = &(struct clk_init_data){
3022 .name = "ts", 3847 .name = "ts",
3023 .ops = &clk_regmap_gate_ops, 3848 .ops = &clk_regmap_gate_ops,
3024 .parent_names = (const char *[]){ "ts_div" }, 3849 .parent_hws = (const struct clk_hw *[]) {
3850 &g12a_ts_div.hw
3851 },
3025 .num_parents = 1, 3852 .num_parents = 1,
3026 }, 3853 },
3027}; 3854};
3028 3855
3856#define MESON_GATE(_name, _reg, _bit) \
3857 MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
3858
3859#define MESON_GATE_RO(_name, _reg, _bit) \
3860 MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)
3861
3029/* Everything Else (EE) domain gates */ 3862/* Everything Else (EE) domain gates */
3030static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0); 3863static MESON_GATE(g12a_ddr, HHI_GCLK_MPEG0, 0);
3031static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1); 3864static MESON_GATE(g12a_dos, HHI_GCLK_MPEG0, 1);
@@ -3571,6 +4404,240 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
3571 .num = NR_CLKS, 4404 .num = NR_CLKS,
3572}; 4405};
3573 4406
4407static struct clk_hw_onecell_data sm1_hw_onecell_data = {
4408 .hws = {
4409 [CLKID_SYS_PLL] = &g12a_sys_pll.hw,
4410 [CLKID_FIXED_PLL] = &g12a_fixed_pll.hw,
4411 [CLKID_FCLK_DIV2] = &g12a_fclk_div2.hw,
4412 [CLKID_FCLK_DIV3] = &g12a_fclk_div3.hw,
4413 [CLKID_FCLK_DIV4] = &g12a_fclk_div4.hw,
4414 [CLKID_FCLK_DIV5] = &g12a_fclk_div5.hw,
4415 [CLKID_FCLK_DIV7] = &g12a_fclk_div7.hw,
4416 [CLKID_FCLK_DIV2P5] = &g12a_fclk_div2p5.hw,
4417 [CLKID_GP0_PLL] = &g12a_gp0_pll.hw,
4418 [CLKID_MPEG_SEL] = &g12a_mpeg_clk_sel.hw,
4419 [CLKID_MPEG_DIV] = &g12a_mpeg_clk_div.hw,
4420 [CLKID_CLK81] = &g12a_clk81.hw,
4421 [CLKID_MPLL0] = &g12a_mpll0.hw,
4422 [CLKID_MPLL1] = &g12a_mpll1.hw,
4423 [CLKID_MPLL2] = &g12a_mpll2.hw,
4424 [CLKID_MPLL3] = &g12a_mpll3.hw,
4425 [CLKID_DDR] = &g12a_ddr.hw,
4426 [CLKID_DOS] = &g12a_dos.hw,
4427 [CLKID_AUDIO_LOCKER] = &g12a_audio_locker.hw,
4428 [CLKID_MIPI_DSI_HOST] = &g12a_mipi_dsi_host.hw,
4429 [CLKID_ETH_PHY] = &g12a_eth_phy.hw,
4430 [CLKID_ISA] = &g12a_isa.hw,
4431 [CLKID_PL301] = &g12a_pl301.hw,
4432 [CLKID_PERIPHS] = &g12a_periphs.hw,
4433 [CLKID_SPICC0] = &g12a_spicc_0.hw,
4434 [CLKID_I2C] = &g12a_i2c.hw,
4435 [CLKID_SANA] = &g12a_sana.hw,
4436 [CLKID_SD] = &g12a_sd.hw,
4437 [CLKID_RNG0] = &g12a_rng0.hw,
4438 [CLKID_UART0] = &g12a_uart0.hw,
4439 [CLKID_SPICC1] = &g12a_spicc_1.hw,
4440 [CLKID_HIU_IFACE] = &g12a_hiu_reg.hw,
4441 [CLKID_MIPI_DSI_PHY] = &g12a_mipi_dsi_phy.hw,
4442 [CLKID_ASSIST_MISC] = &g12a_assist_misc.hw,
4443 [CLKID_SD_EMMC_A] = &g12a_emmc_a.hw,
4444 [CLKID_SD_EMMC_B] = &g12a_emmc_b.hw,
4445 [CLKID_SD_EMMC_C] = &g12a_emmc_c.hw,
4446 [CLKID_AUDIO_CODEC] = &g12a_audio_codec.hw,
4447 [CLKID_AUDIO] = &g12a_audio.hw,
4448 [CLKID_ETH] = &g12a_eth_core.hw,
4449 [CLKID_DEMUX] = &g12a_demux.hw,
4450 [CLKID_AUDIO_IFIFO] = &g12a_audio_ififo.hw,
4451 [CLKID_ADC] = &g12a_adc.hw,
4452 [CLKID_UART1] = &g12a_uart1.hw,
4453 [CLKID_G2D] = &g12a_g2d.hw,
4454 [CLKID_RESET] = &g12a_reset.hw,
4455 [CLKID_PCIE_COMB] = &g12a_pcie_comb.hw,
4456 [CLKID_PARSER] = &g12a_parser.hw,
4457 [CLKID_USB] = &g12a_usb_general.hw,
4458 [CLKID_PCIE_PHY] = &g12a_pcie_phy.hw,
4459 [CLKID_AHB_ARB0] = &g12a_ahb_arb0.hw,
4460 [CLKID_AHB_DATA_BUS] = &g12a_ahb_data_bus.hw,
4461 [CLKID_AHB_CTRL_BUS] = &g12a_ahb_ctrl_bus.hw,
4462 [CLKID_HTX_HDCP22] = &g12a_htx_hdcp22.hw,
4463 [CLKID_HTX_PCLK] = &g12a_htx_pclk.hw,
4464 [CLKID_BT656] = &g12a_bt656.hw,
4465 [CLKID_USB1_DDR_BRIDGE] = &g12a_usb1_to_ddr.hw,
4466 [CLKID_MMC_PCLK] = &g12a_mmc_pclk.hw,
4467 [CLKID_UART2] = &g12a_uart2.hw,
4468 [CLKID_VPU_INTR] = &g12a_vpu_intr.hw,
4469 [CLKID_GIC] = &g12a_gic.hw,
4470 [CLKID_SD_EMMC_A_CLK0_SEL] = &g12a_sd_emmc_a_clk0_sel.hw,
4471 [CLKID_SD_EMMC_A_CLK0_DIV] = &g12a_sd_emmc_a_clk0_div.hw,
4472 [CLKID_SD_EMMC_A_CLK0] = &g12a_sd_emmc_a_clk0.hw,
4473 [CLKID_SD_EMMC_B_CLK0_SEL] = &g12a_sd_emmc_b_clk0_sel.hw,
4474 [CLKID_SD_EMMC_B_CLK0_DIV] = &g12a_sd_emmc_b_clk0_div.hw,
4475 [CLKID_SD_EMMC_B_CLK0] = &g12a_sd_emmc_b_clk0.hw,
4476 [CLKID_SD_EMMC_C_CLK0_SEL] = &g12a_sd_emmc_c_clk0_sel.hw,
4477 [CLKID_SD_EMMC_C_CLK0_DIV] = &g12a_sd_emmc_c_clk0_div.hw,
4478 [CLKID_SD_EMMC_C_CLK0] = &g12a_sd_emmc_c_clk0.hw,
4479 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4480 [CLKID_MPLL1_DIV] = &g12a_mpll1_div.hw,
4481 [CLKID_MPLL2_DIV] = &g12a_mpll2_div.hw,
4482 [CLKID_MPLL3_DIV] = &g12a_mpll3_div.hw,
4483 [CLKID_FCLK_DIV2_DIV] = &g12a_fclk_div2_div.hw,
4484 [CLKID_FCLK_DIV3_DIV] = &g12a_fclk_div3_div.hw,
4485 [CLKID_FCLK_DIV4_DIV] = &g12a_fclk_div4_div.hw,
4486 [CLKID_FCLK_DIV5_DIV] = &g12a_fclk_div5_div.hw,
4487 [CLKID_FCLK_DIV7_DIV] = &g12a_fclk_div7_div.hw,
4488 [CLKID_FCLK_DIV2P5_DIV] = &g12a_fclk_div2p5_div.hw,
4489 [CLKID_HIFI_PLL] = &g12a_hifi_pll.hw,
4490 [CLKID_VCLK2_VENCI0] = &g12a_vclk2_venci0.hw,
4491 [CLKID_VCLK2_VENCI1] = &g12a_vclk2_venci1.hw,
4492 [CLKID_VCLK2_VENCP0] = &g12a_vclk2_vencp0.hw,
4493 [CLKID_VCLK2_VENCP1] = &g12a_vclk2_vencp1.hw,
4494 [CLKID_VCLK2_VENCT0] = &g12a_vclk2_venct0.hw,
4495 [CLKID_VCLK2_VENCT1] = &g12a_vclk2_venct1.hw,
4496 [CLKID_VCLK2_OTHER] = &g12a_vclk2_other.hw,
4497 [CLKID_VCLK2_ENCI] = &g12a_vclk2_enci.hw,
4498 [CLKID_VCLK2_ENCP] = &g12a_vclk2_encp.hw,
4499 [CLKID_DAC_CLK] = &g12a_dac_clk.hw,
4500 [CLKID_AOCLK] = &g12a_aoclk_gate.hw,
4501 [CLKID_IEC958] = &g12a_iec958_gate.hw,
4502 [CLKID_ENC480P] = &g12a_enc480p.hw,
4503 [CLKID_RNG1] = &g12a_rng1.hw,
4504 [CLKID_VCLK2_ENCT] = &g12a_vclk2_enct.hw,
4505 [CLKID_VCLK2_ENCL] = &g12a_vclk2_encl.hw,
4506 [CLKID_VCLK2_VENCLMMC] = &g12a_vclk2_venclmmc.hw,
4507 [CLKID_VCLK2_VENCL] = &g12a_vclk2_vencl.hw,
4508 [CLKID_VCLK2_OTHER1] = &g12a_vclk2_other1.hw,
4509 [CLKID_FIXED_PLL_DCO] = &g12a_fixed_pll_dco.hw,
4510 [CLKID_SYS_PLL_DCO] = &g12a_sys_pll_dco.hw,
4511 [CLKID_GP0_PLL_DCO] = &g12a_gp0_pll_dco.hw,
4512 [CLKID_HIFI_PLL_DCO] = &g12a_hifi_pll_dco.hw,
4513 [CLKID_DMA] = &g12a_dma.hw,
4514 [CLKID_EFUSE] = &g12a_efuse.hw,
4515 [CLKID_ROM_BOOT] = &g12a_rom_boot.hw,
4516 [CLKID_RESET_SEC] = &g12a_reset_sec.hw,
4517 [CLKID_SEC_AHB_APB3] = &g12a_sec_ahb_apb3.hw,
4518 [CLKID_MPLL_PREDIV] = &g12a_mpll_prediv.hw,
4519 [CLKID_VPU_0_SEL] = &g12a_vpu_0_sel.hw,
4520 [CLKID_VPU_0_DIV] = &g12a_vpu_0_div.hw,
4521 [CLKID_VPU_0] = &g12a_vpu_0.hw,
4522 [CLKID_VPU_1_SEL] = &g12a_vpu_1_sel.hw,
4523 [CLKID_VPU_1_DIV] = &g12a_vpu_1_div.hw,
4524 [CLKID_VPU_1] = &g12a_vpu_1.hw,
4525 [CLKID_VPU] = &g12a_vpu.hw,
4526 [CLKID_VAPB_0_SEL] = &g12a_vapb_0_sel.hw,
4527 [CLKID_VAPB_0_DIV] = &g12a_vapb_0_div.hw,
4528 [CLKID_VAPB_0] = &g12a_vapb_0.hw,
4529 [CLKID_VAPB_1_SEL] = &g12a_vapb_1_sel.hw,
4530 [CLKID_VAPB_1_DIV] = &g12a_vapb_1_div.hw,
4531 [CLKID_VAPB_1] = &g12a_vapb_1.hw,
4532 [CLKID_VAPB_SEL] = &g12a_vapb_sel.hw,
4533 [CLKID_VAPB] = &g12a_vapb.hw,
4534 [CLKID_HDMI_PLL_DCO] = &g12a_hdmi_pll_dco.hw,
4535 [CLKID_HDMI_PLL_OD] = &g12a_hdmi_pll_od.hw,
4536 [CLKID_HDMI_PLL_OD2] = &g12a_hdmi_pll_od2.hw,
4537 [CLKID_HDMI_PLL] = &g12a_hdmi_pll.hw,
4538 [CLKID_VID_PLL] = &g12a_vid_pll_div.hw,
4539 [CLKID_VID_PLL_SEL] = &g12a_vid_pll_sel.hw,
4540 [CLKID_VID_PLL_DIV] = &g12a_vid_pll.hw,
4541 [CLKID_VCLK_SEL] = &g12a_vclk_sel.hw,
4542 [CLKID_VCLK2_SEL] = &g12a_vclk2_sel.hw,
4543 [CLKID_VCLK_INPUT] = &g12a_vclk_input.hw,
4544 [CLKID_VCLK2_INPUT] = &g12a_vclk2_input.hw,
4545 [CLKID_VCLK_DIV] = &g12a_vclk_div.hw,
4546 [CLKID_VCLK2_DIV] = &g12a_vclk2_div.hw,
4547 [CLKID_VCLK] = &g12a_vclk.hw,
4548 [CLKID_VCLK2] = &g12a_vclk2.hw,
4549 [CLKID_VCLK_DIV1] = &g12a_vclk_div1.hw,
4550 [CLKID_VCLK_DIV2_EN] = &g12a_vclk_div2_en.hw,
4551 [CLKID_VCLK_DIV4_EN] = &g12a_vclk_div4_en.hw,
4552 [CLKID_VCLK_DIV6_EN] = &g12a_vclk_div6_en.hw,
4553 [CLKID_VCLK_DIV12_EN] = &g12a_vclk_div12_en.hw,
4554 [CLKID_VCLK2_DIV1] = &g12a_vclk2_div1.hw,
4555 [CLKID_VCLK2_DIV2_EN] = &g12a_vclk2_div2_en.hw,
4556 [CLKID_VCLK2_DIV4_EN] = &g12a_vclk2_div4_en.hw,
4557 [CLKID_VCLK2_DIV6_EN] = &g12a_vclk2_div6_en.hw,
4558 [CLKID_VCLK2_DIV12_EN] = &g12a_vclk2_div12_en.hw,
4559 [CLKID_VCLK_DIV2] = &g12a_vclk_div2.hw,
4560 [CLKID_VCLK_DIV4] = &g12a_vclk_div4.hw,
4561 [CLKID_VCLK_DIV6] = &g12a_vclk_div6.hw,
4562 [CLKID_VCLK_DIV12] = &g12a_vclk_div12.hw,
4563 [CLKID_VCLK2_DIV2] = &g12a_vclk2_div2.hw,
4564 [CLKID_VCLK2_DIV4] = &g12a_vclk2_div4.hw,
4565 [CLKID_VCLK2_DIV6] = &g12a_vclk2_div6.hw,
4566 [CLKID_VCLK2_DIV12] = &g12a_vclk2_div12.hw,
4567 [CLKID_CTS_ENCI_SEL] = &g12a_cts_enci_sel.hw,
4568 [CLKID_CTS_ENCP_SEL] = &g12a_cts_encp_sel.hw,
4569 [CLKID_CTS_VDAC_SEL] = &g12a_cts_vdac_sel.hw,
4570 [CLKID_HDMI_TX_SEL] = &g12a_hdmi_tx_sel.hw,
4571 [CLKID_CTS_ENCI] = &g12a_cts_enci.hw,
4572 [CLKID_CTS_ENCP] = &g12a_cts_encp.hw,
4573 [CLKID_CTS_VDAC] = &g12a_cts_vdac.hw,
4574 [CLKID_HDMI_TX] = &g12a_hdmi_tx.hw,
4575 [CLKID_HDMI_SEL] = &g12a_hdmi_sel.hw,
4576 [CLKID_HDMI_DIV] = &g12a_hdmi_div.hw,
4577 [CLKID_HDMI] = &g12a_hdmi.hw,
4578 [CLKID_MALI_0_SEL] = &g12a_mali_0_sel.hw,
4579 [CLKID_MALI_0_DIV] = &g12a_mali_0_div.hw,
4580 [CLKID_MALI_0] = &g12a_mali_0.hw,
4581 [CLKID_MALI_1_SEL] = &g12a_mali_1_sel.hw,
4582 [CLKID_MALI_1_DIV] = &g12a_mali_1_div.hw,
4583 [CLKID_MALI_1] = &g12a_mali_1.hw,
4584 [CLKID_MALI] = &g12a_mali.hw,
4585 [CLKID_MPLL_50M_DIV] = &g12a_mpll_50m_div.hw,
4586 [CLKID_MPLL_50M] = &g12a_mpll_50m.hw,
4587 [CLKID_SYS_PLL_DIV16_EN] = &g12a_sys_pll_div16_en.hw,
4588 [CLKID_SYS_PLL_DIV16] = &g12a_sys_pll_div16.hw,
4589 [CLKID_CPU_CLK_DYN0_SEL] = &g12a_cpu_clk_premux0.hw,
4590 [CLKID_CPU_CLK_DYN0_DIV] = &g12a_cpu_clk_mux0_div.hw,
4591 [CLKID_CPU_CLK_DYN0] = &g12a_cpu_clk_postmux0.hw,
4592 [CLKID_CPU_CLK_DYN1_SEL] = &g12a_cpu_clk_premux1.hw,
4593 [CLKID_CPU_CLK_DYN1_DIV] = &g12a_cpu_clk_mux1_div.hw,
4594 [CLKID_CPU_CLK_DYN1] = &g12a_cpu_clk_postmux1.hw,
4595 [CLKID_CPU_CLK_DYN] = &g12a_cpu_clk_dyn.hw,
4596 [CLKID_CPU_CLK] = &g12a_cpu_clk.hw,
4597 [CLKID_CPU_CLK_DIV16_EN] = &g12a_cpu_clk_div16_en.hw,
4598 [CLKID_CPU_CLK_DIV16] = &g12a_cpu_clk_div16.hw,
4599 [CLKID_CPU_CLK_APB_DIV] = &g12a_cpu_clk_apb_div.hw,
4600 [CLKID_CPU_CLK_APB] = &g12a_cpu_clk_apb.hw,
4601 [CLKID_CPU_CLK_ATB_DIV] = &g12a_cpu_clk_atb_div.hw,
4602 [CLKID_CPU_CLK_ATB] = &g12a_cpu_clk_atb.hw,
4603 [CLKID_CPU_CLK_AXI_DIV] = &g12a_cpu_clk_axi_div.hw,
4604 [CLKID_CPU_CLK_AXI] = &g12a_cpu_clk_axi.hw,
4605 [CLKID_CPU_CLK_TRACE_DIV] = &g12a_cpu_clk_trace_div.hw,
4606 [CLKID_CPU_CLK_TRACE] = &g12a_cpu_clk_trace.hw,
4607 [CLKID_PCIE_PLL_DCO] = &g12a_pcie_pll_dco.hw,
4608 [CLKID_PCIE_PLL_DCO_DIV2] = &g12a_pcie_pll_dco_div2.hw,
4609 [CLKID_PCIE_PLL_OD] = &g12a_pcie_pll_od.hw,
4610 [CLKID_PCIE_PLL] = &g12a_pcie_pll.hw,
4611 [CLKID_VDEC_1_SEL] = &g12a_vdec_1_sel.hw,
4612 [CLKID_VDEC_1_DIV] = &g12a_vdec_1_div.hw,
4613 [CLKID_VDEC_1] = &g12a_vdec_1.hw,
4614 [CLKID_VDEC_HEVC_SEL] = &g12a_vdec_hevc_sel.hw,
4615 [CLKID_VDEC_HEVC_DIV] = &g12a_vdec_hevc_div.hw,
4616 [CLKID_VDEC_HEVC] = &g12a_vdec_hevc.hw,
4617 [CLKID_VDEC_HEVCF_SEL] = &g12a_vdec_hevcf_sel.hw,
4618 [CLKID_VDEC_HEVCF_DIV] = &g12a_vdec_hevcf_div.hw,
4619 [CLKID_VDEC_HEVCF] = &g12a_vdec_hevcf.hw,
4620 [CLKID_TS_DIV] = &g12a_ts_div.hw,
4621 [CLKID_TS] = &g12a_ts.hw,
4622 [CLKID_GP1_PLL_DCO] = &sm1_gp1_pll_dco.hw,
4623 [CLKID_GP1_PLL] = &sm1_gp1_pll.hw,
4624 [CLKID_DSU_CLK_DYN0_SEL] = &sm1_dsu_clk_premux0.hw,
4625 [CLKID_DSU_CLK_DYN0_DIV] = &sm1_dsu_clk_premux1.hw,
4626 [CLKID_DSU_CLK_DYN0] = &sm1_dsu_clk_mux0_div.hw,
4627 [CLKID_DSU_CLK_DYN1_SEL] = &sm1_dsu_clk_postmux0.hw,
4628 [CLKID_DSU_CLK_DYN1_DIV] = &sm1_dsu_clk_mux1_div.hw,
4629 [CLKID_DSU_CLK_DYN1] = &sm1_dsu_clk_postmux1.hw,
4630 [CLKID_DSU_CLK_DYN] = &sm1_dsu_clk_dyn.hw,
4631 [CLKID_DSU_CLK_FINAL] = &sm1_dsu_final_clk.hw,
4632 [CLKID_DSU_CLK] = &sm1_dsu_clk.hw,
4633 [CLKID_CPU1_CLK] = &sm1_cpu1_clk.hw,
4634 [CLKID_CPU2_CLK] = &sm1_cpu2_clk.hw,
4635 [CLKID_CPU3_CLK] = &sm1_cpu3_clk.hw,
4636 [NR_CLKS] = NULL,
4637 },
4638 .num = NR_CLKS,
4639};
4640
3574/* Convenience table to populate regmap in .probe */ 4641/* Convenience table to populate regmap in .probe */
3575static struct clk_regmap *const g12a_clk_regmaps[] = { 4642static struct clk_regmap *const g12a_clk_regmaps[] = {
3576 &g12a_clk81, 4643 &g12a_clk81,
@@ -3786,34 +4853,243 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
3786 &g12b_cpub_clk_axi, 4853 &g12b_cpub_clk_axi,
3787 &g12b_cpub_clk_trace_sel, 4854 &g12b_cpub_clk_trace_sel,
3788 &g12b_cpub_clk_trace, 4855 &g12b_cpub_clk_trace,
4856 &sm1_gp1_pll_dco,
4857 &sm1_gp1_pll,
4858 &sm1_dsu_clk_premux0,
4859 &sm1_dsu_clk_premux1,
4860 &sm1_dsu_clk_mux0_div,
4861 &sm1_dsu_clk_postmux0,
4862 &sm1_dsu_clk_mux1_div,
4863 &sm1_dsu_clk_postmux1,
4864 &sm1_dsu_clk_dyn,
4865 &sm1_dsu_final_clk,
4866 &sm1_dsu_clk,
4867 &sm1_cpu1_clk,
4868 &sm1_cpu2_clk,
4869 &sm1_cpu3_clk,
3789}; 4870};
3790 4871
3791static const struct reg_sequence g12a_init_regs[] = { 4872static const struct reg_sequence g12a_init_regs[] = {
3792 { .reg = HHI_MPLL_CNTL0, .def = 0x00000543 }, 4873 { .reg = HHI_MPLL_CNTL0, .def = 0x00000543 },
3793}; 4874};
3794 4875
3795static const struct meson_eeclkc_data g12a_clkc_data = { 4876static int meson_g12a_dvfs_setup_common(struct platform_device *pdev,
3796 .regmap_clks = g12a_clk_regmaps, 4877 struct clk_hw **hws)
3797 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), 4878{
3798 .hw_onecell_data = &g12a_hw_onecell_data, 4879 const char *notifier_clk_name;
3799 .init_regs = g12a_init_regs, 4880 struct clk *notifier_clk;
3800 .init_count = ARRAY_SIZE(g12a_init_regs), 4881 struct clk_hw *xtal;
3801}; 4882 int ret;
3802 4883
3803static const struct meson_eeclkc_data g12b_clkc_data = { 4884 xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
3804 .regmap_clks = g12a_clk_regmaps, 4885
3805 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps), 4886 /* Setup clock notifier for cpu_clk_postmux0 */
3806 .hw_onecell_data = &g12b_hw_onecell_data 4887 g12a_cpu_clk_postmux0_nb_data.xtal = xtal;
4888 notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_postmux0.hw);
4889 notifier_clk = __clk_lookup(notifier_clk_name);
4890 ret = clk_notifier_register(notifier_clk,
4891 &g12a_cpu_clk_postmux0_nb_data.nb);
4892 if (ret) {
4893 dev_err(&pdev->dev, "failed to register the cpu_clk_postmux0 notifier\n");
4894 return ret;
4895 }
4896
4897 /* Setup clock notifier for cpu_clk_dyn mux */
4898 notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_dyn.hw);
4899 notifier_clk = __clk_lookup(notifier_clk_name);
4900 ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
4901 if (ret) {
4902 dev_err(&pdev->dev, "failed to register the cpu_clk_dyn notifier\n");
4903 return ret;
4904 }
4905
4906 return 0;
4907}
4908
4909static int meson_g12b_dvfs_setup(struct platform_device *pdev)
4910{
4911 struct clk_hw **hws = g12b_hw_onecell_data.hws;
4912 const char *notifier_clk_name;
4913 struct clk *notifier_clk;
4914 struct clk_hw *xtal;
4915 int ret;
4916
4917 ret = meson_g12a_dvfs_setup_common(pdev, hws);
4918 if (ret)
4919 return ret;
4920
4921 xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
4922
4923 /* Setup clock notifier for cpu_clk mux */
4924 notifier_clk_name = clk_hw_get_name(&g12b_cpu_clk.hw);
4925 notifier_clk = __clk_lookup(notifier_clk_name);
4926 ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
4927 if (ret) {
4928 dev_err(&pdev->dev, "failed to register the cpu_clk notifier\n");
4929 return ret;
4930 }
4931
4932 /* Setup clock notifier for sys1_pll */
4933 notifier_clk_name = clk_hw_get_name(&g12b_sys1_pll.hw);
4934 notifier_clk = __clk_lookup(notifier_clk_name);
4935 ret = clk_notifier_register(notifier_clk,
4936 &g12b_cpu_clk_sys1_pll_nb_data.nb);
4937 if (ret) {
4938 dev_err(&pdev->dev, "failed to register the sys1_pll notifier\n");
4939 return ret;
4940 }
4941
4942 /* Add notifiers for the second CPU cluster */
4943
4944 /* Setup clock notifier for cpub_clk_postmux0 */
4945 g12b_cpub_clk_postmux0_nb_data.xtal = xtal;
4946 notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_postmux0.hw);
4947 notifier_clk = __clk_lookup(notifier_clk_name);
4948 ret = clk_notifier_register(notifier_clk,
4949 &g12b_cpub_clk_postmux0_nb_data.nb);
4950 if (ret) {
4951 dev_err(&pdev->dev, "failed to register the cpub_clk_postmux0 notifier\n");
4952 return ret;
4953 }
4954
4955 /* Setup clock notifier for cpub_clk_dyn mux */
4956 notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_dyn.hw);
4957 notifier_clk = __clk_lookup(notifier_clk_name);
4958 ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
4959 if (ret) {
4960 dev_err(&pdev->dev, "failed to register the cpub_clk_dyn notifier\n");
4961 return ret;
4962 }
4963
4964 /* Setup clock notifier for cpub_clk mux */
4965 notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk.hw);
4966 notifier_clk = __clk_lookup(notifier_clk_name);
4967 ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
4968 if (ret) {
4969 dev_err(&pdev->dev, "failed to register the cpub_clk notifier\n");
4970 return ret;
4971 }
4972
4973 /* Setup clock notifier for sys_pll */
4974 notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw);
4975 notifier_clk = __clk_lookup(notifier_clk_name);
4976 ret = clk_notifier_register(notifier_clk,
4977 &g12b_cpub_clk_sys_pll_nb_data.nb);
4978 if (ret) {
4979 dev_err(&pdev->dev, "failed to register the sys_pll notifier\n");
4980 return ret;
4981 }
4982
4983 return 0;
4984}
4985
4986static int meson_g12a_dvfs_setup(struct platform_device *pdev)
4987{
4988 struct clk_hw **hws = g12a_hw_onecell_data.hws;
4989 const char *notifier_clk_name;
4990 struct clk *notifier_clk;
4991 int ret;
4992
4993 ret = meson_g12a_dvfs_setup_common(pdev, hws);
4994 if (ret)
4995 return ret;
4996
4997 /* Setup clock notifier for cpu_clk mux */
4998 notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk.hw);
4999 notifier_clk = __clk_lookup(notifier_clk_name);
5000 ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
5001 if (ret) {
5002 dev_err(&pdev->dev, "failed to register the cpu_clk notifier\n");
5003 return ret;
5004 }
5005
5006 /* Setup clock notifier for sys_pll */
5007 notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw);
5008 notifier_clk = __clk_lookup(notifier_clk_name);
5009 ret = clk_notifier_register(notifier_clk, &g12a_sys_pll_nb_data.nb);
5010 if (ret) {
5011 dev_err(&pdev->dev, "failed to register the sys_pll notifier\n");
5012 return ret;
5013 }
5014
5015 return 0;
5016}
5017
5018struct meson_g12a_data {
5019 const struct meson_eeclkc_data eeclkc_data;
5020 int (*dvfs_setup)(struct platform_device *pdev);
5021};
5022
5023static int meson_g12a_probe(struct platform_device *pdev)
5024{
5025 const struct meson_eeclkc_data *eeclkc_data;
5026 const struct meson_g12a_data *g12a_data;
5027 int ret;
5028
5029 eeclkc_data = of_device_get_match_data(&pdev->dev);
5030 if (!eeclkc_data)
5031 return -EINVAL;
5032
5033 ret = meson_eeclkc_probe(pdev);
5034 if (ret)
5035 return ret;
5036
5037 g12a_data = container_of(eeclkc_data, struct meson_g12a_data,
5038 eeclkc_data);
5039
5040 if (g12a_data->dvfs_setup)
5041 return g12a_data->dvfs_setup(pdev);
5042
5043 return 0;
5044}
5045
5046static const struct meson_g12a_data g12a_clkc_data = {
5047 .eeclkc_data = {
5048 .regmap_clks = g12a_clk_regmaps,
5049 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5050 .hw_onecell_data = &g12a_hw_onecell_data,
5051 .init_regs = g12a_init_regs,
5052 .init_count = ARRAY_SIZE(g12a_init_regs),
5053 },
5054 .dvfs_setup = meson_g12a_dvfs_setup,
5055};
5056
5057static const struct meson_g12a_data g12b_clkc_data = {
5058 .eeclkc_data = {
5059 .regmap_clks = g12a_clk_regmaps,
5060 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5061 .hw_onecell_data = &g12b_hw_onecell_data,
5062 },
5063 .dvfs_setup = meson_g12b_dvfs_setup,
5064};
5065
5066static const struct meson_g12a_data sm1_clkc_data = {
5067 .eeclkc_data = {
5068 .regmap_clks = g12a_clk_regmaps,
5069 .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
5070 .hw_onecell_data = &sm1_hw_onecell_data,
5071 },
5072 .dvfs_setup = meson_g12a_dvfs_setup,
3807}; 5073};
3808 5074
3809static const struct of_device_id clkc_match_table[] = { 5075static const struct of_device_id clkc_match_table[] = {
3810 { .compatible = "amlogic,g12a-clkc", .data = &g12a_clkc_data }, 5076 {
3811 { .compatible = "amlogic,g12b-clkc", .data = &g12b_clkc_data }, 5077 .compatible = "amlogic,g12a-clkc",
5078 .data = &g12a_clkc_data.eeclkc_data
5079 },
5080 {
5081 .compatible = "amlogic,g12b-clkc",
5082 .data = &g12b_clkc_data.eeclkc_data
5083 },
5084 {
5085 .compatible = "amlogic,sm1-clkc",
5086 .data = &sm1_clkc_data.eeclkc_data
5087 },
3812 {} 5088 {}
3813}; 5089};
3814 5090
3815static struct platform_driver g12a_driver = { 5091static struct platform_driver g12a_driver = {
3816 .probe = meson_eeclkc_probe, 5092 .probe = meson_g12a_probe,
3817 .driver = { 5093 .driver = {
3818 .name = "g12a-clkc", 5094 .name = "g12a-clkc",
3819 .of_match_table = clkc_match_table, 5095 .of_match_table = clkc_match_table,
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index c8aed31fbe17..9df4068aced1 100644
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -29,6 +29,14 @@
29#define HHI_GP0_PLL_CNTL5 0x054 29#define HHI_GP0_PLL_CNTL5 0x054
30#define HHI_GP0_PLL_CNTL6 0x058 30#define HHI_GP0_PLL_CNTL6 0x058
31#define HHI_GP0_PLL_STS 0x05C 31#define HHI_GP0_PLL_STS 0x05C
32#define HHI_GP1_PLL_CNTL0 0x060
33#define HHI_GP1_PLL_CNTL1 0x064
34#define HHI_GP1_PLL_CNTL2 0x068
35#define HHI_GP1_PLL_CNTL3 0x06C
36#define HHI_GP1_PLL_CNTL4 0x070
37#define HHI_GP1_PLL_CNTL5 0x074
38#define HHI_GP1_PLL_CNTL6 0x078
39#define HHI_GP1_PLL_STS 0x07C
32#define HHI_PCIE_PLL_CNTL0 0x098 40#define HHI_PCIE_PLL_CNTL0 0x098
33#define HHI_PCIE_PLL_CNTL1 0x09C 41#define HHI_PCIE_PLL_CNTL1 0x09C
34#define HHI_PCIE_PLL_CNTL2 0x0A0 42#define HHI_PCIE_PLL_CNTL2 0x0A0
@@ -72,6 +80,11 @@
72#define HHI_SYS_CPUB_CLK_CNTL1 0x200 80#define HHI_SYS_CPUB_CLK_CNTL1 0x200
73#define HHI_SYS_CPUB_CLK_CNTL 0x208 81#define HHI_SYS_CPUB_CLK_CNTL 0x208
74#define HHI_VPU_CLKB_CNTL 0x20C 82#define HHI_VPU_CLKB_CNTL 0x20C
83#define HHI_SYS_CPU_CLK_CNTL2 0x210
84#define HHI_SYS_CPU_CLK_CNTL3 0x214
85#define HHI_SYS_CPU_CLK_CNTL4 0x218
86#define HHI_SYS_CPU_CLK_CNTL5 0x21c
87#define HHI_SYS_CPU_CLK_CNTL6 0x220
75#define HHI_GEN_CLK_CNTL 0x228 88#define HHI_GEN_CLK_CNTL 0x228
76#define HHI_VDIN_MEAS_CLK_CNTL 0x250 89#define HHI_VDIN_MEAS_CLK_CNTL 0x250
77#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254 90#define HHI_MIPIDSI_PHY_CLK_CNTL 0x254
@@ -216,7 +229,6 @@
216#define CLKID_CPUB_CLK_DYN1_DIV 221 229#define CLKID_CPUB_CLK_DYN1_DIV 221
217#define CLKID_CPUB_CLK_DYN1 222 230#define CLKID_CPUB_CLK_DYN1 222
218#define CLKID_CPUB_CLK_DYN 223 231#define CLKID_CPUB_CLK_DYN 223
219#define CLKID_CPUB_CLK 224
220#define CLKID_CPUB_CLK_DIV16_EN 225 232#define CLKID_CPUB_CLK_DIV16_EN 225
221#define CLKID_CPUB_CLK_DIV16 226 233#define CLKID_CPUB_CLK_DIV16 226
222#define CLKID_CPUB_CLK_DIV2 227 234#define CLKID_CPUB_CLK_DIV2 227
@@ -234,8 +246,17 @@
234#define CLKID_CPUB_CLK_AXI 239 246#define CLKID_CPUB_CLK_AXI 239
235#define CLKID_CPUB_CLK_TRACE_SEL 240 247#define CLKID_CPUB_CLK_TRACE_SEL 240
236#define CLKID_CPUB_CLK_TRACE 241 248#define CLKID_CPUB_CLK_TRACE 241
249#define CLKID_GP1_PLL_DCO 242
250#define CLKID_DSU_CLK_DYN0_SEL 244
251#define CLKID_DSU_CLK_DYN0_DIV 245
252#define CLKID_DSU_CLK_DYN0 246
253#define CLKID_DSU_CLK_DYN1_SEL 247
254#define CLKID_DSU_CLK_DYN1_DIV 248
255#define CLKID_DSU_CLK_DYN1 249
256#define CLKID_DSU_CLK_DYN 250
257#define CLKID_DSU_CLK_FINAL 251
237 258
238#define NR_CLKS 242 259#define NR_CLKS 256
239 260
240/* include the CLKIDs that have been made part of the DT binding */ 261/* include the CLKIDs that have been made part of the DT binding */
241#include <dt-bindings/clock/g12a-clkc.h> 262#include <dt-bindings/clock/g12a-clkc.h>
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index 449f6ac189d8..e940861a396b 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -11,8 +11,6 @@
11#include "clk-regmap.h" 11#include "clk-regmap.h"
12#include "clk-dualdiv.h" 12#include "clk-dualdiv.h"
13 13
14#define IN_PREFIX "ao-in-"
15
16/* AO Configuration Clock registers offsets */ 14/* AO Configuration Clock registers offsets */
17#define AO_RTI_PWR_CNTL_REG1 0x0c 15#define AO_RTI_PWR_CNTL_REG1 0x0c
18#define AO_RTI_PWR_CNTL_REG0 0x10 16#define AO_RTI_PWR_CNTL_REG0 0x10
@@ -31,7 +29,9 @@ static struct clk_regmap _name##_ao = { \
31 .hw.init = &(struct clk_init_data) { \ 29 .hw.init = &(struct clk_init_data) { \
32 .name = #_name "_ao", \ 30 .name = #_name "_ao", \
33 .ops = &clk_regmap_gate_ops, \ 31 .ops = &clk_regmap_gate_ops, \
34 .parent_names = (const char *[]){ IN_PREFIX "mpeg-clk" }, \ 32 .parent_data = &(const struct clk_parent_data) { \
33 .fw_name = "mpeg-clk", \
34 }, \
35 .num_parents = 1, \ 35 .num_parents = 1, \
36 .flags = CLK_IGNORE_UNUSED, \ 36 .flags = CLK_IGNORE_UNUSED, \
37 }, \ 37 }, \
@@ -52,7 +52,9 @@ static struct clk_regmap ao_cts_oscin = {
52 .hw.init = &(struct clk_init_data){ 52 .hw.init = &(struct clk_init_data){
53 .name = "ao_cts_oscin", 53 .name = "ao_cts_oscin",
54 .ops = &clk_regmap_gate_ro_ops, 54 .ops = &clk_regmap_gate_ro_ops,
55 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 55 .parent_data = &(const struct clk_parent_data) {
56 .fw_name = "xtal",
57 },
56 .num_parents = 1, 58 .num_parents = 1,
57 }, 59 },
58}; 60};
@@ -65,7 +67,7 @@ static struct clk_regmap ao_32k_pre = {
65 .hw.init = &(struct clk_init_data){ 67 .hw.init = &(struct clk_init_data){
66 .name = "ao_32k_pre", 68 .name = "ao_32k_pre",
67 .ops = &clk_regmap_gate_ops, 69 .ops = &clk_regmap_gate_ops,
68 .parent_names = (const char *[]){ "ao_cts_oscin" }, 70 .parent_hws = (const struct clk_hw *[]) { &ao_cts_oscin.hw },
69 .num_parents = 1, 71 .num_parents = 1,
70 }, 72 },
71}; 73};
@@ -112,7 +114,7 @@ static struct clk_regmap ao_32k_div = {
112 .hw.init = &(struct clk_init_data){ 114 .hw.init = &(struct clk_init_data){
113 .name = "ao_32k_div", 115 .name = "ao_32k_div",
114 .ops = &meson_clk_dualdiv_ops, 116 .ops = &meson_clk_dualdiv_ops,
115 .parent_names = (const char *[]){ "ao_32k_pre" }, 117 .parent_hws = (const struct clk_hw *[]) { &ao_32k_pre.hw },
116 .num_parents = 1, 118 .num_parents = 1,
117 }, 119 },
118}; 120};
@@ -127,8 +129,10 @@ static struct clk_regmap ao_32k_sel = {
127 .hw.init = &(struct clk_init_data){ 129 .hw.init = &(struct clk_init_data){
128 .name = "ao_32k_sel", 130 .name = "ao_32k_sel",
129 .ops = &clk_regmap_mux_ops, 131 .ops = &clk_regmap_mux_ops,
130 .parent_names = (const char *[]){ "ao_32k_div", 132 .parent_hws = (const struct clk_hw *[]) {
131 "ao_32k_pre" }, 133 &ao_32k_div.hw,
134 &ao_32k_pre.hw
135 },
132 .num_parents = 2, 136 .num_parents = 2,
133 .flags = CLK_SET_RATE_PARENT, 137 .flags = CLK_SET_RATE_PARENT,
134 }, 138 },
@@ -142,7 +146,7 @@ static struct clk_regmap ao_32k = {
142 .hw.init = &(struct clk_init_data){ 146 .hw.init = &(struct clk_init_data){
143 .name = "ao_32k", 147 .name = "ao_32k",
144 .ops = &clk_regmap_gate_ops, 148 .ops = &clk_regmap_gate_ops,
145 .parent_names = (const char *[]){ "ao_32k_sel" }, 149 .parent_hws = (const struct clk_hw *[]) { &ao_32k_sel.hw },
146 .num_parents = 1, 150 .num_parents = 1,
147 .flags = CLK_SET_RATE_PARENT, 151 .flags = CLK_SET_RATE_PARENT,
148 }, 152 },
@@ -159,10 +163,12 @@ static struct clk_regmap ao_cts_rtc_oscin = {
159 .hw.init = &(struct clk_init_data){ 163 .hw.init = &(struct clk_init_data){
160 .name = "ao_cts_rtc_oscin", 164 .name = "ao_cts_rtc_oscin",
161 .ops = &clk_regmap_mux_ops, 165 .ops = &clk_regmap_mux_ops,
162 .parent_names = (const char *[]){ IN_PREFIX "ext-32k-0", 166 .parent_data = (const struct clk_parent_data []) {
163 IN_PREFIX "ext-32k-1", 167 { .fw_name = "ext-32k-0", },
164 IN_PREFIX "ext-32k-2", 168 { .fw_name = "ext-32k-1", },
165 "ao_32k" }, 169 { .fw_name = "ext-32k-2", },
170 { .hw = &ao_32k.hw },
171 },
166 .num_parents = 4, 172 .num_parents = 4,
167 .flags = CLK_SET_RATE_PARENT, 173 .flags = CLK_SET_RATE_PARENT,
168 }, 174 },
@@ -178,8 +184,10 @@ static struct clk_regmap ao_clk81 = {
178 .hw.init = &(struct clk_init_data){ 184 .hw.init = &(struct clk_init_data){
179 .name = "ao_clk81", 185 .name = "ao_clk81",
180 .ops = &clk_regmap_mux_ro_ops, 186 .ops = &clk_regmap_mux_ro_ops,
181 .parent_names = (const char *[]){ IN_PREFIX "mpeg-clk", 187 .parent_data = (const struct clk_parent_data []) {
182 "ao_cts_rtc_oscin" }, 188 { .fw_name = "mpeg-clk", },
189 { .hw = &ao_cts_rtc_oscin.hw },
190 },
183 .num_parents = 2, 191 .num_parents = 2,
184 .flags = CLK_SET_RATE_PARENT, 192 .flags = CLK_SET_RATE_PARENT,
185 }, 193 },
@@ -208,8 +216,10 @@ static struct clk_regmap ao_cts_cec = {
208 * Until CCF gets fixed, adding this fake parent that won't 216 * Until CCF gets fixed, adding this fake parent that won't
209 * ever be registered should work around the problem 217 * ever be registered should work around the problem
210 */ 218 */
211 .parent_names = (const char *[]){ "fixme", 219 .parent_data = (const struct clk_parent_data []) {
212 "ao_cts_rtc_oscin" }, 220 { .name = "fixme", .index = -1, },
221 { .hw = &ao_cts_rtc_oscin.hw },
222 },
213 .num_parents = 2, 223 .num_parents = 2,
214 .flags = CLK_SET_RATE_PARENT, 224 .flags = CLK_SET_RATE_PARENT,
215 }, 225 },
@@ -261,14 +271,6 @@ static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
261 .num = NR_CLKS, 271 .num = NR_CLKS,
262}; 272};
263 273
264static const struct meson_aoclk_input gxbb_aoclk_inputs[] = {
265 { .name = "xtal", .required = true, },
266 { .name = "mpeg-clk", .required = true, },
267 {. name = "ext-32k-0", .required = false, },
268 {. name = "ext-32k-1", .required = false, },
269 {. name = "ext-32k-2", .required = false, },
270};
271
272static const struct meson_aoclk_data gxbb_aoclkc_data = { 274static const struct meson_aoclk_data gxbb_aoclkc_data = {
273 .reset_reg = AO_RTI_GEN_CNTL_REG0, 275 .reset_reg = AO_RTI_GEN_CNTL_REG0,
274 .num_reset = ARRAY_SIZE(gxbb_aoclk_reset), 276 .num_reset = ARRAY_SIZE(gxbb_aoclk_reset),
@@ -276,9 +278,6 @@ static const struct meson_aoclk_data gxbb_aoclkc_data = {
276 .num_clks = ARRAY_SIZE(gxbb_aoclk), 278 .num_clks = ARRAY_SIZE(gxbb_aoclk),
277 .clks = gxbb_aoclk, 279 .clks = gxbb_aoclk,
278 .hw_data = &gxbb_aoclk_onecell_data, 280 .hw_data = &gxbb_aoclk_onecell_data,
279 .inputs = gxbb_aoclk_inputs,
280 .num_inputs = ARRAY_SIZE(gxbb_aoclk_inputs),
281 .input_prefix = IN_PREFIX,
282}; 281};
283 282
284static const struct of_device_id gxbb_aoclkc_match_table[] = { 283static const struct of_device_id gxbb_aoclkc_match_table[] = {
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index dab16d9b1af8..7cfb998eeb3e 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -10,15 +10,12 @@
10#include <linux/platform_device.h> 10#include <linux/platform_device.h>
11 11
12#include "gxbb.h" 12#include "gxbb.h"
13#include "clk-input.h"
14#include "clk-regmap.h" 13#include "clk-regmap.h"
15#include "clk-pll.h" 14#include "clk-pll.h"
16#include "clk-mpll.h" 15#include "clk-mpll.h"
17#include "meson-eeclk.h" 16#include "meson-eeclk.h"
18#include "vid-pll-div.h" 17#include "vid-pll-div.h"
19 18
20#define IN_PREFIX "ee-in-"
21
22static DEFINE_SPINLOCK(meson_clk_lock); 19static DEFINE_SPINLOCK(meson_clk_lock);
23 20
24static const struct pll_params_table gxbb_gp0_pll_params_table[] = { 21static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
@@ -121,7 +118,9 @@ static struct clk_regmap gxbb_fixed_pll_dco = {
121 .hw.init = &(struct clk_init_data){ 118 .hw.init = &(struct clk_init_data){
122 .name = "fixed_pll_dco", 119 .name = "fixed_pll_dco",
123 .ops = &meson_clk_pll_ro_ops, 120 .ops = &meson_clk_pll_ro_ops,
124 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 121 .parent_data = &(const struct clk_parent_data) {
122 .fw_name = "xtal",
123 },
125 .num_parents = 1, 124 .num_parents = 1,
126 }, 125 },
127}; 126};
@@ -136,7 +135,9 @@ static struct clk_regmap gxbb_fixed_pll = {
136 .hw.init = &(struct clk_init_data){ 135 .hw.init = &(struct clk_init_data){
137 .name = "fixed_pll", 136 .name = "fixed_pll",
138 .ops = &clk_regmap_divider_ro_ops, 137 .ops = &clk_regmap_divider_ro_ops,
139 .parent_names = (const char *[]){ "fixed_pll_dco" }, 138 .parent_hws = (const struct clk_hw *[]) {
139 &gxbb_fixed_pll_dco.hw
140 },
140 .num_parents = 1, 141 .num_parents = 1,
141 /* 142 /*
142 * This clock won't ever change at runtime so 143 * This clock won't ever change at runtime so
@@ -151,7 +152,9 @@ static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
151 .hw.init = &(struct clk_init_data){ 152 .hw.init = &(struct clk_init_data){
152 .name = "hdmi_pll_pre_mult", 153 .name = "hdmi_pll_pre_mult",
153 .ops = &clk_fixed_factor_ops, 154 .ops = &clk_fixed_factor_ops,
154 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 155 .parent_data = &(const struct clk_parent_data) {
156 .fw_name = "xtal",
157 },
155 .num_parents = 1, 158 .num_parents = 1,
156 }, 159 },
157}; 160};
@@ -192,7 +195,9 @@ static struct clk_regmap gxbb_hdmi_pll_dco = {
192 .hw.init = &(struct clk_init_data){ 195 .hw.init = &(struct clk_init_data){
193 .name = "hdmi_pll_dco", 196 .name = "hdmi_pll_dco",
194 .ops = &meson_clk_pll_ro_ops, 197 .ops = &meson_clk_pll_ro_ops,
195 .parent_names = (const char *[]){ "hdmi_pll_pre_mult" }, 198 .parent_hws = (const struct clk_hw *[]) {
199 &gxbb_hdmi_pll_pre_mult.hw
200 },
196 .num_parents = 1, 201 .num_parents = 1,
197 /* 202 /*
198 * Display directly handle hdmi pll registers ATM, we need 203 * Display directly handle hdmi pll registers ATM, we need
@@ -244,7 +249,9 @@ static struct clk_regmap gxl_hdmi_pll_dco = {
244 .hw.init = &(struct clk_init_data){ 249 .hw.init = &(struct clk_init_data){
245 .name = "hdmi_pll_dco", 250 .name = "hdmi_pll_dco",
246 .ops = &meson_clk_pll_ro_ops, 251 .ops = &meson_clk_pll_ro_ops,
247 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 252 .parent_data = &(const struct clk_parent_data) {
253 .fw_name = "xtal",
254 },
248 .num_parents = 1, 255 .num_parents = 1,
249 /* 256 /*
250 * Display directly handle hdmi pll registers ATM, we need 257 * Display directly handle hdmi pll registers ATM, we need
@@ -264,7 +271,9 @@ static struct clk_regmap gxbb_hdmi_pll_od = {
264 .hw.init = &(struct clk_init_data){ 271 .hw.init = &(struct clk_init_data){
265 .name = "hdmi_pll_od", 272 .name = "hdmi_pll_od",
266 .ops = &clk_regmap_divider_ro_ops, 273 .ops = &clk_regmap_divider_ro_ops,
267 .parent_names = (const char *[]){ "hdmi_pll_dco" }, 274 .parent_hws = (const struct clk_hw *[]) {
275 &gxbb_hdmi_pll_dco.hw
276 },
268 .num_parents = 1, 277 .num_parents = 1,
269 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 278 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
270 }, 279 },
@@ -280,7 +289,9 @@ static struct clk_regmap gxbb_hdmi_pll_od2 = {
280 .hw.init = &(struct clk_init_data){ 289 .hw.init = &(struct clk_init_data){
281 .name = "hdmi_pll_od2", 290 .name = "hdmi_pll_od2",
282 .ops = &clk_regmap_divider_ro_ops, 291 .ops = &clk_regmap_divider_ro_ops,
283 .parent_names = (const char *[]){ "hdmi_pll_od" }, 292 .parent_hws = (const struct clk_hw *[]) {
293 &gxbb_hdmi_pll_od.hw
294 },
284 .num_parents = 1, 295 .num_parents = 1,
285 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 296 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
286 }, 297 },
@@ -296,7 +307,9 @@ static struct clk_regmap gxbb_hdmi_pll = {
296 .hw.init = &(struct clk_init_data){ 307 .hw.init = &(struct clk_init_data){
297 .name = "hdmi_pll", 308 .name = "hdmi_pll",
298 .ops = &clk_regmap_divider_ro_ops, 309 .ops = &clk_regmap_divider_ro_ops,
299 .parent_names = (const char *[]){ "hdmi_pll_od2" }, 310 .parent_hws = (const struct clk_hw *[]) {
311 &gxbb_hdmi_pll_od2.hw
312 },
300 .num_parents = 1, 313 .num_parents = 1,
301 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 314 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
302 }, 315 },
@@ -312,7 +325,9 @@ static struct clk_regmap gxl_hdmi_pll_od = {
312 .hw.init = &(struct clk_init_data){ 325 .hw.init = &(struct clk_init_data){
313 .name = "hdmi_pll_od", 326 .name = "hdmi_pll_od",
314 .ops = &clk_regmap_divider_ro_ops, 327 .ops = &clk_regmap_divider_ro_ops,
315 .parent_names = (const char *[]){ "hdmi_pll_dco" }, 328 .parent_hws = (const struct clk_hw *[]) {
329 &gxl_hdmi_pll_dco.hw
330 },
316 .num_parents = 1, 331 .num_parents = 1,
317 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 332 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
318 }, 333 },
@@ -328,7 +343,9 @@ static struct clk_regmap gxl_hdmi_pll_od2 = {
328 .hw.init = &(struct clk_init_data){ 343 .hw.init = &(struct clk_init_data){
329 .name = "hdmi_pll_od2", 344 .name = "hdmi_pll_od2",
330 .ops = &clk_regmap_divider_ro_ops, 345 .ops = &clk_regmap_divider_ro_ops,
331 .parent_names = (const char *[]){ "hdmi_pll_od" }, 346 .parent_hws = (const struct clk_hw *[]) {
347 &gxl_hdmi_pll_od.hw
348 },
332 .num_parents = 1, 349 .num_parents = 1,
333 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 350 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
334 }, 351 },
@@ -344,7 +361,9 @@ static struct clk_regmap gxl_hdmi_pll = {
344 .hw.init = &(struct clk_init_data){ 361 .hw.init = &(struct clk_init_data){
345 .name = "hdmi_pll", 362 .name = "hdmi_pll",
346 .ops = &clk_regmap_divider_ro_ops, 363 .ops = &clk_regmap_divider_ro_ops,
347 .parent_names = (const char *[]){ "hdmi_pll_od2" }, 364 .parent_hws = (const struct clk_hw *[]) {
365 &gxl_hdmi_pll_od2.hw
366 },
348 .num_parents = 1, 367 .num_parents = 1,
349 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT, 368 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
350 }, 369 },
@@ -381,7 +400,9 @@ static struct clk_regmap gxbb_sys_pll_dco = {
381 .hw.init = &(struct clk_init_data){ 400 .hw.init = &(struct clk_init_data){
382 .name = "sys_pll_dco", 401 .name = "sys_pll_dco",
383 .ops = &meson_clk_pll_ro_ops, 402 .ops = &meson_clk_pll_ro_ops,
384 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 403 .parent_data = &(const struct clk_parent_data) {
404 .fw_name = "xtal",
405 },
385 .num_parents = 1, 406 .num_parents = 1,
386 }, 407 },
387}; 408};
@@ -396,7 +417,9 @@ static struct clk_regmap gxbb_sys_pll = {
396 .hw.init = &(struct clk_init_data){ 417 .hw.init = &(struct clk_init_data){
397 .name = "sys_pll", 418 .name = "sys_pll",
398 .ops = &clk_regmap_divider_ro_ops, 419 .ops = &clk_regmap_divider_ro_ops,
399 .parent_names = (const char *[]){ "sys_pll_dco" }, 420 .parent_hws = (const struct clk_hw *[]) {
421 &gxbb_sys_pll_dco.hw
422 },
400 .num_parents = 1, 423 .num_parents = 1,
401 .flags = CLK_SET_RATE_PARENT, 424 .flags = CLK_SET_RATE_PARENT,
402 }, 425 },
@@ -442,7 +465,9 @@ static struct clk_regmap gxbb_gp0_pll_dco = {
442 .hw.init = &(struct clk_init_data){ 465 .hw.init = &(struct clk_init_data){
443 .name = "gp0_pll_dco", 466 .name = "gp0_pll_dco",
444 .ops = &meson_clk_pll_ops, 467 .ops = &meson_clk_pll_ops,
445 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 468 .parent_data = &(const struct clk_parent_data) {
469 .fw_name = "xtal",
470 },
446 .num_parents = 1, 471 .num_parents = 1,
447 }, 472 },
448}; 473};
@@ -494,7 +519,9 @@ static struct clk_regmap gxl_gp0_pll_dco = {
494 .hw.init = &(struct clk_init_data){ 519 .hw.init = &(struct clk_init_data){
495 .name = "gp0_pll_dco", 520 .name = "gp0_pll_dco",
496 .ops = &meson_clk_pll_ops, 521 .ops = &meson_clk_pll_ops,
497 .parent_names = (const char *[]){ IN_PREFIX "xtal" }, 522 .parent_data = &(const struct clk_parent_data) {
523 .fw_name = "xtal",
524 },
498 .num_parents = 1, 525 .num_parents = 1,
499 }, 526 },
500}; 527};
@@ -509,7 +536,17 @@ static struct clk_regmap gxbb_gp0_pll = {
509 .hw.init = &(struct clk_init_data){ 536 .hw.init = &(struct clk_init_data){
510 .name = "gp0_pll", 537 .name = "gp0_pll",
511 .ops = &clk_regmap_divider_ops, 538 .ops = &clk_regmap_divider_ops,
512 .parent_names = (const char *[]){ "gp0_pll_dco" }, 539 .parent_data = &(const struct clk_parent_data) {
540 /*
541 * Note:
542 * GXL and GXBB have different gp0_pll_dco (with
543 * different struct clk_hw). We fallback to the global
544 * naming string mechanism so gp0_pll picks up the
545 * appropriate one.
546 */
547 .name = "gp0_pll_dco",
548 .index = -1,
549 },
513 .num_parents = 1, 550 .num_parents = 1,
514 .flags = CLK_SET_RATE_PARENT, 551 .flags = CLK_SET_RATE_PARENT,
515 }, 552 },
@@ -521,7 +558,9 @@ static struct clk_fixed_factor gxbb_fclk_div2_div = {
521 .hw.init = &(struct clk_init_data){ 558 .hw.init = &(struct clk_init_data){
522 .name = "fclk_div2_div", 559 .name = "fclk_div2_div",
523 .ops = &clk_fixed_factor_ops, 560 .ops = &clk_fixed_factor_ops,
524 .parent_names = (const char *[]){ "fixed_pll" }, 561 .parent_hws = (const struct clk_hw *[]) {
562 &gxbb_fixed_pll.hw
563 },
525 .num_parents = 1, 564 .num_parents = 1,
526 }, 565 },
527}; 566};
@@ -534,7 +573,9 @@ static struct clk_regmap gxbb_fclk_div2 = {
534 .hw.init = &(struct clk_init_data){ 573 .hw.init = &(struct clk_init_data){
535 .name = "fclk_div2", 574 .name = "fclk_div2",
536 .ops = &clk_regmap_gate_ops, 575 .ops = &clk_regmap_gate_ops,
537 .parent_names = (const char *[]){ "fclk_div2_div" }, 576 .parent_hws = (const struct clk_hw *[]) {
577 &gxbb_fclk_div2_div.hw
578 },
538 .num_parents = 1, 579 .num_parents = 1,
539 .flags = CLK_IS_CRITICAL, 580 .flags = CLK_IS_CRITICAL,
540 }, 581 },
@@ -546,7 +587,7 @@ static struct clk_fixed_factor gxbb_fclk_div3_div = {
546 .hw.init = &(struct clk_init_data){ 587 .hw.init = &(struct clk_init_data){
547 .name = "fclk_div3_div", 588 .name = "fclk_div3_div",
548 .ops = &clk_fixed_factor_ops, 589 .ops = &clk_fixed_factor_ops,
549 .parent_names = (const char *[]){ "fixed_pll" }, 590 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
550 .num_parents = 1, 591 .num_parents = 1,
551 }, 592 },
552}; 593};
@@ -559,7 +600,9 @@ static struct clk_regmap gxbb_fclk_div3 = {
559 .hw.init = &(struct clk_init_data){ 600 .hw.init = &(struct clk_init_data){
560 .name = "fclk_div3", 601 .name = "fclk_div3",
561 .ops = &clk_regmap_gate_ops, 602 .ops = &clk_regmap_gate_ops,
562 .parent_names = (const char *[]){ "fclk_div3_div" }, 603 .parent_hws = (const struct clk_hw *[]) {
604 &gxbb_fclk_div3_div.hw
605 },
563 .num_parents = 1, 606 .num_parents = 1,
564 /* 607 /*
565 * FIXME: 608 * FIXME:
@@ -582,7 +625,7 @@ static struct clk_fixed_factor gxbb_fclk_div4_div = {
582 .hw.init = &(struct clk_init_data){ 625 .hw.init = &(struct clk_init_data){
583 .name = "fclk_div4_div", 626 .name = "fclk_div4_div",
584 .ops = &clk_fixed_factor_ops, 627 .ops = &clk_fixed_factor_ops,
585 .parent_names = (const char *[]){ "fixed_pll" }, 628 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
586 .num_parents = 1, 629 .num_parents = 1,
587 }, 630 },
588}; 631};
@@ -595,7 +638,9 @@ static struct clk_regmap gxbb_fclk_div4 = {
595 .hw.init = &(struct clk_init_data){ 638 .hw.init = &(struct clk_init_data){
596 .name = "fclk_div4", 639 .name = "fclk_div4",
597 .ops = &clk_regmap_gate_ops, 640 .ops = &clk_regmap_gate_ops,
598 .parent_names = (const char *[]){ "fclk_div4_div" }, 641 .parent_hws = (const struct clk_hw *[]) {
642 &gxbb_fclk_div4_div.hw
643 },
599 .num_parents = 1, 644 .num_parents = 1,
600 }, 645 },
601}; 646};
@@ -606,7 +651,7 @@ static struct clk_fixed_factor gxbb_fclk_div5_div = {
606 .hw.init = &(struct clk_init_data){ 651 .hw.init = &(struct clk_init_data){
607 .name = "fclk_div5_div", 652 .name = "fclk_div5_div",
608 .ops = &clk_fixed_factor_ops, 653 .ops = &clk_fixed_factor_ops,
609 .parent_names = (const char *[]){ "fixed_pll" }, 654 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
610 .num_parents = 1, 655 .num_parents = 1,
611 }, 656 },
612}; 657};
@@ -619,7 +664,9 @@ static struct clk_regmap gxbb_fclk_div5 = {
619 .hw.init = &(struct clk_init_data){ 664 .hw.init = &(struct clk_init_data){
620 .name = "fclk_div5", 665 .name = "fclk_div5",
621 .ops = &clk_regmap_gate_ops, 666 .ops = &clk_regmap_gate_ops,
622 .parent_names = (const char *[]){ "fclk_div5_div" }, 667 .parent_hws = (const struct clk_hw *[]) {
668 &gxbb_fclk_div5_div.hw
669 },
623 .num_parents = 1, 670 .num_parents = 1,
624 }, 671 },
625}; 672};
@@ -630,7 +677,7 @@ static struct clk_fixed_factor gxbb_fclk_div7_div = {
630 .hw.init = &(struct clk_init_data){ 677 .hw.init = &(struct clk_init_data){
631 .name = "fclk_div7_div", 678 .name = "fclk_div7_div",
632 .ops = &clk_fixed_factor_ops, 679 .ops = &clk_fixed_factor_ops,
633 .parent_names = (const char *[]){ "fixed_pll" }, 680 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
634 .num_parents = 1, 681 .num_parents = 1,
635 }, 682 },
636}; 683};
@@ -643,7 +690,9 @@ static struct clk_regmap gxbb_fclk_div7 = {
643 .hw.init = &(struct clk_init_data){ 690 .hw.init = &(struct clk_init_data){
644 .name = "fclk_div7", 691 .name = "fclk_div7",
645 .ops = &clk_regmap_gate_ops, 692 .ops = &clk_regmap_gate_ops,
646 .parent_names = (const char *[]){ "fclk_div7_div" }, 693 .parent_hws = (const struct clk_hw *[]) {
694 &gxbb_fclk_div7_div.hw
695 },
647 .num_parents = 1, 696 .num_parents = 1,
648 }, 697 },
649}; 698};
@@ -657,7 +706,7 @@ static struct clk_regmap gxbb_mpll_prediv = {
657 .hw.init = &(struct clk_init_data){ 706 .hw.init = &(struct clk_init_data){
658 .name = "mpll_prediv", 707 .name = "mpll_prediv",
659 .ops = &clk_regmap_divider_ro_ops, 708 .ops = &clk_regmap_divider_ro_ops,
660 .parent_names = (const char *[]){ "fixed_pll" }, 709 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
661 .num_parents = 1, 710 .num_parents = 1,
662 }, 711 },
663}; 712};
@@ -684,7 +733,9 @@ static struct clk_regmap gxbb_mpll0_div = {
684 .hw.init = &(struct clk_init_data){ 733 .hw.init = &(struct clk_init_data){
685 .name = "mpll0_div", 734 .name = "mpll0_div",
686 .ops = &meson_clk_mpll_ops, 735 .ops = &meson_clk_mpll_ops,
687 .parent_names = (const char *[]){ "mpll_prediv" }, 736 .parent_hws = (const struct clk_hw *[]) {
737 &gxbb_mpll_prediv.hw
738 },
688 .num_parents = 1, 739 .num_parents = 1,
689 }, 740 },
690}; 741};
@@ -697,7 +748,7 @@ static struct clk_regmap gxbb_mpll0 = {
697 .hw.init = &(struct clk_init_data){ 748 .hw.init = &(struct clk_init_data){
698 .name = "mpll0", 749 .name = "mpll0",
699 .ops = &clk_regmap_gate_ops, 750 .ops = &clk_regmap_gate_ops,
700 .parent_names = (const char *[]){ "mpll0_div" }, 751 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll0_div.hw },
701 .num_parents = 1, 752 .num_parents = 1,
702 .flags = CLK_SET_RATE_PARENT, 753 .flags = CLK_SET_RATE_PARENT,
703 }, 754 },
@@ -725,7 +776,9 @@ static struct clk_regmap gxbb_mpll1_div = {
725 .hw.init = &(struct clk_init_data){ 776 .hw.init = &(struct clk_init_data){
726 .name = "mpll1_div", 777 .name = "mpll1_div",
727 .ops = &meson_clk_mpll_ops, 778 .ops = &meson_clk_mpll_ops,
728 .parent_names = (const char *[]){ "mpll_prediv" }, 779 .parent_hws = (const struct clk_hw *[]) {
780 &gxbb_mpll_prediv.hw
781 },
729 .num_parents = 1, 782 .num_parents = 1,
730 }, 783 },
731}; 784};
@@ -738,7 +791,7 @@ static struct clk_regmap gxbb_mpll1 = {
738 .hw.init = &(struct clk_init_data){ 791 .hw.init = &(struct clk_init_data){
739 .name = "mpll1", 792 .name = "mpll1",
740 .ops = &clk_regmap_gate_ops, 793 .ops = &clk_regmap_gate_ops,
741 .parent_names = (const char *[]){ "mpll1_div" }, 794 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw },
742 .num_parents = 1, 795 .num_parents = 1,
743 .flags = CLK_SET_RATE_PARENT, 796 .flags = CLK_SET_RATE_PARENT,
744 }, 797 },
@@ -766,7 +819,9 @@ static struct clk_regmap gxbb_mpll2_div = {
766 .hw.init = &(struct clk_init_data){ 819 .hw.init = &(struct clk_init_data){
767 .name = "mpll2_div", 820 .name = "mpll2_div",
768 .ops = &meson_clk_mpll_ops, 821 .ops = &meson_clk_mpll_ops,
769 .parent_names = (const char *[]){ "mpll_prediv" }, 822 .parent_hws = (const struct clk_hw *[]) {
823 &gxbb_mpll_prediv.hw
824 },
770 .num_parents = 1, 825 .num_parents = 1,
771 }, 826 },
772}; 827};
@@ -779,16 +834,21 @@ static struct clk_regmap gxbb_mpll2 = {
779 .hw.init = &(struct clk_init_data){ 834 .hw.init = &(struct clk_init_data){
780 .name = "mpll2", 835 .name = "mpll2",
781 .ops = &clk_regmap_gate_ops, 836 .ops = &clk_regmap_gate_ops,
782 .parent_names = (const char *[]){ "mpll2_div" }, 837 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw },
783 .num_parents = 1, 838 .num_parents = 1,
784 .flags = CLK_SET_RATE_PARENT, 839 .flags = CLK_SET_RATE_PARENT,
785 }, 840 },
786}; 841};
787 842
788static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; 843static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
789static const char * const clk81_parent_names[] = { 844static const struct clk_parent_data clk81_parent_data[] = {
790 IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", 845 { .fw_name = "xtal", },
791 "fclk_div3", "fclk_div5" 846 { .hw = &gxbb_fclk_div7.hw },
847 { .hw = &gxbb_mpll1.hw },
848 { .hw = &gxbb_mpll2.hw },
849 { .hw = &gxbb_fclk_div4.hw },
850 { .hw = &gxbb_fclk_div3.hw },
851 { .hw = &gxbb_fclk_div5.hw },
792}; 852};
793 853
794static struct clk_regmap gxbb_mpeg_clk_sel = { 854static struct clk_regmap gxbb_mpeg_clk_sel = {
@@ -806,8 +866,8 @@ static struct clk_regmap gxbb_mpeg_clk_sel = {
806 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 866 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
807 * fclk_div4, fclk_div3, fclk_div5 867 * fclk_div4, fclk_div3, fclk_div5
808 */ 868 */
809 .parent_names = clk81_parent_names, 869 .parent_data = clk81_parent_data,
810 .num_parents = ARRAY_SIZE(clk81_parent_names), 870 .num_parents = ARRAY_SIZE(clk81_parent_data),
811 }, 871 },
812}; 872};
813 873
@@ -820,7 +880,9 @@ static struct clk_regmap gxbb_mpeg_clk_div = {
820 .hw.init = &(struct clk_init_data){ 880 .hw.init = &(struct clk_init_data){
821 .name = "mpeg_clk_div", 881 .name = "mpeg_clk_div",
822 .ops = &clk_regmap_divider_ro_ops, 882 .ops = &clk_regmap_divider_ro_ops,
823 .parent_names = (const char *[]){ "mpeg_clk_sel" }, 883 .parent_hws = (const struct clk_hw *[]) {
884 &gxbb_mpeg_clk_sel.hw
885 },
824 .num_parents = 1, 886 .num_parents = 1,
825 }, 887 },
826}; 888};
@@ -834,7 +896,9 @@ static struct clk_regmap gxbb_clk81 = {
834 .hw.init = &(struct clk_init_data){ 896 .hw.init = &(struct clk_init_data){
835 .name = "clk81", 897 .name = "clk81",
836 .ops = &clk_regmap_gate_ops, 898 .ops = &clk_regmap_gate_ops,
837 .parent_names = (const char *[]){ "mpeg_clk_div" }, 899 .parent_hws = (const struct clk_hw *[]) {
900 &gxbb_mpeg_clk_div.hw
901 },
838 .num_parents = 1, 902 .num_parents = 1,
839 .flags = CLK_IS_CRITICAL, 903 .flags = CLK_IS_CRITICAL,
840 }, 904 },
@@ -850,7 +914,10 @@ static struct clk_regmap gxbb_sar_adc_clk_sel = {
850 .name = "sar_adc_clk_sel", 914 .name = "sar_adc_clk_sel",
851 .ops = &clk_regmap_mux_ops, 915 .ops = &clk_regmap_mux_ops,
852 /* NOTE: The datasheet doesn't list the parents for bit 10 */ 916 /* NOTE: The datasheet doesn't list the parents for bit 10 */
853 .parent_names = (const char *[]){ IN_PREFIX "xtal", "clk81", }, 917 .parent_data = (const struct clk_parent_data []) {
918 { .fw_name = "xtal", },
919 { .hw = &gxbb_clk81.hw },
920 },
854 .num_parents = 2, 921 .num_parents = 2,
855 }, 922 },
856}; 923};
@@ -864,7 +931,9 @@ static struct clk_regmap gxbb_sar_adc_clk_div = {
864 .hw.init = &(struct clk_init_data){ 931 .hw.init = &(struct clk_init_data){
865 .name = "sar_adc_clk_div", 932 .name = "sar_adc_clk_div",
866 .ops = &clk_regmap_divider_ops, 933 .ops = &clk_regmap_divider_ops,
867 .parent_names = (const char *[]){ "sar_adc_clk_sel" }, 934 .parent_hws = (const struct clk_hw *[]) {
935 &gxbb_sar_adc_clk_sel.hw
936 },
868 .num_parents = 1, 937 .num_parents = 1,
869 }, 938 },
870}; 939};
@@ -877,7 +946,9 @@ static struct clk_regmap gxbb_sar_adc_clk = {
877 .hw.init = &(struct clk_init_data){ 946 .hw.init = &(struct clk_init_data){
878 .name = "sar_adc_clk", 947 .name = "sar_adc_clk",
879 .ops = &clk_regmap_gate_ops, 948 .ops = &clk_regmap_gate_ops,
880 .parent_names = (const char *[]){ "sar_adc_clk_div" }, 949 .parent_hws = (const struct clk_hw *[]) {
950 &gxbb_sar_adc_clk_div.hw
951 },
881 .num_parents = 1, 952 .num_parents = 1,
882 .flags = CLK_SET_RATE_PARENT, 953 .flags = CLK_SET_RATE_PARENT,
883 }, 954 },
@@ -888,9 +959,15 @@ static struct clk_regmap gxbb_sar_adc_clk = {
888 * muxed by a glitch-free switch. 959 * muxed by a glitch-free switch.
889 */ 960 */
890 961
891static const char * const gxbb_mali_0_1_parent_names[] = { 962static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = {
892 IN_PREFIX "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7", 963 { .fw_name = "xtal", },
893 "fclk_div4", "fclk_div3", "fclk_div5" 964 { .hw = &gxbb_gp0_pll.hw },
965 { .hw = &gxbb_mpll2.hw },
966 { .hw = &gxbb_mpll1.hw },
967 { .hw = &gxbb_fclk_div7.hw },
968 { .hw = &gxbb_fclk_div4.hw },
969 { .hw = &gxbb_fclk_div3.hw },
970 { .hw = &gxbb_fclk_div5.hw },
894}; 971};
895 972
896static struct clk_regmap gxbb_mali_0_sel = { 973static struct clk_regmap gxbb_mali_0_sel = {
@@ -907,7 +984,7 @@ static struct clk_regmap gxbb_mali_0_sel = {
907 * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 984 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
908 * fclk_div4, fclk_div3, fclk_div5 985 * fclk_div4, fclk_div3, fclk_div5
909 */ 986 */
910 .parent_names = gxbb_mali_0_1_parent_names, 987 .parent_data = gxbb_mali_0_1_parent_data,
911 .num_parents = 8, 988 .num_parents = 8,
912 .flags = CLK_SET_RATE_NO_REPARENT, 989 .flags = CLK_SET_RATE_NO_REPARENT,
913 }, 990 },
@@ -922,7 +999,9 @@ static struct clk_regmap gxbb_mali_0_div = {
922 .hw.init = &(struct clk_init_data){ 999 .hw.init = &(struct clk_init_data){
923 .name = "mali_0_div", 1000 .name = "mali_0_div",
924 .ops = &clk_regmap_divider_ops, 1001 .ops = &clk_regmap_divider_ops,
925 .parent_names = (const char *[]){ "mali_0_sel" }, 1002 .parent_hws = (const struct clk_hw *[]) {
1003 &gxbb_mali_0_sel.hw
1004 },
926 .num_parents = 1, 1005 .num_parents = 1,
927 .flags = CLK_SET_RATE_NO_REPARENT, 1006 .flags = CLK_SET_RATE_NO_REPARENT,
928 }, 1007 },
@@ -936,7 +1015,9 @@ static struct clk_regmap gxbb_mali_0 = {
936 .hw.init = &(struct clk_init_data){ 1015 .hw.init = &(struct clk_init_data){
937 .name = "mali_0", 1016 .name = "mali_0",
938 .ops = &clk_regmap_gate_ops, 1017 .ops = &clk_regmap_gate_ops,
939 .parent_names = (const char *[]){ "mali_0_div" }, 1018 .parent_hws = (const struct clk_hw *[]) {
1019 &gxbb_mali_0_div.hw
1020 },
940 .num_parents = 1, 1021 .num_parents = 1,
941 .flags = CLK_SET_RATE_PARENT, 1022 .flags = CLK_SET_RATE_PARENT,
942 }, 1023 },
@@ -956,7 +1037,7 @@ static struct clk_regmap gxbb_mali_1_sel = {
956 * xtal, gp0_pll, mpll2, mpll1, fclk_div7, 1037 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
957 * fclk_div4, fclk_div3, fclk_div5 1038 * fclk_div4, fclk_div3, fclk_div5
958 */ 1039 */
959 .parent_names = gxbb_mali_0_1_parent_names, 1040 .parent_data = gxbb_mali_0_1_parent_data,
960 .num_parents = 8, 1041 .num_parents = 8,
961 .flags = CLK_SET_RATE_NO_REPARENT, 1042 .flags = CLK_SET_RATE_NO_REPARENT,
962 }, 1043 },
@@ -971,7 +1052,9 @@ static struct clk_regmap gxbb_mali_1_div = {
971 .hw.init = &(struct clk_init_data){ 1052 .hw.init = &(struct clk_init_data){
972 .name = "mali_1_div", 1053 .name = "mali_1_div",
973 .ops = &clk_regmap_divider_ops, 1054 .ops = &clk_regmap_divider_ops,
974 .parent_names = (const char *[]){ "mali_1_sel" }, 1055 .parent_hws = (const struct clk_hw *[]) {
1056 &gxbb_mali_1_sel.hw
1057 },
975 .num_parents = 1, 1058 .num_parents = 1,
976 .flags = CLK_SET_RATE_NO_REPARENT, 1059 .flags = CLK_SET_RATE_NO_REPARENT,
977 }, 1060 },
@@ -985,14 +1068,17 @@ static struct clk_regmap gxbb_mali_1 = {
985 .hw.init = &(struct clk_init_data){ 1068 .hw.init = &(struct clk_init_data){
986 .name = "mali_1", 1069 .name = "mali_1",
987 .ops = &clk_regmap_gate_ops, 1070 .ops = &clk_regmap_gate_ops,
988 .parent_names = (const char *[]){ "mali_1_div" }, 1071 .parent_hws = (const struct clk_hw *[]) {
1072 &gxbb_mali_1_div.hw
1073 },
989 .num_parents = 1, 1074 .num_parents = 1,
990 .flags = CLK_SET_RATE_PARENT, 1075 .flags = CLK_SET_RATE_PARENT,
991 }, 1076 },
992}; 1077};
993 1078
994static const char * const gxbb_mali_parent_names[] = { 1079static const struct clk_hw *gxbb_mali_parent_hws[] = {
995 "mali_0", "mali_1" 1080 &gxbb_mali_0.hw,
1081 &gxbb_mali_1.hw,
996}; 1082};
997 1083
998static struct clk_regmap gxbb_mali = { 1084static struct clk_regmap gxbb_mali = {
@@ -1004,7 +1090,7 @@ static struct clk_regmap gxbb_mali = {
1004 .hw.init = &(struct clk_init_data){ 1090 .hw.init = &(struct clk_init_data){
1005 .name = "mali", 1091 .name = "mali",
1006 .ops = &clk_regmap_mux_ops, 1092 .ops = &clk_regmap_mux_ops,
1007 .parent_names = gxbb_mali_parent_names, 1093 .parent_hws = gxbb_mali_parent_hws,
1008 .num_parents = 2, 1094 .num_parents = 2,
1009 .flags = CLK_SET_RATE_NO_REPARENT, 1095 .flags = CLK_SET_RATE_NO_REPARENT,
1010 }, 1096 },
@@ -1021,7 +1107,11 @@ static struct clk_regmap gxbb_cts_amclk_sel = {
1021 .hw.init = &(struct clk_init_data){ 1107 .hw.init = &(struct clk_init_data){
1022 .name = "cts_amclk_sel", 1108 .name = "cts_amclk_sel",
1023 .ops = &clk_regmap_mux_ops, 1109 .ops = &clk_regmap_mux_ops,
1024 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, 1110 .parent_hws = (const struct clk_hw *[]) {
1111 &gxbb_mpll0.hw,
1112 &gxbb_mpll1.hw,
1113 &gxbb_mpll2.hw,
1114 },
1025 .num_parents = 3, 1115 .num_parents = 3,
1026 }, 1116 },
1027}; 1117};
@@ -1036,7 +1126,9 @@ static struct clk_regmap gxbb_cts_amclk_div = {
1036 .hw.init = &(struct clk_init_data){ 1126 .hw.init = &(struct clk_init_data){
1037 .name = "cts_amclk_div", 1127 .name = "cts_amclk_div",
1038 .ops = &clk_regmap_divider_ops, 1128 .ops = &clk_regmap_divider_ops,
1039 .parent_names = (const char *[]){ "cts_amclk_sel" }, 1129 .parent_hws = (const struct clk_hw *[]) {
1130 &gxbb_cts_amclk_sel.hw
1131 },
1040 .num_parents = 1, 1132 .num_parents = 1,
1041 .flags = CLK_SET_RATE_PARENT, 1133 .flags = CLK_SET_RATE_PARENT,
1042 }, 1134 },
@@ -1050,7 +1142,9 @@ static struct clk_regmap gxbb_cts_amclk = {
1050 .hw.init = &(struct clk_init_data){ 1142 .hw.init = &(struct clk_init_data){
1051 .name = "cts_amclk", 1143 .name = "cts_amclk",
1052 .ops = &clk_regmap_gate_ops, 1144 .ops = &clk_regmap_gate_ops,
1053 .parent_names = (const char *[]){ "cts_amclk_div" }, 1145 .parent_hws = (const struct clk_hw *[]) {
1146 &gxbb_cts_amclk_div.hw
1147 },
1054 .num_parents = 1, 1148 .num_parents = 1,
1055 .flags = CLK_SET_RATE_PARENT, 1149 .flags = CLK_SET_RATE_PARENT,
1056 }, 1150 },
@@ -1067,7 +1161,11 @@ static struct clk_regmap gxbb_cts_mclk_i958_sel = {
1067 .hw.init = &(struct clk_init_data) { 1161 .hw.init = &(struct clk_init_data) {
1068 .name = "cts_mclk_i958_sel", 1162 .name = "cts_mclk_i958_sel",
1069 .ops = &clk_regmap_mux_ops, 1163 .ops = &clk_regmap_mux_ops,
1070 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" }, 1164 .parent_hws = (const struct clk_hw *[]) {
1165 &gxbb_mpll0.hw,
1166 &gxbb_mpll1.hw,
1167 &gxbb_mpll2.hw,
1168 },
1071 .num_parents = 3, 1169 .num_parents = 3,
1072 }, 1170 },
1073}; 1171};
@@ -1082,7 +1180,9 @@ static struct clk_regmap gxbb_cts_mclk_i958_div = {
1082 .hw.init = &(struct clk_init_data) { 1180 .hw.init = &(struct clk_init_data) {
1083 .name = "cts_mclk_i958_div", 1181 .name = "cts_mclk_i958_div",
1084 .ops = &clk_regmap_divider_ops, 1182 .ops = &clk_regmap_divider_ops,
1085 .parent_names = (const char *[]){ "cts_mclk_i958_sel" }, 1183 .parent_hws = (const struct clk_hw *[]) {
1184 &gxbb_cts_mclk_i958_sel.hw
1185 },
1086 .num_parents = 1, 1186 .num_parents = 1,
1087 .flags = CLK_SET_RATE_PARENT, 1187 .flags = CLK_SET_RATE_PARENT,
1088 }, 1188 },
@@ -1096,7 +1196,9 @@ static struct clk_regmap gxbb_cts_mclk_i958 = {
1096 .hw.init = &(struct clk_init_data){ 1196 .hw.init = &(struct clk_init_data){
1097 .name = "cts_mclk_i958", 1197 .name = "cts_mclk_i958",
1098 .ops = &clk_regmap_gate_ops, 1198 .ops = &clk_regmap_gate_ops,
1099 .parent_names = (const char *[]){ "cts_mclk_i958_div" }, 1199 .parent_hws = (const struct clk_hw *[]) {
1200 &gxbb_cts_mclk_i958_div.hw
1201 },
1100 .num_parents = 1, 1202 .num_parents = 1,
1101 .flags = CLK_SET_RATE_PARENT, 1203 .flags = CLK_SET_RATE_PARENT,
1102 }, 1204 },
@@ -1111,7 +1213,10 @@ static struct clk_regmap gxbb_cts_i958 = {
1111 .hw.init = &(struct clk_init_data){ 1213 .hw.init = &(struct clk_init_data){
1112 .name = "cts_i958", 1214 .name = "cts_i958",
1113 .ops = &clk_regmap_mux_ops, 1215 .ops = &clk_regmap_mux_ops,
1114 .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" }, 1216 .parent_hws = (const struct clk_hw *[]) {
1217 &gxbb_cts_amclk.hw,
1218 &gxbb_cts_mclk_i958.hw
1219 },
1115 .num_parents = 2, 1220 .num_parents = 2,
1116 /* 1221 /*
1117 *The parent is specific to origin of the audio data. Let the 1222 *The parent is specific to origin of the audio data. Let the
@@ -1121,6 +1226,33 @@ static struct clk_regmap gxbb_cts_i958 = {
1121 }, 1226 },
1122}; 1227};
1123 1228
1229static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {
1230 { .fw_name = "xtal", },
1231 /*
1232 * FIXME: This clock is provided by the ao clock controller but the
1233 * clock is not yet part of the binding of this controller, so string
1234 * name must be use to set this parent.
1235 */
1236 { .name = "cts_slow_oscin", .index = -1 },
1237 { .hw = &gxbb_fclk_div3.hw },
1238 { .hw = &gxbb_fclk_div5.hw },
1239};
1240
1241static struct clk_regmap gxbb_32k_clk_sel = {
1242 .data = &(struct clk_regmap_mux_data){
1243 .offset = HHI_32K_CLK_CNTL,
1244 .mask = 0x3,
1245 .shift = 16,
1246 },
1247 .hw.init = &(struct clk_init_data){
1248 .name = "32k_clk_sel",
1249 .ops = &clk_regmap_mux_ops,
1250 .parent_data = gxbb_32k_clk_parent_data,
1251 .num_parents = 4,
1252 .flags = CLK_SET_RATE_PARENT,
1253 },
1254};
1255
1124static struct clk_regmap gxbb_32k_clk_div = { 1256static struct clk_regmap gxbb_32k_clk_div = {
1125 .data = &(struct clk_regmap_div_data){ 1257 .data = &(struct clk_regmap_div_data){
1126 .offset = HHI_32K_CLK_CNTL, 1258 .offset = HHI_32K_CLK_CNTL,
@@ -1130,7 +1262,9 @@ static struct clk_regmap gxbb_32k_clk_div = {
1130 .hw.init = &(struct clk_init_data){ 1262 .hw.init = &(struct clk_init_data){
1131 .name = "32k_clk_div", 1263 .name = "32k_clk_div",
1132 .ops = &clk_regmap_divider_ops, 1264 .ops = &clk_regmap_divider_ops,
1133 .parent_names = (const char *[]){ "32k_clk_sel" }, 1265 .parent_hws = (const struct clk_hw *[]) {
1266 &gxbb_32k_clk_sel.hw
1267 },
1134 .num_parents = 1, 1268 .num_parents = 1,
1135 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST, 1269 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
1136 }, 1270 },
@@ -1144,34 +1278,20 @@ static struct clk_regmap gxbb_32k_clk = {
1144 .hw.init = &(struct clk_init_data){ 1278 .hw.init = &(struct clk_init_data){
1145 .name = "32k_clk", 1279 .name = "32k_clk",
1146 .ops = &clk_regmap_gate_ops, 1280 .ops = &clk_regmap_gate_ops,
1147 .parent_names = (const char *[]){ "32k_clk_div" }, 1281 .parent_hws = (const struct clk_hw *[]) {
1148 .num_parents = 1, 1282 &gxbb_32k_clk_div.hw
1149 .flags = CLK_SET_RATE_PARENT,
1150 },
1151};
1152
1153static const char * const gxbb_32k_clk_parent_names[] = {
1154 IN_PREFIX "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
1155};
1156
1157static struct clk_regmap gxbb_32k_clk_sel = {
1158 .data = &(struct clk_regmap_mux_data){
1159 .offset = HHI_32K_CLK_CNTL,
1160 .mask = 0x3,
1161 .shift = 16,
1162 }, 1283 },
1163 .hw.init = &(struct clk_init_data){ 1284 .num_parents = 1,
1164 .name = "32k_clk_sel",
1165 .ops = &clk_regmap_mux_ops,
1166 .parent_names = gxbb_32k_clk_parent_names,
1167 .num_parents = 4,
1168 .flags = CLK_SET_RATE_PARENT, 1285 .flags = CLK_SET_RATE_PARENT,
1169 }, 1286 },
1170}; 1287};
1171 1288
1172static const char * const gxbb_sd_emmc_clk0_parent_names[] = { 1289static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = {
1173 IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7", 1290 { .fw_name = "xtal", },
1174 1291 { .hw = &gxbb_fclk_div2.hw },
1292 { .hw = &gxbb_fclk_div3.hw },
1293 { .hw = &gxbb_fclk_div5.hw },
1294 { .hw = &gxbb_fclk_div7.hw },
1175 /* 1295 /*
1176 * Following these parent clocks, we should also have had mpll2, mpll3 1296 * Following these parent clocks, we should also have had mpll2, mpll3
1177 * and gp0_pll but these clocks are too precious to be used here. All 1297 * and gp0_pll but these clocks are too precious to be used here. All
@@ -1190,8 +1310,8 @@ static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
1190 .hw.init = &(struct clk_init_data) { 1310 .hw.init = &(struct clk_init_data) {
1191 .name = "sd_emmc_a_clk0_sel", 1311 .name = "sd_emmc_a_clk0_sel",
1192 .ops = &clk_regmap_mux_ops, 1312 .ops = &clk_regmap_mux_ops,
1193 .parent_names = gxbb_sd_emmc_clk0_parent_names, 1313 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1194 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1314 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1195 .flags = CLK_SET_RATE_PARENT, 1315 .flags = CLK_SET_RATE_PARENT,
1196 }, 1316 },
1197}; 1317};
@@ -1206,7 +1326,9 @@ static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
1206 .hw.init = &(struct clk_init_data) { 1326 .hw.init = &(struct clk_init_data) {
1207 .name = "sd_emmc_a_clk0_div", 1327 .name = "sd_emmc_a_clk0_div",
1208 .ops = &clk_regmap_divider_ops, 1328 .ops = &clk_regmap_divider_ops,
1209 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" }, 1329 .parent_hws = (const struct clk_hw *[]) {
1330 &gxbb_sd_emmc_a_clk0_sel.hw
1331 },
1210 .num_parents = 1, 1332 .num_parents = 1,
1211 .flags = CLK_SET_RATE_PARENT, 1333 .flags = CLK_SET_RATE_PARENT,
1212 }, 1334 },
@@ -1220,7 +1342,9 @@ static struct clk_regmap gxbb_sd_emmc_a_clk0 = {
1220 .hw.init = &(struct clk_init_data){ 1342 .hw.init = &(struct clk_init_data){
1221 .name = "sd_emmc_a_clk0", 1343 .name = "sd_emmc_a_clk0",
1222 .ops = &clk_regmap_gate_ops, 1344 .ops = &clk_regmap_gate_ops,
1223 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" }, 1345 .parent_hws = (const struct clk_hw *[]) {
1346 &gxbb_sd_emmc_a_clk0_div.hw
1347 },
1224 .num_parents = 1, 1348 .num_parents = 1,
1225 .flags = CLK_SET_RATE_PARENT, 1349 .flags = CLK_SET_RATE_PARENT,
1226 }, 1350 },
@@ -1236,8 +1360,8 @@ static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
1236 .hw.init = &(struct clk_init_data) { 1360 .hw.init = &(struct clk_init_data) {
1237 .name = "sd_emmc_b_clk0_sel", 1361 .name = "sd_emmc_b_clk0_sel",
1238 .ops = &clk_regmap_mux_ops, 1362 .ops = &clk_regmap_mux_ops,
1239 .parent_names = gxbb_sd_emmc_clk0_parent_names, 1363 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1240 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1364 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1241 .flags = CLK_SET_RATE_PARENT, 1365 .flags = CLK_SET_RATE_PARENT,
1242 }, 1366 },
1243}; 1367};
@@ -1252,7 +1376,9 @@ static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
1252 .hw.init = &(struct clk_init_data) { 1376 .hw.init = &(struct clk_init_data) {
1253 .name = "sd_emmc_b_clk0_div", 1377 .name = "sd_emmc_b_clk0_div",
1254 .ops = &clk_regmap_divider_ops, 1378 .ops = &clk_regmap_divider_ops,
1255 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" }, 1379 .parent_hws = (const struct clk_hw *[]) {
1380 &gxbb_sd_emmc_b_clk0_sel.hw
1381 },
1256 .num_parents = 1, 1382 .num_parents = 1,
1257 .flags = CLK_SET_RATE_PARENT, 1383 .flags = CLK_SET_RATE_PARENT,
1258 }, 1384 },
@@ -1266,7 +1392,9 @@ static struct clk_regmap gxbb_sd_emmc_b_clk0 = {
1266 .hw.init = &(struct clk_init_data){ 1392 .hw.init = &(struct clk_init_data){
1267 .name = "sd_emmc_b_clk0", 1393 .name = "sd_emmc_b_clk0",
1268 .ops = &clk_regmap_gate_ops, 1394 .ops = &clk_regmap_gate_ops,
1269 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" }, 1395 .parent_hws = (const struct clk_hw *[]) {
1396 &gxbb_sd_emmc_b_clk0_div.hw
1397 },
1270 .num_parents = 1, 1398 .num_parents = 1,
1271 .flags = CLK_SET_RATE_PARENT, 1399 .flags = CLK_SET_RATE_PARENT,
1272 }, 1400 },
@@ -1282,8 +1410,8 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
1282 .hw.init = &(struct clk_init_data) { 1410 .hw.init = &(struct clk_init_data) {
1283 .name = "sd_emmc_c_clk0_sel", 1411 .name = "sd_emmc_c_clk0_sel",
1284 .ops = &clk_regmap_mux_ops, 1412 .ops = &clk_regmap_mux_ops,
1285 .parent_names = gxbb_sd_emmc_clk0_parent_names, 1413 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1286 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names), 1414 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1287 .flags = CLK_SET_RATE_PARENT, 1415 .flags = CLK_SET_RATE_PARENT,
1288 }, 1416 },
1289}; 1417};
@@ -1298,7 +1426,9 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
1298 .hw.init = &(struct clk_init_data) { 1426 .hw.init = &(struct clk_init_data) {
1299 .name = "sd_emmc_c_clk0_div", 1427 .name = "sd_emmc_c_clk0_div",
1300 .ops = &clk_regmap_divider_ops, 1428 .ops = &clk_regmap_divider_ops,
1301 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" }, 1429 .parent_hws = (const struct clk_hw *[]) {
1430 &gxbb_sd_emmc_c_clk0_sel.hw
1431 },
1302 .num_parents = 1, 1432 .num_parents = 1,
1303 .flags = CLK_SET_RATE_PARENT, 1433 .flags = CLK_SET_RATE_PARENT,
1304 }, 1434 },
@@ -1312,7 +1442,9 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
1312 .hw.init = &(struct clk_init_data){ 1442 .hw.init = &(struct clk_init_data){
1313 .name = "sd_emmc_c_clk0", 1443 .name = "sd_emmc_c_clk0",
1314 .ops = &clk_regmap_gate_ops, 1444 .ops = &clk_regmap_gate_ops,
1315 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" }, 1445 .parent_hws = (const struct clk_hw *[]) {
1446 &gxbb_sd_emmc_c_clk0_div.hw
1447 },
1316 .num_parents = 1, 1448 .num_parents = 1,
1317 .flags = CLK_SET_RATE_PARENT, 1449 .flags = CLK_SET_RATE_PARENT,
1318 }, 1450 },
@@ -1320,8 +1452,11 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
1320 1452
1321/* VPU Clock */ 1453/* VPU Clock */
1322 1454
1323static const char * const gxbb_vpu_parent_names[] = { 1455static const struct clk_hw *gxbb_vpu_parent_hws[] = {
1324 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" 1456 &gxbb_fclk_div4.hw,
1457 &gxbb_fclk_div3.hw,
1458 &gxbb_fclk_div5.hw,
1459 &gxbb_fclk_div7.hw,
1325}; 1460};
1326 1461
1327static struct clk_regmap gxbb_vpu_0_sel = { 1462static struct clk_regmap gxbb_vpu_0_sel = {
@@ -1337,8 +1472,8 @@ static struct clk_regmap gxbb_vpu_0_sel = {
1337 * bits 9:10 selects from 4 possible parents: 1472 * bits 9:10 selects from 4 possible parents:
1338 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1473 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1339 */ 1474 */
1340 .parent_names = gxbb_vpu_parent_names, 1475 .parent_hws = gxbb_vpu_parent_hws,
1341 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names), 1476 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1342 .flags = CLK_SET_RATE_NO_REPARENT, 1477 .flags = CLK_SET_RATE_NO_REPARENT,
1343 }, 1478 },
1344}; 1479};
@@ -1352,7 +1487,7 @@ static struct clk_regmap gxbb_vpu_0_div = {
1352 .hw.init = &(struct clk_init_data){ 1487 .hw.init = &(struct clk_init_data){
1353 .name = "vpu_0_div", 1488 .name = "vpu_0_div",
1354 .ops = &clk_regmap_divider_ops, 1489 .ops = &clk_regmap_divider_ops,
1355 .parent_names = (const char *[]){ "vpu_0_sel" }, 1490 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw },
1356 .num_parents = 1, 1491 .num_parents = 1,
1357 .flags = CLK_SET_RATE_PARENT, 1492 .flags = CLK_SET_RATE_PARENT,
1358 }, 1493 },
@@ -1366,7 +1501,7 @@ static struct clk_regmap gxbb_vpu_0 = {
1366 .hw.init = &(struct clk_init_data) { 1501 .hw.init = &(struct clk_init_data) {
1367 .name = "vpu_0", 1502 .name = "vpu_0",
1368 .ops = &clk_regmap_gate_ops, 1503 .ops = &clk_regmap_gate_ops,
1369 .parent_names = (const char *[]){ "vpu_0_div" }, 1504 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw },
1370 .num_parents = 1, 1505 .num_parents = 1,
1371 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1506 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1372 }, 1507 },
@@ -1385,8 +1520,8 @@ static struct clk_regmap gxbb_vpu_1_sel = {
1385 * bits 25:26 selects from 4 possible parents: 1520 * bits 25:26 selects from 4 possible parents:
1386 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1521 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1387 */ 1522 */
1388 .parent_names = gxbb_vpu_parent_names, 1523 .parent_hws = gxbb_vpu_parent_hws,
1389 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names), 1524 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1390 .flags = CLK_SET_RATE_NO_REPARENT, 1525 .flags = CLK_SET_RATE_NO_REPARENT,
1391 }, 1526 },
1392}; 1527};
@@ -1400,7 +1535,7 @@ static struct clk_regmap gxbb_vpu_1_div = {
1400 .hw.init = &(struct clk_init_data){ 1535 .hw.init = &(struct clk_init_data){
1401 .name = "vpu_1_div", 1536 .name = "vpu_1_div",
1402 .ops = &clk_regmap_divider_ops, 1537 .ops = &clk_regmap_divider_ops,
1403 .parent_names = (const char *[]){ "vpu_1_sel" }, 1538 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw },
1404 .num_parents = 1, 1539 .num_parents = 1,
1405 .flags = CLK_SET_RATE_PARENT, 1540 .flags = CLK_SET_RATE_PARENT,
1406 }, 1541 },
@@ -1414,7 +1549,7 @@ static struct clk_regmap gxbb_vpu_1 = {
1414 .hw.init = &(struct clk_init_data) { 1549 .hw.init = &(struct clk_init_data) {
1415 .name = "vpu_1", 1550 .name = "vpu_1",
1416 .ops = &clk_regmap_gate_ops, 1551 .ops = &clk_regmap_gate_ops,
1417 .parent_names = (const char *[]){ "vpu_1_div" }, 1552 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw },
1418 .num_parents = 1, 1553 .num_parents = 1,
1419 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1554 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1420 }, 1555 },
@@ -1433,7 +1568,10 @@ static struct clk_regmap gxbb_vpu = {
1433 * bit 31 selects from 2 possible parents: 1568 * bit 31 selects from 2 possible parents:
1434 * vpu_0 or vpu_1 1569 * vpu_0 or vpu_1
1435 */ 1570 */
1436 .parent_names = (const char *[]){ "vpu_0", "vpu_1" }, 1571 .parent_hws = (const struct clk_hw *[]) {
1572 &gxbb_vpu_0.hw,
1573 &gxbb_vpu_1.hw
1574 },
1437 .num_parents = 2, 1575 .num_parents = 2,
1438 .flags = CLK_SET_RATE_NO_REPARENT, 1576 .flags = CLK_SET_RATE_NO_REPARENT,
1439 }, 1577 },
@@ -1441,8 +1579,11 @@ static struct clk_regmap gxbb_vpu = {
1441 1579
1442/* VAPB Clock */ 1580/* VAPB Clock */
1443 1581
1444static const char * const gxbb_vapb_parent_names[] = { 1582static const struct clk_hw *gxbb_vapb_parent_hws[] = {
1445 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" 1583 &gxbb_fclk_div4.hw,
1584 &gxbb_fclk_div3.hw,
1585 &gxbb_fclk_div5.hw,
1586 &gxbb_fclk_div7.hw,
1446}; 1587};
1447 1588
1448static struct clk_regmap gxbb_vapb_0_sel = { 1589static struct clk_regmap gxbb_vapb_0_sel = {
@@ -1458,8 +1599,8 @@ static struct clk_regmap gxbb_vapb_0_sel = {
1458 * bits 9:10 selects from 4 possible parents: 1599 * bits 9:10 selects from 4 possible parents:
1459 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1600 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1460 */ 1601 */
1461 .parent_names = gxbb_vapb_parent_names, 1602 .parent_hws = gxbb_vapb_parent_hws,
1462 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names), 1603 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1463 .flags = CLK_SET_RATE_NO_REPARENT, 1604 .flags = CLK_SET_RATE_NO_REPARENT,
1464 }, 1605 },
1465}; 1606};
@@ -1473,7 +1614,9 @@ static struct clk_regmap gxbb_vapb_0_div = {
1473 .hw.init = &(struct clk_init_data){ 1614 .hw.init = &(struct clk_init_data){
1474 .name = "vapb_0_div", 1615 .name = "vapb_0_div",
1475 .ops = &clk_regmap_divider_ops, 1616 .ops = &clk_regmap_divider_ops,
1476 .parent_names = (const char *[]){ "vapb_0_sel" }, 1617 .parent_hws = (const struct clk_hw *[]) {
1618 &gxbb_vapb_0_sel.hw
1619 },
1477 .num_parents = 1, 1620 .num_parents = 1,
1478 .flags = CLK_SET_RATE_PARENT, 1621 .flags = CLK_SET_RATE_PARENT,
1479 }, 1622 },
@@ -1487,7 +1630,9 @@ static struct clk_regmap gxbb_vapb_0 = {
1487 .hw.init = &(struct clk_init_data) { 1630 .hw.init = &(struct clk_init_data) {
1488 .name = "vapb_0", 1631 .name = "vapb_0",
1489 .ops = &clk_regmap_gate_ops, 1632 .ops = &clk_regmap_gate_ops,
1490 .parent_names = (const char *[]){ "vapb_0_div" }, 1633 .parent_hws = (const struct clk_hw *[]) {
1634 &gxbb_vapb_0_div.hw
1635 },
1491 .num_parents = 1, 1636 .num_parents = 1,
1492 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1637 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1493 }, 1638 },
@@ -1506,8 +1651,8 @@ static struct clk_regmap gxbb_vapb_1_sel = {
1506 * bits 25:26 selects from 4 possible parents: 1651 * bits 25:26 selects from 4 possible parents:
1507 * fclk_div4, fclk_div3, fclk_div5, fclk_div7, 1652 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1508 */ 1653 */
1509 .parent_names = gxbb_vapb_parent_names, 1654 .parent_hws = gxbb_vapb_parent_hws,
1510 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names), 1655 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1511 .flags = CLK_SET_RATE_NO_REPARENT, 1656 .flags = CLK_SET_RATE_NO_REPARENT,
1512 }, 1657 },
1513}; 1658};
@@ -1521,7 +1666,9 @@ static struct clk_regmap gxbb_vapb_1_div = {
1521 .hw.init = &(struct clk_init_data){ 1666 .hw.init = &(struct clk_init_data){
1522 .name = "vapb_1_div", 1667 .name = "vapb_1_div",
1523 .ops = &clk_regmap_divider_ops, 1668 .ops = &clk_regmap_divider_ops,
1524 .parent_names = (const char *[]){ "vapb_1_sel" }, 1669 .parent_hws = (const struct clk_hw *[]) {
1670 &gxbb_vapb_1_sel.hw
1671 },
1525 .num_parents = 1, 1672 .num_parents = 1,
1526 .flags = CLK_SET_RATE_PARENT, 1673 .flags = CLK_SET_RATE_PARENT,
1527 }, 1674 },
@@ -1535,7 +1682,9 @@ static struct clk_regmap gxbb_vapb_1 = {
1535 .hw.init = &(struct clk_init_data) { 1682 .hw.init = &(struct clk_init_data) {
1536 .name = "vapb_1", 1683 .name = "vapb_1",
1537 .ops = &clk_regmap_gate_ops, 1684 .ops = &clk_regmap_gate_ops,
1538 .parent_names = (const char *[]){ "vapb_1_div" }, 1685 .parent_hws = (const struct clk_hw *[]) {
1686 &gxbb_vapb_1_div.hw
1687 },
1539 .num_parents = 1, 1688 .num_parents = 1,
1540 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1689 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1541 }, 1690 },
@@ -1554,7 +1703,10 @@ static struct clk_regmap gxbb_vapb_sel = {
1554 * bit 31 selects from 2 possible parents: 1703 * bit 31 selects from 2 possible parents:
1555 * vapb_0 or vapb_1 1704 * vapb_0 or vapb_1
1556 */ 1705 */
1557 .parent_names = (const char *[]){ "vapb_0", "vapb_1" }, 1706 .parent_hws = (const struct clk_hw *[]) {
1707 &gxbb_vapb_0.hw,
1708 &gxbb_vapb_1.hw
1709 },
1558 .num_parents = 2, 1710 .num_parents = 2,
1559 .flags = CLK_SET_RATE_NO_REPARENT, 1711 .flags = CLK_SET_RATE_NO_REPARENT,
1560 }, 1712 },
@@ -1568,7 +1720,7 @@ static struct clk_regmap gxbb_vapb = {
1568 .hw.init = &(struct clk_init_data) { 1720 .hw.init = &(struct clk_init_data) {
1569 .name = "vapb", 1721 .name = "vapb",
1570 .ops = &clk_regmap_gate_ops, 1722 .ops = &clk_regmap_gate_ops,
1571 .parent_names = (const char *[]){ "vapb_sel" }, 1723 .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw },
1572 .num_parents = 1, 1724 .num_parents = 1,
1573 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1725 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1574 }, 1726 },
@@ -1592,13 +1744,33 @@ static struct clk_regmap gxbb_vid_pll_div = {
1592 .hw.init = &(struct clk_init_data) { 1744 .hw.init = &(struct clk_init_data) {
1593 .name = "vid_pll_div", 1745 .name = "vid_pll_div",
1594 .ops = &meson_vid_pll_div_ro_ops, 1746 .ops = &meson_vid_pll_div_ro_ops,
1595 .parent_names = (const char *[]){ "hdmi_pll" }, 1747 .parent_data = &(const struct clk_parent_data) {
1748 /*
1749 * Note:
1750 * GXL and GXBB have different hdmi_plls (with
1751 * different struct clk_hw). We fallback to the global
1752 * naming string mechanism so vid_pll_div picks up the
1753 * appropriate one.
1754 */
1755 .name = "hdmi_pll",
1756 .index = -1,
1757 },
1596 .num_parents = 1, 1758 .num_parents = 1,
1597 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, 1759 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
1598 }, 1760 },
1599}; 1761};
1600 1762
1601static const char * const gxbb_vid_pll_parent_names[] = { "vid_pll_div", "hdmi_pll" }; 1763static const struct clk_parent_data gxbb_vid_pll_parent_data[] = {
1764 { .hw = &gxbb_vid_pll_div.hw },
1765 /*
1766 * Note:
1767 * GXL and GXBB have different hdmi_plls (with
1768 * different struct clk_hw). We fallback to the global
1769 * naming string mechanism so vid_pll_div picks up the
1770 * appropriate one.
1771 */
1772 { .name = "hdmi_pll", .index = -1 },
1773};
1602 1774
1603static struct clk_regmap gxbb_vid_pll_sel = { 1775static struct clk_regmap gxbb_vid_pll_sel = {
1604 .data = &(struct clk_regmap_mux_data){ 1776 .data = &(struct clk_regmap_mux_data){
@@ -1613,8 +1785,8 @@ static struct clk_regmap gxbb_vid_pll_sel = {
1613 * bit 18 selects from 2 possible parents: 1785 * bit 18 selects from 2 possible parents:
1614 * vid_pll_div or hdmi_pll 1786 * vid_pll_div or hdmi_pll
1615 */ 1787 */
1616 .parent_names = gxbb_vid_pll_parent_names, 1788 .parent_data = gxbb_vid_pll_parent_data,
1617 .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_names), 1789 .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data),
1618 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1790 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1619 }, 1791 },
1620}; 1792};
@@ -1627,15 +1799,22 @@ static struct clk_regmap gxbb_vid_pll = {
1627 .hw.init = &(struct clk_init_data) { 1799 .hw.init = &(struct clk_init_data) {
1628 .name = "vid_pll", 1800 .name = "vid_pll",
1629 .ops = &clk_regmap_gate_ops, 1801 .ops = &clk_regmap_gate_ops,
1630 .parent_names = (const char *[]){ "vid_pll_sel" }, 1802 .parent_hws = (const struct clk_hw *[]) {
1803 &gxbb_vid_pll_sel.hw
1804 },
1631 .num_parents = 1, 1805 .num_parents = 1,
1632 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1806 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1633 }, 1807 },
1634}; 1808};
1635 1809
1636static const char * const gxbb_vclk_parent_names[] = { 1810static const struct clk_hw *gxbb_vclk_parent_hws[] = {
1637 "vid_pll", "fclk_div4", "fclk_div3", "fclk_div5", "vid_pll", 1811 &gxbb_vid_pll.hw,
1638 "fclk_div7", "mpll1", 1812 &gxbb_fclk_div4.hw,
1813 &gxbb_fclk_div3.hw,
1814 &gxbb_fclk_div5.hw,
1815 &gxbb_vid_pll.hw,
1816 &gxbb_fclk_div7.hw,
1817 &gxbb_mpll1.hw,
1639}; 1818};
1640 1819
1641static struct clk_regmap gxbb_vclk_sel = { 1820static struct clk_regmap gxbb_vclk_sel = {
@@ -1652,8 +1831,8 @@ static struct clk_regmap gxbb_vclk_sel = {
1652 * vid_pll, fclk_div4, fclk_div3, fclk_div5, 1831 * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1653 * vid_pll, fclk_div7, mp1 1832 * vid_pll, fclk_div7, mp1
1654 */ 1833 */
1655 .parent_names = gxbb_vclk_parent_names, 1834 .parent_hws = gxbb_vclk_parent_hws,
1656 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_names), 1835 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1657 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1836 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1658 }, 1837 },
1659}; 1838};
@@ -1672,8 +1851,8 @@ static struct clk_regmap gxbb_vclk2_sel = {
1672 * vid_pll, fclk_div4, fclk_div3, fclk_div5, 1851 * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1673 * vid_pll, fclk_div7, mp1 1852 * vid_pll, fclk_div7, mp1
1674 */ 1853 */
1675 .parent_names = gxbb_vclk_parent_names, 1854 .parent_hws = gxbb_vclk_parent_hws,
1676 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_names), 1855 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1677 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 1856 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1678 }, 1857 },
1679}; 1858};
@@ -1686,7 +1865,7 @@ static struct clk_regmap gxbb_vclk_input = {
1686 .hw.init = &(struct clk_init_data) { 1865 .hw.init = &(struct clk_init_data) {
1687 .name = "vclk_input", 1866 .name = "vclk_input",
1688 .ops = &clk_regmap_gate_ops, 1867 .ops = &clk_regmap_gate_ops,
1689 .parent_names = (const char *[]){ "vclk_sel" }, 1868 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw },
1690 .num_parents = 1, 1869 .num_parents = 1,
1691 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1870 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1692 }, 1871 },
@@ -1700,7 +1879,7 @@ static struct clk_regmap gxbb_vclk2_input = {
1700 .hw.init = &(struct clk_init_data) { 1879 .hw.init = &(struct clk_init_data) {
1701 .name = "vclk2_input", 1880 .name = "vclk2_input",
1702 .ops = &clk_regmap_gate_ops, 1881 .ops = &clk_regmap_gate_ops,
1703 .parent_names = (const char *[]){ "vclk2_sel" }, 1882 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw },
1704 .num_parents = 1, 1883 .num_parents = 1,
1705 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1884 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1706 }, 1885 },
@@ -1715,7 +1894,9 @@ static struct clk_regmap gxbb_vclk_div = {
1715 .hw.init = &(struct clk_init_data){ 1894 .hw.init = &(struct clk_init_data){
1716 .name = "vclk_div", 1895 .name = "vclk_div",
1717 .ops = &clk_regmap_divider_ops, 1896 .ops = &clk_regmap_divider_ops,
1718 .parent_names = (const char *[]){ "vclk_input" }, 1897 .parent_hws = (const struct clk_hw *[]) {
1898 &gxbb_vclk_input.hw
1899 },
1719 .num_parents = 1, 1900 .num_parents = 1,
1720 .flags = CLK_GET_RATE_NOCACHE, 1901 .flags = CLK_GET_RATE_NOCACHE,
1721 }, 1902 },
@@ -1730,7 +1911,9 @@ static struct clk_regmap gxbb_vclk2_div = {
1730 .hw.init = &(struct clk_init_data){ 1911 .hw.init = &(struct clk_init_data){
1731 .name = "vclk2_div", 1912 .name = "vclk2_div",
1732 .ops = &clk_regmap_divider_ops, 1913 .ops = &clk_regmap_divider_ops,
1733 .parent_names = (const char *[]){ "vclk2_input" }, 1914 .parent_hws = (const struct clk_hw *[]) {
1915 &gxbb_vclk2_input.hw
1916 },
1734 .num_parents = 1, 1917 .num_parents = 1,
1735 .flags = CLK_GET_RATE_NOCACHE, 1918 .flags = CLK_GET_RATE_NOCACHE,
1736 }, 1919 },
@@ -1744,7 +1927,7 @@ static struct clk_regmap gxbb_vclk = {
1744 .hw.init = &(struct clk_init_data) { 1927 .hw.init = &(struct clk_init_data) {
1745 .name = "vclk", 1928 .name = "vclk",
1746 .ops = &clk_regmap_gate_ops, 1929 .ops = &clk_regmap_gate_ops,
1747 .parent_names = (const char *[]){ "vclk_div" }, 1930 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw },
1748 .num_parents = 1, 1931 .num_parents = 1,
1749 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1932 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1750 }, 1933 },
@@ -1758,7 +1941,7 @@ static struct clk_regmap gxbb_vclk2 = {
1758 .hw.init = &(struct clk_init_data) { 1941 .hw.init = &(struct clk_init_data) {
1759 .name = "vclk2", 1942 .name = "vclk2",
1760 .ops = &clk_regmap_gate_ops, 1943 .ops = &clk_regmap_gate_ops,
1761 .parent_names = (const char *[]){ "vclk2_div" }, 1944 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw },
1762 .num_parents = 1, 1945 .num_parents = 1,
1763 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1946 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1764 }, 1947 },
@@ -1772,7 +1955,7 @@ static struct clk_regmap gxbb_vclk_div1 = {
1772 .hw.init = &(struct clk_init_data) { 1955 .hw.init = &(struct clk_init_data) {
1773 .name = "vclk_div1", 1956 .name = "vclk_div1",
1774 .ops = &clk_regmap_gate_ops, 1957 .ops = &clk_regmap_gate_ops,
1775 .parent_names = (const char *[]){ "vclk" }, 1958 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1776 .num_parents = 1, 1959 .num_parents = 1,
1777 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1960 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1778 }, 1961 },
@@ -1786,7 +1969,7 @@ static struct clk_regmap gxbb_vclk_div2_en = {
1786 .hw.init = &(struct clk_init_data) { 1969 .hw.init = &(struct clk_init_data) {
1787 .name = "vclk_div2_en", 1970 .name = "vclk_div2_en",
1788 .ops = &clk_regmap_gate_ops, 1971 .ops = &clk_regmap_gate_ops,
1789 .parent_names = (const char *[]){ "vclk" }, 1972 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1790 .num_parents = 1, 1973 .num_parents = 1,
1791 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1974 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1792 }, 1975 },
@@ -1800,7 +1983,7 @@ static struct clk_regmap gxbb_vclk_div4_en = {
1800 .hw.init = &(struct clk_init_data) { 1983 .hw.init = &(struct clk_init_data) {
1801 .name = "vclk_div4_en", 1984 .name = "vclk_div4_en",
1802 .ops = &clk_regmap_gate_ops, 1985 .ops = &clk_regmap_gate_ops,
1803 .parent_names = (const char *[]){ "vclk" }, 1986 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1804 .num_parents = 1, 1987 .num_parents = 1,
1805 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 1988 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1806 }, 1989 },
@@ -1814,7 +1997,7 @@ static struct clk_regmap gxbb_vclk_div6_en = {
1814 .hw.init = &(struct clk_init_data) { 1997 .hw.init = &(struct clk_init_data) {
1815 .name = "vclk_div6_en", 1998 .name = "vclk_div6_en",
1816 .ops = &clk_regmap_gate_ops, 1999 .ops = &clk_regmap_gate_ops,
1817 .parent_names = (const char *[]){ "vclk" }, 2000 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1818 .num_parents = 1, 2001 .num_parents = 1,
1819 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2002 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1820 }, 2003 },
@@ -1828,7 +2011,7 @@ static struct clk_regmap gxbb_vclk_div12_en = {
1828 .hw.init = &(struct clk_init_data) { 2011 .hw.init = &(struct clk_init_data) {
1829 .name = "vclk_div12_en", 2012 .name = "vclk_div12_en",
1830 .ops = &clk_regmap_gate_ops, 2013 .ops = &clk_regmap_gate_ops,
1831 .parent_names = (const char *[]){ "vclk" }, 2014 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1832 .num_parents = 1, 2015 .num_parents = 1,
1833 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2016 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1834 }, 2017 },
@@ -1842,7 +2025,7 @@ static struct clk_regmap gxbb_vclk2_div1 = {
1842 .hw.init = &(struct clk_init_data) { 2025 .hw.init = &(struct clk_init_data) {
1843 .name = "vclk2_div1", 2026 .name = "vclk2_div1",
1844 .ops = &clk_regmap_gate_ops, 2027 .ops = &clk_regmap_gate_ops,
1845 .parent_names = (const char *[]){ "vclk2" }, 2028 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
1846 .num_parents = 1, 2029 .num_parents = 1,
1847 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2030 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1848 }, 2031 },
@@ -1856,7 +2039,7 @@ static struct clk_regmap gxbb_vclk2_div2_en = {
1856 .hw.init = &(struct clk_init_data) { 2039 .hw.init = &(struct clk_init_data) {
1857 .name = "vclk2_div2_en", 2040 .name = "vclk2_div2_en",
1858 .ops = &clk_regmap_gate_ops, 2041 .ops = &clk_regmap_gate_ops,
1859 .parent_names = (const char *[]){ "vclk2" }, 2042 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
1860 .num_parents = 1, 2043 .num_parents = 1,
1861 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2044 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1862 }, 2045 },
@@ -1870,7 +2053,7 @@ static struct clk_regmap gxbb_vclk2_div4_en = {
1870 .hw.init = &(struct clk_init_data) { 2053 .hw.init = &(struct clk_init_data) {
1871 .name = "vclk2_div4_en", 2054 .name = "vclk2_div4_en",
1872 .ops = &clk_regmap_gate_ops, 2055 .ops = &clk_regmap_gate_ops,
1873 .parent_names = (const char *[]){ "vclk2" }, 2056 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
1874 .num_parents = 1, 2057 .num_parents = 1,
1875 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2058 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1876 }, 2059 },
@@ -1884,7 +2067,7 @@ static struct clk_regmap gxbb_vclk2_div6_en = {
1884 .hw.init = &(struct clk_init_data) { 2067 .hw.init = &(struct clk_init_data) {
1885 .name = "vclk2_div6_en", 2068 .name = "vclk2_div6_en",
1886 .ops = &clk_regmap_gate_ops, 2069 .ops = &clk_regmap_gate_ops,
1887 .parent_names = (const char *[]){ "vclk2" }, 2070 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
1888 .num_parents = 1, 2071 .num_parents = 1,
1889 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2072 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1890 }, 2073 },
@@ -1898,7 +2081,7 @@ static struct clk_regmap gxbb_vclk2_div12_en = {
1898 .hw.init = &(struct clk_init_data) { 2081 .hw.init = &(struct clk_init_data) {
1899 .name = "vclk2_div12_en", 2082 .name = "vclk2_div12_en",
1900 .ops = &clk_regmap_gate_ops, 2083 .ops = &clk_regmap_gate_ops,
1901 .parent_names = (const char *[]){ "vclk2" }, 2084 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
1902 .num_parents = 1, 2085 .num_parents = 1,
1903 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2086 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1904 }, 2087 },
@@ -1910,7 +2093,9 @@ static struct clk_fixed_factor gxbb_vclk_div2 = {
1910 .hw.init = &(struct clk_init_data){ 2093 .hw.init = &(struct clk_init_data){
1911 .name = "vclk_div2", 2094 .name = "vclk_div2",
1912 .ops = &clk_fixed_factor_ops, 2095 .ops = &clk_fixed_factor_ops,
1913 .parent_names = (const char *[]){ "vclk_div2_en" }, 2096 .parent_hws = (const struct clk_hw *[]) {
2097 &gxbb_vclk_div2_en.hw
2098 },
1914 .num_parents = 1, 2099 .num_parents = 1,
1915 }, 2100 },
1916}; 2101};
@@ -1921,7 +2106,9 @@ static struct clk_fixed_factor gxbb_vclk_div4 = {
1921 .hw.init = &(struct clk_init_data){ 2106 .hw.init = &(struct clk_init_data){
1922 .name = "vclk_div4", 2107 .name = "vclk_div4",
1923 .ops = &clk_fixed_factor_ops, 2108 .ops = &clk_fixed_factor_ops,
1924 .parent_names = (const char *[]){ "vclk_div4_en" }, 2109 .parent_hws = (const struct clk_hw *[]) {
2110 &gxbb_vclk_div4_en.hw
2111 },
1925 .num_parents = 1, 2112 .num_parents = 1,
1926 }, 2113 },
1927}; 2114};
@@ -1932,7 +2119,9 @@ static struct clk_fixed_factor gxbb_vclk_div6 = {
1932 .hw.init = &(struct clk_init_data){ 2119 .hw.init = &(struct clk_init_data){
1933 .name = "vclk_div6", 2120 .name = "vclk_div6",
1934 .ops = &clk_fixed_factor_ops, 2121 .ops = &clk_fixed_factor_ops,
1935 .parent_names = (const char *[]){ "vclk_div6_en" }, 2122 .parent_hws = (const struct clk_hw *[]) {
2123 &gxbb_vclk_div6_en.hw
2124 },
1936 .num_parents = 1, 2125 .num_parents = 1,
1937 }, 2126 },
1938}; 2127};
@@ -1943,7 +2132,9 @@ static struct clk_fixed_factor gxbb_vclk_div12 = {
1943 .hw.init = &(struct clk_init_data){ 2132 .hw.init = &(struct clk_init_data){
1944 .name = "vclk_div12", 2133 .name = "vclk_div12",
1945 .ops = &clk_fixed_factor_ops, 2134 .ops = &clk_fixed_factor_ops,
1946 .parent_names = (const char *[]){ "vclk_div12_en" }, 2135 .parent_hws = (const struct clk_hw *[]) {
2136 &gxbb_vclk_div12_en.hw
2137 },
1947 .num_parents = 1, 2138 .num_parents = 1,
1948 }, 2139 },
1949}; 2140};
@@ -1954,7 +2145,9 @@ static struct clk_fixed_factor gxbb_vclk2_div2 = {
1954 .hw.init = &(struct clk_init_data){ 2145 .hw.init = &(struct clk_init_data){
1955 .name = "vclk2_div2", 2146 .name = "vclk2_div2",
1956 .ops = &clk_fixed_factor_ops, 2147 .ops = &clk_fixed_factor_ops,
1957 .parent_names = (const char *[]){ "vclk2_div2_en" }, 2148 .parent_hws = (const struct clk_hw *[]) {
2149 &gxbb_vclk2_div2_en.hw
2150 },
1958 .num_parents = 1, 2151 .num_parents = 1,
1959 }, 2152 },
1960}; 2153};
@@ -1965,7 +2158,9 @@ static struct clk_fixed_factor gxbb_vclk2_div4 = {
1965 .hw.init = &(struct clk_init_data){ 2158 .hw.init = &(struct clk_init_data){
1966 .name = "vclk2_div4", 2159 .name = "vclk2_div4",
1967 .ops = &clk_fixed_factor_ops, 2160 .ops = &clk_fixed_factor_ops,
1968 .parent_names = (const char *[]){ "vclk2_div4_en" }, 2161 .parent_hws = (const struct clk_hw *[]) {
2162 &gxbb_vclk2_div4_en.hw
2163 },
1969 .num_parents = 1, 2164 .num_parents = 1,
1970 }, 2165 },
1971}; 2166};
@@ -1976,7 +2171,9 @@ static struct clk_fixed_factor gxbb_vclk2_div6 = {
1976 .hw.init = &(struct clk_init_data){ 2171 .hw.init = &(struct clk_init_data){
1977 .name = "vclk2_div6", 2172 .name = "vclk2_div6",
1978 .ops = &clk_fixed_factor_ops, 2173 .ops = &clk_fixed_factor_ops,
1979 .parent_names = (const char *[]){ "vclk2_div6_en" }, 2174 .parent_hws = (const struct clk_hw *[]) {
2175 &gxbb_vclk2_div6_en.hw
2176 },
1980 .num_parents = 1, 2177 .num_parents = 1,
1981 }, 2178 },
1982}; 2179};
@@ -1987,16 +2184,25 @@ static struct clk_fixed_factor gxbb_vclk2_div12 = {
1987 .hw.init = &(struct clk_init_data){ 2184 .hw.init = &(struct clk_init_data){
1988 .name = "vclk2_div12", 2185 .name = "vclk2_div12",
1989 .ops = &clk_fixed_factor_ops, 2186 .ops = &clk_fixed_factor_ops,
1990 .parent_names = (const char *[]){ "vclk2_div12_en" }, 2187 .parent_hws = (const struct clk_hw *[]) {
2188 &gxbb_vclk2_div12_en.hw
2189 },
1991 .num_parents = 1, 2190 .num_parents = 1,
1992 }, 2191 },
1993}; 2192};
1994 2193
1995static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 2194static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1996static const char * const gxbb_cts_parent_names[] = { 2195static const struct clk_hw *gxbb_cts_parent_hws[] = {
1997 "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6", 2196 &gxbb_vclk_div1.hw,
1998 "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4", 2197 &gxbb_vclk_div2.hw,
1999 "vclk2_div6", "vclk2_div12" 2198 &gxbb_vclk_div4.hw,
2199 &gxbb_vclk_div6.hw,
2200 &gxbb_vclk_div12.hw,
2201 &gxbb_vclk2_div1.hw,
2202 &gxbb_vclk2_div2.hw,
2203 &gxbb_vclk2_div4.hw,
2204 &gxbb_vclk2_div6.hw,
2205 &gxbb_vclk2_div12.hw,
2000}; 2206};
2001 2207
2002static struct clk_regmap gxbb_cts_enci_sel = { 2208static struct clk_regmap gxbb_cts_enci_sel = {
@@ -2009,8 +2215,8 @@ static struct clk_regmap gxbb_cts_enci_sel = {
2009 .hw.init = &(struct clk_init_data){ 2215 .hw.init = &(struct clk_init_data){
2010 .name = "cts_enci_sel", 2216 .name = "cts_enci_sel",
2011 .ops = &clk_regmap_mux_ops, 2217 .ops = &clk_regmap_mux_ops,
2012 .parent_names = gxbb_cts_parent_names, 2218 .parent_hws = gxbb_cts_parent_hws,
2013 .num_parents = ARRAY_SIZE(gxbb_cts_parent_names), 2219 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2014 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2220 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2015 }, 2221 },
2016}; 2222};
@@ -2025,8 +2231,8 @@ static struct clk_regmap gxbb_cts_encp_sel = {
2025 .hw.init = &(struct clk_init_data){ 2231 .hw.init = &(struct clk_init_data){
2026 .name = "cts_encp_sel", 2232 .name = "cts_encp_sel",
2027 .ops = &clk_regmap_mux_ops, 2233 .ops = &clk_regmap_mux_ops,
2028 .parent_names = gxbb_cts_parent_names, 2234 .parent_hws = gxbb_cts_parent_hws,
2029 .num_parents = ARRAY_SIZE(gxbb_cts_parent_names), 2235 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2030 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2236 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2031 }, 2237 },
2032}; 2238};
@@ -2041,18 +2247,25 @@ static struct clk_regmap gxbb_cts_vdac_sel = {
2041 .hw.init = &(struct clk_init_data){ 2247 .hw.init = &(struct clk_init_data){
2042 .name = "cts_vdac_sel", 2248 .name = "cts_vdac_sel",
2043 .ops = &clk_regmap_mux_ops, 2249 .ops = &clk_regmap_mux_ops,
2044 .parent_names = gxbb_cts_parent_names, 2250 .parent_hws = gxbb_cts_parent_hws,
2045 .num_parents = ARRAY_SIZE(gxbb_cts_parent_names), 2251 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2046 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2252 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2047 }, 2253 },
2048}; 2254};
2049 2255
2050/* TOFIX: add support for cts_tcon */ 2256/* TOFIX: add support for cts_tcon */
2051static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 }; 2257static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2052static const char * const gxbb_cts_hdmi_tx_parent_names[] = { 2258static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = {
2053 "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6", 2259 &gxbb_vclk_div1.hw,
2054 "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4", 2260 &gxbb_vclk_div2.hw,
2055 "vclk2_div6", "vclk2_div12" 2261 &gxbb_vclk_div4.hw,
2262 &gxbb_vclk_div6.hw,
2263 &gxbb_vclk_div12.hw,
2264 &gxbb_vclk2_div1.hw,
2265 &gxbb_vclk2_div2.hw,
2266 &gxbb_vclk2_div4.hw,
2267 &gxbb_vclk2_div6.hw,
2268 &gxbb_vclk2_div12.hw,
2056}; 2269};
2057 2270
2058static struct clk_regmap gxbb_hdmi_tx_sel = { 2271static struct clk_regmap gxbb_hdmi_tx_sel = {
@@ -2071,8 +2284,8 @@ static struct clk_regmap gxbb_hdmi_tx_sel = {
2071 * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12, 2284 * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
2072 * cts_tcon 2285 * cts_tcon
2073 */ 2286 */
2074 .parent_names = gxbb_cts_hdmi_tx_parent_names, 2287 .parent_hws = gxbb_cts_hdmi_tx_parent_hws,
2075 .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_names), 2288 .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws),
2076 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2289 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2077 }, 2290 },
2078}; 2291};
@@ -2085,7 +2298,9 @@ static struct clk_regmap gxbb_cts_enci = {
2085 .hw.init = &(struct clk_init_data) { 2298 .hw.init = &(struct clk_init_data) {
2086 .name = "cts_enci", 2299 .name = "cts_enci",
2087 .ops = &clk_regmap_gate_ops, 2300 .ops = &clk_regmap_gate_ops,
2088 .parent_names = (const char *[]){ "cts_enci_sel" }, 2301 .parent_hws = (const struct clk_hw *[]) {
2302 &gxbb_cts_enci_sel.hw
2303 },
2089 .num_parents = 1, 2304 .num_parents = 1,
2090 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2305 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2091 }, 2306 },
@@ -2099,7 +2314,9 @@ static struct clk_regmap gxbb_cts_encp = {
2099 .hw.init = &(struct clk_init_data) { 2314 .hw.init = &(struct clk_init_data) {
2100 .name = "cts_encp", 2315 .name = "cts_encp",
2101 .ops = &clk_regmap_gate_ops, 2316 .ops = &clk_regmap_gate_ops,
2102 .parent_names = (const char *[]){ "cts_encp_sel" }, 2317 .parent_hws = (const struct clk_hw *[]) {
2318 &gxbb_cts_encp_sel.hw
2319 },
2103 .num_parents = 1, 2320 .num_parents = 1,
2104 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2321 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2105 }, 2322 },
@@ -2113,7 +2330,9 @@ static struct clk_regmap gxbb_cts_vdac = {
2113 .hw.init = &(struct clk_init_data) { 2330 .hw.init = &(struct clk_init_data) {
2114 .name = "cts_vdac", 2331 .name = "cts_vdac",
2115 .ops = &clk_regmap_gate_ops, 2332 .ops = &clk_regmap_gate_ops,
2116 .parent_names = (const char *[]){ "cts_vdac_sel" }, 2333 .parent_hws = (const struct clk_hw *[]) {
2334 &gxbb_cts_vdac_sel.hw
2335 },
2117 .num_parents = 1, 2336 .num_parents = 1,
2118 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2337 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2119 }, 2338 },
@@ -2127,7 +2346,9 @@ static struct clk_regmap gxbb_hdmi_tx = {
2127 .hw.init = &(struct clk_init_data) { 2346 .hw.init = &(struct clk_init_data) {
2128 .name = "hdmi_tx", 2347 .name = "hdmi_tx",
2129 .ops = &clk_regmap_gate_ops, 2348 .ops = &clk_regmap_gate_ops,
2130 .parent_names = (const char *[]){ "hdmi_tx_sel" }, 2349 .parent_hws = (const struct clk_hw *[]) {
2350 &gxbb_hdmi_tx_sel.hw
2351 },
2131 .num_parents = 1, 2352 .num_parents = 1,
2132 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2353 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2133 }, 2354 },
@@ -2135,8 +2356,11 @@ static struct clk_regmap gxbb_hdmi_tx = {
2135 2356
2136/* HDMI Clocks */ 2357/* HDMI Clocks */
2137 2358
2138static const char * const gxbb_hdmi_parent_names[] = { 2359static const struct clk_parent_data gxbb_hdmi_parent_data[] = {
2139 IN_PREFIX "xtal", "fclk_div4", "fclk_div3", "fclk_div5" 2360 { .fw_name = "xtal", },
2361 { .hw = &gxbb_fclk_div4.hw },
2362 { .hw = &gxbb_fclk_div3.hw },
2363 { .hw = &gxbb_fclk_div5.hw },
2140}; 2364};
2141 2365
2142static struct clk_regmap gxbb_hdmi_sel = { 2366static struct clk_regmap gxbb_hdmi_sel = {
@@ -2149,8 +2373,8 @@ static struct clk_regmap gxbb_hdmi_sel = {
2149 .hw.init = &(struct clk_init_data){ 2373 .hw.init = &(struct clk_init_data){
2150 .name = "hdmi_sel", 2374 .name = "hdmi_sel",
2151 .ops = &clk_regmap_mux_ops, 2375 .ops = &clk_regmap_mux_ops,
2152 .parent_names = gxbb_hdmi_parent_names, 2376 .parent_data = gxbb_hdmi_parent_data,
2153 .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_names), 2377 .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data),
2154 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE, 2378 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2155 }, 2379 },
2156}; 2380};
@@ -2164,7 +2388,7 @@ static struct clk_regmap gxbb_hdmi_div = {
2164 .hw.init = &(struct clk_init_data){ 2388 .hw.init = &(struct clk_init_data){
2165 .name = "hdmi_div", 2389 .name = "hdmi_div",
2166 .ops = &clk_regmap_divider_ops, 2390 .ops = &clk_regmap_divider_ops,
2167 .parent_names = (const char *[]){ "hdmi_sel" }, 2391 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw },
2168 .num_parents = 1, 2392 .num_parents = 1,
2169 .flags = CLK_GET_RATE_NOCACHE, 2393 .flags = CLK_GET_RATE_NOCACHE,
2170 }, 2394 },
@@ -2178,7 +2402,7 @@ static struct clk_regmap gxbb_hdmi = {
2178 .hw.init = &(struct clk_init_data) { 2402 .hw.init = &(struct clk_init_data) {
2179 .name = "hdmi", 2403 .name = "hdmi",
2180 .ops = &clk_regmap_gate_ops, 2404 .ops = &clk_regmap_gate_ops,
2181 .parent_names = (const char *[]){ "hdmi_div" }, 2405 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw },
2182 .num_parents = 1, 2406 .num_parents = 1,
2183 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 2407 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2184 }, 2408 },
@@ -2186,8 +2410,11 @@ static struct clk_regmap gxbb_hdmi = {
2186 2410
2187/* VDEC clocks */ 2411/* VDEC clocks */
2188 2412
2189static const char * const gxbb_vdec_parent_names[] = { 2413static const struct clk_hw *gxbb_vdec_parent_hws[] = {
2190 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" 2414 &gxbb_fclk_div4.hw,
2415 &gxbb_fclk_div3.hw,
2416 &gxbb_fclk_div5.hw,
2417 &gxbb_fclk_div7.hw,
2191}; 2418};
2192 2419
2193static struct clk_regmap gxbb_vdec_1_sel = { 2420static struct clk_regmap gxbb_vdec_1_sel = {
@@ -2200,8 +2427,8 @@ static struct clk_regmap gxbb_vdec_1_sel = {
2200 .hw.init = &(struct clk_init_data){ 2427 .hw.init = &(struct clk_init_data){
2201 .name = "vdec_1_sel", 2428 .name = "vdec_1_sel",
2202 .ops = &clk_regmap_mux_ops, 2429 .ops = &clk_regmap_mux_ops,
2203 .parent_names = gxbb_vdec_parent_names, 2430 .parent_hws = gxbb_vdec_parent_hws,
2204 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names), 2431 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2205 .flags = CLK_SET_RATE_PARENT, 2432 .flags = CLK_SET_RATE_PARENT,
2206 }, 2433 },
2207}; 2434};
@@ -2216,7 +2443,9 @@ static struct clk_regmap gxbb_vdec_1_div = {
2216 .hw.init = &(struct clk_init_data){ 2443 .hw.init = &(struct clk_init_data){
2217 .name = "vdec_1_div", 2444 .name = "vdec_1_div",
2218 .ops = &clk_regmap_divider_ops, 2445 .ops = &clk_regmap_divider_ops,
2219 .parent_names = (const char *[]){ "vdec_1_sel" }, 2446 .parent_hws = (const struct clk_hw *[]) {
2447 &gxbb_vdec_1_sel.hw
2448 },
2220 .num_parents = 1, 2449 .num_parents = 1,
2221 .flags = CLK_SET_RATE_PARENT, 2450 .flags = CLK_SET_RATE_PARENT,
2222 }, 2451 },
@@ -2230,7 +2459,9 @@ static struct clk_regmap gxbb_vdec_1 = {
2230 .hw.init = &(struct clk_init_data) { 2459 .hw.init = &(struct clk_init_data) {
2231 .name = "vdec_1", 2460 .name = "vdec_1",
2232 .ops = &clk_regmap_gate_ops, 2461 .ops = &clk_regmap_gate_ops,
2233 .parent_names = (const char *[]){ "vdec_1_div" }, 2462 .parent_hws = (const struct clk_hw *[]) {
2463 &gxbb_vdec_1_div.hw
2464 },
2234 .num_parents = 1, 2465 .num_parents = 1,
2235 .flags = CLK_SET_RATE_PARENT, 2466 .flags = CLK_SET_RATE_PARENT,
2236 }, 2467 },
@@ -2246,8 +2477,8 @@ static struct clk_regmap gxbb_vdec_hevc_sel = {
2246 .hw.init = &(struct clk_init_data){ 2477 .hw.init = &(struct clk_init_data){
2247 .name = "vdec_hevc_sel", 2478 .name = "vdec_hevc_sel",
2248 .ops = &clk_regmap_mux_ops, 2479 .ops = &clk_regmap_mux_ops,
2249 .parent_names = gxbb_vdec_parent_names, 2480 .parent_hws = gxbb_vdec_parent_hws,
2250 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names), 2481 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2251 .flags = CLK_SET_RATE_PARENT, 2482 .flags = CLK_SET_RATE_PARENT,
2252 }, 2483 },
2253}; 2484};
@@ -2262,7 +2493,9 @@ static struct clk_regmap gxbb_vdec_hevc_div = {
2262 .hw.init = &(struct clk_init_data){ 2493 .hw.init = &(struct clk_init_data){
2263 .name = "vdec_hevc_div", 2494 .name = "vdec_hevc_div",
2264 .ops = &clk_regmap_divider_ops, 2495 .ops = &clk_regmap_divider_ops,
2265 .parent_names = (const char *[]){ "vdec_hevc_sel" }, 2496 .parent_hws = (const struct clk_hw *[]) {
2497 &gxbb_vdec_hevc_sel.hw
2498 },
2266 .num_parents = 1, 2499 .num_parents = 1,
2267 .flags = CLK_SET_RATE_PARENT, 2500 .flags = CLK_SET_RATE_PARENT,
2268 }, 2501 },
@@ -2276,7 +2509,9 @@ static struct clk_regmap gxbb_vdec_hevc = {
2276 .hw.init = &(struct clk_init_data) { 2509 .hw.init = &(struct clk_init_data) {
2277 .name = "vdec_hevc", 2510 .name = "vdec_hevc",
2278 .ops = &clk_regmap_gate_ops, 2511 .ops = &clk_regmap_gate_ops,
2279 .parent_names = (const char *[]){ "vdec_hevc_div" }, 2512 .parent_hws = (const struct clk_hw *[]) {
2513 &gxbb_vdec_hevc_div.hw
2514 },
2280 .num_parents = 1, 2515 .num_parents = 1,
2281 .flags = CLK_SET_RATE_PARENT, 2516 .flags = CLK_SET_RATE_PARENT,
2282 }, 2517 },
@@ -2284,9 +2519,18 @@ static struct clk_regmap gxbb_vdec_hevc = {
2284 2519
2285static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8, 2520static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
2286 9, 10, 11, 13, 14, }; 2521 9, 10, 11, 13, 14, };
2287static const char * const gen_clk_parent_names[] = { 2522static const struct clk_parent_data gen_clk_parent_data[] = {
2288 IN_PREFIX "xtal", "vdec_1", "vdec_hevc", "mpll0", "mpll1", "mpll2", 2523 { .fw_name = "xtal", },
2289 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll", 2524 { .hw = &gxbb_vdec_1.hw },
2525 { .hw = &gxbb_vdec_hevc.hw },
2526 { .hw = &gxbb_mpll0.hw },
2527 { .hw = &gxbb_mpll1.hw },
2528 { .hw = &gxbb_mpll2.hw },
2529 { .hw = &gxbb_fclk_div4.hw },
2530 { .hw = &gxbb_fclk_div3.hw },
2531 { .hw = &gxbb_fclk_div5.hw },
2532 { .hw = &gxbb_fclk_div7.hw },
2533 { .hw = &gxbb_gp0_pll.hw },
2290}; 2534};
2291 2535
2292static struct clk_regmap gxbb_gen_clk_sel = { 2536static struct clk_regmap gxbb_gen_clk_sel = {
@@ -2305,8 +2549,8 @@ static struct clk_regmap gxbb_gen_clk_sel = {
2305 * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4, 2549 * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
2306 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll 2550 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
2307 */ 2551 */
2308 .parent_names = gen_clk_parent_names, 2552 .parent_data = gen_clk_parent_data,
2309 .num_parents = ARRAY_SIZE(gen_clk_parent_names), 2553 .num_parents = ARRAY_SIZE(gen_clk_parent_data),
2310 }, 2554 },
2311}; 2555};
2312 2556
@@ -2319,7 +2563,9 @@ static struct clk_regmap gxbb_gen_clk_div = {
2319 .hw.init = &(struct clk_init_data){ 2563 .hw.init = &(struct clk_init_data){
2320 .name = "gen_clk_div", 2564 .name = "gen_clk_div",
2321 .ops = &clk_regmap_divider_ops, 2565 .ops = &clk_regmap_divider_ops,
2322 .parent_names = (const char *[]){ "gen_clk_sel" }, 2566 .parent_hws = (const struct clk_hw *[]) {
2567 &gxbb_gen_clk_sel.hw
2568 },
2323 .num_parents = 1, 2569 .num_parents = 1,
2324 .flags = CLK_SET_RATE_PARENT, 2570 .flags = CLK_SET_RATE_PARENT,
2325 }, 2571 },
@@ -2333,12 +2579,17 @@ static struct clk_regmap gxbb_gen_clk = {
2333 .hw.init = &(struct clk_init_data){ 2579 .hw.init = &(struct clk_init_data){
2334 .name = "gen_clk", 2580 .name = "gen_clk",
2335 .ops = &clk_regmap_gate_ops, 2581 .ops = &clk_regmap_gate_ops,
2336 .parent_names = (const char *[]){ "gen_clk_div" }, 2582 .parent_hws = (const struct clk_hw *[]) {
2583 &gxbb_gen_clk_div.hw
2584 },
2337 .num_parents = 1, 2585 .num_parents = 1,
2338 .flags = CLK_SET_RATE_PARENT, 2586 .flags = CLK_SET_RATE_PARENT,
2339 }, 2587 },
2340}; 2588};
2341 2589
2590#define MESON_GATE(_name, _reg, _bit) \
2591 MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)
2592
2342/* Everything Else (EE) domain gates */ 2593/* Everything Else (EE) domain gates */
2343static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); 2594static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
2344static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); 2595static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
index b67951909e04..bf8bea675d24 100644
--- a/drivers/clk/meson/meson-aoclk.c
+++ b/drivers/clk/meson/meson-aoclk.c
@@ -17,8 +17,6 @@
17#include <linux/slab.h> 17#include <linux/slab.h>
18#include "meson-aoclk.h" 18#include "meson-aoclk.h"
19 19
20#include "clk-input.h"
21
22static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev, 20static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
23 unsigned long id) 21 unsigned long id)
24{ 22{
@@ -33,37 +31,6 @@ static const struct reset_control_ops meson_aoclk_reset_ops = {
33 .reset = meson_aoclk_do_reset, 31 .reset = meson_aoclk_do_reset,
34}; 32};
35 33
36static int meson_aoclkc_register_inputs(struct device *dev,
37 struct meson_aoclk_data *data)
38{
39 struct clk_hw *hw;
40 char *str;
41 int i;
42
43 for (i = 0; i < data->num_inputs; i++) {
44 const struct meson_aoclk_input *in = &data->inputs[i];
45
46 str = kasprintf(GFP_KERNEL, "%s%s", data->input_prefix,
47 in->name);
48 if (!str)
49 return -ENOMEM;
50
51 hw = meson_clk_hw_register_input(dev, in->name, str, 0);
52 kfree(str);
53
54 if (IS_ERR(hw)) {
55 if (!in->required && PTR_ERR(hw) == -ENOENT)
56 continue;
57 else if (PTR_ERR(hw) != -EPROBE_DEFER)
58 dev_err(dev, "failed to register input %s\n",
59 in->name);
60 return PTR_ERR(hw);
61 }
62 }
63
64 return 0;
65}
66
67int meson_aoclkc_probe(struct platform_device *pdev) 34int meson_aoclkc_probe(struct platform_device *pdev)
68{ 35{
69 struct meson_aoclk_reset_controller *rstc; 36 struct meson_aoclk_reset_controller *rstc;
@@ -86,10 +53,6 @@ int meson_aoclkc_probe(struct platform_device *pdev)
86 return PTR_ERR(regmap); 53 return PTR_ERR(regmap);
87 } 54 }
88 55
89 ret = meson_aoclkc_register_inputs(dev, data);
90 if (ret)
91 return ret;
92
93 /* Reset Controller */ 56 /* Reset Controller */
94 rstc->data = data; 57 rstc->data = data;
95 rstc->regmap = regmap; 58 rstc->regmap = regmap;
diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aoclk.h
index 999cde3868f7..605b43855a69 100644
--- a/drivers/clk/meson/meson-aoclk.h
+++ b/drivers/clk/meson/meson-aoclk.h
@@ -18,20 +18,12 @@
18 18
19#include "clk-regmap.h" 19#include "clk-regmap.h"
20 20
21struct meson_aoclk_input {
22 const char *name;
23 bool required;
24};
25
26struct meson_aoclk_data { 21struct meson_aoclk_data {
27 const unsigned int reset_reg; 22 const unsigned int reset_reg;
28 const int num_reset; 23 const int num_reset;
29 const unsigned int *reset; 24 const unsigned int *reset;
30 const int num_clks; 25 const int num_clks;
31 struct clk_regmap **clks; 26 struct clk_regmap **clks;
32 const int num_inputs;
33 const struct meson_aoclk_input *inputs;
34 const char *input_prefix;
35 const struct clk_hw_onecell_data *hw_data; 27 const struct clk_hw_onecell_data *hw_data;
36}; 28};
37 29
diff --git a/drivers/clk/meson/meson-eeclk.c b/drivers/clk/meson/meson-eeclk.c
index 6ba2094be257..a7cb1e7aedc4 100644
--- a/drivers/clk/meson/meson-eeclk.c
+++ b/drivers/clk/meson/meson-eeclk.c
@@ -10,7 +10,6 @@
10#include <linux/mfd/syscon.h> 10#include <linux/mfd/syscon.h>
11#include <linux/regmap.h> 11#include <linux/regmap.h>
12 12
13#include "clk-input.h"
14#include "clk-regmap.h" 13#include "clk-regmap.h"
15#include "meson-eeclk.h" 14#include "meson-eeclk.h"
16 15
@@ -18,7 +17,6 @@ int meson_eeclkc_probe(struct platform_device *pdev)
18{ 17{
19 const struct meson_eeclkc_data *data; 18 const struct meson_eeclkc_data *data;
20 struct device *dev = &pdev->dev; 19 struct device *dev = &pdev->dev;
21 struct clk_hw *input;
22 struct regmap *map; 20 struct regmap *map;
23 int ret, i; 21 int ret, i;
24 22
@@ -37,14 +35,6 @@ int meson_eeclkc_probe(struct platform_device *pdev)
37 if (data->init_count) 35 if (data->init_count)
38 regmap_multi_reg_write(map, data->init_regs, data->init_count); 36 regmap_multi_reg_write(map, data->init_regs, data->init_count);
39 37
40 input = meson_clk_hw_register_input(dev, "xtal", IN_PREFIX "xtal", 0);
41 if (IS_ERR(input)) {
42 ret = PTR_ERR(input);
43 if (ret != -EPROBE_DEFER)
44 dev_err(dev, "failed to get input clock");
45 return ret;
46 }
47
48 /* Populate regmap for the regmap backed clocks */ 38 /* Populate regmap for the regmap backed clocks */
49 for (i = 0; i < data->regmap_clk_num; i++) 39 for (i = 0; i < data->regmap_clk_num; i++)
50 data->regmap_clks[i]->map = map; 40 data->regmap_clks[i]->map = map;
diff --git a/drivers/clk/meson/meson-eeclk.h b/drivers/clk/meson/meson-eeclk.h
index 9ab5d6fa7ccb..77316207bde1 100644
--- a/drivers/clk/meson/meson-eeclk.h
+++ b/drivers/clk/meson/meson-eeclk.h
@@ -10,8 +10,6 @@
10#include <linux/clk-provider.h> 10#include <linux/clk-provider.h>
11#include "clk-regmap.h" 11#include "clk-regmap.h"
12 12
13#define IN_PREFIX "ee-in-"
14
15struct platform_device; 13struct platform_device;
16 14
17struct meson_eeclkc_data { 15struct meson_eeclkc_data {
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 537219fa573e..67e6691e080c 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -97,7 +97,9 @@ static struct clk_regmap meson8b_fixed_pll_dco = {
97 .hw.init = &(struct clk_init_data){ 97 .hw.init = &(struct clk_init_data){
98 .name = "fixed_pll_dco", 98 .name = "fixed_pll_dco",
99 .ops = &meson_clk_pll_ro_ops, 99 .ops = &meson_clk_pll_ro_ops,
100 .parent_names = (const char *[]){ "xtal" }, 100 .parent_hws = (const struct clk_hw *[]) {
101 &meson8b_xtal.hw
102 },
101 .num_parents = 1, 103 .num_parents = 1,
102 }, 104 },
103}; 105};
@@ -112,7 +114,9 @@ static struct clk_regmap meson8b_fixed_pll = {
112 .hw.init = &(struct clk_init_data){ 114 .hw.init = &(struct clk_init_data){
113 .name = "fixed_pll", 115 .name = "fixed_pll",
114 .ops = &clk_regmap_divider_ro_ops, 116 .ops = &clk_regmap_divider_ro_ops,
115 .parent_names = (const char *[]){ "fixed_pll_dco" }, 117 .parent_hws = (const struct clk_hw *[]) {
118 &meson8b_fixed_pll_dco.hw
119 },
116 .num_parents = 1, 120 .num_parents = 1,
117 /* 121 /*
118 * This clock won't ever change at runtime so 122 * This clock won't ever change at runtime so
@@ -158,7 +162,9 @@ static struct clk_regmap meson8b_hdmi_pll_dco = {
158 /* sometimes also called "HPLL" or "HPLL PLL" */ 162 /* sometimes also called "HPLL" or "HPLL PLL" */
159 .name = "hdmi_pll_dco", 163 .name = "hdmi_pll_dco",
160 .ops = &meson_clk_pll_ro_ops, 164 .ops = &meson_clk_pll_ro_ops,
161 .parent_names = (const char *[]){ "xtal" }, 165 .parent_hws = (const struct clk_hw *[]) {
166 &meson8b_xtal.hw
167 },
162 .num_parents = 1, 168 .num_parents = 1,
163 }, 169 },
164}; 170};
@@ -173,7 +179,9 @@ static struct clk_regmap meson8b_hdmi_pll_lvds_out = {
173 .hw.init = &(struct clk_init_data){ 179 .hw.init = &(struct clk_init_data){
174 .name = "hdmi_pll_lvds_out", 180 .name = "hdmi_pll_lvds_out",
175 .ops = &clk_regmap_divider_ro_ops, 181 .ops = &clk_regmap_divider_ro_ops,
176 .parent_names = (const char *[]){ "hdmi_pll_dco" }, 182 .parent_hws = (const struct clk_hw *[]) {
183 &meson8b_hdmi_pll_dco.hw
184 },
177 .num_parents = 1, 185 .num_parents = 1,
178 .flags = CLK_SET_RATE_PARENT, 186 .flags = CLK_SET_RATE_PARENT,
179 }, 187 },
@@ -189,7 +197,9 @@ static struct clk_regmap meson8b_hdmi_pll_hdmi_out = {
189 .hw.init = &(struct clk_init_data){ 197 .hw.init = &(struct clk_init_data){
190 .name = "hdmi_pll_hdmi_out", 198 .name = "hdmi_pll_hdmi_out",
191 .ops = &clk_regmap_divider_ro_ops, 199 .ops = &clk_regmap_divider_ro_ops,
192 .parent_names = (const char *[]){ "hdmi_pll_dco" }, 200 .parent_hws = (const struct clk_hw *[]) {
201 &meson8b_hdmi_pll_dco.hw
202 },
193 .num_parents = 1, 203 .num_parents = 1,
194 .flags = CLK_SET_RATE_PARENT, 204 .flags = CLK_SET_RATE_PARENT,
195 }, 205 },
@@ -227,7 +237,9 @@ static struct clk_regmap meson8b_sys_pll_dco = {
227 .hw.init = &(struct clk_init_data){ 237 .hw.init = &(struct clk_init_data){
228 .name = "sys_pll_dco", 238 .name = "sys_pll_dco",
229 .ops = &meson_clk_pll_ops, 239 .ops = &meson_clk_pll_ops,
230 .parent_names = (const char *[]){ "xtal" }, 240 .parent_hws = (const struct clk_hw *[]) {
241 &meson8b_xtal.hw
242 },
231 .num_parents = 1, 243 .num_parents = 1,
232 }, 244 },
233}; 245};
@@ -242,7 +254,9 @@ static struct clk_regmap meson8b_sys_pll = {
242 .hw.init = &(struct clk_init_data){ 254 .hw.init = &(struct clk_init_data){
243 .name = "sys_pll", 255 .name = "sys_pll",
244 .ops = &clk_regmap_divider_ops, 256 .ops = &clk_regmap_divider_ops,
245 .parent_names = (const char *[]){ "sys_pll_dco" }, 257 .parent_hws = (const struct clk_hw *[]) {
258 &meson8b_sys_pll_dco.hw
259 },
246 .num_parents = 1, 260 .num_parents = 1,
247 .flags = CLK_SET_RATE_PARENT, 261 .flags = CLK_SET_RATE_PARENT,
248 }, 262 },
@@ -254,7 +268,9 @@ static struct clk_fixed_factor meson8b_fclk_div2_div = {
254 .hw.init = &(struct clk_init_data){ 268 .hw.init = &(struct clk_init_data){
255 .name = "fclk_div2_div", 269 .name = "fclk_div2_div",
256 .ops = &clk_fixed_factor_ops, 270 .ops = &clk_fixed_factor_ops,
257 .parent_names = (const char *[]){ "fixed_pll" }, 271 .parent_hws = (const struct clk_hw *[]) {
272 &meson8b_fixed_pll.hw
273 },
258 .num_parents = 1, 274 .num_parents = 1,
259 }, 275 },
260}; 276};
@@ -267,7 +283,9 @@ static struct clk_regmap meson8b_fclk_div2 = {
267 .hw.init = &(struct clk_init_data){ 283 .hw.init = &(struct clk_init_data){
268 .name = "fclk_div2", 284 .name = "fclk_div2",
269 .ops = &clk_regmap_gate_ops, 285 .ops = &clk_regmap_gate_ops,
270 .parent_names = (const char *[]){ "fclk_div2_div" }, 286 .parent_hws = (const struct clk_hw *[]) {
287 &meson8b_fclk_div2_div.hw
288 },
271 .num_parents = 1, 289 .num_parents = 1,
272 /* 290 /*
273 * FIXME: Ethernet with a RGMII PHYs is not working if 291 * FIXME: Ethernet with a RGMII PHYs is not working if
@@ -285,7 +303,9 @@ static struct clk_fixed_factor meson8b_fclk_div3_div = {
285 .hw.init = &(struct clk_init_data){ 303 .hw.init = &(struct clk_init_data){
286 .name = "fclk_div3_div", 304 .name = "fclk_div3_div",
287 .ops = &clk_fixed_factor_ops, 305 .ops = &clk_fixed_factor_ops,
288 .parent_names = (const char *[]){ "fixed_pll" }, 306 .parent_hws = (const struct clk_hw *[]) {
307 &meson8b_fixed_pll.hw
308 },
289 .num_parents = 1, 309 .num_parents = 1,
290 }, 310 },
291}; 311};
@@ -298,7 +318,9 @@ static struct clk_regmap meson8b_fclk_div3 = {
298 .hw.init = &(struct clk_init_data){ 318 .hw.init = &(struct clk_init_data){
299 .name = "fclk_div3", 319 .name = "fclk_div3",
300 .ops = &clk_regmap_gate_ops, 320 .ops = &clk_regmap_gate_ops,
301 .parent_names = (const char *[]){ "fclk_div3_div" }, 321 .parent_hws = (const struct clk_hw *[]) {
322 &meson8b_fclk_div3_div.hw
323 },
302 .num_parents = 1, 324 .num_parents = 1,
303 }, 325 },
304}; 326};
@@ -309,7 +331,9 @@ static struct clk_fixed_factor meson8b_fclk_div4_div = {
309 .hw.init = &(struct clk_init_data){ 331 .hw.init = &(struct clk_init_data){
310 .name = "fclk_div4_div", 332 .name = "fclk_div4_div",
311 .ops = &clk_fixed_factor_ops, 333 .ops = &clk_fixed_factor_ops,
312 .parent_names = (const char *[]){ "fixed_pll" }, 334 .parent_hws = (const struct clk_hw *[]) {
335 &meson8b_fixed_pll.hw
336 },
313 .num_parents = 1, 337 .num_parents = 1,
314 }, 338 },
315}; 339};
@@ -322,7 +346,9 @@ static struct clk_regmap meson8b_fclk_div4 = {
322 .hw.init = &(struct clk_init_data){ 346 .hw.init = &(struct clk_init_data){
323 .name = "fclk_div4", 347 .name = "fclk_div4",
324 .ops = &clk_regmap_gate_ops, 348 .ops = &clk_regmap_gate_ops,
325 .parent_names = (const char *[]){ "fclk_div4_div" }, 349 .parent_hws = (const struct clk_hw *[]) {
350 &meson8b_fclk_div4_div.hw
351 },
326 .num_parents = 1, 352 .num_parents = 1,
327 }, 353 },
328}; 354};
@@ -333,7 +359,9 @@ static struct clk_fixed_factor meson8b_fclk_div5_div = {
333 .hw.init = &(struct clk_init_data){ 359 .hw.init = &(struct clk_init_data){
334 .name = "fclk_div5_div", 360 .name = "fclk_div5_div",
335 .ops = &clk_fixed_factor_ops, 361 .ops = &clk_fixed_factor_ops,
336 .parent_names = (const char *[]){ "fixed_pll" }, 362 .parent_hws = (const struct clk_hw *[]) {
363 &meson8b_fixed_pll.hw
364 },
337 .num_parents = 1, 365 .num_parents = 1,
338 }, 366 },
339}; 367};
@@ -346,7 +374,9 @@ static struct clk_regmap meson8b_fclk_div5 = {
346 .hw.init = &(struct clk_init_data){ 374 .hw.init = &(struct clk_init_data){
347 .name = "fclk_div5", 375 .name = "fclk_div5",
348 .ops = &clk_regmap_gate_ops, 376 .ops = &clk_regmap_gate_ops,
349 .parent_names = (const char *[]){ "fclk_div5_div" }, 377 .parent_hws = (const struct clk_hw *[]) {
378 &meson8b_fclk_div5_div.hw
379 },
350 .num_parents = 1, 380 .num_parents = 1,
351 }, 381 },
352}; 382};
@@ -357,7 +387,9 @@ static struct clk_fixed_factor meson8b_fclk_div7_div = {
357 .hw.init = &(struct clk_init_data){ 387 .hw.init = &(struct clk_init_data){
358 .name = "fclk_div7_div", 388 .name = "fclk_div7_div",
359 .ops = &clk_fixed_factor_ops, 389 .ops = &clk_fixed_factor_ops,
360 .parent_names = (const char *[]){ "fixed_pll" }, 390 .parent_hws = (const struct clk_hw *[]) {
391 &meson8b_fixed_pll.hw
392 },
361 .num_parents = 1, 393 .num_parents = 1,
362 }, 394 },
363}; 395};
@@ -370,7 +402,9 @@ static struct clk_regmap meson8b_fclk_div7 = {
370 .hw.init = &(struct clk_init_data){ 402 .hw.init = &(struct clk_init_data){
371 .name = "fclk_div7", 403 .name = "fclk_div7",
372 .ops = &clk_regmap_gate_ops, 404 .ops = &clk_regmap_gate_ops,
373 .parent_names = (const char *[]){ "fclk_div7_div" }, 405 .parent_hws = (const struct clk_hw *[]) {
406 &meson8b_fclk_div7_div.hw
407 },
374 .num_parents = 1, 408 .num_parents = 1,
375 }, 409 },
376}; 410};
@@ -384,7 +418,9 @@ static struct clk_regmap meson8b_mpll_prediv = {
384 .hw.init = &(struct clk_init_data){ 418 .hw.init = &(struct clk_init_data){
385 .name = "mpll_prediv", 419 .name = "mpll_prediv",
386 .ops = &clk_regmap_divider_ro_ops, 420 .ops = &clk_regmap_divider_ro_ops,
387 .parent_names = (const char *[]){ "fixed_pll" }, 421 .parent_hws = (const struct clk_hw *[]) {
422 &meson8b_fixed_pll.hw
423 },
388 .num_parents = 1, 424 .num_parents = 1,
389 }, 425 },
390}; 426};
@@ -416,7 +452,9 @@ static struct clk_regmap meson8b_mpll0_div = {
416 .hw.init = &(struct clk_init_data){ 452 .hw.init = &(struct clk_init_data){
417 .name = "mpll0_div", 453 .name = "mpll0_div",
418 .ops = &meson_clk_mpll_ops, 454 .ops = &meson_clk_mpll_ops,
419 .parent_names = (const char *[]){ "mpll_prediv" }, 455 .parent_hws = (const struct clk_hw *[]) {
456 &meson8b_mpll_prediv.hw
457 },
420 .num_parents = 1, 458 .num_parents = 1,
421 }, 459 },
422}; 460};
@@ -429,7 +467,9 @@ static struct clk_regmap meson8b_mpll0 = {
429 .hw.init = &(struct clk_init_data){ 467 .hw.init = &(struct clk_init_data){
430 .name = "mpll0", 468 .name = "mpll0",
431 .ops = &clk_regmap_gate_ops, 469 .ops = &clk_regmap_gate_ops,
432 .parent_names = (const char *[]){ "mpll0_div" }, 470 .parent_hws = (const struct clk_hw *[]) {
471 &meson8b_mpll0_div.hw
472 },
433 .num_parents = 1, 473 .num_parents = 1,
434 .flags = CLK_SET_RATE_PARENT, 474 .flags = CLK_SET_RATE_PARENT,
435 }, 475 },
@@ -457,7 +497,9 @@ static struct clk_regmap meson8b_mpll1_div = {
457 .hw.init = &(struct clk_init_data){ 497 .hw.init = &(struct clk_init_data){
458 .name = "mpll1_div", 498 .name = "mpll1_div",
459 .ops = &meson_clk_mpll_ops, 499 .ops = &meson_clk_mpll_ops,
460 .parent_names = (const char *[]){ "mpll_prediv" }, 500 .parent_hws = (const struct clk_hw *[]) {
501 &meson8b_mpll_prediv.hw
502 },
461 .num_parents = 1, 503 .num_parents = 1,
462 }, 504 },
463}; 505};
@@ -470,7 +512,9 @@ static struct clk_regmap meson8b_mpll1 = {
470 .hw.init = &(struct clk_init_data){ 512 .hw.init = &(struct clk_init_data){
471 .name = "mpll1", 513 .name = "mpll1",
472 .ops = &clk_regmap_gate_ops, 514 .ops = &clk_regmap_gate_ops,
473 .parent_names = (const char *[]){ "mpll1_div" }, 515 .parent_hws = (const struct clk_hw *[]) {
516 &meson8b_mpll1_div.hw
517 },
474 .num_parents = 1, 518 .num_parents = 1,
475 .flags = CLK_SET_RATE_PARENT, 519 .flags = CLK_SET_RATE_PARENT,
476 }, 520 },
@@ -498,7 +542,9 @@ static struct clk_regmap meson8b_mpll2_div = {
498 .hw.init = &(struct clk_init_data){ 542 .hw.init = &(struct clk_init_data){
499 .name = "mpll2_div", 543 .name = "mpll2_div",
500 .ops = &meson_clk_mpll_ops, 544 .ops = &meson_clk_mpll_ops,
501 .parent_names = (const char *[]){ "mpll_prediv" }, 545 .parent_hws = (const struct clk_hw *[]) {
546 &meson8b_mpll_prediv.hw
547 },
502 .num_parents = 1, 548 .num_parents = 1,
503 }, 549 },
504}; 550};
@@ -511,7 +557,9 @@ static struct clk_regmap meson8b_mpll2 = {
511 .hw.init = &(struct clk_init_data){ 557 .hw.init = &(struct clk_init_data){
512 .name = "mpll2", 558 .name = "mpll2",
513 .ops = &clk_regmap_gate_ops, 559 .ops = &clk_regmap_gate_ops,
514 .parent_names = (const char *[]){ "mpll2_div" }, 560 .parent_hws = (const struct clk_hw *[]) {
561 &meson8b_mpll2_div.hw
562 },
515 .num_parents = 1, 563 .num_parents = 1,
516 .flags = CLK_SET_RATE_PARENT, 564 .flags = CLK_SET_RATE_PARENT,
517 }, 565 },
@@ -533,8 +581,11 @@ static struct clk_regmap meson8b_mpeg_clk_sel = {
533 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2, 581 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
534 * fclk_div4, fclk_div3, fclk_div5 582 * fclk_div4, fclk_div3, fclk_div5
535 */ 583 */
536 .parent_names = (const char *[]){ "fclk_div3", "fclk_div4", 584 .parent_hws = (const struct clk_hw *[]) {
537 "fclk_div5" }, 585 &meson8b_fclk_div3.hw,
586 &meson8b_fclk_div4.hw,
587 &meson8b_fclk_div5.hw,
588 },
538 .num_parents = 3, 589 .num_parents = 3,
539 }, 590 },
540}; 591};
@@ -548,7 +599,9 @@ static struct clk_regmap meson8b_mpeg_clk_div = {
548 .hw.init = &(struct clk_init_data){ 599 .hw.init = &(struct clk_init_data){
549 .name = "mpeg_clk_div", 600 .name = "mpeg_clk_div",
550 .ops = &clk_regmap_divider_ro_ops, 601 .ops = &clk_regmap_divider_ro_ops,
551 .parent_names = (const char *[]){ "mpeg_clk_sel" }, 602 .parent_hws = (const struct clk_hw *[]) {
603 &meson8b_mpeg_clk_sel.hw
604 },
552 .num_parents = 1, 605 .num_parents = 1,
553 }, 606 },
554}; 607};
@@ -561,7 +614,9 @@ static struct clk_regmap meson8b_clk81 = {
561 .hw.init = &(struct clk_init_data){ 614 .hw.init = &(struct clk_init_data){
562 .name = "clk81", 615 .name = "clk81",
563 .ops = &clk_regmap_gate_ops, 616 .ops = &clk_regmap_gate_ops,
564 .parent_names = (const char *[]){ "mpeg_clk_div" }, 617 .parent_hws = (const struct clk_hw *[]) {
618 &meson8b_mpeg_clk_div.hw
619 },
565 .num_parents = 1, 620 .num_parents = 1,
566 .flags = CLK_IS_CRITICAL, 621 .flags = CLK_IS_CRITICAL,
567 }, 622 },
@@ -576,7 +631,10 @@ static struct clk_regmap meson8b_cpu_in_sel = {
576 .hw.init = &(struct clk_init_data){ 631 .hw.init = &(struct clk_init_data){
577 .name = "cpu_in_sel", 632 .name = "cpu_in_sel",
578 .ops = &clk_regmap_mux_ops, 633 .ops = &clk_regmap_mux_ops,
579 .parent_names = (const char *[]){ "xtal", "sys_pll" }, 634 .parent_hws = (const struct clk_hw *[]) {
635 &meson8b_xtal.hw,
636 &meson8b_sys_pll.hw,
637 },
580 .num_parents = 2, 638 .num_parents = 2,
581 .flags = (CLK_SET_RATE_PARENT | 639 .flags = (CLK_SET_RATE_PARENT |
582 CLK_SET_RATE_NO_REPARENT), 640 CLK_SET_RATE_NO_REPARENT),
@@ -589,7 +647,9 @@ static struct clk_fixed_factor meson8b_cpu_in_div2 = {
589 .hw.init = &(struct clk_init_data){ 647 .hw.init = &(struct clk_init_data){
590 .name = "cpu_in_div2", 648 .name = "cpu_in_div2",
591 .ops = &clk_fixed_factor_ops, 649 .ops = &clk_fixed_factor_ops,
592 .parent_names = (const char *[]){ "cpu_in_sel" }, 650 .parent_hws = (const struct clk_hw *[]) {
651 &meson8b_cpu_in_sel.hw
652 },
593 .num_parents = 1, 653 .num_parents = 1,
594 .flags = CLK_SET_RATE_PARENT, 654 .flags = CLK_SET_RATE_PARENT,
595 }, 655 },
@@ -601,7 +661,9 @@ static struct clk_fixed_factor meson8b_cpu_in_div3 = {
601 .hw.init = &(struct clk_init_data){ 661 .hw.init = &(struct clk_init_data){
602 .name = "cpu_in_div3", 662 .name = "cpu_in_div3",
603 .ops = &clk_fixed_factor_ops, 663 .ops = &clk_fixed_factor_ops,
604 .parent_names = (const char *[]){ "cpu_in_sel" }, 664 .parent_hws = (const struct clk_hw *[]) {
665 &meson8b_cpu_in_sel.hw
666 },
605 .num_parents = 1, 667 .num_parents = 1,
606 .flags = CLK_SET_RATE_PARENT, 668 .flags = CLK_SET_RATE_PARENT,
607 }, 669 },
@@ -630,7 +692,9 @@ static struct clk_regmap meson8b_cpu_scale_div = {
630 .hw.init = &(struct clk_init_data){ 692 .hw.init = &(struct clk_init_data){
631 .name = "cpu_scale_div", 693 .name = "cpu_scale_div",
632 .ops = &clk_regmap_divider_ops, 694 .ops = &clk_regmap_divider_ops,
633 .parent_names = (const char *[]){ "cpu_in_sel" }, 695 .parent_hws = (const struct clk_hw *[]) {
696 &meson8b_cpu_in_sel.hw
697 },
634 .num_parents = 1, 698 .num_parents = 1,
635 .flags = CLK_SET_RATE_PARENT, 699 .flags = CLK_SET_RATE_PARENT,
636 }, 700 },
@@ -649,13 +713,15 @@ static struct clk_regmap meson8b_cpu_scale_out_sel = {
649 .ops = &clk_regmap_mux_ops, 713 .ops = &clk_regmap_mux_ops,
650 /* 714 /*
651 * NOTE: We are skipping the parent with value 0x2 (which is 715 * NOTE: We are skipping the parent with value 0x2 (which is
652 * "cpu_in_div3") because it results in a duty cycle of 33% 716 * meson8b_cpu_in_div3) because it results in a duty cycle of
653 * which makes the system unstable and can result in a lockup 717 * 33% which makes the system unstable and can result in a
654 * of the whole system. 718 * lockup of the whole system.
655 */ 719 */
656 .parent_names = (const char *[]) { "cpu_in_sel", 720 .parent_hws = (const struct clk_hw *[]) {
657 "cpu_in_div2", 721 &meson8b_cpu_in_sel.hw,
658 "cpu_scale_div" }, 722 &meson8b_cpu_in_div2.hw,
723 &meson8b_cpu_scale_div.hw,
724 },
659 .num_parents = 3, 725 .num_parents = 3,
660 .flags = CLK_SET_RATE_PARENT, 726 .flags = CLK_SET_RATE_PARENT,
661 }, 727 },
@@ -670,8 +736,10 @@ static struct clk_regmap meson8b_cpu_clk = {
670 .hw.init = &(struct clk_init_data){ 736 .hw.init = &(struct clk_init_data){
671 .name = "cpu_clk", 737 .name = "cpu_clk",
672 .ops = &clk_regmap_mux_ops, 738 .ops = &clk_regmap_mux_ops,
673 .parent_names = (const char *[]){ "xtal", 739 .parent_hws = (const struct clk_hw *[]) {
674 "cpu_scale_out_sel" }, 740 &meson8b_xtal.hw,
741 &meson8b_cpu_scale_out_sel.hw,
742 },
675 .num_parents = 2, 743 .num_parents = 2,
676 .flags = (CLK_SET_RATE_PARENT | 744 .flags = (CLK_SET_RATE_PARENT |
677 CLK_SET_RATE_NO_REPARENT | 745 CLK_SET_RATE_NO_REPARENT |
@@ -690,8 +758,13 @@ static struct clk_regmap meson8b_nand_clk_sel = {
690 .name = "nand_clk_sel", 758 .name = "nand_clk_sel",
691 .ops = &clk_regmap_mux_ops, 759 .ops = &clk_regmap_mux_ops,
692 /* FIXME all other parents are unknown: */ 760 /* FIXME all other parents are unknown: */
693 .parent_names = (const char *[]){ "fclk_div4", "fclk_div3", 761 .parent_hws = (const struct clk_hw *[]) {
694 "fclk_div5", "fclk_div7", "xtal" }, 762 &meson8b_fclk_div4.hw,
763 &meson8b_fclk_div3.hw,
764 &meson8b_fclk_div5.hw,
765 &meson8b_fclk_div7.hw,
766 &meson8b_xtal.hw,
767 },
695 .num_parents = 5, 768 .num_parents = 5,
696 .flags = CLK_SET_RATE_PARENT, 769 .flags = CLK_SET_RATE_PARENT,
697 }, 770 },
@@ -707,7 +780,9 @@ static struct clk_regmap meson8b_nand_clk_div = {
707 .hw.init = &(struct clk_init_data){ 780 .hw.init = &(struct clk_init_data){
708 .name = "nand_clk_div", 781 .name = "nand_clk_div",
709 .ops = &clk_regmap_divider_ops, 782 .ops = &clk_regmap_divider_ops,
710 .parent_names = (const char *[]){ "nand_clk_sel" }, 783 .parent_hws = (const struct clk_hw *[]) {
784 &meson8b_nand_clk_sel.hw
785 },
711 .num_parents = 1, 786 .num_parents = 1,
712 .flags = CLK_SET_RATE_PARENT, 787 .flags = CLK_SET_RATE_PARENT,
713 }, 788 },
@@ -721,7 +796,9 @@ static struct clk_regmap meson8b_nand_clk_gate = {
721 .hw.init = &(struct clk_init_data){ 796 .hw.init = &(struct clk_init_data){
722 .name = "nand_clk_gate", 797 .name = "nand_clk_gate",
723 .ops = &clk_regmap_gate_ops, 798 .ops = &clk_regmap_gate_ops,
724 .parent_names = (const char *[]){ "nand_clk_div" }, 799 .parent_hws = (const struct clk_hw *[]) {
800 &meson8b_nand_clk_div.hw
801 },
725 .num_parents = 1, 802 .num_parents = 1,
726 .flags = CLK_SET_RATE_PARENT, 803 .flags = CLK_SET_RATE_PARENT,
727 }, 804 },
@@ -733,7 +810,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div2 = {
733 .hw.init = &(struct clk_init_data){ 810 .hw.init = &(struct clk_init_data){
734 .name = "cpu_clk_div2", 811 .name = "cpu_clk_div2",
735 .ops = &clk_fixed_factor_ops, 812 .ops = &clk_fixed_factor_ops,
736 .parent_names = (const char *[]){ "cpu_clk" }, 813 .parent_hws = (const struct clk_hw *[]) {
814 &meson8b_cpu_clk.hw
815 },
737 .num_parents = 1, 816 .num_parents = 1,
738 }, 817 },
739}; 818};
@@ -744,7 +823,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div3 = {
744 .hw.init = &(struct clk_init_data){ 823 .hw.init = &(struct clk_init_data){
745 .name = "cpu_clk_div3", 824 .name = "cpu_clk_div3",
746 .ops = &clk_fixed_factor_ops, 825 .ops = &clk_fixed_factor_ops,
747 .parent_names = (const char *[]){ "cpu_clk" }, 826 .parent_hws = (const struct clk_hw *[]) {
827 &meson8b_cpu_clk.hw
828 },
748 .num_parents = 1, 829 .num_parents = 1,
749 }, 830 },
750}; 831};
@@ -755,7 +836,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div4 = {
755 .hw.init = &(struct clk_init_data){ 836 .hw.init = &(struct clk_init_data){
756 .name = "cpu_clk_div4", 837 .name = "cpu_clk_div4",
757 .ops = &clk_fixed_factor_ops, 838 .ops = &clk_fixed_factor_ops,
758 .parent_names = (const char *[]){ "cpu_clk" }, 839 .parent_hws = (const struct clk_hw *[]) {
840 &meson8b_cpu_clk.hw
841 },
759 .num_parents = 1, 842 .num_parents = 1,
760 }, 843 },
761}; 844};
@@ -766,7 +849,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div5 = {
766 .hw.init = &(struct clk_init_data){ 849 .hw.init = &(struct clk_init_data){
767 .name = "cpu_clk_div5", 850 .name = "cpu_clk_div5",
768 .ops = &clk_fixed_factor_ops, 851 .ops = &clk_fixed_factor_ops,
769 .parent_names = (const char *[]){ "cpu_clk" }, 852 .parent_hws = (const struct clk_hw *[]) {
853 &meson8b_cpu_clk.hw
854 },
770 .num_parents = 1, 855 .num_parents = 1,
771 }, 856 },
772}; 857};
@@ -777,7 +862,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div6 = {
777 .hw.init = &(struct clk_init_data){ 862 .hw.init = &(struct clk_init_data){
778 .name = "cpu_clk_div6", 863 .name = "cpu_clk_div6",
779 .ops = &clk_fixed_factor_ops, 864 .ops = &clk_fixed_factor_ops,
780 .parent_names = (const char *[]){ "cpu_clk" }, 865 .parent_hws = (const struct clk_hw *[]) {
866 &meson8b_cpu_clk.hw
867 },
781 .num_parents = 1, 868 .num_parents = 1,
782 }, 869 },
783}; 870};
@@ -788,7 +875,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div7 = {
788 .hw.init = &(struct clk_init_data){ 875 .hw.init = &(struct clk_init_data){
789 .name = "cpu_clk_div7", 876 .name = "cpu_clk_div7",
790 .ops = &clk_fixed_factor_ops, 877 .ops = &clk_fixed_factor_ops,
791 .parent_names = (const char *[]){ "cpu_clk" }, 878 .parent_hws = (const struct clk_hw *[]) {
879 &meson8b_cpu_clk.hw
880 },
792 .num_parents = 1, 881 .num_parents = 1,
793 }, 882 },
794}; 883};
@@ -799,7 +888,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div8 = {
799 .hw.init = &(struct clk_init_data){ 888 .hw.init = &(struct clk_init_data){
800 .name = "cpu_clk_div8", 889 .name = "cpu_clk_div8",
801 .ops = &clk_fixed_factor_ops, 890 .ops = &clk_fixed_factor_ops,
802 .parent_names = (const char *[]){ "cpu_clk" }, 891 .parent_hws = (const struct clk_hw *[]) {
892 &meson8b_cpu_clk.hw
893 },
803 .num_parents = 1, 894 .num_parents = 1,
804 }, 895 },
805}; 896};
@@ -815,13 +906,15 @@ static struct clk_regmap meson8b_apb_clk_sel = {
815 .hw.init = &(struct clk_init_data){ 906 .hw.init = &(struct clk_init_data){
816 .name = "apb_clk_sel", 907 .name = "apb_clk_sel",
817 .ops = &clk_regmap_mux_ops, 908 .ops = &clk_regmap_mux_ops,
818 .parent_names = (const char *[]){ "cpu_clk_div2", 909 .parent_hws = (const struct clk_hw *[]) {
819 "cpu_clk_div3", 910 &meson8b_cpu_clk_div2.hw,
820 "cpu_clk_div4", 911 &meson8b_cpu_clk_div3.hw,
821 "cpu_clk_div5", 912 &meson8b_cpu_clk_div4.hw,
822 "cpu_clk_div6", 913 &meson8b_cpu_clk_div5.hw,
823 "cpu_clk_div7", 914 &meson8b_cpu_clk_div6.hw,
824 "cpu_clk_div8", }, 915 &meson8b_cpu_clk_div7.hw,
916 &meson8b_cpu_clk_div8.hw,
917 },
825 .num_parents = 7, 918 .num_parents = 7,
826 }, 919 },
827}; 920};
@@ -835,7 +928,9 @@ static struct clk_regmap meson8b_apb_clk_gate = {
835 .hw.init = &(struct clk_init_data){ 928 .hw.init = &(struct clk_init_data){
836 .name = "apb_clk_dis", 929 .name = "apb_clk_dis",
837 .ops = &clk_regmap_gate_ro_ops, 930 .ops = &clk_regmap_gate_ro_ops,
838 .parent_names = (const char *[]){ "apb_clk_sel" }, 931 .parent_hws = (const struct clk_hw *[]) {
932 &meson8b_apb_clk_sel.hw
933 },
839 .num_parents = 1, 934 .num_parents = 1,
840 .flags = CLK_SET_RATE_PARENT, 935 .flags = CLK_SET_RATE_PARENT,
841 }, 936 },
@@ -850,13 +945,15 @@ static struct clk_regmap meson8b_periph_clk_sel = {
850 .hw.init = &(struct clk_init_data){ 945 .hw.init = &(struct clk_init_data){
851 .name = "periph_clk_sel", 946 .name = "periph_clk_sel",
852 .ops = &clk_regmap_mux_ops, 947 .ops = &clk_regmap_mux_ops,
853 .parent_names = (const char *[]){ "cpu_clk_div2", 948 .parent_hws = (const struct clk_hw *[]) {
854 "cpu_clk_div3", 949 &meson8b_cpu_clk_div2.hw,
855 "cpu_clk_div4", 950 &meson8b_cpu_clk_div3.hw,
856 "cpu_clk_div5", 951 &meson8b_cpu_clk_div4.hw,
857 "cpu_clk_div6", 952 &meson8b_cpu_clk_div5.hw,
858 "cpu_clk_div7", 953 &meson8b_cpu_clk_div6.hw,
859 "cpu_clk_div8", }, 954 &meson8b_cpu_clk_div7.hw,
955 &meson8b_cpu_clk_div8.hw,
956 },
860 .num_parents = 7, 957 .num_parents = 7,
861 }, 958 },
862}; 959};
@@ -870,7 +967,9 @@ static struct clk_regmap meson8b_periph_clk_gate = {
870 .hw.init = &(struct clk_init_data){ 967 .hw.init = &(struct clk_init_data){
871 .name = "periph_clk_dis", 968 .name = "periph_clk_dis",
872 .ops = &clk_regmap_gate_ro_ops, 969 .ops = &clk_regmap_gate_ro_ops,
873 .parent_names = (const char *[]){ "periph_clk_sel" }, 970 .parent_hws = (const struct clk_hw *[]) {
971 &meson8b_periph_clk_sel.hw
972 },
874 .num_parents = 1, 973 .num_parents = 1,
875 .flags = CLK_SET_RATE_PARENT, 974 .flags = CLK_SET_RATE_PARENT,
876 }, 975 },
@@ -887,13 +986,15 @@ static struct clk_regmap meson8b_axi_clk_sel = {
887 .hw.init = &(struct clk_init_data){ 986 .hw.init = &(struct clk_init_data){
888 .name = "axi_clk_sel", 987 .name = "axi_clk_sel",
889 .ops = &clk_regmap_mux_ops, 988 .ops = &clk_regmap_mux_ops,
890 .parent_names = (const char *[]){ "cpu_clk_div2", 989 .parent_hws = (const struct clk_hw *[]) {
891 "cpu_clk_div3", 990 &meson8b_cpu_clk_div2.hw,
892 "cpu_clk_div4", 991 &meson8b_cpu_clk_div3.hw,
893 "cpu_clk_div5", 992 &meson8b_cpu_clk_div4.hw,
894 "cpu_clk_div6", 993 &meson8b_cpu_clk_div5.hw,
895 "cpu_clk_div7", 994 &meson8b_cpu_clk_div6.hw,
896 "cpu_clk_div8", }, 995 &meson8b_cpu_clk_div7.hw,
996 &meson8b_cpu_clk_div8.hw,
997 },
897 .num_parents = 7, 998 .num_parents = 7,
898 }, 999 },
899}; 1000};
@@ -907,7 +1008,9 @@ static struct clk_regmap meson8b_axi_clk_gate = {
907 .hw.init = &(struct clk_init_data){ 1008 .hw.init = &(struct clk_init_data){
908 .name = "axi_clk_dis", 1009 .name = "axi_clk_dis",
909 .ops = &clk_regmap_gate_ro_ops, 1010 .ops = &clk_regmap_gate_ro_ops,
910 .parent_names = (const char *[]){ "axi_clk_sel" }, 1011 .parent_hws = (const struct clk_hw *[]) {
1012 &meson8b_axi_clk_sel.hw
1013 },
911 .num_parents = 1, 1014 .num_parents = 1,
912 .flags = CLK_SET_RATE_PARENT, 1015 .flags = CLK_SET_RATE_PARENT,
913 }, 1016 },
@@ -922,13 +1025,15 @@ static struct clk_regmap meson8b_l2_dram_clk_sel = {
922 .hw.init = &(struct clk_init_data){ 1025 .hw.init = &(struct clk_init_data){
923 .name = "l2_dram_clk_sel", 1026 .name = "l2_dram_clk_sel",
924 .ops = &clk_regmap_mux_ops, 1027 .ops = &clk_regmap_mux_ops,
925 .parent_names = (const char *[]){ "cpu_clk_div2", 1028 .parent_hws = (const struct clk_hw *[]) {
926 "cpu_clk_div3", 1029 &meson8b_cpu_clk_div2.hw,
927 "cpu_clk_div4", 1030 &meson8b_cpu_clk_div3.hw,
928 "cpu_clk_div5", 1031 &meson8b_cpu_clk_div4.hw,
929 "cpu_clk_div6", 1032 &meson8b_cpu_clk_div5.hw,
930 "cpu_clk_div7", 1033 &meson8b_cpu_clk_div6.hw,
931 "cpu_clk_div8", }, 1034 &meson8b_cpu_clk_div7.hw,
1035 &meson8b_cpu_clk_div8.hw,
1036 },
932 .num_parents = 7, 1037 .num_parents = 7,
933 }, 1038 },
934}; 1039};
@@ -942,7 +1047,9 @@ static struct clk_regmap meson8b_l2_dram_clk_gate = {
942 .hw.init = &(struct clk_init_data){ 1047 .hw.init = &(struct clk_init_data){
943 .name = "l2_dram_clk_dis", 1048 .name = "l2_dram_clk_dis",
944 .ops = &clk_regmap_gate_ro_ops, 1049 .ops = &clk_regmap_gate_ro_ops,
945 .parent_names = (const char *[]){ "l2_dram_clk_sel" }, 1050 .parent_hws = (const struct clk_hw *[]) {
1051 &meson8b_l2_dram_clk_sel.hw
1052 },
946 .num_parents = 1, 1053 .num_parents = 1,
947 .flags = CLK_SET_RATE_PARENT, 1054 .flags = CLK_SET_RATE_PARENT,
948 }, 1055 },
@@ -963,7 +1070,9 @@ static struct clk_regmap meson8b_vid_pll_in_sel = {
963 * Meson8b: hdmi_pll_dco 1070 * Meson8b: hdmi_pll_dco
964 * Meson8m2: vid2_pll 1071 * Meson8m2: vid2_pll
965 */ 1072 */
966 .parent_names = (const char *[]){ "hdmi_pll_dco" }, 1073 .parent_hws = (const struct clk_hw *[]) {
1074 &meson8b_hdmi_pll_dco.hw
1075 },
967 .num_parents = 1, 1076 .num_parents = 1,
968 .flags = CLK_SET_RATE_PARENT, 1077 .flags = CLK_SET_RATE_PARENT,
969 }, 1078 },
@@ -977,7 +1086,9 @@ static struct clk_regmap meson8b_vid_pll_in_en = {
977 .hw.init = &(struct clk_init_data){ 1086 .hw.init = &(struct clk_init_data){
978 .name = "vid_pll_in_en", 1087 .name = "vid_pll_in_en",
979 .ops = &clk_regmap_gate_ro_ops, 1088 .ops = &clk_regmap_gate_ro_ops,
980 .parent_names = (const char *[]){ "vid_pll_in_sel" }, 1089 .parent_hws = (const struct clk_hw *[]) {
1090 &meson8b_vid_pll_in_sel.hw
1091 },
981 .num_parents = 1, 1092 .num_parents = 1,
982 .flags = CLK_SET_RATE_PARENT, 1093 .flags = CLK_SET_RATE_PARENT,
983 }, 1094 },
@@ -992,7 +1103,9 @@ static struct clk_regmap meson8b_vid_pll_pre_div = {
992 .hw.init = &(struct clk_init_data){ 1103 .hw.init = &(struct clk_init_data){
993 .name = "vid_pll_pre_div", 1104 .name = "vid_pll_pre_div",
994 .ops = &clk_regmap_divider_ro_ops, 1105 .ops = &clk_regmap_divider_ro_ops,
995 .parent_names = (const char *[]){ "vid_pll_in_en" }, 1106 .parent_hws = (const struct clk_hw *[]) {
1107 &meson8b_vid_pll_in_en.hw
1108 },
996 .num_parents = 1, 1109 .num_parents = 1,
997 .flags = CLK_SET_RATE_PARENT, 1110 .flags = CLK_SET_RATE_PARENT,
998 }, 1111 },
@@ -1007,7 +1120,9 @@ static struct clk_regmap meson8b_vid_pll_post_div = {
1007 .hw.init = &(struct clk_init_data){ 1120 .hw.init = &(struct clk_init_data){
1008 .name = "vid_pll_post_div", 1121 .name = "vid_pll_post_div",
1009 .ops = &clk_regmap_divider_ro_ops, 1122 .ops = &clk_regmap_divider_ro_ops,
1010 .parent_names = (const char *[]){ "vid_pll_pre_div" }, 1123 .parent_hws = (const struct clk_hw *[]) {
1124 &meson8b_vid_pll_pre_div.hw
1125 },
1011 .num_parents = 1, 1126 .num_parents = 1,
1012 .flags = CLK_SET_RATE_PARENT, 1127 .flags = CLK_SET_RATE_PARENT,
1013 }, 1128 },
@@ -1023,8 +1138,10 @@ static struct clk_regmap meson8b_vid_pll = {
1023 .name = "vid_pll", 1138 .name = "vid_pll",
1024 .ops = &clk_regmap_mux_ro_ops, 1139 .ops = &clk_regmap_mux_ro_ops,
1025 /* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */ 1140 /* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */
1026 .parent_names = (const char *[]){ "vid_pll_pre_div", 1141 .parent_hws = (const struct clk_hw *[]) {
1027 "vid_pll_post_div" }, 1142 &meson8b_vid_pll_pre_div.hw,
1143 &meson8b_vid_pll_post_div.hw,
1144 },
1028 .num_parents = 2, 1145 .num_parents = 2,
1029 .flags = CLK_SET_RATE_PARENT, 1146 .flags = CLK_SET_RATE_PARENT,
1030 }, 1147 },
@@ -1039,15 +1156,22 @@ static struct clk_regmap meson8b_vid_pll_final_div = {
1039 .hw.init = &(struct clk_init_data){ 1156 .hw.init = &(struct clk_init_data){
1040 .name = "vid_pll_final_div", 1157 .name = "vid_pll_final_div",
1041 .ops = &clk_regmap_divider_ro_ops, 1158 .ops = &clk_regmap_divider_ro_ops,
1042 .parent_names = (const char *[]){ "vid_pll" }, 1159 .parent_hws = (const struct clk_hw *[]) {
1160 &meson8b_vid_pll.hw
1161 },
1043 .num_parents = 1, 1162 .num_parents = 1,
1044 .flags = CLK_SET_RATE_PARENT, 1163 .flags = CLK_SET_RATE_PARENT,
1045 }, 1164 },
1046}; 1165};
1047 1166
1048static const char * const meson8b_vclk_mux_parents[] = { 1167static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = {
1049 "vid_pll_final_div", "fclk_div4", "fclk_div3", "fclk_div5", 1168 &meson8b_vid_pll_final_div.hw,
1050 "vid_pll_final_div", "fclk_div7", "mpll1" 1169 &meson8b_fclk_div4.hw,
1170 &meson8b_fclk_div3.hw,
1171 &meson8b_fclk_div5.hw,
1172 &meson8b_vid_pll_final_div.hw,
1173 &meson8b_fclk_div7.hw,
1174 &meson8b_mpll1.hw,
1051}; 1175};
1052 1176
1053static struct clk_regmap meson8b_vclk_in_sel = { 1177static struct clk_regmap meson8b_vclk_in_sel = {
@@ -1059,8 +1183,8 @@ static struct clk_regmap meson8b_vclk_in_sel = {
1059 .hw.init = &(struct clk_init_data){ 1183 .hw.init = &(struct clk_init_data){
1060 .name = "vclk_in_sel", 1184 .name = "vclk_in_sel",
1061 .ops = &clk_regmap_mux_ro_ops, 1185 .ops = &clk_regmap_mux_ro_ops,
1062 .parent_names = meson8b_vclk_mux_parents, 1186 .parent_hws = meson8b_vclk_mux_parent_hws,
1063 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parents), 1187 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
1064 .flags = CLK_SET_RATE_PARENT, 1188 .flags = CLK_SET_RATE_PARENT,
1065 }, 1189 },
1066}; 1190};
@@ -1073,7 +1197,9 @@ static struct clk_regmap meson8b_vclk_in_en = {
1073 .hw.init = &(struct clk_init_data){ 1197 .hw.init = &(struct clk_init_data){
1074 .name = "vclk_in_en", 1198 .name = "vclk_in_en",
1075 .ops = &clk_regmap_gate_ro_ops, 1199 .ops = &clk_regmap_gate_ro_ops,
1076 .parent_names = (const char *[]){ "vclk_in_sel" }, 1200 .parent_hws = (const struct clk_hw *[]) {
1201 &meson8b_vclk_in_sel.hw
1202 },
1077 .num_parents = 1, 1203 .num_parents = 1,
1078 .flags = CLK_SET_RATE_PARENT, 1204 .flags = CLK_SET_RATE_PARENT,
1079 }, 1205 },
@@ -1087,7 +1213,9 @@ static struct clk_regmap meson8b_vclk_div1_gate = {
1087 .hw.init = &(struct clk_init_data){ 1213 .hw.init = &(struct clk_init_data){
1088 .name = "vclk_div1_en", 1214 .name = "vclk_div1_en",
1089 .ops = &clk_regmap_gate_ro_ops, 1215 .ops = &clk_regmap_gate_ro_ops,
1090 .parent_names = (const char *[]){ "vclk_in_en" }, 1216 .parent_hws = (const struct clk_hw *[]) {
1217 &meson8b_vclk_in_en.hw
1218 },
1091 .num_parents = 1, 1219 .num_parents = 1,
1092 .flags = CLK_SET_RATE_PARENT, 1220 .flags = CLK_SET_RATE_PARENT,
1093 }, 1221 },
@@ -1099,7 +1227,9 @@ static struct clk_fixed_factor meson8b_vclk_div2_div = {
1099 .hw.init = &(struct clk_init_data){ 1227 .hw.init = &(struct clk_init_data){
1100 .name = "vclk_div2", 1228 .name = "vclk_div2",
1101 .ops = &clk_fixed_factor_ops, 1229 .ops = &clk_fixed_factor_ops,
1102 .parent_names = (const char *[]){ "vclk_in_en" }, 1230 .parent_hws = (const struct clk_hw *[]) {
1231 &meson8b_vclk_in_en.hw
1232 },
1103 .num_parents = 1, 1233 .num_parents = 1,
1104 .flags = CLK_SET_RATE_PARENT, 1234 .flags = CLK_SET_RATE_PARENT,
1105 } 1235 }
@@ -1113,7 +1243,9 @@ static struct clk_regmap meson8b_vclk_div2_div_gate = {
1113 .hw.init = &(struct clk_init_data){ 1243 .hw.init = &(struct clk_init_data){
1114 .name = "vclk_div2_en", 1244 .name = "vclk_div2_en",
1115 .ops = &clk_regmap_gate_ro_ops, 1245 .ops = &clk_regmap_gate_ro_ops,
1116 .parent_names = (const char *[]){ "vclk_div2" }, 1246 .parent_hws = (const struct clk_hw *[]) {
1247 &meson8b_vclk_div2_div.hw
1248 },
1117 .num_parents = 1, 1249 .num_parents = 1,
1118 .flags = CLK_SET_RATE_PARENT, 1250 .flags = CLK_SET_RATE_PARENT,
1119 }, 1251 },
@@ -1125,7 +1257,9 @@ static struct clk_fixed_factor meson8b_vclk_div4_div = {
1125 .hw.init = &(struct clk_init_data){ 1257 .hw.init = &(struct clk_init_data){
1126 .name = "vclk_div4", 1258 .name = "vclk_div4",
1127 .ops = &clk_fixed_factor_ops, 1259 .ops = &clk_fixed_factor_ops,
1128 .parent_names = (const char *[]){ "vclk_in_en" }, 1260 .parent_hws = (const struct clk_hw *[]) {
1261 &meson8b_vclk_in_en.hw
1262 },
1129 .num_parents = 1, 1263 .num_parents = 1,
1130 .flags = CLK_SET_RATE_PARENT, 1264 .flags = CLK_SET_RATE_PARENT,
1131 } 1265 }
@@ -1139,7 +1273,9 @@ static struct clk_regmap meson8b_vclk_div4_div_gate = {
1139 .hw.init = &(struct clk_init_data){ 1273 .hw.init = &(struct clk_init_data){
1140 .name = "vclk_div4_en", 1274 .name = "vclk_div4_en",
1141 .ops = &clk_regmap_gate_ro_ops, 1275 .ops = &clk_regmap_gate_ro_ops,
1142 .parent_names = (const char *[]){ "vclk_div4" }, 1276 .parent_hws = (const struct clk_hw *[]) {
1277 &meson8b_vclk_div4_div.hw
1278 },
1143 .num_parents = 1, 1279 .num_parents = 1,
1144 .flags = CLK_SET_RATE_PARENT, 1280 .flags = CLK_SET_RATE_PARENT,
1145 }, 1281 },
@@ -1151,7 +1287,9 @@ static struct clk_fixed_factor meson8b_vclk_div6_div = {
1151 .hw.init = &(struct clk_init_data){ 1287 .hw.init = &(struct clk_init_data){
1152 .name = "vclk_div6", 1288 .name = "vclk_div6",
1153 .ops = &clk_fixed_factor_ops, 1289 .ops = &clk_fixed_factor_ops,
1154 .parent_names = (const char *[]){ "vclk_in_en" }, 1290 .parent_hws = (const struct clk_hw *[]) {
1291 &meson8b_vclk_in_en.hw
1292 },
1155 .num_parents = 1, 1293 .num_parents = 1,
1156 .flags = CLK_SET_RATE_PARENT, 1294 .flags = CLK_SET_RATE_PARENT,
1157 } 1295 }
@@ -1165,7 +1303,9 @@ static struct clk_regmap meson8b_vclk_div6_div_gate = {
1165 .hw.init = &(struct clk_init_data){ 1303 .hw.init = &(struct clk_init_data){
1166 .name = "vclk_div6_en", 1304 .name = "vclk_div6_en",
1167 .ops = &clk_regmap_gate_ro_ops, 1305 .ops = &clk_regmap_gate_ro_ops,
1168 .parent_names = (const char *[]){ "vclk_div6" }, 1306 .parent_hws = (const struct clk_hw *[]) {
1307 &meson8b_vclk_div6_div.hw
1308 },
1169 .num_parents = 1, 1309 .num_parents = 1,
1170 .flags = CLK_SET_RATE_PARENT, 1310 .flags = CLK_SET_RATE_PARENT,
1171 }, 1311 },
@@ -1177,7 +1317,9 @@ static struct clk_fixed_factor meson8b_vclk_div12_div = {
1177 .hw.init = &(struct clk_init_data){ 1317 .hw.init = &(struct clk_init_data){
1178 .name = "vclk_div12", 1318 .name = "vclk_div12",
1179 .ops = &clk_fixed_factor_ops, 1319 .ops = &clk_fixed_factor_ops,
1180 .parent_names = (const char *[]){ "vclk_in_en" }, 1320 .parent_hws = (const struct clk_hw *[]) {
1321 &meson8b_vclk_in_en.hw
1322 },
1181 .num_parents = 1, 1323 .num_parents = 1,
1182 .flags = CLK_SET_RATE_PARENT, 1324 .flags = CLK_SET_RATE_PARENT,
1183 } 1325 }
@@ -1191,7 +1333,9 @@ static struct clk_regmap meson8b_vclk_div12_div_gate = {
1191 .hw.init = &(struct clk_init_data){ 1333 .hw.init = &(struct clk_init_data){
1192 .name = "vclk_div12_en", 1334 .name = "vclk_div12_en",
1193 .ops = &clk_regmap_gate_ro_ops, 1335 .ops = &clk_regmap_gate_ro_ops,
1194 .parent_names = (const char *[]){ "vclk_div12" }, 1336 .parent_hws = (const struct clk_hw *[]) {
1337 &meson8b_vclk_div12_div.hw
1338 },
1195 .num_parents = 1, 1339 .num_parents = 1,
1196 .flags = CLK_SET_RATE_PARENT, 1340 .flags = CLK_SET_RATE_PARENT,
1197 }, 1341 },
@@ -1206,8 +1350,8 @@ static struct clk_regmap meson8b_vclk2_in_sel = {
1206 .hw.init = &(struct clk_init_data){ 1350 .hw.init = &(struct clk_init_data){
1207 .name = "vclk2_in_sel", 1351 .name = "vclk2_in_sel",
1208 .ops = &clk_regmap_mux_ro_ops, 1352 .ops = &clk_regmap_mux_ro_ops,
1209 .parent_names = meson8b_vclk_mux_parents, 1353 .parent_hws = meson8b_vclk_mux_parent_hws,
1210 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parents), 1354 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
1211 .flags = CLK_SET_RATE_PARENT, 1355 .flags = CLK_SET_RATE_PARENT,
1212 }, 1356 },
1213}; 1357};
@@ -1220,7 +1364,9 @@ static struct clk_regmap meson8b_vclk2_clk_in_en = {
1220 .hw.init = &(struct clk_init_data){ 1364 .hw.init = &(struct clk_init_data){
1221 .name = "vclk2_in_en", 1365 .name = "vclk2_in_en",
1222 .ops = &clk_regmap_gate_ro_ops, 1366 .ops = &clk_regmap_gate_ro_ops,
1223 .parent_names = (const char *[]){ "vclk2_in_sel" }, 1367 .parent_hws = (const struct clk_hw *[]) {
1368 &meson8b_vclk2_in_sel.hw
1369 },
1224 .num_parents = 1, 1370 .num_parents = 1,
1225 .flags = CLK_SET_RATE_PARENT, 1371 .flags = CLK_SET_RATE_PARENT,
1226 }, 1372 },
@@ -1234,7 +1380,9 @@ static struct clk_regmap meson8b_vclk2_div1_gate = {
1234 .hw.init = &(struct clk_init_data){ 1380 .hw.init = &(struct clk_init_data){
1235 .name = "vclk2_div1_en", 1381 .name = "vclk2_div1_en",
1236 .ops = &clk_regmap_gate_ro_ops, 1382 .ops = &clk_regmap_gate_ro_ops,
1237 .parent_names = (const char *[]){ "vclk2_in_en" }, 1383 .parent_hws = (const struct clk_hw *[]) {
1384 &meson8b_vclk2_clk_in_en.hw
1385 },
1238 .num_parents = 1, 1386 .num_parents = 1,
1239 .flags = CLK_SET_RATE_PARENT, 1387 .flags = CLK_SET_RATE_PARENT,
1240 }, 1388 },
@@ -1246,7 +1394,9 @@ static struct clk_fixed_factor meson8b_vclk2_div2_div = {
1246 .hw.init = &(struct clk_init_data){ 1394 .hw.init = &(struct clk_init_data){
1247 .name = "vclk2_div2", 1395 .name = "vclk2_div2",
1248 .ops = &clk_fixed_factor_ops, 1396 .ops = &clk_fixed_factor_ops,
1249 .parent_names = (const char *[]){ "vclk2_in_en" }, 1397 .parent_hws = (const struct clk_hw *[]) {
1398 &meson8b_vclk2_clk_in_en.hw
1399 },
1250 .num_parents = 1, 1400 .num_parents = 1,
1251 .flags = CLK_SET_RATE_PARENT, 1401 .flags = CLK_SET_RATE_PARENT,
1252 } 1402 }
@@ -1260,7 +1410,9 @@ static struct clk_regmap meson8b_vclk2_div2_div_gate = {
1260 .hw.init = &(struct clk_init_data){ 1410 .hw.init = &(struct clk_init_data){
1261 .name = "vclk2_div2_en", 1411 .name = "vclk2_div2_en",
1262 .ops = &clk_regmap_gate_ro_ops, 1412 .ops = &clk_regmap_gate_ro_ops,
1263 .parent_names = (const char *[]){ "vclk2_div2" }, 1413 .parent_hws = (const struct clk_hw *[]) {
1414 &meson8b_vclk2_div2_div.hw
1415 },
1264 .num_parents = 1, 1416 .num_parents = 1,
1265 .flags = CLK_SET_RATE_PARENT, 1417 .flags = CLK_SET_RATE_PARENT,
1266 }, 1418 },
@@ -1272,7 +1424,9 @@ static struct clk_fixed_factor meson8b_vclk2_div4_div = {
1272 .hw.init = &(struct clk_init_data){ 1424 .hw.init = &(struct clk_init_data){
1273 .name = "vclk2_div4", 1425 .name = "vclk2_div4",
1274 .ops = &clk_fixed_factor_ops, 1426 .ops = &clk_fixed_factor_ops,
1275 .parent_names = (const char *[]){ "vclk2_in_en" }, 1427 .parent_hws = (const struct clk_hw *[]) {
1428 &meson8b_vclk2_clk_in_en.hw
1429 },
1276 .num_parents = 1, 1430 .num_parents = 1,
1277 .flags = CLK_SET_RATE_PARENT, 1431 .flags = CLK_SET_RATE_PARENT,
1278 } 1432 }
@@ -1286,7 +1440,9 @@ static struct clk_regmap meson8b_vclk2_div4_div_gate = {
1286 .hw.init = &(struct clk_init_data){ 1440 .hw.init = &(struct clk_init_data){
1287 .name = "vclk2_div4_en", 1441 .name = "vclk2_div4_en",
1288 .ops = &clk_regmap_gate_ro_ops, 1442 .ops = &clk_regmap_gate_ro_ops,
1289 .parent_names = (const char *[]){ "vclk2_div4" }, 1443 .parent_hws = (const struct clk_hw *[]) {
1444 &meson8b_vclk2_div4_div.hw
1445 },
1290 .num_parents = 1, 1446 .num_parents = 1,
1291 .flags = CLK_SET_RATE_PARENT, 1447 .flags = CLK_SET_RATE_PARENT,
1292 }, 1448 },
@@ -1298,7 +1454,9 @@ static struct clk_fixed_factor meson8b_vclk2_div6_div = {
1298 .hw.init = &(struct clk_init_data){ 1454 .hw.init = &(struct clk_init_data){
1299 .name = "vclk2_div6", 1455 .name = "vclk2_div6",
1300 .ops = &clk_fixed_factor_ops, 1456 .ops = &clk_fixed_factor_ops,
1301 .parent_names = (const char *[]){ "vclk2_in_en" }, 1457 .parent_hws = (const struct clk_hw *[]) {
1458 &meson8b_vclk2_clk_in_en.hw
1459 },
1302 .num_parents = 1, 1460 .num_parents = 1,
1303 .flags = CLK_SET_RATE_PARENT, 1461 .flags = CLK_SET_RATE_PARENT,
1304 } 1462 }
@@ -1312,7 +1470,9 @@ static struct clk_regmap meson8b_vclk2_div6_div_gate = {
1312 .hw.init = &(struct clk_init_data){ 1470 .hw.init = &(struct clk_init_data){
1313 .name = "vclk2_div6_en", 1471 .name = "vclk2_div6_en",
1314 .ops = &clk_regmap_gate_ro_ops, 1472 .ops = &clk_regmap_gate_ro_ops,
1315 .parent_names = (const char *[]){ "vclk2_div6" }, 1473 .parent_hws = (const struct clk_hw *[]) {
1474 &meson8b_vclk2_div6_div.hw
1475 },
1316 .num_parents = 1, 1476 .num_parents = 1,
1317 .flags = CLK_SET_RATE_PARENT, 1477 .flags = CLK_SET_RATE_PARENT,
1318 }, 1478 },
@@ -1324,7 +1484,9 @@ static struct clk_fixed_factor meson8b_vclk2_div12_div = {
1324 .hw.init = &(struct clk_init_data){ 1484 .hw.init = &(struct clk_init_data){
1325 .name = "vclk2_div12", 1485 .name = "vclk2_div12",
1326 .ops = &clk_fixed_factor_ops, 1486 .ops = &clk_fixed_factor_ops,
1327 .parent_names = (const char *[]){ "vclk2_in_en" }, 1487 .parent_hws = (const struct clk_hw *[]) {
1488 &meson8b_vclk2_clk_in_en.hw
1489 },
1328 .num_parents = 1, 1490 .num_parents = 1,
1329 .flags = CLK_SET_RATE_PARENT, 1491 .flags = CLK_SET_RATE_PARENT,
1330 } 1492 }
@@ -1338,15 +1500,20 @@ static struct clk_regmap meson8b_vclk2_div12_div_gate = {
1338 .hw.init = &(struct clk_init_data){ 1500 .hw.init = &(struct clk_init_data){
1339 .name = "vclk2_div12_en", 1501 .name = "vclk2_div12_en",
1340 .ops = &clk_regmap_gate_ro_ops, 1502 .ops = &clk_regmap_gate_ro_ops,
1341 .parent_names = (const char *[]){ "vclk2_div12" }, 1503 .parent_hws = (const struct clk_hw *[]) {
1504 &meson8b_vclk2_div12_div.hw
1505 },
1342 .num_parents = 1, 1506 .num_parents = 1,
1343 .flags = CLK_SET_RATE_PARENT, 1507 .flags = CLK_SET_RATE_PARENT,
1344 }, 1508 },
1345}; 1509};
1346 1510
1347static const char * const meson8b_vclk_enc_mux_parents[] = { 1511static const struct clk_hw *meson8b_vclk_enc_mux_parent_hws[] = {
1348 "vclk_div1_en", "vclk_div2_en", "vclk_div4_en", "vclk_div6_en", 1512 &meson8b_vclk_div1_gate.hw,
1349 "vclk_div12_en", 1513 &meson8b_vclk_div2_div_gate.hw,
1514 &meson8b_vclk_div4_div_gate.hw,
1515 &meson8b_vclk_div6_div_gate.hw,
1516 &meson8b_vclk_div12_div_gate.hw,
1350}; 1517};
1351 1518
1352static struct clk_regmap meson8b_cts_enct_sel = { 1519static struct clk_regmap meson8b_cts_enct_sel = {
@@ -1358,8 +1525,8 @@ static struct clk_regmap meson8b_cts_enct_sel = {
1358 .hw.init = &(struct clk_init_data){ 1525 .hw.init = &(struct clk_init_data){
1359 .name = "cts_enct_sel", 1526 .name = "cts_enct_sel",
1360 .ops = &clk_regmap_mux_ro_ops, 1527 .ops = &clk_regmap_mux_ro_ops,
1361 .parent_names = meson8b_vclk_enc_mux_parents, 1528 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1362 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents), 1529 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1363 .flags = CLK_SET_RATE_PARENT, 1530 .flags = CLK_SET_RATE_PARENT,
1364 }, 1531 },
1365}; 1532};
@@ -1372,7 +1539,9 @@ static struct clk_regmap meson8b_cts_enct = {
1372 .hw.init = &(struct clk_init_data){ 1539 .hw.init = &(struct clk_init_data){
1373 .name = "cts_enct", 1540 .name = "cts_enct",
1374 .ops = &clk_regmap_gate_ro_ops, 1541 .ops = &clk_regmap_gate_ro_ops,
1375 .parent_names = (const char *[]){ "cts_enct_sel" }, 1542 .parent_hws = (const struct clk_hw *[]) {
1543 &meson8b_cts_enct_sel.hw
1544 },
1376 .num_parents = 1, 1545 .num_parents = 1,
1377 .flags = CLK_SET_RATE_PARENT, 1546 .flags = CLK_SET_RATE_PARENT,
1378 }, 1547 },
@@ -1387,8 +1556,8 @@ static struct clk_regmap meson8b_cts_encp_sel = {
1387 .hw.init = &(struct clk_init_data){ 1556 .hw.init = &(struct clk_init_data){
1388 .name = "cts_encp_sel", 1557 .name = "cts_encp_sel",
1389 .ops = &clk_regmap_mux_ro_ops, 1558 .ops = &clk_regmap_mux_ro_ops,
1390 .parent_names = meson8b_vclk_enc_mux_parents, 1559 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1391 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents), 1560 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1392 .flags = CLK_SET_RATE_PARENT, 1561 .flags = CLK_SET_RATE_PARENT,
1393 }, 1562 },
1394}; 1563};
@@ -1401,7 +1570,9 @@ static struct clk_regmap meson8b_cts_encp = {
1401 .hw.init = &(struct clk_init_data){ 1570 .hw.init = &(struct clk_init_data){
1402 .name = "cts_encp", 1571 .name = "cts_encp",
1403 .ops = &clk_regmap_gate_ro_ops, 1572 .ops = &clk_regmap_gate_ro_ops,
1404 .parent_names = (const char *[]){ "cts_encp_sel" }, 1573 .parent_hws = (const struct clk_hw *[]) {
1574 &meson8b_cts_encp_sel.hw
1575 },
1405 .num_parents = 1, 1576 .num_parents = 1,
1406 .flags = CLK_SET_RATE_PARENT, 1577 .flags = CLK_SET_RATE_PARENT,
1407 }, 1578 },
@@ -1416,8 +1587,8 @@ static struct clk_regmap meson8b_cts_enci_sel = {
1416 .hw.init = &(struct clk_init_data){ 1587 .hw.init = &(struct clk_init_data){
1417 .name = "cts_enci_sel", 1588 .name = "cts_enci_sel",
1418 .ops = &clk_regmap_mux_ro_ops, 1589 .ops = &clk_regmap_mux_ro_ops,
1419 .parent_names = meson8b_vclk_enc_mux_parents, 1590 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1420 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents), 1591 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1421 .flags = CLK_SET_RATE_PARENT, 1592 .flags = CLK_SET_RATE_PARENT,
1422 }, 1593 },
1423}; 1594};
@@ -1430,7 +1601,9 @@ static struct clk_regmap meson8b_cts_enci = {
1430 .hw.init = &(struct clk_init_data){ 1601 .hw.init = &(struct clk_init_data){
1431 .name = "cts_enci", 1602 .name = "cts_enci",
1432 .ops = &clk_regmap_gate_ro_ops, 1603 .ops = &clk_regmap_gate_ro_ops,
1433 .parent_names = (const char *[]){ "cts_enci_sel" }, 1604 .parent_hws = (const struct clk_hw *[]) {
1605 &meson8b_cts_enci_sel.hw
1606 },
1434 .num_parents = 1, 1607 .num_parents = 1,
1435 .flags = CLK_SET_RATE_PARENT, 1608 .flags = CLK_SET_RATE_PARENT,
1436 }, 1609 },
@@ -1445,8 +1618,8 @@ static struct clk_regmap meson8b_hdmi_tx_pixel_sel = {
1445 .hw.init = &(struct clk_init_data){ 1618 .hw.init = &(struct clk_init_data){
1446 .name = "hdmi_tx_pixel_sel", 1619 .name = "hdmi_tx_pixel_sel",
1447 .ops = &clk_regmap_mux_ro_ops, 1620 .ops = &clk_regmap_mux_ro_ops,
1448 .parent_names = meson8b_vclk_enc_mux_parents, 1621 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1449 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents), 1622 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1450 .flags = CLK_SET_RATE_PARENT, 1623 .flags = CLK_SET_RATE_PARENT,
1451 }, 1624 },
1452}; 1625};
@@ -1459,15 +1632,20 @@ static struct clk_regmap meson8b_hdmi_tx_pixel = {
1459 .hw.init = &(struct clk_init_data){ 1632 .hw.init = &(struct clk_init_data){
1460 .name = "hdmi_tx_pixel", 1633 .name = "hdmi_tx_pixel",
1461 .ops = &clk_regmap_gate_ro_ops, 1634 .ops = &clk_regmap_gate_ro_ops,
1462 .parent_names = (const char *[]){ "hdmi_tx_pixel_sel" }, 1635 .parent_hws = (const struct clk_hw *[]) {
1636 &meson8b_hdmi_tx_pixel_sel.hw
1637 },
1463 .num_parents = 1, 1638 .num_parents = 1,
1464 .flags = CLK_SET_RATE_PARENT, 1639 .flags = CLK_SET_RATE_PARENT,
1465 }, 1640 },
1466}; 1641};
1467 1642
1468static const char * const meson8b_vclk2_enc_mux_parents[] = { 1643static const struct clk_hw *meson8b_vclk2_enc_mux_parent_hws[] = {
1469 "vclk2_div1_en", "vclk2_div2_en", "vclk2_div4_en", "vclk2_div6_en", 1644 &meson8b_vclk2_div1_gate.hw,
1470 "vclk2_div12_en", 1645 &meson8b_vclk2_div2_div_gate.hw,
1646 &meson8b_vclk2_div4_div_gate.hw,
1647 &meson8b_vclk2_div6_div_gate.hw,
1648 &meson8b_vclk2_div12_div_gate.hw,
1471}; 1649};
1472 1650
1473static struct clk_regmap meson8b_cts_encl_sel = { 1651static struct clk_regmap meson8b_cts_encl_sel = {
@@ -1479,8 +1657,8 @@ static struct clk_regmap meson8b_cts_encl_sel = {
1479 .hw.init = &(struct clk_init_data){ 1657 .hw.init = &(struct clk_init_data){
1480 .name = "cts_encl_sel", 1658 .name = "cts_encl_sel",
1481 .ops = &clk_regmap_mux_ro_ops, 1659 .ops = &clk_regmap_mux_ro_ops,
1482 .parent_names = meson8b_vclk2_enc_mux_parents, 1660 .parent_hws = meson8b_vclk2_enc_mux_parent_hws,
1483 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parents), 1661 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
1484 .flags = CLK_SET_RATE_PARENT, 1662 .flags = CLK_SET_RATE_PARENT,
1485 }, 1663 },
1486}; 1664};
@@ -1493,7 +1671,9 @@ static struct clk_regmap meson8b_cts_encl = {
1493 .hw.init = &(struct clk_init_data){ 1671 .hw.init = &(struct clk_init_data){
1494 .name = "cts_encl", 1672 .name = "cts_encl",
1495 .ops = &clk_regmap_gate_ro_ops, 1673 .ops = &clk_regmap_gate_ro_ops,
1496 .parent_names = (const char *[]){ "cts_encl_sel" }, 1674 .parent_hws = (const struct clk_hw *[]) {
1675 &meson8b_cts_encl_sel.hw
1676 },
1497 .num_parents = 1, 1677 .num_parents = 1,
1498 .flags = CLK_SET_RATE_PARENT, 1678 .flags = CLK_SET_RATE_PARENT,
1499 }, 1679 },
@@ -1508,8 +1688,8 @@ static struct clk_regmap meson8b_cts_vdac0_sel = {
1508 .hw.init = &(struct clk_init_data){ 1688 .hw.init = &(struct clk_init_data){
1509 .name = "cts_vdac0_sel", 1689 .name = "cts_vdac0_sel",
1510 .ops = &clk_regmap_mux_ro_ops, 1690 .ops = &clk_regmap_mux_ro_ops,
1511 .parent_names = meson8b_vclk2_enc_mux_parents, 1691 .parent_hws = meson8b_vclk2_enc_mux_parent_hws,
1512 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parents), 1692 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
1513 .flags = CLK_SET_RATE_PARENT, 1693 .flags = CLK_SET_RATE_PARENT,
1514 }, 1694 },
1515}; 1695};
@@ -1522,7 +1702,9 @@ static struct clk_regmap meson8b_cts_vdac0 = {
1522 .hw.init = &(struct clk_init_data){ 1702 .hw.init = &(struct clk_init_data){
1523 .name = "cts_vdac0", 1703 .name = "cts_vdac0",
1524 .ops = &clk_regmap_gate_ro_ops, 1704 .ops = &clk_regmap_gate_ro_ops,
1525 .parent_names = (const char *[]){ "cts_vdac0_sel" }, 1705 .parent_hws = (const struct clk_hw *[]) {
1706 &meson8b_cts_vdac0_sel.hw
1707 },
1526 .num_parents = 1, 1708 .num_parents = 1,
1527 .flags = CLK_SET_RATE_PARENT, 1709 .flags = CLK_SET_RATE_PARENT,
1528 }, 1710 },
@@ -1539,7 +1721,9 @@ static struct clk_regmap meson8b_hdmi_sys_sel = {
1539 .name = "hdmi_sys_sel", 1721 .name = "hdmi_sys_sel",
1540 .ops = &clk_regmap_mux_ro_ops, 1722 .ops = &clk_regmap_mux_ro_ops,
1541 /* FIXME: all other parents are unknown */ 1723 /* FIXME: all other parents are unknown */
1542 .parent_names = (const char *[]){ "xtal" }, 1724 .parent_hws = (const struct clk_hw *[]) {
1725 &meson8b_xtal.hw
1726 },
1543 .num_parents = 1, 1727 .num_parents = 1,
1544 .flags = CLK_SET_RATE_NO_REPARENT, 1728 .flags = CLK_SET_RATE_NO_REPARENT,
1545 }, 1729 },
@@ -1554,7 +1738,9 @@ static struct clk_regmap meson8b_hdmi_sys_div = {
1554 .hw.init = &(struct clk_init_data){ 1738 .hw.init = &(struct clk_init_data){
1555 .name = "hdmi_sys_div", 1739 .name = "hdmi_sys_div",
1556 .ops = &clk_regmap_divider_ro_ops, 1740 .ops = &clk_regmap_divider_ro_ops,
1557 .parent_names = (const char *[]){ "hdmi_sys_sel" }, 1741 .parent_hws = (const struct clk_hw *[]) {
1742 &meson8b_hdmi_sys_sel.hw
1743 },
1558 .num_parents = 1, 1744 .num_parents = 1,
1559 .flags = CLK_SET_RATE_PARENT, 1745 .flags = CLK_SET_RATE_PARENT,
1560 }, 1746 },
@@ -1568,7 +1754,9 @@ static struct clk_regmap meson8b_hdmi_sys = {
1568 .hw.init = &(struct clk_init_data) { 1754 .hw.init = &(struct clk_init_data) {
1569 .name = "hdmi_sys", 1755 .name = "hdmi_sys",
1570 .ops = &clk_regmap_gate_ro_ops, 1756 .ops = &clk_regmap_gate_ro_ops,
1571 .parent_names = (const char *[]){ "hdmi_sys_div" }, 1757 .parent_hws = (const struct clk_hw *[]) {
1758 &meson8b_hdmi_sys_div.hw
1759 },
1572 .num_parents = 1, 1760 .num_parents = 1,
1573 .flags = CLK_SET_RATE_PARENT, 1761 .flags = CLK_SET_RATE_PARENT,
1574 }, 1762 },
@@ -1579,9 +1767,14 @@ static struct clk_regmap meson8b_hdmi_sys = {
1579 * muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only 1767 * muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only
1580 * has mali_0 and no glitch-free mux. 1768 * has mali_0 and no glitch-free mux.
1581 */ 1769 */
1582static const char * const meson8b_mali_0_1_parent_names[] = { 1770static const struct clk_hw *meson8b_mali_0_1_parent_hws[] = {
1583 "xtal", "mpll2", "mpll1", "fclk_div7", "fclk_div4", "fclk_div3", 1771 &meson8b_xtal.hw,
1584 "fclk_div5" 1772 &meson8b_mpll2.hw,
1773 &meson8b_mpll1.hw,
1774 &meson8b_fclk_div7.hw,
1775 &meson8b_fclk_div4.hw,
1776 &meson8b_fclk_div3.hw,
1777 &meson8b_fclk_div5.hw,
1585}; 1778};
1586 1779
1587static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 }; 1780static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 };
@@ -1596,8 +1789,8 @@ static struct clk_regmap meson8b_mali_0_sel = {
1596 .hw.init = &(struct clk_init_data){ 1789 .hw.init = &(struct clk_init_data){
1597 .name = "mali_0_sel", 1790 .name = "mali_0_sel",
1598 .ops = &clk_regmap_mux_ops, 1791 .ops = &clk_regmap_mux_ops,
1599 .parent_names = meson8b_mali_0_1_parent_names, 1792 .parent_hws = meson8b_mali_0_1_parent_hws,
1600 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_names), 1793 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_hws),
1601 /* 1794 /*
1602 * Don't propagate rate changes up because the only changeable 1795 * Don't propagate rate changes up because the only changeable
1603 * parents are mpll1 and mpll2 but we need those for audio and 1796 * parents are mpll1 and mpll2 but we need those for audio and
@@ -1617,7 +1810,9 @@ static struct clk_regmap meson8b_mali_0_div = {
1617 .hw.init = &(struct clk_init_data){ 1810 .hw.init = &(struct clk_init_data){
1618 .name = "mali_0_div", 1811 .name = "mali_0_div",
1619 .ops = &clk_regmap_divider_ops, 1812 .ops = &clk_regmap_divider_ops,
1620 .parent_names = (const char *[]){ "mali_0_sel" }, 1813 .parent_hws = (const struct clk_hw *[]) {
1814 &meson8b_mali_0_sel.hw
1815 },
1621 .num_parents = 1, 1816 .num_parents = 1,
1622 .flags = CLK_SET_RATE_PARENT, 1817 .flags = CLK_SET_RATE_PARENT,
1623 }, 1818 },
@@ -1631,7 +1826,9 @@ static struct clk_regmap meson8b_mali_0 = {
1631 .hw.init = &(struct clk_init_data){ 1826 .hw.init = &(struct clk_init_data){
1632 .name = "mali_0", 1827 .name = "mali_0",
1633 .ops = &clk_regmap_gate_ops, 1828 .ops = &clk_regmap_gate_ops,
1634 .parent_names = (const char *[]){ "mali_0_div" }, 1829 .parent_hws = (const struct clk_hw *[]) {
1830 &meson8b_mali_0_div.hw
1831 },
1635 .num_parents = 1, 1832 .num_parents = 1,
1636 .flags = CLK_SET_RATE_PARENT, 1833 .flags = CLK_SET_RATE_PARENT,
1637 }, 1834 },
@@ -1647,8 +1844,8 @@ static struct clk_regmap meson8b_mali_1_sel = {
1647 .hw.init = &(struct clk_init_data){ 1844 .hw.init = &(struct clk_init_data){
1648 .name = "mali_1_sel", 1845 .name = "mali_1_sel",
1649 .ops = &clk_regmap_mux_ops, 1846 .ops = &clk_regmap_mux_ops,
1650 .parent_names = meson8b_mali_0_1_parent_names, 1847 .parent_hws = meson8b_mali_0_1_parent_hws,
1651 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_names), 1848 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_hws),
1652 /* 1849 /*
1653 * Don't propagate rate changes up because the only changeable 1850 * Don't propagate rate changes up because the only changeable
1654 * parents are mpll1 and mpll2 but we need those for audio and 1851 * parents are mpll1 and mpll2 but we need those for audio and
@@ -1668,7 +1865,9 @@ static struct clk_regmap meson8b_mali_1_div = {
1668 .hw.init = &(struct clk_init_data){ 1865 .hw.init = &(struct clk_init_data){
1669 .name = "mali_1_div", 1866 .name = "mali_1_div",
1670 .ops = &clk_regmap_divider_ops, 1867 .ops = &clk_regmap_divider_ops,
1671 .parent_names = (const char *[]){ "mali_1_sel" }, 1868 .parent_hws = (const struct clk_hw *[]) {
1869 &meson8b_mali_1_sel.hw
1870 },
1672 .num_parents = 1, 1871 .num_parents = 1,
1673 .flags = CLK_SET_RATE_PARENT, 1872 .flags = CLK_SET_RATE_PARENT,
1674 }, 1873 },
@@ -1682,7 +1881,9 @@ static struct clk_regmap meson8b_mali_1 = {
1682 .hw.init = &(struct clk_init_data){ 1881 .hw.init = &(struct clk_init_data){
1683 .name = "mali_1", 1882 .name = "mali_1",
1684 .ops = &clk_regmap_gate_ops, 1883 .ops = &clk_regmap_gate_ops,
1685 .parent_names = (const char *[]){ "mali_1_div" }, 1884 .parent_hws = (const struct clk_hw *[]) {
1885 &meson8b_mali_1_div.hw
1886 },
1686 .num_parents = 1, 1887 .num_parents = 1,
1687 .flags = CLK_SET_RATE_PARENT, 1888 .flags = CLK_SET_RATE_PARENT,
1688 }, 1889 },
@@ -1697,7 +1898,10 @@ static struct clk_regmap meson8b_mali = {
1697 .hw.init = &(struct clk_init_data){ 1898 .hw.init = &(struct clk_init_data){
1698 .name = "mali", 1899 .name = "mali",
1699 .ops = &clk_regmap_mux_ops, 1900 .ops = &clk_regmap_mux_ops,
1700 .parent_names = (const char *[]){ "mali_0", "mali_1" }, 1901 .parent_hws = (const struct clk_hw *[]) {
1902 &meson8b_mali_0.hw,
1903 &meson8b_mali_1.hw,
1904 },
1701 .num_parents = 2, 1905 .num_parents = 2,
1702 .flags = CLK_SET_RATE_PARENT, 1906 .flags = CLK_SET_RATE_PARENT,
1703 }, 1907 },
@@ -1740,7 +1944,9 @@ static struct clk_regmap meson8m2_gp_pll_dco = {
1740 .hw.init = &(struct clk_init_data){ 1944 .hw.init = &(struct clk_init_data){
1741 .name = "gp_pll_dco", 1945 .name = "gp_pll_dco",
1742 .ops = &meson_clk_pll_ops, 1946 .ops = &meson_clk_pll_ops,
1743 .parent_names = (const char *[]){ "xtal" }, 1947 .parent_hws = (const struct clk_hw *[]) {
1948 &meson8b_xtal.hw
1949 },
1744 .num_parents = 1, 1950 .num_parents = 1,
1745 }, 1951 },
1746}; 1952};
@@ -1755,18 +1961,26 @@ static struct clk_regmap meson8m2_gp_pll = {
1755 .hw.init = &(struct clk_init_data){ 1961 .hw.init = &(struct clk_init_data){
1756 .name = "gp_pll", 1962 .name = "gp_pll",
1757 .ops = &clk_regmap_divider_ops, 1963 .ops = &clk_regmap_divider_ops,
1758 .parent_names = (const char *[]){ "gp_pll_dco" }, 1964 .parent_hws = (const struct clk_hw *[]) {
1965 &meson8m2_gp_pll_dco.hw
1966 },
1759 .num_parents = 1, 1967 .num_parents = 1,
1760 .flags = CLK_SET_RATE_PARENT, 1968 .flags = CLK_SET_RATE_PARENT,
1761 }, 1969 },
1762}; 1970};
1763 1971
1764static const char * const meson8b_vpu_0_1_parent_names[] = { 1972static const struct clk_hw *meson8b_vpu_0_1_parent_hws[] = {
1765 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7" 1973 &meson8b_fclk_div4.hw,
1974 &meson8b_fclk_div3.hw,
1975 &meson8b_fclk_div5.hw,
1976 &meson8b_fclk_div7.hw,
1766}; 1977};
1767 1978
1768static const char * const mmeson8m2_vpu_0_1_parent_names[] = { 1979static const struct clk_hw *mmeson8m2_vpu_0_1_parent_hws[] = {
1769 "fclk_div4", "fclk_div3", "fclk_div5", "gp_pll" 1980 &meson8b_fclk_div4.hw,
1981 &meson8b_fclk_div3.hw,
1982 &meson8b_fclk_div5.hw,
1983 &meson8m2_gp_pll.hw,
1770}; 1984};
1771 1985
1772static struct clk_regmap meson8b_vpu_0_sel = { 1986static struct clk_regmap meson8b_vpu_0_sel = {
@@ -1778,8 +1992,8 @@ static struct clk_regmap meson8b_vpu_0_sel = {
1778 .hw.init = &(struct clk_init_data){ 1992 .hw.init = &(struct clk_init_data){
1779 .name = "vpu_0_sel", 1993 .name = "vpu_0_sel",
1780 .ops = &clk_regmap_mux_ops, 1994 .ops = &clk_regmap_mux_ops,
1781 .parent_names = meson8b_vpu_0_1_parent_names, 1995 .parent_hws = meson8b_vpu_0_1_parent_hws,
1782 .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_names), 1996 .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
1783 .flags = CLK_SET_RATE_PARENT, 1997 .flags = CLK_SET_RATE_PARENT,
1784 }, 1998 },
1785}; 1999};
@@ -1793,8 +2007,8 @@ static struct clk_regmap meson8m2_vpu_0_sel = {
1793 .hw.init = &(struct clk_init_data){ 2007 .hw.init = &(struct clk_init_data){
1794 .name = "vpu_0_sel", 2008 .name = "vpu_0_sel",
1795 .ops = &clk_regmap_mux_ops, 2009 .ops = &clk_regmap_mux_ops,
1796 .parent_names = mmeson8m2_vpu_0_1_parent_names, 2010 .parent_hws = mmeson8m2_vpu_0_1_parent_hws,
1797 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_names), 2011 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
1798 .flags = CLK_SET_RATE_PARENT, 2012 .flags = CLK_SET_RATE_PARENT,
1799 }, 2013 },
1800}; 2014};
@@ -1808,7 +2022,17 @@ static struct clk_regmap meson8b_vpu_0_div = {
1808 .hw.init = &(struct clk_init_data){ 2022 .hw.init = &(struct clk_init_data){
1809 .name = "vpu_0_div", 2023 .name = "vpu_0_div",
1810 .ops = &clk_regmap_divider_ops, 2024 .ops = &clk_regmap_divider_ops,
1811 .parent_names = (const char *[]){ "vpu_0_sel" }, 2025 .parent_data = &(const struct clk_parent_data) {
2026 /*
2027 * Note:
2028 * meson8b and meson8m2 have different vpu_0_sels (with
2029 * different struct clk_hw). We fallback to the global
2030 * naming string mechanism so vpu_0_div picks up the
2031 * appropriate one.
2032 */
2033 .name = "vpu_0_sel",
2034 .index = -1,
2035 },
1812 .num_parents = 1, 2036 .num_parents = 1,
1813 .flags = CLK_SET_RATE_PARENT, 2037 .flags = CLK_SET_RATE_PARENT,
1814 }, 2038 },
@@ -1822,7 +2046,9 @@ static struct clk_regmap meson8b_vpu_0 = {
1822 .hw.init = &(struct clk_init_data) { 2046 .hw.init = &(struct clk_init_data) {
1823 .name = "vpu_0", 2047 .name = "vpu_0",
1824 .ops = &clk_regmap_gate_ops, 2048 .ops = &clk_regmap_gate_ops,
1825 .parent_names = (const char *[]){ "vpu_0_div" }, 2049 .parent_hws = (const struct clk_hw *[]) {
2050 &meson8b_vpu_0_div.hw
2051 },
1826 .num_parents = 1, 2052 .num_parents = 1,
1827 .flags = CLK_SET_RATE_PARENT, 2053 .flags = CLK_SET_RATE_PARENT,
1828 }, 2054 },
@@ -1837,8 +2063,8 @@ static struct clk_regmap meson8b_vpu_1_sel = {
1837 .hw.init = &(struct clk_init_data){ 2063 .hw.init = &(struct clk_init_data){
1838 .name = "vpu_1_sel", 2064 .name = "vpu_1_sel",
1839 .ops = &clk_regmap_mux_ops, 2065 .ops = &clk_regmap_mux_ops,
1840 .parent_names = meson8b_vpu_0_1_parent_names, 2066 .parent_hws = meson8b_vpu_0_1_parent_hws,
1841 .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_names), 2067 .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
1842 .flags = CLK_SET_RATE_PARENT, 2068 .flags = CLK_SET_RATE_PARENT,
1843 }, 2069 },
1844}; 2070};
@@ -1852,8 +2078,8 @@ static struct clk_regmap meson8m2_vpu_1_sel = {
1852 .hw.init = &(struct clk_init_data){ 2078 .hw.init = &(struct clk_init_data){
1853 .name = "vpu_1_sel", 2079 .name = "vpu_1_sel",
1854 .ops = &clk_regmap_mux_ops, 2080 .ops = &clk_regmap_mux_ops,
1855 .parent_names = mmeson8m2_vpu_0_1_parent_names, 2081 .parent_hws = mmeson8m2_vpu_0_1_parent_hws,
1856 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_names), 2082 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
1857 .flags = CLK_SET_RATE_PARENT, 2083 .flags = CLK_SET_RATE_PARENT,
1858 }, 2084 },
1859}; 2085};
@@ -1867,7 +2093,17 @@ static struct clk_regmap meson8b_vpu_1_div = {
1867 .hw.init = &(struct clk_init_data){ 2093 .hw.init = &(struct clk_init_data){
1868 .name = "vpu_1_div", 2094 .name = "vpu_1_div",
1869 .ops = &clk_regmap_divider_ops, 2095 .ops = &clk_regmap_divider_ops,
1870 .parent_names = (const char *[]){ "vpu_1_sel" }, 2096 .parent_data = &(const struct clk_parent_data) {
2097 /*
2098 * Note:
2099 * meson8b and meson8m2 have different vpu_1_sels (with
2100 * different struct clk_hw). We fallback to the global
2101 * naming string mechanism so vpu_1_div picks up the
2102 * appropriate one.
2103 */
2104 .name = "vpu_1_sel",
2105 .index = -1,
2106 },
1871 .num_parents = 1, 2107 .num_parents = 1,
1872 .flags = CLK_SET_RATE_PARENT, 2108 .flags = CLK_SET_RATE_PARENT,
1873 }, 2109 },
@@ -1881,7 +2117,9 @@ static struct clk_regmap meson8b_vpu_1 = {
1881 .hw.init = &(struct clk_init_data) { 2117 .hw.init = &(struct clk_init_data) {
1882 .name = "vpu_1", 2118 .name = "vpu_1",
1883 .ops = &clk_regmap_gate_ops, 2119 .ops = &clk_regmap_gate_ops,
1884 .parent_names = (const char *[]){ "vpu_1_div" }, 2120 .parent_hws = (const struct clk_hw *[]) {
2121 &meson8b_vpu_1_div.hw
2122 },
1885 .num_parents = 1, 2123 .num_parents = 1,
1886 .flags = CLK_SET_RATE_PARENT, 2124 .flags = CLK_SET_RATE_PARENT,
1887 }, 2125 },
@@ -1896,14 +2134,22 @@ static struct clk_regmap meson8b_vpu = {
1896 .hw.init = &(struct clk_init_data){ 2134 .hw.init = &(struct clk_init_data){
1897 .name = "vpu", 2135 .name = "vpu",
1898 .ops = &clk_regmap_mux_ops, 2136 .ops = &clk_regmap_mux_ops,
1899 .parent_names = (const char *[]){ "vpu_0", "vpu_1" }, 2137 .parent_hws = (const struct clk_hw *[]) {
2138 &meson8b_vpu_0.hw,
2139 &meson8b_vpu_1.hw,
2140 },
1900 .num_parents = 2, 2141 .num_parents = 2,
1901 .flags = CLK_SET_RATE_NO_REPARENT, 2142 .flags = CLK_SET_RATE_NO_REPARENT,
1902 }, 2143 },
1903}; 2144};
1904 2145
1905static const char * const meson8b_vdec_parent_names[] = { 2146static const struct clk_hw *meson8b_vdec_parent_hws[] = {
1906 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "mpll2", "mpll1" 2147 &meson8b_fclk_div4.hw,
2148 &meson8b_fclk_div3.hw,
2149 &meson8b_fclk_div5.hw,
2150 &meson8b_fclk_div7.hw,
2151 &meson8b_mpll2.hw,
2152 &meson8b_mpll1.hw,
1907}; 2153};
1908 2154
1909static struct clk_regmap meson8b_vdec_1_sel = { 2155static struct clk_regmap meson8b_vdec_1_sel = {
@@ -1916,8 +2162,8 @@ static struct clk_regmap meson8b_vdec_1_sel = {
1916 .hw.init = &(struct clk_init_data){ 2162 .hw.init = &(struct clk_init_data){
1917 .name = "vdec_1_sel", 2163 .name = "vdec_1_sel",
1918 .ops = &clk_regmap_mux_ops, 2164 .ops = &clk_regmap_mux_ops,
1919 .parent_names = meson8b_vdec_parent_names, 2165 .parent_hws = meson8b_vdec_parent_hws,
1920 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_names), 2166 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
1921 .flags = CLK_SET_RATE_PARENT, 2167 .flags = CLK_SET_RATE_PARENT,
1922 }, 2168 },
1923}; 2169};
@@ -1932,7 +2178,9 @@ static struct clk_regmap meson8b_vdec_1_1_div = {
1932 .hw.init = &(struct clk_init_data){ 2178 .hw.init = &(struct clk_init_data){
1933 .name = "vdec_1_1_div", 2179 .name = "vdec_1_1_div",
1934 .ops = &clk_regmap_divider_ops, 2180 .ops = &clk_regmap_divider_ops,
1935 .parent_names = (const char *[]){ "vdec_1_sel" }, 2181 .parent_hws = (const struct clk_hw *[]) {
2182 &meson8b_vdec_1_sel.hw
2183 },
1936 .num_parents = 1, 2184 .num_parents = 1,
1937 .flags = CLK_SET_RATE_PARENT, 2185 .flags = CLK_SET_RATE_PARENT,
1938 }, 2186 },
@@ -1946,7 +2194,9 @@ static struct clk_regmap meson8b_vdec_1_1 = {
1946 .hw.init = &(struct clk_init_data) { 2194 .hw.init = &(struct clk_init_data) {
1947 .name = "vdec_1_1", 2195 .name = "vdec_1_1",
1948 .ops = &clk_regmap_gate_ops, 2196 .ops = &clk_regmap_gate_ops,
1949 .parent_names = (const char *[]){ "vdec_1_1_div" }, 2197 .parent_hws = (const struct clk_hw *[]) {
2198 &meson8b_vdec_1_1_div.hw
2199 },
1950 .num_parents = 1, 2200 .num_parents = 1,
1951 .flags = CLK_SET_RATE_PARENT, 2201 .flags = CLK_SET_RATE_PARENT,
1952 }, 2202 },
@@ -1962,7 +2212,9 @@ static struct clk_regmap meson8b_vdec_1_2_div = {
1962 .hw.init = &(struct clk_init_data){ 2212 .hw.init = &(struct clk_init_data){
1963 .name = "vdec_1_2_div", 2213 .name = "vdec_1_2_div",
1964 .ops = &clk_regmap_divider_ops, 2214 .ops = &clk_regmap_divider_ops,
1965 .parent_names = (const char *[]){ "vdec_1_sel" }, 2215 .parent_hws = (const struct clk_hw *[]) {
2216 &meson8b_vdec_1_sel.hw
2217 },
1966 .num_parents = 1, 2218 .num_parents = 1,
1967 .flags = CLK_SET_RATE_PARENT, 2219 .flags = CLK_SET_RATE_PARENT,
1968 }, 2220 },
@@ -1976,7 +2228,9 @@ static struct clk_regmap meson8b_vdec_1_2 = {
1976 .hw.init = &(struct clk_init_data) { 2228 .hw.init = &(struct clk_init_data) {
1977 .name = "vdec_1_2", 2229 .name = "vdec_1_2",
1978 .ops = &clk_regmap_gate_ops, 2230 .ops = &clk_regmap_gate_ops,
1979 .parent_names = (const char *[]){ "vdec_1_2_div" }, 2231 .parent_hws = (const struct clk_hw *[]) {
2232 &meson8b_vdec_1_2_div.hw
2233 },
1980 .num_parents = 1, 2234 .num_parents = 1,
1981 .flags = CLK_SET_RATE_PARENT, 2235 .flags = CLK_SET_RATE_PARENT,
1982 }, 2236 },
@@ -1992,7 +2246,10 @@ static struct clk_regmap meson8b_vdec_1 = {
1992 .hw.init = &(struct clk_init_data){ 2246 .hw.init = &(struct clk_init_data){
1993 .name = "vdec_1", 2247 .name = "vdec_1",
1994 .ops = &clk_regmap_mux_ops, 2248 .ops = &clk_regmap_mux_ops,
1995 .parent_names = (const char *[]){ "vdec_1_1", "vdec_1_2" }, 2249 .parent_hws = (const struct clk_hw *[]) {
2250 &meson8b_vdec_1_1.hw,
2251 &meson8b_vdec_1_2.hw,
2252 },
1996 .num_parents = 2, 2253 .num_parents = 2,
1997 .flags = CLK_SET_RATE_PARENT, 2254 .flags = CLK_SET_RATE_PARENT,
1998 }, 2255 },
@@ -2008,8 +2265,8 @@ static struct clk_regmap meson8b_vdec_hcodec_sel = {
2008 .hw.init = &(struct clk_init_data){ 2265 .hw.init = &(struct clk_init_data){
2009 .name = "vdec_hcodec_sel", 2266 .name = "vdec_hcodec_sel",
2010 .ops = &clk_regmap_mux_ops, 2267 .ops = &clk_regmap_mux_ops,
2011 .parent_names = meson8b_vdec_parent_names, 2268 .parent_hws = meson8b_vdec_parent_hws,
2012 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_names), 2269 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2013 .flags = CLK_SET_RATE_PARENT, 2270 .flags = CLK_SET_RATE_PARENT,
2014 }, 2271 },
2015}; 2272};
@@ -2024,7 +2281,9 @@ static struct clk_regmap meson8b_vdec_hcodec_div = {
2024 .hw.init = &(struct clk_init_data){ 2281 .hw.init = &(struct clk_init_data){
2025 .name = "vdec_hcodec_div", 2282 .name = "vdec_hcodec_div",
2026 .ops = &clk_regmap_divider_ops, 2283 .ops = &clk_regmap_divider_ops,
2027 .parent_names = (const char *[]){ "vdec_hcodec_sel" }, 2284 .parent_hws = (const struct clk_hw *[]) {
2285 &meson8b_vdec_hcodec_sel.hw
2286 },
2028 .num_parents = 1, 2287 .num_parents = 1,
2029 .flags = CLK_SET_RATE_PARENT, 2288 .flags = CLK_SET_RATE_PARENT,
2030 }, 2289 },
@@ -2038,7 +2297,9 @@ static struct clk_regmap meson8b_vdec_hcodec = {
2038 .hw.init = &(struct clk_init_data) { 2297 .hw.init = &(struct clk_init_data) {
2039 .name = "vdec_hcodec", 2298 .name = "vdec_hcodec",
2040 .ops = &clk_regmap_gate_ops, 2299 .ops = &clk_regmap_gate_ops,
2041 .parent_names = (const char *[]){ "vdec_hcodec_div" }, 2300 .parent_hws = (const struct clk_hw *[]) {
2301 &meson8b_vdec_hcodec_div.hw
2302 },
2042 .num_parents = 1, 2303 .num_parents = 1,
2043 .flags = CLK_SET_RATE_PARENT, 2304 .flags = CLK_SET_RATE_PARENT,
2044 }, 2305 },
@@ -2054,8 +2315,8 @@ static struct clk_regmap meson8b_vdec_2_sel = {
2054 .hw.init = &(struct clk_init_data){ 2315 .hw.init = &(struct clk_init_data){
2055 .name = "vdec_2_sel", 2316 .name = "vdec_2_sel",
2056 .ops = &clk_regmap_mux_ops, 2317 .ops = &clk_regmap_mux_ops,
2057 .parent_names = meson8b_vdec_parent_names, 2318 .parent_hws = meson8b_vdec_parent_hws,
2058 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_names), 2319 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2059 .flags = CLK_SET_RATE_PARENT, 2320 .flags = CLK_SET_RATE_PARENT,
2060 }, 2321 },
2061}; 2322};
@@ -2070,7 +2331,9 @@ static struct clk_regmap meson8b_vdec_2_div = {
2070 .hw.init = &(struct clk_init_data){ 2331 .hw.init = &(struct clk_init_data){
2071 .name = "vdec_2_div", 2332 .name = "vdec_2_div",
2072 .ops = &clk_regmap_divider_ops, 2333 .ops = &clk_regmap_divider_ops,
2073 .parent_names = (const char *[]){ "vdec_2_sel" }, 2334 .parent_hws = (const struct clk_hw *[]) {
2335 &meson8b_vdec_2_sel.hw
2336 },
2074 .num_parents = 1, 2337 .num_parents = 1,
2075 .flags = CLK_SET_RATE_PARENT, 2338 .flags = CLK_SET_RATE_PARENT,
2076 }, 2339 },
@@ -2084,7 +2347,9 @@ static struct clk_regmap meson8b_vdec_2 = {
2084 .hw.init = &(struct clk_init_data) { 2347 .hw.init = &(struct clk_init_data) {
2085 .name = "vdec_2", 2348 .name = "vdec_2",
2086 .ops = &clk_regmap_gate_ops, 2349 .ops = &clk_regmap_gate_ops,
2087 .parent_names = (const char *[]){ "vdec_2_div" }, 2350 .parent_hws = (const struct clk_hw *[]) {
2351 &meson8b_vdec_2_div.hw
2352 },
2088 .num_parents = 1, 2353 .num_parents = 1,
2089 .flags = CLK_SET_RATE_PARENT, 2354 .flags = CLK_SET_RATE_PARENT,
2090 }, 2355 },
@@ -2100,8 +2365,8 @@ static struct clk_regmap meson8b_vdec_hevc_sel = {
2100 .hw.init = &(struct clk_init_data){ 2365 .hw.init = &(struct clk_init_data){
2101 .name = "vdec_hevc_sel", 2366 .name = "vdec_hevc_sel",
2102 .ops = &clk_regmap_mux_ops, 2367 .ops = &clk_regmap_mux_ops,
2103 .parent_names = meson8b_vdec_parent_names, 2368 .parent_hws = meson8b_vdec_parent_hws,
2104 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_names), 2369 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2105 .flags = CLK_SET_RATE_PARENT, 2370 .flags = CLK_SET_RATE_PARENT,
2106 }, 2371 },
2107}; 2372};
@@ -2116,7 +2381,9 @@ static struct clk_regmap meson8b_vdec_hevc_div = {
2116 .hw.init = &(struct clk_init_data){ 2381 .hw.init = &(struct clk_init_data){
2117 .name = "vdec_hevc_div", 2382 .name = "vdec_hevc_div",
2118 .ops = &clk_regmap_divider_ops, 2383 .ops = &clk_regmap_divider_ops,
2119 .parent_names = (const char *[]){ "vdec_hevc_sel" }, 2384 .parent_hws = (const struct clk_hw *[]) {
2385 &meson8b_vdec_hevc_sel.hw
2386 },
2120 .num_parents = 1, 2387 .num_parents = 1,
2121 .flags = CLK_SET_RATE_PARENT, 2388 .flags = CLK_SET_RATE_PARENT,
2122 }, 2389 },
@@ -2130,7 +2397,9 @@ static struct clk_regmap meson8b_vdec_hevc_en = {
2130 .hw.init = &(struct clk_init_data) { 2397 .hw.init = &(struct clk_init_data) {
2131 .name = "vdec_hevc_en", 2398 .name = "vdec_hevc_en",
2132 .ops = &clk_regmap_gate_ops, 2399 .ops = &clk_regmap_gate_ops,
2133 .parent_names = (const char *[]){ "vdec_hevc_div" }, 2400 .parent_hws = (const struct clk_hw *[]) {
2401 &meson8b_vdec_hevc_div.hw
2402 },
2134 .num_parents = 1, 2403 .num_parents = 1,
2135 .flags = CLK_SET_RATE_PARENT, 2404 .flags = CLK_SET_RATE_PARENT,
2136 }, 2405 },
@@ -2147,15 +2416,19 @@ static struct clk_regmap meson8b_vdec_hevc = {
2147 .name = "vdec_hevc", 2416 .name = "vdec_hevc",
2148 .ops = &clk_regmap_mux_ops, 2417 .ops = &clk_regmap_mux_ops,
2149 /* TODO: The second parent is currently unknown */ 2418 /* TODO: The second parent is currently unknown */
2150 .parent_names = (const char *[]){ "vdec_hevc_en" }, 2419 .parent_hws = (const struct clk_hw *[]) {
2420 &meson8b_vdec_hevc_en.hw
2421 },
2151 .num_parents = 1, 2422 .num_parents = 1,
2152 .flags = CLK_SET_RATE_PARENT, 2423 .flags = CLK_SET_RATE_PARENT,
2153 }, 2424 },
2154}; 2425};
2155 2426
2156/* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */ 2427/* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
2157static const char * const meson8b_cts_amclk_parent_names[] = { 2428static const struct clk_hw *meson8b_cts_amclk_parent_hws[] = {
2158 "mpll0", "mpll1", "mpll2" 2429 &meson8b_mpll0.hw,
2430 &meson8b_mpll1.hw,
2431 &meson8b_mpll2.hw
2159}; 2432};
2160 2433
2161static u32 meson8b_cts_amclk_mux_table[] = { 1, 2, 3 }; 2434static u32 meson8b_cts_amclk_mux_table[] = { 1, 2, 3 };
@@ -2171,8 +2444,8 @@ static struct clk_regmap meson8b_cts_amclk_sel = {
2171 .hw.init = &(struct clk_init_data){ 2444 .hw.init = &(struct clk_init_data){
2172 .name = "cts_amclk_sel", 2445 .name = "cts_amclk_sel",
2173 .ops = &clk_regmap_mux_ops, 2446 .ops = &clk_regmap_mux_ops,
2174 .parent_names = meson8b_cts_amclk_parent_names, 2447 .parent_hws = meson8b_cts_amclk_parent_hws,
2175 .num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_names), 2448 .num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_hws),
2176 }, 2449 },
2177}; 2450};
2178 2451
@@ -2186,7 +2459,9 @@ static struct clk_regmap meson8b_cts_amclk_div = {
2186 .hw.init = &(struct clk_init_data){ 2459 .hw.init = &(struct clk_init_data){
2187 .name = "cts_amclk_div", 2460 .name = "cts_amclk_div",
2188 .ops = &clk_regmap_divider_ops, 2461 .ops = &clk_regmap_divider_ops,
2189 .parent_names = (const char *[]){ "cts_amclk_sel" }, 2462 .parent_hws = (const struct clk_hw *[]) {
2463 &meson8b_cts_amclk_sel.hw
2464 },
2190 .num_parents = 1, 2465 .num_parents = 1,
2191 .flags = CLK_SET_RATE_PARENT, 2466 .flags = CLK_SET_RATE_PARENT,
2192 }, 2467 },
@@ -2200,15 +2475,19 @@ static struct clk_regmap meson8b_cts_amclk = {
2200 .hw.init = &(struct clk_init_data){ 2475 .hw.init = &(struct clk_init_data){
2201 .name = "cts_amclk", 2476 .name = "cts_amclk",
2202 .ops = &clk_regmap_gate_ops, 2477 .ops = &clk_regmap_gate_ops,
2203 .parent_names = (const char *[]){ "cts_amclk_div" }, 2478 .parent_hws = (const struct clk_hw *[]) {
2479 &meson8b_cts_amclk_div.hw
2480 },
2204 .num_parents = 1, 2481 .num_parents = 1,
2205 .flags = CLK_SET_RATE_PARENT, 2482 .flags = CLK_SET_RATE_PARENT,
2206 }, 2483 },
2207}; 2484};
2208 2485
2209/* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */ 2486/* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
2210static const char * const meson8b_cts_mclk_i958_parent_names[] = { 2487static const struct clk_hw *meson8b_cts_mclk_i958_parent_hws[] = {
2211 "mpll0", "mpll1", "mpll2" 2488 &meson8b_mpll0.hw,
2489 &meson8b_mpll1.hw,
2490 &meson8b_mpll2.hw
2212}; 2491};
2213 2492
2214static u32 meson8b_cts_mclk_i958_mux_table[] = { 1, 2, 3 }; 2493static u32 meson8b_cts_mclk_i958_mux_table[] = { 1, 2, 3 };
@@ -2224,8 +2503,8 @@ static struct clk_regmap meson8b_cts_mclk_i958_sel = {
2224 .hw.init = &(struct clk_init_data) { 2503 .hw.init = &(struct clk_init_data) {
2225 .name = "cts_mclk_i958_sel", 2504 .name = "cts_mclk_i958_sel",
2226 .ops = &clk_regmap_mux_ops, 2505 .ops = &clk_regmap_mux_ops,
2227 .parent_names = meson8b_cts_mclk_i958_parent_names, 2506 .parent_hws = meson8b_cts_mclk_i958_parent_hws,
2228 .num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_names), 2507 .num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_hws),
2229 }, 2508 },
2230}; 2509};
2231 2510
@@ -2239,7 +2518,9 @@ static struct clk_regmap meson8b_cts_mclk_i958_div = {
2239 .hw.init = &(struct clk_init_data) { 2518 .hw.init = &(struct clk_init_data) {
2240 .name = "cts_mclk_i958_div", 2519 .name = "cts_mclk_i958_div",
2241 .ops = &clk_regmap_divider_ops, 2520 .ops = &clk_regmap_divider_ops,
2242 .parent_names = (const char *[]){ "cts_mclk_i958_sel" }, 2521 .parent_hws = (const struct clk_hw *[]) {
2522 &meson8b_cts_mclk_i958_sel.hw
2523 },
2243 .num_parents = 1, 2524 .num_parents = 1,
2244 .flags = CLK_SET_RATE_PARENT, 2525 .flags = CLK_SET_RATE_PARENT,
2245 }, 2526 },
@@ -2253,7 +2534,9 @@ static struct clk_regmap meson8b_cts_mclk_i958 = {
2253 .hw.init = &(struct clk_init_data){ 2534 .hw.init = &(struct clk_init_data){
2254 .name = "cts_mclk_i958", 2535 .name = "cts_mclk_i958",
2255 .ops = &clk_regmap_gate_ops, 2536 .ops = &clk_regmap_gate_ops,
2256 .parent_names = (const char *[]){ "cts_mclk_i958_div" }, 2537 .parent_hws = (const struct clk_hw *[]) {
2538 &meson8b_cts_mclk_i958_div.hw
2539 },
2257 .num_parents = 1, 2540 .num_parents = 1,
2258 .flags = CLK_SET_RATE_PARENT, 2541 .flags = CLK_SET_RATE_PARENT,
2259 }, 2542 },
@@ -2268,8 +2551,10 @@ static struct clk_regmap meson8b_cts_i958 = {
2268 .hw.init = &(struct clk_init_data){ 2551 .hw.init = &(struct clk_init_data){
2269 .name = "cts_i958", 2552 .name = "cts_i958",
2270 .ops = &clk_regmap_mux_ops, 2553 .ops = &clk_regmap_mux_ops,
2271 .parent_names = (const char *[]){ "cts_amclk", 2554 .parent_hws = (const struct clk_hw *[]) {
2272 "cts_mclk_i958" }, 2555 &meson8b_cts_amclk.hw,
2556 &meson8b_cts_mclk_i958.hw
2557 },
2273 .num_parents = 2, 2558 .num_parents = 2,
2274 /* 2559 /*
2275 * The parent is specific to origin of the audio data. Let the 2560 * The parent is specific to origin of the audio data. Let the
@@ -2279,6 +2564,9 @@ static struct clk_regmap meson8b_cts_i958 = {
2279 }, 2564 },
2280}; 2565};
2281 2566
2567#define MESON_GATE(_name, _reg, _bit) \
2568 MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw)
2569
2282/* Everything Else (EE) domain gates */ 2570/* Everything Else (EE) domain gates */
2283 2571
2284static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0); 2572static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index b09f6ded0a30..415e6906a113 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -8,6 +8,9 @@ config MVEBU_CLK_CPU
8config MVEBU_CLK_COREDIV 8config MVEBU_CLK_COREDIV
9 bool 9 bool
10 10
11config ARMADA_AP_CP_HELPER
12 bool
13
11config ARMADA_370_CLK 14config ARMADA_370_CLK
12 bool 15 bool
13 select MVEBU_CLK_COMMON 16 select MVEBU_CLK_COMMON
@@ -35,9 +38,14 @@ config ARMADA_XP_CLK
35 38
36config ARMADA_AP806_SYSCON 39config ARMADA_AP806_SYSCON
37 bool 40 bool
41 select ARMADA_AP_CP_HELPER
42
43config ARMADA_AP_CPU_CLK
44 bool
38 45
39config ARMADA_CP110_SYSCON 46config ARMADA_CP110_SYSCON
40 bool 47 bool
48 select ARMADA_AP_CP_HELPER
41 49
42config DOVE_CLK 50config DOVE_CLK
43 bool 51 bool
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 93ac3685271f..04464cef0f06 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -2,6 +2,7 @@
2obj-$(CONFIG_MVEBU_CLK_COMMON) += common.o 2obj-$(CONFIG_MVEBU_CLK_COMMON) += common.o
3obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o 3obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
4obj-$(CONFIG_MVEBU_CLK_COREDIV) += clk-corediv.o 4obj-$(CONFIG_MVEBU_CLK_COREDIV) += clk-corediv.o
5obj-$(CONFIG_ARMADA_AP_CP_HELPER) += armada_ap_cp_helper.o
5 6
6obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o 7obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o
7obj-$(CONFIG_ARMADA_375_CLK) += armada-375.o 8obj-$(CONFIG_ARMADA_375_CLK) += armada-375.o
@@ -12,6 +13,7 @@ obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-tbg.o
12obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-periph.o 13obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-periph.o
13obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o mv98dx3236.o 14obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o mv98dx3236.o
14obj-$(CONFIG_ARMADA_AP806_SYSCON) += ap806-system-controller.o 15obj-$(CONFIG_ARMADA_AP806_SYSCON) += ap806-system-controller.o
16obj-$(CONFIG_ARMADA_AP_CPU_CLK) += ap-cpu-clk.o
15obj-$(CONFIG_ARMADA_CP110_SYSCON) += cp110-system-controller.o 17obj-$(CONFIG_ARMADA_CP110_SYSCON) += cp110-system-controller.o
16obj-$(CONFIG_DOVE_CLK) += dove.o dove-divider.o 18obj-$(CONFIG_DOVE_CLK) += dove.o dove-divider.o
17obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o 19obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o
diff --git a/drivers/clk/mvebu/ap-cpu-clk.c b/drivers/clk/mvebu/ap-cpu-clk.c
new file mode 100644
index 000000000000..af5e5acad370
--- /dev/null
+++ b/drivers/clk/mvebu/ap-cpu-clk.c
@@ -0,0 +1,356 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Marvell Armada AP CPU Clock Controller
4 *
5 * Copyright (C) 2018 Marvell
6 *
7 * Omri Itach <omrii@marvell.com>
8 * Gregory Clement <gregory.clement@bootlin.com>
9 */
10
11#define pr_fmt(fmt) "ap-cpu-clk: " fmt
12
13#include <linux/clk-provider.h>
14#include <linux/clk.h>
15#include <linux/mfd/syscon.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_platform.h>
19#include <linux/platform_device.h>
20#include <linux/regmap.h>
21#include "armada_ap_cp_helper.h"
22
23#define AP806_CPU_CLUSTER0 0
24#define AP806_CPU_CLUSTER1 1
25#define AP806_CPUS_PER_CLUSTER 2
26#define APN806_CPU1_MASK 0x1
27
28#define APN806_CLUSTER_NUM_OFFSET 8
29#define APN806_CLUSTER_NUM_MASK BIT(APN806_CLUSTER_NUM_OFFSET)
30
31#define APN806_MAX_DIVIDER 32
32
33/**
34 * struct cpu_dfs_regs: CPU DFS register mapping
35 * @divider_reg: full integer ratio from PLL frequency to CPU clock frequency
36 * @force_reg: request to force new ratio regardless of relation to other clocks
37 * @ratio_reg: central request to switch ratios
38 */
39struct cpu_dfs_regs {
40 unsigned int divider_reg;
41 unsigned int force_reg;
42 unsigned int ratio_reg;
43 unsigned int ratio_state_reg;
44 unsigned int divider_mask;
45 unsigned int cluster_offset;
46 unsigned int force_mask;
47 int divider_offset;
48 int divider_ratio;
49 int ratio_offset;
50 int ratio_state_offset;
51 int ratio_state_cluster_offset;
52};
53
54/* AP806 CPU DFS register mapping*/
55#define AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET 0x278
56#define AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET 0x280
57#define AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET 0x284
58#define AP806_CA72MP2_0_PLL_SR_REG_OFFSET 0xC94
59
60#define AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET 0x14
61#define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET 0
62#define AP806_PLL_CR_CPU_CLK_DIV_RATIO 0
63#define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \
64 (0x3f << AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
65#define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET 24
66#define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK \
67 (0x1 << AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET)
68#define AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET 16
69#define AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET 0
70#define AP806_CA72MP2_0_PLL_RATIO_STATE 11
71
72#define STATUS_POLL_PERIOD_US 1
73#define STATUS_POLL_TIMEOUT_US 1000000
74
75#define to_ap_cpu_clk(_hw) container_of(_hw, struct ap_cpu_clk, hw)
76
77static const struct cpu_dfs_regs ap806_dfs_regs = {
78 .divider_reg = AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET,
79 .force_reg = AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET,
80 .ratio_reg = AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET,
81 .ratio_state_reg = AP806_CA72MP2_0_PLL_SR_REG_OFFSET,
82 .divider_mask = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK,
83 .cluster_offset = AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET,
84 .force_mask = AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK,
85 .divider_offset = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET,
86 .divider_ratio = AP806_PLL_CR_CPU_CLK_DIV_RATIO,
87 .ratio_offset = AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET,
88 .ratio_state_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET,
89 .ratio_state_cluster_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET,
90};
91
92/* AP807 CPU DFS register mapping */
93#define AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET 0x278
94#define AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET 0x27c
95#define AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET 0xc98
96#define AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET 0x8
97#define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET 18
98#define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \
99 (0x3f << AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
100#define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET 12
101#define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK \
102 (0x3f << AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET)
103#define AP807_PLL_CR_CPU_CLK_DIV_RATIO 3
104#define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET 0
105#define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK \
106 (0x3 << AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET)
107#define AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET 6
108#define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET 20
109#define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET 3
110
111static const struct cpu_dfs_regs ap807_dfs_regs = {
112 .divider_reg = AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET,
113 .force_reg = AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET,
114 .ratio_reg = AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET,
115 .ratio_state_reg = AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET,
116 .divider_mask = AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK,
117 .cluster_offset = AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET,
118 .force_mask = AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK,
119 .divider_offset = AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET,
120 .divider_ratio = AP807_PLL_CR_CPU_CLK_DIV_RATIO,
121 .ratio_offset = AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET,
122 .ratio_state_offset = AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET,
123 .ratio_state_cluster_offset =
124 AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET
125};
126
127/*
128 * struct ap806_clk: CPU cluster clock controller instance
129 * @cluster: Cluster clock controller index
130 * @clk_name: Cluster clock controller name
131 * @dev : Cluster clock device
132 * @hw: HW specific structure of Cluster clock controller
133 * @pll_cr_base: CA72MP2 Register base (Device Sample at Reset register)
134 */
135struct ap_cpu_clk {
136 unsigned int cluster;
137 const char *clk_name;
138 struct device *dev;
139 struct clk_hw hw;
140 struct regmap *pll_cr_base;
141 const struct cpu_dfs_regs *pll_regs;
142};
143
144static unsigned long ap_cpu_clk_recalc_rate(struct clk_hw *hw,
145 unsigned long parent_rate)
146{
147 struct ap_cpu_clk *clk = to_ap_cpu_clk(hw);
148 unsigned int cpu_clkdiv_reg;
149 int cpu_clkdiv_ratio;
150
151 cpu_clkdiv_reg = clk->pll_regs->divider_reg +
152 (clk->cluster * clk->pll_regs->cluster_offset);
153 regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &cpu_clkdiv_ratio);
154 cpu_clkdiv_ratio &= clk->pll_regs->divider_mask;
155 cpu_clkdiv_ratio >>= clk->pll_regs->divider_offset;
156
157 return parent_rate / cpu_clkdiv_ratio;
158}
159
160static int ap_cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
161 unsigned long parent_rate)
162{
163 struct ap_cpu_clk *clk = to_ap_cpu_clk(hw);
164 int ret, reg, divider = parent_rate / rate;
165 unsigned int cpu_clkdiv_reg, cpu_force_reg, cpu_ratio_reg, stable_bit;
166
167 cpu_clkdiv_reg = clk->pll_regs->divider_reg +
168 (clk->cluster * clk->pll_regs->cluster_offset);
169 cpu_force_reg = clk->pll_regs->force_reg +
170 (clk->cluster * clk->pll_regs->cluster_offset);
171 cpu_ratio_reg = clk->pll_regs->ratio_reg +
172 (clk->cluster * clk->pll_regs->cluster_offset);
173
174 regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &reg);
175 reg &= ~(clk->pll_regs->divider_mask);
176 reg |= (divider << clk->pll_regs->divider_offset);
177
178 /*
179 * AP807 CPU divider has two channels with ratio 1:3 and divider_ratio
180 * is 1. Otherwise, in the case of the AP806, divider_ratio is 0.
181 */
182 if (clk->pll_regs->divider_ratio) {
183 reg &= ~(AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK);
184 reg |= ((divider * clk->pll_regs->divider_ratio) <<
185 AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET);
186 }
187 regmap_write(clk->pll_cr_base, cpu_clkdiv_reg, reg);
188
189
190 regmap_update_bits(clk->pll_cr_base, cpu_force_reg,
191 clk->pll_regs->force_mask,
192 clk->pll_regs->force_mask);
193
194 regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg,
195 BIT(clk->pll_regs->ratio_offset),
196 BIT(clk->pll_regs->ratio_offset));
197
198 stable_bit = BIT(clk->pll_regs->ratio_state_offset +
199 clk->cluster *
200 clk->pll_regs->ratio_state_cluster_offset),
201 ret = regmap_read_poll_timeout(clk->pll_cr_base,
202 clk->pll_regs->ratio_state_reg, reg,
203 reg & stable_bit, STATUS_POLL_PERIOD_US,
204 STATUS_POLL_TIMEOUT_US);
205 if (ret)
206 return ret;
207
208 regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg,
209 BIT(clk->pll_regs->ratio_offset), 0);
210
211 return 0;
212}
213
214static long ap_cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
215 unsigned long *parent_rate)
216{
217 int divider = *parent_rate / rate;
218
219 divider = min(divider, APN806_MAX_DIVIDER);
220
221 return *parent_rate / divider;
222}
223
224static const struct clk_ops ap_cpu_clk_ops = {
225 .recalc_rate = ap_cpu_clk_recalc_rate,
226 .round_rate = ap_cpu_clk_round_rate,
227 .set_rate = ap_cpu_clk_set_rate,
228};
229
230static int ap_cpu_clock_probe(struct platform_device *pdev)
231{
232 int ret, nclusters = 0, cluster_index = 0;
233 struct device *dev = &pdev->dev;
234 struct device_node *dn, *np = dev->of_node;
235 struct clk_hw_onecell_data *ap_cpu_data;
236 struct ap_cpu_clk *ap_cpu_clk;
237 struct regmap *regmap;
238
239 regmap = syscon_node_to_regmap(np->parent);
240 if (IS_ERR(regmap)) {
241 pr_err("cannot get pll_cr_base regmap\n");
242 return PTR_ERR(regmap);
243 }
244
245 /*
246 * AP806 has 4 cpus and DFS for AP806 is controlled per
247 * cluster (2 CPUs per cluster), cpu0 and cpu1 are fixed to
248 * cluster0 while cpu2 and cpu3 are fixed to cluster1 whether
249 * they are enabled or not. Since cpu0 is the boot cpu, then
250 * cluster0 must exist. If cpu2 or cpu3 is enabled, cluster1
251 * will exist and the cluster number is 2; otherwise the
252 * cluster number is 1.
253 */
254 nclusters = 1;
255 for_each_of_cpu_node(dn) {
256 int cpu, err;
257
258 err = of_property_read_u32(dn, "reg", &cpu);
259 if (WARN_ON(err))
260 return err;
261
262 /* If cpu2 or cpu3 is enabled */
263 if (cpu & APN806_CLUSTER_NUM_MASK) {
264 nclusters = 2;
265 break;
266 }
267 }
268 /*
269 * DFS for AP806 is controlled per cluster (2 CPUs per cluster),
270 * so allocate structs per cluster
271 */
272 ap_cpu_clk = devm_kcalloc(dev, nclusters, sizeof(*ap_cpu_clk),
273 GFP_KERNEL);
274 if (!ap_cpu_clk)
275 return -ENOMEM;
276
277 ap_cpu_data = devm_kzalloc(dev, sizeof(*ap_cpu_data) +
278 sizeof(struct clk_hw *) * nclusters,
279 GFP_KERNEL);
280 if (!ap_cpu_data)
281 return -ENOMEM;
282
283 for_each_of_cpu_node(dn) {
284 char *clk_name = "cpu-cluster-0";
285 struct clk_init_data init;
286 const char *parent_name;
287 struct clk *parent;
288 int cpu, err;
289
290 err = of_property_read_u32(dn, "reg", &cpu);
291 if (WARN_ON(err))
292 return err;
293
294 cluster_index = cpu & APN806_CLUSTER_NUM_MASK;
295 cluster_index >>= APN806_CLUSTER_NUM_OFFSET;
296
297 /* Initialize once for one cluster */
298 if (ap_cpu_data->hws[cluster_index])
299 continue;
300
301 parent = of_clk_get(np, cluster_index);
302 if (IS_ERR(parent)) {
303 dev_err(dev, "Could not get the clock parent\n");
304 return -EINVAL;
305 }
306 parent_name = __clk_get_name(parent);
307 clk_name[12] += cluster_index;
308 ap_cpu_clk[cluster_index].clk_name =
309 ap_cp_unique_name(dev, np->parent, clk_name);
310 ap_cpu_clk[cluster_index].cluster = cluster_index;
311 ap_cpu_clk[cluster_index].pll_cr_base = regmap;
312 ap_cpu_clk[cluster_index].hw.init = &init;
313 ap_cpu_clk[cluster_index].dev = dev;
314 ap_cpu_clk[cluster_index].pll_regs = of_device_get_match_data(&pdev->dev);
315
316 init.name = ap_cpu_clk[cluster_index].clk_name;
317 init.ops = &ap_cpu_clk_ops;
318 init.num_parents = 1;
319 init.parent_names = &parent_name;
320
321 ret = devm_clk_hw_register(dev, &ap_cpu_clk[cluster_index].hw);
322 if (ret)
323 return ret;
324 ap_cpu_data->hws[cluster_index] = &ap_cpu_clk[cluster_index].hw;
325 }
326
327 ap_cpu_data->num = cluster_index + 1;
328
329 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, ap_cpu_data);
330 if (ret)
331 dev_err(dev, "failed to register OF clock provider\n");
332
333 return ret;
334}
335
336static const struct of_device_id ap_cpu_clock_of_match[] = {
337 {
338 .compatible = "marvell,ap806-cpu-clock",
339 .data = &ap806_dfs_regs,
340 },
341 {
342 .compatible = "marvell,ap807-cpu-clock",
343 .data = &ap807_dfs_regs,
344 },
345 { }
346};
347
348static struct platform_driver ap_cpu_clock_driver = {
349 .probe = ap_cpu_clock_probe,
350 .driver = {
351 .name = "marvell-ap-cpu-clock",
352 .of_match_table = ap_cpu_clock_of_match,
353 .suppress_bind_attrs = true,
354 },
355};
356builtin_platform_driver(ap_cpu_clock_driver);
diff --git a/drivers/clk/mvebu/ap806-system-controller.c b/drivers/clk/mvebu/ap806-system-controller.c
index ea54a874bbda..948bd1e71aea 100644
--- a/drivers/clk/mvebu/ap806-system-controller.c
+++ b/drivers/clk/mvebu/ap806-system-controller.c
@@ -10,18 +10,18 @@
10 10
11#define pr_fmt(fmt) "ap806-system-controller: " fmt 11#define pr_fmt(fmt) "ap806-system-controller: " fmt
12 12
13#include "armada_ap_cp_helper.h"
13#include <linux/clk-provider.h> 14#include <linux/clk-provider.h>
14#include <linux/mfd/syscon.h> 15#include <linux/mfd/syscon.h>
15#include <linux/init.h> 16#include <linux/init.h>
16#include <linux/of.h> 17#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19#include <linux/regmap.h> 19#include <linux/regmap.h>
20 20
21#define AP806_SAR_REG 0x400 21#define AP806_SAR_REG 0x400
22#define AP806_SAR_CLKFREQ_MODE_MASK 0x1f 22#define AP806_SAR_CLKFREQ_MODE_MASK 0x1f
23 23
24#define AP806_CLK_NUM 5 24#define AP806_CLK_NUM 6
25 25
26static struct clk *ap806_clks[AP806_CLK_NUM]; 26static struct clk *ap806_clks[AP806_CLK_NUM];
27 27
@@ -30,86 +30,149 @@ static struct clk_onecell_data ap806_clk_data = {
30 .clk_num = AP806_CLK_NUM, 30 .clk_num = AP806_CLK_NUM,
31}; 31};
32 32
33static char *ap806_unique_name(struct device *dev, struct device_node *np, 33static int ap806_get_sar_clocks(unsigned int freq_mode,
34 char *name) 34 unsigned int *cpuclk_freq,
35 unsigned int *dclk_freq)
35{ 36{
36 const __be32 *reg;
37 u64 addr;
38
39 reg = of_get_property(np, "reg", NULL);
40 addr = of_translate_address(np, reg);
41 return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s",
42 (unsigned long long)addr, name);
43}
44
45static int ap806_syscon_common_probe(struct platform_device *pdev,
46 struct device_node *syscon_node)
47{
48 unsigned int freq_mode, cpuclk_freq;
49 const char *name, *fixedclk_name;
50 struct device *dev = &pdev->dev;
51 struct device_node *np = dev->of_node;
52 struct regmap *regmap;
53 u32 reg;
54 int ret;
55
56 regmap = syscon_node_to_regmap(syscon_node);
57 if (IS_ERR(regmap)) {
58 dev_err(dev, "cannot get regmap\n");
59 return PTR_ERR(regmap);
60 }
61
62 ret = regmap_read(regmap, AP806_SAR_REG, &reg);
63 if (ret) {
64 dev_err(dev, "cannot read from regmap\n");
65 return ret;
66 }
67
68 freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
69 switch (freq_mode) { 37 switch (freq_mode) {
70 case 0x0: 38 case 0x0:
39 *cpuclk_freq = 2000;
40 *dclk_freq = 600;
41 break;
71 case 0x1: 42 case 0x1:
72 cpuclk_freq = 2000; 43 *cpuclk_freq = 2000;
44 *dclk_freq = 525;
73 break; 45 break;
74 case 0x6: 46 case 0x6:
47 *cpuclk_freq = 1800;
48 *dclk_freq = 600;
49 break;
75 case 0x7: 50 case 0x7:
76 cpuclk_freq = 1800; 51 *cpuclk_freq = 1800;
52 *dclk_freq = 525;
77 break; 53 break;
78 case 0x4: 54 case 0x4:
55 *cpuclk_freq = 1600;
56 *dclk_freq = 400;
57 break;
79 case 0xB: 58 case 0xB:
59 *cpuclk_freq = 1600;
60 *dclk_freq = 450;
61 break;
80 case 0xD: 62 case 0xD:
81 cpuclk_freq = 1600; 63 *cpuclk_freq = 1600;
64 *dclk_freq = 525;
82 break; 65 break;
83 case 0x1a: 66 case 0x1a:
84 cpuclk_freq = 1400; 67 *cpuclk_freq = 1400;
68 *dclk_freq = 400;
85 break; 69 break;
86 case 0x14: 70 case 0x14:
71 *cpuclk_freq = 1300;
72 *dclk_freq = 400;
73 break;
87 case 0x17: 74 case 0x17:
88 cpuclk_freq = 1300; 75 *cpuclk_freq = 1300;
76 *dclk_freq = 325;
89 break; 77 break;
90 case 0x19: 78 case 0x19:
91 cpuclk_freq = 1200; 79 *cpuclk_freq = 1200;
80 *dclk_freq = 400;
92 break; 81 break;
93 case 0x13: 82 case 0x13:
83 *cpuclk_freq = 1000;
84 *dclk_freq = 325;
85 break;
94 case 0x1d: 86 case 0x1d:
95 cpuclk_freq = 1000; 87 *cpuclk_freq = 1000;
88 *dclk_freq = 400;
96 break; 89 break;
97 case 0x1c: 90 case 0x1c:
98 cpuclk_freq = 800; 91 *cpuclk_freq = 800;
92 *dclk_freq = 400;
99 break; 93 break;
100 case 0x1b: 94 case 0x1b:
101 cpuclk_freq = 600; 95 *cpuclk_freq = 600;
96 *dclk_freq = 400;
102 break; 97 break;
103 default: 98 default:
104 dev_err(dev, "invalid SAR value\n");
105 return -EINVAL; 99 return -EINVAL;
106 } 100 }
107 101
102 return 0;
103}
104
105static int ap807_get_sar_clocks(unsigned int freq_mode,
106 unsigned int *cpuclk_freq,
107 unsigned int *dclk_freq)
108{
109 switch (freq_mode) {
110 case 0x0:
111 *cpuclk_freq = 2000;
112 *dclk_freq = 1200;
113 break;
114 case 0x6:
115 *cpuclk_freq = 2200;
116 *dclk_freq = 1200;
117 break;
118 case 0xD:
119 *cpuclk_freq = 1600;
120 *dclk_freq = 1200;
121 break;
122 default:
123 return -EINVAL;
124 }
125
126 return 0;
127}
128
129static int ap806_syscon_common_probe(struct platform_device *pdev,
130 struct device_node *syscon_node)
131{
132 unsigned int freq_mode, cpuclk_freq, dclk_freq;
133 const char *name, *fixedclk_name;
134 struct device *dev = &pdev->dev;
135 struct device_node *np = dev->of_node;
136 struct regmap *regmap;
137 u32 reg;
138 int ret;
139
140 regmap = syscon_node_to_regmap(syscon_node);
141 if (IS_ERR(regmap)) {
142 dev_err(dev, "cannot get regmap\n");
143 return PTR_ERR(regmap);
144 }
145
146 ret = regmap_read(regmap, AP806_SAR_REG, &reg);
147 if (ret) {
148 dev_err(dev, "cannot read from regmap\n");
149 return ret;
150 }
151
152 freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
153
154 if (of_device_is_compatible(pdev->dev.of_node,
155 "marvell,ap806-clock")) {
156 ret = ap806_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
157 } else if (of_device_is_compatible(pdev->dev.of_node,
158 "marvell,ap807-clock")) {
159 ret = ap807_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
160 } else {
161 dev_err(dev, "compatible not supported\n");
162 return -EINVAL;
163 }
164
165 if (ret) {
166 dev_err(dev, "invalid Sample at Reset value\n");
167 return ret;
168 }
169
108 /* Convert to hertz */ 170 /* Convert to hertz */
109 cpuclk_freq *= 1000 * 1000; 171 cpuclk_freq *= 1000 * 1000;
172 dclk_freq *= 1000 * 1000;
110 173
111 /* CPU clocks depend on the Sample At Reset configuration */ 174 /* CPU clocks depend on the Sample At Reset configuration */
112 name = ap806_unique_name(dev, syscon_node, "cpu-cluster-0"); 175 name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-0");
113 ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL, 176 ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
114 0, cpuclk_freq); 177 0, cpuclk_freq);
115 if (IS_ERR(ap806_clks[0])) { 178 if (IS_ERR(ap806_clks[0])) {
@@ -117,7 +180,7 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
117 goto fail0; 180 goto fail0;
118 } 181 }
119 182
120 name = ap806_unique_name(dev, syscon_node, "cpu-cluster-1"); 183 name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-1");
121 ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0, 184 ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
122 cpuclk_freq); 185 cpuclk_freq);
123 if (IS_ERR(ap806_clks[1])) { 186 if (IS_ERR(ap806_clks[1])) {
@@ -126,7 +189,7 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
126 } 189 }
127 190
128 /* Fixed clock is always 1200 Mhz */ 191 /* Fixed clock is always 1200 Mhz */
129 fixedclk_name = ap806_unique_name(dev, syscon_node, "fixed"); 192 fixedclk_name = ap_cp_unique_name(dev, syscon_node, "fixed");
130 ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL, 193 ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL,
131 0, 1200 * 1000 * 1000); 194 0, 1200 * 1000 * 1000);
132 if (IS_ERR(ap806_clks[2])) { 195 if (IS_ERR(ap806_clks[2])) {
@@ -135,7 +198,7 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
135 } 198 }
136 199
137 /* MSS Clock is fixed clock divided by 6 */ 200 /* MSS Clock is fixed clock divided by 6 */
138 name = ap806_unique_name(dev, syscon_node, "mss"); 201 name = ap_cp_unique_name(dev, syscon_node, "mss");
139 ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name, 202 ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
140 0, 1, 6); 203 0, 1, 6);
141 if (IS_ERR(ap806_clks[3])) { 204 if (IS_ERR(ap806_clks[3])) {
@@ -144,7 +207,7 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
144 } 207 }
145 208
146 /* SDIO(/eMMC) Clock is fixed clock divided by 3 */ 209 /* SDIO(/eMMC) Clock is fixed clock divided by 3 */
147 name = ap806_unique_name(dev, syscon_node, "sdio"); 210 name = ap_cp_unique_name(dev, syscon_node, "sdio");
148 ap806_clks[4] = clk_register_fixed_factor(NULL, name, 211 ap806_clks[4] = clk_register_fixed_factor(NULL, name,
149 fixedclk_name, 212 fixedclk_name,
150 0, 1, 3); 213 0, 1, 3);
@@ -153,6 +216,14 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
153 goto fail4; 216 goto fail4;
154 } 217 }
155 218
219 /* AP-DCLK(HCLK) Clock is DDR clock divided by 2 */
220 name = ap_cp_unique_name(dev, syscon_node, "ap-dclk");
221 ap806_clks[5] = clk_register_fixed_rate(dev, name, NULL, 0, dclk_freq);
222 if (IS_ERR(ap806_clks[5])) {
223 ret = PTR_ERR(ap806_clks[5]);
224 goto fail5;
225 }
226
156 ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data); 227 ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
157 if (ret) 228 if (ret)
158 goto fail_clk_add; 229 goto fail_clk_add;
@@ -160,6 +231,8 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
160 return 0; 231 return 0;
161 232
162fail_clk_add: 233fail_clk_add:
234 clk_unregister_fixed_factor(ap806_clks[5]);
235fail5:
163 clk_unregister_fixed_factor(ap806_clks[4]); 236 clk_unregister_fixed_factor(ap806_clks[4]);
164fail4: 237fail4:
165 clk_unregister_fixed_factor(ap806_clks[3]); 238 clk_unregister_fixed_factor(ap806_clks[3]);
@@ -206,6 +279,7 @@ builtin_platform_driver(ap806_syscon_legacy_driver);
206 279
207static const struct of_device_id ap806_clock_of_match[] = { 280static const struct of_device_id ap806_clock_of_match[] = {
208 { .compatible = "marvell,ap806-clock", }, 281 { .compatible = "marvell,ap806-clock", },
282 { .compatible = "marvell,ap807-clock", },
209 { } 283 { }
210}; 284};
211 285
diff --git a/drivers/clk/mvebu/armada_ap_cp_helper.c b/drivers/clk/mvebu/armada_ap_cp_helper.c
new file mode 100644
index 000000000000..6a930f697ee5
--- /dev/null
+++ b/drivers/clk/mvebu/armada_ap_cp_helper.c
@@ -0,0 +1,30 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Marvell Armada AP and CP110 helper
4 *
5 * Copyright (C) 2018 Marvell
6 *
7 * Gregory Clement <gregory.clement@bootlin.com>
8 *
9 */
10
11#include "armada_ap_cp_helper.h"
12#include <linux/device.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15
16char *ap_cp_unique_name(struct device *dev, struct device_node *np,
17 const char *name)
18{
19 const __be32 *reg;
20 u64 addr;
21
22 /* Do not create a name if there is no clock */
23 if (!name)
24 return NULL;
25
26 reg = of_get_property(np, "reg", NULL);
27 addr = of_translate_address(np, reg);
28 return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s",
29 (unsigned long long)addr, name);
30}
diff --git a/drivers/clk/mvebu/armada_ap_cp_helper.h b/drivers/clk/mvebu/armada_ap_cp_helper.h
new file mode 100644
index 000000000000..810af1e5dfa4
--- /dev/null
+++ b/drivers/clk/mvebu/armada_ap_cp_helper.h
@@ -0,0 +1,11 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2
3#ifndef __ARMADA_AP_CP_HELPER_H
4#define __ARMADA_AP_CP_HELPER_H
5
6struct device;
7struct device_node;
8
9char *ap_cp_unique_name(struct device *dev, struct device_node *np,
10 const char *name);
11#endif
diff --git a/drivers/clk/mvebu/cp110-system-controller.c b/drivers/clk/mvebu/cp110-system-controller.c
index b6de283f45e3..808463276145 100644
--- a/drivers/clk/mvebu/cp110-system-controller.c
+++ b/drivers/clk/mvebu/cp110-system-controller.c
@@ -26,11 +26,11 @@
26 26
27#define pr_fmt(fmt) "cp110-system-controller: " fmt 27#define pr_fmt(fmt) "cp110-system-controller: " fmt
28 28
29#include "armada_ap_cp_helper.h"
29#include <linux/clk-provider.h> 30#include <linux/clk-provider.h>
30#include <linux/mfd/syscon.h> 31#include <linux/mfd/syscon.h>
31#include <linux/init.h> 32#include <linux/init.h>
32#include <linux/of.h> 33#include <linux/of.h>
33#include <linux/of_address.h>
34#include <linux/platform_device.h> 34#include <linux/platform_device.h>
35#include <linux/regmap.h> 35#include <linux/regmap.h>
36#include <linux/slab.h> 36#include <linux/slab.h>
@@ -212,22 +212,6 @@ static struct clk_hw *cp110_of_clk_get(struct of_phandle_args *clkspec,
212 return ERR_PTR(-EINVAL); 212 return ERR_PTR(-EINVAL);
213} 213}
214 214
215static char *cp110_unique_name(struct device *dev, struct device_node *np,
216 const char *name)
217{
218 const __be32 *reg;
219 u64 addr;
220
221 /* Do not create a name if there is no clock */
222 if (!name)
223 return NULL;
224
225 reg = of_get_property(np, "reg", NULL);
226 addr = of_translate_address(np, reg);
227 return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s",
228 (unsigned long long)addr, name);
229}
230
231static int cp110_syscon_common_probe(struct platform_device *pdev, 215static int cp110_syscon_common_probe(struct platform_device *pdev,
232 struct device_node *syscon_node) 216 struct device_node *syscon_node)
233{ 217{
@@ -261,7 +245,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
261 cp110_clk_data->num = CP110_CLK_NUM; 245 cp110_clk_data->num = CP110_CLK_NUM;
262 246
263 /* Register the PLL0 which is the root of the hw tree */ 247 /* Register the PLL0 which is the root of the hw tree */
264 pll0_name = cp110_unique_name(dev, syscon_node, "pll0"); 248 pll0_name = ap_cp_unique_name(dev, syscon_node, "pll0");
265 hw = clk_hw_register_fixed_rate(NULL, pll0_name, NULL, 0, 249 hw = clk_hw_register_fixed_rate(NULL, pll0_name, NULL, 0,
266 1000 * 1000 * 1000); 250 1000 * 1000 * 1000);
267 if (IS_ERR(hw)) { 251 if (IS_ERR(hw)) {
@@ -272,7 +256,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
272 cp110_clks[CP110_CORE_PLL0] = hw; 256 cp110_clks[CP110_CORE_PLL0] = hw;
273 257
274 /* PPv2 is PLL0/3 */ 258 /* PPv2 is PLL0/3 */
275 ppv2_name = cp110_unique_name(dev, syscon_node, "ppv2-core"); 259 ppv2_name = ap_cp_unique_name(dev, syscon_node, "ppv2-core");
276 hw = clk_hw_register_fixed_factor(NULL, ppv2_name, pll0_name, 0, 1, 3); 260 hw = clk_hw_register_fixed_factor(NULL, ppv2_name, pll0_name, 0, 1, 3);
277 if (IS_ERR(hw)) { 261 if (IS_ERR(hw)) {
278 ret = PTR_ERR(hw); 262 ret = PTR_ERR(hw);
@@ -282,7 +266,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
282 cp110_clks[CP110_CORE_PPV2] = hw; 266 cp110_clks[CP110_CORE_PPV2] = hw;
283 267
284 /* X2CORE clock is PLL0/2 */ 268 /* X2CORE clock is PLL0/2 */
285 x2core_name = cp110_unique_name(dev, syscon_node, "x2core"); 269 x2core_name = ap_cp_unique_name(dev, syscon_node, "x2core");
286 hw = clk_hw_register_fixed_factor(NULL, x2core_name, pll0_name, 270 hw = clk_hw_register_fixed_factor(NULL, x2core_name, pll0_name,
287 0, 1, 2); 271 0, 1, 2);
288 if (IS_ERR(hw)) { 272 if (IS_ERR(hw)) {
@@ -293,7 +277,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
293 cp110_clks[CP110_CORE_X2CORE] = hw; 277 cp110_clks[CP110_CORE_X2CORE] = hw;
294 278
295 /* Core clock is X2CORE/2 */ 279 /* Core clock is X2CORE/2 */
296 core_name = cp110_unique_name(dev, syscon_node, "core"); 280 core_name = ap_cp_unique_name(dev, syscon_node, "core");
297 hw = clk_hw_register_fixed_factor(NULL, core_name, x2core_name, 281 hw = clk_hw_register_fixed_factor(NULL, core_name, x2core_name,
298 0, 1, 2); 282 0, 1, 2);
299 if (IS_ERR(hw)) { 283 if (IS_ERR(hw)) {
@@ -303,7 +287,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
303 287
304 cp110_clks[CP110_CORE_CORE] = hw; 288 cp110_clks[CP110_CORE_CORE] = hw;
305 /* NAND can be either PLL0/2.5 or core clock */ 289 /* NAND can be either PLL0/2.5 or core clock */
306 nand_name = cp110_unique_name(dev, syscon_node, "nand-core"); 290 nand_name = ap_cp_unique_name(dev, syscon_node, "nand-core");
307 if (nand_clk_ctrl & NF_CLOCK_SEL_400_MASK) 291 if (nand_clk_ctrl & NF_CLOCK_SEL_400_MASK)
308 hw = clk_hw_register_fixed_factor(NULL, nand_name, 292 hw = clk_hw_register_fixed_factor(NULL, nand_name,
309 pll0_name, 0, 2, 5); 293 pll0_name, 0, 2, 5);
@@ -318,7 +302,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
318 cp110_clks[CP110_CORE_NAND] = hw; 302 cp110_clks[CP110_CORE_NAND] = hw;
319 303
320 /* SDIO clock is PLL0/2.5 */ 304 /* SDIO clock is PLL0/2.5 */
321 sdio_name = cp110_unique_name(dev, syscon_node, "sdio-core"); 305 sdio_name = ap_cp_unique_name(dev, syscon_node, "sdio-core");
322 hw = clk_hw_register_fixed_factor(NULL, sdio_name, 306 hw = clk_hw_register_fixed_factor(NULL, sdio_name,
323 pll0_name, 0, 2, 5); 307 pll0_name, 0, 2, 5);
324 if (IS_ERR(hw)) { 308 if (IS_ERR(hw)) {
@@ -330,7 +314,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
330 314
331 /* create the unique name for all the gate clocks */ 315 /* create the unique name for all the gate clocks */
332 for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) 316 for (i = 0; i < ARRAY_SIZE(gate_base_names); i++)
333 gate_name[i] = cp110_unique_name(dev, syscon_node, 317 gate_name[i] = ap_cp_unique_name(dev, syscon_node,
334 gate_base_names[i]); 318 gate_base_names[i]);
335 319
336 for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) { 320 for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) {
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index e1ff83cc361e..32dbb4f09492 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -21,7 +21,6 @@ if COMMON_CLK_QCOM
21 21
22config QCOM_A53PLL 22config QCOM_A53PLL
23 tristate "MSM8916 A53 PLL" 23 tristate "MSM8916 A53 PLL"
24 default ARCH_QCOM
25 help 24 help
26 Support for the A53 PLL on MSM8916 devices. It provides 25 Support for the A53 PLL on MSM8916 devices. It provides
27 the CPU with frequencies above 1GHz. 26 the CPU with frequencies above 1GHz.
@@ -31,7 +30,6 @@ config QCOM_A53PLL
31config QCOM_CLK_APCS_MSM8916 30config QCOM_CLK_APCS_MSM8916
32 tristate "MSM8916 APCS Clock Controller" 31 tristate "MSM8916 APCS Clock Controller"
33 depends on QCOM_APCS_IPC || COMPILE_TEST 32 depends on QCOM_APCS_IPC || COMPILE_TEST
34 default ARCH_QCOM
35 help 33 help
36 Support for the APCS Clock Controller on msm8916 devices. The 34 Support for the APCS Clock Controller on msm8916 devices. The
37 APCS is managing the mux and divider which feeds the CPUs. 35 APCS is managing the mux and divider which feeds the CPUs.
@@ -292,6 +290,13 @@ config SDM_LPASSCC_845
292 Say Y if you want to use the LPASS branch clocks of the LPASS clock 290 Say Y if you want to use the LPASS branch clocks of the LPASS clock
293 controller to reset the LPASS subsystem. 291 controller to reset the LPASS subsystem.
294 292
293config SM_GCC_8150
294 tristate "SM8150 Global Clock Controller"
295 help
296 Support for the global clock controller on SM8150 devices.
297 Say Y if you want to use peripheral devices such as UART,
298 SPI, I2C, USB, SD/UFS, PCIe etc.
299
295config SPMI_PMIC_CLKDIV 300config SPMI_PMIC_CLKDIV
296 tristate "SPMI PMIC clkdiv Support" 301 tristate "SPMI PMIC clkdiv Support"
297 depends on SPMI || COMPILE_TEST 302 depends on SPMI || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index f0768fb1f037..4a813b4055d0 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
50obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o 50obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
51obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o 51obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
52obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o 52obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
53obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
53obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o 54obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
54obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o 55obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
55obj-$(CONFIG_QCOM_HFPLL) += hfpll.o 56obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 0ced4a5a9a17..055318f97991 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -32,6 +32,7 @@
32# define PLL_LOCK_DET BIT(31) 32# define PLL_LOCK_DET BIT(31)
33 33
34#define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) 34#define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
35#define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
35#define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) 36#define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
36#define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) 37#define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
37 38
@@ -44,14 +45,17 @@
44# define PLL_VCO_MASK 0x3 45# define PLL_VCO_MASK 0x3
45 46
46#define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U]) 47#define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
48#define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
47 49
48#define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) 50#define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
49#define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) 51#define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
52#define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
50#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) 53#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
51#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) 54#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
52#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) 55#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
53#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) 56#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
54#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) 57#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
58#define PLL_CAL_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_VAL])
55 59
56const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 60const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
57 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 61 [CLK_ALPHA_PLL_TYPE_DEFAULT] = {
@@ -96,6 +100,22 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
96 [PLL_OFF_OPMODE] = 0x2c, 100 [PLL_OFF_OPMODE] = 0x2c,
97 [PLL_OFF_FRAC] = 0x38, 101 [PLL_OFF_FRAC] = 0x38,
98 }, 102 },
103 [CLK_ALPHA_PLL_TYPE_TRION] = {
104 [PLL_OFF_L_VAL] = 0x04,
105 [PLL_OFF_CAL_L_VAL] = 0x08,
106 [PLL_OFF_USER_CTL] = 0x0c,
107 [PLL_OFF_USER_CTL_U] = 0x10,
108 [PLL_OFF_USER_CTL_U1] = 0x14,
109 [PLL_OFF_CONFIG_CTL] = 0x18,
110 [PLL_OFF_CONFIG_CTL_U] = 0x1c,
111 [PLL_OFF_CONFIG_CTL_U1] = 0x20,
112 [PLL_OFF_TEST_CTL] = 0x24,
113 [PLL_OFF_TEST_CTL_U] = 0x28,
114 [PLL_OFF_STATUS] = 0x30,
115 [PLL_OFF_OPMODE] = 0x38,
116 [PLL_OFF_ALPHA_VAL] = 0x40,
117 [PLL_OFF_CAL_VAL] = 0x44,
118 },
99}; 119};
100EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 120EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
101 121
@@ -120,6 +140,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
120#define FABIA_PLL_OUT_MASK 0x7 140#define FABIA_PLL_OUT_MASK 0x7
121#define FABIA_PLL_RATE_MARGIN 500 141#define FABIA_PLL_RATE_MARGIN 500
122 142
143#define TRION_PLL_STANDBY 0x0
144#define TRION_PLL_RUN 0x1
145#define TRION_PLL_OUT_MASK 0x7
146
123#define pll_alpha_width(p) \ 147#define pll_alpha_width(p) \
124 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ 148 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
125 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) 149 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
@@ -730,6 +754,130 @@ static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
730 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); 754 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
731} 755}
732 756
757static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
758 struct regmap *regmap)
759{
760 u32 mode_regval, opmode_regval;
761 int ret;
762
763 ret = regmap_read(regmap, PLL_MODE(pll), &mode_regval);
764 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_regval);
765 if (ret)
766 return 0;
767
768 return ((opmode_regval & TRION_PLL_RUN) && (mode_regval & PLL_OUTCTRL));
769}
770
771static int clk_trion_pll_is_enabled(struct clk_hw *hw)
772{
773 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
774
775 return trion_pll_is_enabled(pll, pll->clkr.regmap);
776}
777
778static int clk_trion_pll_enable(struct clk_hw *hw)
779{
780 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
781 struct regmap *regmap = pll->clkr.regmap;
782 u32 val;
783 int ret;
784
785 ret = regmap_read(regmap, PLL_MODE(pll), &val);
786 if (ret)
787 return ret;
788
789 /* If in FSM mode, just vote for it */
790 if (val & PLL_VOTE_FSM_ENA) {
791 ret = clk_enable_regmap(hw);
792 if (ret)
793 return ret;
794 return wait_for_pll_enable_active(pll);
795 }
796
797 /* Set operation mode to RUN */
798 regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_RUN);
799
800 ret = wait_for_pll_enable_lock(pll);
801 if (ret)
802 return ret;
803
804 /* Enable the PLL outputs */
805 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
806 TRION_PLL_OUT_MASK, TRION_PLL_OUT_MASK);
807 if (ret)
808 return ret;
809
810 /* Enable the global PLL outputs */
811 return regmap_update_bits(regmap, PLL_MODE(pll),
812 PLL_OUTCTRL, PLL_OUTCTRL);
813}
814
815static void clk_trion_pll_disable(struct clk_hw *hw)
816{
817 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
818 struct regmap *regmap = pll->clkr.regmap;
819 u32 val;
820 int ret;
821
822 ret = regmap_read(regmap, PLL_MODE(pll), &val);
823 if (ret)
824 return;
825
826 /* If in FSM mode, just unvote it */
827 if (val & PLL_VOTE_FSM_ENA) {
828 clk_disable_regmap(hw);
829 return;
830 }
831
832 /* Disable the global PLL output */
833 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
834 if (ret)
835 return;
836
837 /* Disable the PLL outputs */
838 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
839 TRION_PLL_OUT_MASK, 0);
840 if (ret)
841 return;
842
843 /* Place the PLL mode in STANDBY */
844 regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_STANDBY);
845 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
846}
847
848static unsigned long
849clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
850{
851 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
852 struct regmap *regmap = pll->clkr.regmap;
853 u32 l, frac;
854 u64 prate = parent_rate;
855
856 regmap_read(regmap, PLL_L_VAL(pll), &l);
857 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
858
859 return alpha_pll_calc_rate(prate, l, frac, ALPHA_REG_16BIT_WIDTH);
860}
861
862static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate,
863 unsigned long *prate)
864{
865 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
866 unsigned long min_freq, max_freq;
867 u32 l;
868 u64 a;
869
870 rate = alpha_pll_round_rate(rate, *prate,
871 &l, &a, ALPHA_REG_16BIT_WIDTH);
872 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
873 return rate;
874
875 min_freq = pll->vco_table[0].min_freq;
876 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
877
878 return clamp(rate, min_freq, max_freq);
879}
880
733const struct clk_ops clk_alpha_pll_ops = { 881const struct clk_ops clk_alpha_pll_ops = {
734 .enable = clk_alpha_pll_enable, 882 .enable = clk_alpha_pll_enable,
735 .disable = clk_alpha_pll_disable, 883 .disable = clk_alpha_pll_disable,
@@ -760,6 +908,15 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = {
760}; 908};
761EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); 909EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
762 910
911const struct clk_ops clk_trion_fixed_pll_ops = {
912 .enable = clk_trion_pll_enable,
913 .disable = clk_trion_pll_disable,
914 .is_enabled = clk_trion_pll_is_enabled,
915 .recalc_rate = clk_trion_pll_recalc_rate,
916 .round_rate = clk_trion_pll_round_rate,
917};
918EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);
919
763static unsigned long 920static unsigned long
764clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 921clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
765{ 922{
@@ -832,7 +989,7 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
832 int div; 989 int div;
833 990
834 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ 991 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
835 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1; 992 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1;
836 993
837 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 994 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
838 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 995 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
@@ -1036,11 +1193,6 @@ static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1036 u32 i, div = 1, val; 1193 u32 i, div = 1, val;
1037 int ret; 1194 int ret;
1038 1195
1039 if (!pll->post_div_table) {
1040 pr_err("Missing the post_div_table for the PLL\n");
1041 return -EINVAL;
1042 }
1043
1044 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1196 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1045 if (ret) 1197 if (ret)
1046 return ret; 1198 return ret;
@@ -1058,16 +1210,71 @@ static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1058 return (parent_rate / div); 1210 return (parent_rate / div);
1059} 1211}
1060 1212
1061static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw, 1213static unsigned long
1062 unsigned long rate, unsigned long *prate) 1214clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1063{ 1215{
1064 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1216 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1217 struct regmap *regmap = pll->clkr.regmap;
1218 u32 i, div = 1, val;
1065 1219
1066 if (!pll->post_div_table) { 1220 regmap_read(regmap, PLL_USER_CTL(pll), &val);
1067 pr_err("Missing the post_div_table for the PLL\n"); 1221
1068 return -EINVAL; 1222 val >>= pll->post_div_shift;
1223 val &= PLL_POST_DIV_MASK(pll);
1224
1225 for (i = 0; i < pll->num_post_div; i++) {
1226 if (pll->post_div_table[i].val == val) {
1227 div = pll->post_div_table[i].div;
1228 break;
1229 }
1230 }
1231
1232 return (parent_rate / div);
1233}
1234
1235static long
1236clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1237 unsigned long *prate)
1238{
1239 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1240
1241 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1242 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1243};
1244
1245static int
1246clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1247 unsigned long parent_rate)
1248{
1249 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1250 struct regmap *regmap = pll->clkr.regmap;
1251 int i, val = 0, div;
1252
1253 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1254 for (i = 0; i < pll->num_post_div; i++) {
1255 if (pll->post_div_table[i].div == div) {
1256 val = pll->post_div_table[i].val;
1257 break;
1258 }
1069 } 1259 }
1070 1260
1261 return regmap_update_bits(regmap, PLL_USER_CTL(pll),
1262 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1263 val << PLL_POST_DIV_SHIFT);
1264}
1265
1266const struct clk_ops clk_trion_pll_postdiv_ops = {
1267 .recalc_rate = clk_trion_pll_postdiv_recalc_rate,
1268 .round_rate = clk_trion_pll_postdiv_round_rate,
1269 .set_rate = clk_trion_pll_postdiv_set_rate,
1270};
1271EXPORT_SYMBOL_GPL(clk_trion_pll_postdiv_ops);
1272
1273static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
1274 unsigned long rate, unsigned long *prate)
1275{
1276 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1277
1071 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1278 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1072 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1279 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1073} 1280}
@@ -1089,12 +1296,7 @@ static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
1089 if (val & PLL_VOTE_FSM_ENA) 1296 if (val & PLL_VOTE_FSM_ENA)
1090 return 0; 1297 return 0;
1091 1298
1092 if (!pll->post_div_table) { 1299 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1093 pr_err("Missing the post_div_table for the PLL\n");
1094 return -EINVAL;
1095 }
1096
1097 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
1098 for (i = 0; i < pll->num_post_div; i++) { 1300 for (i = 0; i < pll->num_post_div; i++) {
1099 if (pll->post_div_table[i].div == div) { 1301 if (pll->post_div_table[i].div == div) {
1100 val = pll->post_div_table[i].val; 1302 val = pll->post_div_table[i].val;
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 66755f0f84fc..15f27f4b06df 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -13,22 +13,27 @@ enum {
13 CLK_ALPHA_PLL_TYPE_HUAYRA, 13 CLK_ALPHA_PLL_TYPE_HUAYRA,
14 CLK_ALPHA_PLL_TYPE_BRAMMO, 14 CLK_ALPHA_PLL_TYPE_BRAMMO,
15 CLK_ALPHA_PLL_TYPE_FABIA, 15 CLK_ALPHA_PLL_TYPE_FABIA,
16 CLK_ALPHA_PLL_TYPE_TRION,
16 CLK_ALPHA_PLL_TYPE_MAX, 17 CLK_ALPHA_PLL_TYPE_MAX,
17}; 18};
18 19
19enum { 20enum {
20 PLL_OFF_L_VAL, 21 PLL_OFF_L_VAL,
22 PLL_OFF_CAL_L_VAL,
21 PLL_OFF_ALPHA_VAL, 23 PLL_OFF_ALPHA_VAL,
22 PLL_OFF_ALPHA_VAL_U, 24 PLL_OFF_ALPHA_VAL_U,
23 PLL_OFF_USER_CTL, 25 PLL_OFF_USER_CTL,
24 PLL_OFF_USER_CTL_U, 26 PLL_OFF_USER_CTL_U,
27 PLL_OFF_USER_CTL_U1,
25 PLL_OFF_CONFIG_CTL, 28 PLL_OFF_CONFIG_CTL,
26 PLL_OFF_CONFIG_CTL_U, 29 PLL_OFF_CONFIG_CTL_U,
30 PLL_OFF_CONFIG_CTL_U1,
27 PLL_OFF_TEST_CTL, 31 PLL_OFF_TEST_CTL,
28 PLL_OFF_TEST_CTL_U, 32 PLL_OFF_TEST_CTL_U,
29 PLL_OFF_STATUS, 33 PLL_OFF_STATUS,
30 PLL_OFF_OPMODE, 34 PLL_OFF_OPMODE,
31 PLL_OFF_FRAC, 35 PLL_OFF_FRAC,
36 PLL_OFF_CAL_VAL,
32 PLL_OFF_MAX_REGS 37 PLL_OFF_MAX_REGS
33}; 38};
34 39
@@ -117,5 +122,7 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
117 const struct alpha_pll_config *config); 122 const struct alpha_pll_config *config);
118void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 123void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
119 const struct alpha_pll_config *config); 124 const struct alpha_pll_config *config);
125extern const struct clk_ops clk_trion_fixed_pll_ops;
126extern const struct clk_ops clk_trion_pll_postdiv_ops;
120 127
121#endif 128#endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 8c02bffe50df..57dbac9a590e 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -119,7 +119,7 @@ static int update_config(struct clk_rcg2 *rcg)
119 } 119 }
120 120
121 WARN(1, "%s: rcg didn't update its configuration.", name); 121 WARN(1, "%s: rcg didn't update its configuration.", name);
122 return 0; 122 return -EBUSY;
123} 123}
124 124
125static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index) 125static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index c3fd632af119..49694082e9ec 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -95,7 +95,10 @@ static DEFINE_MUTEX(rpmh_clk_lock);
95 .hw.init = &(struct clk_init_data){ \ 95 .hw.init = &(struct clk_init_data){ \
96 .ops = &clk_rpmh_ops, \ 96 .ops = &clk_rpmh_ops, \
97 .name = #_name, \ 97 .name = #_name, \
98 .parent_names = (const char *[]){ "xo_board" }, \ 98 .parent_data = &(const struct clk_parent_data){ \
99 .fw_name = "xo", \
100 .name = "xo_board", \
101 }, \
99 .num_parents = 1, \ 102 .num_parents = 1, \
100 }, \ 103 }, \
101 }; \ 104 }; \
@@ -110,7 +113,10 @@ static DEFINE_MUTEX(rpmh_clk_lock);
110 .hw.init = &(struct clk_init_data){ \ 113 .hw.init = &(struct clk_init_data){ \
111 .ops = &clk_rpmh_ops, \ 114 .ops = &clk_rpmh_ops, \
112 .name = #_name_active, \ 115 .name = #_name_active, \
113 .parent_names = (const char *[]){ "xo_board" }, \ 116 .parent_data = &(const struct clk_parent_data){ \
117 .fw_name = "xo", \
118 .name = "xo_board", \
119 }, \
114 .num_parents = 1, \ 120 .num_parents = 1, \
115 }, \ 121 }, \
116 } 122 }
@@ -368,6 +374,33 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
368 .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks), 374 .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),
369}; 375};
370 376
377DEFINE_CLK_RPMH_ARC(sm8150, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
378DEFINE_CLK_RPMH_VRM(sm8150, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
379DEFINE_CLK_RPMH_VRM(sm8150, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
380DEFINE_CLK_RPMH_VRM(sm8150, rf_clk1, rf_clk1_ao, "rfclka1", 1);
381DEFINE_CLK_RPMH_VRM(sm8150, rf_clk2, rf_clk2_ao, "rfclka2", 1);
382DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1);
383
384static struct clk_hw *sm8150_rpmh_clocks[] = {
385 [RPMH_CXO_CLK] = &sm8150_bi_tcxo.hw,
386 [RPMH_CXO_CLK_A] = &sm8150_bi_tcxo_ao.hw,
387 [RPMH_LN_BB_CLK2] = &sm8150_ln_bb_clk2.hw,
388 [RPMH_LN_BB_CLK2_A] = &sm8150_ln_bb_clk2_ao.hw,
389 [RPMH_LN_BB_CLK3] = &sm8150_ln_bb_clk3.hw,
390 [RPMH_LN_BB_CLK3_A] = &sm8150_ln_bb_clk3_ao.hw,
391 [RPMH_RF_CLK1] = &sm8150_rf_clk1.hw,
392 [RPMH_RF_CLK1_A] = &sm8150_rf_clk1_ao.hw,
393 [RPMH_RF_CLK2] = &sm8150_rf_clk2.hw,
394 [RPMH_RF_CLK2_A] = &sm8150_rf_clk2_ao.hw,
395 [RPMH_RF_CLK3] = &sm8150_rf_clk3.hw,
396 [RPMH_RF_CLK3_A] = &sm8150_rf_clk3_ao.hw,
397};
398
399static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
400 .clks = sm8150_rpmh_clocks,
401 .num_clks = ARRAY_SIZE(sm8150_rpmh_clocks),
402};
403
371static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, 404static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
372 void *data) 405 void *data)
373{ 406{
@@ -447,6 +480,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
447 480
448static const struct of_device_id clk_rpmh_match_table[] = { 481static const struct of_device_id clk_rpmh_match_table[] = {
449 { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845}, 482 { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
483 { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
450 { } 484 { }
451}; 485};
452MODULE_DEVICE_TABLE(of, clk_rpmh_match_table); 486MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index a6b2f86112d8..28ddc747d703 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -306,4 +306,24 @@ int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
306} 306}
307EXPORT_SYMBOL_GPL(qcom_cc_probe); 307EXPORT_SYMBOL_GPL(qcom_cc_probe);
308 308
309int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
310 const struct qcom_cc_desc *desc)
311{
312 struct regmap *regmap;
313 struct resource *res;
314 void __iomem *base;
315
316 res = platform_get_resource(pdev, IORESOURCE_MEM, index);
317 base = devm_ioremap_resource(&pdev->dev, res);
318 if (IS_ERR(base))
319 return -ENOMEM;
320
321 regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config);
322 if (IS_ERR(regmap))
323 return PTR_ERR(regmap);
324
325 return qcom_cc_really_probe(pdev, desc, regmap);
326}
327EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index);
328
309MODULE_LICENSE("GPL v2"); 329MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index 1e2a8bdac55a..bb39a7e106d8 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -61,5 +61,7 @@ extern int qcom_cc_really_probe(struct platform_device *pdev,
61 struct regmap *regmap); 61 struct regmap *regmap);
62extern int qcom_cc_probe(struct platform_device *pdev, 62extern int qcom_cc_probe(struct platform_device *pdev,
63 const struct qcom_cc_desc *desc); 63 const struct qcom_cc_desc *desc);
64extern int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
65 const struct qcom_cc_desc *desc);
64 66
65#endif 67#endif
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index 39ade58b4ada..e01f5f591d1e 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -1108,7 +1108,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
1108 .name = "sdcc2_apps_clk_src", 1108 .name = "sdcc2_apps_clk_src",
1109 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, 1109 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1110 .num_parents = 4, 1110 .num_parents = 4,
1111 .ops = &clk_rcg2_ops, 1111 .ops = &clk_rcg2_floor_ops,
1112 }, 1112 },
1113}; 1113};
1114 1114
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index 033688264c7b..091acd59c1d6 100644
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -1042,7 +1042,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
1042 .name = "sdcc2_apps_clk_src", 1042 .name = "sdcc2_apps_clk_src",
1043 .parent_names = gcc_parent_names_4, 1043 .parent_names = gcc_parent_names_4,
1044 .num_parents = 4, 1044 .num_parents = 4,
1045 .ops = &clk_rcg2_ops, 1045 .ops = &clk_rcg2_floor_ops,
1046 }, 1046 },
1047}; 1047};
1048 1048
@@ -1066,7 +1066,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
1066 .name = "sdcc4_apps_clk_src", 1066 .name = "sdcc4_apps_clk_src",
1067 .parent_names = gcc_parent_names_1, 1067 .parent_names = gcc_parent_names_1,
1068 .num_parents = 3, 1068 .num_parents = 3,
1069 .ops = &clk_rcg2_ops, 1069 .ops = &clk_rcg2_floor_ops,
1070 }, 1070 },
1071}; 1071};
1072 1072
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index 29cf464dd2c8..bd32212f37e6 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -1057,7 +1057,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
1057 .name = "sdcc1_apps_clk_src", 1057 .name = "sdcc1_apps_clk_src",
1058 .parent_names = gcc_parent_names_13, 1058 .parent_names = gcc_parent_names_13,
1059 .num_parents = 5, 1059 .num_parents = 5,
1060 .ops = &clk_rcg2_ops, 1060 .ops = &clk_rcg2_floor_ops,
1061 }, 1061 },
1062}; 1062};
1063 1063
@@ -1103,7 +1103,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
1103 .name = "sdcc2_apps_clk_src", 1103 .name = "sdcc2_apps_clk_src",
1104 .parent_names = gcc_parent_names_14, 1104 .parent_names = gcc_parent_names_14,
1105 .num_parents = 4, 1105 .num_parents = 4,
1106 .ops = &clk_rcg2_ops, 1106 .ops = &clk_rcg2_floor_ops,
1107 }, 1107 },
1108}; 1108};
1109 1109
@@ -2604,6 +2604,32 @@ static struct clk_branch gcc_usb_hs_system_clk = {
2604 }, 2604 },
2605}; 2605};
2606 2606
2607static struct clk_branch gcc_wdsp_q6ss_ahbs_clk = {
2608 .halt_reg = 0x1e004,
2609 .halt_check = BRANCH_HALT,
2610 .clkr = {
2611 .enable_reg = 0x1e004,
2612 .enable_mask = BIT(0),
2613 .hw.init = &(struct clk_init_data){
2614 .name = "gcc_wdsp_q6ss_ahbs_clk",
2615 .ops = &clk_branch2_ops,
2616 },
2617 },
2618};
2619
2620static struct clk_branch gcc_wdsp_q6ss_axim_clk = {
2621 .halt_reg = 0x1e008,
2622 .halt_check = BRANCH_HALT,
2623 .clkr = {
2624 .enable_reg = 0x1e008,
2625 .enable_mask = BIT(0),
2626 .hw.init = &(struct clk_init_data){
2627 .name = "gcc_wdsp_q6ss_axim_clk",
2628 .ops = &clk_branch2_ops,
2629 },
2630 },
2631};
2632
2607static struct clk_hw *gcc_qcs404_hws[] = { 2633static struct clk_hw *gcc_qcs404_hws[] = {
2608 &cxo.hw, 2634 &cxo.hw,
2609}; 2635};
@@ -2749,6 +2775,9 @@ static struct clk_regmap *gcc_qcs404_clocks[] = {
2749 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, 2775 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
2750 [GCC_DCC_CLK] = &gcc_dcc_clk.clkr, 2776 [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
2751 [GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr, 2777 [GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr,
2778 [GCC_WCSS_Q6_AHB_CLK] = &gcc_wdsp_q6ss_ahbs_clk.clkr,
2779 [GCC_WCSS_Q6_AXIM_CLK] = &gcc_wdsp_q6ss_axim_clk.clkr,
2780
2752}; 2781};
2753 2782
2754static const struct qcom_reset_map gcc_qcs404_resets[] = { 2783static const struct qcom_reset_map gcc_qcs404_resets[] = {
@@ -2774,6 +2803,7 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = {
2774 [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 }, 2803 [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
2775 [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 }, 2804 [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
2776 [GCC_EMAC_BCR] = { 0x4e000 }, 2805 [GCC_EMAC_BCR] = { 0x4e000 },
2806 [GCC_WDSP_RESTART] = {0x19000},
2777}; 2807};
2778 2808
2779static const struct regmap_config gcc_qcs404_regmap_config = { 2809static const struct regmap_config gcc_qcs404_regmap_config = {
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
index 8827db23066f..bf5730832ef3 100644
--- a/drivers/clk/qcom/gcc-sdm660.c
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -787,7 +787,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
787 .name = "sdcc2_apps_clk_src", 787 .name = "sdcc2_apps_clk_src",
788 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4, 788 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4,
789 .num_parents = 4, 789 .num_parents = 4,
790 .ops = &clk_rcg2_ops, 790 .ops = &clk_rcg2_floor_ops,
791 }, 791 },
792}; 792};
793 793
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index 7131dcf9b060..95be125c3bdd 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -685,7 +685,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
685 .name = "gcc_sdcc2_apps_clk_src", 685 .name = "gcc_sdcc2_apps_clk_src",
686 .parent_names = gcc_parent_names_10, 686 .parent_names = gcc_parent_names_10,
687 .num_parents = 5, 687 .num_parents = 5,
688 .ops = &clk_rcg2_ops, 688 .ops = &clk_rcg2_floor_ops,
689 }, 689 },
690}; 690};
691 691
@@ -709,7 +709,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
709 .name = "gcc_sdcc4_apps_clk_src", 709 .name = "gcc_sdcc4_apps_clk_src",
710 .parent_names = gcc_parent_names_0, 710 .parent_names = gcc_parent_names_0,
711 .num_parents = 4, 711 .num_parents = 4,
712 .ops = &clk_rcg2_ops, 712 .ops = &clk_rcg2_floor_ops,
713 }, 713 },
714}; 714};
715 715
diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
new file mode 100644
index 000000000000..20877214acff
--- /dev/null
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -0,0 +1,3588 @@
1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
3
4#include <linux/kernel.h>
5#include <linux/bitops.h>
6#include <linux/err.h>
7#include <linux/platform_device.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/of_device.h>
11#include <linux/clk-provider.h>
12#include <linux/regmap.h>
13#include <linux/reset-controller.h>
14
15#include <dt-bindings/clock/qcom,gcc-sm8150.h>
16
17#include "common.h"
18#include "clk-alpha-pll.h"
19#include "clk-branch.h"
20#include "clk-pll.h"
21#include "clk-rcg.h"
22#include "clk-regmap.h"
23#include "reset.h"
24
25enum {
26 P_BI_TCXO,
27 P_AUD_REF_CLK,
28 P_CORE_BI_PLL_TEST_SE,
29 P_GPLL0_OUT_EVEN,
30 P_GPLL0_OUT_MAIN,
31 P_GPLL7_OUT_MAIN,
32 P_GPLL9_OUT_MAIN,
33 P_SLEEP_CLK,
34};
35
36static const struct pll_vco trion_vco[] = {
37 { 249600000, 2000000000, 0 },
38};
39
40static struct clk_alpha_pll gpll0 = {
41 .offset = 0x0,
42 .vco_table = trion_vco,
43 .num_vco = ARRAY_SIZE(trion_vco),
44 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
45 .clkr = {
46 .enable_reg = 0x52000,
47 .enable_mask = BIT(0),
48 .hw.init = &(struct clk_init_data){
49 .name = "gpll0",
50 .parent_data = &(const struct clk_parent_data){
51 .fw_name = "bi_tcxo",
52 .name = "bi_tcxo",
53 },
54 .num_parents = 1,
55 .ops = &clk_trion_fixed_pll_ops,
56 },
57 },
58};
59
60static const struct clk_div_table post_div_table_trion_even[] = {
61 { 0x0, 1 },
62 { 0x1, 2 },
63 { 0x3, 4 },
64 { 0x7, 8 },
65 { }
66};
67
68static struct clk_alpha_pll_postdiv gpll0_out_even = {
69 .offset = 0x0,
70 .post_div_shift = 8,
71 .post_div_table = post_div_table_trion_even,
72 .num_post_div = ARRAY_SIZE(post_div_table_trion_even),
73 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
74 .width = 4,
75 .clkr.hw.init = &(struct clk_init_data){
76 .name = "gpll0_out_even",
77 .parent_data = &(const struct clk_parent_data){
78 .fw_name = "bi_tcxo",
79 .name = "bi_tcxo",
80 },
81 .num_parents = 1,
82 .ops = &clk_trion_pll_postdiv_ops,
83 },
84};
85
86static struct clk_alpha_pll gpll7 = {
87 .offset = 0x1a000,
88 .vco_table = trion_vco,
89 .num_vco = ARRAY_SIZE(trion_vco),
90 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
91 .clkr = {
92 .enable_reg = 0x52000,
93 .enable_mask = BIT(7),
94 .hw.init = &(struct clk_init_data){
95 .name = "gpll7",
96 .parent_data = &(const struct clk_parent_data){
97 .fw_name = "bi_tcxo",
98 .name = "bi_tcxo",
99 },
100 .num_parents = 1,
101 .ops = &clk_trion_fixed_pll_ops,
102 },
103 },
104};
105
106static struct clk_alpha_pll gpll9 = {
107 .offset = 0x1c000,
108 .vco_table = trion_vco,
109 .num_vco = ARRAY_SIZE(trion_vco),
110 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
111 .clkr = {
112 .enable_reg = 0x52000,
113 .enable_mask = BIT(9),
114 .hw.init = &(struct clk_init_data){
115 .name = "gpll9",
116 .parent_data = &(const struct clk_parent_data){
117 .fw_name = "bi_tcxo",
118 .name = "bi_tcxo",
119 },
120 .num_parents = 1,
121 .ops = &clk_trion_fixed_pll_ops,
122 },
123 },
124};
125
126static const struct parent_map gcc_parent_map_0[] = {
127 { P_BI_TCXO, 0 },
128 { P_GPLL0_OUT_MAIN, 1 },
129 { P_GPLL0_OUT_EVEN, 6 },
130 { P_CORE_BI_PLL_TEST_SE, 7 },
131};
132
133static const struct clk_parent_data gcc_parents_0[] = {
134 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
135 { .hw = &gpll0.clkr.hw },
136 { .hw = &gpll0_out_even.clkr.hw },
137 { .fw_name = "core_bi_pll_test_se" },
138};
139
140static const struct parent_map gcc_parent_map_1[] = {
141 { P_BI_TCXO, 0 },
142 { P_GPLL0_OUT_MAIN, 1 },
143 { P_SLEEP_CLK, 5 },
144 { P_GPLL0_OUT_EVEN, 6 },
145 { P_CORE_BI_PLL_TEST_SE, 7 },
146};
147
148static const struct clk_parent_data gcc_parents_1[] = {
149 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
150 { .hw = &gpll0.clkr.hw },
151 { .fw_name = "sleep_clk", .name = "sleep_clk" },
152 { .hw = &gpll0_out_even.clkr.hw },
153 { .fw_name = "core_bi_pll_test_se" },
154};
155
156static const struct parent_map gcc_parent_map_2[] = {
157 { P_BI_TCXO, 0 },
158 { P_SLEEP_CLK, 5 },
159 { P_CORE_BI_PLL_TEST_SE, 7 },
160};
161
162static const struct clk_parent_data gcc_parents_2[] = {
163 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
164 { .fw_name = "sleep_clk", .name = "sleep_clk" },
165 { .fw_name = "core_bi_pll_test_se" },
166};
167
168static const struct parent_map gcc_parent_map_3[] = {
169 { P_BI_TCXO, 0 },
170 { P_GPLL0_OUT_MAIN, 1 },
171 { P_CORE_BI_PLL_TEST_SE, 7 },
172};
173
174static const struct clk_parent_data gcc_parents_3[] = {
175 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
176 { .hw = &gpll0.clkr.hw },
177 { .fw_name = "core_bi_pll_test_se"},
178};
179
180static const struct parent_map gcc_parent_map_4[] = {
181 { P_BI_TCXO, 0 },
182 { P_CORE_BI_PLL_TEST_SE, 7 },
183};
184
185static const struct clk_parent_data gcc_parents_4[] = {
186 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
187 { .fw_name = "core_bi_pll_test_se" },
188};
189
190static const struct parent_map gcc_parent_map_5[] = {
191 { P_BI_TCXO, 0 },
192 { P_GPLL0_OUT_MAIN, 1 },
193 { P_GPLL7_OUT_MAIN, 3 },
194 { P_GPLL0_OUT_EVEN, 6 },
195 { P_CORE_BI_PLL_TEST_SE, 7 },
196};
197
198static const struct clk_parent_data gcc_parents_5[] = {
199 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
200 { .hw = &gpll0.clkr.hw },
201 { .hw = &gpll7.clkr.hw },
202 { .hw = &gpll0_out_even.clkr.hw },
203 { .fw_name = "core_bi_pll_test_se" },
204};
205
206static const struct parent_map gcc_parent_map_6[] = {
207 { P_BI_TCXO, 0 },
208 { P_GPLL0_OUT_MAIN, 1 },
209 { P_GPLL9_OUT_MAIN, 2 },
210 { P_GPLL0_OUT_EVEN, 6 },
211 { P_CORE_BI_PLL_TEST_SE, 7 },
212};
213
214static const struct clk_parent_data gcc_parents_6[] = {
215 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
216 { .hw = &gpll0.clkr.hw },
217 { .hw = &gpll9.clkr.hw },
218 { .hw = &gpll0_out_even.clkr.hw },
219 { .fw_name = "core_bi_pll_test_se" },
220};
221
222static const struct parent_map gcc_parent_map_7[] = {
223 { P_BI_TCXO, 0 },
224 { P_GPLL0_OUT_MAIN, 1 },
225 { P_AUD_REF_CLK, 2 },
226 { P_GPLL0_OUT_EVEN, 6 },
227 { P_CORE_BI_PLL_TEST_SE, 7 },
228};
229
230static const struct clk_parent_data gcc_parents_7[] = {
231 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
232 { .hw = &gpll0.clkr.hw },
233 { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
234 { .hw = &gpll0_out_even.clkr.hw },
235 { .fw_name = "core_bi_pll_test_se" },
236};
237
238static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
239 F(19200000, P_BI_TCXO, 1, 0, 0),
240 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
241 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
242 { }
243};
244
245static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
246 .cmd_rcgr = 0x48014,
247 .mnd_width = 0,
248 .hid_width = 5,
249 .parent_map = gcc_parent_map_0,
250 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
251 .clkr.hw.init = &(struct clk_init_data){
252 .name = "gcc_cpuss_ahb_clk_src",
253 .parent_data = gcc_parents_0,
254 .num_parents = 4,
255 .flags = CLK_SET_RATE_PARENT,
256 .ops = &clk_rcg2_ops,
257 },
258};
259
260static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
261 F(19200000, P_BI_TCXO, 1, 0, 0),
262 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
263 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
264 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
265 { }
266};
267
268static struct clk_rcg2 gcc_emac_ptp_clk_src = {
269 .cmd_rcgr = 0x6038,
270 .mnd_width = 0,
271 .hid_width = 5,
272 .parent_map = gcc_parent_map_5,
273 .freq_tbl = ftbl_gcc_emac_ptp_clk_src,
274 .clkr.hw.init = &(struct clk_init_data){
275 .name = "gcc_emac_ptp_clk_src",
276 .parent_data = gcc_parents_5,
277 .num_parents = 5,
278 .flags = CLK_SET_RATE_PARENT,
279 .ops = &clk_rcg2_ops,
280 },
281};
282
283static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
284 F(2500000, P_BI_TCXO, 1, 25, 192),
285 F(5000000, P_BI_TCXO, 1, 25, 96),
286 F(19200000, P_BI_TCXO, 1, 0, 0),
287 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
288 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
289 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
290 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
291 { }
292};
293
294static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
295 .cmd_rcgr = 0x601c,
296 .mnd_width = 8,
297 .hid_width = 5,
298 .parent_map = gcc_parent_map_5,
299 .freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
300 .clkr.hw.init = &(struct clk_init_data){
301 .name = "gcc_emac_rgmii_clk_src",
302 .parent_data = gcc_parents_5,
303 .num_parents = 5,
304 .flags = CLK_SET_RATE_PARENT,
305 .ops = &clk_rcg2_ops,
306 },
307};
308
309static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
310 F(19200000, P_BI_TCXO, 1, 0, 0),
311 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
312 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
313 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
314 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
315 { }
316};
317
318static struct clk_rcg2 gcc_gp1_clk_src = {
319 .cmd_rcgr = 0x64004,
320 .mnd_width = 8,
321 .hid_width = 5,
322 .parent_map = gcc_parent_map_1,
323 .freq_tbl = ftbl_gcc_gp1_clk_src,
324 .clkr.hw.init = &(struct clk_init_data){
325 .name = "gcc_gp1_clk_src",
326 .parent_data = gcc_parents_1,
327 .num_parents = 5,
328 .flags = CLK_SET_RATE_PARENT,
329 .ops = &clk_rcg2_ops,
330 },
331};
332
333static struct clk_rcg2 gcc_gp2_clk_src = {
334 .cmd_rcgr = 0x65004,
335 .mnd_width = 8,
336 .hid_width = 5,
337 .parent_map = gcc_parent_map_1,
338 .freq_tbl = ftbl_gcc_gp1_clk_src,
339 .clkr.hw.init = &(struct clk_init_data){
340 .name = "gcc_gp2_clk_src",
341 .parent_data = gcc_parents_1,
342 .num_parents = 5,
343 .flags = CLK_SET_RATE_PARENT,
344 .ops = &clk_rcg2_ops,
345 },
346};
347
348static struct clk_rcg2 gcc_gp3_clk_src = {
349 .cmd_rcgr = 0x66004,
350 .mnd_width = 8,
351 .hid_width = 5,
352 .parent_map = gcc_parent_map_1,
353 .freq_tbl = ftbl_gcc_gp1_clk_src,
354 .clkr.hw.init = &(struct clk_init_data){
355 .name = "gcc_gp3_clk_src",
356 .parent_data = gcc_parents_1,
357 .num_parents = 5,
358 .flags = CLK_SET_RATE_PARENT,
359 .ops = &clk_rcg2_ops,
360 },
361};
362
363static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
364 F(9600000, P_BI_TCXO, 2, 0, 0),
365 F(19200000, P_BI_TCXO, 1, 0, 0),
366 { }
367};
368
369static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
370 .cmd_rcgr = 0x6b02c,
371 .mnd_width = 16,
372 .hid_width = 5,
373 .parent_map = gcc_parent_map_2,
374 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
375 .clkr.hw.init = &(struct clk_init_data){
376 .name = "gcc_pcie_0_aux_clk_src",
377 .parent_data = gcc_parents_2,
378 .num_parents = 3,
379 .flags = CLK_SET_RATE_PARENT,
380 .ops = &clk_rcg2_ops,
381 },
382};
383
384static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
385 .cmd_rcgr = 0x8d02c,
386 .mnd_width = 16,
387 .hid_width = 5,
388 .parent_map = gcc_parent_map_2,
389 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
390 .clkr.hw.init = &(struct clk_init_data){
391 .name = "gcc_pcie_1_aux_clk_src",
392 .parent_data = gcc_parents_2,
393 .num_parents = 3,
394 .flags = CLK_SET_RATE_PARENT,
395 .ops = &clk_rcg2_ops,
396 },
397};
398
399static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
400 F(19200000, P_BI_TCXO, 1, 0, 0),
401 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
402 { }
403};
404
405static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
406 .cmd_rcgr = 0x6f014,
407 .mnd_width = 0,
408 .hid_width = 5,
409 .parent_map = gcc_parent_map_0,
410 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
411 .clkr.hw.init = &(struct clk_init_data){
412 .name = "gcc_pcie_phy_refgen_clk_src",
413 .parent_data = gcc_parents_0,
414 .num_parents = 4,
415 .flags = CLK_SET_RATE_PARENT,
416 .ops = &clk_rcg2_ops,
417 },
418};
419
420static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
421 F(9600000, P_BI_TCXO, 2, 0, 0),
422 F(19200000, P_BI_TCXO, 1, 0, 0),
423 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
424 { }
425};
426
427static struct clk_rcg2 gcc_pdm2_clk_src = {
428 .cmd_rcgr = 0x33010,
429 .mnd_width = 0,
430 .hid_width = 5,
431 .parent_map = gcc_parent_map_0,
432 .freq_tbl = ftbl_gcc_pdm2_clk_src,
433 .clkr.hw.init = &(struct clk_init_data){
434 .name = "gcc_pdm2_clk_src",
435 .parent_data = gcc_parents_0,
436 .num_parents = 4,
437 .flags = CLK_SET_RATE_PARENT,
438 .ops = &clk_rcg2_ops,
439 },
440};
441
442static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
443 F(19200000, P_BI_TCXO, 1, 0, 0),
444 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
445 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
446 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
447 { }
448};
449
450static struct clk_rcg2 gcc_qspi_core_clk_src = {
451 .cmd_rcgr = 0x4b008,
452 .mnd_width = 0,
453 .hid_width = 5,
454 .parent_map = gcc_parent_map_0,
455 .freq_tbl = ftbl_gcc_qspi_core_clk_src,
456 .clkr.hw.init = &(struct clk_init_data){
457 .name = "gcc_qspi_core_clk_src",
458 .parent_data = gcc_parents_0,
459 .num_parents = 4,
460 .flags = CLK_SET_RATE_PARENT,
461 .ops = &clk_rcg2_ops,
462 },
463};
464
465static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
466 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
467 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
468 F(19200000, P_BI_TCXO, 1, 0, 0),
469 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
470 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
471 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
472 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
473 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
474 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
475 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
476 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
477 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
478 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
479 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
480 F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
481 { }
482};
483
484static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
485 .cmd_rcgr = 0x17148,
486 .mnd_width = 16,
487 .hid_width = 5,
488 .parent_map = gcc_parent_map_0,
489 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
490 .clkr.hw.init = &(struct clk_init_data){
491 .name = "gcc_qupv3_wrap0_s0_clk_src",
492 .parent_data = gcc_parents_0,
493 .num_parents = 4,
494 .flags = CLK_SET_RATE_PARENT,
495 .ops = &clk_rcg2_ops,
496 },
497};
498
499static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
500 .cmd_rcgr = 0x17278,
501 .mnd_width = 16,
502 .hid_width = 5,
503 .parent_map = gcc_parent_map_0,
504 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
505 .clkr.hw.init = &(struct clk_init_data){
506 .name = "gcc_qupv3_wrap0_s1_clk_src",
507 .parent_data = gcc_parents_0,
508 .num_parents = 4,
509 .flags = CLK_SET_RATE_PARENT,
510 .ops = &clk_rcg2_ops,
511 },
512};
513
514static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
515 .cmd_rcgr = 0x173a8,
516 .mnd_width = 16,
517 .hid_width = 5,
518 .parent_map = gcc_parent_map_0,
519 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
520 .clkr.hw.init = &(struct clk_init_data){
521 .name = "gcc_qupv3_wrap0_s2_clk_src",
522 .parent_data = gcc_parents_0,
523 .num_parents = 4,
524 .flags = CLK_SET_RATE_PARENT,
525 .ops = &clk_rcg2_ops,
526 },
527};
528
529static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
530 .cmd_rcgr = 0x174d8,
531 .mnd_width = 16,
532 .hid_width = 5,
533 .parent_map = gcc_parent_map_0,
534 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
535 .clkr.hw.init = &(struct clk_init_data){
536 .name = "gcc_qupv3_wrap0_s3_clk_src",
537 .parent_data = gcc_parents_0,
538 .num_parents = 4,
539 .flags = CLK_SET_RATE_PARENT,
540 .ops = &clk_rcg2_ops,
541 },
542};
543
544static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
545 .cmd_rcgr = 0x17608,
546 .mnd_width = 16,
547 .hid_width = 5,
548 .parent_map = gcc_parent_map_0,
549 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
550 .clkr.hw.init = &(struct clk_init_data){
551 .name = "gcc_qupv3_wrap0_s4_clk_src",
552 .parent_data = gcc_parents_0,
553 .num_parents = 4,
554 .flags = CLK_SET_RATE_PARENT,
555 .ops = &clk_rcg2_ops,
556 },
557};
558
559static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
560 .cmd_rcgr = 0x17738,
561 .mnd_width = 16,
562 .hid_width = 5,
563 .parent_map = gcc_parent_map_0,
564 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
565 .clkr.hw.init = &(struct clk_init_data){
566 .name = "gcc_qupv3_wrap0_s5_clk_src",
567 .parent_data = gcc_parents_0,
568 .num_parents = 4,
569 .flags = CLK_SET_RATE_PARENT,
570 .ops = &clk_rcg2_ops,
571 },
572};
573
574static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
575 .cmd_rcgr = 0x17868,
576 .mnd_width = 16,
577 .hid_width = 5,
578 .parent_map = gcc_parent_map_0,
579 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
580 .clkr.hw.init = &(struct clk_init_data){
581 .name = "gcc_qupv3_wrap0_s6_clk_src",
582 .parent_data = gcc_parents_0,
583 .num_parents = 4,
584 .flags = CLK_SET_RATE_PARENT,
585 .ops = &clk_rcg2_ops,
586 },
587};
588
589static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
590 .cmd_rcgr = 0x17998,
591 .mnd_width = 16,
592 .hid_width = 5,
593 .parent_map = gcc_parent_map_0,
594 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
595 .clkr.hw.init = &(struct clk_init_data){
596 .name = "gcc_qupv3_wrap0_s7_clk_src",
597 .parent_data = gcc_parents_0,
598 .num_parents = 4,
599 .flags = CLK_SET_RATE_PARENT,
600 .ops = &clk_rcg2_ops,
601 },
602};
603
604static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
605 .cmd_rcgr = 0x18148,
606 .mnd_width = 16,
607 .hid_width = 5,
608 .parent_map = gcc_parent_map_0,
609 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
610 .clkr.hw.init = &(struct clk_init_data){
611 .name = "gcc_qupv3_wrap1_s0_clk_src",
612 .parent_data = gcc_parents_0,
613 .num_parents = 4,
614 .flags = CLK_SET_RATE_PARENT,
615 .ops = &clk_rcg2_ops,
616 },
617};
618
619static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
620 .cmd_rcgr = 0x18278,
621 .mnd_width = 16,
622 .hid_width = 5,
623 .parent_map = gcc_parent_map_0,
624 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
625 .clkr.hw.init = &(struct clk_init_data){
626 .name = "gcc_qupv3_wrap1_s1_clk_src",
627 .parent_data = gcc_parents_0,
628 .num_parents = 4,
629 .flags = CLK_SET_RATE_PARENT,
630 .ops = &clk_rcg2_ops,
631 },
632};
633
634static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
635 .cmd_rcgr = 0x183a8,
636 .mnd_width = 16,
637 .hid_width = 5,
638 .parent_map = gcc_parent_map_0,
639 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
640 .clkr.hw.init = &(struct clk_init_data){
641 .name = "gcc_qupv3_wrap1_s2_clk_src",
642 .parent_data = gcc_parents_0,
643 .num_parents = 4,
644 .flags = CLK_SET_RATE_PARENT,
645 .ops = &clk_rcg2_ops,
646 },
647};
648
649static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
650 .cmd_rcgr = 0x184d8,
651 .mnd_width = 16,
652 .hid_width = 5,
653 .parent_map = gcc_parent_map_0,
654 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
655 .clkr.hw.init = &(struct clk_init_data){
656 .name = "gcc_qupv3_wrap1_s3_clk_src",
657 .parent_data = gcc_parents_0,
658 .num_parents = 4,
659 .flags = CLK_SET_RATE_PARENT,
660 .ops = &clk_rcg2_ops,
661 },
662};
663
664static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
665 .cmd_rcgr = 0x18608,
666 .mnd_width = 16,
667 .hid_width = 5,
668 .parent_map = gcc_parent_map_0,
669 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
670 .clkr.hw.init = &(struct clk_init_data){
671 .name = "gcc_qupv3_wrap1_s4_clk_src",
672 .parent_data = gcc_parents_0,
673 .num_parents = 4,
674 .flags = CLK_SET_RATE_PARENT,
675 .ops = &clk_rcg2_ops,
676 },
677};
678
679static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
680 .cmd_rcgr = 0x18738,
681 .mnd_width = 16,
682 .hid_width = 5,
683 .parent_map = gcc_parent_map_0,
684 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
685 .clkr.hw.init = &(struct clk_init_data){
686 .name = "gcc_qupv3_wrap1_s5_clk_src",
687 .parent_data = gcc_parents_0,
688 .num_parents = 4,
689 .flags = CLK_SET_RATE_PARENT,
690 .ops = &clk_rcg2_ops,
691 },
692};
693
694static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
695 .cmd_rcgr = 0x1e148,
696 .mnd_width = 16,
697 .hid_width = 5,
698 .parent_map = gcc_parent_map_0,
699 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
700 .clkr.hw.init = &(struct clk_init_data){
701 .name = "gcc_qupv3_wrap2_s0_clk_src",
702 .parent_data = gcc_parents_0,
703 .num_parents = 4,
704 .flags = CLK_SET_RATE_PARENT,
705 .ops = &clk_rcg2_ops,
706 },
707};
708
709static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
710 .cmd_rcgr = 0x1e278,
711 .mnd_width = 16,
712 .hid_width = 5,
713 .parent_map = gcc_parent_map_0,
714 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
715 .clkr.hw.init = &(struct clk_init_data){
716 .name = "gcc_qupv3_wrap2_s1_clk_src",
717 .parent_data = gcc_parents_0,
718 .num_parents = 4,
719 .flags = CLK_SET_RATE_PARENT,
720 .ops = &clk_rcg2_ops,
721 },
722};
723
724static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
725 .cmd_rcgr = 0x1e3a8,
726 .mnd_width = 16,
727 .hid_width = 5,
728 .parent_map = gcc_parent_map_0,
729 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
730 .clkr.hw.init = &(struct clk_init_data){
731 .name = "gcc_qupv3_wrap2_s2_clk_src",
732 .parent_data = gcc_parents_0,
733 .num_parents = 4,
734 .flags = CLK_SET_RATE_PARENT,
735 .ops = &clk_rcg2_ops,
736 },
737};
738
739static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
740 .cmd_rcgr = 0x1e4d8,
741 .mnd_width = 16,
742 .hid_width = 5,
743 .parent_map = gcc_parent_map_0,
744 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
745 .clkr.hw.init = &(struct clk_init_data){
746 .name = "gcc_qupv3_wrap2_s3_clk_src",
747 .parent_data = gcc_parents_0,
748 .num_parents = 4,
749 .flags = CLK_SET_RATE_PARENT,
750 .ops = &clk_rcg2_ops,
751 },
752};
753
754static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
755 .cmd_rcgr = 0x1e608,
756 .mnd_width = 16,
757 .hid_width = 5,
758 .parent_map = gcc_parent_map_0,
759 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
760 .clkr.hw.init = &(struct clk_init_data){
761 .name = "gcc_qupv3_wrap2_s4_clk_src",
762 .parent_data = gcc_parents_0,
763 .num_parents = 4,
764 .flags = CLK_SET_RATE_PARENT,
765 .ops = &clk_rcg2_ops,
766 },
767};
768
769static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
770 .cmd_rcgr = 0x1e738,
771 .mnd_width = 16,
772 .hid_width = 5,
773 .parent_map = gcc_parent_map_0,
774 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
775 .clkr.hw.init = &(struct clk_init_data){
776 .name = "gcc_qupv3_wrap2_s5_clk_src",
777 .parent_data = gcc_parents_0,
778 .num_parents = 4,
779 .flags = CLK_SET_RATE_PARENT,
780 .ops = &clk_rcg2_ops,
781 },
782};
783
784static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
785 F(400000, P_BI_TCXO, 12, 1, 4),
786 F(9600000, P_BI_TCXO, 2, 0, 0),
787 F(19200000, P_BI_TCXO, 1, 0, 0),
788 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
789 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
790 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
791 F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
792 { }
793};
794
795static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
796 .cmd_rcgr = 0x1400c,
797 .mnd_width = 8,
798 .hid_width = 5,
799 .parent_map = gcc_parent_map_6,
800 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "gcc_sdcc2_apps_clk_src",
803 .parent_data = gcc_parents_6,
804 .num_parents = 5,
805 .flags = CLK_SET_RATE_PARENT,
806 .ops = &clk_rcg2_floor_ops,
807 },
808};
809
810static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
811 F(400000, P_BI_TCXO, 12, 1, 4),
812 F(9600000, P_BI_TCXO, 2, 0, 0),
813 F(19200000, P_BI_TCXO, 1, 0, 0),
814 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
815 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
816 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
817 { }
818};
819
820static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
821 .cmd_rcgr = 0x1600c,
822 .mnd_width = 8,
823 .hid_width = 5,
824 .parent_map = gcc_parent_map_3,
825 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
826 .clkr.hw.init = &(struct clk_init_data){
827 .name = "gcc_sdcc4_apps_clk_src",
828 .parent_data = gcc_parents_3,
829 .num_parents = 3,
830 .flags = CLK_SET_RATE_PARENT,
831 .ops = &clk_rcg2_floor_ops,
832 },
833};
834
835static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
836 F(105495, P_BI_TCXO, 2, 1, 91),
837 { }
838};
839
840static struct clk_rcg2 gcc_tsif_ref_clk_src = {
841 .cmd_rcgr = 0x36010,
842 .mnd_width = 8,
843 .hid_width = 5,
844 .parent_map = gcc_parent_map_7,
845 .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
846 .clkr.hw.init = &(struct clk_init_data){
847 .name = "gcc_tsif_ref_clk_src",
848 .parent_data = gcc_parents_7,
849 .num_parents = 5,
850 .flags = CLK_SET_RATE_PARENT,
851 .ops = &clk_rcg2_ops,
852 },
853};
854
855static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
856 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
857 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
858 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
859 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
860 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
861 { }
862};
863
864static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
865 .cmd_rcgr = 0x75020,
866 .mnd_width = 8,
867 .hid_width = 5,
868 .parent_map = gcc_parent_map_0,
869 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
870 .clkr.hw.init = &(struct clk_init_data){
871 .name = "gcc_ufs_card_axi_clk_src",
872 .parent_data = gcc_parents_0,
873 .num_parents = 4,
874 .flags = CLK_SET_RATE_PARENT,
875 .ops = &clk_rcg2_ops,
876 },
877};
878
879static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
880 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
881 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
882 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
883 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
884 { }
885};
886
887static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
888 .cmd_rcgr = 0x75060,
889 .mnd_width = 0,
890 .hid_width = 5,
891 .parent_map = gcc_parent_map_0,
892 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
893 .clkr.hw.init = &(struct clk_init_data){
894 .name = "gcc_ufs_card_ice_core_clk_src",
895 .parent_data = gcc_parents_0,
896 .num_parents = 4,
897 .flags = CLK_SET_RATE_PARENT,
898 .ops = &clk_rcg2_ops,
899 },
900};
901
902static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
903 F(19200000, P_BI_TCXO, 1, 0, 0),
904 { }
905};
906
907static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
908 .cmd_rcgr = 0x75094,
909 .mnd_width = 0,
910 .hid_width = 5,
911 .parent_map = gcc_parent_map_4,
912 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
913 .clkr.hw.init = &(struct clk_init_data){
914 .name = "gcc_ufs_card_phy_aux_clk_src",
915 .parent_data = gcc_parents_4,
916 .num_parents = 2,
917 .flags = CLK_SET_RATE_PARENT,
918 .ops = &clk_rcg2_ops,
919 },
920};
921
922static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
923 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
924 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
925 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
926 { }
927};
928
929static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
930 .cmd_rcgr = 0x75078,
931 .mnd_width = 0,
932 .hid_width = 5,
933 .parent_map = gcc_parent_map_0,
934 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
935 .clkr.hw.init = &(struct clk_init_data){
936 .name = "gcc_ufs_card_unipro_core_clk_src",
937 .parent_data = gcc_parents_0,
938 .num_parents = 4,
939 .flags = CLK_SET_RATE_PARENT,
940 .ops = &clk_rcg2_ops,
941 },
942};
943
944static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
945 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
946 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
947 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
948 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
949 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
950 { }
951};
952
953static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
954 .cmd_rcgr = 0x77020,
955 .mnd_width = 8,
956 .hid_width = 5,
957 .parent_map = gcc_parent_map_0,
958 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
959 .clkr.hw.init = &(struct clk_init_data){
960 .name = "gcc_ufs_phy_axi_clk_src",
961 .parent_data = gcc_parents_0,
962 .num_parents = 4,
963 .flags = CLK_SET_RATE_PARENT,
964 .ops = &clk_rcg2_ops,
965 },
966};
967
968static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
969 .cmd_rcgr = 0x77060,
970 .mnd_width = 0,
971 .hid_width = 5,
972 .parent_map = gcc_parent_map_0,
973 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
974 .clkr.hw.init = &(struct clk_init_data){
975 .name = "gcc_ufs_phy_ice_core_clk_src",
976 .parent_data = gcc_parents_0,
977 .num_parents = 4,
978 .flags = CLK_SET_RATE_PARENT,
979 .ops = &clk_rcg2_ops,
980 },
981};
982
983static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
984 .cmd_rcgr = 0x77094,
985 .mnd_width = 0,
986 .hid_width = 5,
987 .parent_map = gcc_parent_map_4,
988 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
989 .clkr.hw.init = &(struct clk_init_data){
990 .name = "gcc_ufs_phy_phy_aux_clk_src",
991 .parent_data = gcc_parents_4,
992 .num_parents = 2,
993 .flags = CLK_SET_RATE_PARENT,
994 .ops = &clk_rcg2_ops,
995 },
996};
997
998static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
999 .cmd_rcgr = 0x77078,
1000 .mnd_width = 0,
1001 .hid_width = 5,
1002 .parent_map = gcc_parent_map_0,
1003 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1004 .clkr.hw.init = &(struct clk_init_data){
1005 .name = "gcc_ufs_phy_unipro_core_clk_src",
1006 .parent_data = gcc_parents_0,
1007 .num_parents = 4,
1008 .flags = CLK_SET_RATE_PARENT,
1009 .ops = &clk_rcg2_ops,
1010 },
1011};
1012
1013static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1014 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
1015 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
1016 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1017 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1018 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1019 { }
1020};
1021
1022static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1023 .cmd_rcgr = 0xf01c,
1024 .mnd_width = 8,
1025 .hid_width = 5,
1026 .parent_map = gcc_parent_map_0,
1027 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1028 .clkr.hw.init = &(struct clk_init_data){
1029 .name = "gcc_usb30_prim_master_clk_src",
1030 .parent_data = gcc_parents_0,
1031 .num_parents = 4,
1032 .flags = CLK_SET_RATE_PARENT,
1033 .ops = &clk_rcg2_ops,
1034 },
1035};
1036
1037static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1038 F(19200000, P_BI_TCXO, 1, 0, 0),
1039 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1040 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
1041 { }
1042};
1043
1044static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1045 .cmd_rcgr = 0xf034,
1046 .mnd_width = 0,
1047 .hid_width = 5,
1048 .parent_map = gcc_parent_map_0,
1049 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1050 .clkr.hw.init = &(struct clk_init_data){
1051 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1052 .parent_data = gcc_parents_0,
1053 .num_parents = 4,
1054 .flags = CLK_SET_RATE_PARENT,
1055 .ops = &clk_rcg2_ops,
1056 },
1057};
1058
1059static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1060 .cmd_rcgr = 0x1001c,
1061 .mnd_width = 8,
1062 .hid_width = 5,
1063 .parent_map = gcc_parent_map_0,
1064 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1065 .clkr.hw.init = &(struct clk_init_data){
1066 .name = "gcc_usb30_sec_master_clk_src",
1067 .parent_data = gcc_parents_0,
1068 .num_parents = 4,
1069 .flags = CLK_SET_RATE_PARENT,
1070 .ops = &clk_rcg2_ops,
1071 },
1072};
1073
1074static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1075 .cmd_rcgr = 0x10034,
1076 .mnd_width = 0,
1077 .hid_width = 5,
1078 .parent_map = gcc_parent_map_0,
1079 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1080 .clkr.hw.init = &(struct clk_init_data){
1081 .name = "gcc_usb30_sec_mock_utmi_clk_src",
1082 .parent_data = gcc_parents_0,
1083 .num_parents = 4,
1084 .flags = CLK_SET_RATE_PARENT,
1085 .ops = &clk_rcg2_ops,
1086 },
1087};
1088
1089static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1090 .cmd_rcgr = 0xf060,
1091 .mnd_width = 0,
1092 .hid_width = 5,
1093 .parent_map = gcc_parent_map_2,
1094 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1095 .clkr.hw.init = &(struct clk_init_data){
1096 .name = "gcc_usb3_prim_phy_aux_clk_src",
1097 .parent_data = gcc_parents_2,
1098 .num_parents = 3,
1099 .flags = CLK_SET_RATE_PARENT,
1100 .ops = &clk_rcg2_ops,
1101 },
1102};
1103
1104static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1105 .cmd_rcgr = 0x10060,
1106 .mnd_width = 0,
1107 .hid_width = 5,
1108 .parent_map = gcc_parent_map_2,
1109 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1110 .clkr.hw.init = &(struct clk_init_data){
1111 .name = "gcc_usb3_sec_phy_aux_clk_src",
1112 .parent_data = gcc_parents_2,
1113 .num_parents = 3,
1114 .flags = CLK_SET_RATE_PARENT,
1115 .ops = &clk_rcg2_ops,
1116 },
1117};
1118
1119static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1120 .halt_reg = 0x90018,
1121 .halt_check = BRANCH_HALT,
1122 .clkr = {
1123 .enable_reg = 0x90018,
1124 .enable_mask = BIT(0),
1125 .hw.init = &(struct clk_init_data){
1126 .name = "gcc_aggre_noc_pcie_tbu_clk",
1127 .ops = &clk_branch2_ops,
1128 },
1129 },
1130};
1131
1132static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1133 .halt_reg = 0x750c0,
1134 .halt_check = BRANCH_HALT,
1135 .hwcg_reg = 0x750c0,
1136 .hwcg_bit = 1,
1137 .clkr = {
1138 .enable_reg = 0x750c0,
1139 .enable_mask = BIT(0),
1140 .hw.init = &(struct clk_init_data){
1141 .name = "gcc_aggre_ufs_card_axi_clk",
1142 .parent_hws = (const struct clk_hw *[]){
1143 &gcc_ufs_card_axi_clk_src.clkr.hw },
1144 .num_parents = 1,
1145 .flags = CLK_SET_RATE_PARENT,
1146 .ops = &clk_branch2_ops,
1147 },
1148 },
1149};
1150
1151static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
1152 .halt_reg = 0x750c0,
1153 .halt_check = BRANCH_HALT,
1154 .hwcg_reg = 0x750c0,
1155 .hwcg_bit = 1,
1156 .clkr = {
1157 .enable_reg = 0x750c0,
1158 .enable_mask = BIT(1),
1159 .hw.init = &(struct clk_init_data){
1160 .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
1161 .parent_hws = (const struct clk_hw *[]){
1162 &gcc_aggre_ufs_card_axi_clk.clkr.hw },
1163 .num_parents = 1,
1164 .flags = CLK_SET_RATE_PARENT,
1165 .ops = &clk_branch_simple_ops,
1166 },
1167 },
1168};
1169
1170static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1171 .halt_reg = 0x770c0,
1172 .halt_check = BRANCH_HALT,
1173 .hwcg_reg = 0x770c0,
1174 .hwcg_bit = 1,
1175 .clkr = {
1176 .enable_reg = 0x770c0,
1177 .enable_mask = BIT(0),
1178 .hw.init = &(struct clk_init_data){
1179 .name = "gcc_aggre_ufs_phy_axi_clk",
1180 .parent_hws = (const struct clk_hw *[]){
1181 &gcc_ufs_phy_axi_clk_src.clkr.hw },
1182 .num_parents = 1,
1183 .flags = CLK_SET_RATE_PARENT,
1184 .ops = &clk_branch2_ops,
1185 },
1186 },
1187};
1188
1189static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1190 .halt_reg = 0x770c0,
1191 .halt_check = BRANCH_HALT,
1192 .hwcg_reg = 0x770c0,
1193 .hwcg_bit = 1,
1194 .clkr = {
1195 .enable_reg = 0x770c0,
1196 .enable_mask = BIT(1),
1197 .hw.init = &(struct clk_init_data){
1198 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1199 .parent_hws = (const struct clk_hw *[]){
1200 &gcc_aggre_ufs_phy_axi_clk.clkr.hw },
1201 .num_parents = 1,
1202 .flags = CLK_SET_RATE_PARENT,
1203 .ops = &clk_branch_simple_ops,
1204 },
1205 },
1206};
1207
1208static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1209 .halt_reg = 0xf07c,
1210 .halt_check = BRANCH_HALT,
1211 .clkr = {
1212 .enable_reg = 0xf07c,
1213 .enable_mask = BIT(0),
1214 .hw.init = &(struct clk_init_data){
1215 .name = "gcc_aggre_usb3_prim_axi_clk",
1216 .parent_hws = (const struct clk_hw *[]){
1217 &gcc_usb30_prim_master_clk_src.clkr.hw },
1218 .num_parents = 1,
1219 .flags = CLK_SET_RATE_PARENT,
1220 .ops = &clk_branch2_ops,
1221 },
1222 },
1223};
1224
1225static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1226 .halt_reg = 0x1007c,
1227 .halt_check = BRANCH_HALT,
1228 .clkr = {
1229 .enable_reg = 0x1007c,
1230 .enable_mask = BIT(0),
1231 .hw.init = &(struct clk_init_data){
1232 .name = "gcc_aggre_usb3_sec_axi_clk",
1233 .parent_hws = (const struct clk_hw *[]){
1234 &gcc_usb30_sec_master_clk_src.clkr.hw },
1235 .num_parents = 1,
1236 .flags = CLK_SET_RATE_PARENT,
1237 .ops = &clk_branch2_ops,
1238 },
1239 },
1240};
1241
1242static struct clk_branch gcc_boot_rom_ahb_clk = {
1243 .halt_reg = 0x38004,
1244 .halt_check = BRANCH_HALT_VOTED,
1245 .hwcg_reg = 0x38004,
1246 .hwcg_bit = 1,
1247 .clkr = {
1248 .enable_reg = 0x52004,
1249 .enable_mask = BIT(10),
1250 .hw.init = &(struct clk_init_data){
1251 .name = "gcc_boot_rom_ahb_clk",
1252 .ops = &clk_branch2_ops,
1253 },
1254 },
1255};
1256
1257/*
1258 * Clock ON depends on external parent 'config noc', so cant poll
1259 * delay and also mark as crtitical for camss boot
1260 */
1261static struct clk_branch gcc_camera_ahb_clk = {
1262 .halt_reg = 0xb008,
1263 .halt_check = BRANCH_HALT_DELAY,
1264 .hwcg_reg = 0xb008,
1265 .hwcg_bit = 1,
1266 .clkr = {
1267 .enable_reg = 0xb008,
1268 .enable_mask = BIT(0),
1269 .hw.init = &(struct clk_init_data){
1270 .name = "gcc_camera_ahb_clk",
1271 .flags = CLK_IS_CRITICAL,
1272 .ops = &clk_branch2_ops,
1273 },
1274 },
1275};
1276
1277static struct clk_branch gcc_camera_hf_axi_clk = {
1278 .halt_reg = 0xb030,
1279 .halt_check = BRANCH_HALT,
1280 .clkr = {
1281 .enable_reg = 0xb030,
1282 .enable_mask = BIT(0),
1283 .hw.init = &(struct clk_init_data){
1284 .name = "gcc_camera_hf_axi_clk",
1285 .ops = &clk_branch2_ops,
1286 },
1287 },
1288};
1289
1290static struct clk_branch gcc_camera_sf_axi_clk = {
1291 .halt_reg = 0xb034,
1292 .halt_check = BRANCH_HALT,
1293 .clkr = {
1294 .enable_reg = 0xb034,
1295 .enable_mask = BIT(0),
1296 .hw.init = &(struct clk_init_data){
1297 .name = "gcc_camera_sf_axi_clk",
1298 .ops = &clk_branch2_ops,
1299 },
1300 },
1301};
1302
1303/* XO critical input to camss, so no need to poll */
1304static struct clk_branch gcc_camera_xo_clk = {
1305 .halt_reg = 0xb044,
1306 .halt_check = BRANCH_HALT_DELAY,
1307 .clkr = {
1308 .enable_reg = 0xb044,
1309 .enable_mask = BIT(0),
1310 .hw.init = &(struct clk_init_data){
1311 .name = "gcc_camera_xo_clk",
1312 .flags = CLK_IS_CRITICAL,
1313 .ops = &clk_branch2_ops,
1314 },
1315 },
1316};
1317
1318static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1319 .halt_reg = 0xf078,
1320 .halt_check = BRANCH_HALT,
1321 .clkr = {
1322 .enable_reg = 0xf078,
1323 .enable_mask = BIT(0),
1324 .hw.init = &(struct clk_init_data){
1325 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1326 .parent_hws = (const struct clk_hw *[]){
1327 &gcc_usb30_prim_master_clk_src.clkr.hw },
1328 .num_parents = 1,
1329 .flags = CLK_SET_RATE_PARENT,
1330 .ops = &clk_branch2_ops,
1331 },
1332 },
1333};
1334
1335static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1336 .halt_reg = 0x10078,
1337 .halt_check = BRANCH_HALT,
1338 .clkr = {
1339 .enable_reg = 0x10078,
1340 .enable_mask = BIT(0),
1341 .hw.init = &(struct clk_init_data){
1342 .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1343 .parent_hws = (const struct clk_hw *[]){
1344 &gcc_usb30_sec_master_clk_src.clkr.hw },
1345 .num_parents = 1,
1346 .flags = CLK_SET_RATE_PARENT,
1347 .ops = &clk_branch2_ops,
1348 },
1349 },
1350};
1351
1352static struct clk_branch gcc_cpuss_ahb_clk = {
1353 .halt_reg = 0x48000,
1354 .halt_check = BRANCH_HALT_VOTED,
1355 .clkr = {
1356 .enable_reg = 0x52004,
1357 .enable_mask = BIT(21),
1358 .hw.init = &(struct clk_init_data){
1359 .name = "gcc_cpuss_ahb_clk",
1360 .parent_hws = (const struct clk_hw *[]){
1361 &gcc_cpuss_ahb_clk_src.clkr.hw },
1362 .num_parents = 1,
1363 /* required for cpuss */
1364 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1365 .ops = &clk_branch2_ops,
1366 },
1367 },
1368};
1369
1370static struct clk_branch gcc_cpuss_dvm_bus_clk = {
1371 .halt_reg = 0x48190,
1372 .halt_check = BRANCH_HALT,
1373 .clkr = {
1374 .enable_reg = 0x48190,
1375 .enable_mask = BIT(0),
1376 .hw.init = &(struct clk_init_data){
1377 .name = "gcc_cpuss_dvm_bus_clk",
1378 /* required for cpuss */
1379 .flags = CLK_IS_CRITICAL,
1380 .ops = &clk_branch2_ops,
1381 },
1382 },
1383};
1384
1385static struct clk_branch gcc_cpuss_gnoc_clk = {
1386 .halt_reg = 0x48004,
1387 .halt_check = BRANCH_HALT_VOTED,
1388 .hwcg_reg = 0x48004,
1389 .hwcg_bit = 1,
1390 .clkr = {
1391 .enable_reg = 0x52004,
1392 .enable_mask = BIT(22),
1393 .hw.init = &(struct clk_init_data){
1394 .name = "gcc_cpuss_gnoc_clk",
1395 /* required for cpuss */
1396 .flags = CLK_IS_CRITICAL,
1397 .ops = &clk_branch2_ops,
1398 },
1399 },
1400};
1401
1402static struct clk_branch gcc_cpuss_rbcpr_clk = {
1403 .halt_reg = 0x48008,
1404 .halt_check = BRANCH_HALT,
1405 .clkr = {
1406 .enable_reg = 0x48008,
1407 .enable_mask = BIT(0),
1408 .hw.init = &(struct clk_init_data){
1409 .name = "gcc_cpuss_rbcpr_clk",
1410 .ops = &clk_branch2_ops,
1411 },
1412 },
1413};
1414
1415static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1416 .halt_reg = 0x71154,
1417 .halt_check = BRANCH_VOTED,
1418 .clkr = {
1419 .enable_reg = 0x71154,
1420 .enable_mask = BIT(0),
1421 .hw.init = &(struct clk_init_data){
1422 .name = "gcc_ddrss_gpu_axi_clk",
1423 .ops = &clk_branch2_ops,
1424 },
1425 },
1426};
1427
1428/*
1429 * Clock ON depends on external parent 'config noc', so cant poll
1430 * delay and also mark as crtitical for disp boot
1431 */
1432static struct clk_branch gcc_disp_ahb_clk = {
1433 .halt_reg = 0xb00c,
1434 .halt_check = BRANCH_HALT_DELAY,
1435 .hwcg_reg = 0xb00c,
1436 .hwcg_bit = 1,
1437 .clkr = {
1438 .enable_reg = 0xb00c,
1439 .enable_mask = BIT(0),
1440 .hw.init = &(struct clk_init_data){
1441 .name = "gcc_disp_ahb_clk",
1442 .flags = CLK_IS_CRITICAL,
1443 .ops = &clk_branch2_ops,
1444 },
1445 },
1446};
1447
1448static struct clk_branch gcc_disp_hf_axi_clk = {
1449 .halt_reg = 0xb038,
1450 .halt_check = BRANCH_HALT,
1451 .clkr = {
1452 .enable_reg = 0xb038,
1453 .enable_mask = BIT(0),
1454 .hw.init = &(struct clk_init_data){
1455 .name = "gcc_disp_hf_axi_clk",
1456 .ops = &clk_branch2_ops,
1457 },
1458 },
1459};
1460
1461static struct clk_branch gcc_disp_sf_axi_clk = {
1462 .halt_reg = 0xb03c,
1463 .halt_check = BRANCH_HALT,
1464 .clkr = {
1465 .enable_reg = 0xb03c,
1466 .enable_mask = BIT(0),
1467 .hw.init = &(struct clk_init_data){
1468 .name = "gcc_disp_sf_axi_clk",
1469 .ops = &clk_branch2_ops,
1470 },
1471 },
1472};
1473
1474/* XO critical input to disp, so no need to poll */
1475static struct clk_branch gcc_disp_xo_clk = {
1476 .halt_reg = 0xb048,
1477 .halt_check = BRANCH_HALT_DELAY,
1478 .clkr = {
1479 .enable_reg = 0xb048,
1480 .enable_mask = BIT(0),
1481 .hw.init = &(struct clk_init_data){
1482 .name = "gcc_disp_xo_clk",
1483 .flags = CLK_IS_CRITICAL,
1484 .ops = &clk_branch2_ops,
1485 },
1486 },
1487};
1488
1489static struct clk_branch gcc_emac_axi_clk = {
1490 .halt_reg = 0x6010,
1491 .halt_check = BRANCH_HALT,
1492 .clkr = {
1493 .enable_reg = 0x6010,
1494 .enable_mask = BIT(0),
1495 .hw.init = &(struct clk_init_data){
1496 .name = "gcc_emac_axi_clk",
1497 .ops = &clk_branch2_ops,
1498 },
1499 },
1500};
1501
1502static struct clk_branch gcc_emac_ptp_clk = {
1503 .halt_reg = 0x6034,
1504 .halt_check = BRANCH_HALT,
1505 .clkr = {
1506 .enable_reg = 0x6034,
1507 .enable_mask = BIT(0),
1508 .hw.init = &(struct clk_init_data){
1509 .name = "gcc_emac_ptp_clk",
1510 .parent_hws = (const struct clk_hw *[]){
1511 &gcc_emac_ptp_clk_src.clkr.hw },
1512 .num_parents = 1,
1513 .flags = CLK_SET_RATE_PARENT,
1514 .ops = &clk_branch2_ops,
1515 },
1516 },
1517};
1518
1519static struct clk_branch gcc_emac_rgmii_clk = {
1520 .halt_reg = 0x6018,
1521 .halt_check = BRANCH_HALT,
1522 .clkr = {
1523 .enable_reg = 0x6018,
1524 .enable_mask = BIT(0),
1525 .hw.init = &(struct clk_init_data){
1526 .name = "gcc_emac_rgmii_clk",
1527 .parent_hws = (const struct clk_hw *[]){
1528 &gcc_emac_rgmii_clk_src.clkr.hw },
1529 .num_parents = 1,
1530 .flags = CLK_SET_RATE_PARENT,
1531 .ops = &clk_branch2_ops,
1532 },
1533 },
1534};
1535
1536static struct clk_branch gcc_emac_slv_ahb_clk = {
1537 .halt_reg = 0x6014,
1538 .halt_check = BRANCH_HALT,
1539 .hwcg_reg = 0x6014,
1540 .hwcg_bit = 1,
1541 .clkr = {
1542 .enable_reg = 0x6014,
1543 .enable_mask = BIT(0),
1544 .hw.init = &(struct clk_init_data){
1545 .name = "gcc_emac_slv_ahb_clk",
1546 .ops = &clk_branch2_ops,
1547 },
1548 },
1549};
1550
1551static struct clk_branch gcc_gp1_clk = {
1552 .halt_reg = 0x64000,
1553 .halt_check = BRANCH_HALT,
1554 .clkr = {
1555 .enable_reg = 0x64000,
1556 .enable_mask = BIT(0),
1557 .hw.init = &(struct clk_init_data){
1558 .name = "gcc_gp1_clk",
1559 .parent_hws = (const struct clk_hw *[]){
1560 &gcc_gp1_clk_src.clkr.hw },
1561 .num_parents = 1,
1562 .flags = CLK_SET_RATE_PARENT,
1563 .ops = &clk_branch2_ops,
1564 },
1565 },
1566};
1567
1568static struct clk_branch gcc_gp2_clk = {
1569 .halt_reg = 0x65000,
1570 .halt_check = BRANCH_HALT,
1571 .clkr = {
1572 .enable_reg = 0x65000,
1573 .enable_mask = BIT(0),
1574 .hw.init = &(struct clk_init_data){
1575 .name = "gcc_gp2_clk",
1576 .parent_hws = (const struct clk_hw *[]){
1577 &gcc_gp2_clk_src.clkr.hw },
1578 .num_parents = 1,
1579 .flags = CLK_SET_RATE_PARENT,
1580 .ops = &clk_branch2_ops,
1581 },
1582 },
1583};
1584
1585static struct clk_branch gcc_gp3_clk = {
1586 .halt_reg = 0x66000,
1587 .halt_check = BRANCH_HALT,
1588 .clkr = {
1589 .enable_reg = 0x66000,
1590 .enable_mask = BIT(0),
1591 .hw.init = &(struct clk_init_data){
1592 .name = "gcc_gp3_clk",
1593 .parent_hws = (const struct clk_hw *[]){
1594 &gcc_gp3_clk_src.clkr.hw },
1595 .num_parents = 1,
1596 .flags = CLK_SET_RATE_PARENT,
1597 .ops = &clk_branch2_ops,
1598 },
1599 },
1600};
1601
1602static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1603 .halt_reg = 0x71004,
1604 .halt_check = BRANCH_HALT,
1605 .hwcg_reg = 0x71004,
1606 .hwcg_bit = 1,
1607 .clkr = {
1608 .enable_reg = 0x71004,
1609 .enable_mask = BIT(0),
1610 .hw.init = &(struct clk_init_data){
1611 .name = "gcc_gpu_cfg_ahb_clk",
1612 /* required for gpu */
1613 .flags = CLK_IS_CRITICAL,
1614 .ops = &clk_branch2_ops,
1615 },
1616 },
1617};
1618
1619static struct clk_branch gcc_gpu_iref_clk = {
1620 .halt_reg = 0x8c010,
1621 .halt_check = BRANCH_HALT,
1622 .clkr = {
1623 .enable_reg = 0x8c010,
1624 .enable_mask = BIT(0),
1625 .hw.init = &(struct clk_init_data){
1626 .name = "gcc_gpu_iref_clk",
1627 .ops = &clk_branch2_ops,
1628 },
1629 },
1630};
1631
1632static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1633 .halt_reg = 0x7100c,
1634 .halt_check = BRANCH_VOTED,
1635 .clkr = {
1636 .enable_reg = 0x7100c,
1637 .enable_mask = BIT(0),
1638 .hw.init = &(struct clk_init_data){
1639 .name = "gcc_gpu_memnoc_gfx_clk",
1640 .ops = &clk_branch2_ops,
1641 },
1642 },
1643};
1644
1645static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1646 .halt_reg = 0x71018,
1647 .halt_check = BRANCH_HALT,
1648 .clkr = {
1649 .enable_reg = 0x71018,
1650 .enable_mask = BIT(0),
1651 .hw.init = &(struct clk_init_data){
1652 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1653 .ops = &clk_branch2_ops,
1654 },
1655 },
1656};
1657
1658static struct clk_branch gcc_npu_at_clk = {
1659 .halt_reg = 0x4d010,
1660 .halt_check = BRANCH_VOTED,
1661 .clkr = {
1662 .enable_reg = 0x4d010,
1663 .enable_mask = BIT(0),
1664 .hw.init = &(struct clk_init_data){
1665 .name = "gcc_npu_at_clk",
1666 .ops = &clk_branch2_ops,
1667 },
1668 },
1669};
1670
1671static struct clk_branch gcc_npu_axi_clk = {
1672 .halt_reg = 0x4d008,
1673 .halt_check = BRANCH_VOTED,
1674 .clkr = {
1675 .enable_reg = 0x4d008,
1676 .enable_mask = BIT(0),
1677 .hw.init = &(struct clk_init_data){
1678 .name = "gcc_npu_axi_clk",
1679 .ops = &clk_branch2_ops,
1680 },
1681 },
1682};
1683
1684static struct clk_branch gcc_npu_cfg_ahb_clk = {
1685 .halt_reg = 0x4d004,
1686 .halt_check = BRANCH_HALT,
1687 .hwcg_reg = 0x4d004,
1688 .hwcg_bit = 1,
1689 .clkr = {
1690 .enable_reg = 0x4d004,
1691 .enable_mask = BIT(0),
1692 .hw.init = &(struct clk_init_data){
1693 .name = "gcc_npu_cfg_ahb_clk",
1694 /* required for npu */
1695 .flags = CLK_IS_CRITICAL,
1696 .ops = &clk_branch2_ops,
1697 },
1698 },
1699};
1700
1701static struct clk_branch gcc_npu_trig_clk = {
1702 .halt_reg = 0x4d00c,
1703 .halt_check = BRANCH_VOTED,
1704 .clkr = {
1705 .enable_reg = 0x4d00c,
1706 .enable_mask = BIT(0),
1707 .hw.init = &(struct clk_init_data){
1708 .name = "gcc_npu_trig_clk",
1709 .ops = &clk_branch2_ops,
1710 },
1711 },
1712};
1713
1714static struct clk_branch gcc_pcie0_phy_refgen_clk = {
1715 .halt_reg = 0x6f02c,
1716 .halt_check = BRANCH_HALT,
1717 .clkr = {
1718 .enable_reg = 0x6f02c,
1719 .enable_mask = BIT(0),
1720 .hw.init = &(struct clk_init_data){
1721 .name = "gcc_pcie0_phy_refgen_clk",
1722 .parent_hws = (const struct clk_hw *[]){
1723 &gcc_pcie_phy_refgen_clk_src.clkr.hw },
1724 .num_parents = 1,
1725 .flags = CLK_SET_RATE_PARENT,
1726 .ops = &clk_branch2_ops,
1727 },
1728 },
1729};
1730
1731static struct clk_branch gcc_pcie1_phy_refgen_clk = {
1732 .halt_reg = 0x6f030,
1733 .halt_check = BRANCH_HALT,
1734 .clkr = {
1735 .enable_reg = 0x6f030,
1736 .enable_mask = BIT(0),
1737 .hw.init = &(struct clk_init_data){
1738 .name = "gcc_pcie1_phy_refgen_clk",
1739 .parent_hws = (const struct clk_hw *[]){
1740 &gcc_pcie_phy_refgen_clk_src.clkr.hw },
1741 .num_parents = 1,
1742 .flags = CLK_SET_RATE_PARENT,
1743 .ops = &clk_branch2_ops,
1744 },
1745 },
1746};
1747
1748static struct clk_branch gcc_pcie_0_aux_clk = {
1749 .halt_reg = 0x6b020,
1750 .halt_check = BRANCH_HALT_VOTED,
1751 .clkr = {
1752 .enable_reg = 0x5200c,
1753 .enable_mask = BIT(3),
1754 .hw.init = &(struct clk_init_data){
1755 .name = "gcc_pcie_0_aux_clk",
1756 .parent_hws = (const struct clk_hw *[]){
1757 &gcc_pcie_0_aux_clk_src.clkr.hw },
1758 .num_parents = 1,
1759 .flags = CLK_SET_RATE_PARENT,
1760 .ops = &clk_branch2_ops,
1761 },
1762 },
1763};
1764
1765static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1766 .halt_reg = 0x6b01c,
1767 .halt_check = BRANCH_HALT_VOTED,
1768 .hwcg_reg = 0x6b01c,
1769 .hwcg_bit = 1,
1770 .clkr = {
1771 .enable_reg = 0x5200c,
1772 .enable_mask = BIT(2),
1773 .hw.init = &(struct clk_init_data){
1774 .name = "gcc_pcie_0_cfg_ahb_clk",
1775 .ops = &clk_branch2_ops,
1776 },
1777 },
1778};
1779
1780static struct clk_branch gcc_pcie_0_clkref_clk = {
1781 .halt_reg = 0x8c00c,
1782 .halt_check = BRANCH_HALT,
1783 .clkr = {
1784 .enable_reg = 0x8c00c,
1785 .enable_mask = BIT(0),
1786 .hw.init = &(struct clk_init_data){
1787 .name = "gcc_pcie_0_clkref_clk",
1788 .ops = &clk_branch2_ops,
1789 },
1790 },
1791};
1792
1793static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1794 .halt_reg = 0x6b018,
1795 .halt_check = BRANCH_HALT_VOTED,
1796 .clkr = {
1797 .enable_reg = 0x5200c,
1798 .enable_mask = BIT(1),
1799 .hw.init = &(struct clk_init_data){
1800 .name = "gcc_pcie_0_mstr_axi_clk",
1801 .ops = &clk_branch2_ops,
1802 },
1803 },
1804};
1805
1806/* Clock ON depends on external parent 'PIPE' clock, so dont poll */
1807static struct clk_branch gcc_pcie_0_pipe_clk = {
1808 .halt_reg = 0x6b024,
1809 .halt_check = BRANCH_HALT_DELAY,
1810 .clkr = {
1811 .enable_reg = 0x5200c,
1812 .enable_mask = BIT(4),
1813 .hw.init = &(struct clk_init_data){
1814 .name = "gcc_pcie_0_pipe_clk",
1815 .ops = &clk_branch2_ops,
1816 },
1817 },
1818};
1819
1820static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1821 .halt_reg = 0x6b014,
1822 .halt_check = BRANCH_HALT_VOTED,
1823 .hwcg_reg = 0x6b014,
1824 .hwcg_bit = 1,
1825 .clkr = {
1826 .enable_reg = 0x5200c,
1827 .enable_mask = BIT(0),
1828 .hw.init = &(struct clk_init_data){
1829 .name = "gcc_pcie_0_slv_axi_clk",
1830 .ops = &clk_branch2_ops,
1831 },
1832 },
1833};
1834
1835static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1836 .halt_reg = 0x6b010,
1837 .halt_check = BRANCH_HALT_VOTED,
1838 .clkr = {
1839 .enable_reg = 0x5200c,
1840 .enable_mask = BIT(5),
1841 .hw.init = &(struct clk_init_data){
1842 .name = "gcc_pcie_0_slv_q2a_axi_clk",
1843 .ops = &clk_branch2_ops,
1844 },
1845 },
1846};
1847
1848static struct clk_branch gcc_pcie_1_aux_clk = {
1849 .halt_reg = 0x8d020,
1850 .halt_check = BRANCH_HALT_VOTED,
1851 .clkr = {
1852 .enable_reg = 0x52004,
1853 .enable_mask = BIT(29),
1854 .hw.init = &(struct clk_init_data){
1855 .name = "gcc_pcie_1_aux_clk",
1856 .parent_hws = (const struct clk_hw *[]){
1857 &gcc_pcie_1_aux_clk_src.clkr.hw },
1858 .num_parents = 1,
1859 .flags = CLK_SET_RATE_PARENT,
1860 .ops = &clk_branch2_ops,
1861 },
1862 },
1863};
1864
1865static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1866 .halt_reg = 0x8d01c,
1867 .halt_check = BRANCH_HALT_VOTED,
1868 .hwcg_reg = 0x8d01c,
1869 .hwcg_bit = 1,
1870 .clkr = {
1871 .enable_reg = 0x52004,
1872 .enable_mask = BIT(28),
1873 .hw.init = &(struct clk_init_data){
1874 .name = "gcc_pcie_1_cfg_ahb_clk",
1875 .ops = &clk_branch2_ops,
1876 },
1877 },
1878};
1879
1880static struct clk_branch gcc_pcie_1_clkref_clk = {
1881 .halt_reg = 0x8c02c,
1882 .halt_check = BRANCH_HALT,
1883 .clkr = {
1884 .enable_reg = 0x8c02c,
1885 .enable_mask = BIT(0),
1886 .hw.init = &(struct clk_init_data){
1887 .name = "gcc_pcie_1_clkref_clk",
1888 .ops = &clk_branch2_ops,
1889 },
1890 },
1891};
1892
1893static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1894 .halt_reg = 0x8d018,
1895 .halt_check = BRANCH_HALT_VOTED,
1896 .clkr = {
1897 .enable_reg = 0x52004,
1898 .enable_mask = BIT(27),
1899 .hw.init = &(struct clk_init_data){
1900 .name = "gcc_pcie_1_mstr_axi_clk",
1901 .ops = &clk_branch2_ops,
1902 },
1903 },
1904};
1905
1906/* Clock ON depends on external parent 'PIPE' clock, so dont poll */
1907static struct clk_branch gcc_pcie_1_pipe_clk = {
1908 .halt_reg = 0x8d024,
1909 .halt_check = BRANCH_HALT_DELAY,
1910 .clkr = {
1911 .enable_reg = 0x52004,
1912 .enable_mask = BIT(30),
1913 .hw.init = &(struct clk_init_data){
1914 .name = "gcc_pcie_1_pipe_clk",
1915 .ops = &clk_branch2_ops,
1916 },
1917 },
1918};
1919
1920static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1921 .halt_reg = 0x8d014,
1922 .halt_check = BRANCH_HALT_VOTED,
1923 .hwcg_reg = 0x8d014,
1924 .hwcg_bit = 1,
1925 .clkr = {
1926 .enable_reg = 0x52004,
1927 .enable_mask = BIT(26),
1928 .hw.init = &(struct clk_init_data){
1929 .name = "gcc_pcie_1_slv_axi_clk",
1930 .ops = &clk_branch2_ops,
1931 },
1932 },
1933};
1934
1935static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1936 .halt_reg = 0x8d010,
1937 .halt_check = BRANCH_HALT_VOTED,
1938 .clkr = {
1939 .enable_reg = 0x52004,
1940 .enable_mask = BIT(25),
1941 .hw.init = &(struct clk_init_data){
1942 .name = "gcc_pcie_1_slv_q2a_axi_clk",
1943 .ops = &clk_branch2_ops,
1944 },
1945 },
1946};
1947
1948static struct clk_branch gcc_pcie_phy_aux_clk = {
1949 .halt_reg = 0x6f004,
1950 .halt_check = BRANCH_HALT,
1951 .clkr = {
1952 .enable_reg = 0x6f004,
1953 .enable_mask = BIT(0),
1954 .hw.init = &(struct clk_init_data){
1955 .name = "gcc_pcie_phy_aux_clk",
1956 .parent_hws = (const struct clk_hw *[]){
1957 &gcc_pcie_0_aux_clk_src.clkr.hw },
1958 .num_parents = 1,
1959 .flags = CLK_SET_RATE_PARENT,
1960 .ops = &clk_branch2_ops,
1961 },
1962 },
1963};
1964
1965static struct clk_branch gcc_pdm2_clk = {
1966 .halt_reg = 0x3300c,
1967 .halt_check = BRANCH_HALT,
1968 .clkr = {
1969 .enable_reg = 0x3300c,
1970 .enable_mask = BIT(0),
1971 .hw.init = &(struct clk_init_data){
1972 .name = "gcc_pdm2_clk",
1973 .parent_hws = (const struct clk_hw *[]){
1974 &gcc_pdm2_clk_src.clkr.hw },
1975 .num_parents = 1,
1976 .flags = CLK_SET_RATE_PARENT,
1977 .ops = &clk_branch2_ops,
1978 },
1979 },
1980};
1981
1982static struct clk_branch gcc_pdm_ahb_clk = {
1983 .halt_reg = 0x33004,
1984 .halt_check = BRANCH_HALT,
1985 .hwcg_reg = 0x33004,
1986 .hwcg_bit = 1,
1987 .clkr = {
1988 .enable_reg = 0x33004,
1989 .enable_mask = BIT(0),
1990 .hw.init = &(struct clk_init_data){
1991 .name = "gcc_pdm_ahb_clk",
1992 .ops = &clk_branch2_ops,
1993 },
1994 },
1995};
1996
1997static struct clk_branch gcc_pdm_xo4_clk = {
1998 .halt_reg = 0x33008,
1999 .halt_check = BRANCH_HALT,
2000 .clkr = {
2001 .enable_reg = 0x33008,
2002 .enable_mask = BIT(0),
2003 .hw.init = &(struct clk_init_data){
2004 .name = "gcc_pdm_xo4_clk",
2005 .ops = &clk_branch2_ops,
2006 },
2007 },
2008};
2009
2010static struct clk_branch gcc_prng_ahb_clk = {
2011 .halt_reg = 0x34004,
2012 .halt_check = BRANCH_HALT_VOTED,
2013 .clkr = {
2014 .enable_reg = 0x52004,
2015 .enable_mask = BIT(13),
2016 .hw.init = &(struct clk_init_data){
2017 .name = "gcc_prng_ahb_clk",
2018 .ops = &clk_branch2_ops,
2019 },
2020 },
2021};
2022
2023static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2024 .halt_reg = 0xb018,
2025 .halt_check = BRANCH_HALT,
2026 .hwcg_reg = 0xb018,
2027 .hwcg_bit = 1,
2028 .clkr = {
2029 .enable_reg = 0xb018,
2030 .enable_mask = BIT(0),
2031 .hw.init = &(struct clk_init_data){
2032 .name = "gcc_qmip_camera_nrt_ahb_clk",
2033 .ops = &clk_branch2_ops,
2034 },
2035 },
2036};
2037
2038static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2039 .halt_reg = 0xb01c,
2040 .halt_check = BRANCH_HALT,
2041 .hwcg_reg = 0xb01c,
2042 .hwcg_bit = 1,
2043 .clkr = {
2044 .enable_reg = 0xb01c,
2045 .enable_mask = BIT(0),
2046 .hw.init = &(struct clk_init_data){
2047 .name = "gcc_qmip_camera_rt_ahb_clk",
2048 .ops = &clk_branch2_ops,
2049 },
2050 },
2051};
2052
2053static struct clk_branch gcc_qmip_disp_ahb_clk = {
2054 .halt_reg = 0xb020,
2055 .halt_check = BRANCH_HALT,
2056 .hwcg_reg = 0xb020,
2057 .hwcg_bit = 1,
2058 .clkr = {
2059 .enable_reg = 0xb020,
2060 .enable_mask = BIT(0),
2061 .hw.init = &(struct clk_init_data){
2062 .name = "gcc_qmip_disp_ahb_clk",
2063 .ops = &clk_branch2_ops,
2064 },
2065 },
2066};
2067
2068static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2069 .halt_reg = 0xb010,
2070 .halt_check = BRANCH_HALT,
2071 .hwcg_reg = 0xb010,
2072 .hwcg_bit = 1,
2073 .clkr = {
2074 .enable_reg = 0xb010,
2075 .enable_mask = BIT(0),
2076 .hw.init = &(struct clk_init_data){
2077 .name = "gcc_qmip_video_cvp_ahb_clk",
2078 .ops = &clk_branch2_ops,
2079 },
2080 },
2081};
2082
2083static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2084 .halt_reg = 0xb014,
2085 .halt_check = BRANCH_HALT,
2086 .hwcg_reg = 0xb014,
2087 .hwcg_bit = 1,
2088 .clkr = {
2089 .enable_reg = 0xb014,
2090 .enable_mask = BIT(0),
2091 .hw.init = &(struct clk_init_data){
2092 .name = "gcc_qmip_video_vcodec_ahb_clk",
2093 .ops = &clk_branch2_ops,
2094 },
2095 },
2096};
2097
2098static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
2099 .halt_reg = 0x4b000,
2100 .halt_check = BRANCH_HALT,
2101 .clkr = {
2102 .enable_reg = 0x4b000,
2103 .enable_mask = BIT(0),
2104 .hw.init = &(struct clk_init_data){
2105 .name = "gcc_qspi_cnoc_periph_ahb_clk",
2106 .ops = &clk_branch2_ops,
2107 },
2108 },
2109};
2110
2111static struct clk_branch gcc_qspi_core_clk = {
2112 .halt_reg = 0x4b004,
2113 .halt_check = BRANCH_HALT,
2114 .clkr = {
2115 .enable_reg = 0x4b004,
2116 .enable_mask = BIT(0),
2117 .hw.init = &(struct clk_init_data){
2118 .name = "gcc_qspi_core_clk",
2119 .parent_hws = (const struct clk_hw *[]){
2120 &gcc_qspi_core_clk_src.clkr.hw },
2121 .num_parents = 1,
2122 .flags = CLK_SET_RATE_PARENT,
2123 .ops = &clk_branch2_ops,
2124 },
2125 },
2126};
2127
2128static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2129 .halt_reg = 0x17144,
2130 .halt_check = BRANCH_HALT_VOTED,
2131 .clkr = {
2132 .enable_reg = 0x5200c,
2133 .enable_mask = BIT(10),
2134 .hw.init = &(struct clk_init_data){
2135 .name = "gcc_qupv3_wrap0_s0_clk",
2136 .parent_hws = (const struct clk_hw *[]){
2137 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw },
2138 .num_parents = 1,
2139 .flags = CLK_SET_RATE_PARENT,
2140 .ops = &clk_branch2_ops,
2141 },
2142 },
2143};
2144
2145static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2146 .halt_reg = 0x17274,
2147 .halt_check = BRANCH_HALT_VOTED,
2148 .clkr = {
2149 .enable_reg = 0x5200c,
2150 .enable_mask = BIT(11),
2151 .hw.init = &(struct clk_init_data){
2152 .name = "gcc_qupv3_wrap0_s1_clk",
2153 .parent_hws = (const struct clk_hw *[]){
2154 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw },
2155 .num_parents = 1,
2156 .flags = CLK_SET_RATE_PARENT,
2157 .ops = &clk_branch2_ops,
2158 },
2159 },
2160};
2161
2162static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2163 .halt_reg = 0x173a4,
2164 .halt_check = BRANCH_HALT_VOTED,
2165 .clkr = {
2166 .enable_reg = 0x5200c,
2167 .enable_mask = BIT(12),
2168 .hw.init = &(struct clk_init_data){
2169 .name = "gcc_qupv3_wrap0_s2_clk",
2170 .parent_hws = (const struct clk_hw *[]){
2171 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw },
2172 .num_parents = 1,
2173 .flags = CLK_SET_RATE_PARENT,
2174 .ops = &clk_branch2_ops,
2175 },
2176 },
2177};
2178
2179static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2180 .halt_reg = 0x174d4,
2181 .halt_check = BRANCH_HALT_VOTED,
2182 .clkr = {
2183 .enable_reg = 0x5200c,
2184 .enable_mask = BIT(13),
2185 .hw.init = &(struct clk_init_data){
2186 .name = "gcc_qupv3_wrap0_s3_clk",
2187 .parent_hws = (const struct clk_hw *[]){
2188 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw },
2189 .num_parents = 1,
2190 .flags = CLK_SET_RATE_PARENT,
2191 .ops = &clk_branch2_ops,
2192 },
2193 },
2194};
2195
2196static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2197 .halt_reg = 0x17604,
2198 .halt_check = BRANCH_HALT_VOTED,
2199 .clkr = {
2200 .enable_reg = 0x5200c,
2201 .enable_mask = BIT(14),
2202 .hw.init = &(struct clk_init_data){
2203 .name = "gcc_qupv3_wrap0_s4_clk",
2204 .parent_hws = (const struct clk_hw *[]){
2205 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw },
2206 .num_parents = 1,
2207 .flags = CLK_SET_RATE_PARENT,
2208 .ops = &clk_branch2_ops,
2209 },
2210 },
2211};
2212
2213static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2214 .halt_reg = 0x17734,
2215 .halt_check = BRANCH_HALT_VOTED,
2216 .clkr = {
2217 .enable_reg = 0x5200c,
2218 .enable_mask = BIT(15),
2219 .hw.init = &(struct clk_init_data){
2220 .name = "gcc_qupv3_wrap0_s5_clk",
2221 .parent_hws = (const struct clk_hw *[]){
2222 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw },
2223 .num_parents = 1,
2224 .flags = CLK_SET_RATE_PARENT,
2225 .ops = &clk_branch2_ops,
2226 },
2227 },
2228};
2229
2230static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2231 .halt_reg = 0x17864,
2232 .halt_check = BRANCH_HALT_VOTED,
2233 .clkr = {
2234 .enable_reg = 0x5200c,
2235 .enable_mask = BIT(16),
2236 .hw.init = &(struct clk_init_data){
2237 .name = "gcc_qupv3_wrap0_s6_clk",
2238 .parent_hws = (const struct clk_hw *[]){
2239 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw },
2240 .num_parents = 1,
2241 .flags = CLK_SET_RATE_PARENT,
2242 .ops = &clk_branch2_ops,
2243 },
2244 },
2245};
2246
2247static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2248 .halt_reg = 0x17994,
2249 .halt_check = BRANCH_HALT_VOTED,
2250 .clkr = {
2251 .enable_reg = 0x5200c,
2252 .enable_mask = BIT(17),
2253 .hw.init = &(struct clk_init_data){
2254 .name = "gcc_qupv3_wrap0_s7_clk",
2255 .parent_hws = (const struct clk_hw *[]){
2256 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw },
2257 .num_parents = 1,
2258 .flags = CLK_SET_RATE_PARENT,
2259 .ops = &clk_branch2_ops,
2260 },
2261 },
2262};
2263
2264static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2265 .halt_reg = 0x18144,
2266 .halt_check = BRANCH_HALT_VOTED,
2267 .clkr = {
2268 .enable_reg = 0x5200c,
2269 .enable_mask = BIT(22),
2270 .hw.init = &(struct clk_init_data){
2271 .name = "gcc_qupv3_wrap1_s0_clk",
2272 .parent_hws = (const struct clk_hw *[]){
2273 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw },
2274 .num_parents = 1,
2275 .flags = CLK_SET_RATE_PARENT,
2276 .ops = &clk_branch2_ops,
2277 },
2278 },
2279};
2280
2281static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2282 .halt_reg = 0x18274,
2283 .halt_check = BRANCH_HALT_VOTED,
2284 .clkr = {
2285 .enable_reg = 0x5200c,
2286 .enable_mask = BIT(23),
2287 .hw.init = &(struct clk_init_data){
2288 .name = "gcc_qupv3_wrap1_s1_clk",
2289 .parent_hws = (const struct clk_hw *[]){
2290 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw },
2291 .num_parents = 1,
2292 .flags = CLK_SET_RATE_PARENT,
2293 .ops = &clk_branch2_ops,
2294 },
2295 },
2296};
2297
2298static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2299 .halt_reg = 0x183a4,
2300 .halt_check = BRANCH_HALT_VOTED,
2301 .clkr = {
2302 .enable_reg = 0x5200c,
2303 .enable_mask = BIT(24),
2304 .hw.init = &(struct clk_init_data){
2305 .name = "gcc_qupv3_wrap1_s2_clk",
2306 .parent_hws = (const struct clk_hw *[]){
2307 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw },
2308 .num_parents = 1,
2309 .flags = CLK_SET_RATE_PARENT,
2310 .ops = &clk_branch2_ops,
2311 },
2312 },
2313};
2314
2315static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2316 .halt_reg = 0x184d4,
2317 .halt_check = BRANCH_HALT_VOTED,
2318 .clkr = {
2319 .enable_reg = 0x5200c,
2320 .enable_mask = BIT(25),
2321 .hw.init = &(struct clk_init_data){
2322 .name = "gcc_qupv3_wrap1_s3_clk",
2323 .parent_hws = (const struct clk_hw *[]){
2324 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw },
2325 .num_parents = 1,
2326 .flags = CLK_SET_RATE_PARENT,
2327 .ops = &clk_branch2_ops,
2328 },
2329 },
2330};
2331
2332static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2333 .halt_reg = 0x18604,
2334 .halt_check = BRANCH_HALT_VOTED,
2335 .clkr = {
2336 .enable_reg = 0x5200c,
2337 .enable_mask = BIT(26),
2338 .hw.init = &(struct clk_init_data){
2339 .name = "gcc_qupv3_wrap1_s4_clk",
2340 .parent_hws = (const struct clk_hw *[]){
2341 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw },
2342 .num_parents = 1,
2343 .flags = CLK_SET_RATE_PARENT,
2344 .ops = &clk_branch2_ops,
2345 },
2346 },
2347};
2348
2349static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2350 .halt_reg = 0x18734,
2351 .halt_check = BRANCH_HALT_VOTED,
2352 .clkr = {
2353 .enable_reg = 0x5200c,
2354 .enable_mask = BIT(27),
2355 .hw.init = &(struct clk_init_data){
2356 .name = "gcc_qupv3_wrap1_s5_clk",
2357 .parent_hws = (const struct clk_hw *[]){
2358 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw },
2359 .num_parents = 1,
2360 .flags = CLK_SET_RATE_PARENT,
2361 .ops = &clk_branch2_ops,
2362 },
2363 },
2364};
2365
2366static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2367 .halt_reg = 0x1e144,
2368 .halt_check = BRANCH_HALT_VOTED,
2369 .clkr = {
2370 .enable_reg = 0x52014,
2371 .enable_mask = BIT(4),
2372 .hw.init = &(struct clk_init_data){
2373 .name = "gcc_qupv3_wrap2_s0_clk",
2374 .parent_hws = (const struct clk_hw *[]){
2375 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw },
2376 .num_parents = 1,
2377 .flags = CLK_SET_RATE_PARENT,
2378 .ops = &clk_branch2_ops,
2379 },
2380 },
2381};
2382
2383static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2384 .halt_reg = 0x1e274,
2385 .halt_check = BRANCH_HALT_VOTED,
2386 .clkr = {
2387 .enable_reg = 0x52014,
2388 .enable_mask = BIT(5),
2389 .hw.init = &(struct clk_init_data){
2390 .name = "gcc_qupv3_wrap2_s1_clk",
2391 .parent_hws = (const struct clk_hw *[]){
2392 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw },
2393 .num_parents = 1,
2394 .flags = CLK_SET_RATE_PARENT,
2395 .ops = &clk_branch2_ops,
2396 },
2397 },
2398};
2399
2400static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2401 .halt_reg = 0x1e3a4,
2402 .halt_check = BRANCH_HALT_VOTED,
2403 .clkr = {
2404 .enable_reg = 0x52014,
2405 .enable_mask = BIT(6),
2406 .hw.init = &(struct clk_init_data){
2407 .name = "gcc_qupv3_wrap2_s2_clk",
2408 .parent_hws = (const struct clk_hw *[]){
2409 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw },
2410 .num_parents = 1,
2411 .flags = CLK_SET_RATE_PARENT,
2412 .ops = &clk_branch2_ops,
2413 },
2414 },
2415};
2416
2417static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2418 .halt_reg = 0x1e4d4,
2419 .halt_check = BRANCH_HALT_VOTED,
2420 .clkr = {
2421 .enable_reg = 0x52014,
2422 .enable_mask = BIT(7),
2423 .hw.init = &(struct clk_init_data){
2424 .name = "gcc_qupv3_wrap2_s3_clk",
2425 .parent_hws = (const struct clk_hw *[]){
2426 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw },
2427 .num_parents = 1,
2428 .flags = CLK_SET_RATE_PARENT,
2429 .ops = &clk_branch2_ops,
2430 },
2431 },
2432};
2433
2434static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2435 .halt_reg = 0x1e604,
2436 .halt_check = BRANCH_HALT_VOTED,
2437 .clkr = {
2438 .enable_reg = 0x52014,
2439 .enable_mask = BIT(8),
2440 .hw.init = &(struct clk_init_data){
2441 .name = "gcc_qupv3_wrap2_s4_clk",
2442 .parent_hws = (const struct clk_hw *[]){
2443 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw },
2444 .num_parents = 1,
2445 .flags = CLK_SET_RATE_PARENT,
2446 .ops = &clk_branch2_ops,
2447 },
2448 },
2449};
2450
2451static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2452 .halt_reg = 0x1e734,
2453 .halt_check = BRANCH_HALT_VOTED,
2454 .clkr = {
2455 .enable_reg = 0x52014,
2456 .enable_mask = BIT(9),
2457 .hw.init = &(struct clk_init_data){
2458 .name = "gcc_qupv3_wrap2_s5_clk",
2459 .parent_hws = (const struct clk_hw *[]){
2460 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw },
2461 .num_parents = 1,
2462 .flags = CLK_SET_RATE_PARENT,
2463 .ops = &clk_branch2_ops,
2464 },
2465 },
2466};
2467
2468static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2469 .halt_reg = 0x17004,
2470 .halt_check = BRANCH_HALT_VOTED,
2471 .clkr = {
2472 .enable_reg = 0x5200c,
2473 .enable_mask = BIT(6),
2474 .hw.init = &(struct clk_init_data){
2475 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2476 .ops = &clk_branch2_ops,
2477 },
2478 },
2479};
2480
2481static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2482 .halt_reg = 0x17008,
2483 .halt_check = BRANCH_HALT_VOTED,
2484 .hwcg_reg = 0x17008,
2485 .hwcg_bit = 1,
2486 .clkr = {
2487 .enable_reg = 0x5200c,
2488 .enable_mask = BIT(7),
2489 .hw.init = &(struct clk_init_data){
2490 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2491 .ops = &clk_branch2_ops,
2492 },
2493 },
2494};
2495
2496static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2497 .halt_reg = 0x18004,
2498 .halt_check = BRANCH_HALT_VOTED,
2499 .clkr = {
2500 .enable_reg = 0x5200c,
2501 .enable_mask = BIT(20),
2502 .hw.init = &(struct clk_init_data){
2503 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2504 .ops = &clk_branch2_ops,
2505 },
2506 },
2507};
2508
2509static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2510 .halt_reg = 0x18008,
2511 .halt_check = BRANCH_HALT_VOTED,
2512 .hwcg_reg = 0x18008,
2513 .hwcg_bit = 1,
2514 .clkr = {
2515 .enable_reg = 0x5200c,
2516 .enable_mask = BIT(21),
2517 .hw.init = &(struct clk_init_data){
2518 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2519 .ops = &clk_branch2_ops,
2520 },
2521 },
2522};
2523
2524static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
2525 .halt_reg = 0x1e004,
2526 .halt_check = BRANCH_HALT_VOTED,
2527 .clkr = {
2528 .enable_reg = 0x52014,
2529 .enable_mask = BIT(2),
2530 .hw.init = &(struct clk_init_data){
2531 .name = "gcc_qupv3_wrap_2_m_ahb_clk",
2532 .ops = &clk_branch2_ops,
2533 },
2534 },
2535};
2536
2537static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
2538 .halt_reg = 0x1e008,
2539 .halt_check = BRANCH_HALT_VOTED,
2540 .hwcg_reg = 0x1e008,
2541 .hwcg_bit = 1,
2542 .clkr = {
2543 .enable_reg = 0x52014,
2544 .enable_mask = BIT(1),
2545 .hw.init = &(struct clk_init_data){
2546 .name = "gcc_qupv3_wrap_2_s_ahb_clk",
2547 .ops = &clk_branch2_ops,
2548 },
2549 },
2550};
2551
2552static struct clk_branch gcc_sdcc2_ahb_clk = {
2553 .halt_reg = 0x14008,
2554 .halt_check = BRANCH_HALT,
2555 .clkr = {
2556 .enable_reg = 0x14008,
2557 .enable_mask = BIT(0),
2558 .hw.init = &(struct clk_init_data){
2559 .name = "gcc_sdcc2_ahb_clk",
2560 .ops = &clk_branch2_ops,
2561 },
2562 },
2563};
2564
2565static struct clk_branch gcc_sdcc2_apps_clk = {
2566 .halt_reg = 0x14004,
2567 .halt_check = BRANCH_HALT,
2568 .clkr = {
2569 .enable_reg = 0x14004,
2570 .enable_mask = BIT(0),
2571 .hw.init = &(struct clk_init_data){
2572 .name = "gcc_sdcc2_apps_clk",
2573 .parent_hws = (const struct clk_hw *[]){
2574 &gcc_sdcc2_apps_clk_src.clkr.hw },
2575 .num_parents = 1,
2576 .flags = CLK_SET_RATE_PARENT,
2577 .ops = &clk_branch2_ops,
2578 },
2579 },
2580};
2581
2582static struct clk_branch gcc_sdcc4_ahb_clk = {
2583 .halt_reg = 0x16008,
2584 .halt_check = BRANCH_HALT,
2585 .clkr = {
2586 .enable_reg = 0x16008,
2587 .enable_mask = BIT(0),
2588 .hw.init = &(struct clk_init_data){
2589 .name = "gcc_sdcc4_ahb_clk",
2590 .ops = &clk_branch2_ops,
2591 },
2592 },
2593};
2594
2595static struct clk_branch gcc_sdcc4_apps_clk = {
2596 .halt_reg = 0x16004,
2597 .halt_check = BRANCH_HALT,
2598 .clkr = {
2599 .enable_reg = 0x16004,
2600 .enable_mask = BIT(0),
2601 .hw.init = &(struct clk_init_data){
2602 .name = "gcc_sdcc4_apps_clk",
2603 .parent_hws = (const struct clk_hw *[]){
2604 &gcc_sdcc4_apps_clk_src.clkr.hw },
2605 .num_parents = 1,
2606 .flags = CLK_SET_RATE_PARENT,
2607 .ops = &clk_branch2_ops,
2608 },
2609 },
2610};
2611
2612static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2613 .halt_reg = 0x4819c,
2614 .halt_check = BRANCH_HALT_VOTED,
2615 .clkr = {
2616 .enable_reg = 0x52004,
2617 .enable_mask = BIT(0),
2618 .hw.init = &(struct clk_init_data){
2619 .name = "gcc_sys_noc_cpuss_ahb_clk",
2620 .parent_hws = (const struct clk_hw *[]){
2621 &gcc_cpuss_ahb_clk_src.clkr.hw },
2622 .num_parents = 1,
2623 /* required for cpuss */
2624 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
2625 .ops = &clk_branch2_ops,
2626 },
2627 },
2628};
2629
2630static struct clk_branch gcc_tsif_ahb_clk = {
2631 .halt_reg = 0x36004,
2632 .halt_check = BRANCH_HALT,
2633 .clkr = {
2634 .enable_reg = 0x36004,
2635 .enable_mask = BIT(0),
2636 .hw.init = &(struct clk_init_data){
2637 .name = "gcc_tsif_ahb_clk",
2638 .ops = &clk_branch2_ops,
2639 },
2640 },
2641};
2642
2643static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2644 .halt_reg = 0x3600c,
2645 .halt_check = BRANCH_HALT,
2646 .clkr = {
2647 .enable_reg = 0x3600c,
2648 .enable_mask = BIT(0),
2649 .hw.init = &(struct clk_init_data){
2650 .name = "gcc_tsif_inactivity_timers_clk",
2651 .ops = &clk_branch2_ops,
2652 },
2653 },
2654};
2655
2656static struct clk_branch gcc_tsif_ref_clk = {
2657 .halt_reg = 0x36008,
2658 .halt_check = BRANCH_HALT,
2659 .clkr = {
2660 .enable_reg = 0x36008,
2661 .enable_mask = BIT(0),
2662 .hw.init = &(struct clk_init_data){
2663 .name = "gcc_tsif_ref_clk",
2664 .parent_hws = (const struct clk_hw *[]){
2665 &gcc_tsif_ref_clk_src.clkr.hw },
2666 .num_parents = 1,
2667 .flags = CLK_SET_RATE_PARENT,
2668 .ops = &clk_branch2_ops,
2669 },
2670 },
2671};
2672
2673static struct clk_branch gcc_ufs_card_ahb_clk = {
2674 .halt_reg = 0x75014,
2675 .halt_check = BRANCH_HALT,
2676 .hwcg_reg = 0x75014,
2677 .hwcg_bit = 1,
2678 .clkr = {
2679 .enable_reg = 0x75014,
2680 .enable_mask = BIT(0),
2681 .hw.init = &(struct clk_init_data){
2682 .name = "gcc_ufs_card_ahb_clk",
2683 .ops = &clk_branch2_ops,
2684 },
2685 },
2686};
2687
2688static struct clk_branch gcc_ufs_card_axi_clk = {
2689 .halt_reg = 0x75010,
2690 .halt_check = BRANCH_HALT,
2691 .hwcg_reg = 0x75010,
2692 .hwcg_bit = 1,
2693 .clkr = {
2694 .enable_reg = 0x75010,
2695 .enable_mask = BIT(0),
2696 .hw.init = &(struct clk_init_data){
2697 .name = "gcc_ufs_card_axi_clk",
2698 .parent_hws = (const struct clk_hw *[]){
2699 &gcc_ufs_card_axi_clk_src.clkr.hw },
2700 .num_parents = 1,
2701 .flags = CLK_SET_RATE_PARENT,
2702 .ops = &clk_branch2_ops,
2703 },
2704 },
2705};
2706
2707static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
2708 .halt_reg = 0x75010,
2709 .halt_check = BRANCH_HALT,
2710 .hwcg_reg = 0x75010,
2711 .hwcg_bit = 1,
2712 .clkr = {
2713 .enable_reg = 0x75010,
2714 .enable_mask = BIT(1),
2715 .hw.init = &(struct clk_init_data){
2716 .name = "gcc_ufs_card_axi_hw_ctl_clk",
2717 .parent_hws = (const struct clk_hw *[]){
2718 &gcc_ufs_card_axi_clk.clkr.hw },
2719 .num_parents = 1,
2720 .flags = CLK_SET_RATE_PARENT,
2721 .ops = &clk_branch_simple_ops,
2722 },
2723 },
2724};
2725
2726static struct clk_branch gcc_ufs_card_clkref_clk = {
2727 .halt_reg = 0x8c004,
2728 .halt_check = BRANCH_HALT,
2729 .clkr = {
2730 .enable_reg = 0x8c004,
2731 .enable_mask = BIT(0),
2732 .hw.init = &(struct clk_init_data){
2733 .name = "gcc_ufs_card_clkref_clk",
2734 .ops = &clk_branch2_ops,
2735 },
2736 },
2737};
2738
2739static struct clk_branch gcc_ufs_card_ice_core_clk = {
2740 .halt_reg = 0x7505c,
2741 .halt_check = BRANCH_HALT,
2742 .hwcg_reg = 0x7505c,
2743 .hwcg_bit = 1,
2744 .clkr = {
2745 .enable_reg = 0x7505c,
2746 .enable_mask = BIT(0),
2747 .hw.init = &(struct clk_init_data){
2748 .name = "gcc_ufs_card_ice_core_clk",
2749 .parent_hws = (const struct clk_hw *[]){
2750 &gcc_ufs_card_ice_core_clk_src.clkr.hw },
2751 .num_parents = 1,
2752 .flags = CLK_SET_RATE_PARENT,
2753 .ops = &clk_branch2_ops,
2754 },
2755 },
2756};
2757
2758static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
2759 .halt_reg = 0x7505c,
2760 .halt_check = BRANCH_HALT,
2761 .hwcg_reg = 0x7505c,
2762 .hwcg_bit = 1,
2763 .clkr = {
2764 .enable_reg = 0x7505c,
2765 .enable_mask = BIT(1),
2766 .hw.init = &(struct clk_init_data){
2767 .name = "gcc_ufs_card_ice_core_hw_ctl_clk",
2768 .parent_hws = (const struct clk_hw *[]){
2769 &gcc_ufs_card_ice_core_clk.clkr.hw },
2770 .num_parents = 1,
2771 .flags = CLK_SET_RATE_PARENT,
2772 .ops = &clk_branch_simple_ops,
2773 },
2774 },
2775};
2776
2777static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2778 .halt_reg = 0x75090,
2779 .halt_check = BRANCH_HALT,
2780 .hwcg_reg = 0x75090,
2781 .hwcg_bit = 1,
2782 .clkr = {
2783 .enable_reg = 0x75090,
2784 .enable_mask = BIT(0),
2785 .hw.init = &(struct clk_init_data){
2786 .name = "gcc_ufs_card_phy_aux_clk",
2787 .parent_hws = (const struct clk_hw *[]){
2788 &gcc_ufs_card_phy_aux_clk_src.clkr.hw },
2789 .num_parents = 1,
2790 .flags = CLK_SET_RATE_PARENT,
2791 .ops = &clk_branch2_ops,
2792 },
2793 },
2794};
2795
2796static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
2797 .halt_reg = 0x75090,
2798 .halt_check = BRANCH_HALT,
2799 .hwcg_reg = 0x75090,
2800 .hwcg_bit = 1,
2801 .clkr = {
2802 .enable_reg = 0x75090,
2803 .enable_mask = BIT(1),
2804 .hw.init = &(struct clk_init_data){
2805 .name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
2806 .parent_hws = (const struct clk_hw *[]){
2807 &gcc_ufs_card_phy_aux_clk.clkr.hw },
2808 .num_parents = 1,
2809 .flags = CLK_SET_RATE_PARENT,
2810 .ops = &clk_branch_simple_ops,
2811 },
2812 },
2813};
2814
2815static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2816 .halt_reg = 0x75058,
2817 .halt_check = BRANCH_HALT,
2818 .hwcg_reg = 0x75058,
2819 .hwcg_bit = 1,
2820 .clkr = {
2821 .enable_reg = 0x75058,
2822 .enable_mask = BIT(0),
2823 .hw.init = &(struct clk_init_data){
2824 .name = "gcc_ufs_card_unipro_core_clk",
2825 .parent_hws = (const struct clk_hw *[]){
2826 &gcc_ufs_card_unipro_core_clk_src.clkr.hw },
2827 .num_parents = 1,
2828 .flags = CLK_SET_RATE_PARENT,
2829 .ops = &clk_branch2_ops,
2830 },
2831 },
2832};
2833
2834static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
2835 .halt_reg = 0x75058,
2836 .halt_check = BRANCH_HALT,
2837 .hwcg_reg = 0x75058,
2838 .hwcg_bit = 1,
2839 .clkr = {
2840 .enable_reg = 0x75058,
2841 .enable_mask = BIT(1),
2842 .hw.init = &(struct clk_init_data){
2843 .name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
2844 .parent_hws = (const struct clk_hw *[]){
2845 &gcc_ufs_card_unipro_core_clk.clkr.hw },
2846 .num_parents = 1,
2847 .flags = CLK_SET_RATE_PARENT,
2848 .ops = &clk_branch_simple_ops,
2849 },
2850 },
2851};
2852
2853static struct clk_branch gcc_ufs_mem_clkref_clk = {
2854 .halt_reg = 0x8c000,
2855 .halt_check = BRANCH_HALT,
2856 .clkr = {
2857 .enable_reg = 0x8c000,
2858 .enable_mask = BIT(0),
2859 .hw.init = &(struct clk_init_data){
2860 .name = "gcc_ufs_mem_clkref_clk",
2861 .ops = &clk_branch2_ops,
2862 },
2863 },
2864};
2865
2866static struct clk_branch gcc_ufs_phy_ahb_clk = {
2867 .halt_reg = 0x77014,
2868 .halt_check = BRANCH_HALT,
2869 .hwcg_reg = 0x77014,
2870 .hwcg_bit = 1,
2871 .clkr = {
2872 .enable_reg = 0x77014,
2873 .enable_mask = BIT(0),
2874 .hw.init = &(struct clk_init_data){
2875 .name = "gcc_ufs_phy_ahb_clk",
2876 .ops = &clk_branch2_ops,
2877 },
2878 },
2879};
2880
2881static struct clk_branch gcc_ufs_phy_axi_clk = {
2882 .halt_reg = 0x77010,
2883 .halt_check = BRANCH_HALT,
2884 .hwcg_reg = 0x77010,
2885 .hwcg_bit = 1,
2886 .clkr = {
2887 .enable_reg = 0x77010,
2888 .enable_mask = BIT(0),
2889 .hw.init = &(struct clk_init_data){
2890 .name = "gcc_ufs_phy_axi_clk",
2891 .parent_hws = (const struct clk_hw *[]){
2892 &gcc_ufs_phy_axi_clk_src.clkr.hw },
2893 .num_parents = 1,
2894 .flags = CLK_SET_RATE_PARENT,
2895 .ops = &clk_branch2_ops,
2896 },
2897 },
2898};
2899
2900static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
2901 .halt_reg = 0x77010,
2902 .halt_check = BRANCH_HALT,
2903 .hwcg_reg = 0x77010,
2904 .hwcg_bit = 1,
2905 .clkr = {
2906 .enable_reg = 0x77010,
2907 .enable_mask = BIT(1),
2908 .hw.init = &(struct clk_init_data){
2909 .name = "gcc_ufs_phy_axi_hw_ctl_clk",
2910 .parent_hws = (const struct clk_hw *[]){
2911 &gcc_ufs_phy_axi_clk.clkr.hw },
2912 .num_parents = 1,
2913 .flags = CLK_SET_RATE_PARENT,
2914 .ops = &clk_branch_simple_ops,
2915 },
2916 },
2917};
2918
2919static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2920 .halt_reg = 0x7705c,
2921 .halt_check = BRANCH_HALT,
2922 .hwcg_reg = 0x7705c,
2923 .hwcg_bit = 1,
2924 .clkr = {
2925 .enable_reg = 0x7705c,
2926 .enable_mask = BIT(0),
2927 .hw.init = &(struct clk_init_data){
2928 .name = "gcc_ufs_phy_ice_core_clk",
2929 .parent_hws = (const struct clk_hw *[]){
2930 &gcc_ufs_phy_ice_core_clk_src.clkr.hw },
2931 .num_parents = 1,
2932 .flags = CLK_SET_RATE_PARENT,
2933 .ops = &clk_branch2_ops,
2934 },
2935 },
2936};
2937
2938static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
2939 .halt_reg = 0x7705c,
2940 .halt_check = BRANCH_HALT,
2941 .hwcg_reg = 0x7705c,
2942 .hwcg_bit = 1,
2943 .clkr = {
2944 .enable_reg = 0x7705c,
2945 .enable_mask = BIT(1),
2946 .hw.init = &(struct clk_init_data){
2947 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
2948 .parent_hws = (const struct clk_hw *[]){
2949 &gcc_ufs_phy_ice_core_clk.clkr.hw },
2950 .num_parents = 1,
2951 .flags = CLK_SET_RATE_PARENT,
2952 .ops = &clk_branch_simple_ops,
2953 },
2954 },
2955};
2956
2957static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2958 .halt_reg = 0x77090,
2959 .halt_check = BRANCH_HALT,
2960 .hwcg_reg = 0x77090,
2961 .hwcg_bit = 1,
2962 .clkr = {
2963 .enable_reg = 0x77090,
2964 .enable_mask = BIT(0),
2965 .hw.init = &(struct clk_init_data){
2966 .name = "gcc_ufs_phy_phy_aux_clk",
2967 .parent_hws = (const struct clk_hw *[]){
2968 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw },
2969 .num_parents = 1,
2970 .flags = CLK_SET_RATE_PARENT,
2971 .ops = &clk_branch2_ops,
2972 },
2973 },
2974};
2975
2976static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
2977 .halt_reg = 0x77090,
2978 .halt_check = BRANCH_HALT,
2979 .hwcg_reg = 0x77090,
2980 .hwcg_bit = 1,
2981 .clkr = {
2982 .enable_reg = 0x77090,
2983 .enable_mask = BIT(1),
2984 .hw.init = &(struct clk_init_data){
2985 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
2986 .parent_hws = (const struct clk_hw *[]){
2987 &gcc_ufs_phy_phy_aux_clk.clkr.hw },
2988 .num_parents = 1,
2989 .flags = CLK_SET_RATE_PARENT,
2990 .ops = &clk_branch_simple_ops,
2991 },
2992 },
2993};
2994
2995static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2996 .halt_reg = 0x77058,
2997 .halt_check = BRANCH_HALT,
2998 .hwcg_reg = 0x77058,
2999 .hwcg_bit = 1,
3000 .clkr = {
3001 .enable_reg = 0x77058,
3002 .enable_mask = BIT(0),
3003 .hw.init = &(struct clk_init_data){
3004 .name = "gcc_ufs_phy_unipro_core_clk",
3005 .parent_hws = (const struct clk_hw *[]){
3006 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw },
3007 .num_parents = 1,
3008 .flags = CLK_SET_RATE_PARENT,
3009 .ops = &clk_branch2_ops,
3010 },
3011 },
3012};
3013
3014static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
3015 .halt_reg = 0x77058,
3016 .halt_check = BRANCH_HALT,
3017 .hwcg_reg = 0x77058,
3018 .hwcg_bit = 1,
3019 .clkr = {
3020 .enable_reg = 0x77058,
3021 .enable_mask = BIT(1),
3022 .hw.init = &(struct clk_init_data){
3023 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
3024 .parent_hws = (const struct clk_hw *[]){
3025 &gcc_ufs_phy_unipro_core_clk.clkr.hw },
3026 .num_parents = 1,
3027 .flags = CLK_SET_RATE_PARENT,
3028 .ops = &clk_branch_simple_ops,
3029 },
3030 },
3031};
3032
3033static struct clk_branch gcc_usb30_prim_master_clk = {
3034 .halt_reg = 0xf010,
3035 .halt_check = BRANCH_HALT,
3036 .clkr = {
3037 .enable_reg = 0xf010,
3038 .enable_mask = BIT(0),
3039 .hw.init = &(struct clk_init_data){
3040 .name = "gcc_usb30_prim_master_clk",
3041 .parent_hws = (const struct clk_hw *[]){
3042 &gcc_usb30_prim_master_clk_src.clkr.hw },
3043 .num_parents = 1,
3044 .flags = CLK_SET_RATE_PARENT,
3045 .ops = &clk_branch2_ops,
3046 },
3047 },
3048};
3049
3050static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3051 .halt_reg = 0xf018,
3052 .halt_check = BRANCH_HALT,
3053 .clkr = {
3054 .enable_reg = 0xf018,
3055 .enable_mask = BIT(0),
3056 .hw.init = &(struct clk_init_data){
3057 .name = "gcc_usb30_prim_mock_utmi_clk",
3058 .parent_hws = (const struct clk_hw *[]){
3059 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw },
3060 .num_parents = 1,
3061 .flags = CLK_SET_RATE_PARENT,
3062 .ops = &clk_branch2_ops,
3063 },
3064 },
3065};
3066
3067static struct clk_branch gcc_usb30_prim_sleep_clk = {
3068 .halt_reg = 0xf014,
3069 .halt_check = BRANCH_HALT,
3070 .clkr = {
3071 .enable_reg = 0xf014,
3072 .enable_mask = BIT(0),
3073 .hw.init = &(struct clk_init_data){
3074 .name = "gcc_usb30_prim_sleep_clk",
3075 .ops = &clk_branch2_ops,
3076 },
3077 },
3078};
3079
3080static struct clk_branch gcc_usb30_sec_master_clk = {
3081 .halt_reg = 0x10010,
3082 .halt_check = BRANCH_HALT,
3083 .clkr = {
3084 .enable_reg = 0x10010,
3085 .enable_mask = BIT(0),
3086 .hw.init = &(struct clk_init_data){
3087 .name = "gcc_usb30_sec_master_clk",
3088 .parent_hws = (const struct clk_hw *[]){
3089 &gcc_usb30_sec_master_clk_src.clkr.hw },
3090 .num_parents = 1,
3091 .flags = CLK_SET_RATE_PARENT,
3092 .ops = &clk_branch2_ops,
3093 },
3094 },
3095};
3096
3097static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
3098 .halt_reg = 0x10018,
3099 .halt_check = BRANCH_HALT,
3100 .clkr = {
3101 .enable_reg = 0x10018,
3102 .enable_mask = BIT(0),
3103 .hw.init = &(struct clk_init_data){
3104 .name = "gcc_usb30_sec_mock_utmi_clk",
3105 .parent_hws = (const struct clk_hw *[]){
3106 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw },
3107 .num_parents = 1,
3108 .flags = CLK_SET_RATE_PARENT,
3109 .ops = &clk_branch2_ops,
3110 },
3111 },
3112};
3113
3114static struct clk_branch gcc_usb30_sec_sleep_clk = {
3115 .halt_reg = 0x10014,
3116 .halt_check = BRANCH_HALT,
3117 .clkr = {
3118 .enable_reg = 0x10014,
3119 .enable_mask = BIT(0),
3120 .hw.init = &(struct clk_init_data){
3121 .name = "gcc_usb30_sec_sleep_clk",
3122 .ops = &clk_branch2_ops,
3123 },
3124 },
3125};
3126
3127static struct clk_branch gcc_usb3_prim_clkref_clk = {
3128 .halt_reg = 0x8c008,
3129 .halt_check = BRANCH_HALT,
3130 .clkr = {
3131 .enable_reg = 0x8c008,
3132 .enable_mask = BIT(0),
3133 .hw.init = &(struct clk_init_data){
3134 .name = "gcc_usb3_prim_clkref_clk",
3135 .ops = &clk_branch2_ops,
3136 },
3137 },
3138};
3139
3140static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3141 .halt_reg = 0xf050,
3142 .halt_check = BRANCH_HALT,
3143 .clkr = {
3144 .enable_reg = 0xf050,
3145 .enable_mask = BIT(0),
3146 .hw.init = &(struct clk_init_data){
3147 .name = "gcc_usb3_prim_phy_aux_clk",
3148 .parent_hws = (const struct clk_hw *[]){
3149 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
3150 .num_parents = 1,
3151 .flags = CLK_SET_RATE_PARENT,
3152 .ops = &clk_branch2_ops,
3153 },
3154 },
3155};
3156
3157static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3158 .halt_reg = 0xf054,
3159 .halt_check = BRANCH_HALT,
3160 .clkr = {
3161 .enable_reg = 0xf054,
3162 .enable_mask = BIT(0),
3163 .hw.init = &(struct clk_init_data){
3164 .name = "gcc_usb3_prim_phy_com_aux_clk",
3165 .parent_hws = (const struct clk_hw *[]){
3166 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
3167 .num_parents = 1,
3168 .flags = CLK_SET_RATE_PARENT,
3169 .ops = &clk_branch2_ops,
3170 },
3171 },
3172};
3173
3174static struct clk_branch gcc_usb3_sec_clkref_clk = {
3175 .halt_reg = 0x8c028,
3176 .halt_check = BRANCH_HALT,
3177 .clkr = {
3178 .enable_reg = 0x8c028,
3179 .enable_mask = BIT(0),
3180 .hw.init = &(struct clk_init_data){
3181 .name = "gcc_usb3_sec_clkref_clk",
3182 .ops = &clk_branch2_ops,
3183 },
3184 },
3185};
3186
3187static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
3188 .halt_reg = 0x10050,
3189 .halt_check = BRANCH_HALT,
3190 .clkr = {
3191 .enable_reg = 0x10050,
3192 .enable_mask = BIT(0),
3193 .hw.init = &(struct clk_init_data){
3194 .name = "gcc_usb3_sec_phy_aux_clk",
3195 .parent_hws = (const struct clk_hw *[]){
3196 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
3197 .num_parents = 1,
3198 .flags = CLK_SET_RATE_PARENT,
3199 .ops = &clk_branch2_ops,
3200 },
3201 },
3202};
3203
3204static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
3205 .halt_reg = 0x10054,
3206 .halt_check = BRANCH_HALT,
3207 .clkr = {
3208 .enable_reg = 0x10054,
3209 .enable_mask = BIT(0),
3210 .hw.init = &(struct clk_init_data){
3211 .name = "gcc_usb3_sec_phy_com_aux_clk",
3212 .parent_hws = (const struct clk_hw *[]){
3213 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
3214 .num_parents = 1,
3215 .flags = CLK_SET_RATE_PARENT,
3216 .ops = &clk_branch2_ops,
3217 },
3218 },
3219};
3220
3221/*
3222 * Clock ON depends on external parent 'config noc', so cant poll
3223 * delay and also mark as crtitical for video boot
3224 */
3225static struct clk_branch gcc_video_ahb_clk = {
3226 .halt_reg = 0xb004,
3227 .halt_check = BRANCH_HALT_DELAY,
3228 .hwcg_reg = 0xb004,
3229 .hwcg_bit = 1,
3230 .clkr = {
3231 .enable_reg = 0xb004,
3232 .enable_mask = BIT(0),
3233 .hw.init = &(struct clk_init_data){
3234 .name = "gcc_video_ahb_clk",
3235 .flags = CLK_IS_CRITICAL,
3236 .ops = &clk_branch2_ops,
3237 },
3238 },
3239};
3240
3241static struct clk_branch gcc_video_axi0_clk = {
3242 .halt_reg = 0xb024,
3243 .halt_check = BRANCH_HALT,
3244 .clkr = {
3245 .enable_reg = 0xb024,
3246 .enable_mask = BIT(0),
3247 .hw.init = &(struct clk_init_data){
3248 .name = "gcc_video_axi0_clk",
3249 .ops = &clk_branch2_ops,
3250 },
3251 },
3252};
3253
3254static struct clk_branch gcc_video_axi1_clk = {
3255 .halt_reg = 0xb028,
3256 .halt_check = BRANCH_HALT,
3257 .clkr = {
3258 .enable_reg = 0xb028,
3259 .enable_mask = BIT(0),
3260 .hw.init = &(struct clk_init_data){
3261 .name = "gcc_video_axi1_clk",
3262 .ops = &clk_branch2_ops,
3263 },
3264 },
3265};
3266
3267static struct clk_branch gcc_video_axic_clk = {
3268 .halt_reg = 0xb02c,
3269 .halt_check = BRANCH_HALT,
3270 .clkr = {
3271 .enable_reg = 0xb02c,
3272 .enable_mask = BIT(0),
3273 .hw.init = &(struct clk_init_data){
3274 .name = "gcc_video_axic_clk",
3275 .ops = &clk_branch2_ops,
3276 },
3277 },
3278};
3279
3280/* XO critical input to video, so no need to poll */
3281static struct clk_branch gcc_video_xo_clk = {
3282 .halt_reg = 0xb040,
3283 .halt_check = BRANCH_HALT_DELAY,
3284 .clkr = {
3285 .enable_reg = 0xb040,
3286 .enable_mask = BIT(0),
3287 .hw.init = &(struct clk_init_data){
3288 .name = "gcc_video_xo_clk",
3289 .flags = CLK_IS_CRITICAL,
3290 .ops = &clk_branch2_ops,
3291 },
3292 },
3293};
3294
3295static struct clk_regmap *gcc_sm8150_clocks[] = {
3296 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3297 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3298 [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] =
3299 &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
3300 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3301 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] =
3302 &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
3303 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3304 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3305 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3306 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3307 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3308 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3309 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3310 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3311 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3312 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3313 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3314 [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
3315 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3316 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
3317 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3318 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3319 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3320 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3321 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3322 [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr,
3323 [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr,
3324 [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,
3325 [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr,
3326 [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr,
3327 [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr,
3328 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3329 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3330 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3331 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3332 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3333 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3334 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3335 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
3336 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3337 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3338 [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,
3339 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
3340 [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
3341 [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr,
3342 [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
3343 [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
3344 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3345 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3346 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3347 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
3348 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3349 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3350 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3351 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3352 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3353 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3354 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3355 [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
3356 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3357 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3358 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3359 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3360 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3361 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
3362 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3363 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3364 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3365 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3366 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3367 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3368 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3369 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3370 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3371 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3372 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3373 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3374 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3375 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3376 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3377 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3378 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3379 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3380 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3381 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3382 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3383 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3384 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3385 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3386 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3387 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3388 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3389 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3390 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3391 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3392 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3393 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3394 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3395 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3396 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3397 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3398 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3399 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3400 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3401 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3402 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3403 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
3404 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
3405 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
3406 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
3407 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
3408 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
3409 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
3410 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
3411 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
3412 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
3413 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
3414 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
3415 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3416 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3417 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3418 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3419 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
3420 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
3421 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3422 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3423 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3424 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3425 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3426 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3427 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3428 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3429 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3430 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3431 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
3432 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3433 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3434 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3435 [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
3436 [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
3437 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3438 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3439 [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] =
3440 &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
3441 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3442 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3443 [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] =
3444 &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
3445 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3446 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
3447 &gcc_ufs_card_unipro_core_clk_src.clkr,
3448 [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] =
3449 &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
3450 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
3451 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3452 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3453 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3454 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
3455 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3456 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3457 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] =
3458 &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
3459 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3460 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3461 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
3462 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3463 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3464 &gcc_ufs_phy_unipro_core_clk_src.clkr,
3465 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =
3466 &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
3467 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3468 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3469 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3470 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3471 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3472 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3473 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3474 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3475 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3476 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3477 &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3478 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3479 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3480 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3481 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3482 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3483 [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
3484 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3485 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3486 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3487 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3488 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3489 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3490 [GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr,
3491 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3492 [GPLL0] = &gpll0.clkr,
3493 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3494 [GPLL7] = &gpll7.clkr,
3495 [GPLL9] = &gpll9.clkr,
3496};
3497
3498static const struct qcom_reset_map gcc_sm8150_resets[] = {
3499 [GCC_EMAC_BCR] = { 0x6000 },
3500 [GCC_GPU_BCR] = { 0x71000 },
3501 [GCC_MMSS_BCR] = { 0xb000 },
3502 [GCC_NPU_BCR] = { 0x4d000 },
3503 [GCC_PCIE_0_BCR] = { 0x6b000 },
3504 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3505 [GCC_PCIE_1_BCR] = { 0x8d000 },
3506 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3507 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3508 [GCC_PDM_BCR] = { 0x33000 },
3509 [GCC_PRNG_BCR] = { 0x34000 },
3510 [GCC_QSPI_BCR] = { 0x24008 },
3511 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3512 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3513 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3514 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3515 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3516 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3517 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3518 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3519 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3520 [GCC_SDCC2_BCR] = { 0x14000 },
3521 [GCC_SDCC4_BCR] = { 0x16000 },
3522 [GCC_TSIF_BCR] = { 0x36000 },
3523 [GCC_UFS_CARD_BCR] = { 0x75000 },
3524 [GCC_UFS_PHY_BCR] = { 0x77000 },
3525 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3526 [GCC_USB30_SEC_BCR] = { 0x10000 },
3527 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3528};
3529
3530static const struct regmap_config gcc_sm8150_regmap_config = {
3531 .reg_bits = 32,
3532 .reg_stride = 4,
3533 .val_bits = 32,
3534 .max_register = 0x9c040,
3535 .fast_io = true,
3536};
3537
3538static const struct qcom_cc_desc gcc_sm8150_desc = {
3539 .config = &gcc_sm8150_regmap_config,
3540 .clks = gcc_sm8150_clocks,
3541 .num_clks = ARRAY_SIZE(gcc_sm8150_clocks),
3542 .resets = gcc_sm8150_resets,
3543 .num_resets = ARRAY_SIZE(gcc_sm8150_resets),
3544};
3545
3546static const struct of_device_id gcc_sm8150_match_table[] = {
3547 { .compatible = "qcom,gcc-sm8150" },
3548 { }
3549};
3550MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table);
3551
3552static int gcc_sm8150_probe(struct platform_device *pdev)
3553{
3554 struct regmap *regmap;
3555
3556 regmap = qcom_cc_map(pdev, &gcc_sm8150_desc);
3557 if (IS_ERR(regmap))
3558 return PTR_ERR(regmap);
3559
3560 /* Disable the GPLL0 active input to NPU and GPU via MISC registers */
3561 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
3562 regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
3563
3564 return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap);
3565}
3566
3567static struct platform_driver gcc_sm8150_driver = {
3568 .probe = gcc_sm8150_probe,
3569 .driver = {
3570 .name = "gcc-sm8150",
3571 .of_match_table = gcc_sm8150_match_table,
3572 },
3573};
3574
3575static int __init gcc_sm8150_init(void)
3576{
3577 return platform_driver_register(&gcc_sm8150_driver);
3578}
3579subsys_initcall(gcc_sm8150_init);
3580
3581static void __exit gcc_sm8150_exit(void)
3582{
3583 platform_driver_unregister(&gcc_sm8150_driver);
3584}
3585module_exit(gcc_sm8150_exit);
3586
3587MODULE_DESCRIPTION("QTI GCC SM8150 Driver");
3588MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/qcom/lpasscc-sdm845.c b/drivers/clk/qcom/lpasscc-sdm845.c
index e246b99dfbc6..56d3e9928892 100644
--- a/drivers/clk/qcom/lpasscc-sdm845.c
+++ b/drivers/clk/qcom/lpasscc-sdm845.c
@@ -112,25 +112,6 @@ static const struct qcom_cc_desc lpass_qdsp6ss_sdm845_desc = {
112 .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sdm845_clocks), 112 .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sdm845_clocks),
113}; 113};
114 114
115static int lpass_clocks_sdm845_probe(struct platform_device *pdev, int index,
116 const struct qcom_cc_desc *desc)
117{
118 struct regmap *regmap;
119 struct resource *res;
120 void __iomem *base;
121
122 res = platform_get_resource(pdev, IORESOURCE_MEM, index);
123 base = devm_ioremap_resource(&pdev->dev, res);
124 if (IS_ERR(base))
125 return PTR_ERR(base);
126
127 regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config);
128 if (IS_ERR(regmap))
129 return PTR_ERR(regmap);
130
131 return qcom_cc_really_probe(pdev, desc, regmap);
132}
133
134static int lpass_cc_sdm845_probe(struct platform_device *pdev) 115static int lpass_cc_sdm845_probe(struct platform_device *pdev)
135{ 116{
136 const struct qcom_cc_desc *desc; 117 const struct qcom_cc_desc *desc;
@@ -139,14 +120,14 @@ static int lpass_cc_sdm845_probe(struct platform_device *pdev)
139 lpass_regmap_config.name = "cc"; 120 lpass_regmap_config.name = "cc";
140 desc = &lpass_cc_sdm845_desc; 121 desc = &lpass_cc_sdm845_desc;
141 122
142 ret = lpass_clocks_sdm845_probe(pdev, 0, desc); 123 ret = qcom_cc_probe_by_index(pdev, 0, desc);
143 if (ret) 124 if (ret)
144 return ret; 125 return ret;
145 126
146 lpass_regmap_config.name = "qdsp6ss"; 127 lpass_regmap_config.name = "qdsp6ss";
147 desc = &lpass_qdsp6ss_sdm845_desc; 128 desc = &lpass_qdsp6ss_sdm845_desc;
148 129
149 return lpass_clocks_sdm845_probe(pdev, 1, desc); 130 return qcom_cc_probe_by_index(pdev, 1, desc);
150} 131}
151 132
152static const struct of_device_id lpass_cc_sdm845_match_table[] = { 133static const struct of_device_id lpass_cc_sdm845_match_table[] = {
diff --git a/drivers/clk/qcom/turingcc-qcs404.c b/drivers/clk/qcom/turingcc-qcs404.c
index aa859e6ec9bd..4cfbbf5bf4d9 100644
--- a/drivers/clk/qcom/turingcc-qcs404.c
+++ b/drivers/clk/qcom/turingcc-qcs404.c
@@ -96,7 +96,7 @@ static const struct regmap_config turingcc_regmap_config = {
96 .reg_bits = 32, 96 .reg_bits = 32,
97 .reg_stride = 4, 97 .reg_stride = 4,
98 .val_bits = 32, 98 .val_bits = 32,
99 .max_register = 0x30000, 99 .max_register = 0x23004,
100 .fast_io = true, 100 .fast_io = true,
101}; 101};
102 102
diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h
index b6b127e45634..0837c1a7ae49 100644
--- a/include/dt-bindings/clock/g12a-clkc.h
+++ b/include/dt-bindings/clock/g12a-clkc.h
@@ -137,5 +137,11 @@
137#define CLKID_VDEC_HEVC 207 137#define CLKID_VDEC_HEVC 207
138#define CLKID_VDEC_HEVCF 210 138#define CLKID_VDEC_HEVCF 210
139#define CLKID_TS 212 139#define CLKID_TS 212
140#define CLKID_CPUB_CLK 224
141#define CLKID_GP1_PLL 243
142#define CLKID_DSU_CLK 252
143#define CLKID_CPU1_CLK 253
144#define CLKID_CPU2_CLK 254
145#define CLKID_CPU3_CLK 255
140 146
141#endif /* __G12A_CLKC_H */ 147#endif /* __G12A_CLKC_H */
diff --git a/include/dt-bindings/clock/mt6779-clk.h b/include/dt-bindings/clock/mt6779-clk.h
new file mode 100644
index 000000000000..b083139afbd2
--- /dev/null
+++ b/include/dt-bindings/clock/mt6779-clk.h
@@ -0,0 +1,436 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#ifndef _DT_BINDINGS_CLK_MT6779_H
8#define _DT_BINDINGS_CLK_MT6779_H
9
10/* TOPCKGEN */
11#define CLK_TOP_AXI 1
12#define CLK_TOP_MM 2
13#define CLK_TOP_CAM 3
14#define CLK_TOP_MFG 4
15#define CLK_TOP_CAMTG 5
16#define CLK_TOP_UART 6
17#define CLK_TOP_SPI 7
18#define CLK_TOP_MSDC50_0_HCLK 8
19#define CLK_TOP_MSDC50_0 9
20#define CLK_TOP_MSDC30_1 10
21#define CLK_TOP_MSDC30_2 11
22#define CLK_TOP_AUD 12
23#define CLK_TOP_AUD_INTBUS 13
24#define CLK_TOP_FPWRAP_ULPOSC 14
25#define CLK_TOP_SCP 15
26#define CLK_TOP_ATB 16
27#define CLK_TOP_SSPM 17
28#define CLK_TOP_DPI0 18
29#define CLK_TOP_SCAM 19
30#define CLK_TOP_AUD_1 20
31#define CLK_TOP_AUD_2 21
32#define CLK_TOP_DISP_PWM 22
33#define CLK_TOP_SSUSB_TOP_XHCI 23
34#define CLK_TOP_USB_TOP 24
35#define CLK_TOP_SPM 25
36#define CLK_TOP_I2C 26
37#define CLK_TOP_F52M_MFG 27
38#define CLK_TOP_SENINF 28
39#define CLK_TOP_DXCC 29
40#define CLK_TOP_CAMTG2 30
41#define CLK_TOP_AUD_ENG1 31
42#define CLK_TOP_AUD_ENG2 32
43#define CLK_TOP_FAES_UFSFDE 33
44#define CLK_TOP_FUFS 34
45#define CLK_TOP_IMG 35
46#define CLK_TOP_DSP 36
47#define CLK_TOP_DSP1 37
48#define CLK_TOP_DSP2 38
49#define CLK_TOP_IPU_IF 39
50#define CLK_TOP_CAMTG3 40
51#define CLK_TOP_CAMTG4 41
52#define CLK_TOP_PMICSPI 42
53#define CLK_TOP_MAINPLL_CK 43
54#define CLK_TOP_MAINPLL_D2 44
55#define CLK_TOP_MAINPLL_D3 45
56#define CLK_TOP_MAINPLL_D5 46
57#define CLK_TOP_MAINPLL_D7 47
58#define CLK_TOP_MAINPLL_D2_D2 48
59#define CLK_TOP_MAINPLL_D2_D4 49
60#define CLK_TOP_MAINPLL_D2_D8 50
61#define CLK_TOP_MAINPLL_D2_D16 51
62#define CLK_TOP_MAINPLL_D3_D2 52
63#define CLK_TOP_MAINPLL_D3_D4 53
64#define CLK_TOP_MAINPLL_D3_D8 54
65#define CLK_TOP_MAINPLL_D5_D2 55
66#define CLK_TOP_MAINPLL_D5_D4 56
67#define CLK_TOP_MAINPLL_D7_D2 57
68#define CLK_TOP_MAINPLL_D7_D4 58
69#define CLK_TOP_UNIVPLL_CK 59
70#define CLK_TOP_UNIVPLL_D2 60
71#define CLK_TOP_UNIVPLL_D3 61
72#define CLK_TOP_UNIVPLL_D5 62
73#define CLK_TOP_UNIVPLL_D7 63
74#define CLK_TOP_UNIVPLL_D2_D2 64
75#define CLK_TOP_UNIVPLL_D2_D4 65
76#define CLK_TOP_UNIVPLL_D2_D8 66
77#define CLK_TOP_UNIVPLL_D3_D2 67
78#define CLK_TOP_UNIVPLL_D3_D4 68
79#define CLK_TOP_UNIVPLL_D3_D8 69
80#define CLK_TOP_UNIVPLL_D5_D2 70
81#define CLK_TOP_UNIVPLL_D5_D4 71
82#define CLK_TOP_UNIVPLL_D5_D8 72
83#define CLK_TOP_APLL1_CK 73
84#define CLK_TOP_APLL1_D2 74
85#define CLK_TOP_APLL1_D4 75
86#define CLK_TOP_APLL1_D8 76
87#define CLK_TOP_APLL2_CK 77
88#define CLK_TOP_APLL2_D2 78
89#define CLK_TOP_APLL2_D4 79
90#define CLK_TOP_APLL2_D8 80
91#define CLK_TOP_TVDPLL_CK 81
92#define CLK_TOP_TVDPLL_D2 82
93#define CLK_TOP_TVDPLL_D4 83
94#define CLK_TOP_TVDPLL_D8 84
95#define CLK_TOP_TVDPLL_D16 85
96#define CLK_TOP_MSDCPLL_CK 86
97#define CLK_TOP_MSDCPLL_D2 87
98#define CLK_TOP_MSDCPLL_D4 88
99#define CLK_TOP_MSDCPLL_D8 89
100#define CLK_TOP_MSDCPLL_D16 90
101#define CLK_TOP_AD_OSC_CK 91
102#define CLK_TOP_OSC_D2 92
103#define CLK_TOP_OSC_D4 93
104#define CLK_TOP_OSC_D8 94
105#define CLK_TOP_OSC_D16 95
106#define CLK_TOP_F26M_CK_D2 96
107#define CLK_TOP_MFGPLL_CK 97
108#define CLK_TOP_UNIVP_192M_CK 98
109#define CLK_TOP_UNIVP_192M_D2 99
110#define CLK_TOP_UNIVP_192M_D4 100
111#define CLK_TOP_UNIVP_192M_D8 101
112#define CLK_TOP_UNIVP_192M_D16 102
113#define CLK_TOP_UNIVP_192M_D32 103
114#define CLK_TOP_MMPLL_CK 104
115#define CLK_TOP_MMPLL_D4 105
116#define CLK_TOP_MMPLL_D4_D2 106
117#define CLK_TOP_MMPLL_D4_D4 107
118#define CLK_TOP_MMPLL_D5 108
119#define CLK_TOP_MMPLL_D5_D2 109
120#define CLK_TOP_MMPLL_D5_D4 110
121#define CLK_TOP_MMPLL_D6 111
122#define CLK_TOP_MMPLL_D7 112
123#define CLK_TOP_CLK26M 113
124#define CLK_TOP_CLK13M 114
125#define CLK_TOP_ADSP 115
126#define CLK_TOP_DPMAIF 116
127#define CLK_TOP_VENC 117
128#define CLK_TOP_VDEC 118
129#define CLK_TOP_CAMTM 119
130#define CLK_TOP_PWM 120
131#define CLK_TOP_ADSPPLL_CK 121
132#define CLK_TOP_I2S0_M_SEL 122
133#define CLK_TOP_I2S1_M_SEL 123
134#define CLK_TOP_I2S2_M_SEL 124
135#define CLK_TOP_I2S3_M_SEL 125
136#define CLK_TOP_I2S4_M_SEL 126
137#define CLK_TOP_I2S5_M_SEL 127
138#define CLK_TOP_APLL12_DIV0 128
139#define CLK_TOP_APLL12_DIV1 129
140#define CLK_TOP_APLL12_DIV2 130
141#define CLK_TOP_APLL12_DIV3 131
142#define CLK_TOP_APLL12_DIV4 132
143#define CLK_TOP_APLL12_DIVB 133
144#define CLK_TOP_APLL12_DIV5 134
145#define CLK_TOP_IPE 135
146#define CLK_TOP_DPE 136
147#define CLK_TOP_CCU 137
148#define CLK_TOP_DSP3 138
149#define CLK_TOP_SENINF1 139
150#define CLK_TOP_SENINF2 140
151#define CLK_TOP_AUD_H 141
152#define CLK_TOP_CAMTG5 142
153#define CLK_TOP_TVDPLL_MAINPLL_D2_CK 143
154#define CLK_TOP_AD_OSC2_CK 144
155#define CLK_TOP_OSC2_D2 145
156#define CLK_TOP_OSC2_D3 146
157#define CLK_TOP_FMEM_466M_CK 147
158#define CLK_TOP_ADSPPLL_D4 148
159#define CLK_TOP_ADSPPLL_D5 149
160#define CLK_TOP_ADSPPLL_D6 150
161#define CLK_TOP_OSC_D10 151
162#define CLK_TOP_UNIVPLL_D3_D16 152
163#define CLK_TOP_NR_CLK 153
164
165/* APMIXED */
166#define CLK_APMIXED_ARMPLL_LL 1
167#define CLK_APMIXED_ARMPLL_BL 2
168#define CLK_APMIXED_ARMPLL_BB 3
169#define CLK_APMIXED_CCIPLL 4
170#define CLK_APMIXED_MAINPLL 5
171#define CLK_APMIXED_UNIV2PLL 6
172#define CLK_APMIXED_MSDCPLL 7
173#define CLK_APMIXED_ADSPPLL 8
174#define CLK_APMIXED_MMPLL 9
175#define CLK_APMIXED_MFGPLL 10
176#define CLK_APMIXED_TVDPLL 11
177#define CLK_APMIXED_APLL1 12
178#define CLK_APMIXED_APLL2 13
179#define CLK_APMIXED_SSUSB26M 14
180#define CLK_APMIXED_APPLL26M 15
181#define CLK_APMIXED_MIPIC0_26M 16
182#define CLK_APMIXED_MDPLLGP26M 17
183#define CLK_APMIXED_MM_F26M 18
184#define CLK_APMIXED_UFS26M 19
185#define CLK_APMIXED_MIPIC1_26M 20
186#define CLK_APMIXED_MEMPLL26M 21
187#define CLK_APMIXED_CLKSQ_LVPLL_26M 22
188#define CLK_APMIXED_MIPID0_26M 23
189#define CLK_APMIXED_MIPID1_26M 24
190#define CLK_APMIXED_NR_CLK 25
191
192/* CAMSYS */
193#define CLK_CAM_LARB10 1
194#define CLK_CAM_DFP_VAD 2
195#define CLK_CAM_LARB11 3
196#define CLK_CAM_LARB9 4
197#define CLK_CAM_CAM 5
198#define CLK_CAM_CAMTG 6
199#define CLK_CAM_SENINF 7
200#define CLK_CAM_CAMSV0 8
201#define CLK_CAM_CAMSV1 9
202#define CLK_CAM_CAMSV2 10
203#define CLK_CAM_CAMSV3 11
204#define CLK_CAM_CCU 12
205#define CLK_CAM_FAKE_ENG 13
206#define CLK_CAM_NR_CLK 14
207
208/* INFRA */
209#define CLK_INFRA_PMIC_TMR 1
210#define CLK_INFRA_PMIC_AP 2
211#define CLK_INFRA_PMIC_MD 3
212#define CLK_INFRA_PMIC_CONN 4
213#define CLK_INFRA_SCPSYS 5
214#define CLK_INFRA_SEJ 6
215#define CLK_INFRA_APXGPT 7
216#define CLK_INFRA_ICUSB 8
217#define CLK_INFRA_GCE 9
218#define CLK_INFRA_THERM 10
219#define CLK_INFRA_I2C0 11
220#define CLK_INFRA_I2C1 12
221#define CLK_INFRA_I2C2 13
222#define CLK_INFRA_I2C3 14
223#define CLK_INFRA_PWM_HCLK 15
224#define CLK_INFRA_PWM1 16
225#define CLK_INFRA_PWM2 17
226#define CLK_INFRA_PWM3 18
227#define CLK_INFRA_PWM4 19
228#define CLK_INFRA_PWM 20
229#define CLK_INFRA_UART0 21
230#define CLK_INFRA_UART1 22
231#define CLK_INFRA_UART2 23
232#define CLK_INFRA_UART3 24
233#define CLK_INFRA_GCE_26M 25
234#define CLK_INFRA_CQ_DMA_FPC 26
235#define CLK_INFRA_BTIF 27
236#define CLK_INFRA_SPI0 28
237#define CLK_INFRA_MSDC0 29
238#define CLK_INFRA_MSDC1 30
239#define CLK_INFRA_MSDC2 31
240#define CLK_INFRA_MSDC0_SCK 32
241#define CLK_INFRA_DVFSRC 33
242#define CLK_INFRA_GCPU 34
243#define CLK_INFRA_TRNG 35
244#define CLK_INFRA_AUXADC 36
245#define CLK_INFRA_CPUM 37
246#define CLK_INFRA_CCIF1_AP 38
247#define CLK_INFRA_CCIF1_MD 39
248#define CLK_INFRA_AUXADC_MD 40
249#define CLK_INFRA_MSDC1_SCK 41
250#define CLK_INFRA_MSDC2_SCK 42
251#define CLK_INFRA_AP_DMA 43
252#define CLK_INFRA_XIU 44
253#define CLK_INFRA_DEVICE_APC 45
254#define CLK_INFRA_CCIF_AP 46
255#define CLK_INFRA_DEBUGSYS 47
256#define CLK_INFRA_AUD 48
257#define CLK_INFRA_CCIF_MD 49
258#define CLK_INFRA_DXCC_SEC_CORE 50
259#define CLK_INFRA_DXCC_AO 51
260#define CLK_INFRA_DRAMC_F26M 52
261#define CLK_INFRA_IRTX 53
262#define CLK_INFRA_DISP_PWM 54
263#define CLK_INFRA_DPMAIF_CK 55
264#define CLK_INFRA_AUD_26M_BCLK 56
265#define CLK_INFRA_SPI1 57
266#define CLK_INFRA_I2C4 58
267#define CLK_INFRA_MODEM_TEMP_SHARE 59
268#define CLK_INFRA_SPI2 60
269#define CLK_INFRA_SPI3 61
270#define CLK_INFRA_UNIPRO_SCK 62
271#define CLK_INFRA_UNIPRO_TICK 63
272#define CLK_INFRA_UFS_MP_SAP_BCLK 64
273#define CLK_INFRA_MD32_BCLK 65
274#define CLK_INFRA_SSPM 66
275#define CLK_INFRA_UNIPRO_MBIST 67
276#define CLK_INFRA_SSPM_BUS_HCLK 68
277#define CLK_INFRA_I2C5 69
278#define CLK_INFRA_I2C5_ARBITER 70
279#define CLK_INFRA_I2C5_IMM 71
280#define CLK_INFRA_I2C1_ARBITER 72
281#define CLK_INFRA_I2C1_IMM 73
282#define CLK_INFRA_I2C2_ARBITER 74
283#define CLK_INFRA_I2C2_IMM 75
284#define CLK_INFRA_SPI4 76
285#define CLK_INFRA_SPI5 77
286#define CLK_INFRA_CQ_DMA 78
287#define CLK_INFRA_UFS 79
288#define CLK_INFRA_AES_UFSFDE 80
289#define CLK_INFRA_UFS_TICK 81
290#define CLK_INFRA_MSDC0_SELF 82
291#define CLK_INFRA_MSDC1_SELF 83
292#define CLK_INFRA_MSDC2_SELF 84
293#define CLK_INFRA_SSPM_26M_SELF 85
294#define CLK_INFRA_SSPM_32K_SELF 86
295#define CLK_INFRA_UFS_AXI 87
296#define CLK_INFRA_I2C6 88
297#define CLK_INFRA_AP_MSDC0 89
298#define CLK_INFRA_MD_MSDC0 90
299#define CLK_INFRA_USB 91
300#define CLK_INFRA_DEVMPU_BCLK 92
301#define CLK_INFRA_CCIF2_AP 93
302#define CLK_INFRA_CCIF2_MD 94
303#define CLK_INFRA_CCIF3_AP 95
304#define CLK_INFRA_CCIF3_MD 96
305#define CLK_INFRA_SEJ_F13M 97
306#define CLK_INFRA_AES_BCLK 98
307#define CLK_INFRA_I2C7 99
308#define CLK_INFRA_I2C8 100
309#define CLK_INFRA_FBIST2FPC 101
310#define CLK_INFRA_CCIF4_AP 102
311#define CLK_INFRA_CCIF4_MD 103
312#define CLK_INFRA_FADSP 104
313#define CLK_INFRA_SSUSB_XHCI 105
314#define CLK_INFRA_SPI6 106
315#define CLK_INFRA_SPI7 107
316#define CLK_INFRA_NR_CLK 108
317
318/* MFGCFG */
319#define CLK_MFGCFG_BG3D 1
320#define CLK_MFGCFG_NR_CLK 2
321
322/* IMG */
323#define CLK_IMG_WPE_A 1
324#define CLK_IMG_MFB 2
325#define CLK_IMG_DIP 3
326#define CLK_IMG_LARB6 4
327#define CLK_IMG_LARB5 5
328#define CLK_IMG_NR_CLK 6
329
330/* IPE */
331#define CLK_IPE_LARB7 1
332#define CLK_IPE_LARB8 2
333#define CLK_IPE_SMI_SUBCOM 3
334#define CLK_IPE_FD 4
335#define CLK_IPE_FE 5
336#define CLK_IPE_RSC 6
337#define CLK_IPE_DPE 7
338#define CLK_IPE_NR_CLK 8
339
340/* MM_CONFIG */
341#define CLK_MM_SMI_COMMON 1
342#define CLK_MM_SMI_LARB0 2
343#define CLK_MM_SMI_LARB1 3
344#define CLK_MM_GALS_COMM0 4
345#define CLK_MM_GALS_COMM1 5
346#define CLK_MM_GALS_CCU2MM 6
347#define CLK_MM_GALS_IPU12MM 7
348#define CLK_MM_GALS_IMG2MM 8
349#define CLK_MM_GALS_CAM2MM 9
350#define CLK_MM_GALS_IPU2MM 10
351#define CLK_MM_MDP_DL_TXCK 11
352#define CLK_MM_IPU_DL_TXCK 12
353#define CLK_MM_MDP_RDMA0 13
354#define CLK_MM_MDP_RDMA1 14
355#define CLK_MM_MDP_RSZ0 15
356#define CLK_MM_MDP_RSZ1 16
357#define CLK_MM_MDP_TDSHP 17
358#define CLK_MM_MDP_WROT0 18
359#define CLK_MM_FAKE_ENG 19
360#define CLK_MM_DISP_OVL0 20
361#define CLK_MM_DISP_OVL0_2L 21
362#define CLK_MM_DISP_OVL1_2L 22
363#define CLK_MM_DISP_RDMA0 23
364#define CLK_MM_DISP_RDMA1 24
365#define CLK_MM_DISP_WDMA0 25
366#define CLK_MM_DISP_COLOR0 26
367#define CLK_MM_DISP_CCORR0 27
368#define CLK_MM_DISP_AAL0 28
369#define CLK_MM_DISP_GAMMA0 29
370#define CLK_MM_DISP_DITHER0 30
371#define CLK_MM_DISP_SPLIT 31
372#define CLK_MM_DSI0_MM_CK 32
373#define CLK_MM_DSI0_IF_CK 33
374#define CLK_MM_DPI_MM_CK 34
375#define CLK_MM_DPI_IF_CK 35
376#define CLK_MM_FAKE_ENG2 36
377#define CLK_MM_MDP_DL_RX_CK 37
378#define CLK_MM_IPU_DL_RX_CK 38
379#define CLK_MM_26M 39
380#define CLK_MM_MM_R2Y 40
381#define CLK_MM_DISP_RSZ 41
382#define CLK_MM_MDP_WDMA0 42
383#define CLK_MM_MDP_AAL 43
384#define CLK_MM_MDP_HDR 44
385#define CLK_MM_DBI_MM_CK 45
386#define CLK_MM_DBI_IF_CK 46
387#define CLK_MM_MDP_WROT1 47
388#define CLK_MM_DISP_POSTMASK0 48
389#define CLK_MM_DISP_HRT_BW 49
390#define CLK_MM_DISP_OVL_FBDC 50
391#define CLK_MM_NR_CLK 51
392
393/* VDEC_GCON */
394#define CLK_VDEC_VDEC 1
395#define CLK_VDEC_LARB1 2
396#define CLK_VDEC_GCON_NR_CLK 3
397
398/* VENC_GCON */
399#define CLK_VENC_GCON_LARB 1
400#define CLK_VENC_GCON_VENC 2
401#define CLK_VENC_GCON_JPGENC 3
402#define CLK_VENC_GCON_GALS 4
403#define CLK_VENC_GCON_NR_CLK 5
404
405/* AUD */
406#define CLK_AUD_AFE 1
407#define CLK_AUD_22M 2
408#define CLK_AUD_24M 3
409#define CLK_AUD_APLL2_TUNER 4
410#define CLK_AUD_APLL_TUNER 5
411#define CLK_AUD_TDM 6
412#define CLK_AUD_ADC 7
413#define CLK_AUD_DAC 8
414#define CLK_AUD_DAC_PREDIS 9
415#define CLK_AUD_TML 10
416#define CLK_AUD_NLE 11
417#define CLK_AUD_I2S1_BCLK_SW 12
418#define CLK_AUD_I2S2_BCLK_SW 13
419#define CLK_AUD_I2S3_BCLK_SW 14
420#define CLK_AUD_I2S4_BCLK_SW 15
421#define CLK_AUD_I2S5_BCLK_SW 16
422#define CLK_AUD_CONN_I2S_ASRC 17
423#define CLK_AUD_GENERAL1_ASRC 18
424#define CLK_AUD_GENERAL2_ASRC 19
425#define CLK_AUD_DAC_HIRES 20
426#define CLK_AUD_PDN_ADDA6_ADC 21
427#define CLK_AUD_ADC_HIRES 22
428#define CLK_AUD_ADC_HIRES_TML 23
429#define CLK_AUD_ADDA6_ADC_HIRES 24
430#define CLK_AUD_3RD_DAC 25
431#define CLK_AUD_3RD_DAC_PREDIS 26
432#define CLK_AUD_3RD_DAC_TML 27
433#define CLK_AUD_3RD_DAC_HIRES 28
434#define CLK_AUD_NR_CLK 29
435
436#endif /* _DT_BINDINGS_CLK_MT6779_H */
diff --git a/include/dt-bindings/clock/mt8183-clk.h b/include/dt-bindings/clock/mt8183-clk.h
index 0046506eb24c..a7b470b0ec8a 100644
--- a/include/dt-bindings/clock/mt8183-clk.h
+++ b/include/dt-bindings/clock/mt8183-clk.h
@@ -284,6 +284,10 @@
284#define CLK_INFRA_FBIST2FPC 100 284#define CLK_INFRA_FBIST2FPC 100
285#define CLK_INFRA_NR_CLK 101 285#define CLK_INFRA_NR_CLK 101
286 286
287/* PERICFG */
288#define CLK_PERI_AXI 0
289#define CLK_PERI_NR_CLK 1
290
287/* MFGCFG */ 291/* MFGCFG */
288#define CLK_MFG_BG3D 0 292#define CLK_MFG_BG3D 0
289#define CLK_MFG_NR_CLK 1 293#define CLK_MFG_NR_CLK 1
diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
index 2cd62c98561f..bc3051543347 100644
--- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
+++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
@@ -146,6 +146,8 @@
146#define GCC_MDP_TBU_CLK 138 146#define GCC_MDP_TBU_CLK 138
147#define GCC_QDSS_DAP_CLK 139 147#define GCC_QDSS_DAP_CLK 139
148#define GCC_DCC_XO_CLK 140 148#define GCC_DCC_XO_CLK 140
149#define GCC_WCSS_Q6_AHB_CLK 141
150#define GCC_WCSS_Q6_AXIM_CLK 142
149#define GCC_CDSP_CFG_AHB_CLK 143 151#define GCC_CDSP_CFG_AHB_CLK 143
150#define GCC_BIMC_CDSP_CLK 144 152#define GCC_BIMC_CDSP_CLK 144
151#define GCC_CDSP_TBU_CLK 145 153#define GCC_CDSP_TBU_CLK 145
@@ -173,5 +175,6 @@
173#define GCC_PCIE_0_CORE_STICKY_ARES 19 175#define GCC_PCIE_0_CORE_STICKY_ARES 19
174#define GCC_PCIE_0_SLEEP_ARES 20 176#define GCC_PCIE_0_SLEEP_ARES 20
175#define GCC_PCIE_0_PIPE_ARES 21 177#define GCC_PCIE_0_PIPE_ARES 21
178#define GCC_WDSP_RESTART 22
176 179
177#endif 180#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h
new file mode 100644
index 000000000000..90d60ef94c64
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h
@@ -0,0 +1,243 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8150_H
7#define _DT_BINDINGS_CLK_QCOM_GCC_SM8150_H
8
9/* GCC clocks */
10#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0
11#define GCC_AGGRE_UFS_CARD_AXI_CLK 1
12#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 2
13#define GCC_AGGRE_UFS_PHY_AXI_CLK 3
14#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 4
15#define GCC_AGGRE_USB3_PRIM_AXI_CLK 5
16#define GCC_AGGRE_USB3_SEC_AXI_CLK 6
17#define GCC_BOOT_ROM_AHB_CLK 7
18#define GCC_CAMERA_AHB_CLK 8
19#define GCC_CAMERA_HF_AXI_CLK 9
20#define GCC_CAMERA_SF_AXI_CLK 10
21#define GCC_CAMERA_XO_CLK 11
22#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12
23#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13
24#define GCC_CPUSS_AHB_CLK 14
25#define GCC_CPUSS_AHB_CLK_SRC 15
26#define GCC_CPUSS_DVM_BUS_CLK 16
27#define GCC_CPUSS_GNOC_CLK 17
28#define GCC_CPUSS_RBCPR_CLK 18
29#define GCC_DDRSS_GPU_AXI_CLK 19
30#define GCC_DISP_AHB_CLK 20
31#define GCC_DISP_HF_AXI_CLK 21
32#define GCC_DISP_SF_AXI_CLK 22
33#define GCC_DISP_XO_CLK 23
34#define GCC_EMAC_AXI_CLK 24
35#define GCC_EMAC_PTP_CLK 25
36#define GCC_EMAC_PTP_CLK_SRC 26
37#define GCC_EMAC_RGMII_CLK 27
38#define GCC_EMAC_RGMII_CLK_SRC 28
39#define GCC_EMAC_SLV_AHB_CLK 29
40#define GCC_GP1_CLK 30
41#define GCC_GP1_CLK_SRC 31
42#define GCC_GP2_CLK 32
43#define GCC_GP2_CLK_SRC 33
44#define GCC_GP3_CLK 34
45#define GCC_GP3_CLK_SRC 35
46#define GCC_GPU_CFG_AHB_CLK 36
47#define GCC_GPU_GPLL0_CLK_SRC 37
48#define GCC_GPU_GPLL0_DIV_CLK_SRC 38
49#define GCC_GPU_IREF_CLK 39
50#define GCC_GPU_MEMNOC_GFX_CLK 40
51#define GCC_GPU_SNOC_DVM_GFX_CLK 41
52#define GCC_NPU_AT_CLK 42
53#define GCC_NPU_AXI_CLK 43
54#define GCC_NPU_CFG_AHB_CLK 44
55#define GCC_NPU_GPLL0_CLK_SRC 45
56#define GCC_NPU_GPLL0_DIV_CLK_SRC 46
57#define GCC_NPU_TRIG_CLK 47
58#define GCC_PCIE0_PHY_REFGEN_CLK 48
59#define GCC_PCIE1_PHY_REFGEN_CLK 49
60#define GCC_PCIE_0_AUX_CLK 50
61#define GCC_PCIE_0_AUX_CLK_SRC 51
62#define GCC_PCIE_0_CFG_AHB_CLK 52
63#define GCC_PCIE_0_CLKREF_CLK 53
64#define GCC_PCIE_0_MSTR_AXI_CLK 54
65#define GCC_PCIE_0_PIPE_CLK 55
66#define GCC_PCIE_0_SLV_AXI_CLK 56
67#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57
68#define GCC_PCIE_1_AUX_CLK 58
69#define GCC_PCIE_1_AUX_CLK_SRC 59
70#define GCC_PCIE_1_CFG_AHB_CLK 60
71#define GCC_PCIE_1_CLKREF_CLK 61
72#define GCC_PCIE_1_MSTR_AXI_CLK 62
73#define GCC_PCIE_1_PIPE_CLK 63
74#define GCC_PCIE_1_SLV_AXI_CLK 64
75#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 65
76#define GCC_PCIE_PHY_AUX_CLK 66
77#define GCC_PCIE_PHY_REFGEN_CLK_SRC 67
78#define GCC_PDM2_CLK 68
79#define GCC_PDM2_CLK_SRC 69
80#define GCC_PDM_AHB_CLK 70
81#define GCC_PDM_XO4_CLK 71
82#define GCC_PRNG_AHB_CLK 72
83#define GCC_QMIP_CAMERA_NRT_AHB_CLK 73
84#define GCC_QMIP_CAMERA_RT_AHB_CLK 74
85#define GCC_QMIP_DISP_AHB_CLK 75
86#define GCC_QMIP_VIDEO_CVP_AHB_CLK 76
87#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 77
88#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 78
89#define GCC_QSPI_CORE_CLK 79
90#define GCC_QSPI_CORE_CLK_SRC 80
91#define GCC_QUPV3_WRAP0_S0_CLK 81
92#define GCC_QUPV3_WRAP0_S0_CLK_SRC 82
93#define GCC_QUPV3_WRAP0_S1_CLK 83
94#define GCC_QUPV3_WRAP0_S1_CLK_SRC 84
95#define GCC_QUPV3_WRAP0_S2_CLK 85
96#define GCC_QUPV3_WRAP0_S2_CLK_SRC 86
97#define GCC_QUPV3_WRAP0_S3_CLK 87
98#define GCC_QUPV3_WRAP0_S3_CLK_SRC 88
99#define GCC_QUPV3_WRAP0_S4_CLK 89
100#define GCC_QUPV3_WRAP0_S4_CLK_SRC 90
101#define GCC_QUPV3_WRAP0_S5_CLK 91
102#define GCC_QUPV3_WRAP0_S5_CLK_SRC 92
103#define GCC_QUPV3_WRAP0_S6_CLK 93
104#define GCC_QUPV3_WRAP0_S6_CLK_SRC 94
105#define GCC_QUPV3_WRAP0_S7_CLK 95
106#define GCC_QUPV3_WRAP0_S7_CLK_SRC 96
107#define GCC_QUPV3_WRAP1_S0_CLK 97
108#define GCC_QUPV3_WRAP1_S0_CLK_SRC 98
109#define GCC_QUPV3_WRAP1_S1_CLK 99
110#define GCC_QUPV3_WRAP1_S1_CLK_SRC 100
111#define GCC_QUPV3_WRAP1_S2_CLK 101
112#define GCC_QUPV3_WRAP1_S2_CLK_SRC 102
113#define GCC_QUPV3_WRAP1_S3_CLK 103
114#define GCC_QUPV3_WRAP1_S3_CLK_SRC 104
115#define GCC_QUPV3_WRAP1_S4_CLK 105
116#define GCC_QUPV3_WRAP1_S4_CLK_SRC 106
117#define GCC_QUPV3_WRAP1_S5_CLK 107
118#define GCC_QUPV3_WRAP1_S5_CLK_SRC 108
119#define GCC_QUPV3_WRAP2_S0_CLK 109
120#define GCC_QUPV3_WRAP2_S0_CLK_SRC 110
121#define GCC_QUPV3_WRAP2_S1_CLK 111
122#define GCC_QUPV3_WRAP2_S1_CLK_SRC 112
123#define GCC_QUPV3_WRAP2_S2_CLK 113
124#define GCC_QUPV3_WRAP2_S2_CLK_SRC 114
125#define GCC_QUPV3_WRAP2_S3_CLK 115
126#define GCC_QUPV3_WRAP2_S3_CLK_SRC 116
127#define GCC_QUPV3_WRAP2_S4_CLK 117
128#define GCC_QUPV3_WRAP2_S4_CLK_SRC 118
129#define GCC_QUPV3_WRAP2_S5_CLK 119
130#define GCC_QUPV3_WRAP2_S5_CLK_SRC 120
131#define GCC_QUPV3_WRAP_0_M_AHB_CLK 121
132#define GCC_QUPV3_WRAP_0_S_AHB_CLK 122
133#define GCC_QUPV3_WRAP_1_M_AHB_CLK 123
134#define GCC_QUPV3_WRAP_1_S_AHB_CLK 124
135#define GCC_QUPV3_WRAP_2_M_AHB_CLK 125
136#define GCC_QUPV3_WRAP_2_S_AHB_CLK 126
137#define GCC_SDCC2_AHB_CLK 127
138#define GCC_SDCC2_APPS_CLK 128
139#define GCC_SDCC2_APPS_CLK_SRC 129
140#define GCC_SDCC4_AHB_CLK 130
141#define GCC_SDCC4_APPS_CLK 131
142#define GCC_SDCC4_APPS_CLK_SRC 132
143#define GCC_SYS_NOC_CPUSS_AHB_CLK 133
144#define GCC_TSIF_AHB_CLK 134
145#define GCC_TSIF_INACTIVITY_TIMERS_CLK 135
146#define GCC_TSIF_REF_CLK 136
147#define GCC_TSIF_REF_CLK_SRC 137
148#define GCC_UFS_CARD_AHB_CLK 138
149#define GCC_UFS_CARD_AXI_CLK 139
150#define GCC_UFS_CARD_AXI_CLK_SRC 140
151#define GCC_UFS_CARD_AXI_HW_CTL_CLK 141
152#define GCC_UFS_CARD_CLKREF_CLK 142
153#define GCC_UFS_CARD_ICE_CORE_CLK 143
154#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 144
155#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 145
156#define GCC_UFS_CARD_PHY_AUX_CLK 146
157#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 147
158#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 148
159#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 149
160#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 150
161#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 151
162#define GCC_UFS_CARD_UNIPRO_CORE_CLK 152
163#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 153
164#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 154
165#define GCC_UFS_MEM_CLKREF_CLK 155
166#define GCC_UFS_PHY_AHB_CLK 156
167#define GCC_UFS_PHY_AXI_CLK 157
168#define GCC_UFS_PHY_AXI_CLK_SRC 158
169#define GCC_UFS_PHY_AXI_HW_CTL_CLK 159
170#define GCC_UFS_PHY_ICE_CORE_CLK 160
171#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 161
172#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 162
173#define GCC_UFS_PHY_PHY_AUX_CLK 163
174#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 164
175#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 165
176#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 166
177#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 167
178#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 168
179#define GCC_UFS_PHY_UNIPRO_CORE_CLK 169
180#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 170
181#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 171
182#define GCC_USB30_PRIM_MASTER_CLK 172
183#define GCC_USB30_PRIM_MASTER_CLK_SRC 173
184#define GCC_USB30_PRIM_MOCK_UTMI_CLK 174
185#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 175
186#define GCC_USB30_PRIM_SLEEP_CLK 176
187#define GCC_USB30_SEC_MASTER_CLK 177
188#define GCC_USB30_SEC_MASTER_CLK_SRC 178
189#define GCC_USB30_SEC_MOCK_UTMI_CLK 179
190#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 180
191#define GCC_USB30_SEC_SLEEP_CLK 181
192#define GCC_USB3_PRIM_CLKREF_CLK 182
193#define GCC_USB3_PRIM_PHY_AUX_CLK 183
194#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 184
195#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 185
196#define GCC_USB3_PRIM_PHY_PIPE_CLK 186
197#define GCC_USB3_SEC_CLKREF_CLK 187
198#define GCC_USB3_SEC_PHY_AUX_CLK 188
199#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 189
200#define GCC_USB3_SEC_PHY_COM_AUX_CLK 190
201#define GCC_USB3_SEC_PHY_PIPE_CLK 191
202#define GCC_VIDEO_AHB_CLK 192
203#define GCC_VIDEO_AXI0_CLK 193
204#define GCC_VIDEO_AXI1_CLK 194
205#define GCC_VIDEO_AXIC_CLK 195
206#define GCC_VIDEO_XO_CLK 196
207#define GPLL0 197
208#define GPLL0_OUT_EVEN 198
209#define GPLL7 199
210#define GPLL9 200
211
212/* Reset clocks */
213#define GCC_EMAC_BCR 0
214#define GCC_GPU_BCR 1
215#define GCC_MMSS_BCR 2
216#define GCC_NPU_BCR 3
217#define GCC_PCIE_0_BCR 4
218#define GCC_PCIE_0_PHY_BCR 5
219#define GCC_PCIE_1_BCR 6
220#define GCC_PCIE_1_PHY_BCR 7
221#define GCC_PCIE_PHY_BCR 8
222#define GCC_PDM_BCR 9
223#define GCC_PRNG_BCR 10
224#define GCC_QSPI_BCR 11
225#define GCC_QUPV3_WRAPPER_0_BCR 12
226#define GCC_QUPV3_WRAPPER_1_BCR 13
227#define GCC_QUPV3_WRAPPER_2_BCR 14
228#define GCC_QUSB2PHY_PRIM_BCR 15
229#define GCC_QUSB2PHY_SEC_BCR 16
230#define GCC_USB3_PHY_PRIM_BCR 17
231#define GCC_USB3_DP_PHY_PRIM_BCR 18
232#define GCC_USB3_PHY_SEC_BCR 19
233#define GCC_USB3PHY_PHY_SEC_BCR 20
234#define GCC_SDCC2_BCR 21
235#define GCC_SDCC4_BCR 22
236#define GCC_TSIF_BCR 23
237#define GCC_UFS_CARD_BCR 24
238#define GCC_UFS_PHY_BCR 25
239#define GCC_USB30_PRIM_BCR 26
240#define GCC_USB30_SEC_BCR 27
241#define GCC_USB_PHY_CFG_AHB2PHY_BCR 28
242
243#endif
diff --git a/include/dt-bindings/reset-controller/mt8183-resets.h b/include/dt-bindings/reset-controller/mt8183-resets.h
new file mode 100644
index 000000000000..8804e34ebdd4
--- /dev/null
+++ b/include/dt-bindings/reset-controller/mt8183-resets.h
@@ -0,0 +1,81 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Yong Liang <yong.liang@mediatek.com>
5 */
6
7#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8183
8#define _DT_BINDINGS_RESET_CONTROLLER_MT8183
9
10/* INFRACFG AO resets */
11#define MT8183_INFRACFG_AO_THERM_SW_RST 0
12#define MT8183_INFRACFG_AO_USB_TOP_SW_RST 1
13#define MT8183_INFRACFG_AO_MM_IOMMU_SW_RST 3
14#define MT8183_INFRACFG_AO_MSDC3_SW_RST 4
15#define MT8183_INFRACFG_AO_MSDC2_SW_RST 5
16#define MT8183_INFRACFG_AO_MSDC1_SW_RST 6
17#define MT8183_INFRACFG_AO_MSDC0_SW_RST 7
18#define MT8183_INFRACFG_AO_APDMA_SW_RST 9
19#define MT8183_INFRACFG_AO_MIMP_D_SW_RST 10
20#define MT8183_INFRACFG_AO_BTIF_SW_RST 12
21#define MT8183_INFRACFG_AO_DISP_PWM_SW_RST 14
22#define MT8183_INFRACFG_AO_AUXADC_SW_RST 15
23
24#define MT8183_INFRACFG_AO_IRTX_SW_RST 32
25#define MT8183_INFRACFG_AO_SPI0_SW_RST 33
26#define MT8183_INFRACFG_AO_I2C0_SW_RST 34
27#define MT8183_INFRACFG_AO_I2C1_SW_RST 35
28#define MT8183_INFRACFG_AO_I2C2_SW_RST 36
29#define MT8183_INFRACFG_AO_I2C3_SW_RST 37
30#define MT8183_INFRACFG_AO_UART0_SW_RST 38
31#define MT8183_INFRACFG_AO_UART1_SW_RST 39
32#define MT8183_INFRACFG_AO_UART2_SW_RST 40
33#define MT8183_INFRACFG_AO_PWM_SW_RST 41
34#define MT8183_INFRACFG_AO_SPI1_SW_RST 42
35#define MT8183_INFRACFG_AO_I2C4_SW_RST 43
36#define MT8183_INFRACFG_AO_DVFSP_SW_RST 44
37#define MT8183_INFRACFG_AO_SPI2_SW_RST 45
38#define MT8183_INFRACFG_AO_SPI3_SW_RST 46
39#define MT8183_INFRACFG_AO_UFSHCI_SW_RST 47
40
41#define MT8183_INFRACFG_AO_PMIC_WRAP_SW_RST 64
42#define MT8183_INFRACFG_AO_SPM_SW_RST 65
43#define MT8183_INFRACFG_AO_USBSIF_SW_RST 66
44#define MT8183_INFRACFG_AO_KP_SW_RST 68
45#define MT8183_INFRACFG_AO_APXGPT_SW_RST 69
46#define MT8183_INFRACFG_AO_CLDMA_AO_SW_RST 70
47#define MT8183_INFRACFG_AO_UNIPRO_UFS_SW_RST 71
48#define MT8183_INFRACFG_AO_DX_CC_SW_RST 72
49#define MT8183_INFRACFG_AO_UFSPHY_SW_RST 73
50
51#define MT8183_INFRACFG_AO_DX_CC_SEC_SW_RST 96
52#define MT8183_INFRACFG_AO_GCE_SW_RST 97
53#define MT8183_INFRACFG_AO_CLDMA_SW_RST 98
54#define MT8183_INFRACFG_AO_TRNG_SW_RST 99
55#define MT8183_INFRACFG_AO_AP_MD_CCIF_1_SW_RST 103
56#define MT8183_INFRACFG_AO_AP_MD_CCIF_SW_RST 104
57#define MT8183_INFRACFG_AO_I2C1_IMM_SW_RST 105
58#define MT8183_INFRACFG_AO_I2C1_ARB_SW_RST 106
59#define MT8183_INFRACFG_AO_I2C2_IMM_SW_RST 107
60#define MT8183_INFRACFG_AO_I2C2_ARB_SW_RST 108
61#define MT8183_INFRACFG_AO_I2C5_SW_RST 109
62#define MT8183_INFRACFG_AO_I2C5_IMM_SW_RST 110
63#define MT8183_INFRACFG_AO_I2C5_ARB_SW_RST 111
64#define MT8183_INFRACFG_AO_SPI4_SW_RST 112
65#define MT8183_INFRACFG_AO_SPI5_SW_RST 113
66#define MT8183_INFRACFG_AO_INFRA2MFGAXI_CBIP_CLAS_SW_RST 114
67#define MT8183_INFRACFG_AO_MFGAXI2INFRA_M0_CBIP_GLAS_OUT_SW_RST 115
68#define MT8183_INFRACFG_AO_MFGAXI2INFRA_M1_CBIP_GLAS_OUT_SW_RST 116
69#define MT8183_INFRACFG_AO_UFS_AES_SW_RST 117
70#define MT8183_INFRACFG_AO_CCU_I2C_IRQ_SW_RST 118
71#define MT8183_INFRACFG_AO_CCU_I2C_DMA_SW_RST 119
72#define MT8183_INFRACFG_AO_I2C6_SW_RST 120
73#define MT8183_INFRACFG_AO_CCU_GALS_SW_RST 121
74#define MT8183_INFRACFG_AO_IPU_GALS_SW_RST 122
75#define MT8183_INFRACFG_AO_CONN2AP_GALS_SW_RST 123
76#define MT8183_INFRACFG_AO_AP_MD_CCIF2_SW_RST 124
77#define MT8183_INFRACFG_AO_AP_MD_CCIF3_SW_RST 125
78#define MT8183_INFRACFG_AO_I2C7_SW_RST 126
79#define MT8183_INFRACFG_AO_I2C8_SW_RST 127
80
81#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */
diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
new file mode 100644
index 000000000000..14b78dabed0e
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
@@ -0,0 +1,38 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2019 BayLibre, SAS.
4 * Author: Jerome Brunet <jbrunet@baylibre.com>
5 *
6 */
7
8#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H
9#define _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H
10
11#define AUD_RESET_PDM 0
12#define AUD_RESET_TDMIN_A 1
13#define AUD_RESET_TDMIN_B 2
14#define AUD_RESET_TDMIN_C 3
15#define AUD_RESET_TDMIN_LB 4
16#define AUD_RESET_LOOPBACK 5
17#define AUD_RESET_TODDR_A 6
18#define AUD_RESET_TODDR_B 7
19#define AUD_RESET_TODDR_C 8
20#define AUD_RESET_FRDDR_A 9
21#define AUD_RESET_FRDDR_B 10
22#define AUD_RESET_FRDDR_C 11
23#define AUD_RESET_TDMOUT_A 12
24#define AUD_RESET_TDMOUT_B 13
25#define AUD_RESET_TDMOUT_C 14
26#define AUD_RESET_SPDIFOUT 15
27#define AUD_RESET_SPDIFOUT_B 16
28#define AUD_RESET_SPDIFIN 17
29#define AUD_RESET_EQDRC 18
30#define AUD_RESET_RESAMPLE 19
31#define AUD_RESET_DDRARB 20
32#define AUD_RESET_POWDET 21
33#define AUD_RESET_TORAM 22
34#define AUD_RESET_TOACODEC 23
35#define AUD_RESET_TOHDMITX 24
36#define AUD_RESET_CLKTREE 25
37
38#endif
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 2ae7604783dd..dce5521a9bf6 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -817,6 +817,7 @@ unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
817struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); 817struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
818struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, 818struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
819 unsigned int index); 819 unsigned int index);
820int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
820unsigned int __clk_get_enable_count(struct clk *clk); 821unsigned int __clk_get_enable_count(struct clk *clk);
821unsigned long clk_hw_get_rate(const struct clk_hw *hw); 822unsigned long clk_hw_get_rate(const struct clk_hw *hw);
822unsigned long __clk_get_flags(struct clk *clk); 823unsigned long __clk_get_flags(struct clk *clk);
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-10 19:37:18 -0400