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-rw-r--r--Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt42
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt22
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt1
-rw-r--r--Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc.txt21
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt7
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/clk-aspeed.c78
-rw-r--r--drivers/clk/clk-aspeed.h82
-rw-r--r--drivers/clk/clk-ast2600.c704
-rw-r--r--drivers/clk/clk-composite.c1
-rw-r--r--drivers/clk/clk-qoriq.c2
-rw-r--r--drivers/clk/clk-si5341.c1
-rw-r--r--drivers/clk/clk.c58
-rw-r--r--drivers/clk/davinci/pll.c5
-rw-r--r--drivers/clk/ingenic/jz4725b-cgu.c2
-rw-r--r--drivers/clk/ingenic/jz4740-cgu.c11
-rw-r--r--drivers/clk/ingenic/jz4770-cgu.c2
-rw-r--r--drivers/clk/ingenic/jz4780-cgu.c2
-rw-r--r--drivers/clk/mediatek/Kconfig56
-rw-r--r--drivers/clk/mediatek/Makefile9
-rw-r--r--drivers/clk/mediatek/clk-gate.c5
-rw-r--r--drivers/clk/mediatek/clk-gate.h3
-rw-r--r--drivers/clk/mediatek/clk-mt6779-aud.c117
-rw-r--r--drivers/clk/mediatek/clk-mt6779-cam.c66
-rw-r--r--drivers/clk/mediatek/clk-mt6779-img.c58
-rw-r--r--drivers/clk/mediatek/clk-mt6779-ipe.c60
-rw-r--r--drivers/clk/mediatek/clk-mt6779-mfg.c55
-rw-r--r--drivers/clk/mediatek/clk-mt6779-mm.c113
-rw-r--r--drivers/clk/mediatek/clk-mt6779-vdec.c67
-rw-r--r--drivers/clk/mediatek/clk-mt6779-venc.c58
-rw-r--r--drivers/clk/mediatek/clk-mt6779.c1315
-rw-r--r--drivers/clk/mediatek/clk-mt8183-mfgcfg.c7
-rw-r--r--drivers/clk/mediatek/clk-mt8183.c44
-rw-r--r--drivers/clk/mediatek/clk-mtk.c16
-rw-r--r--drivers/clk/mediatek/clk-mtk.h8
-rw-r--r--drivers/clk/mediatek/reset.c56
-rw-r--r--drivers/clk/mvebu/Kconfig8
-rw-r--r--drivers/clk/mvebu/Makefile2
-rw-r--r--drivers/clk/mvebu/ap-cpu-clk.c356
-rw-r--r--drivers/clk/mvebu/ap806-system-controller.c178
-rw-r--r--drivers/clk/mvebu/armada_ap_cp_helper.c30
-rw-r--r--drivers/clk/mvebu/armada_ap_cp_helper.h11
-rw-r--r--drivers/clk/mvebu/cp110-system-controller.c32
-rw-r--r--drivers/clk/qcom/Kconfig9
-rw-r--r--drivers/clk/qcom/Makefile1
-rw-r--r--drivers/clk/qcom/clk-alpha-pll.c236
-rw-r--r--drivers/clk/qcom/clk-alpha-pll.h7
-rw-r--r--drivers/clk/qcom/clk-rcg2.c2
-rw-r--r--drivers/clk/qcom/clk-rpmh.c38
-rw-r--r--drivers/clk/qcom/common.c20
-rw-r--r--drivers/clk/qcom/common.h2
-rw-r--r--drivers/clk/qcom/gcc-ipq8074.c2
-rw-r--r--drivers/clk/qcom/gcc-msm8998.c4
-rw-r--r--drivers/clk/qcom/gcc-qcs404.c34
-rw-r--r--drivers/clk/qcom/gcc-sdm660.c2
-rw-r--r--drivers/clk/qcom/gcc-sdm845.c4
-rw-r--r--drivers/clk/qcom/gcc-sm8150.c3588
-rw-r--r--drivers/clk/qcom/lpasscc-sdm845.c23
-rw-r--r--drivers/clk/qcom/turingcc-qcs404.c2
-rw-r--r--drivers/clk/st/clk-flexgen.c1
-rw-r--r--drivers/clk/st/clkgen-fsyn.c1
-rw-r--r--drivers/clk/st/clkgen-pll.c13
-rw-r--r--drivers/clk/ti/clk-814x.c1
-rw-r--r--drivers/clk/versatile/clk-versatile.c1
-rw-r--r--include/dt-bindings/clock/ast2600-clock.h113
-rw-r--r--include/dt-bindings/clock/mt6779-clk.h436
-rw-r--r--include/dt-bindings/clock/mt8183-clk.h4
-rw-r--r--include/dt-bindings/clock/qcom,gcc-qcs404.h3
-rw-r--r--include/dt-bindings/clock/qcom,gcc-sm8150.h243
-rw-r--r--include/dt-bindings/reset-controller/mt8183-resets.h81
-rw-r--r--include/linux/clk.h17
81 files changed, 8412 insertions, 258 deletions
diff --git a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
index 7b8b8eb0191f..26410fbb85be 100644
--- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
@@ -18,17 +18,19 @@ Clocks:
18------- 18-------
19 19
20 20
21The Device Tree node representing the AP806 system controller provides 21The Device Tree node representing the AP806/AP807 system controller
22a number of clocks: 22provides a number of clocks:
23 23
24 - 0: clock of CPU cluster 0 24 - 0: reference clock of CPU cluster 0
25 - 1: clock of CPU cluster 1 25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz 26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL 27 - 3: MSS clock, derived from the fixed PLL
28 28
29Required properties: 29Required properties:
30 30
31 - compatible: must be: "marvell,ap806-clock" 31 - compatible: must be one of:
32 * "marvell,ap806-clock"
33 * "marvell,ap807-clock"
32 - #clock-cells: must be set to 1 34 - #clock-cells: must be set to 1
33 35
34Pinctrl: 36Pinctrl:
@@ -143,3 +145,33 @@ ap_syscon1: system-controller@6f8000 {
143 #thermal-sensor-cells = <1>; 145 #thermal-sensor-cells = <1>;
144 }; 146 };
145}; 147};
148
149Cluster clocks:
150---------------
151
152Device Tree Clock bindings for cluster clock of Marvell
153AP806/AP807. Each cluster contain up to 2 CPUs running at the same
154frequency.
155
156Required properties:
157 - compatible: must be one of:
158 * "marvell,ap806-cpu-clock"
159 * "marvell,ap807-cpu-clock"
160- #clock-cells : should be set to 1.
161
162- clocks : shall be the input parent clock(s) phandle for the clock
163 (one per cluster)
164
165- reg: register range associated with the cluster clocks
166
167ap_syscon1: system-controller@6f8000 {
168 compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd";
169 reg = <0x6f8000 0x1000>;
170
171 cpu_clk: clock-cpu@278 {
172 compatible = "marvell,ap806-cpu-clock";
173 clocks = <&ap_clk 0>, <&ap_clk 1>;
174 #clock-cells = <1>;
175 reg = <0x278 0xa30>;
176 };
177};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
index 161e63a6c254..ff000ccade78 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
@@ -8,6 +8,7 @@ Required Properties:
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-apmixedsys" 9 - "mediatek,mt2701-apmixedsys"
10 - "mediatek,mt2712-apmixedsys", "syscon" 10 - "mediatek,mt2712-apmixedsys", "syscon"
11 - "mediatek,mt6779-apmixedsys", "syscon"
11 - "mediatek,mt6797-apmixedsys" 12 - "mediatek,mt6797-apmixedsys"
12 - "mediatek,mt7622-apmixedsys" 13 - "mediatek,mt7622-apmixedsys"
13 - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys" 14 - "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
index 07c9d813465c..e4ca7b703123 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
@@ -7,6 +7,7 @@ Required Properties:
7 7
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-audsys", "syscon" 9 - "mediatek,mt2701-audsys", "syscon"
10 - "mediatek,mt6779-audio", "syscon"
10 - "mediatek,mt7622-audsys", "syscon" 11 - "mediatek,mt7622-audsys", "syscon"
11 - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon" 12 - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
12 - "mediatek,mt8183-audiosys", "syscon" 13 - "mediatek,mt8183-audiosys", "syscon"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
index d8930f64aa98..1f4aaa15a37e 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,camsys.txt
@@ -6,6 +6,7 @@ The MediaTek camsys controller provides various clocks to the system.
6Required Properties: 6Required Properties:
7 7
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt6779-camsys", "syscon"
9 - "mediatek,mt8183-camsys", "syscon" 10 - "mediatek,mt8183-camsys", "syscon"
10- #clock-cells: Must be 1 11- #clock-cells: Must be 1
11 12
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
index e3bc4a1e7a6e..2b693e343c56 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imgsys.txt
@@ -8,6 +8,7 @@ Required Properties:
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-imgsys", "syscon" 9 - "mediatek,mt2701-imgsys", "syscon"
10 - "mediatek,mt2712-imgsys", "syscon" 10 - "mediatek,mt2712-imgsys", "syscon"
11 - "mediatek,mt6779-imgsys", "syscon"
11 - "mediatek,mt6797-imgsys", "syscon" 12 - "mediatek,mt6797-imgsys", "syscon"
12 - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon" 13 - "mediatek,mt7623-imgsys", "mediatek,mt2701-imgsys", "syscon"
13 - "mediatek,mt8173-imgsys", "syscon" 14 - "mediatek,mt8173-imgsys", "syscon"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
index a90913988d7e..db2f4fd754e7 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
@@ -9,6 +9,7 @@ Required Properties:
9- compatible: Should be one of: 9- compatible: Should be one of:
10 - "mediatek,mt2701-infracfg", "syscon" 10 - "mediatek,mt2701-infracfg", "syscon"
11 - "mediatek,mt2712-infracfg", "syscon" 11 - "mediatek,mt2712-infracfg", "syscon"
12 - "mediatek,mt6779-infracfg_ao", "syscon"
12 - "mediatek,mt6797-infracfg", "syscon" 13 - "mediatek,mt6797-infracfg", "syscon"
13 - "mediatek,mt7622-infracfg", "syscon" 14 - "mediatek,mt7622-infracfg", "syscon"
14 - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon" 15 - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt
new file mode 100644
index 000000000000..2ce889b023d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ipesys.txt
@@ -0,0 +1,22 @@
1Mediatek ipesys controller
2============================
3
4The Mediatek ipesys controller provides various clocks to the system.
5
6Required Properties:
7
8- compatible: Should be one of:
9 - "mediatek,mt6779-ipesys", "syscon"
10- #clock-cells: Must be 1
11
12The ipesys controller uses the common clk binding from
13Documentation/devicetree/bindings/clock/clock-bindings.txt
14The available clocks are defined in dt-bindings/clock/mt*-clk.h.
15
16Example:
17
18ipesys: clock-controller@1b000000 {
19 compatible = "mediatek,mt6779-ipesys", "syscon";
20 reg = <0 0x1b000000 0 0x1000>;
21 #clock-cells = <1>;
22};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
index 72787e7dd227..ad5f9d2f6818 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mfgcfg.txt
@@ -7,6 +7,7 @@ Required Properties:
7 7
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2712-mfgcfg", "syscon" 9 - "mediatek,mt2712-mfgcfg", "syscon"
10 - "mediatek,mt6779-mfgcfg", "syscon"
10 - "mediatek,mt8183-mfgcfg", "syscon" 11 - "mediatek,mt8183-mfgcfg", "syscon"
11- #clock-cells: Must be 1 12- #clock-cells: Must be 1
12 13
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
index 545eab717c96..301eefbe1618 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
@@ -8,6 +8,7 @@ Required Properties:
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-mmsys", "syscon" 9 - "mediatek,mt2701-mmsys", "syscon"
10 - "mediatek,mt2712-mmsys", "syscon" 10 - "mediatek,mt2712-mmsys", "syscon"
11 - "mediatek,mt6779-mmsys", "syscon"
11 - "mediatek,mt6797-mmsys", "syscon" 12 - "mediatek,mt6797-mmsys", "syscon"
12 - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon" 13 - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
13 - "mediatek,mt8173-mmsys", "syscon" 14 - "mediatek,mt8173-mmsys", "syscon"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
index 4c7e478117a0..ecf027a9003a 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
@@ -14,6 +14,7 @@ Required Properties:
14 - "mediatek,mt7629-pericfg", "syscon" 14 - "mediatek,mt7629-pericfg", "syscon"
15 - "mediatek,mt8135-pericfg", "syscon" 15 - "mediatek,mt8135-pericfg", "syscon"
16 - "mediatek,mt8173-pericfg", "syscon" 16 - "mediatek,mt8173-pericfg", "syscon"
17 - "mediatek,mt8183-pericfg", "syscon"
17- #clock-cells: Must be 1 18- #clock-cells: Must be 1
18- #reset-cells: Must be 1 19- #reset-cells: Must be 1
19 20
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
index a023b8338960..0293d693ce0c 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.txt
@@ -8,6 +8,7 @@ Required Properties:
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-topckgen" 9 - "mediatek,mt2701-topckgen"
10 - "mediatek,mt2712-topckgen", "syscon" 10 - "mediatek,mt2712-topckgen", "syscon"
11 - "mediatek,mt6779-topckgen", "syscon"
11 - "mediatek,mt6797-topckgen" 12 - "mediatek,mt6797-topckgen"
12 - "mediatek,mt7622-topckgen" 13 - "mediatek,mt7622-topckgen"
13 - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen" 14 - "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
index 57176bb8dbb5..7894558b7a1c 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vdecsys.txt
@@ -8,6 +8,7 @@ Required Properties:
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2701-vdecsys", "syscon" 9 - "mediatek,mt2701-vdecsys", "syscon"
10 - "mediatek,mt2712-vdecsys", "syscon" 10 - "mediatek,mt2712-vdecsys", "syscon"
11 - "mediatek,mt6779-vdecsys", "syscon"
11 - "mediatek,mt6797-vdecsys", "syscon" 12 - "mediatek,mt6797-vdecsys", "syscon"
12 - "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon" 13 - "mediatek,mt7623-vdecsys", "mediatek,mt2701-vdecsys", "syscon"
13 - "mediatek,mt8173-vdecsys", "syscon" 14 - "mediatek,mt8173-vdecsys", "syscon"
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
index c9faa6269087..6a6a14e15cd7 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vencsys.txt
@@ -7,6 +7,7 @@ Required Properties:
7 7
8- compatible: Should be one of: 8- compatible: Should be one of:
9 - "mediatek,mt2712-vencsys", "syscon" 9 - "mediatek,mt2712-vencsys", "syscon"
10 - "mediatek,mt6779-vencsys", "syscon"
10 - "mediatek,mt6797-vencsys", "syscon" 11 - "mediatek,mt6797-vencsys", "syscon"
11 - "mediatek,mt8173-vencsys", "syscon" 12 - "mediatek,mt8173-vencsys", "syscon"
12 - "mediatek,mt8183-vencsys", "syscon" 13 - "mediatek,mt8183-vencsys", "syscon"
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 8661c3cd3ccf..d14362ad4132 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -23,6 +23,7 @@ Required properties :
23 "qcom,gcc-sdm630" 23 "qcom,gcc-sdm630"
24 "qcom,gcc-sdm660" 24 "qcom,gcc-sdm660"
25 "qcom,gcc-sdm845" 25 "qcom,gcc-sdm845"
26 "qcom,gcc-sm8150"
26 27
27- reg : shall contain base register location and length 28- reg : shall contain base register location and length
28- #clock-cells : shall contain 1 29- #clock-cells : shall contain 1
@@ -38,6 +39,13 @@ Documentation/devicetree/bindings/thermal/qcom-tsens.txt
38- protected-clocks : Protected clock specifier list as per common clock 39- protected-clocks : Protected clock specifier list as per common clock
39 binding. 40 binding.
40 41
42For SM8150 only:
43 - clocks: a list of phandles and clock-specifier pairs,
44 one for each entry in clock-names.
45 - clock-names: "bi_tcxo" (required)
46 "sleep_clk" (optional)
47 "aud_ref_clock" (optional)
48
41Example: 49Example:
42 clock-controller@900000 { 50 clock-controller@900000 {
43 compatible = "qcom,gcc-msm8960"; 51 compatible = "qcom,gcc-msm8960";
@@ -71,3 +79,16 @@ Example of GCC with protected-clocks properties:
71 <GCC_LPASS_Q6_AXI_CLK>, 79 <GCC_LPASS_Q6_AXI_CLK>,
72 <GCC_LPASS_SWAY_CLK>; 80 <GCC_LPASS_SWAY_CLK>;
73 }; 81 };
82
83Example of GCC with clocks
84 gcc: clock-controller@100000 {
85 compatible = "qcom,gcc-sm8150";
86 reg = <0x00100000 0x1f0000>;
87 #clock-cells = <1>;
88 #reset-cells = <1>;
89 #power-domain-cells = <1>;
90 clock-names = "bi_tcxo",
91 "sleep_clk";
92 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
93 <&sleep_clk>;
94 };
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt b/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt
index 3c007653da31..365bbde599b1 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt
@@ -6,9 +6,14 @@ some Qualcomm Technologies Inc. SoCs. It accepts clock requests from
6other hardware subsystems via RSC to control clocks. 6other hardware subsystems via RSC to control clocks.
7 7
8Required properties : 8Required properties :
9- compatible : shall contain "qcom,sdm845-rpmh-clk" 9- compatible : must be one of:
10 "qcom,sdm845-rpmh-clk"
11 "qcom,sm8150-rpmh-clk"
10 12
11- #clock-cells : must contain 1 13- #clock-cells : must contain 1
14- clocks: a list of phandles and clock-specifier pairs,
15 one for each entry in clock-names.
16- clock-names: Parent board clock: "xo".
12 17
13Example : 18Example :
14 19
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0cad76021297..0138fb14e6f8 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
30obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o 30obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
31obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o 31obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
32obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o 32obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o
33obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o
33obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o 34obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
34obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o 35obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
35obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o 36obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o
diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
index 42b4df6ba249..abf06fb6453e 100644
--- a/drivers/clk/clk-aspeed.c
+++ b/drivers/clk/clk-aspeed.c
@@ -1,19 +1,19 @@
1// SPDX-License-Identifier: GPL-2.0+ 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright IBM Corp
2 3
3#define pr_fmt(fmt) "clk-aspeed: " fmt 4#define pr_fmt(fmt) "clk-aspeed: " fmt
4 5
5#include <linux/clk-provider.h>
6#include <linux/mfd/syscon.h> 6#include <linux/mfd/syscon.h>
7#include <linux/of_address.h> 7#include <linux/of_address.h>
8#include <linux/of_device.h> 8#include <linux/of_device.h>
9#include <linux/platform_device.h> 9#include <linux/platform_device.h>
10#include <linux/regmap.h> 10#include <linux/regmap.h>
11#include <linux/reset-controller.h>
12#include <linux/slab.h> 11#include <linux/slab.h>
13#include <linux/spinlock.h>
14 12
15#include <dt-bindings/clock/aspeed-clock.h> 13#include <dt-bindings/clock/aspeed-clock.h>
16 14
15#include "clk-aspeed.h"
16
17#define ASPEED_NUM_CLKS 36 17#define ASPEED_NUM_CLKS 36
18 18
19#define ASPEED_RESET2_OFFSET 32 19#define ASPEED_RESET2_OFFSET 32
@@ -42,48 +42,6 @@ static struct clk_hw_onecell_data *aspeed_clk_data;
42 42
43static void __iomem *scu_base; 43static void __iomem *scu_base;
44 44
45/**
46 * struct aspeed_gate_data - Aspeed gated clocks
47 * @clock_idx: bit used to gate this clock in the clock register
48 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
49 * reset is required when enabling the clock
50 * @name: the clock name
51 * @parent_name: the name of the parent clock
52 * @flags: standard clock framework flags
53 */
54struct aspeed_gate_data {
55 u8 clock_idx;
56 s8 reset_idx;
57 const char *name;
58 const char *parent_name;
59 unsigned long flags;
60};
61
62/**
63 * struct aspeed_clk_gate - Aspeed specific clk_gate structure
64 * @hw: handle between common and hardware-specific interfaces
65 * @reg: register controlling gate
66 * @clock_idx: bit used to gate this clock in the clock register
67 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
68 * reset is required when enabling the clock
69 * @flags: hardware-specific flags
70 * @lock: register lock
71 *
72 * Some of the clocks in the Aspeed SoC must be put in reset before enabling.
73 * This modified version of clk_gate allows an optional reset bit to be
74 * specified.
75 */
76struct aspeed_clk_gate {
77 struct clk_hw hw;
78 struct regmap *map;
79 u8 clock_idx;
80 s8 reset_idx;
81 u8 flags;
82 spinlock_t *lock;
83};
84
85#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
86
87/* TODO: ask Aspeed about the actual parent data */ 45/* TODO: ask Aspeed about the actual parent data */
88static const struct aspeed_gate_data aspeed_gates[] = { 46static const struct aspeed_gate_data aspeed_gates[] = {
89 /* clk rst name parent flags */ 47 /* clk rst name parent flags */
@@ -208,13 +166,6 @@ static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val)
208 mult, div); 166 mult, div);
209} 167}
210 168
211struct aspeed_clk_soc_data {
212 const struct clk_div_table *div_table;
213 const struct clk_div_table *eclk_div_table;
214 const struct clk_div_table *mac_div_table;
215 struct clk_hw *(*calc_pll)(const char *name, u32 val);
216};
217
218static const struct aspeed_clk_soc_data ast2500_data = { 169static const struct aspeed_clk_soc_data ast2500_data = {
219 .div_table = ast2500_div_table, 170 .div_table = ast2500_div_table,
220 .eclk_div_table = ast2500_eclk_div_table, 171 .eclk_div_table = ast2500_eclk_div_table,
@@ -315,18 +266,6 @@ static const struct clk_ops aspeed_clk_gate_ops = {
315 .is_enabled = aspeed_clk_is_enabled, 266 .is_enabled = aspeed_clk_is_enabled,
316}; 267};
317 268
318/**
319 * struct aspeed_reset - Aspeed reset controller
320 * @map: regmap to access the containing system controller
321 * @rcdev: reset controller device
322 */
323struct aspeed_reset {
324 struct regmap *map;
325 struct reset_controller_dev rcdev;
326};
327
328#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
329
330static const u8 aspeed_resets[] = { 269static const u8 aspeed_resets[] = {
331 /* SCU04 resets */ 270 /* SCU04 resets */
332 [ASPEED_RESET_XDMA] = 25, 271 [ASPEED_RESET_XDMA] = 25,
@@ -500,9 +439,14 @@ static int aspeed_clk_probe(struct platform_device *pdev)
500 return PTR_ERR(hw); 439 return PTR_ERR(hw);
501 aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw; 440 aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw;
502 441
503 /* SD/SDIO clock divider (TODO: There's a gate too) */ 442 /* SD/SDIO clock divider and gate */
504 hw = clk_hw_register_divider_table(dev, "sdio", "hpll", 0, 443 hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
505 scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, 444 scu_base + ASPEED_CLK_SELECTION, 15, 0,
445 &aspeed_clk_lock);
446 if (IS_ERR(hw))
447 return PTR_ERR(hw);
448 hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
449 0, scu_base + ASPEED_CLK_SELECTION, 12, 3, 0,
506 soc_data->div_table, 450 soc_data->div_table,
507 &aspeed_clk_lock); 451 &aspeed_clk_lock);
508 if (IS_ERR(hw)) 452 if (IS_ERR(hw))
diff --git a/drivers/clk/clk-aspeed.h b/drivers/clk/clk-aspeed.h
new file mode 100644
index 000000000000..5296b15b1c88
--- /dev/null
+++ b/drivers/clk/clk-aspeed.h
@@ -0,0 +1,82 @@
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Structures used by ASPEED clock drivers
4 *
5 * Copyright 2019 IBM Corp.
6 */
7
8#include <linux/clk-provider.h>
9#include <linux/kernel.h>
10#include <linux/reset-controller.h>
11#include <linux/spinlock.h>
12
13struct clk_div_table;
14struct regmap;
15
16/**
17 * struct aspeed_gate_data - Aspeed gated clocks
18 * @clock_idx: bit used to gate this clock in the clock register
19 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
20 * reset is required when enabling the clock
21 * @name: the clock name
22 * @parent_name: the name of the parent clock
23 * @flags: standard clock framework flags
24 */
25struct aspeed_gate_data {
26 u8 clock_idx;
27 s8 reset_idx;
28 const char *name;
29 const char *parent_name;
30 unsigned long flags;
31};
32
33/**
34 * struct aspeed_clk_gate - Aspeed specific clk_gate structure
35 * @hw: handle between common and hardware-specific interfaces
36 * @reg: register controlling gate
37 * @clock_idx: bit used to gate this clock in the clock register
38 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
39 * reset is required when enabling the clock
40 * @flags: hardware-specific flags
41 * @lock: register lock
42 *
43 * Some of the clocks in the Aspeed SoC must be put in reset before enabling.
44 * This modified version of clk_gate allows an optional reset bit to be
45 * specified.
46 */
47struct aspeed_clk_gate {
48 struct clk_hw hw;
49 struct regmap *map;
50 u8 clock_idx;
51 s8 reset_idx;
52 u8 flags;
53 spinlock_t *lock;
54};
55
56#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
57
58/**
59 * struct aspeed_reset - Aspeed reset controller
60 * @map: regmap to access the containing system controller
61 * @rcdev: reset controller device
62 */
63struct aspeed_reset {
64 struct regmap *map;
65 struct reset_controller_dev rcdev;
66};
67
68#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
69
70/**
71 * struct aspeed_clk_soc_data - Aspeed SoC specific divisor information
72 * @div_table: Common divider lookup table
73 * @eclk_div_table: Divider lookup table for ECLK
74 * @mac_div_table: Divider lookup table for MAC (Ethernet) clocks
75 * @calc_pll: Callback to maculate common PLL settings
76 */
77struct aspeed_clk_soc_data {
78 const struct clk_div_table *div_table;
79 const struct clk_div_table *eclk_div_table;
80 const struct clk_div_table *mac_div_table;
81 struct clk_hw *(*calc_pll)(const char *name, u32 val);
82};
diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
new file mode 100644
index 000000000000..1c1bb39bb04e
--- /dev/null
+++ b/drivers/clk/clk-ast2600.c
@@ -0,0 +1,704 @@
1// SPDX-License-Identifier: GPL-2.0-or-later
2// Copyright IBM Corp
3// Copyright ASPEED Technology
4
5#define pr_fmt(fmt) "clk-ast2600: " fmt
6
7#include <linux/mfd/syscon.h>
8#include <linux/of_address.h>
9#include <linux/of_device.h>
10#include <linux/platform_device.h>
11#include <linux/regmap.h>
12#include <linux/slab.h>
13
14#include <dt-bindings/clock/ast2600-clock.h>
15
16#include "clk-aspeed.h"
17
18#define ASPEED_G6_NUM_CLKS 67
19
20#define ASPEED_G6_SILICON_REV 0x004
21
22#define ASPEED_G6_RESET_CTRL 0x040
23#define ASPEED_G6_RESET_CTRL2 0x050
24
25#define ASPEED_G6_CLK_STOP_CTRL 0x080
26#define ASPEED_G6_CLK_STOP_CTRL2 0x090
27
28#define ASPEED_G6_MISC_CTRL 0x0C0
29#define UART_DIV13_EN BIT(12)
30
31#define ASPEED_G6_CLK_SELECTION1 0x300
32#define ASPEED_G6_CLK_SELECTION2 0x304
33#define ASPEED_G6_CLK_SELECTION4 0x310
34
35#define ASPEED_HPLL_PARAM 0x200
36#define ASPEED_APLL_PARAM 0x210
37#define ASPEED_MPLL_PARAM 0x220
38#define ASPEED_EPLL_PARAM 0x240
39#define ASPEED_DPLL_PARAM 0x260
40
41#define ASPEED_G6_STRAP1 0x500
42
43/* Globally visible clocks */
44static DEFINE_SPINLOCK(aspeed_g6_clk_lock);
45
46/* Keeps track of all clocks */
47static struct clk_hw_onecell_data *aspeed_g6_clk_data;
48
49static void __iomem *scu_g6_base;
50
51/*
52 * Clocks marked with CLK_IS_CRITICAL:
53 *
54 * ref0 and ref1 are essential for the SoC to operate
55 * mpll is required if SDRAM is used
56 */
57static const struct aspeed_gate_data aspeed_g6_gates[] = {
58 /* clk rst name parent flags */
59 [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
60 [ASPEED_CLK_GATE_ECLK] = { 1, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */
61 [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
62 /* vclk parent - dclk/d1clk/hclk/mclk */
63 [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
64 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
65 /* From dpll */
66 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
67 [ASPEED_CLK_GATE_REF0CLK] = { 6, -1, "ref0clk-gate", "clkin", CLK_IS_CRITICAL },
68 [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
69 /* Reserved 8 */
70 [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
71 /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */
72 [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", "d1clk", 0 }, /* GFX CRT */
73 /* Reserved 11/12 */
74 [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
75 [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
76 [ASPEED_CLK_GATE_UART5CLK] = { 15, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
77 /* Reserved 16/19 */
78 [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac12", 0 }, /* MAC1 */
79 [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac12", 0 }, /* MAC2 */
80 /* Reserved 22/23 */
81 [ASPEED_CLK_GATE_RSACLK] = { 24, 4, "rsaclk-gate", NULL, 0 }, /* HAC */
82 [ASPEED_CLK_GATE_RVASCLK] = { 25, 9, "rvasclk-gate", NULL, 0 }, /* RVAS */
83 /* Reserved 26 */
84 [ASPEED_CLK_GATE_EMMCCLK] = { 27, 16, "emmcclk-gate", NULL, 0 }, /* For card clk */
85 /* Reserved 28/29/30 */
86 [ASPEED_CLK_GATE_LCLK] = { 32, 32, "lclk-gate", NULL, 0 }, /* LPC */
87 [ASPEED_CLK_GATE_ESPICLK] = { 33, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
88 [ASPEED_CLK_GATE_REF1CLK] = { 34, -1, "ref1clk-gate", "clkin", CLK_IS_CRITICAL },
89 /* Reserved 35 */
90 [ASPEED_CLK_GATE_SDCLK] = { 36, 56, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
91 [ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
92 /* Reserved 38 RSA: no longer used */
93 /* Reserved 39 */
94 [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", NULL, 0 }, /* I3C0 */
95 [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", NULL, 0 }, /* I3C1 */
96 [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", NULL, 0 }, /* I3C2 */
97 [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", NULL, 0 }, /* I3C3 */
98 [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", NULL, 0 }, /* I3C4 */
99 [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", NULL, 0 }, /* I3C5 */
100 [ASPEED_CLK_GATE_I3C6CLK] = { 46, 46, "i3c6clk-gate", NULL, 0 }, /* I3C6 */
101 [ASPEED_CLK_GATE_I3C7CLK] = { 47, 47, "i3c7clk-gate", NULL, 0 }, /* I3C7 */
102 [ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
103 [ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
104 [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
105 [ASPEED_CLK_GATE_UART4CLK] = { 51, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
106 [ASPEED_CLK_GATE_MAC3CLK] = { 52, 52, "mac3clk-gate", "mac34", 0 }, /* MAC3 */
107 [ASPEED_CLK_GATE_MAC4CLK] = { 53, 53, "mac4clk-gate", "mac34", 0 }, /* MAC4 */
108 [ASPEED_CLK_GATE_UART6CLK] = { 54, -1, "uart6clk-gate", "uartx", 0 }, /* UART6 */
109 [ASPEED_CLK_GATE_UART7CLK] = { 55, -1, "uart7clk-gate", "uartx", 0 }, /* UART7 */
110 [ASPEED_CLK_GATE_UART8CLK] = { 56, -1, "uart8clk-gate", "uartx", 0 }, /* UART8 */
111 [ASPEED_CLK_GATE_UART9CLK] = { 57, -1, "uart9clk-gate", "uartx", 0 }, /* UART9 */
112 [ASPEED_CLK_GATE_UART10CLK] = { 58, -1, "uart10clk-gate", "uartx", 0 }, /* UART10 */
113 [ASPEED_CLK_GATE_UART11CLK] = { 59, -1, "uart11clk-gate", "uartx", 0 }, /* UART11 */
114 [ASPEED_CLK_GATE_UART12CLK] = { 60, -1, "uart12clk-gate", "uartx", 0 }, /* UART12 */
115 [ASPEED_CLK_GATE_UART13CLK] = { 61, -1, "uart13clk-gate", "uartx", 0 }, /* UART13 */
116 [ASPEED_CLK_GATE_FSICLK] = { 62, 59, "fsiclk-gate", NULL, 0 }, /* FSI */
117};
118
119static const char * const eclk_parent_names[] = { "mpll", "hpll", "dpll" };
120
121static const struct clk_div_table ast2600_eclk_div_table[] = {
122 { 0x0, 2 },
123 { 0x1, 2 },
124 { 0x2, 3 },
125 { 0x3, 4 },
126 { 0x4, 5 },
127 { 0x5, 6 },
128 { 0x6, 7 },
129 { 0x7, 8 },
130 { 0 }
131};
132
133static const struct clk_div_table ast2600_mac_div_table[] = {
134 { 0x0, 4 },
135 { 0x1, 4 },
136 { 0x2, 6 },
137 { 0x3, 8 },
138 { 0x4, 10 },
139 { 0x5, 12 },
140 { 0x6, 14 },
141 { 0x7, 16 },
142 { 0 }
143};
144
145static const struct clk_div_table ast2600_div_table[] = {
146 { 0x0, 4 },
147 { 0x1, 8 },
148 { 0x2, 12 },
149 { 0x3, 16 },
150 { 0x4, 20 },
151 { 0x5, 24 },
152 { 0x6, 28 },
153 { 0x7, 32 },
154 { 0 }
155};
156
157/* For hpll/dpll/epll/mpll */
158static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
159{
160 unsigned int mult, div;
161
162 if (val & BIT(24)) {
163 /* Pass through mode */
164 mult = div = 1;
165 } else {
166 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
167 u32 m = val & 0x1fff;
168 u32 n = (val >> 13) & 0x3f;
169 u32 p = (val >> 19) & 0xf;
170 mult = (m + 1) / (n + 1);
171 div = (p + 1);
172 }
173 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
174 mult, div);
175};
176
177static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)
178{
179 unsigned int mult, div;
180
181 if (val & BIT(20)) {
182 /* Pass through mode */
183 mult = div = 1;
184 } else {
185 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
186 u32 m = (val >> 5) & 0x3f;
187 u32 od = (val >> 4) & 0x1;
188 u32 n = val & 0xf;
189
190 mult = (2 - od) * (m + 2);
191 div = n + 1;
192 }
193 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
194 mult, div);
195};
196
197static u32 get_bit(u8 idx)
198{
199 return BIT(idx % 32);
200}
201
202static u32 get_reset_reg(struct aspeed_clk_gate *gate)
203{
204 if (gate->reset_idx < 32)
205 return ASPEED_G6_RESET_CTRL;
206
207 return ASPEED_G6_RESET_CTRL2;
208}
209
210static u32 get_clock_reg(struct aspeed_clk_gate *gate)
211{
212 if (gate->clock_idx < 32)
213 return ASPEED_G6_CLK_STOP_CTRL;
214
215 return ASPEED_G6_CLK_STOP_CTRL2;
216}
217
218static int aspeed_g6_clk_is_enabled(struct clk_hw *hw)
219{
220 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
221 u32 clk = get_bit(gate->clock_idx);
222 u32 rst = get_bit(gate->reset_idx);
223 u32 reg;
224 u32 enval;
225
226 /*
227 * If the IP is in reset, treat the clock as not enabled,
228 * this happens with some clocks such as the USB one when
229 * coming from cold reset. Without this, aspeed_clk_enable()
230 * will fail to lift the reset.
231 */
232 if (gate->reset_idx >= 0) {
233 regmap_read(gate->map, get_reset_reg(gate), &reg);
234
235 if (reg & rst)
236 return 0;
237 }
238
239 regmap_read(gate->map, get_clock_reg(gate), &reg);
240
241 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
242
243 return ((reg & clk) == enval) ? 1 : 0;
244}
245
246static int aspeed_g6_clk_enable(struct clk_hw *hw)
247{
248 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
249 unsigned long flags;
250 u32 clk = get_bit(gate->clock_idx);
251 u32 rst = get_bit(gate->reset_idx);
252
253 spin_lock_irqsave(gate->lock, flags);
254
255 if (aspeed_g6_clk_is_enabled(hw)) {
256 spin_unlock_irqrestore(gate->lock, flags);
257 return 0;
258 }
259
260 if (gate->reset_idx >= 0) {
261 /* Put IP in reset */
262 regmap_write(gate->map, get_reset_reg(gate), rst);
263 /* Delay 100us */
264 udelay(100);
265 }
266
267 /* Enable clock */
268 if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
269 regmap_write(gate->map, get_clock_reg(gate), clk);
270 } else {
271 /* Use set to clear register */
272 regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk);
273 }
274
275 if (gate->reset_idx >= 0) {
276 /* A delay of 10ms is specified by the ASPEED docs */
277 mdelay(10);
278 /* Take IP out of reset */
279 regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst);
280 }
281
282 spin_unlock_irqrestore(gate->lock, flags);
283
284 return 0;
285}
286
287static void aspeed_g6_clk_disable(struct clk_hw *hw)
288{
289 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
290 unsigned long flags;
291 u32 clk = get_bit(gate->clock_idx);
292
293 spin_lock_irqsave(gate->lock, flags);
294
295 if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
296 regmap_write(gate->map, get_clock_reg(gate), clk);
297 } else {
298 /* Use set to clear register */
299 regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk);
300 }
301
302 spin_unlock_irqrestore(gate->lock, flags);
303}
304
305static const struct clk_ops aspeed_g6_clk_gate_ops = {
306 .enable = aspeed_g6_clk_enable,
307 .disable = aspeed_g6_clk_disable,
308 .is_enabled = aspeed_g6_clk_is_enabled,
309};
310
311static int aspeed_g6_reset_deassert(struct reset_controller_dev *rcdev,
312 unsigned long id)
313{
314 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
315 u32 rst = get_bit(id);
316 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
317
318 /* Use set to clear register */
319 return regmap_write(ar->map, reg + 0x04, rst);
320}
321
322static int aspeed_g6_reset_assert(struct reset_controller_dev *rcdev,
323 unsigned long id)
324{
325 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
326 u32 rst = get_bit(id);
327 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
328
329 return regmap_write(ar->map, reg, rst);
330}
331
332static int aspeed_g6_reset_status(struct reset_controller_dev *rcdev,
333 unsigned long id)
334{
335 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
336 int ret;
337 u32 val;
338 u32 rst = get_bit(id);
339 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
340
341 ret = regmap_read(ar->map, reg, &val);
342 if (ret)
343 return ret;
344
345 return !!(val & rst);
346}
347
348static const struct reset_control_ops aspeed_g6_reset_ops = {
349 .assert = aspeed_g6_reset_assert,
350 .deassert = aspeed_g6_reset_deassert,
351 .status = aspeed_g6_reset_status,
352};
353
354static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev,
355 const char *name, const char *parent_name, unsigned long flags,
356 struct regmap *map, u8 clock_idx, u8 reset_idx,
357 u8 clk_gate_flags, spinlock_t *lock)
358{
359 struct aspeed_clk_gate *gate;
360 struct clk_init_data init;
361 struct clk_hw *hw;
362 int ret;
363
364 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
365 if (!gate)
366 return ERR_PTR(-ENOMEM);
367
368 init.name = name;
369 init.ops = &aspeed_g6_clk_gate_ops;
370 init.flags = flags;
371 init.parent_names = parent_name ? &parent_name : NULL;
372 init.num_parents = parent_name ? 1 : 0;
373
374 gate->map = map;
375 gate->clock_idx = clock_idx;
376 gate->reset_idx = reset_idx;
377 gate->flags = clk_gate_flags;
378 gate->lock = lock;
379 gate->hw.init = &init;
380
381 hw = &gate->hw;
382 ret = clk_hw_register(dev, hw);
383 if (ret) {
384 kfree(gate);
385 hw = ERR_PTR(ret);
386 }
387
388 return hw;
389}
390
391static const char * const vclk_parent_names[] = {
392 "dpll",
393 "d1pll",
394 "hclk",
395 "mclk",
396};
397
398static const char * const d1clk_parent_names[] = {
399 "dpll",
400 "epll",
401 "usb-phy-40m",
402 "gpioc6_clkin",
403 "dp_phy_pll",
404};
405
406static int aspeed_g6_clk_probe(struct platform_device *pdev)
407{
408 struct device *dev = &pdev->dev;
409 struct aspeed_reset *ar;
410 struct regmap *map;
411 struct clk_hw *hw;
412 u32 val, rate;
413 int i, ret;
414
415 map = syscon_node_to_regmap(dev->of_node);
416 if (IS_ERR(map)) {
417 dev_err(dev, "no syscon regmap\n");
418 return PTR_ERR(map);
419 }
420
421 ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
422 if (!ar)
423 return -ENOMEM;
424
425 ar->map = map;
426
427 ar->rcdev.owner = THIS_MODULE;
428 ar->rcdev.nr_resets = 64;
429 ar->rcdev.ops = &aspeed_g6_reset_ops;
430 ar->rcdev.of_node = dev->of_node;
431
432 ret = devm_reset_controller_register(dev, &ar->rcdev);
433 if (ret) {
434 dev_err(dev, "could not register reset controller\n");
435 return ret;
436 }
437
438 /* UART clock div13 setting */
439 regmap_read(map, ASPEED_G6_MISC_CTRL, &val);
440 if (val & UART_DIV13_EN)
441 rate = 24000000 / 13;
442 else
443 rate = 24000000;
444 hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
445 if (IS_ERR(hw))
446 return PTR_ERR(hw);
447 aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw;
448
449 /* UART6~13 clock div13 setting */
450 regmap_read(map, 0x80, &val);
451 if (val & BIT(31))
452 rate = 24000000 / 13;
453 else
454 rate = 24000000;
455 hw = clk_hw_register_fixed_rate(dev, "uartx", NULL, 0, rate);
456 if (IS_ERR(hw))
457 return PTR_ERR(hw);
458 aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw;
459
460 /* EMMC ext clock divider */
461 hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "hpll", 0,
462 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 15, 0,
463 &aspeed_g6_clk_lock);
464 if (IS_ERR(hw))
465 return PTR_ERR(hw);
466 hw = clk_hw_register_divider_table(dev, "emmc_extclk", "emmc_extclk_gate", 0,
467 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 12, 3, 0,
468 ast2600_div_table,
469 &aspeed_g6_clk_lock);
470 if (IS_ERR(hw))
471 return PTR_ERR(hw);
472 aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw;
473
474 /* SD/SDIO clock divider and gate */
475 hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
476 scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0,
477 &aspeed_g6_clk_lock);
478 if (IS_ERR(hw))
479 return PTR_ERR(hw);
480 hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
481 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0,
482 ast2600_div_table,
483 &aspeed_g6_clk_lock);
484 if (IS_ERR(hw))
485 return PTR_ERR(hw);
486 aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw;
487
488 /* MAC1/2 AHB bus clock divider */
489 hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0,
490 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0,
491 ast2600_mac_div_table,
492 &aspeed_g6_clk_lock);
493 if (IS_ERR(hw))
494 return PTR_ERR(hw);
495 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw;
496
497 /* MAC3/4 AHB bus clock divider */
498 hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0,
499 scu_g6_base + 0x310, 24, 3, 0,
500 ast2600_mac_div_table,
501 &aspeed_g6_clk_lock);
502 if (IS_ERR(hw))
503 return PTR_ERR(hw);
504 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw;
505
506 /* LPC Host (LHCLK) clock divider */
507 hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
508 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
509 ast2600_div_table,
510 &aspeed_g6_clk_lock);
511 if (IS_ERR(hw))
512 return PTR_ERR(hw);
513 aspeed_g6_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
514
515 /* gfx d1clk : use dp clk */
516 regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10));
517 /* SoC Display clock selection */
518 hw = clk_hw_register_mux(dev, "d1clk", d1clk_parent_names,
519 ARRAY_SIZE(d1clk_parent_names), 0,
520 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 8, 3, 0,
521 &aspeed_g6_clk_lock);
522 if (IS_ERR(hw))
523 return PTR_ERR(hw);
524 aspeed_g6_clk_data->hws[ASPEED_CLK_D1CLK] = hw;
525
526 /* d1 clk div 0x308[17:15] x [14:12] - 8,7,6,5,4,3,2,1 */
527 regmap_write(map, 0x308, 0x12000); /* 3x3 = 9 */
528
529 /* P-Bus (BCLK) clock divider */
530 hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
531 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
532 ast2600_div_table,
533 &aspeed_g6_clk_lock);
534 if (IS_ERR(hw))
535 return PTR_ERR(hw);
536 aspeed_g6_clk_data->hws[ASPEED_CLK_BCLK] = hw;
537
538 /* Video Capture clock selection */
539 hw = clk_hw_register_mux(dev, "vclk", vclk_parent_names,
540 ARRAY_SIZE(vclk_parent_names), 0,
541 scu_g6_base + ASPEED_G6_CLK_SELECTION2, 12, 3, 0,
542 &aspeed_g6_clk_lock);
543 if (IS_ERR(hw))
544 return PTR_ERR(hw);
545 aspeed_g6_clk_data->hws[ASPEED_CLK_VCLK] = hw;
546
547 /* Video Engine clock divider */
548 hw = clk_hw_register_divider_table(dev, "eclk", NULL, 0,
549 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 28, 3, 0,
550 ast2600_eclk_div_table,
551 &aspeed_g6_clk_lock);
552 if (IS_ERR(hw))
553 return PTR_ERR(hw);
554 aspeed_g6_clk_data->hws[ASPEED_CLK_ECLK] = hw;
555
556 for (i = 0; i < ARRAY_SIZE(aspeed_g6_gates); i++) {
557 const struct aspeed_gate_data *gd = &aspeed_g6_gates[i];
558 u32 gate_flags;
559
560 /*
561 * Special case: the USB port 1 clock (bit 14) is always
562 * working the opposite way from the other ones.
563 */
564 gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
565 hw = aspeed_g6_clk_hw_register_gate(dev,
566 gd->name,
567 gd->parent_name,
568 gd->flags,
569 map,
570 gd->clock_idx,
571 gd->reset_idx,
572 gate_flags,
573 &aspeed_g6_clk_lock);
574 if (IS_ERR(hw))
575 return PTR_ERR(hw);
576 aspeed_g6_clk_data->hws[i] = hw;
577 }
578
579 return 0;
580};
581
582static const struct of_device_id aspeed_g6_clk_dt_ids[] = {
583 { .compatible = "aspeed,ast2600-scu" },
584 { }
585};
586
587static struct platform_driver aspeed_g6_clk_driver = {
588 .probe = aspeed_g6_clk_probe,
589 .driver = {
590 .name = "ast2600-clk",
591 .of_match_table = aspeed_g6_clk_dt_ids,
592 .suppress_bind_attrs = true,
593 },
594};
595builtin_platform_driver(aspeed_g6_clk_driver);
596
597static const u32 ast2600_a0_axi_ahb_div_table[] = {
598 2, 2, 3, 5,
599};
600
601static const u32 ast2600_a1_axi_ahb_div_table[] = {
602 4, 6, 2, 4,
603};
604
605static void __init aspeed_g6_cc(struct regmap *map)
606{
607 struct clk_hw *hw;
608 u32 val, div, chip_id, axi_div, ahb_div;
609
610 clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
611
612 /*
613 * High-speed PLL clock derived from the crystal. This the CPU clock,
614 * and we assume that it is enabled
615 */
616 regmap_read(map, ASPEED_HPLL_PARAM, &val);
617 aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val);
618
619 regmap_read(map, ASPEED_MPLL_PARAM, &val);
620 aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val);
621
622 regmap_read(map, ASPEED_DPLL_PARAM, &val);
623 aspeed_g6_clk_data->hws[ASPEED_CLK_DPLL] = ast2600_calc_pll("dpll", val);
624
625 regmap_read(map, ASPEED_EPLL_PARAM, &val);
626 aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val);
627
628 regmap_read(map, ASPEED_APLL_PARAM, &val);
629 aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val);
630
631 /* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/
632 regmap_read(map, ASPEED_G6_STRAP1, &val);
633 if (val & BIT(16))
634 axi_div = 1;
635 else
636 axi_div = 2;
637
638 regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);
639 if (chip_id & BIT(16))
640 ahb_div = ast2600_a1_axi_ahb_div_table[(val >> 11) & 0x3];
641 else
642 ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3];
643
644 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div);
645 aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw;
646
647 regmap_read(map, ASPEED_G6_CLK_SELECTION1, &val);
648 val = (val >> 23) & 0x7;
649 div = 4 * (val + 1);
650 hw = clk_hw_register_fixed_factor(NULL, "apb1", "hpll", 0, 1, div);
651 aspeed_g6_clk_data->hws[ASPEED_CLK_APB1] = hw;
652
653 regmap_read(map, ASPEED_G6_CLK_SELECTION4, &val);
654 val = (val >> 9) & 0x7;
655 div = 2 * (val + 1);
656 hw = clk_hw_register_fixed_factor(NULL, "apb2", "ahb", 0, 1, div);
657 aspeed_g6_clk_data->hws[ASPEED_CLK_APB2] = hw;
658
659 /* USB 2.0 port1 phy 40MHz clock */
660 hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000);
661 aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw;
662};
663
664static void __init aspeed_g6_cc_init(struct device_node *np)
665{
666 struct regmap *map;
667 int ret;
668 int i;
669
670 scu_g6_base = of_iomap(np, 0);
671 if (!scu_g6_base)
672 return;
673
674 aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws,
675 ASPEED_G6_NUM_CLKS), GFP_KERNEL);
676 if (!aspeed_g6_clk_data)
677 return;
678
679 /*
680 * This way all clocks fetched before the platform device probes,
681 * except those we assign here for early use, will be deferred.
682 */
683 for (i = 0; i < ASPEED_G6_NUM_CLKS; i++)
684 aspeed_g6_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
685
686 /*
687 * We check that the regmap works on this very first access,
688 * but as this is an MMIO-backed regmap, subsequent regmap
689 * access is not going to fail and we skip error checks from
690 * this point.
691 */
692 map = syscon_node_to_regmap(np);
693 if (IS_ERR(map)) {
694 pr_err("no syscon regmap\n");
695 return;
696 }
697
698 aspeed_g6_cc(map);
699 aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
700 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);
701 if (ret)
702 pr_err("failed to add DT provider: %d\n", ret);
703};
704CLK_OF_DECLARE_DRIVER(aspeed_cc_g6, "aspeed,ast2600-scu", aspeed_g6_cc_init);
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index b06038b8f658..4f13a681ddfc 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -3,7 +3,6 @@
3 * Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved. 3 * Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved.
4 */ 4 */
5 5
6#include <linux/clk.h>
7#include <linux/clk-provider.h> 6#include <linux/clk-provider.h>
8#include <linux/err.h> 7#include <linux/err.h>
9#include <linux/slab.h> 8#include <linux/slab.h>
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 07f3b252f3e0..bed140f7375f 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -686,7 +686,7 @@ static const struct clockgen_chipinfo chipinfo[] = {
686 .guts_compat = "fsl,qoriq-device-config-1.0", 686 .guts_compat = "fsl,qoriq-device-config-1.0",
687 .init_periph = p5020_init_periph, 687 .init_periph = p5020_init_periph,
688 .cmux_groups = { 688 .cmux_groups = {
689 &p2041_cmux_grp1, &p2041_cmux_grp2 689 &p5020_cmux_grp1, &p5020_cmux_grp2
690 }, 690 },
691 .cmux_to_group = { 691 .cmux_to_group = {
692 0, 1, -1 692 0, 1, -1
diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c
index 72424eb7e5f8..6e780c2a9e6b 100644
--- a/drivers/clk/clk-si5341.c
+++ b/drivers/clk/clk-si5341.c
@@ -547,7 +547,6 @@ static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
547 bool is_integer; 547 bool is_integer;
548 548
549 n_num = synth->data->freq_vco; 549 n_num = synth->data->freq_vco;
550 n_den = rate;
551 550
552 /* see if there's an integer solution */ 551 /* see if there's an integer solution */
553 r = do_div(n_num, rate); 552 r = do_div(n_num, rate);
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index c11b1781d24a..1b291a6e169b 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -593,6 +593,8 @@ static void clk_core_get_boundaries(struct clk_core *core,
593{ 593{
594 struct clk *clk_user; 594 struct clk *clk_user;
595 595
596 lockdep_assert_held(&prepare_lock);
597
596 *min_rate = core->min_rate; 598 *min_rate = core->min_rate;
597 *max_rate = core->max_rate; 599 *max_rate = core->max_rate;
598 600
@@ -2853,9 +2855,6 @@ static struct hlist_head *orphan_list[] = {
2853static void clk_summary_show_one(struct seq_file *s, struct clk_core *c, 2855static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
2854 int level) 2856 int level)
2855{ 2857{
2856 if (!c)
2857 return;
2858
2859 seq_printf(s, "%*s%-*s %7d %8d %8d %11lu %10lu %5d %6d\n", 2858 seq_printf(s, "%*s%-*s %7d %8d %8d %11lu %10lu %5d %6d\n",
2860 level * 3 + 1, "", 2859 level * 3 + 1, "",
2861 30 - level * 3, c->name, 2860 30 - level * 3, c->name,
@@ -2870,9 +2869,6 @@ static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
2870{ 2869{
2871 struct clk_core *child; 2870 struct clk_core *child;
2872 2871
2873 if (!c)
2874 return;
2875
2876 clk_summary_show_one(s, c, level); 2872 clk_summary_show_one(s, c, level);
2877 2873
2878 hlist_for_each_entry(child, &c->children, child_node) 2874 hlist_for_each_entry(child, &c->children, child_node)
@@ -2902,8 +2898,9 @@ DEFINE_SHOW_ATTRIBUTE(clk_summary);
2902 2898
2903static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level) 2899static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
2904{ 2900{
2905 if (!c) 2901 unsigned long min_rate, max_rate;
2906 return; 2902
2903 clk_core_get_boundaries(c, &min_rate, &max_rate);
2907 2904
2908 /* This should be JSON format, i.e. elements separated with a comma */ 2905 /* This should be JSON format, i.e. elements separated with a comma */
2909 seq_printf(s, "\"%s\": { ", c->name); 2906 seq_printf(s, "\"%s\": { ", c->name);
@@ -2911,6 +2908,8 @@ static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
2911 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count); 2908 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
2912 seq_printf(s, "\"protect_count\": %d,", c->protect_count); 2909 seq_printf(s, "\"protect_count\": %d,", c->protect_count);
2913 seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c)); 2910 seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c));
2911 seq_printf(s, "\"min_rate\": %lu,", min_rate);
2912 seq_printf(s, "\"max_rate\": %lu,", max_rate);
2914 seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c)); 2913 seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c));
2915 seq_printf(s, "\"phase\": %d,", clk_core_get_phase(c)); 2914 seq_printf(s, "\"phase\": %d,", clk_core_get_phase(c));
2916 seq_printf(s, "\"duty_cycle\": %u", 2915 seq_printf(s, "\"duty_cycle\": %u",
@@ -2921,9 +2920,6 @@ static void clk_dump_subtree(struct seq_file *s, struct clk_core *c, int level)
2921{ 2920{
2922 struct clk_core *child; 2921 struct clk_core *child;
2923 2922
2924 if (!c)
2925 return;
2926
2927 clk_dump_one(s, c, level); 2923 clk_dump_one(s, c, level);
2928 2924
2929 hlist_for_each_entry(child, &c->children, child_node) { 2925 hlist_for_each_entry(child, &c->children, child_node) {
@@ -3019,15 +3015,15 @@ static void possible_parent_show(struct seq_file *s, struct clk_core *core,
3019 */ 3015 */
3020 parent = clk_core_get_parent_by_index(core, i); 3016 parent = clk_core_get_parent_by_index(core, i);
3021 if (parent) 3017 if (parent)
3022 seq_printf(s, "%s", parent->name); 3018 seq_puts(s, parent->name);
3023 else if (core->parents[i].name) 3019 else if (core->parents[i].name)
3024 seq_printf(s, "%s", core->parents[i].name); 3020 seq_puts(s, core->parents[i].name);
3025 else if (core->parents[i].fw_name) 3021 else if (core->parents[i].fw_name)
3026 seq_printf(s, "<%s>(fw)", core->parents[i].fw_name); 3022 seq_printf(s, "<%s>(fw)", core->parents[i].fw_name);
3027 else if (core->parents[i].index >= 0) 3023 else if (core->parents[i].index >= 0)
3028 seq_printf(s, "%s", 3024 seq_puts(s,
3029 of_clk_get_parent_name(core->of_node, 3025 of_clk_get_parent_name(core->of_node,
3030 core->parents[i].index)); 3026 core->parents[i].index));
3031 else 3027 else
3032 seq_puts(s, "(missing)"); 3028 seq_puts(s, "(missing)");
3033 3029
@@ -3070,6 +3066,34 @@ static int clk_duty_cycle_show(struct seq_file *s, void *data)
3070} 3066}
3071DEFINE_SHOW_ATTRIBUTE(clk_duty_cycle); 3067DEFINE_SHOW_ATTRIBUTE(clk_duty_cycle);
3072 3068
3069static int clk_min_rate_show(struct seq_file *s, void *data)
3070{
3071 struct clk_core *core = s->private;
3072 unsigned long min_rate, max_rate;
3073
3074 clk_prepare_lock();
3075 clk_core_get_boundaries(core, &min_rate, &max_rate);
3076 clk_prepare_unlock();
3077 seq_printf(s, "%lu\n", min_rate);
3078
3079 return 0;
3080}
3081DEFINE_SHOW_ATTRIBUTE(clk_min_rate);
3082
3083static int clk_max_rate_show(struct seq_file *s, void *data)
3084{
3085 struct clk_core *core = s->private;
3086 unsigned long min_rate, max_rate;
3087
3088 clk_prepare_lock();
3089 clk_core_get_boundaries(core, &min_rate, &max_rate);
3090 clk_prepare_unlock();
3091 seq_printf(s, "%lu\n", max_rate);
3092
3093 return 0;
3094}
3095DEFINE_SHOW_ATTRIBUTE(clk_max_rate);
3096
3073static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry) 3097static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
3074{ 3098{
3075 struct dentry *root; 3099 struct dentry *root;
@@ -3081,6 +3105,8 @@ static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
3081 core->dentry = root; 3105 core->dentry = root;
3082 3106
3083 debugfs_create_ulong("clk_rate", 0444, root, &core->rate); 3107 debugfs_create_ulong("clk_rate", 0444, root, &core->rate);
3108 debugfs_create_file("clk_min_rate", 0444, root, core, &clk_min_rate_fops);
3109 debugfs_create_file("clk_max_rate", 0444, root, core, &clk_max_rate_fops);
3084 debugfs_create_ulong("clk_accuracy", 0444, root, &core->accuracy); 3110 debugfs_create_ulong("clk_accuracy", 0444, root, &core->accuracy);
3085 debugfs_create_u32("clk_phase", 0444, root, &core->phase); 3111 debugfs_create_u32("clk_phase", 0444, root, &core->phase);
3086 debugfs_create_file("clk_flags", 0444, root, core, &clk_flags_fops); 3112 debugfs_create_file("clk_flags", 0444, root, core, &clk_flags_fops);
diff --git a/drivers/clk/davinci/pll.c b/drivers/clk/davinci/pll.c
index 1c99e992d638..1ac11b6a47a3 100644
--- a/drivers/clk/davinci/pll.c
+++ b/drivers/clk/davinci/pll.c
@@ -778,12 +778,15 @@ int of_davinci_pll_init(struct device *dev, struct device_node *node,
778 int i; 778 int i;
779 779
780 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); 780 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
781 if (!clk_data) 781 if (!clk_data) {
782 of_node_put(child);
782 return -ENOMEM; 783 return -ENOMEM;
784 }
783 785
784 clks = kmalloc_array(n_clks, sizeof(*clks), GFP_KERNEL); 786 clks = kmalloc_array(n_clks, sizeof(*clks), GFP_KERNEL);
785 if (!clks) { 787 if (!clks) {
786 kfree(clk_data); 788 kfree(clk_data);
789 of_node_put(child);
787 return -ENOMEM; 790 return -ENOMEM;
788 } 791 }
789 792
diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c
index 2642d36d1e2c..a3b4635f6278 100644
--- a/drivers/clk/ingenic/jz4725b-cgu.c
+++ b/drivers/clk/ingenic/jz4725b-cgu.c
@@ -257,4 +257,4 @@ static void __init jz4725b_cgu_init(struct device_node *np)
257 257
258 ingenic_cgu_register_syscore_ops(cgu); 258 ingenic_cgu_register_syscore_ops(cgu);
259} 259}
260CLK_OF_DECLARE(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init); 260CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init);
diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index 4c0a20949c2c..978f32dd424a 100644
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -53,6 +53,10 @@ static const u8 jz4740_cgu_cpccr_div_table[] = {
53 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 53 1, 2, 3, 4, 6, 8, 12, 16, 24, 32,
54}; 54};
55 55
56static const u8 jz4740_cgu_pll_half_div_table[] = {
57 2, 1,
58};
59
56static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { 60static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
57 61
58 /* External clocks */ 62 /* External clocks */
@@ -86,7 +90,10 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
86 [JZ4740_CLK_PLL_HALF] = { 90 [JZ4740_CLK_PLL_HALF] = {
87 "pll half", CGU_CLK_DIV, 91 "pll half", CGU_CLK_DIV,
88 .parents = { JZ4740_CLK_PLL, -1, -1, -1 }, 92 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
89 .div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1 }, 93 .div = {
94 CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
95 jz4740_cgu_pll_half_div_table,
96 },
90 }, 97 },
91 98
92 [JZ4740_CLK_CCLK] = { 99 [JZ4740_CLK_CCLK] = {
@@ -241,4 +248,4 @@ static void __init jz4740_cgu_init(struct device_node *np)
241 248
242 ingenic_cgu_register_syscore_ops(cgu); 249 ingenic_cgu_register_syscore_ops(cgu);
243} 250}
244CLK_OF_DECLARE(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init); 251CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);
diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c
index eebc1bea3841..956dd653a43d 100644
--- a/drivers/clk/ingenic/jz4770-cgu.c
+++ b/drivers/clk/ingenic/jz4770-cgu.c
@@ -443,4 +443,4 @@ static void __init jz4770_cgu_init(struct device_node *np)
443} 443}
444 444
445/* We only probe via devicetree, no need for a platform driver */ 445/* We only probe via devicetree, no need for a platform driver */
446CLK_OF_DECLARE(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init); 446CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init);
diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c
index 8c67f89df25e..ea905ff72bf0 100644
--- a/drivers/clk/ingenic/jz4780-cgu.c
+++ b/drivers/clk/ingenic/jz4780-cgu.c
@@ -725,4 +725,4 @@ static void __init jz4780_cgu_init(struct device_node *np)
725 725
726 ingenic_cgu_register_syscore_ops(cgu); 726 ingenic_cgu_register_syscore_ops(cgu);
727} 727}
728CLK_OF_DECLARE(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init); 728CLK_OF_DECLARE_DRIVER(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init);
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index ce3d9b300bab..7efc3617bbd5 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -117,6 +117,62 @@ config COMMON_CLK_MT2712_VENCSYS
117 ---help--- 117 ---help---
118 This driver supports MediaTek MT2712 vencsys clocks. 118 This driver supports MediaTek MT2712 vencsys clocks.
119 119
120config COMMON_CLK_MT6779
121 bool "Clock driver for MediaTek MT6779"
122 depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
123 select COMMON_CLK_MEDIATEK
124 default ARCH_MEDIATEK && ARM64
125 help
126 This driver supports MediaTek MT6779 basic clocks.
127
128config COMMON_CLK_MT6779_MMSYS
129 bool "Clock driver for MediaTek MT6779 mmsys"
130 depends on COMMON_CLK_MT6779
131 help
132 This driver supports MediaTek MT6779 mmsys clocks.
133
134config COMMON_CLK_MT6779_IMGSYS
135 bool "Clock driver for MediaTek MT6779 imgsys"
136 depends on COMMON_CLK_MT6779
137 help
138 This driver supports MediaTek MT6779 imgsys clocks.
139
140config COMMON_CLK_MT6779_IPESYS
141 bool "Clock driver for MediaTek MT6779 ipesys"
142 depends on COMMON_CLK_MT6779
143 help
144 This driver supports MediaTek MT6779 ipesys clocks.
145
146config COMMON_CLK_MT6779_CAMSYS
147 bool "Clock driver for MediaTek MT6779 camsys"
148 depends on COMMON_CLK_MT6779
149 help
150 This driver supports MediaTek MT6779 camsys clocks.
151
152config COMMON_CLK_MT6779_VDECSYS
153 bool "Clock driver for MediaTek MT6779 vdecsys"
154 depends on COMMON_CLK_MT6779
155 help
156 This driver supports MediaTek MT6779 vdecsys clocks.
157
158config COMMON_CLK_MT6779_VENCSYS
159 bool "Clock driver for MediaTek MT6779 vencsys"
160 depends on COMMON_CLK_MT6779
161 help
162 This driver supports MediaTek MT6779 vencsys clocks.
163
164config COMMON_CLK_MT6779_MFGCFG
165 bool "Clock driver for MediaTek MT6779 mfgcfg"
166 depends on COMMON_CLK_MT6779
167 help
168 This driver supports MediaTek MT6779 mfgcfg clocks.
169
170config COMMON_CLK_MT6779_AUDSYS
171 bool "Clock driver for Mediatek MT6779 audsys"
172 depends on COMMON_CLK_MT6779
173 help
174 This driver supports Mediatek MT6779 audsys clocks.
175
120config COMMON_CLK_MT6797 176config COMMON_CLK_MT6797
121 bool "Clock driver for MediaTek MT6797" 177 bool "Clock driver for MediaTek MT6797"
122 depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST 178 depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 672de0099eef..8cdb76a5cd71 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -1,6 +1,15 @@
1# SPDX-License-Identifier: GPL-2.0 1# SPDX-License-Identifier: GPL-2.0
2obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o 2obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
3 3
4obj-$(CONFIG_COMMON_CLK_MT6779) += clk-mt6779.o
5obj-$(CONFIG_COMMON_CLK_MT6779_MMSYS) += clk-mt6779-mm.o
6obj-$(CONFIG_COMMON_CLK_MT6779_IMGSYS) += clk-mt6779-img.o
7obj-$(CONFIG_COMMON_CLK_MT6779_IPESYS) += clk-mt6779-ipe.o
8obj-$(CONFIG_COMMON_CLK_MT6779_CAMSYS) += clk-mt6779-cam.o
9obj-$(CONFIG_COMMON_CLK_MT6779_VDECSYS) += clk-mt6779-vdec.o
10obj-$(CONFIG_COMMON_CLK_MT6779_VENCSYS) += clk-mt6779-venc.o
11obj-$(CONFIG_COMMON_CLK_MT6779_MFGCFG) += clk-mt6779-mfg.o
12obj-$(CONFIG_COMMON_CLK_MT6779_AUDSYS) += clk-mt6779-aud.o
4obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o 13obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o
5obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o 14obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o
6obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o 15obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index 803bf0ae1fd6..a35cf0b22150 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -150,7 +150,8 @@ struct clk *mtk_clk_register_gate(
150 int sta_ofs, 150 int sta_ofs,
151 u8 bit, 151 u8 bit,
152 const struct clk_ops *ops, 152 const struct clk_ops *ops,
153 unsigned long flags) 153 unsigned long flags,
154 struct device *dev)
154{ 155{
155 struct mtk_clk_gate *cg; 156 struct mtk_clk_gate *cg;
156 struct clk *clk; 157 struct clk *clk;
@@ -174,7 +175,7 @@ struct clk *mtk_clk_register_gate(
174 175
175 cg->hw.init = &init; 176 cg->hw.init = &init;
176 177
177 clk = clk_register(NULL, &cg->hw); 178 clk = clk_register(dev, &cg->hw);
178 if (IS_ERR(clk)) 179 if (IS_ERR(clk))
179 kfree(cg); 180 kfree(cg);
180 181
diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
index e05c73697485..3c3329ec54b7 100644
--- a/drivers/clk/mediatek/clk-gate.h
+++ b/drivers/clk/mediatek/clk-gate.h
@@ -40,7 +40,8 @@ struct clk *mtk_clk_register_gate(
40 int sta_ofs, 40 int sta_ofs,
41 u8 bit, 41 u8 bit,
42 const struct clk_ops *ops, 42 const struct clk_ops *ops,
43 unsigned long flags); 43 unsigned long flags,
44 struct device *dev);
44 45
45#define GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, \ 46#define GATE_MTK_FLAGS(_id, _name, _parent, _regs, _shift, \
46 _ops, _flags) { \ 47 _ops, _flags) { \
diff --git a/drivers/clk/mediatek/clk-mt6779-aud.c b/drivers/clk/mediatek/clk-mt6779-aud.c
new file mode 100644
index 000000000000..11b209f95e25
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-aud.c
@@ -0,0 +1,117 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/of.h>
9#include <linux/of_address.h>
10#include <linux/of_device.h>
11#include <linux/platform_device.h>
12
13#include "clk-mtk.h"
14#include "clk-gate.h"
15
16#include <dt-bindings/clock/mt6779-clk.h>
17
18static const struct mtk_gate_regs audio0_cg_regs = {
19 .set_ofs = 0x0,
20 .clr_ofs = 0x0,
21 .sta_ofs = 0x0,
22};
23
24static const struct mtk_gate_regs audio1_cg_regs = {
25 .set_ofs = 0x4,
26 .clr_ofs = 0x4,
27 .sta_ofs = 0x4,
28};
29
30#define GATE_AUDIO0(_id, _name, _parent, _shift) \
31 GATE_MTK(_id, _name, _parent, &audio0_cg_regs, _shift, \
32 &mtk_clk_gate_ops_no_setclr)
33#define GATE_AUDIO1(_id, _name, _parent, _shift) \
34 GATE_MTK(_id, _name, _parent, &audio1_cg_regs, _shift, \
35 &mtk_clk_gate_ops_no_setclr)
36
37static const struct mtk_gate audio_clks[] = {
38 /* AUDIO0 */
39 GATE_AUDIO0(CLK_AUD_AFE, "aud_afe", "audio_sel", 2),
40 GATE_AUDIO0(CLK_AUD_22M, "aud_22m", "aud_eng1_sel", 8),
41 GATE_AUDIO0(CLK_AUD_24M, "aud_24m", "aud_eng2_sel", 9),
42 GATE_AUDIO0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner",
43 "aud_eng2_sel", 18),
44 GATE_AUDIO0(CLK_AUD_APLL_TUNER, "aud_apll_tuner",
45 "aud_eng1_sel", 19),
46 GATE_AUDIO0(CLK_AUD_TDM, "aud_tdm", "aud_eng1_sel", 20),
47 GATE_AUDIO0(CLK_AUD_ADC, "aud_adc", "audio_sel", 24),
48 GATE_AUDIO0(CLK_AUD_DAC, "aud_dac", "audio_sel", 25),
49 GATE_AUDIO0(CLK_AUD_DAC_PREDIS, "aud_dac_predis",
50 "audio_sel", 26),
51 GATE_AUDIO0(CLK_AUD_TML, "aud_tml", "audio_sel", 27),
52 GATE_AUDIO0(CLK_AUD_NLE, "aud_nle", "audio_sel", 28),
53 /* AUDIO1 */
54 GATE_AUDIO1(CLK_AUD_I2S1_BCLK_SW, "aud_i2s1_bclk",
55 "audio_sel", 4),
56 GATE_AUDIO1(CLK_AUD_I2S2_BCLK_SW, "aud_i2s2_bclk",
57 "audio_sel", 5),
58 GATE_AUDIO1(CLK_AUD_I2S3_BCLK_SW, "aud_i2s3_bclk",
59 "audio_sel", 6),
60 GATE_AUDIO1(CLK_AUD_I2S4_BCLK_SW, "aud_i2s4_bclk",
61 "audio_sel", 7),
62 GATE_AUDIO1(CLK_AUD_I2S5_BCLK_SW, "aud_i2s5_bclk",
63 "audio_sel", 8),
64 GATE_AUDIO1(CLK_AUD_CONN_I2S_ASRC, "aud_conn_i2s",
65 "audio_sel", 12),
66 GATE_AUDIO1(CLK_AUD_GENERAL1_ASRC, "aud_general1",
67 "audio_sel", 13),
68 GATE_AUDIO1(CLK_AUD_GENERAL2_ASRC, "aud_general2",
69 "audio_sel", 14),
70 GATE_AUDIO1(CLK_AUD_DAC_HIRES, "aud_dac_hires",
71 "audio_h_sel", 15),
72 GATE_AUDIO1(CLK_AUD_ADC_HIRES, "aud_adc_hires",
73 "audio_h_sel", 16),
74 GATE_AUDIO1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml",
75 "audio_h_sel", 17),
76 GATE_AUDIO1(CLK_AUD_PDN_ADDA6_ADC, "aud_pdn_adda6_adc",
77 "audio_sel", 20),
78 GATE_AUDIO1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires",
79 "audio_h_sel",
80 21),
81 GATE_AUDIO1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "audio_sel",
82 28),
83 GATE_AUDIO1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis",
84 "audio_sel", 29),
85 GATE_AUDIO1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml",
86 "audio_sel", 30),
87 GATE_AUDIO1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires",
88 "audio_h_sel", 31),
89};
90
91static const struct of_device_id of_match_clk_mt6779_aud[] = {
92 { .compatible = "mediatek,mt6779-audio", },
93 {}
94};
95
96static int clk_mt6779_aud_probe(struct platform_device *pdev)
97{
98 struct clk_onecell_data *clk_data;
99 struct device_node *node = pdev->dev.of_node;
100
101 clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
102
103 mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
104 clk_data);
105
106 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
107}
108
109static struct platform_driver clk_mt6779_aud_drv = {
110 .probe = clk_mt6779_aud_probe,
111 .driver = {
112 .name = "clk-mt6779-aud",
113 .of_match_table = of_match_clk_mt6779_aud,
114 },
115};
116
117builtin_platform_driver(clk_mt6779_aud_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-cam.c b/drivers/clk/mediatek/clk-mt6779-cam.c
new file mode 100644
index 000000000000..244d4208b7fb
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-cam.c
@@ -0,0 +1,66 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9#include <dt-bindings/clock/mt6779-clk.h>
10
11#include "clk-mtk.h"
12#include "clk-gate.h"
13
14static const struct mtk_gate_regs cam_cg_regs = {
15 .set_ofs = 0x0004,
16 .clr_ofs = 0x0008,
17 .sta_ofs = 0x0000,
18};
19
20#define GATE_CAM(_id, _name, _parent, _shift) \
21 GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, \
22 &mtk_clk_gate_ops_setclr)
23
24static const struct mtk_gate cam_clks[] = {
25 GATE_CAM(CLK_CAM_LARB10, "camsys_larb10", "cam_sel", 0),
26 GATE_CAM(CLK_CAM_DFP_VAD, "camsys_dfp_vad", "cam_sel", 1),
27 GATE_CAM(CLK_CAM_LARB11, "camsys_larb11", "cam_sel", 2),
28 GATE_CAM(CLK_CAM_LARB9, "camsys_larb9", "cam_sel", 3),
29 GATE_CAM(CLK_CAM_CAM, "camsys_cam", "cam_sel", 6),
30 GATE_CAM(CLK_CAM_CAMTG, "camsys_camtg", "cam_sel", 7),
31 GATE_CAM(CLK_CAM_SENINF, "camsys_seninf", "cam_sel", 8),
32 GATE_CAM(CLK_CAM_CAMSV0, "camsys_camsv0", "cam_sel", 9),
33 GATE_CAM(CLK_CAM_CAMSV1, "camsys_camsv1", "cam_sel", 10),
34 GATE_CAM(CLK_CAM_CAMSV2, "camsys_camsv2", "cam_sel", 11),
35 GATE_CAM(CLK_CAM_CAMSV3, "camsys_camsv3", "cam_sel", 12),
36 GATE_CAM(CLK_CAM_CCU, "camsys_ccu", "cam_sel", 13),
37 GATE_CAM(CLK_CAM_FAKE_ENG, "camsys_fake_eng", "cam_sel", 14),
38};
39
40static const struct of_device_id of_match_clk_mt6779_cam[] = {
41 { .compatible = "mediatek,mt6779-camsys", },
42 {}
43};
44
45static int clk_mt6779_cam_probe(struct platform_device *pdev)
46{
47 struct clk_onecell_data *clk_data;
48 struct device_node *node = pdev->dev.of_node;
49
50 clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
51
52 mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks),
53 clk_data);
54
55 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
56}
57
58static struct platform_driver clk_mt6779_cam_drv = {
59 .probe = clk_mt6779_cam_probe,
60 .driver = {
61 .name = "clk-mt6779-cam",
62 .of_match_table = of_match_clk_mt6779_cam,
63 },
64};
65
66builtin_platform_driver(clk_mt6779_cam_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-img.c b/drivers/clk/mediatek/clk-mt6779-img.c
new file mode 100644
index 000000000000..26292a45c613
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-img.c
@@ -0,0 +1,58 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9#include <dt-bindings/clock/mt6779-clk.h>
10
11#include "clk-mtk.h"
12#include "clk-gate.h"
13
14static const struct mtk_gate_regs img_cg_regs = {
15 .set_ofs = 0x0004,
16 .clr_ofs = 0x0008,
17 .sta_ofs = 0x0000,
18};
19
20#define GATE_IMG(_id, _name, _parent, _shift) \
21 GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, \
22 &mtk_clk_gate_ops_setclr)
23
24static const struct mtk_gate img_clks[] = {
25 GATE_IMG(CLK_IMG_LARB5, "imgsys_larb5", "img_sel", 0),
26 GATE_IMG(CLK_IMG_LARB6, "imgsys_larb6", "img_sel", 1),
27 GATE_IMG(CLK_IMG_DIP, "imgsys_dip", "img_sel", 2),
28 GATE_IMG(CLK_IMG_MFB, "imgsys_mfb", "img_sel", 6),
29 GATE_IMG(CLK_IMG_WPE_A, "imgsys_wpe_a", "img_sel", 7),
30};
31
32static const struct of_device_id of_match_clk_mt6779_img[] = {
33 { .compatible = "mediatek,mt6779-imgsys", },
34 {}
35};
36
37static int clk_mt6779_img_probe(struct platform_device *pdev)
38{
39 struct clk_onecell_data *clk_data;
40 struct device_node *node = pdev->dev.of_node;
41
42 clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
43
44 mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
45 clk_data);
46
47 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
48}
49
50static struct platform_driver clk_mt6779_img_drv = {
51 .probe = clk_mt6779_img_probe,
52 .driver = {
53 .name = "clk-mt6779-img",
54 .of_match_table = of_match_clk_mt6779_img,
55 },
56};
57
58builtin_platform_driver(clk_mt6779_img_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-ipe.c b/drivers/clk/mediatek/clk-mt6779-ipe.c
new file mode 100644
index 000000000000..bb519075639c
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-ipe.c
@@ -0,0 +1,60 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9#include <dt-bindings/clock/mt6779-clk.h>
10
11#include "clk-mtk.h"
12#include "clk-gate.h"
13
14static const struct mtk_gate_regs ipe_cg_regs = {
15 .set_ofs = 0x0004,
16 .clr_ofs = 0x0008,
17 .sta_ofs = 0x0000,
18};
19
20#define GATE_IPE(_id, _name, _parent, _shift) \
21 GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, \
22 &mtk_clk_gate_ops_setclr)
23
24static const struct mtk_gate ipe_clks[] = {
25 GATE_IPE(CLK_IPE_LARB7, "ipe_larb7", "ipe_sel", 0),
26 GATE_IPE(CLK_IPE_LARB8, "ipe_larb8", "ipe_sel", 1),
27 GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "ipe_sel", 2),
28 GATE_IPE(CLK_IPE_FD, "ipe_fd", "ipe_sel", 3),
29 GATE_IPE(CLK_IPE_FE, "ipe_fe", "ipe_sel", 4),
30 GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "ipe_sel", 5),
31 GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "ipe_sel", 6),
32};
33
34static const struct of_device_id of_match_clk_mt6779_ipe[] = {
35 { .compatible = "mediatek,mt6779-ipesys", },
36 {}
37};
38
39static int clk_mt6779_ipe_probe(struct platform_device *pdev)
40{
41 struct clk_onecell_data *clk_data;
42 struct device_node *node = pdev->dev.of_node;
43
44 clk_data = mtk_alloc_clk_data(CLK_IPE_NR_CLK);
45
46 mtk_clk_register_gates(node, ipe_clks, ARRAY_SIZE(ipe_clks),
47 clk_data);
48
49 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
50}
51
52static struct platform_driver clk_mt6779_ipe_drv = {
53 .probe = clk_mt6779_ipe_probe,
54 .driver = {
55 .name = "clk-mt6779-ipe",
56 .of_match_table = of_match_clk_mt6779_ipe,
57 },
58};
59
60builtin_platform_driver(clk_mt6779_ipe_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-mfg.c b/drivers/clk/mediatek/clk-mt6779-mfg.c
new file mode 100644
index 000000000000..c6ee2a89c070
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-mfg.c
@@ -0,0 +1,55 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9
10#include "clk-mtk.h"
11#include "clk-gate.h"
12
13#include <dt-bindings/clock/mt6779-clk.h>
14
15static const struct mtk_gate_regs mfg_cg_regs = {
16 .set_ofs = 0x4,
17 .clr_ofs = 0x8,
18 .sta_ofs = 0x0,
19};
20
21#define GATE_MFG(_id, _name, _parent, _shift) \
22 GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, \
23 &mtk_clk_gate_ops_setclr)
24
25static const struct mtk_gate mfg_clks[] = {
26 GATE_MFG(CLK_MFGCFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
27};
28
29static int clk_mt6779_mfg_probe(struct platform_device *pdev)
30{
31 struct clk_onecell_data *clk_data;
32 struct device_node *node = pdev->dev.of_node;
33
34 clk_data = mtk_alloc_clk_data(CLK_MFGCFG_NR_CLK);
35
36 mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
37 clk_data);
38
39 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
40}
41
42static const struct of_device_id of_match_clk_mt6779_mfg[] = {
43 { .compatible = "mediatek,mt6779-mfgcfg", },
44 {}
45};
46
47static struct platform_driver clk_mt6779_mfg_drv = {
48 .probe = clk_mt6779_mfg_probe,
49 .driver = {
50 .name = "clk-mt6779-mfg",
51 .of_match_table = of_match_clk_mt6779_mfg,
52 },
53};
54
55builtin_platform_driver(clk_mt6779_mfg_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-mm.c b/drivers/clk/mediatek/clk-mt6779-mm.c
new file mode 100644
index 000000000000..fb5fbb8e3e41
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-mm.c
@@ -0,0 +1,113 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9#include <dt-bindings/clock/mt6779-clk.h>
10
11#include "clk-mtk.h"
12#include "clk-gate.h"
13
14static const struct mtk_gate_regs mm0_cg_regs = {
15 .set_ofs = 0x0104,
16 .clr_ofs = 0x0108,
17 .sta_ofs = 0x0100,
18};
19
20static const struct mtk_gate_regs mm1_cg_regs = {
21 .set_ofs = 0x0114,
22 .clr_ofs = 0x0118,
23 .sta_ofs = 0x0110,
24};
25
26#define GATE_MM0(_id, _name, _parent, _shift) \
27 GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, \
28 &mtk_clk_gate_ops_setclr)
29#define GATE_MM1(_id, _name, _parent, _shift) \
30 GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, \
31 &mtk_clk_gate_ops_setclr)
32
33static const struct mtk_gate mm_clks[] = {
34 /* MM0 */
35 GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
36 GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
37 GATE_MM0(CLK_MM_SMI_LARB1, "mm_smi_larb1", "mm_sel", 2),
38 GATE_MM0(CLK_MM_GALS_COMM0, "mm_gals_comm0", "mm_sel", 3),
39 GATE_MM0(CLK_MM_GALS_COMM1, "mm_gals_comm1", "mm_sel", 4),
40 GATE_MM0(CLK_MM_GALS_CCU2MM, "mm_gals_ccu2mm", "mm_sel", 5),
41 GATE_MM0(CLK_MM_GALS_IPU12MM, "mm_gals_ipu12mm", "mm_sel", 6),
42 GATE_MM0(CLK_MM_GALS_IMG2MM, "mm_gals_img2mm", "mm_sel", 7),
43 GATE_MM0(CLK_MM_GALS_CAM2MM, "mm_gals_cam2mm", "mm_sel", 8),
44 GATE_MM0(CLK_MM_GALS_IPU2MM, "mm_gals_ipu2mm", "mm_sel", 9),
45 GATE_MM0(CLK_MM_MDP_DL_TXCK, "mm_mdp_dl_txck", "mm_sel", 10),
46 GATE_MM0(CLK_MM_IPU_DL_TXCK, "mm_ipu_dl_txck", "mm_sel", 11),
47 GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 12),
48 GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 13),
49 GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 14),
50 GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 15),
51 GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 16),
52 GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 17),
53 GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 18),
54 GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 19),
55 GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 20),
56 GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 21),
57 GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 22),
58 GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 23),
59 GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 24),
60 GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 25),
61 GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 26),
62 GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "mm_sel", 27),
63 GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "mm_sel", 28),
64 GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "mm_sel", 29),
65 GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "mm_sel", 30),
66 GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),
67 /* MM1 */
68 GATE_MM1(CLK_MM_DSI0_MM_CK, "mm_dsi0_mmck", "mm_sel", 0),
69 GATE_MM1(CLK_MM_DSI0_IF_CK, "mm_dsi0_ifck", "mm_sel", 1),
70 GATE_MM1(CLK_MM_DPI_MM_CK, "mm_dpi_mmck", "mm_sel", 2),
71 GATE_MM1(CLK_MM_DPI_IF_CK, "mm_dpi_ifck", "dpi0_sel", 3),
72 GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 4),
73 GATE_MM1(CLK_MM_MDP_DL_RX_CK, "mm_mdp_dl_rxck", "mm_sel", 5),
74 GATE_MM1(CLK_MM_IPU_DL_RX_CK, "mm_ipu_dl_rxck", "mm_sel", 6),
75 GATE_MM1(CLK_MM_26M, "mm_26m", "f_f26m_ck", 7),
76 GATE_MM1(CLK_MM_MM_R2Y, "mm_mmsys_r2y", "mm_sel", 8),
77 GATE_MM1(CLK_MM_DISP_RSZ, "mm_disp_rsz", "mm_sel", 9),
78 GATE_MM1(CLK_MM_MDP_AAL, "mm_mdp_aal", "mm_sel", 10),
79 GATE_MM1(CLK_MM_MDP_HDR, "mm_mdp_hdr", "mm_sel", 11),
80 GATE_MM1(CLK_MM_DBI_MM_CK, "mm_dbi_mmck", "mm_sel", 12),
81 GATE_MM1(CLK_MM_DBI_IF_CK, "mm_dbi_ifck", "dpi0_sel", 13),
82 GATE_MM1(CLK_MM_DISP_POSTMASK0, "mm_disp_pm0", "mm_sel", 14),
83 GATE_MM1(CLK_MM_DISP_HRT_BW, "mm_disp_hrt_bw", "mm_sel", 15),
84 GATE_MM1(CLK_MM_DISP_OVL_FBDC, "mm_disp_ovl_fbdc", "mm_sel", 16),
85};
86
87static const struct of_device_id of_match_clk_mt6779_mm[] = {
88 { .compatible = "mediatek,mt6779-mmsys", },
89 {}
90};
91
92static int clk_mt6779_mm_probe(struct platform_device *pdev)
93{
94 struct clk_onecell_data *clk_data;
95 struct device_node *node = pdev->dev.of_node;
96
97 clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
98
99 mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
100 clk_data);
101
102 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
103}
104
105static struct platform_driver clk_mt6779_mm_drv = {
106 .probe = clk_mt6779_mm_probe,
107 .driver = {
108 .name = "clk-mt6779-mm",
109 .of_match_table = of_match_clk_mt6779_mm,
110 },
111};
112
113builtin_platform_driver(clk_mt6779_mm_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-vdec.c b/drivers/clk/mediatek/clk-mt6779-vdec.c
new file mode 100644
index 000000000000..1900da2586a1
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-vdec.c
@@ -0,0 +1,67 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9
10#include "clk-mtk.h"
11#include "clk-gate.h"
12
13#include <dt-bindings/clock/mt6779-clk.h>
14
15static const struct mtk_gate_regs vdec0_cg_regs = {
16 .set_ofs = 0x0000,
17 .clr_ofs = 0x0004,
18 .sta_ofs = 0x0000,
19};
20
21static const struct mtk_gate_regs vdec1_cg_regs = {
22 .set_ofs = 0x0008,
23 .clr_ofs = 0x000c,
24 .sta_ofs = 0x0008,
25};
26
27#define GATE_VDEC0_I(_id, _name, _parent, _shift) \
28 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, \
29 &mtk_clk_gate_ops_setclr_inv)
30#define GATE_VDEC1_I(_id, _name, _parent, _shift) \
31 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, \
32 &mtk_clk_gate_ops_setclr_inv)
33
34static const struct mtk_gate vdec_clks[] = {
35 /* VDEC0 */
36 GATE_VDEC0_I(CLK_VDEC_VDEC, "vdec_cken", "vdec_sel", 0),
37 /* VDEC1 */
38 GATE_VDEC1_I(CLK_VDEC_LARB1, "vdec_larb1_cken", "vdec_sel", 0),
39};
40
41static const struct of_device_id of_match_clk_mt6779_vdec[] = {
42 { .compatible = "mediatek,mt6779-vdecsys", },
43 {}
44};
45
46static int clk_mt6779_vdec_probe(struct platform_device *pdev)
47{
48 struct clk_onecell_data *clk_data;
49 struct device_node *node = pdev->dev.of_node;
50
51 clk_data = mtk_alloc_clk_data(CLK_VDEC_GCON_NR_CLK);
52
53 mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
54 clk_data);
55
56 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
57}
58
59static struct platform_driver clk_mt6779_vdec_drv = {
60 .probe = clk_mt6779_vdec_probe,
61 .driver = {
62 .name = "clk-mt6779-vdec",
63 .of_match_table = of_match_clk_mt6779_vdec,
64 },
65};
66
67builtin_platform_driver(clk_mt6779_vdec_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779-venc.c b/drivers/clk/mediatek/clk-mt6779-venc.c
new file mode 100644
index 000000000000..b41d1f859edc
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779-venc.c
@@ -0,0 +1,58 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/clk-provider.h>
8#include <linux/platform_device.h>
9
10#include "clk-mtk.h"
11#include "clk-gate.h"
12
13#include <dt-bindings/clock/mt6779-clk.h>
14
15static const struct mtk_gate_regs venc_cg_regs = {
16 .set_ofs = 0x0004,
17 .clr_ofs = 0x0008,
18 .sta_ofs = 0x0000,
19};
20
21#define GATE_VENC_I(_id, _name, _parent, _shift) \
22 GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, \
23 &mtk_clk_gate_ops_setclr_inv)
24
25static const struct mtk_gate venc_clks[] = {
26 GATE_VENC_I(CLK_VENC_GCON_LARB, "venc_larb", "venc_sel", 0),
27 GATE_VENC_I(CLK_VENC_GCON_VENC, "venc_venc", "venc_sel", 4),
28 GATE_VENC_I(CLK_VENC_GCON_JPGENC, "venc_jpgenc", "venc_sel", 8),
29 GATE_VENC_I(CLK_VENC_GCON_GALS, "venc_gals", "venc_sel", 28),
30};
31
32static const struct of_device_id of_match_clk_mt6779_venc[] = {
33 { .compatible = "mediatek,mt6779-vencsys", },
34 {}
35};
36
37static int clk_mt6779_venc_probe(struct platform_device *pdev)
38{
39 struct clk_onecell_data *clk_data;
40 struct device_node *node = pdev->dev.of_node;
41
42 clk_data = mtk_alloc_clk_data(CLK_VENC_GCON_NR_CLK);
43
44 mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
45 clk_data);
46
47 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
48}
49
50static struct platform_driver clk_mt6779_venc_drv = {
51 .probe = clk_mt6779_venc_probe,
52 .driver = {
53 .name = "clk-mt6779-venc",
54 .of_match_table = of_match_clk_mt6779_venc,
55 },
56};
57
58builtin_platform_driver(clk_mt6779_venc_drv);
diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
new file mode 100644
index 000000000000..608a9a6621a3
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6779.c
@@ -0,0 +1,1315 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#include <linux/of.h>
8#include <linux/of_address.h>
9#include <linux/of_device.h>
10#include <linux/platform_device.h>
11
12#include "clk-mtk.h"
13#include "clk-mux.h"
14#include "clk-gate.h"
15
16#include <dt-bindings/clock/mt6779-clk.h>
17
18static DEFINE_SPINLOCK(mt6779_clk_lock);
19
20static const struct mtk_fixed_clk top_fixed_clks[] = {
21 FIXED_CLK(CLK_TOP_CLK26M, "f_f26m_ck", "clk26m", 26000000),
22};
23
24static const struct mtk_fixed_factor top_divs[] = {
25 FACTOR(CLK_TOP_CLK13M, "clk13m", "clk26m", 1, 2),
26 FACTOR(CLK_TOP_F26M_CK_D2, "csw_f26m_ck_d2", "clk26m", 1, 2),
27 FACTOR(CLK_TOP_MAINPLL_CK, "mainpll_ck", "mainpll", 1, 1),
28 FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll_ck", 1, 2),
29 FACTOR(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2),
30 FACTOR(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4),
31 FACTOR(CLK_TOP_MAINPLL_D2_D8, "mainpll_d2_d8", "mainpll_d2", 1, 8),
32 FACTOR(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16),
33 FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
34 FACTOR(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2),
35 FACTOR(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4),
36 FACTOR(CLK_TOP_MAINPLL_D3_D8, "mainpll_d3_d8", "mainpll_d3", 1, 8),
37 FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
38 FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
39 FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
40 FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
41 FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
42 FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
43 FACTOR(CLK_TOP_UNIVPLL_CK, "univpll", "univ2pll", 1, 2),
44 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
45 FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2),
46 FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4),
47 FACTOR(CLK_TOP_UNIVPLL_D2_D8, "univpll_d2_d8", "univpll_d2", 1, 8),
48 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
49 FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2),
50 FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4),
51 FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8),
52 FACTOR(CLK_TOP_UNIVPLL_D3_D16, "univpll_d3_d16", "univpll_d3", 1, 16),
53 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
54 FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
55 FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
56 FACTOR(CLK_TOP_UNIVPLL_D5_D8, "univpll_d5_d8", "univpll_d5", 1, 8),
57 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
58 FACTOR(CLK_TOP_UNIVP_192M_CK, "univpll_192m_ck", "univ2pll", 1, 13),
59 FACTOR(CLK_TOP_UNIVP_192M_D2, "univpll_192m_d2", "univpll_192m_ck",
60 1, 2),
61 FACTOR(CLK_TOP_UNIVP_192M_D4, "univpll_192m_d4", "univpll_192m_ck",
62 1, 4),
63 FACTOR(CLK_TOP_UNIVP_192M_D8, "univpll_192m_d8", "univpll_192m_ck",
64 1, 8),
65 FACTOR(CLK_TOP_UNIVP_192M_D16, "univpll_192m_d16", "univpll_192m_ck",
66 1, 16),
67 FACTOR(CLK_TOP_UNIVP_192M_D32, "univpll_192m_d32", "univpll_192m_ck",
68 1, 32),
69 FACTOR(CLK_TOP_APLL1_CK, "apll1_ck", "apll1", 1, 1),
70 FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
71 FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
72 FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
73 FACTOR(CLK_TOP_APLL2_CK, "apll2_ck", "apll2", 1, 1),
74 FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
75 FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
76 FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
77 FACTOR(CLK_TOP_TVDPLL_CK, "tvdpll_ck", "tvdpll", 1, 1),
78 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1, 2),
79 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
80 FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
81 FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
82 FACTOR(CLK_TOP_MMPLL_CK, "mmpll_ck", "mmpll", 1, 1),
83 FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
84 FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll_d4", 1, 2),
85 FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll_d4", 1, 4),
86 FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
87 FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll_d5", 1, 2),
88 FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll_d5", 1, 4),
89 FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
90 FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
91 FACTOR(CLK_TOP_MFGPLL_CK, "mfgpll_ck", "mfgpll", 1, 1),
92 FACTOR(CLK_TOP_ADSPPLL_CK, "adsppll_ck", "adsppll", 1, 1),
93 FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
94 FACTOR(CLK_TOP_ADSPPLL_D5, "adsppll_d5", "adsppll", 1, 5),
95 FACTOR(CLK_TOP_ADSPPLL_D6, "adsppll_d6", "adsppll", 1, 6),
96 FACTOR(CLK_TOP_MSDCPLL_CK, "msdcpll_ck", "msdcpll", 1, 1),
97 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
98 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
99 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
100 FACTOR(CLK_TOP_MSDCPLL_D16, "msdcpll_d16", "msdcpll", 1, 16),
101 FACTOR(CLK_TOP_AD_OSC_CK, "ad_osc_ck", "osc", 1, 1),
102 FACTOR(CLK_TOP_OSC_D2, "osc_d2", "osc", 1, 2),
103 FACTOR(CLK_TOP_OSC_D4, "osc_d4", "osc", 1, 4),
104 FACTOR(CLK_TOP_OSC_D8, "osc_d8", "osc", 1, 8),
105 FACTOR(CLK_TOP_OSC_D10, "osc_d10", "osc", 1, 10),
106 FACTOR(CLK_TOP_OSC_D16, "osc_d16", "osc", 1, 16),
107 FACTOR(CLK_TOP_AD_OSC2_CK, "ad_osc2_ck", "osc2", 1, 1),
108 FACTOR(CLK_TOP_OSC2_D2, "osc2_d2", "osc2", 1, 2),
109 FACTOR(CLK_TOP_OSC2_D3, "osc2_d3", "osc2", 1, 3),
110 FACTOR(CLK_TOP_TVDPLL_MAINPLL_D2_CK, "tvdpll_mainpll_d2_ck",
111 "tvdpll", 1, 1),
112 FACTOR(CLK_TOP_FMEM_466M_CK, "fmem_466m_ck", "fmem", 1, 1),
113};
114
115static const char * const axi_parents[] = {
116 "clk26m",
117 "mainpll_d2_d4",
118 "mainpll_d7",
119 "osc_d4"
120};
121
122static const char * const mm_parents[] = {
123 "clk26m",
124 "tvdpll_mainpll_d2_ck",
125 "mmpll_d7",
126 "mmpll_d5_d2",
127 "mainpll_d2_d2",
128 "mainpll_d3_d2"
129};
130
131static const char * const scp_parents[] = {
132 "clk26m",
133 "univpll_d2_d8",
134 "mainpll_d2_d4",
135 "mainpll_d3",
136 "univpll_d3",
137 "ad_osc2_ck",
138 "osc2_d2",
139 "osc2_d3"
140};
141
142static const char * const img_parents[] = {
143 "clk26m",
144 "mainpll_d2",
145 "mainpll_d2",
146 "univpll_d3",
147 "mainpll_d3",
148 "mmpll_d5_d2",
149 "tvdpll_mainpll_d2_ck",
150 "mainpll_d5"
151};
152
153static const char * const ipe_parents[] = {
154 "clk26m",
155 "mainpll_d2",
156 "mmpll_d7",
157 "univpll_d3",
158 "mainpll_d3",
159 "mmpll_d5_d2",
160 "mainpll_d2_d2",
161 "mainpll_d5"
162};
163
164static const char * const dpe_parents[] = {
165 "clk26m",
166 "mainpll_d2",
167 "mmpll_d7",
168 "univpll_d3",
169 "mainpll_d3",
170 "mmpll_d5_d2",
171 "mainpll_d2_d2",
172 "mainpll_d5"
173};
174
175static const char * const cam_parents[] = {
176 "clk26m",
177 "mainpll_d2",
178 "mmpll_d6",
179 "mainpll_d3",
180 "mmpll_d7",
181 "univpll_d3",
182 "mmpll_d5_d2",
183 "adsppll_d5",
184 "tvdpll_mainpll_d2_ck",
185 "univpll_d3_d2"
186};
187
188static const char * const ccu_parents[] = {
189 "clk26m",
190 "mainpll_d2",
191 "mmpll_d6",
192 "mainpll_d3",
193 "mmpll_d7",
194 "univpll_d3",
195 "mmpll_d5_d2",
196 "mainpll_d2_d2",
197 "adsppll_d5",
198 "univpll_d3_d2"
199};
200
201static const char * const dsp_parents[] = {
202 "clk26m",
203 "univpll_d3_d8",
204 "univpll_d3_d4",
205 "mainpll_d2_d4",
206 "univpll_d3_d2",
207 "mainpll_d2_d2",
208 "univpll_d2_d2",
209 "mainpll_d3",
210 "univpll_d3",
211 "mmpll_d7",
212 "mmpll_d6",
213 "adsppll_d5",
214 "tvdpll_ck",
215 "tvdpll_mainpll_d2_ck",
216 "univpll_d2",
217 "adsppll_d4"
218};
219
220static const char * const dsp1_parents[] = {
221 "clk26m",
222 "univpll_d3_d8",
223 "univpll_d3_d4",
224 "mainpll_d2_d4",
225 "univpll_d3_d2",
226 "mainpll_d2_d2",
227 "univpll_d2_d2",
228 "mainpll_d3",
229 "univpll_d3",
230 "mmpll_d7",
231 "mmpll_d6",
232 "adsppll_d5",
233 "tvdpll_ck",
234 "tvdpll_mainpll_d2_ck",
235 "univpll_d2",
236 "adsppll_d4"
237};
238
239static const char * const dsp2_parents[] = {
240 "clk26m",
241 "univpll_d3_d8",
242 "univpll_d3_d4",
243 "mainpll_d2_d4",
244 "univpll_d3_d2",
245 "mainpll_d2_d2",
246 "univpll_d2_d2",
247 "mainpll_d3",
248 "univpll_d3",
249 "mmpll_d7",
250 "mmpll_d6",
251 "adsppll_d5",
252 "tvdpll_ck",
253 "tvdpll_mainpll_d2_ck",
254 "univpll_d2",
255 "adsppll_d4"
256};
257
258static const char * const dsp3_parents[] = {
259 "clk26m",
260 "univpll_d3_d8",
261 "mainpll_d2_d4",
262 "univpll_d3_d2",
263 "mainpll_d2_d2",
264 "univpll_d2_d2",
265 "mainpll_d3",
266 "univpll_d3",
267 "mmpll_d7",
268 "mmpll_d6",
269 "mainpll_d2",
270 "tvdpll_ck",
271 "tvdpll_mainpll_d2_ck",
272 "univpll_d2",
273 "adsppll_d4",
274 "mmpll_d4"
275};
276
277static const char * const ipu_if_parents[] = {
278 "clk26m",
279 "univpll_d3_d8",
280 "univpll_d3_d4",
281 "mainpll_d2_d4",
282 "univpll_d3_d2",
283 "mainpll_d2_d2",
284 "univpll_d2_d2",
285 "mainpll_d3",
286 "univpll_d3",
287 "mmpll_d7",
288 "mmpll_d6",
289 "adsppll_d5",
290 "tvdpll_ck",
291 "tvdpll_mainpll_d2_ck",
292 "univpll_d2",
293 "adsppll_d4"
294};
295
296static const char * const mfg_parents[] = {
297 "clk26m",
298 "mfgpll_ck",
299 "univpll_d3",
300 "mainpll_d5"
301};
302
303static const char * const f52m_mfg_parents[] = {
304 "clk26m",
305 "univpll_d3_d2",
306 "univpll_d3_d4",
307 "univpll_d3_d8"
308};
309
310static const char * const camtg_parents[] = {
311 "clk26m",
312 "univpll_192m_d8",
313 "univpll_d3_d8",
314 "univpll_192m_d4",
315 "univpll_d3_d16",
316 "csw_f26m_ck_d2",
317 "univpll_192m_d16",
318 "univpll_192m_d32"
319};
320
321static const char * const camtg2_parents[] = {
322 "clk26m",
323 "univpll_192m_d8",
324 "univpll_d3_d8",
325 "univpll_192m_d4",
326 "univpll_d3_d16",
327 "csw_f26m_ck_d2",
328 "univpll_192m_d16",
329 "univpll_192m_d32"
330};
331
332static const char * const camtg3_parents[] = {
333 "clk26m",
334 "univpll_192m_d8",
335 "univpll_d3_d8",
336 "univpll_192m_d4",
337 "univpll_d3_d16",
338 "csw_f26m_ck_d2",
339 "univpll_192m_d16",
340 "univpll_192m_d32"
341};
342
343static const char * const camtg4_parents[] = {
344 "clk26m",
345 "univpll_192m_d8",
346 "univpll_d3_d8",
347 "univpll_192m_d4",
348 "univpll_d3_d16",
349 "csw_f26m_ck_d2",
350 "univpll_192m_d16",
351 "univpll_192m_d32"
352};
353
354static const char * const uart_parents[] = {
355 "clk26m",
356 "univpll_d3_d8"
357};
358
359static const char * const spi_parents[] = {
360 "clk26m",
361 "mainpll_d5_d2",
362 "mainpll_d3_d4",
363 "msdcpll_d4"
364};
365
366static const char * const msdc50_hclk_parents[] = {
367 "clk26m",
368 "mainpll_d2_d2",
369 "mainpll_d3_d2"
370};
371
372static const char * const msdc50_0_parents[] = {
373 "clk26m",
374 "msdcpll_ck",
375 "msdcpll_d2",
376 "univpll_d2_d4",
377 "mainpll_d3_d2",
378 "univpll_d2_d2"
379};
380
381static const char * const msdc30_1_parents[] = {
382 "clk26m",
383 "univpll_d3_d2",
384 "mainpll_d3_d2",
385 "mainpll_d7",
386 "msdcpll_d2"
387};
388
389static const char * const audio_parents[] = {
390 "clk26m",
391 "mainpll_d5_d4",
392 "mainpll_d7_d4",
393 "mainpll_d2_d16"
394};
395
396static const char * const aud_intbus_parents[] = {
397 "clk26m",
398 "mainpll_d2_d4",
399 "mainpll_d7_d2"
400};
401
402static const char * const fpwrap_ulposc_parents[] = {
403 "osc_d10",
404 "clk26m",
405 "osc_d4",
406 "osc_d8",
407 "osc_d16"
408};
409
410static const char * const atb_parents[] = {
411 "clk26m",
412 "mainpll_d2_d2",
413 "mainpll_d5"
414};
415
416static const char * const sspm_parents[] = {
417 "clk26m",
418 "univpll_d2_d4",
419 "mainpll_d2_d2",
420 "univpll_d2_d2",
421 "mainpll_d3"
422};
423
424static const char * const dpi0_parents[] = {
425 "clk26m",
426 "tvdpll_d2",
427 "tvdpll_d4",
428 "tvdpll_d8",
429 "tvdpll_d16"
430};
431
432static const char * const scam_parents[] = {
433 "clk26m",
434 "mainpll_d5_d2"
435};
436
437static const char * const disppwm_parents[] = {
438 "clk26m",
439 "univpll_d3_d4",
440 "osc_d2",
441 "osc_d4",
442 "osc_d16"
443};
444
445static const char * const usb_top_parents[] = {
446 "clk26m",
447 "univpll_d5_d4",
448 "univpll_d3_d4",
449 "univpll_d5_d2"
450};
451
452static const char * const ssusb_top_xhci_parents[] = {
453 "clk26m",
454 "univpll_d5_d4",
455 "univpll_d3_d4",
456 "univpll_d5_d2"
457};
458
459static const char * const spm_parents[] = {
460 "clk26m",
461 "osc_d8",
462 "mainpll_d2_d8"
463};
464
465static const char * const i2c_parents[] = {
466 "clk26m",
467 "mainpll_d2_d8",
468 "univpll_d5_d2"
469};
470
471static const char * const seninf_parents[] = {
472 "clk26m",
473 "univpll_d7",
474 "univpll_d3_d2",
475 "univpll_d2_d2",
476 "mainpll_d3",
477 "mmpll_d4_d2",
478 "mmpll_d7",
479 "mmpll_d6"
480};
481
482static const char * const seninf1_parents[] = {
483 "clk26m",
484 "univpll_d7",
485 "univpll_d3_d2",
486 "univpll_d2_d2",
487 "mainpll_d3",
488 "mmpll_d4_d2",
489 "mmpll_d7",
490 "mmpll_d6"
491};
492
493static const char * const seninf2_parents[] = {
494 "clk26m",
495 "univpll_d7",
496 "univpll_d3_d2",
497 "univpll_d2_d2",
498 "mainpll_d3",
499 "mmpll_d4_d2",
500 "mmpll_d7",
501 "mmpll_d6"
502};
503
504static const char * const dxcc_parents[] = {
505 "clk26m",
506 "mainpll_d2_d2",
507 "mainpll_d2_d4",
508 "mainpll_d2_d8"
509};
510
511static const char * const aud_engen1_parents[] = {
512 "clk26m",
513 "apll1_d2",
514 "apll1_d4",
515 "apll1_d8"
516};
517
518static const char * const aud_engen2_parents[] = {
519 "clk26m",
520 "apll2_d2",
521 "apll2_d4",
522 "apll2_d8"
523};
524
525static const char * const faes_ufsfde_parents[] = {
526 "clk26m",
527 "mainpll_d2",
528 "mainpll_d2_d2",
529 "mainpll_d3",
530 "mainpll_d2_d4",
531 "univpll_d3"
532};
533
534static const char * const fufs_parents[] = {
535 "clk26m",
536 "mainpll_d2_d4",
537 "mainpll_d2_d8",
538 "mainpll_d2_d16"
539};
540
541static const char * const aud_1_parents[] = {
542 "clk26m",
543 "apll1_ck"
544};
545
546static const char * const aud_2_parents[] = {
547 "clk26m",
548 "apll2_ck"
549};
550
551static const char * const adsp_parents[] = {
552 "clk26m",
553 "mainpll_d3",
554 "univpll_d2_d4",
555 "univpll_d2",
556 "mmpll_d4",
557 "adsppll_d4",
558 "adsppll_d6"
559};
560
561static const char * const dpmaif_parents[] = {
562 "clk26m",
563 "univpll_d2_d4",
564 "mainpll_d3",
565 "mainpll_d2_d2",
566 "univpll_d2_d2",
567 "univpll_d3"
568};
569
570static const char * const venc_parents[] = {
571 "clk26m",
572 "mmpll_d7",
573 "mainpll_d3",
574 "univpll_d2_d2",
575 "mainpll_d2_d2",
576 "univpll_d3",
577 "mmpll_d6",
578 "mainpll_d5",
579 "mainpll_d3_d2",
580 "mmpll_d4_d2",
581 "univpll_d2_d4",
582 "mmpll_d5",
583 "univpll_192m_d2"
584
585};
586
587static const char * const vdec_parents[] = {
588 "clk26m",
589 "univpll_d2_d4",
590 "mainpll_d3",
591 "univpll_d2_d2",
592 "mainpll_d2_d2",
593 "univpll_d3",
594 "univpll_d5",
595 "univpll_d5_d2",
596 "mainpll_d2",
597 "univpll_d2",
598 "univpll_192m_d2"
599};
600
601static const char * const camtm_parents[] = {
602 "clk26m",
603 "univpll_d7",
604 "univpll_d3_d2",
605 "univpll_d2_d2"
606};
607
608static const char * const pwm_parents[] = {
609 "clk26m",
610 "univpll_d2_d8"
611};
612
613static const char * const audio_h_parents[] = {
614 "clk26m",
615 "univpll_d7",
616 "apll1_ck",
617 "apll2_ck"
618};
619
620static const char * const camtg5_parents[] = {
621 "clk26m",
622 "univpll_192m_d8",
623 "univpll_d3_d8",
624 "univpll_192m_d4",
625 "univpll_d3_d16",
626 "csw_f26m_ck_d2",
627 "univpll_192m_d16",
628 "univpll_192m_d32"
629};
630
631/*
632 * CRITICAL CLOCK:
633 * axi_sel is the main bus clock of whole SOC.
634 * spm_sel is the clock of the always-on co-processor.
635 * sspm_sel is the clock of the always-on co-processor.
636 */
637static const struct mtk_mux top_muxes[] = {
638 /* CLK_CFG_0 */
639 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "axi_sel", axi_parents,
640 0x20, 0x24, 0x28, 0, 2, 7,
641 0x004, 0, CLK_IS_CRITICAL),
642 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM, "mm_sel", mm_parents,
643 0x20, 0x24, 0x28, 8, 3, 15, 0x004, 1),
644 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP, "scp_sel", scp_parents,
645 0x20, 0x24, 0x28, 16, 3, 23, 0x004, 2),
646 /* CLK_CFG_1 */
647 MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG, "img_sel", img_parents,
648 0x30, 0x34, 0x38, 0, 3, 7, 0x004, 4),
649 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "ipe_sel", ipe_parents,
650 0x30, 0x34, 0x38, 8, 3, 15, 0x004, 5),
651 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPE, "dpe_sel", dpe_parents,
652 0x30, 0x34, 0x38, 16, 3, 23, 0x004, 6),
653 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "cam_sel", cam_parents,
654 0x30, 0x34, 0x38, 24, 4, 31, 0x004, 7),
655 /* CLK_CFG_2 */
656 MUX_GATE_CLR_SET_UPD(CLK_TOP_CCU, "ccu_sel", ccu_parents,
657 0x40, 0x44, 0x48, 0, 4, 7, 0x004, 8),
658 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP, "dsp_sel", dsp_parents,
659 0x40, 0x44, 0x48, 8, 4, 15, 0x004, 9),
660 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP1, "dsp1_sel", dsp1_parents,
661 0x40, 0x44, 0x48, 16, 4, 23, 0x004, 10),
662 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP2, "dsp2_sel", dsp2_parents,
663 0x40, 0x44, 0x48, 24, 4, 31, 0x004, 11),
664 /* CLK_CFG_3 */
665 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP3, "dsp3_sel", dsp3_parents,
666 0x50, 0x54, 0x58, 0, 4, 7, 0x004, 12),
667 MUX_GATE_CLR_SET_UPD(CLK_TOP_IPU_IF, "ipu_if_sel", ipu_if_parents,
668 0x50, 0x54, 0x58, 8, 4, 15, 0x004, 13),
669 MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "mfg_sel", mfg_parents,
670 0x50, 0x54, 0x58, 16, 2, 23, 0x004, 14),
671 MUX_GATE_CLR_SET_UPD(CLK_TOP_F52M_MFG, "f52m_mfg_sel",
672 f52m_mfg_parents, 0x50, 0x54, 0x58,
673 24, 2, 31, 0x004, 15),
674 /* CLK_CFG_4 */
675 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "camtg_sel", camtg_parents,
676 0x60, 0x64, 0x68, 0, 3, 7, 0x004, 16),
677 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "camtg2_sel", camtg2_parents,
678 0x60, 0x64, 0x68, 8, 3, 15, 0x004, 17),
679 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "camtg3_sel", camtg3_parents,
680 0x60, 0x64, 0x68, 16, 3, 23, 0x004, 18),
681 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "camtg4_sel", camtg4_parents,
682 0x60, 0x64, 0x68, 24, 3, 31, 0x004, 19),
683 /* CLK_CFG_5 */
684 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "uart_sel", uart_parents,
685 0x70, 0x74, 0x78, 0, 1, 7, 0x004, 20),
686 MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "spi_sel", spi_parents,
687 0x70, 0x74, 0x78, 8, 2, 15, 0x004, 21),
688 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "msdc50_hclk_sel",
689 msdc50_hclk_parents, 0x70, 0x74, 0x78,
690 16, 2, 23, 0x004, 22),
691 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "msdc50_0_sel",
692 msdc50_0_parents, 0x70, 0x74, 0x78,
693 24, 3, 31, 0x004, 23),
694 /* CLK_CFG_6 */
695 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "msdc30_1_sel",
696 msdc30_1_parents, 0x80, 0x84, 0x88,
697 0, 3, 7, 0x004, 24),
698 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD, "audio_sel", audio_parents,
699 0x80, 0x84, 0x88, 8, 2, 15, 0x004, 25),
700 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "aud_intbus_sel",
701 aud_intbus_parents, 0x80, 0x84, 0x88,
702 16, 2, 23, 0x004, 26),
703 MUX_GATE_CLR_SET_UPD(CLK_TOP_FPWRAP_ULPOSC, "fpwrap_ulposc_sel",
704 fpwrap_ulposc_parents, 0x80, 0x84, 0x88,
705 24, 3, 31, 0x004, 27),
706 /* CLK_CFG_7 */
707 MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB, "atb_sel", atb_parents,
708 0x90, 0x94, 0x98, 0, 2, 7, 0x004, 28),
709 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "sspm_sel", sspm_parents,
710 0x90, 0x94, 0x98, 8, 3, 15,
711 0x004, 29, CLK_IS_CRITICAL),
712 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI0, "dpi0_sel", dpi0_parents,
713 0x90, 0x94, 0x98, 16, 3, 23, 0x004, 30),
714 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCAM, "scam_sel", scam_parents,
715 0x90, 0x94, 0x98, 24, 1, 31, 0x004, 0),
716 /* CLK_CFG_8 */
717 MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM, "disppwm_sel",
718 disppwm_parents, 0xa0, 0xa4, 0xa8,
719 0, 3, 7, 0x008, 1),
720 MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "usb_top_sel",
721 usb_top_parents, 0xa0, 0xa4, 0xa8,
722 8, 2, 15, 0x008, 2),
723 MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_TOP_XHCI, "ssusb_top_xhci_sel",
724 ssusb_top_xhci_parents, 0xa0, 0xa4, 0xa8,
725 16, 2, 23, 0x008, 3),
726 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "spm_sel", spm_parents,
727 0xa0, 0xa4, 0xa8, 24, 2, 31,
728 0x008, 4, CLK_IS_CRITICAL),
729 /* CLK_CFG_9 */
730 MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "i2c_sel", i2c_parents,
731 0xb0, 0xb4, 0xb8, 0, 2, 7, 0x008, 5),
732 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "seninf_sel", seninf_parents,
733 0xb0, 0xb4, 0xb8, 8, 2, 15, 0x008, 6),
734 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "seninf1_sel",
735 seninf1_parents, 0xb0, 0xb4, 0xb8,
736 16, 2, 23, 0x008, 7),
737 MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "seninf2_sel",
738 seninf2_parents, 0xb0, 0xb4, 0xb8,
739 24, 2, 31, 0x008, 8),
740 /* CLK_CFG_10 */
741 MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "dxcc_sel", dxcc_parents,
742 0xc0, 0xc4, 0xc8, 0, 2, 7, 0x008, 9),
743 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG1, "aud_eng1_sel",
744 aud_engen1_parents, 0xc0, 0xc4, 0xc8,
745 8, 2, 15, 0x008, 10),
746 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENG2, "aud_eng2_sel",
747 aud_engen2_parents, 0xc0, 0xc4, 0xc8,
748 16, 2, 23, 0x008, 11),
749 MUX_GATE_CLR_SET_UPD(CLK_TOP_FAES_UFSFDE, "faes_ufsfde_sel",
750 faes_ufsfde_parents, 0xc0, 0xc4, 0xc8,
751 24, 3, 31,
752 0x008, 12),
753 /* CLK_CFG_11 */
754 MUX_GATE_CLR_SET_UPD(CLK_TOP_FUFS, "fufs_sel", fufs_parents,
755 0xd0, 0xd4, 0xd8, 0, 2, 7, 0x008, 13),
756 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1, "aud_1_sel", aud_1_parents,
757 0xd0, 0xd4, 0xd8, 8, 1, 15, 0x008, 14),
758 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2, "aud_2_sel", aud_2_parents,
759 0xd0, 0xd4, 0xd8, 16, 1, 23, 0x008, 15),
760 MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP, "adsp_sel", adsp_parents,
761 0xd0, 0xd4, 0xd8, 24, 3, 31, 0x008, 16),
762 /* CLK_CFG_12 */
763 MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF, "dpmaif_sel", dpmaif_parents,
764 0xe0, 0xe4, 0xe8, 0, 3, 7, 0x008, 17),
765 MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "venc_sel", venc_parents,
766 0xe0, 0xe4, 0xe8, 8, 4, 15, 0x008, 18),
767 MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "vdec_sel", vdec_parents,
768 0xe0, 0xe4, 0xe8, 16, 4, 23, 0x008, 19),
769 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "camtm_sel", camtm_parents,
770 0xe0, 0xe4, 0xe8, 24, 2, 31, 0x004, 20),
771 /* CLK_CFG_13 */
772 MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "pwm_sel", pwm_parents,
773 0xf0, 0xf4, 0xf8, 0, 1, 7, 0x008, 21),
774 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_H, "audio_h_sel",
775 audio_h_parents, 0xf0, 0xf4, 0xf8,
776 8, 2, 15, 0x008, 22),
777 MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "camtg5_sel", camtg5_parents,
778 0xf0, 0xf4, 0xf8, 24, 3, 31, 0x008, 24),
779};
780
781static const char * const i2s0_m_ck_parents[] = {
782 "aud_1_sel",
783 "aud_2_sel"
784};
785
786static const char * const i2s1_m_ck_parents[] = {
787 "aud_1_sel",
788 "aud_2_sel"
789};
790
791static const char * const i2s2_m_ck_parents[] = {
792 "aud_1_sel",
793 "aud_2_sel"
794};
795
796static const char * const i2s3_m_ck_parents[] = {
797 "aud_1_sel",
798 "aud_2_sel"
799};
800
801static const char * const i2s4_m_ck_parents[] = {
802 "aud_1_sel",
803 "aud_2_sel"
804};
805
806static const char * const i2s5_m_ck_parents[] = {
807 "aud_1_sel",
808 "aud_2_sel"
809};
810
811static const struct mtk_composite top_aud_muxes[] = {
812 MUX(CLK_TOP_I2S0_M_SEL, "i2s0_m_ck_sel", i2s0_m_ck_parents,
813 0x320, 8, 1),
814 MUX(CLK_TOP_I2S1_M_SEL, "i2s1_m_ck_sel", i2s1_m_ck_parents,
815 0x320, 9, 1),
816 MUX(CLK_TOP_I2S2_M_SEL, "i2s2_m_ck_sel", i2s2_m_ck_parents,
817 0x320, 10, 1),
818 MUX(CLK_TOP_I2S3_M_SEL, "i2s3_m_ck_sel", i2s3_m_ck_parents,
819 0x320, 11, 1),
820 MUX(CLK_TOP_I2S4_M_SEL, "i2s4_m_ck_sel", i2s4_m_ck_parents,
821 0x320, 12, 1),
822 MUX(CLK_TOP_I2S5_M_SEL, "i2s5_m_ck_sel", i2s5_m_ck_parents,
823 0x328, 20, 1),
824};
825
826static struct mtk_composite top_aud_divs[] = {
827 DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "i2s0_m_ck_sel",
828 0x320, 2, 0x324, 8, 0),
829 DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "i2s1_m_ck_sel",
830 0x320, 3, 0x324, 8, 8),
831 DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "i2s2_m_ck_sel",
832 0x320, 4, 0x324, 8, 16),
833 DIV_GATE(CLK_TOP_APLL12_DIV3, "apll12_div3", "i2s3_m_ck_sel",
834 0x320, 5, 0x324, 8, 24),
835 DIV_GATE(CLK_TOP_APLL12_DIV4, "apll12_div4", "i2s4_m_ck_sel",
836 0x320, 6, 0x328, 8, 0),
837 DIV_GATE(CLK_TOP_APLL12_DIVB, "apll12_divb", "apll12_div4",
838 0x320, 7, 0x328, 8, 8),
839 DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "i2s5_m_ck_sel",
840 0x328, 16, 0x328, 4, 28),
841};
842
843static const struct mtk_gate_regs infra0_cg_regs = {
844 .set_ofs = 0x80,
845 .clr_ofs = 0x84,
846 .sta_ofs = 0x90,
847};
848
849static const struct mtk_gate_regs infra1_cg_regs = {
850 .set_ofs = 0x88,
851 .clr_ofs = 0x8c,
852 .sta_ofs = 0x94,
853};
854
855static const struct mtk_gate_regs infra2_cg_regs = {
856 .set_ofs = 0xa4,
857 .clr_ofs = 0xa8,
858 .sta_ofs = 0xac,
859};
860
861static const struct mtk_gate_regs infra3_cg_regs = {
862 .set_ofs = 0xc0,
863 .clr_ofs = 0xc4,
864 .sta_ofs = 0xc8,
865};
866
867#define GATE_INFRA0(_id, _name, _parent, _shift) \
868 GATE_MTK(_id, _name, _parent, &infra0_cg_regs, _shift, \
869 &mtk_clk_gate_ops_setclr)
870#define GATE_INFRA1(_id, _name, _parent, _shift) \
871 GATE_MTK(_id, _name, _parent, &infra1_cg_regs, _shift, \
872 &mtk_clk_gate_ops_setclr)
873#define GATE_INFRA2(_id, _name, _parent, _shift) \
874 GATE_MTK(_id, _name, _parent, &infra2_cg_regs, _shift, \
875 &mtk_clk_gate_ops_setclr)
876#define GATE_INFRA3(_id, _name, _parent, _shift) \
877 GATE_MTK(_id, _name, _parent, &infra3_cg_regs, _shift, \
878 &mtk_clk_gate_ops_setclr)
879
880static const struct mtk_gate infra_clks[] = {
881 /* INFRA0 */
882 GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr",
883 "axi_sel", 0),
884 GATE_INFRA0(CLK_INFRA_PMIC_AP, "infra_pmic_ap",
885 "axi_sel", 1),
886 GATE_INFRA0(CLK_INFRA_PMIC_MD, "infra_pmic_md",
887 "axi_sel", 2),
888 GATE_INFRA0(CLK_INFRA_PMIC_CONN, "infra_pmic_conn",
889 "axi_sel", 3),
890 GATE_INFRA0(CLK_INFRA_SCPSYS, "infra_scp",
891 "axi_sel", 4),
892 GATE_INFRA0(CLK_INFRA_SEJ, "infra_sej",
893 "f_f26m_ck", 5),
894 GATE_INFRA0(CLK_INFRA_APXGPT, "infra_apxgpt",
895 "axi_sel", 6),
896 GATE_INFRA0(CLK_INFRA_ICUSB, "infra_icusb",
897 "axi_sel", 8),
898 GATE_INFRA0(CLK_INFRA_GCE, "infra_gce",
899 "axi_sel", 9),
900 GATE_INFRA0(CLK_INFRA_THERM, "infra_therm",
901 "axi_sel", 10),
902 GATE_INFRA0(CLK_INFRA_I2C0, "infra_i2c0",
903 "i2c_sel", 11),
904 GATE_INFRA0(CLK_INFRA_I2C1, "infra_i2c1",
905 "i2c_sel", 12),
906 GATE_INFRA0(CLK_INFRA_I2C2, "infra_i2c2",
907 "i2c_sel", 13),
908 GATE_INFRA0(CLK_INFRA_I2C3, "infra_i2c3",
909 "i2c_sel", 14),
910 GATE_INFRA0(CLK_INFRA_PWM_HCLK, "infra_pwm_hclk",
911 "pwm_sel", 15),
912 GATE_INFRA0(CLK_INFRA_PWM1, "infra_pwm1",
913 "pwm_sel", 16),
914 GATE_INFRA0(CLK_INFRA_PWM2, "infra_pwm2",
915 "pwm_sel", 17),
916 GATE_INFRA0(CLK_INFRA_PWM3, "infra_pwm3",
917 "pwm_sel", 18),
918 GATE_INFRA0(CLK_INFRA_PWM4, "infra_pwm4",
919 "pwm_sel", 19),
920 GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
921 "pwm_sel", 21),
922 GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
923 "uart_sel", 23),
924 GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
925 "uart_sel", 24),
926 GATE_INFRA0(CLK_INFRA_UART3, "infra_uart3",
927 "uart_sel", 25),
928 GATE_INFRA0(CLK_INFRA_GCE_26M, "infra_gce_26m",
929 "axi_sel", 27),
930 GATE_INFRA0(CLK_INFRA_CQ_DMA_FPC, "infra_cqdma_fpc",
931 "axi_sel", 28),
932 GATE_INFRA0(CLK_INFRA_BTIF, "infra_btif",
933 "axi_sel", 31),
934 /* INFRA1 */
935 GATE_INFRA1(CLK_INFRA_SPI0, "infra_spi0",
936 "spi_sel", 1),
937 GATE_INFRA1(CLK_INFRA_MSDC0, "infra_msdc0",
938 "msdc50_hclk_sel", 2),
939 GATE_INFRA1(CLK_INFRA_MSDC1, "infra_msdc1",
940 "axi_sel", 4),
941 GATE_INFRA1(CLK_INFRA_MSDC2, "infra_msdc2",
942 "axi_sel", 5),
943 GATE_INFRA1(CLK_INFRA_MSDC0_SCK, "infra_msdc0_sck",
944 "msdc50_0_sel", 6),
945 GATE_INFRA1(CLK_INFRA_DVFSRC, "infra_dvfsrc",
946 "f_f26m_ck", 7),
947 GATE_INFRA1(CLK_INFRA_GCPU, "infra_gcpu",
948 "axi_sel", 8),
949 GATE_INFRA1(CLK_INFRA_TRNG, "infra_trng",
950 "axi_sel", 9),
951 GATE_INFRA1(CLK_INFRA_AUXADC, "infra_auxadc",
952 "f_f26m_ck", 10),
953 GATE_INFRA1(CLK_INFRA_CPUM, "infra_cpum",
954 "axi_sel", 11),
955 GATE_INFRA1(CLK_INFRA_CCIF1_AP, "infra_ccif1_ap",
956 "axi_sel", 12),
957 GATE_INFRA1(CLK_INFRA_CCIF1_MD, "infra_ccif1_md",
958 "axi_sel", 13),
959 GATE_INFRA1(CLK_INFRA_AUXADC_MD, "infra_auxadc_md",
960 "f_f26m_ck", 14),
961 GATE_INFRA1(CLK_INFRA_MSDC1_SCK, "infra_msdc1_sck",
962 "msdc30_1_sel", 16),
963 GATE_INFRA1(CLK_INFRA_MSDC2_SCK, "infra_msdc2_sck",
964 "msdc30_2_sel", 17),
965 GATE_INFRA1(CLK_INFRA_AP_DMA, "infra_apdma",
966 "axi_sel", 18),
967 GATE_INFRA1(CLK_INFRA_XIU, "infra_xiu",
968 "axi_sel", 19),
969 GATE_INFRA1(CLK_INFRA_DEVICE_APC, "infra_device_apc",
970 "axi_sel", 20),
971 GATE_INFRA1(CLK_INFRA_CCIF_AP, "infra_ccif_ap",
972 "axi_sel", 23),
973 GATE_INFRA1(CLK_INFRA_DEBUGSYS, "infra_debugsys",
974 "axi_sel", 24),
975 GATE_INFRA1(CLK_INFRA_AUD, "infra_audio",
976 "axi_sel", 25),
977 GATE_INFRA1(CLK_INFRA_CCIF_MD, "infra_ccif_md",
978 "axi_sel", 26),
979 GATE_INFRA1(CLK_INFRA_DXCC_SEC_CORE, "infra_dxcc_sec_core",
980 "dxcc_sel", 27),
981 GATE_INFRA1(CLK_INFRA_DXCC_AO, "infra_dxcc_ao",
982 "dxcc_sel", 28),
983 GATE_INFRA1(CLK_INFRA_DEVMPU_BCLK, "infra_devmpu_bclk",
984 "axi_sel", 30),
985 GATE_INFRA1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
986 "f_f26m_ck", 31),
987 /* INFRA2 */
988 GATE_INFRA2(CLK_INFRA_IRTX, "infra_irtx",
989 "f_f26m_ck", 0),
990 GATE_INFRA2(CLK_INFRA_USB, "infra_usb",
991 "usb_top_sel", 1),
992 GATE_INFRA2(CLK_INFRA_DISP_PWM, "infra_disppwm",
993 "axi_sel", 2),
994 GATE_INFRA2(CLK_INFRA_AUD_26M_BCLK,
995 "infracfg_ao_audio_26m_bclk", "f_f26m_ck", 4),
996 GATE_INFRA2(CLK_INFRA_SPI1, "infra_spi1",
997 "spi_sel", 6),
998 GATE_INFRA2(CLK_INFRA_I2C4, "infra_i2c4",
999 "i2c_sel", 7),
1000 GATE_INFRA2(CLK_INFRA_MODEM_TEMP_SHARE, "infra_md_tmp_share",
1001 "f_f26m_ck", 8),
1002 GATE_INFRA2(CLK_INFRA_SPI2, "infra_spi2",
1003 "spi_sel", 9),
1004 GATE_INFRA2(CLK_INFRA_SPI3, "infra_spi3",
1005 "spi_sel", 10),
1006 GATE_INFRA2(CLK_INFRA_UNIPRO_SCK, "infra_unipro_sck",
1007 "fufs_sel", 11),
1008 GATE_INFRA2(CLK_INFRA_UNIPRO_TICK, "infra_unipro_tick",
1009 "fufs_sel", 12),
1010 GATE_INFRA2(CLK_INFRA_UFS_MP_SAP_BCLK, "infra_ufs_mp_sap_bck",
1011 "fufs_sel", 13),
1012 GATE_INFRA2(CLK_INFRA_MD32_BCLK, "infra_md32_bclk",
1013 "axi_sel", 14),
1014 GATE_INFRA2(CLK_INFRA_UNIPRO_MBIST, "infra_unipro_mbist",
1015 "axi_sel", 16),
1016 GATE_INFRA2(CLK_INFRA_SSPM_BUS_HCLK, "infra_sspm_bus_hclk",
1017 "axi_sel", 17),
1018 GATE_INFRA2(CLK_INFRA_I2C5, "infra_i2c5",
1019 "i2c_sel", 18),
1020 GATE_INFRA2(CLK_INFRA_I2C5_ARBITER, "infra_i2c5_arbiter",
1021 "i2c_sel", 19),
1022 GATE_INFRA2(CLK_INFRA_I2C5_IMM, "infra_i2c5_imm",
1023 "i2c_sel", 20),
1024 GATE_INFRA2(CLK_INFRA_I2C1_ARBITER, "infra_i2c1_arbiter",
1025 "i2c_sel", 21),
1026 GATE_INFRA2(CLK_INFRA_I2C1_IMM, "infra_i2c1_imm",
1027 "i2c_sel", 22),
1028 GATE_INFRA2(CLK_INFRA_I2C2_ARBITER, "infra_i2c2_arbiter",
1029 "i2c_sel", 23),
1030 GATE_INFRA2(CLK_INFRA_I2C2_IMM, "infra_i2c2_imm",
1031 "i2c_sel", 24),
1032 GATE_INFRA2(CLK_INFRA_SPI4, "infra_spi4",
1033 "spi_sel", 25),
1034 GATE_INFRA2(CLK_INFRA_SPI5, "infra_spi5",
1035 "spi_sel", 26),
1036 GATE_INFRA2(CLK_INFRA_CQ_DMA, "infra_cqdma",
1037 "axi_sel", 27),
1038 GATE_INFRA2(CLK_INFRA_UFS, "infra_ufs",
1039 "fufs_sel", 28),
1040 GATE_INFRA2(CLK_INFRA_AES_UFSFDE, "infra_aes_ufsfde",
1041 "faes_ufsfde_sel", 29),
1042 GATE_INFRA2(CLK_INFRA_UFS_TICK, "infra_ufs_tick",
1043 "fufs_sel", 30),
1044 GATE_INFRA2(CLK_INFRA_SSUSB_XHCI, "infra_ssusb_xhci",
1045 "ssusb_top_xhci_sel", 31),
1046 /* INFRA3 */
1047 GATE_INFRA3(CLK_INFRA_MSDC0_SELF, "infra_msdc0_self",
1048 "msdc50_0_sel", 0),
1049 GATE_INFRA3(CLK_INFRA_MSDC1_SELF, "infra_msdc1_self",
1050 "msdc50_0_sel", 1),
1051 GATE_INFRA3(CLK_INFRA_MSDC2_SELF, "infra_msdc2_self",
1052 "msdc50_0_sel", 2),
1053 GATE_INFRA3(CLK_INFRA_SSPM_26M_SELF, "infra_sspm_26m_self",
1054 "f_f26m_ck", 3),
1055 GATE_INFRA3(CLK_INFRA_SSPM_32K_SELF, "infra_sspm_32k_self",
1056 "f_f26m_ck", 4),
1057 GATE_INFRA3(CLK_INFRA_UFS_AXI, "infra_ufs_axi",
1058 "axi_sel", 5),
1059 GATE_INFRA3(CLK_INFRA_I2C6, "infra_i2c6",
1060 "i2c_sel", 6),
1061 GATE_INFRA3(CLK_INFRA_AP_MSDC0, "infra_ap_msdc0",
1062 "msdc50_hclk_sel", 7),
1063 GATE_INFRA3(CLK_INFRA_MD_MSDC0, "infra_md_msdc0",
1064 "msdc50_hclk_sel", 8),
1065 GATE_INFRA3(CLK_INFRA_CCIF2_AP, "infra_ccif2_ap",
1066 "axi_sel", 16),
1067 GATE_INFRA3(CLK_INFRA_CCIF2_MD, "infra_ccif2_md",
1068 "axi_sel", 17),
1069 GATE_INFRA3(CLK_INFRA_CCIF3_AP, "infra_ccif3_ap",
1070 "axi_sel", 18),
1071 GATE_INFRA3(CLK_INFRA_CCIF3_MD, "infra_ccif3_md",
1072 "axi_sel", 19),
1073 GATE_INFRA3(CLK_INFRA_SEJ_F13M, "infra_sej_f13m",
1074 "f_f26m_ck", 20),
1075 GATE_INFRA3(CLK_INFRA_AES_BCLK, "infra_aes_bclk",
1076 "axi_sel", 21),
1077 GATE_INFRA3(CLK_INFRA_I2C7, "infra_i2c7",
1078 "i2c_sel", 22),
1079 GATE_INFRA3(CLK_INFRA_I2C8, "infra_i2c8",
1080 "i2c_sel", 23),
1081 GATE_INFRA3(CLK_INFRA_FBIST2FPC, "infra_fbist2fpc",
1082 "msdc50_0_sel", 24),
1083 GATE_INFRA3(CLK_INFRA_DPMAIF_CK, "infra_dpmaif",
1084 "dpmaif_sel", 26),
1085 GATE_INFRA3(CLK_INFRA_FADSP, "infra_fadsp",
1086 "adsp_sel", 27),
1087 GATE_INFRA3(CLK_INFRA_CCIF4_AP, "infra_ccif4_ap",
1088 "axi_sel", 28),
1089 GATE_INFRA3(CLK_INFRA_CCIF4_MD, "infra_ccif4_md",
1090 "axi_sel", 29),
1091 GATE_INFRA3(CLK_INFRA_SPI6, "infra_spi6",
1092 "spi_sel", 30),
1093 GATE_INFRA3(CLK_INFRA_SPI7, "infra_spi7",
1094 "spi_sel", 31),
1095};
1096
1097static const struct mtk_gate_regs apmixed_cg_regs = {
1098 .set_ofs = 0x20,
1099 .clr_ofs = 0x20,
1100 .sta_ofs = 0x20,
1101};
1102
1103#define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \
1104 GATE_MTK_FLAGS(_id, _name, _parent, &apmixed_cg_regs, \
1105 _shift, &mtk_clk_gate_ops_no_setclr_inv, _flags)
1106
1107#define GATE_APMIXED(_id, _name, _parent, _shift) \
1108 GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, 0)
1109
1110/*
1111 * CRITICAL CLOCK:
1112 * apmixed_appll26m is the toppest clock gate of all PLLs.
1113 */
1114static const struct mtk_gate apmixed_clks[] = {
1115 GATE_APMIXED(CLK_APMIXED_SSUSB26M, "apmixed_ssusb26m",
1116 "f_f26m_ck", 4),
1117 GATE_APMIXED_FLAGS(CLK_APMIXED_APPLL26M, "apmixed_appll26m",
1118 "f_f26m_ck", 5, CLK_IS_CRITICAL),
1119 GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m",
1120 "f_f26m_ck", 6),
1121 GATE_APMIXED(CLK_APMIXED_MDPLLGP26M, "apmixed_mdpll26m",
1122 "f_f26m_ck", 7),
1123 GATE_APMIXED(CLK_APMIXED_MM_F26M, "apmixed_mmsys26m",
1124 "f_f26m_ck", 8),
1125 GATE_APMIXED(CLK_APMIXED_UFS26M, "apmixed_ufs26m",
1126 "f_f26m_ck", 9),
1127 GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m",
1128 "f_f26m_ck", 11),
1129 GATE_APMIXED(CLK_APMIXED_MEMPLL26M, "apmixed_mempll26m",
1130 "f_f26m_ck", 13),
1131 GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
1132 "f_f26m_ck", 14),
1133 GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m",
1134 "f_f26m_ck", 16),
1135 GATE_APMIXED(CLK_APMIXED_MIPID1_26M, "apmixed_mipid126m",
1136 "f_f26m_ck", 17),
1137};
1138
1139#define MT6779_PLL_FMAX (3800UL * MHZ)
1140#define MT6779_PLL_FMIN (1500UL * MHZ)
1141
1142#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1143 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
1144 _pd_shift, _tuner_reg, _tuner_en_reg, \
1145 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1146 _pcw_chg_reg, _div_table) { \
1147 .id = _id, \
1148 .name = _name, \
1149 .reg = _reg, \
1150 .pwr_reg = _pwr_reg, \
1151 .en_mask = _en_mask, \
1152 .flags = _flags, \
1153 .rst_bar_mask = _rst_bar_mask, \
1154 .fmax = MT6779_PLL_FMAX, \
1155 .fmin = MT6779_PLL_FMIN, \
1156 .pcwbits = _pcwbits, \
1157 .pcwibits = _pcwibits, \
1158 .pd_reg = _pd_reg, \
1159 .pd_shift = _pd_shift, \
1160 .tuner_reg = _tuner_reg, \
1161 .tuner_en_reg = _tuner_en_reg, \
1162 .tuner_en_bit = _tuner_en_bit, \
1163 .pcw_reg = _pcw_reg, \
1164 .pcw_shift = _pcw_shift, \
1165 .pcw_chg_reg = _pcw_chg_reg, \
1166 .div_table = _div_table, \
1167 }
1168
1169#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1170 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
1171 _pd_shift, _tuner_reg, _tuner_en_reg, \
1172 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1173 _pcw_chg_reg) \
1174 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
1175 _rst_bar_mask, _pcwbits, _pcwibits, _pd_reg, \
1176 _pd_shift, _tuner_reg, _tuner_en_reg, \
1177 _tuner_en_bit, _pcw_reg, _pcw_shift, \
1178 _pcw_chg_reg, NULL)
1179
1180static const struct mtk_pll_data plls[] = {
1181 PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, BIT(0),
1182 PLL_AO, 0, 22, 8, 0x0204, 24, 0, 0, 0, 0x0204, 0, 0),
1183 PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, BIT(0),
1184 PLL_AO, 0, 22, 8, 0x0214, 24, 0, 0, 0, 0x0214, 0, 0),
1185 PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, BIT(0),
1186 PLL_AO, 0, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0, 0),
1187 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, BIT(0),
1188 (HAVE_RST_BAR), BIT(24), 22, 8, 0x0234, 24, 0, 0, 0,
1189 0x0234, 0, 0),
1190 PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, BIT(0),
1191 (HAVE_RST_BAR), BIT(24), 22, 8, 0x0244, 24,
1192 0, 0, 0, 0x0244, 0, 0),
1193 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, BIT(0),
1194 0, 0, 22, 8, 0x0254, 24, 0, 0, 0, 0x0254, 0, 0),
1195 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, BIT(0),
1196 0, 0, 22, 8, 0x0264, 24, 0, 0, 0, 0x0264, 0, 0),
1197 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, BIT(0),
1198 0, 0, 22, 8, 0x0274, 24, 0, 0, 0, 0x0274, 0, 0),
1199 PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, BIT(0),
1200 (HAVE_RST_BAR), BIT(23), 22, 8, 0x02b4, 24,
1201 0, 0, 0, 0x02b4, 0, 0),
1202 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, BIT(0),
1203 (HAVE_RST_BAR), BIT(23), 22, 8, 0x0284, 24,
1204 0, 0, 0, 0x0284, 0, 0),
1205 PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, BIT(0),
1206 0, 0, 32, 8, 0x02C0, 1, 0, 0x14, 0, 0x02C4, 0, 0x2C0),
1207 PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, BIT(0),
1208 0, 0, 32, 8, 0x02D4, 1, 0, 0x14, 1, 0x02D8, 0, 0x02D4),
1209};
1210
1211static int clk_mt6779_apmixed_probe(struct platform_device *pdev)
1212{
1213 struct clk_onecell_data *clk_data;
1214 struct device_node *node = pdev->dev.of_node;
1215
1216 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1217
1218 mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1219
1220 mtk_clk_register_gates(node, apmixed_clks,
1221 ARRAY_SIZE(apmixed_clks), clk_data);
1222
1223 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1224}
1225
1226static int clk_mt6779_top_probe(struct platform_device *pdev)
1227{
1228 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1229 void __iomem *base;
1230 struct clk_onecell_data *clk_data;
1231 struct device_node *node = pdev->dev.of_node;
1232
1233 base = devm_ioremap_resource(&pdev->dev, res);
1234 if (IS_ERR(base))
1235 return PTR_ERR(base);
1236
1237 clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1238
1239 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1240 clk_data);
1241
1242 mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
1243
1244 mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes),
1245 node, &mt6779_clk_lock, clk_data);
1246
1247 mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes),
1248 base, &mt6779_clk_lock, clk_data);
1249
1250 mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
1251 base, &mt6779_clk_lock, clk_data);
1252
1253 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1254}
1255
1256static int clk_mt6779_infra_probe(struct platform_device *pdev)
1257{
1258 struct clk_onecell_data *clk_data;
1259 struct device_node *node = pdev->dev.of_node;
1260
1261 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1262
1263 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
1264 clk_data);
1265
1266 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1267}
1268
1269static const struct of_device_id of_match_clk_mt6779[] = {
1270 {
1271 .compatible = "mediatek,mt6779-apmixed",
1272 .data = clk_mt6779_apmixed_probe,
1273 }, {
1274 .compatible = "mediatek,mt6779-topckgen",
1275 .data = clk_mt6779_top_probe,
1276 }, {
1277 .compatible = "mediatek,mt6779-infracfg_ao",
1278 .data = clk_mt6779_infra_probe,
1279 }, {
1280 /* sentinel */
1281 }
1282};
1283
1284static int clk_mt6779_probe(struct platform_device *pdev)
1285{
1286 int (*clk_probe)(struct platform_device *pdev);
1287 int r;
1288
1289 clk_probe = of_device_get_match_data(&pdev->dev);
1290 if (!clk_probe)
1291 return -EINVAL;
1292
1293 r = clk_probe(pdev);
1294 if (r)
1295 dev_err(&pdev->dev,
1296 "could not register clock provider: %s: %d\n",
1297 pdev->name, r);
1298
1299 return r;
1300}
1301
1302static struct platform_driver clk_mt6779_drv = {
1303 .probe = clk_mt6779_probe,
1304 .driver = {
1305 .name = "clk-mt6779",
1306 .of_match_table = of_match_clk_mt6779,
1307 },
1308};
1309
1310static int __init clk_mt6779_init(void)
1311{
1312 return platform_driver_register(&clk_mt6779_drv);
1313}
1314
1315arch_initcall(clk_mt6779_init);
diff --git a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
index 99a6b020833e..37b4162c5882 100644
--- a/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
+++ b/drivers/clk/mediatek/clk-mt8183-mfgcfg.c
@@ -5,6 +5,7 @@
5 5
6#include <linux/clk-provider.h> 6#include <linux/clk-provider.h>
7#include <linux/platform_device.h> 7#include <linux/platform_device.h>
8#include <linux/pm_runtime.h>
8 9
9#include "clk-mtk.h" 10#include "clk-mtk.h"
10#include "clk-gate.h" 11#include "clk-gate.h"
@@ -30,10 +31,12 @@ static int clk_mt8183_mfg_probe(struct platform_device *pdev)
30 struct clk_onecell_data *clk_data; 31 struct clk_onecell_data *clk_data;
31 struct device_node *node = pdev->dev.of_node; 32 struct device_node *node = pdev->dev.of_node;
32 33
34 pm_runtime_enable(&pdev->dev);
35
33 clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK); 36 clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
34 37
35 mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks), 38 mtk_clk_register_gates_with_dev(node, mfg_clks, ARRAY_SIZE(mfg_clks),
36 clk_data); 39 clk_data, &pdev->dev);
37 40
38 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 41 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
39} 42}
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 1aa5f4059251..7e7452e56694 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -17,6 +17,9 @@
17 17
18#include <dt-bindings/clock/mt8183-clk.h> 18#include <dt-bindings/clock/mt8183-clk.h>
19 19
20/* Infra global controller reset set register */
21#define INFRA_RST0_SET_OFFSET 0x120
22
20static DEFINE_SPINLOCK(mt8183_clk_lock); 23static DEFINE_SPINLOCK(mt8183_clk_lock);
21 24
22static const struct mtk_fixed_clk top_fixed_clks[] = { 25static const struct mtk_fixed_clk top_fixed_clks[] = {
@@ -999,6 +1002,20 @@ static const struct mtk_gate infra_clks[] = {
999 "msdc50_0_sel", 24), 1002 "msdc50_0_sel", 24),
1000}; 1003};
1001 1004
1005static const struct mtk_gate_regs peri_cg_regs = {
1006 .set_ofs = 0x20c,
1007 .clr_ofs = 0x20c,
1008 .sta_ofs = 0x20c,
1009};
1010
1011#define GATE_PERI(_id, _name, _parent, _shift) \
1012 GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \
1013 &mtk_clk_gate_ops_no_setclr_inv)
1014
1015static const struct mtk_gate peri_clks[] = {
1016 GATE_PERI(CLK_PERI_AXI, "peri_axi", "axi_sel", 31),
1017};
1018
1002static const struct mtk_gate_regs apmixed_cg_regs = { 1019static const struct mtk_gate_regs apmixed_cg_regs = {
1003 .set_ofs = 0x20, 1020 .set_ofs = 0x20,
1004 .clr_ofs = 0x20, 1021 .clr_ofs = 0x20,
@@ -1185,12 +1202,36 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
1185{ 1202{
1186 struct clk_onecell_data *clk_data; 1203 struct clk_onecell_data *clk_data;
1187 struct device_node *node = pdev->dev.of_node; 1204 struct device_node *node = pdev->dev.of_node;
1205 int r;
1188 1206
1189 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); 1207 clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1190 1208
1191 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), 1209 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
1192 clk_data); 1210 clk_data);
1193 1211
1212 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1213 if (r) {
1214 dev_err(&pdev->dev,
1215 "%s(): could not register clock provider: %d\n",
1216 __func__, r);
1217 return r;
1218 }
1219
1220 mtk_register_reset_controller_set_clr(node, 4, INFRA_RST0_SET_OFFSET);
1221
1222 return r;
1223}
1224
1225static int clk_mt8183_peri_probe(struct platform_device *pdev)
1226{
1227 struct clk_onecell_data *clk_data;
1228 struct device_node *node = pdev->dev.of_node;
1229
1230 clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
1231
1232 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
1233 clk_data);
1234
1194 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); 1235 return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1195} 1236}
1196 1237
@@ -1224,6 +1265,9 @@ static const struct of_device_id of_match_clk_mt8183[] = {
1224 .compatible = "mediatek,mt8183-infracfg", 1265 .compatible = "mediatek,mt8183-infracfg",
1225 .data = clk_mt8183_infra_probe, 1266 .data = clk_mt8183_infra_probe,
1226 }, { 1267 }, {
1268 .compatible = "mediatek,mt8183-pericfg",
1269 .data = clk_mt8183_peri_probe,
1270 }, {
1227 .compatible = "mediatek,mt8183-mcucfg", 1271 .compatible = "mediatek,mt8183-mcucfg",
1228 .data = clk_mt8183_mcu_probe, 1272 .data = clk_mt8183_mcu_probe,
1229 }, { 1273 }, {
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index d28790c74919..cec1c8a27211 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -12,6 +12,7 @@
12#include <linux/delay.h> 12#include <linux/delay.h>
13#include <linux/clkdev.h> 13#include <linux/clkdev.h>
14#include <linux/mfd/syscon.h> 14#include <linux/mfd/syscon.h>
15#include <linux/device.h>
15 16
16#include "clk-mtk.h" 17#include "clk-mtk.h"
17#include "clk-gate.h" 18#include "clk-gate.h"
@@ -93,9 +94,10 @@ void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
93 } 94 }
94} 95}
95 96
96int mtk_clk_register_gates(struct device_node *node, 97int mtk_clk_register_gates_with_dev(struct device_node *node,
97 const struct mtk_gate *clks, 98 const struct mtk_gate *clks,
98 int num, struct clk_onecell_data *clk_data) 99 int num, struct clk_onecell_data *clk_data,
100 struct device *dev)
99{ 101{
100 int i; 102 int i;
101 struct clk *clk; 103 struct clk *clk;
@@ -122,7 +124,7 @@ int mtk_clk_register_gates(struct device_node *node,
122 gate->regs->set_ofs, 124 gate->regs->set_ofs,
123 gate->regs->clr_ofs, 125 gate->regs->clr_ofs,
124 gate->regs->sta_ofs, 126 gate->regs->sta_ofs,
125 gate->shift, gate->ops, gate->flags); 127 gate->shift, gate->ops, gate->flags, dev);
126 128
127 if (IS_ERR(clk)) { 129 if (IS_ERR(clk)) {
128 pr_err("Failed to register clk %s: %ld\n", 130 pr_err("Failed to register clk %s: %ld\n",
@@ -136,6 +138,14 @@ int mtk_clk_register_gates(struct device_node *node,
136 return 0; 138 return 0;
137} 139}
138 140
141int mtk_clk_register_gates(struct device_node *node,
142 const struct mtk_gate *clks,
143 int num, struct clk_onecell_data *clk_data)
144{
145 return mtk_clk_register_gates_with_dev(node,
146 clks, num, clk_data, NULL);
147}
148
139struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, 149struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
140 void __iomem *base, spinlock_t *lock) 150 void __iomem *base, spinlock_t *lock)
141{ 151{
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 733a11d1de94..c3d6756b0c7e 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -169,6 +169,11 @@ int mtk_clk_register_gates(struct device_node *node,
169 const struct mtk_gate *clks, int num, 169 const struct mtk_gate *clks, int num,
170 struct clk_onecell_data *clk_data); 170 struct clk_onecell_data *clk_data);
171 171
172int mtk_clk_register_gates_with_dev(struct device_node *node,
173 const struct mtk_gate *clks,
174 int num, struct clk_onecell_data *clk_data,
175 struct device *dev);
176
172struct mtk_clk_divider { 177struct mtk_clk_divider {
173 int id; 178 int id;
174 const char *name; 179 const char *name;
@@ -240,4 +245,7 @@ struct clk *mtk_clk_register_ref2usb_tx(const char *name,
240void mtk_register_reset_controller(struct device_node *np, 245void mtk_register_reset_controller(struct device_node *np,
241 unsigned int num_regs, int regofs); 246 unsigned int num_regs, int regofs);
242 247
248void mtk_register_reset_controller_set_clr(struct device_node *np,
249 unsigned int num_regs, int regofs);
250
243#endif /* __DRV_CLK_MTK_H */ 251#endif /* __DRV_CLK_MTK_H */
diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index d8376b92349e..cb939c071b0c 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -19,6 +19,24 @@ struct mtk_reset {
19 struct reset_controller_dev rcdev; 19 struct reset_controller_dev rcdev;
20}; 20};
21 21
22static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
23 unsigned long id)
24{
25 struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
26 unsigned int reg = data->regofs + ((id / 32) << 4);
27
28 return regmap_write(data->regmap, reg, 1);
29}
30
31static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
32 unsigned long id)
33{
34 struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
35 unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4;
36
37 return regmap_write(data->regmap, reg, 1);
38}
39
22static int mtk_reset_assert(struct reset_controller_dev *rcdev, 40static int mtk_reset_assert(struct reset_controller_dev *rcdev,
23 unsigned long id) 41 unsigned long id)
24{ 42{
@@ -49,14 +67,32 @@ static int mtk_reset(struct reset_controller_dev *rcdev,
49 return mtk_reset_deassert(rcdev, id); 67 return mtk_reset_deassert(rcdev, id);
50} 68}
51 69
70static int mtk_reset_set_clr(struct reset_controller_dev *rcdev,
71 unsigned long id)
72{
73 int ret;
74
75 ret = mtk_reset_assert_set_clr(rcdev, id);
76 if (ret)
77 return ret;
78 return mtk_reset_deassert_set_clr(rcdev, id);
79}
80
52static const struct reset_control_ops mtk_reset_ops = { 81static const struct reset_control_ops mtk_reset_ops = {
53 .assert = mtk_reset_assert, 82 .assert = mtk_reset_assert,
54 .deassert = mtk_reset_deassert, 83 .deassert = mtk_reset_deassert,
55 .reset = mtk_reset, 84 .reset = mtk_reset,
56}; 85};
57 86
58void mtk_register_reset_controller(struct device_node *np, 87static const struct reset_control_ops mtk_reset_ops_set_clr = {
59 unsigned int num_regs, int regofs) 88 .assert = mtk_reset_assert_set_clr,
89 .deassert = mtk_reset_deassert_set_clr,
90 .reset = mtk_reset_set_clr,
91};
92
93static void mtk_register_reset_controller_common(struct device_node *np,
94 unsigned int num_regs, int regofs,
95 const struct reset_control_ops *reset_ops)
60{ 96{
61 struct mtk_reset *data; 97 struct mtk_reset *data;
62 int ret; 98 int ret;
@@ -77,7 +113,7 @@ void mtk_register_reset_controller(struct device_node *np,
77 data->regofs = regofs; 113 data->regofs = regofs;
78 data->rcdev.owner = THIS_MODULE; 114 data->rcdev.owner = THIS_MODULE;
79 data->rcdev.nr_resets = num_regs * 32; 115 data->rcdev.nr_resets = num_regs * 32;
80 data->rcdev.ops = &mtk_reset_ops; 116 data->rcdev.ops = reset_ops;
81 data->rcdev.of_node = np; 117 data->rcdev.of_node = np;
82 118
83 ret = reset_controller_register(&data->rcdev); 119 ret = reset_controller_register(&data->rcdev);
@@ -87,3 +123,17 @@ void mtk_register_reset_controller(struct device_node *np,
87 return; 123 return;
88 } 124 }
89} 125}
126
127void mtk_register_reset_controller(struct device_node *np,
128 unsigned int num_regs, int regofs)
129{
130 mtk_register_reset_controller_common(np, num_regs, regofs,
131 &mtk_reset_ops);
132}
133
134void mtk_register_reset_controller_set_clr(struct device_node *np,
135 unsigned int num_regs, int regofs)
136{
137 mtk_register_reset_controller_common(np, num_regs, regofs,
138 &mtk_reset_ops_set_clr);
139}
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index b09f6ded0a30..415e6906a113 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -8,6 +8,9 @@ config MVEBU_CLK_CPU
8config MVEBU_CLK_COREDIV 8config MVEBU_CLK_COREDIV
9 bool 9 bool
10 10
11config ARMADA_AP_CP_HELPER
12 bool
13
11config ARMADA_370_CLK 14config ARMADA_370_CLK
12 bool 15 bool
13 select MVEBU_CLK_COMMON 16 select MVEBU_CLK_COMMON
@@ -35,9 +38,14 @@ config ARMADA_XP_CLK
35 38
36config ARMADA_AP806_SYSCON 39config ARMADA_AP806_SYSCON
37 bool 40 bool
41 select ARMADA_AP_CP_HELPER
42
43config ARMADA_AP_CPU_CLK
44 bool
38 45
39config ARMADA_CP110_SYSCON 46config ARMADA_CP110_SYSCON
40 bool 47 bool
48 select ARMADA_AP_CP_HELPER
41 49
42config DOVE_CLK 50config DOVE_CLK
43 bool 51 bool
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 93ac3685271f..04464cef0f06 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -2,6 +2,7 @@
2obj-$(CONFIG_MVEBU_CLK_COMMON) += common.o 2obj-$(CONFIG_MVEBU_CLK_COMMON) += common.o
3obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o 3obj-$(CONFIG_MVEBU_CLK_CPU) += clk-cpu.o
4obj-$(CONFIG_MVEBU_CLK_COREDIV) += clk-corediv.o 4obj-$(CONFIG_MVEBU_CLK_COREDIV) += clk-corediv.o
5obj-$(CONFIG_ARMADA_AP_CP_HELPER) += armada_ap_cp_helper.o
5 6
6obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o 7obj-$(CONFIG_ARMADA_370_CLK) += armada-370.o
7obj-$(CONFIG_ARMADA_375_CLK) += armada-375.o 8obj-$(CONFIG_ARMADA_375_CLK) += armada-375.o
@@ -12,6 +13,7 @@ obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-tbg.o
12obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-periph.o 13obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-periph.o
13obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o mv98dx3236.o 14obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o mv98dx3236.o
14obj-$(CONFIG_ARMADA_AP806_SYSCON) += ap806-system-controller.o 15obj-$(CONFIG_ARMADA_AP806_SYSCON) += ap806-system-controller.o
16obj-$(CONFIG_ARMADA_AP_CPU_CLK) += ap-cpu-clk.o
15obj-$(CONFIG_ARMADA_CP110_SYSCON) += cp110-system-controller.o 17obj-$(CONFIG_ARMADA_CP110_SYSCON) += cp110-system-controller.o
16obj-$(CONFIG_DOVE_CLK) += dove.o dove-divider.o 18obj-$(CONFIG_DOVE_CLK) += dove.o dove-divider.o
17obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o 19obj-$(CONFIG_KIRKWOOD_CLK) += kirkwood.o
diff --git a/drivers/clk/mvebu/ap-cpu-clk.c b/drivers/clk/mvebu/ap-cpu-clk.c
new file mode 100644
index 000000000000..af5e5acad370
--- /dev/null
+++ b/drivers/clk/mvebu/ap-cpu-clk.c
@@ -0,0 +1,356 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Marvell Armada AP CPU Clock Controller
4 *
5 * Copyright (C) 2018 Marvell
6 *
7 * Omri Itach <omrii@marvell.com>
8 * Gregory Clement <gregory.clement@bootlin.com>
9 */
10
11#define pr_fmt(fmt) "ap-cpu-clk: " fmt
12
13#include <linux/clk-provider.h>
14#include <linux/clk.h>
15#include <linux/mfd/syscon.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_platform.h>
19#include <linux/platform_device.h>
20#include <linux/regmap.h>
21#include "armada_ap_cp_helper.h"
22
23#define AP806_CPU_CLUSTER0 0
24#define AP806_CPU_CLUSTER1 1
25#define AP806_CPUS_PER_CLUSTER 2
26#define APN806_CPU1_MASK 0x1
27
28#define APN806_CLUSTER_NUM_OFFSET 8
29#define APN806_CLUSTER_NUM_MASK BIT(APN806_CLUSTER_NUM_OFFSET)
30
31#define APN806_MAX_DIVIDER 32
32
33/**
34 * struct cpu_dfs_regs: CPU DFS register mapping
35 * @divider_reg: full integer ratio from PLL frequency to CPU clock frequency
36 * @force_reg: request to force new ratio regardless of relation to other clocks
37 * @ratio_reg: central request to switch ratios
38 */
39struct cpu_dfs_regs {
40 unsigned int divider_reg;
41 unsigned int force_reg;
42 unsigned int ratio_reg;
43 unsigned int ratio_state_reg;
44 unsigned int divider_mask;
45 unsigned int cluster_offset;
46 unsigned int force_mask;
47 int divider_offset;
48 int divider_ratio;
49 int ratio_offset;
50 int ratio_state_offset;
51 int ratio_state_cluster_offset;
52};
53
54/* AP806 CPU DFS register mapping*/
55#define AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET 0x278
56#define AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET 0x280
57#define AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET 0x284
58#define AP806_CA72MP2_0_PLL_SR_REG_OFFSET 0xC94
59
60#define AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET 0x14
61#define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET 0
62#define AP806_PLL_CR_CPU_CLK_DIV_RATIO 0
63#define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \
64 (0x3f << AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
65#define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET 24
66#define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK \
67 (0x1 << AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET)
68#define AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET 16
69#define AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET 0
70#define AP806_CA72MP2_0_PLL_RATIO_STATE 11
71
72#define STATUS_POLL_PERIOD_US 1
73#define STATUS_POLL_TIMEOUT_US 1000000
74
75#define to_ap_cpu_clk(_hw) container_of(_hw, struct ap_cpu_clk, hw)
76
77static const struct cpu_dfs_regs ap806_dfs_regs = {
78 .divider_reg = AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET,
79 .force_reg = AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET,
80 .ratio_reg = AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET,
81 .ratio_state_reg = AP806_CA72MP2_0_PLL_SR_REG_OFFSET,
82 .divider_mask = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK,
83 .cluster_offset = AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET,
84 .force_mask = AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK,
85 .divider_offset = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET,
86 .divider_ratio = AP806_PLL_CR_CPU_CLK_DIV_RATIO,
87 .ratio_offset = AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET,
88 .ratio_state_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET,
89 .ratio_state_cluster_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET,
90};
91
92/* AP807 CPU DFS register mapping */
93#define AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET 0x278
94#define AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET 0x27c
95#define AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET 0xc98
96#define AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET 0x8
97#define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET 18
98#define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \
99 (0x3f << AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
100#define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET 12
101#define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK \
102 (0x3f << AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET)
103#define AP807_PLL_CR_CPU_CLK_DIV_RATIO 3
104#define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET 0
105#define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK \
106 (0x3 << AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET)
107#define AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET 6
108#define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET 20
109#define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET 3
110
111static const struct cpu_dfs_regs ap807_dfs_regs = {
112 .divider_reg = AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET,
113 .force_reg = AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET,
114 .ratio_reg = AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET,
115 .ratio_state_reg = AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET,
116 .divider_mask = AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK,
117 .cluster_offset = AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET,
118 .force_mask = AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK,
119 .divider_offset = AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET,
120 .divider_ratio = AP807_PLL_CR_CPU_CLK_DIV_RATIO,
121 .ratio_offset = AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET,
122 .ratio_state_offset = AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET,
123 .ratio_state_cluster_offset =
124 AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET
125};
126
127/*
128 * struct ap806_clk: CPU cluster clock controller instance
129 * @cluster: Cluster clock controller index
130 * @clk_name: Cluster clock controller name
131 * @dev : Cluster clock device
132 * @hw: HW specific structure of Cluster clock controller
133 * @pll_cr_base: CA72MP2 Register base (Device Sample at Reset register)
134 */
135struct ap_cpu_clk {
136 unsigned int cluster;
137 const char *clk_name;
138 struct device *dev;
139 struct clk_hw hw;
140 struct regmap *pll_cr_base;
141 const struct cpu_dfs_regs *pll_regs;
142};
143
144static unsigned long ap_cpu_clk_recalc_rate(struct clk_hw *hw,
145 unsigned long parent_rate)
146{
147 struct ap_cpu_clk *clk = to_ap_cpu_clk(hw);
148 unsigned int cpu_clkdiv_reg;
149 int cpu_clkdiv_ratio;
150
151 cpu_clkdiv_reg = clk->pll_regs->divider_reg +
152 (clk->cluster * clk->pll_regs->cluster_offset);
153 regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &cpu_clkdiv_ratio);
154 cpu_clkdiv_ratio &= clk->pll_regs->divider_mask;
155 cpu_clkdiv_ratio >>= clk->pll_regs->divider_offset;
156
157 return parent_rate / cpu_clkdiv_ratio;
158}
159
160static int ap_cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
161 unsigned long parent_rate)
162{
163 struct ap_cpu_clk *clk = to_ap_cpu_clk(hw);
164 int ret, reg, divider = parent_rate / rate;
165 unsigned int cpu_clkdiv_reg, cpu_force_reg, cpu_ratio_reg, stable_bit;
166
167 cpu_clkdiv_reg = clk->pll_regs->divider_reg +
168 (clk->cluster * clk->pll_regs->cluster_offset);
169 cpu_force_reg = clk->pll_regs->force_reg +
170 (clk->cluster * clk->pll_regs->cluster_offset);
171 cpu_ratio_reg = clk->pll_regs->ratio_reg +
172 (clk->cluster * clk->pll_regs->cluster_offset);
173
174 regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &reg);
175 reg &= ~(clk->pll_regs->divider_mask);
176 reg |= (divider << clk->pll_regs->divider_offset);
177
178 /*
179 * AP807 CPU divider has two channels with ratio 1:3 and divider_ratio
180 * is 1. Otherwise, in the case of the AP806, divider_ratio is 0.
181 */
182 if (clk->pll_regs->divider_ratio) {
183 reg &= ~(AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK);
184 reg |= ((divider * clk->pll_regs->divider_ratio) <<
185 AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET);
186 }
187 regmap_write(clk->pll_cr_base, cpu_clkdiv_reg, reg);
188
189
190 regmap_update_bits(clk->pll_cr_base, cpu_force_reg,
191 clk->pll_regs->force_mask,
192 clk->pll_regs->force_mask);
193
194 regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg,
195 BIT(clk->pll_regs->ratio_offset),
196 BIT(clk->pll_regs->ratio_offset));
197
198 stable_bit = BIT(clk->pll_regs->ratio_state_offset +
199 clk->cluster *
200 clk->pll_regs->ratio_state_cluster_offset),
201 ret = regmap_read_poll_timeout(clk->pll_cr_base,
202 clk->pll_regs->ratio_state_reg, reg,
203 reg & stable_bit, STATUS_POLL_PERIOD_US,
204 STATUS_POLL_TIMEOUT_US);
205 if (ret)
206 return ret;
207
208 regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg,
209 BIT(clk->pll_regs->ratio_offset), 0);
210
211 return 0;
212}
213
214static long ap_cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
215 unsigned long *parent_rate)
216{
217 int divider = *parent_rate / rate;
218
219 divider = min(divider, APN806_MAX_DIVIDER);
220
221 return *parent_rate / divider;
222}
223
224static const struct clk_ops ap_cpu_clk_ops = {
225 .recalc_rate = ap_cpu_clk_recalc_rate,
226 .round_rate = ap_cpu_clk_round_rate,
227 .set_rate = ap_cpu_clk_set_rate,
228};
229
230static int ap_cpu_clock_probe(struct platform_device *pdev)
231{
232 int ret, nclusters = 0, cluster_index = 0;
233 struct device *dev = &pdev->dev;
234 struct device_node *dn, *np = dev->of_node;
235 struct clk_hw_onecell_data *ap_cpu_data;
236 struct ap_cpu_clk *ap_cpu_clk;
237 struct regmap *regmap;
238
239 regmap = syscon_node_to_regmap(np->parent);
240 if (IS_ERR(regmap)) {
241 pr_err("cannot get pll_cr_base regmap\n");
242 return PTR_ERR(regmap);
243 }
244
245 /*
246 * AP806 has 4 cpus and DFS for AP806 is controlled per
247 * cluster (2 CPUs per cluster), cpu0 and cpu1 are fixed to
248 * cluster0 while cpu2 and cpu3 are fixed to cluster1 whether
249 * they are enabled or not. Since cpu0 is the boot cpu, then
250 * cluster0 must exist. If cpu2 or cpu3 is enabled, cluster1
251 * will exist and the cluster number is 2; otherwise the
252 * cluster number is 1.
253 */
254 nclusters = 1;
255 for_each_of_cpu_node(dn) {
256 int cpu, err;
257
258 err = of_property_read_u32(dn, "reg", &cpu);
259 if (WARN_ON(err))
260 return err;
261
262 /* If cpu2 or cpu3 is enabled */
263 if (cpu & APN806_CLUSTER_NUM_MASK) {
264 nclusters = 2;
265 break;
266 }
267 }
268 /*
269 * DFS for AP806 is controlled per cluster (2 CPUs per cluster),
270 * so allocate structs per cluster
271 */
272 ap_cpu_clk = devm_kcalloc(dev, nclusters, sizeof(*ap_cpu_clk),
273 GFP_KERNEL);
274 if (!ap_cpu_clk)
275 return -ENOMEM;
276
277 ap_cpu_data = devm_kzalloc(dev, sizeof(*ap_cpu_data) +
278 sizeof(struct clk_hw *) * nclusters,
279 GFP_KERNEL);
280 if (!ap_cpu_data)
281 return -ENOMEM;
282
283 for_each_of_cpu_node(dn) {
284 char *clk_name = "cpu-cluster-0";
285 struct clk_init_data init;
286 const char *parent_name;
287 struct clk *parent;
288 int cpu, err;
289
290 err = of_property_read_u32(dn, "reg", &cpu);
291 if (WARN_ON(err))
292 return err;
293
294 cluster_index = cpu & APN806_CLUSTER_NUM_MASK;
295 cluster_index >>= APN806_CLUSTER_NUM_OFFSET;
296
297 /* Initialize once for one cluster */
298 if (ap_cpu_data->hws[cluster_index])
299 continue;
300
301 parent = of_clk_get(np, cluster_index);
302 if (IS_ERR(parent)) {
303 dev_err(dev, "Could not get the clock parent\n");
304 return -EINVAL;
305 }
306 parent_name = __clk_get_name(parent);
307 clk_name[12] += cluster_index;
308 ap_cpu_clk[cluster_index].clk_name =
309 ap_cp_unique_name(dev, np->parent, clk_name);
310 ap_cpu_clk[cluster_index].cluster = cluster_index;
311 ap_cpu_clk[cluster_index].pll_cr_base = regmap;
312 ap_cpu_clk[cluster_index].hw.init = &init;
313 ap_cpu_clk[cluster_index].dev = dev;
314 ap_cpu_clk[cluster_index].pll_regs = of_device_get_match_data(&pdev->dev);
315
316 init.name = ap_cpu_clk[cluster_index].clk_name;
317 init.ops = &ap_cpu_clk_ops;
318 init.num_parents = 1;
319 init.parent_names = &parent_name;
320
321 ret = devm_clk_hw_register(dev, &ap_cpu_clk[cluster_index].hw);
322 if (ret)
323 return ret;
324 ap_cpu_data->hws[cluster_index] = &ap_cpu_clk[cluster_index].hw;
325 }
326
327 ap_cpu_data->num = cluster_index + 1;
328
329 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, ap_cpu_data);
330 if (ret)
331 dev_err(dev, "failed to register OF clock provider\n");
332
333 return ret;
334}
335
336static const struct of_device_id ap_cpu_clock_of_match[] = {
337 {
338 .compatible = "marvell,ap806-cpu-clock",
339 .data = &ap806_dfs_regs,
340 },
341 {
342 .compatible = "marvell,ap807-cpu-clock",
343 .data = &ap807_dfs_regs,
344 },
345 { }
346};
347
348static struct platform_driver ap_cpu_clock_driver = {
349 .probe = ap_cpu_clock_probe,
350 .driver = {
351 .name = "marvell-ap-cpu-clock",
352 .of_match_table = ap_cpu_clock_of_match,
353 .suppress_bind_attrs = true,
354 },
355};
356builtin_platform_driver(ap_cpu_clock_driver);
diff --git a/drivers/clk/mvebu/ap806-system-controller.c b/drivers/clk/mvebu/ap806-system-controller.c
index ea54a874bbda..948bd1e71aea 100644
--- a/drivers/clk/mvebu/ap806-system-controller.c
+++ b/drivers/clk/mvebu/ap806-system-controller.c
@@ -10,18 +10,18 @@
10 10
11#define pr_fmt(fmt) "ap806-system-controller: " fmt 11#define pr_fmt(fmt) "ap806-system-controller: " fmt
12 12
13#include "armada_ap_cp_helper.h"
13#include <linux/clk-provider.h> 14#include <linux/clk-provider.h>
14#include <linux/mfd/syscon.h> 15#include <linux/mfd/syscon.h>
15#include <linux/init.h> 16#include <linux/init.h>
16#include <linux/of.h> 17#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19#include <linux/regmap.h> 19#include <linux/regmap.h>
20 20
21#define AP806_SAR_REG 0x400 21#define AP806_SAR_REG 0x400
22#define AP806_SAR_CLKFREQ_MODE_MASK 0x1f 22#define AP806_SAR_CLKFREQ_MODE_MASK 0x1f
23 23
24#define AP806_CLK_NUM 5 24#define AP806_CLK_NUM 6
25 25
26static struct clk *ap806_clks[AP806_CLK_NUM]; 26static struct clk *ap806_clks[AP806_CLK_NUM];
27 27
@@ -30,86 +30,149 @@ static struct clk_onecell_data ap806_clk_data = {
30 .clk_num = AP806_CLK_NUM, 30 .clk_num = AP806_CLK_NUM,
31}; 31};
32 32
33static char *ap806_unique_name(struct device *dev, struct device_node *np, 33static int ap806_get_sar_clocks(unsigned int freq_mode,
34 char *name) 34 unsigned int *cpuclk_freq,
35 unsigned int *dclk_freq)
35{ 36{
36 const __be32 *reg;
37 u64 addr;
38
39 reg = of_get_property(np, "reg", NULL);
40 addr = of_translate_address(np, reg);
41 return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s",
42 (unsigned long long)addr, name);
43}
44
45static int ap806_syscon_common_probe(struct platform_device *pdev,
46 struct device_node *syscon_node)
47{
48 unsigned int freq_mode, cpuclk_freq;
49 const char *name, *fixedclk_name;
50 struct device *dev = &pdev->dev;
51 struct device_node *np = dev->of_node;
52 struct regmap *regmap;
53 u32 reg;
54 int ret;
55
56 regmap = syscon_node_to_regmap(syscon_node);
57 if (IS_ERR(regmap)) {
58 dev_err(dev, "cannot get regmap\n");
59 return PTR_ERR(regmap);
60 }
61
62 ret = regmap_read(regmap, AP806_SAR_REG, &reg);
63 if (ret) {
64 dev_err(dev, "cannot read from regmap\n");
65 return ret;
66 }
67
68 freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
69 switch (freq_mode) { 37 switch (freq_mode) {
70 case 0x0: 38 case 0x0:
39 *cpuclk_freq = 2000;
40 *dclk_freq = 600;
41 break;
71 case 0x1: 42 case 0x1:
72 cpuclk_freq = 2000; 43 *cpuclk_freq = 2000;
44 *dclk_freq = 525;
73 break; 45 break;
74 case 0x6: 46 case 0x6:
47 *cpuclk_freq = 1800;
48 *dclk_freq = 600;
49 break;
75 case 0x7: 50 case 0x7:
76 cpuclk_freq = 1800; 51 *cpuclk_freq = 1800;
52 *dclk_freq = 525;
77 break; 53 break;
78 case 0x4: 54 case 0x4:
55 *cpuclk_freq = 1600;
56 *dclk_freq = 400;
57 break;
79 case 0xB: 58 case 0xB:
59 *cpuclk_freq = 1600;
60 *dclk_freq = 450;
61 break;
80 case 0xD: 62 case 0xD:
81 cpuclk_freq = 1600; 63 *cpuclk_freq = 1600;
64 *dclk_freq = 525;
82 break; 65 break;
83 case 0x1a: 66 case 0x1a:
84 cpuclk_freq = 1400; 67 *cpuclk_freq = 1400;
68 *dclk_freq = 400;
85 break; 69 break;
86 case 0x14: 70 case 0x14:
71 *cpuclk_freq = 1300;
72 *dclk_freq = 400;
73 break;
87 case 0x17: 74 case 0x17:
88 cpuclk_freq = 1300; 75 *cpuclk_freq = 1300;
76 *dclk_freq = 325;
89 break; 77 break;
90 case 0x19: 78 case 0x19:
91 cpuclk_freq = 1200; 79 *cpuclk_freq = 1200;
80 *dclk_freq = 400;
92 break; 81 break;
93 case 0x13: 82 case 0x13:
83 *cpuclk_freq = 1000;
84 *dclk_freq = 325;
85 break;
94 case 0x1d: 86 case 0x1d:
95 cpuclk_freq = 1000; 87 *cpuclk_freq = 1000;
88 *dclk_freq = 400;
96 break; 89 break;
97 case 0x1c: 90 case 0x1c:
98 cpuclk_freq = 800; 91 *cpuclk_freq = 800;
92 *dclk_freq = 400;
99 break; 93 break;
100 case 0x1b: 94 case 0x1b:
101 cpuclk_freq = 600; 95 *cpuclk_freq = 600;
96 *dclk_freq = 400;
102 break; 97 break;
103 default: 98 default:
104 dev_err(dev, "invalid SAR value\n");
105 return -EINVAL; 99 return -EINVAL;
106 } 100 }
107 101
102 return 0;
103}
104
105static int ap807_get_sar_clocks(unsigned int freq_mode,
106 unsigned int *cpuclk_freq,
107 unsigned int *dclk_freq)
108{
109 switch (freq_mode) {
110 case 0x0:
111 *cpuclk_freq = 2000;
112 *dclk_freq = 1200;
113 break;
114 case 0x6:
115 *cpuclk_freq = 2200;
116 *dclk_freq = 1200;
117 break;
118 case 0xD:
119 *cpuclk_freq = 1600;
120 *dclk_freq = 1200;
121 break;
122 default:
123 return -EINVAL;
124 }
125
126 return 0;
127}
128
129static int ap806_syscon_common_probe(struct platform_device *pdev,
130 struct device_node *syscon_node)
131{
132 unsigned int freq_mode, cpuclk_freq, dclk_freq;
133 const char *name, *fixedclk_name;
134 struct device *dev = &pdev->dev;
135 struct device_node *np = dev->of_node;
136 struct regmap *regmap;
137 u32 reg;
138 int ret;
139
140 regmap = syscon_node_to_regmap(syscon_node);
141 if (IS_ERR(regmap)) {
142 dev_err(dev, "cannot get regmap\n");
143 return PTR_ERR(regmap);
144 }
145
146 ret = regmap_read(regmap, AP806_SAR_REG, &reg);
147 if (ret) {
148 dev_err(dev, "cannot read from regmap\n");
149 return ret;
150 }
151
152 freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
153
154 if (of_device_is_compatible(pdev->dev.of_node,
155 "marvell,ap806-clock")) {
156 ret = ap806_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
157 } else if (of_device_is_compatible(pdev->dev.of_node,
158 "marvell,ap807-clock")) {
159 ret = ap807_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
160 } else {
161 dev_err(dev, "compatible not supported\n");
162 return -EINVAL;
163 }
164
165 if (ret) {
166 dev_err(dev, "invalid Sample at Reset value\n");
167 return ret;
168 }
169
108 /* Convert to hertz */ 170 /* Convert to hertz */
109 cpuclk_freq *= 1000 * 1000; 171 cpuclk_freq *= 1000 * 1000;
172 dclk_freq *= 1000 * 1000;
110 173
111 /* CPU clocks depend on the Sample At Reset configuration */ 174 /* CPU clocks depend on the Sample At Reset configuration */
112 name = ap806_unique_name(dev, syscon_node, "cpu-cluster-0"); 175 name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-0");
113 ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL, 176 ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
114 0, cpuclk_freq); 177 0, cpuclk_freq);
115 if (IS_ERR(ap806_clks[0])) { 178 if (IS_ERR(ap806_clks[0])) {
@@ -117,7 +180,7 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
117 goto fail0; 180 goto fail0;
118 } 181 }
119 182
120 name = ap806_unique_name(dev, syscon_node, "cpu-cluster-1"); 183 name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-1");
121 ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0, 184 ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
122 cpuclk_freq); 185 cpuclk_freq);
123 if (IS_ERR(ap806_clks[1])) { 186 if (IS_ERR(ap806_clks[1])) {
@@ -126,7 +189,7 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
126 } 189 }
127 190
128 /* Fixed clock is always 1200 Mhz */ 191 /* Fixed clock is always 1200 Mhz */
129 fixedclk_name = ap806_unique_name(dev, syscon_node, "fixed"); 192 fixedclk_name = ap_cp_unique_name(dev, syscon_node, "fixed");
130 ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL, 193 ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL,
131 0, 1200 * 1000 * 1000); 194 0, 1200 * 1000 * 1000);
132 if (IS_ERR(ap806_clks[2])) { 195 if (IS_ERR(ap806_clks[2])) {
@@ -135,7 +198,7 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
135 } 198 }
136 199
137 /* MSS Clock is fixed clock divided by 6 */ 200 /* MSS Clock is fixed clock divided by 6 */
138 name = ap806_unique_name(dev, syscon_node, "mss"); 201 name = ap_cp_unique_name(dev, syscon_node, "mss");
139 ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name, 202 ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
140 0, 1, 6); 203 0, 1, 6);
141 if (IS_ERR(ap806_clks[3])) { 204 if (IS_ERR(ap806_clks[3])) {
@@ -144,7 +207,7 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
144 } 207 }
145 208
146 /* SDIO(/eMMC) Clock is fixed clock divided by 3 */ 209 /* SDIO(/eMMC) Clock is fixed clock divided by 3 */
147 name = ap806_unique_name(dev, syscon_node, "sdio"); 210 name = ap_cp_unique_name(dev, syscon_node, "sdio");
148 ap806_clks[4] = clk_register_fixed_factor(NULL, name, 211 ap806_clks[4] = clk_register_fixed_factor(NULL, name,
149 fixedclk_name, 212 fixedclk_name,
150 0, 1, 3); 213 0, 1, 3);
@@ -153,6 +216,14 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
153 goto fail4; 216 goto fail4;
154 } 217 }
155 218
219 /* AP-DCLK(HCLK) Clock is DDR clock divided by 2 */
220 name = ap_cp_unique_name(dev, syscon_node, "ap-dclk");
221 ap806_clks[5] = clk_register_fixed_rate(dev, name, NULL, 0, dclk_freq);
222 if (IS_ERR(ap806_clks[5])) {
223 ret = PTR_ERR(ap806_clks[5]);
224 goto fail5;
225 }
226
156 ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data); 227 ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
157 if (ret) 228 if (ret)
158 goto fail_clk_add; 229 goto fail_clk_add;
@@ -160,6 +231,8 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
160 return 0; 231 return 0;
161 232
162fail_clk_add: 233fail_clk_add:
234 clk_unregister_fixed_factor(ap806_clks[5]);
235fail5:
163 clk_unregister_fixed_factor(ap806_clks[4]); 236 clk_unregister_fixed_factor(ap806_clks[4]);
164fail4: 237fail4:
165 clk_unregister_fixed_factor(ap806_clks[3]); 238 clk_unregister_fixed_factor(ap806_clks[3]);
@@ -206,6 +279,7 @@ builtin_platform_driver(ap806_syscon_legacy_driver);
206 279
207static const struct of_device_id ap806_clock_of_match[] = { 280static const struct of_device_id ap806_clock_of_match[] = {
208 { .compatible = "marvell,ap806-clock", }, 281 { .compatible = "marvell,ap806-clock", },
282 { .compatible = "marvell,ap807-clock", },
209 { } 283 { }
210}; 284};
211 285
diff --git a/drivers/clk/mvebu/armada_ap_cp_helper.c b/drivers/clk/mvebu/armada_ap_cp_helper.c
new file mode 100644
index 000000000000..6a930f697ee5
--- /dev/null
+++ b/drivers/clk/mvebu/armada_ap_cp_helper.c
@@ -0,0 +1,30 @@
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Marvell Armada AP and CP110 helper
4 *
5 * Copyright (C) 2018 Marvell
6 *
7 * Gregory Clement <gregory.clement@bootlin.com>
8 *
9 */
10
11#include "armada_ap_cp_helper.h"
12#include <linux/device.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15
16char *ap_cp_unique_name(struct device *dev, struct device_node *np,
17 const char *name)
18{
19 const __be32 *reg;
20 u64 addr;
21
22 /* Do not create a name if there is no clock */
23 if (!name)
24 return NULL;
25
26 reg = of_get_property(np, "reg", NULL);
27 addr = of_translate_address(np, reg);
28 return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s",
29 (unsigned long long)addr, name);
30}
diff --git a/drivers/clk/mvebu/armada_ap_cp_helper.h b/drivers/clk/mvebu/armada_ap_cp_helper.h
new file mode 100644
index 000000000000..810af1e5dfa4
--- /dev/null
+++ b/drivers/clk/mvebu/armada_ap_cp_helper.h
@@ -0,0 +1,11 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
2
3#ifndef __ARMADA_AP_CP_HELPER_H
4#define __ARMADA_AP_CP_HELPER_H
5
6struct device;
7struct device_node;
8
9char *ap_cp_unique_name(struct device *dev, struct device_node *np,
10 const char *name);
11#endif
diff --git a/drivers/clk/mvebu/cp110-system-controller.c b/drivers/clk/mvebu/cp110-system-controller.c
index b6de283f45e3..808463276145 100644
--- a/drivers/clk/mvebu/cp110-system-controller.c
+++ b/drivers/clk/mvebu/cp110-system-controller.c
@@ -26,11 +26,11 @@
26 26
27#define pr_fmt(fmt) "cp110-system-controller: " fmt 27#define pr_fmt(fmt) "cp110-system-controller: " fmt
28 28
29#include "armada_ap_cp_helper.h"
29#include <linux/clk-provider.h> 30#include <linux/clk-provider.h>
30#include <linux/mfd/syscon.h> 31#include <linux/mfd/syscon.h>
31#include <linux/init.h> 32#include <linux/init.h>
32#include <linux/of.h> 33#include <linux/of.h>
33#include <linux/of_address.h>
34#include <linux/platform_device.h> 34#include <linux/platform_device.h>
35#include <linux/regmap.h> 35#include <linux/regmap.h>
36#include <linux/slab.h> 36#include <linux/slab.h>
@@ -212,22 +212,6 @@ static struct clk_hw *cp110_of_clk_get(struct of_phandle_args *clkspec,
212 return ERR_PTR(-EINVAL); 212 return ERR_PTR(-EINVAL);
213} 213}
214 214
215static char *cp110_unique_name(struct device *dev, struct device_node *np,
216 const char *name)
217{
218 const __be32 *reg;
219 u64 addr;
220
221 /* Do not create a name if there is no clock */
222 if (!name)
223 return NULL;
224
225 reg = of_get_property(np, "reg", NULL);
226 addr = of_translate_address(np, reg);
227 return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s",
228 (unsigned long long)addr, name);
229}
230
231static int cp110_syscon_common_probe(struct platform_device *pdev, 215static int cp110_syscon_common_probe(struct platform_device *pdev,
232 struct device_node *syscon_node) 216 struct device_node *syscon_node)
233{ 217{
@@ -261,7 +245,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
261 cp110_clk_data->num = CP110_CLK_NUM; 245 cp110_clk_data->num = CP110_CLK_NUM;
262 246
263 /* Register the PLL0 which is the root of the hw tree */ 247 /* Register the PLL0 which is the root of the hw tree */
264 pll0_name = cp110_unique_name(dev, syscon_node, "pll0"); 248 pll0_name = ap_cp_unique_name(dev, syscon_node, "pll0");
265 hw = clk_hw_register_fixed_rate(NULL, pll0_name, NULL, 0, 249 hw = clk_hw_register_fixed_rate(NULL, pll0_name, NULL, 0,
266 1000 * 1000 * 1000); 250 1000 * 1000 * 1000);
267 if (IS_ERR(hw)) { 251 if (IS_ERR(hw)) {
@@ -272,7 +256,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
272 cp110_clks[CP110_CORE_PLL0] = hw; 256 cp110_clks[CP110_CORE_PLL0] = hw;
273 257
274 /* PPv2 is PLL0/3 */ 258 /* PPv2 is PLL0/3 */
275 ppv2_name = cp110_unique_name(dev, syscon_node, "ppv2-core"); 259 ppv2_name = ap_cp_unique_name(dev, syscon_node, "ppv2-core");
276 hw = clk_hw_register_fixed_factor(NULL, ppv2_name, pll0_name, 0, 1, 3); 260 hw = clk_hw_register_fixed_factor(NULL, ppv2_name, pll0_name, 0, 1, 3);
277 if (IS_ERR(hw)) { 261 if (IS_ERR(hw)) {
278 ret = PTR_ERR(hw); 262 ret = PTR_ERR(hw);
@@ -282,7 +266,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
282 cp110_clks[CP110_CORE_PPV2] = hw; 266 cp110_clks[CP110_CORE_PPV2] = hw;
283 267
284 /* X2CORE clock is PLL0/2 */ 268 /* X2CORE clock is PLL0/2 */
285 x2core_name = cp110_unique_name(dev, syscon_node, "x2core"); 269 x2core_name = ap_cp_unique_name(dev, syscon_node, "x2core");
286 hw = clk_hw_register_fixed_factor(NULL, x2core_name, pll0_name, 270 hw = clk_hw_register_fixed_factor(NULL, x2core_name, pll0_name,
287 0, 1, 2); 271 0, 1, 2);
288 if (IS_ERR(hw)) { 272 if (IS_ERR(hw)) {
@@ -293,7 +277,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
293 cp110_clks[CP110_CORE_X2CORE] = hw; 277 cp110_clks[CP110_CORE_X2CORE] = hw;
294 278
295 /* Core clock is X2CORE/2 */ 279 /* Core clock is X2CORE/2 */
296 core_name = cp110_unique_name(dev, syscon_node, "core"); 280 core_name = ap_cp_unique_name(dev, syscon_node, "core");
297 hw = clk_hw_register_fixed_factor(NULL, core_name, x2core_name, 281 hw = clk_hw_register_fixed_factor(NULL, core_name, x2core_name,
298 0, 1, 2); 282 0, 1, 2);
299 if (IS_ERR(hw)) { 283 if (IS_ERR(hw)) {
@@ -303,7 +287,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
303 287
304 cp110_clks[CP110_CORE_CORE] = hw; 288 cp110_clks[CP110_CORE_CORE] = hw;
305 /* NAND can be either PLL0/2.5 or core clock */ 289 /* NAND can be either PLL0/2.5 or core clock */
306 nand_name = cp110_unique_name(dev, syscon_node, "nand-core"); 290 nand_name = ap_cp_unique_name(dev, syscon_node, "nand-core");
307 if (nand_clk_ctrl & NF_CLOCK_SEL_400_MASK) 291 if (nand_clk_ctrl & NF_CLOCK_SEL_400_MASK)
308 hw = clk_hw_register_fixed_factor(NULL, nand_name, 292 hw = clk_hw_register_fixed_factor(NULL, nand_name,
309 pll0_name, 0, 2, 5); 293 pll0_name, 0, 2, 5);
@@ -318,7 +302,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
318 cp110_clks[CP110_CORE_NAND] = hw; 302 cp110_clks[CP110_CORE_NAND] = hw;
319 303
320 /* SDIO clock is PLL0/2.5 */ 304 /* SDIO clock is PLL0/2.5 */
321 sdio_name = cp110_unique_name(dev, syscon_node, "sdio-core"); 305 sdio_name = ap_cp_unique_name(dev, syscon_node, "sdio-core");
322 hw = clk_hw_register_fixed_factor(NULL, sdio_name, 306 hw = clk_hw_register_fixed_factor(NULL, sdio_name,
323 pll0_name, 0, 2, 5); 307 pll0_name, 0, 2, 5);
324 if (IS_ERR(hw)) { 308 if (IS_ERR(hw)) {
@@ -330,7 +314,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
330 314
331 /* create the unique name for all the gate clocks */ 315 /* create the unique name for all the gate clocks */
332 for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) 316 for (i = 0; i < ARRAY_SIZE(gate_base_names); i++)
333 gate_name[i] = cp110_unique_name(dev, syscon_node, 317 gate_name[i] = ap_cp_unique_name(dev, syscon_node,
334 gate_base_names[i]); 318 gate_base_names[i]);
335 319
336 for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) { 320 for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) {
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index e1ff83cc361e..32dbb4f09492 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -21,7 +21,6 @@ if COMMON_CLK_QCOM
21 21
22config QCOM_A53PLL 22config QCOM_A53PLL
23 tristate "MSM8916 A53 PLL" 23 tristate "MSM8916 A53 PLL"
24 default ARCH_QCOM
25 help 24 help
26 Support for the A53 PLL on MSM8916 devices. It provides 25 Support for the A53 PLL on MSM8916 devices. It provides
27 the CPU with frequencies above 1GHz. 26 the CPU with frequencies above 1GHz.
@@ -31,7 +30,6 @@ config QCOM_A53PLL
31config QCOM_CLK_APCS_MSM8916 30config QCOM_CLK_APCS_MSM8916
32 tristate "MSM8916 APCS Clock Controller" 31 tristate "MSM8916 APCS Clock Controller"
33 depends on QCOM_APCS_IPC || COMPILE_TEST 32 depends on QCOM_APCS_IPC || COMPILE_TEST
34 default ARCH_QCOM
35 help 33 help
36 Support for the APCS Clock Controller on msm8916 devices. The 34 Support for the APCS Clock Controller on msm8916 devices. The
37 APCS is managing the mux and divider which feeds the CPUs. 35 APCS is managing the mux and divider which feeds the CPUs.
@@ -292,6 +290,13 @@ config SDM_LPASSCC_845
292 Say Y if you want to use the LPASS branch clocks of the LPASS clock 290 Say Y if you want to use the LPASS branch clocks of the LPASS clock
293 controller to reset the LPASS subsystem. 291 controller to reset the LPASS subsystem.
294 292
293config SM_GCC_8150
294 tristate "SM8150 Global Clock Controller"
295 help
296 Support for the global clock controller on SM8150 devices.
297 Say Y if you want to use peripheral devices such as UART,
298 SPI, I2C, USB, SD/UFS, PCIe etc.
299
295config SPMI_PMIC_CLKDIV 300config SPMI_PMIC_CLKDIV
296 tristate "SPMI PMIC clkdiv Support" 301 tristate "SPMI PMIC clkdiv Support"
297 depends on SPMI || COMPILE_TEST 302 depends on SPMI || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index f0768fb1f037..4a813b4055d0 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
50obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o 50obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
51obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o 51obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
52obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o 52obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
53obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
53obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o 54obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
54obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o 55obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
55obj-$(CONFIG_QCOM_HFPLL) += hfpll.o 56obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 0ced4a5a9a17..055318f97991 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -32,6 +32,7 @@
32# define PLL_LOCK_DET BIT(31) 32# define PLL_LOCK_DET BIT(31)
33 33
34#define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL]) 34#define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
35#define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
35#define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL]) 36#define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
36#define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U]) 37#define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
37 38
@@ -44,14 +45,17 @@
44# define PLL_VCO_MASK 0x3 45# define PLL_VCO_MASK 0x3
45 46
46#define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U]) 47#define PLL_USER_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
48#define PLL_USER_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
47 49
48#define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL]) 50#define PLL_CONFIG_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
49#define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U]) 51#define PLL_CONFIG_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
52#define PLL_CONFIG_CTL_U1(p) ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
50#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL]) 53#define PLL_TEST_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
51#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U]) 54#define PLL_TEST_CTL_U(p) ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
52#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS]) 55#define PLL_STATUS(p) ((p)->offset + (p)->regs[PLL_OFF_STATUS])
53#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE]) 56#define PLL_OPMODE(p) ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
54#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC]) 57#define PLL_FRAC(p) ((p)->offset + (p)->regs[PLL_OFF_FRAC])
58#define PLL_CAL_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_VAL])
55 59
56const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 60const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
57 [CLK_ALPHA_PLL_TYPE_DEFAULT] = { 61 [CLK_ALPHA_PLL_TYPE_DEFAULT] = {
@@ -96,6 +100,22 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
96 [PLL_OFF_OPMODE] = 0x2c, 100 [PLL_OFF_OPMODE] = 0x2c,
97 [PLL_OFF_FRAC] = 0x38, 101 [PLL_OFF_FRAC] = 0x38,
98 }, 102 },
103 [CLK_ALPHA_PLL_TYPE_TRION] = {
104 [PLL_OFF_L_VAL] = 0x04,
105 [PLL_OFF_CAL_L_VAL] = 0x08,
106 [PLL_OFF_USER_CTL] = 0x0c,
107 [PLL_OFF_USER_CTL_U] = 0x10,
108 [PLL_OFF_USER_CTL_U1] = 0x14,
109 [PLL_OFF_CONFIG_CTL] = 0x18,
110 [PLL_OFF_CONFIG_CTL_U] = 0x1c,
111 [PLL_OFF_CONFIG_CTL_U1] = 0x20,
112 [PLL_OFF_TEST_CTL] = 0x24,
113 [PLL_OFF_TEST_CTL_U] = 0x28,
114 [PLL_OFF_STATUS] = 0x30,
115 [PLL_OFF_OPMODE] = 0x38,
116 [PLL_OFF_ALPHA_VAL] = 0x40,
117 [PLL_OFF_CAL_VAL] = 0x44,
118 },
99}; 119};
100EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 120EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
101 121
@@ -120,6 +140,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
120#define FABIA_PLL_OUT_MASK 0x7 140#define FABIA_PLL_OUT_MASK 0x7
121#define FABIA_PLL_RATE_MARGIN 500 141#define FABIA_PLL_RATE_MARGIN 500
122 142
143#define TRION_PLL_STANDBY 0x0
144#define TRION_PLL_RUN 0x1
145#define TRION_PLL_OUT_MASK 0x7
146
123#define pll_alpha_width(p) \ 147#define pll_alpha_width(p) \
124 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ 148 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
125 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) 149 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
@@ -730,6 +754,130 @@ static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
730 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); 754 return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
731} 755}
732 756
757static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
758 struct regmap *regmap)
759{
760 u32 mode_regval, opmode_regval;
761 int ret;
762
763 ret = regmap_read(regmap, PLL_MODE(pll), &mode_regval);
764 ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_regval);
765 if (ret)
766 return 0;
767
768 return ((opmode_regval & TRION_PLL_RUN) && (mode_regval & PLL_OUTCTRL));
769}
770
771static int clk_trion_pll_is_enabled(struct clk_hw *hw)
772{
773 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
774
775 return trion_pll_is_enabled(pll, pll->clkr.regmap);
776}
777
778static int clk_trion_pll_enable(struct clk_hw *hw)
779{
780 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
781 struct regmap *regmap = pll->clkr.regmap;
782 u32 val;
783 int ret;
784
785 ret = regmap_read(regmap, PLL_MODE(pll), &val);
786 if (ret)
787 return ret;
788
789 /* If in FSM mode, just vote for it */
790 if (val & PLL_VOTE_FSM_ENA) {
791 ret = clk_enable_regmap(hw);
792 if (ret)
793 return ret;
794 return wait_for_pll_enable_active(pll);
795 }
796
797 /* Set operation mode to RUN */
798 regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_RUN);
799
800 ret = wait_for_pll_enable_lock(pll);
801 if (ret)
802 return ret;
803
804 /* Enable the PLL outputs */
805 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
806 TRION_PLL_OUT_MASK, TRION_PLL_OUT_MASK);
807 if (ret)
808 return ret;
809
810 /* Enable the global PLL outputs */
811 return regmap_update_bits(regmap, PLL_MODE(pll),
812 PLL_OUTCTRL, PLL_OUTCTRL);
813}
814
815static void clk_trion_pll_disable(struct clk_hw *hw)
816{
817 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
818 struct regmap *regmap = pll->clkr.regmap;
819 u32 val;
820 int ret;
821
822 ret = regmap_read(regmap, PLL_MODE(pll), &val);
823 if (ret)
824 return;
825
826 /* If in FSM mode, just unvote it */
827 if (val & PLL_VOTE_FSM_ENA) {
828 clk_disable_regmap(hw);
829 return;
830 }
831
832 /* Disable the global PLL output */
833 ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
834 if (ret)
835 return;
836
837 /* Disable the PLL outputs */
838 ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
839 TRION_PLL_OUT_MASK, 0);
840 if (ret)
841 return;
842
843 /* Place the PLL mode in STANDBY */
844 regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_STANDBY);
845 regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
846}
847
848static unsigned long
849clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
850{
851 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
852 struct regmap *regmap = pll->clkr.regmap;
853 u32 l, frac;
854 u64 prate = parent_rate;
855
856 regmap_read(regmap, PLL_L_VAL(pll), &l);
857 regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
858
859 return alpha_pll_calc_rate(prate, l, frac, ALPHA_REG_16BIT_WIDTH);
860}
861
862static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate,
863 unsigned long *prate)
864{
865 struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
866 unsigned long min_freq, max_freq;
867 u32 l;
868 u64 a;
869
870 rate = alpha_pll_round_rate(rate, *prate,
871 &l, &a, ALPHA_REG_16BIT_WIDTH);
872 if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
873 return rate;
874
875 min_freq = pll->vco_table[0].min_freq;
876 max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
877
878 return clamp(rate, min_freq, max_freq);
879}
880
733const struct clk_ops clk_alpha_pll_ops = { 881const struct clk_ops clk_alpha_pll_ops = {
734 .enable = clk_alpha_pll_enable, 882 .enable = clk_alpha_pll_enable,
735 .disable = clk_alpha_pll_disable, 883 .disable = clk_alpha_pll_disable,
@@ -760,6 +908,15 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = {
760}; 908};
761EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); 909EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
762 910
911const struct clk_ops clk_trion_fixed_pll_ops = {
912 .enable = clk_trion_pll_enable,
913 .disable = clk_trion_pll_disable,
914 .is_enabled = clk_trion_pll_is_enabled,
915 .recalc_rate = clk_trion_pll_recalc_rate,
916 .round_rate = clk_trion_pll_round_rate,
917};
918EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);
919
763static unsigned long 920static unsigned long
764clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 921clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
765{ 922{
@@ -832,7 +989,7 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
832 int div; 989 int div;
833 990
834 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */ 991 /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
835 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1; 992 div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1;
836 993
837 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), 994 return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
838 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, 995 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
@@ -1036,11 +1193,6 @@ static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1036 u32 i, div = 1, val; 1193 u32 i, div = 1, val;
1037 int ret; 1194 int ret;
1038 1195
1039 if (!pll->post_div_table) {
1040 pr_err("Missing the post_div_table for the PLL\n");
1041 return -EINVAL;
1042 }
1043
1044 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val); 1196 ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1045 if (ret) 1197 if (ret)
1046 return ret; 1198 return ret;
@@ -1058,16 +1210,71 @@ static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1058 return (parent_rate / div); 1210 return (parent_rate / div);
1059} 1211}
1060 1212
1061static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw, 1213static unsigned long
1062 unsigned long rate, unsigned long *prate) 1214clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1063{ 1215{
1064 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw); 1216 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1217 struct regmap *regmap = pll->clkr.regmap;
1218 u32 i, div = 1, val;
1065 1219
1066 if (!pll->post_div_table) { 1220 regmap_read(regmap, PLL_USER_CTL(pll), &val);
1067 pr_err("Missing the post_div_table for the PLL\n"); 1221
1068 return -EINVAL; 1222 val >>= pll->post_div_shift;
1223 val &= PLL_POST_DIV_MASK(pll);
1224
1225 for (i = 0; i < pll->num_post_div; i++) {
1226 if (pll->post_div_table[i].val == val) {
1227 div = pll->post_div_table[i].div;
1228 break;
1229 }
1230 }
1231
1232 return (parent_rate / div);
1233}
1234
1235static long
1236clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1237 unsigned long *prate)
1238{
1239 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1240
1241 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1242 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1243};
1244
1245static int
1246clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1247 unsigned long parent_rate)
1248{
1249 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1250 struct regmap *regmap = pll->clkr.regmap;
1251 int i, val = 0, div;
1252
1253 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1254 for (i = 0; i < pll->num_post_div; i++) {
1255 if (pll->post_div_table[i].div == div) {
1256 val = pll->post_div_table[i].val;
1257 break;
1258 }
1069 } 1259 }
1070 1260
1261 return regmap_update_bits(regmap, PLL_USER_CTL(pll),
1262 PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1263 val << PLL_POST_DIV_SHIFT);
1264}
1265
1266const struct clk_ops clk_trion_pll_postdiv_ops = {
1267 .recalc_rate = clk_trion_pll_postdiv_recalc_rate,
1268 .round_rate = clk_trion_pll_postdiv_round_rate,
1269 .set_rate = clk_trion_pll_postdiv_set_rate,
1270};
1271EXPORT_SYMBOL_GPL(clk_trion_pll_postdiv_ops);
1272
1273static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
1274 unsigned long rate, unsigned long *prate)
1275{
1276 struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1277
1071 return divider_round_rate(hw, rate, prate, pll->post_div_table, 1278 return divider_round_rate(hw, rate, prate, pll->post_div_table,
1072 pll->width, CLK_DIVIDER_ROUND_CLOSEST); 1279 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1073} 1280}
@@ -1089,12 +1296,7 @@ static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
1089 if (val & PLL_VOTE_FSM_ENA) 1296 if (val & PLL_VOTE_FSM_ENA)
1090 return 0; 1297 return 0;
1091 1298
1092 if (!pll->post_div_table) { 1299 div = DIV_ROUND_UP_ULL(parent_rate, rate);
1093 pr_err("Missing the post_div_table for the PLL\n");
1094 return -EINVAL;
1095 }
1096
1097 div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
1098 for (i = 0; i < pll->num_post_div; i++) { 1300 for (i = 0; i < pll->num_post_div; i++) {
1099 if (pll->post_div_table[i].div == div) { 1301 if (pll->post_div_table[i].div == div) {
1100 val = pll->post_div_table[i].val; 1302 val = pll->post_div_table[i].val;
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 66755f0f84fc..15f27f4b06df 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -13,22 +13,27 @@ enum {
13 CLK_ALPHA_PLL_TYPE_HUAYRA, 13 CLK_ALPHA_PLL_TYPE_HUAYRA,
14 CLK_ALPHA_PLL_TYPE_BRAMMO, 14 CLK_ALPHA_PLL_TYPE_BRAMMO,
15 CLK_ALPHA_PLL_TYPE_FABIA, 15 CLK_ALPHA_PLL_TYPE_FABIA,
16 CLK_ALPHA_PLL_TYPE_TRION,
16 CLK_ALPHA_PLL_TYPE_MAX, 17 CLK_ALPHA_PLL_TYPE_MAX,
17}; 18};
18 19
19enum { 20enum {
20 PLL_OFF_L_VAL, 21 PLL_OFF_L_VAL,
22 PLL_OFF_CAL_L_VAL,
21 PLL_OFF_ALPHA_VAL, 23 PLL_OFF_ALPHA_VAL,
22 PLL_OFF_ALPHA_VAL_U, 24 PLL_OFF_ALPHA_VAL_U,
23 PLL_OFF_USER_CTL, 25 PLL_OFF_USER_CTL,
24 PLL_OFF_USER_CTL_U, 26 PLL_OFF_USER_CTL_U,
27 PLL_OFF_USER_CTL_U1,
25 PLL_OFF_CONFIG_CTL, 28 PLL_OFF_CONFIG_CTL,
26 PLL_OFF_CONFIG_CTL_U, 29 PLL_OFF_CONFIG_CTL_U,
30 PLL_OFF_CONFIG_CTL_U1,
27 PLL_OFF_TEST_CTL, 31 PLL_OFF_TEST_CTL,
28 PLL_OFF_TEST_CTL_U, 32 PLL_OFF_TEST_CTL_U,
29 PLL_OFF_STATUS, 33 PLL_OFF_STATUS,
30 PLL_OFF_OPMODE, 34 PLL_OFF_OPMODE,
31 PLL_OFF_FRAC, 35 PLL_OFF_FRAC,
36 PLL_OFF_CAL_VAL,
32 PLL_OFF_MAX_REGS 37 PLL_OFF_MAX_REGS
33}; 38};
34 39
@@ -117,5 +122,7 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
117 const struct alpha_pll_config *config); 122 const struct alpha_pll_config *config);
118void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 123void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
119 const struct alpha_pll_config *config); 124 const struct alpha_pll_config *config);
125extern const struct clk_ops clk_trion_fixed_pll_ops;
126extern const struct clk_ops clk_trion_pll_postdiv_ops;
120 127
121#endif 128#endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 8c02bffe50df..57dbac9a590e 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -119,7 +119,7 @@ static int update_config(struct clk_rcg2 *rcg)
119 } 119 }
120 120
121 WARN(1, "%s: rcg didn't update its configuration.", name); 121 WARN(1, "%s: rcg didn't update its configuration.", name);
122 return 0; 122 return -EBUSY;
123} 123}
124 124
125static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index) 125static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index c3fd632af119..49694082e9ec 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -95,7 +95,10 @@ static DEFINE_MUTEX(rpmh_clk_lock);
95 .hw.init = &(struct clk_init_data){ \ 95 .hw.init = &(struct clk_init_data){ \
96 .ops = &clk_rpmh_ops, \ 96 .ops = &clk_rpmh_ops, \
97 .name = #_name, \ 97 .name = #_name, \
98 .parent_names = (const char *[]){ "xo_board" }, \ 98 .parent_data = &(const struct clk_parent_data){ \
99 .fw_name = "xo", \
100 .name = "xo_board", \
101 }, \
99 .num_parents = 1, \ 102 .num_parents = 1, \
100 }, \ 103 }, \
101 }; \ 104 }; \
@@ -110,7 +113,10 @@ static DEFINE_MUTEX(rpmh_clk_lock);
110 .hw.init = &(struct clk_init_data){ \ 113 .hw.init = &(struct clk_init_data){ \
111 .ops = &clk_rpmh_ops, \ 114 .ops = &clk_rpmh_ops, \
112 .name = #_name_active, \ 115 .name = #_name_active, \
113 .parent_names = (const char *[]){ "xo_board" }, \ 116 .parent_data = &(const struct clk_parent_data){ \
117 .fw_name = "xo", \
118 .name = "xo_board", \
119 }, \
114 .num_parents = 1, \ 120 .num_parents = 1, \
115 }, \ 121 }, \
116 } 122 }
@@ -368,6 +374,33 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
368 .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks), 374 .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),
369}; 375};
370 376
377DEFINE_CLK_RPMH_ARC(sm8150, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
378DEFINE_CLK_RPMH_VRM(sm8150, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
379DEFINE_CLK_RPMH_VRM(sm8150, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
380DEFINE_CLK_RPMH_VRM(sm8150, rf_clk1, rf_clk1_ao, "rfclka1", 1);
381DEFINE_CLK_RPMH_VRM(sm8150, rf_clk2, rf_clk2_ao, "rfclka2", 1);
382DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1);
383
384static struct clk_hw *sm8150_rpmh_clocks[] = {
385 [RPMH_CXO_CLK] = &sm8150_bi_tcxo.hw,
386 [RPMH_CXO_CLK_A] = &sm8150_bi_tcxo_ao.hw,
387 [RPMH_LN_BB_CLK2] = &sm8150_ln_bb_clk2.hw,
388 [RPMH_LN_BB_CLK2_A] = &sm8150_ln_bb_clk2_ao.hw,
389 [RPMH_LN_BB_CLK3] = &sm8150_ln_bb_clk3.hw,
390 [RPMH_LN_BB_CLK3_A] = &sm8150_ln_bb_clk3_ao.hw,
391 [RPMH_RF_CLK1] = &sm8150_rf_clk1.hw,
392 [RPMH_RF_CLK1_A] = &sm8150_rf_clk1_ao.hw,
393 [RPMH_RF_CLK2] = &sm8150_rf_clk2.hw,
394 [RPMH_RF_CLK2_A] = &sm8150_rf_clk2_ao.hw,
395 [RPMH_RF_CLK3] = &sm8150_rf_clk3.hw,
396 [RPMH_RF_CLK3_A] = &sm8150_rf_clk3_ao.hw,
397};
398
399static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
400 .clks = sm8150_rpmh_clocks,
401 .num_clks = ARRAY_SIZE(sm8150_rpmh_clocks),
402};
403
371static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, 404static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
372 void *data) 405 void *data)
373{ 406{
@@ -447,6 +480,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
447 480
448static const struct of_device_id clk_rpmh_match_table[] = { 481static const struct of_device_id clk_rpmh_match_table[] = {
449 { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845}, 482 { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
483 { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
450 { } 484 { }
451}; 485};
452MODULE_DEVICE_TABLE(of, clk_rpmh_match_table); 486MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index a6b2f86112d8..28ddc747d703 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -306,4 +306,24 @@ int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
306} 306}
307EXPORT_SYMBOL_GPL(qcom_cc_probe); 307EXPORT_SYMBOL_GPL(qcom_cc_probe);
308 308
309int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
310 const struct qcom_cc_desc *desc)
311{
312 struct regmap *regmap;
313 struct resource *res;
314 void __iomem *base;
315
316 res = platform_get_resource(pdev, IORESOURCE_MEM, index);
317 base = devm_ioremap_resource(&pdev->dev, res);
318 if (IS_ERR(base))
319 return -ENOMEM;
320
321 regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config);
322 if (IS_ERR(regmap))
323 return PTR_ERR(regmap);
324
325 return qcom_cc_really_probe(pdev, desc, regmap);
326}
327EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index);
328
309MODULE_LICENSE("GPL v2"); 329MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index 1e2a8bdac55a..bb39a7e106d8 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -61,5 +61,7 @@ extern int qcom_cc_really_probe(struct platform_device *pdev,
61 struct regmap *regmap); 61 struct regmap *regmap);
62extern int qcom_cc_probe(struct platform_device *pdev, 62extern int qcom_cc_probe(struct platform_device *pdev,
63 const struct qcom_cc_desc *desc); 63 const struct qcom_cc_desc *desc);
64extern int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
65 const struct qcom_cc_desc *desc);
64 66
65#endif 67#endif
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index 39ade58b4ada..e01f5f591d1e 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -1108,7 +1108,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
1108 .name = "sdcc2_apps_clk_src", 1108 .name = "sdcc2_apps_clk_src",
1109 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, 1109 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
1110 .num_parents = 4, 1110 .num_parents = 4,
1111 .ops = &clk_rcg2_ops, 1111 .ops = &clk_rcg2_floor_ops,
1112 }, 1112 },
1113}; 1113};
1114 1114
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index 033688264c7b..091acd59c1d6 100644
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -1042,7 +1042,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
1042 .name = "sdcc2_apps_clk_src", 1042 .name = "sdcc2_apps_clk_src",
1043 .parent_names = gcc_parent_names_4, 1043 .parent_names = gcc_parent_names_4,
1044 .num_parents = 4, 1044 .num_parents = 4,
1045 .ops = &clk_rcg2_ops, 1045 .ops = &clk_rcg2_floor_ops,
1046 }, 1046 },
1047}; 1047};
1048 1048
@@ -1066,7 +1066,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
1066 .name = "sdcc4_apps_clk_src", 1066 .name = "sdcc4_apps_clk_src",
1067 .parent_names = gcc_parent_names_1, 1067 .parent_names = gcc_parent_names_1,
1068 .num_parents = 3, 1068 .num_parents = 3,
1069 .ops = &clk_rcg2_ops, 1069 .ops = &clk_rcg2_floor_ops,
1070 }, 1070 },
1071}; 1071};
1072 1072
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index 29cf464dd2c8..bd32212f37e6 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -1057,7 +1057,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
1057 .name = "sdcc1_apps_clk_src", 1057 .name = "sdcc1_apps_clk_src",
1058 .parent_names = gcc_parent_names_13, 1058 .parent_names = gcc_parent_names_13,
1059 .num_parents = 5, 1059 .num_parents = 5,
1060 .ops = &clk_rcg2_ops, 1060 .ops = &clk_rcg2_floor_ops,
1061 }, 1061 },
1062}; 1062};
1063 1063
@@ -1103,7 +1103,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
1103 .name = "sdcc2_apps_clk_src", 1103 .name = "sdcc2_apps_clk_src",
1104 .parent_names = gcc_parent_names_14, 1104 .parent_names = gcc_parent_names_14,
1105 .num_parents = 4, 1105 .num_parents = 4,
1106 .ops = &clk_rcg2_ops, 1106 .ops = &clk_rcg2_floor_ops,
1107 }, 1107 },
1108}; 1108};
1109 1109
@@ -2604,6 +2604,32 @@ static struct clk_branch gcc_usb_hs_system_clk = {
2604 }, 2604 },
2605}; 2605};
2606 2606
2607static struct clk_branch gcc_wdsp_q6ss_ahbs_clk = {
2608 .halt_reg = 0x1e004,
2609 .halt_check = BRANCH_HALT,
2610 .clkr = {
2611 .enable_reg = 0x1e004,
2612 .enable_mask = BIT(0),
2613 .hw.init = &(struct clk_init_data){
2614 .name = "gcc_wdsp_q6ss_ahbs_clk",
2615 .ops = &clk_branch2_ops,
2616 },
2617 },
2618};
2619
2620static struct clk_branch gcc_wdsp_q6ss_axim_clk = {
2621 .halt_reg = 0x1e008,
2622 .halt_check = BRANCH_HALT,
2623 .clkr = {
2624 .enable_reg = 0x1e008,
2625 .enable_mask = BIT(0),
2626 .hw.init = &(struct clk_init_data){
2627 .name = "gcc_wdsp_q6ss_axim_clk",
2628 .ops = &clk_branch2_ops,
2629 },
2630 },
2631};
2632
2607static struct clk_hw *gcc_qcs404_hws[] = { 2633static struct clk_hw *gcc_qcs404_hws[] = {
2608 &cxo.hw, 2634 &cxo.hw,
2609}; 2635};
@@ -2749,6 +2775,9 @@ static struct clk_regmap *gcc_qcs404_clocks[] = {
2749 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, 2775 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
2750 [GCC_DCC_CLK] = &gcc_dcc_clk.clkr, 2776 [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
2751 [GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr, 2777 [GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr,
2778 [GCC_WCSS_Q6_AHB_CLK] = &gcc_wdsp_q6ss_ahbs_clk.clkr,
2779 [GCC_WCSS_Q6_AXIM_CLK] = &gcc_wdsp_q6ss_axim_clk.clkr,
2780
2752}; 2781};
2753 2782
2754static const struct qcom_reset_map gcc_qcs404_resets[] = { 2783static const struct qcom_reset_map gcc_qcs404_resets[] = {
@@ -2774,6 +2803,7 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = {
2774 [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 }, 2803 [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
2775 [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 }, 2804 [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
2776 [GCC_EMAC_BCR] = { 0x4e000 }, 2805 [GCC_EMAC_BCR] = { 0x4e000 },
2806 [GCC_WDSP_RESTART] = {0x19000},
2777}; 2807};
2778 2808
2779static const struct regmap_config gcc_qcs404_regmap_config = { 2809static const struct regmap_config gcc_qcs404_regmap_config = {
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
index 8827db23066f..bf5730832ef3 100644
--- a/drivers/clk/qcom/gcc-sdm660.c
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -787,7 +787,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
787 .name = "sdcc2_apps_clk_src", 787 .name = "sdcc2_apps_clk_src",
788 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4, 788 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4,
789 .num_parents = 4, 789 .num_parents = 4,
790 .ops = &clk_rcg2_ops, 790 .ops = &clk_rcg2_floor_ops,
791 }, 791 },
792}; 792};
793 793
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index 7131dcf9b060..95be125c3bdd 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -685,7 +685,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
685 .name = "gcc_sdcc2_apps_clk_src", 685 .name = "gcc_sdcc2_apps_clk_src",
686 .parent_names = gcc_parent_names_10, 686 .parent_names = gcc_parent_names_10,
687 .num_parents = 5, 687 .num_parents = 5,
688 .ops = &clk_rcg2_ops, 688 .ops = &clk_rcg2_floor_ops,
689 }, 689 },
690}; 690};
691 691
@@ -709,7 +709,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
709 .name = "gcc_sdcc4_apps_clk_src", 709 .name = "gcc_sdcc4_apps_clk_src",
710 .parent_names = gcc_parent_names_0, 710 .parent_names = gcc_parent_names_0,
711 .num_parents = 4, 711 .num_parents = 4,
712 .ops = &clk_rcg2_ops, 712 .ops = &clk_rcg2_floor_ops,
713 }, 713 },
714}; 714};
715 715
diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
new file mode 100644
index 000000000000..20877214acff
--- /dev/null
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -0,0 +1,3588 @@
1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
3
4#include <linux/kernel.h>
5#include <linux/bitops.h>
6#include <linux/err.h>
7#include <linux/platform_device.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/of_device.h>
11#include <linux/clk-provider.h>
12#include <linux/regmap.h>
13#include <linux/reset-controller.h>
14
15#include <dt-bindings/clock/qcom,gcc-sm8150.h>
16
17#include "common.h"
18#include "clk-alpha-pll.h"
19#include "clk-branch.h"
20#include "clk-pll.h"
21#include "clk-rcg.h"
22#include "clk-regmap.h"
23#include "reset.h"
24
25enum {
26 P_BI_TCXO,
27 P_AUD_REF_CLK,
28 P_CORE_BI_PLL_TEST_SE,
29 P_GPLL0_OUT_EVEN,
30 P_GPLL0_OUT_MAIN,
31 P_GPLL7_OUT_MAIN,
32 P_GPLL9_OUT_MAIN,
33 P_SLEEP_CLK,
34};
35
36static const struct pll_vco trion_vco[] = {
37 { 249600000, 2000000000, 0 },
38};
39
40static struct clk_alpha_pll gpll0 = {
41 .offset = 0x0,
42 .vco_table = trion_vco,
43 .num_vco = ARRAY_SIZE(trion_vco),
44 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
45 .clkr = {
46 .enable_reg = 0x52000,
47 .enable_mask = BIT(0),
48 .hw.init = &(struct clk_init_data){
49 .name = "gpll0",
50 .parent_data = &(const struct clk_parent_data){
51 .fw_name = "bi_tcxo",
52 .name = "bi_tcxo",
53 },
54 .num_parents = 1,
55 .ops = &clk_trion_fixed_pll_ops,
56 },
57 },
58};
59
60static const struct clk_div_table post_div_table_trion_even[] = {
61 { 0x0, 1 },
62 { 0x1, 2 },
63 { 0x3, 4 },
64 { 0x7, 8 },
65 { }
66};
67
68static struct clk_alpha_pll_postdiv gpll0_out_even = {
69 .offset = 0x0,
70 .post_div_shift = 8,
71 .post_div_table = post_div_table_trion_even,
72 .num_post_div = ARRAY_SIZE(post_div_table_trion_even),
73 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
74 .width = 4,
75 .clkr.hw.init = &(struct clk_init_data){
76 .name = "gpll0_out_even",
77 .parent_data = &(const struct clk_parent_data){
78 .fw_name = "bi_tcxo",
79 .name = "bi_tcxo",
80 },
81 .num_parents = 1,
82 .ops = &clk_trion_pll_postdiv_ops,
83 },
84};
85
86static struct clk_alpha_pll gpll7 = {
87 .offset = 0x1a000,
88 .vco_table = trion_vco,
89 .num_vco = ARRAY_SIZE(trion_vco),
90 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
91 .clkr = {
92 .enable_reg = 0x52000,
93 .enable_mask = BIT(7),
94 .hw.init = &(struct clk_init_data){
95 .name = "gpll7",
96 .parent_data = &(const struct clk_parent_data){
97 .fw_name = "bi_tcxo",
98 .name = "bi_tcxo",
99 },
100 .num_parents = 1,
101 .ops = &clk_trion_fixed_pll_ops,
102 },
103 },
104};
105
106static struct clk_alpha_pll gpll9 = {
107 .offset = 0x1c000,
108 .vco_table = trion_vco,
109 .num_vco = ARRAY_SIZE(trion_vco),
110 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
111 .clkr = {
112 .enable_reg = 0x52000,
113 .enable_mask = BIT(9),
114 .hw.init = &(struct clk_init_data){
115 .name = "gpll9",
116 .parent_data = &(const struct clk_parent_data){
117 .fw_name = "bi_tcxo",
118 .name = "bi_tcxo",
119 },
120 .num_parents = 1,
121 .ops = &clk_trion_fixed_pll_ops,
122 },
123 },
124};
125
126static const struct parent_map gcc_parent_map_0[] = {
127 { P_BI_TCXO, 0 },
128 { P_GPLL0_OUT_MAIN, 1 },
129 { P_GPLL0_OUT_EVEN, 6 },
130 { P_CORE_BI_PLL_TEST_SE, 7 },
131};
132
133static const struct clk_parent_data gcc_parents_0[] = {
134 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
135 { .hw = &gpll0.clkr.hw },
136 { .hw = &gpll0_out_even.clkr.hw },
137 { .fw_name = "core_bi_pll_test_se" },
138};
139
140static const struct parent_map gcc_parent_map_1[] = {
141 { P_BI_TCXO, 0 },
142 { P_GPLL0_OUT_MAIN, 1 },
143 { P_SLEEP_CLK, 5 },
144 { P_GPLL0_OUT_EVEN, 6 },
145 { P_CORE_BI_PLL_TEST_SE, 7 },
146};
147
148static const struct clk_parent_data gcc_parents_1[] = {
149 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
150 { .hw = &gpll0.clkr.hw },
151 { .fw_name = "sleep_clk", .name = "sleep_clk" },
152 { .hw = &gpll0_out_even.clkr.hw },
153 { .fw_name = "core_bi_pll_test_se" },
154};
155
156static const struct parent_map gcc_parent_map_2[] = {
157 { P_BI_TCXO, 0 },
158 { P_SLEEP_CLK, 5 },
159 { P_CORE_BI_PLL_TEST_SE, 7 },
160};
161
162static const struct clk_parent_data gcc_parents_2[] = {
163 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
164 { .fw_name = "sleep_clk", .name = "sleep_clk" },
165 { .fw_name = "core_bi_pll_test_se" },
166};
167
168static const struct parent_map gcc_parent_map_3[] = {
169 { P_BI_TCXO, 0 },
170 { P_GPLL0_OUT_MAIN, 1 },
171 { P_CORE_BI_PLL_TEST_SE, 7 },
172};
173
174static const struct clk_parent_data gcc_parents_3[] = {
175 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
176 { .hw = &gpll0.clkr.hw },
177 { .fw_name = "core_bi_pll_test_se"},
178};
179
180static const struct parent_map gcc_parent_map_4[] = {
181 { P_BI_TCXO, 0 },
182 { P_CORE_BI_PLL_TEST_SE, 7 },
183};
184
185static const struct clk_parent_data gcc_parents_4[] = {
186 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
187 { .fw_name = "core_bi_pll_test_se" },
188};
189
190static const struct parent_map gcc_parent_map_5[] = {
191 { P_BI_TCXO, 0 },
192 { P_GPLL0_OUT_MAIN, 1 },
193 { P_GPLL7_OUT_MAIN, 3 },
194 { P_GPLL0_OUT_EVEN, 6 },
195 { P_CORE_BI_PLL_TEST_SE, 7 },
196};
197
198static const struct clk_parent_data gcc_parents_5[] = {
199 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
200 { .hw = &gpll0.clkr.hw },
201 { .hw = &gpll7.clkr.hw },
202 { .hw = &gpll0_out_even.clkr.hw },
203 { .fw_name = "core_bi_pll_test_se" },
204};
205
206static const struct parent_map gcc_parent_map_6[] = {
207 { P_BI_TCXO, 0 },
208 { P_GPLL0_OUT_MAIN, 1 },
209 { P_GPLL9_OUT_MAIN, 2 },
210 { P_GPLL0_OUT_EVEN, 6 },
211 { P_CORE_BI_PLL_TEST_SE, 7 },
212};
213
214static const struct clk_parent_data gcc_parents_6[] = {
215 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
216 { .hw = &gpll0.clkr.hw },
217 { .hw = &gpll9.clkr.hw },
218 { .hw = &gpll0_out_even.clkr.hw },
219 { .fw_name = "core_bi_pll_test_se" },
220};
221
222static const struct parent_map gcc_parent_map_7[] = {
223 { P_BI_TCXO, 0 },
224 { P_GPLL0_OUT_MAIN, 1 },
225 { P_AUD_REF_CLK, 2 },
226 { P_GPLL0_OUT_EVEN, 6 },
227 { P_CORE_BI_PLL_TEST_SE, 7 },
228};
229
230static const struct clk_parent_data gcc_parents_7[] = {
231 { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
232 { .hw = &gpll0.clkr.hw },
233 { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
234 { .hw = &gpll0_out_even.clkr.hw },
235 { .fw_name = "core_bi_pll_test_se" },
236};
237
238static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
239 F(19200000, P_BI_TCXO, 1, 0, 0),
240 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
241 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
242 { }
243};
244
245static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
246 .cmd_rcgr = 0x48014,
247 .mnd_width = 0,
248 .hid_width = 5,
249 .parent_map = gcc_parent_map_0,
250 .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
251 .clkr.hw.init = &(struct clk_init_data){
252 .name = "gcc_cpuss_ahb_clk_src",
253 .parent_data = gcc_parents_0,
254 .num_parents = 4,
255 .flags = CLK_SET_RATE_PARENT,
256 .ops = &clk_rcg2_ops,
257 },
258};
259
260static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
261 F(19200000, P_BI_TCXO, 1, 0, 0),
262 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
263 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
264 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
265 { }
266};
267
268static struct clk_rcg2 gcc_emac_ptp_clk_src = {
269 .cmd_rcgr = 0x6038,
270 .mnd_width = 0,
271 .hid_width = 5,
272 .parent_map = gcc_parent_map_5,
273 .freq_tbl = ftbl_gcc_emac_ptp_clk_src,
274 .clkr.hw.init = &(struct clk_init_data){
275 .name = "gcc_emac_ptp_clk_src",
276 .parent_data = gcc_parents_5,
277 .num_parents = 5,
278 .flags = CLK_SET_RATE_PARENT,
279 .ops = &clk_rcg2_ops,
280 },
281};
282
283static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
284 F(2500000, P_BI_TCXO, 1, 25, 192),
285 F(5000000, P_BI_TCXO, 1, 25, 96),
286 F(19200000, P_BI_TCXO, 1, 0, 0),
287 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
288 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
289 F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
290 F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
291 { }
292};
293
294static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
295 .cmd_rcgr = 0x601c,
296 .mnd_width = 8,
297 .hid_width = 5,
298 .parent_map = gcc_parent_map_5,
299 .freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
300 .clkr.hw.init = &(struct clk_init_data){
301 .name = "gcc_emac_rgmii_clk_src",
302 .parent_data = gcc_parents_5,
303 .num_parents = 5,
304 .flags = CLK_SET_RATE_PARENT,
305 .ops = &clk_rcg2_ops,
306 },
307};
308
309static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
310 F(19200000, P_BI_TCXO, 1, 0, 0),
311 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
312 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
313 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
314 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
315 { }
316};
317
318static struct clk_rcg2 gcc_gp1_clk_src = {
319 .cmd_rcgr = 0x64004,
320 .mnd_width = 8,
321 .hid_width = 5,
322 .parent_map = gcc_parent_map_1,
323 .freq_tbl = ftbl_gcc_gp1_clk_src,
324 .clkr.hw.init = &(struct clk_init_data){
325 .name = "gcc_gp1_clk_src",
326 .parent_data = gcc_parents_1,
327 .num_parents = 5,
328 .flags = CLK_SET_RATE_PARENT,
329 .ops = &clk_rcg2_ops,
330 },
331};
332
333static struct clk_rcg2 gcc_gp2_clk_src = {
334 .cmd_rcgr = 0x65004,
335 .mnd_width = 8,
336 .hid_width = 5,
337 .parent_map = gcc_parent_map_1,
338 .freq_tbl = ftbl_gcc_gp1_clk_src,
339 .clkr.hw.init = &(struct clk_init_data){
340 .name = "gcc_gp2_clk_src",
341 .parent_data = gcc_parents_1,
342 .num_parents = 5,
343 .flags = CLK_SET_RATE_PARENT,
344 .ops = &clk_rcg2_ops,
345 },
346};
347
348static struct clk_rcg2 gcc_gp3_clk_src = {
349 .cmd_rcgr = 0x66004,
350 .mnd_width = 8,
351 .hid_width = 5,
352 .parent_map = gcc_parent_map_1,
353 .freq_tbl = ftbl_gcc_gp1_clk_src,
354 .clkr.hw.init = &(struct clk_init_data){
355 .name = "gcc_gp3_clk_src",
356 .parent_data = gcc_parents_1,
357 .num_parents = 5,
358 .flags = CLK_SET_RATE_PARENT,
359 .ops = &clk_rcg2_ops,
360 },
361};
362
363static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
364 F(9600000, P_BI_TCXO, 2, 0, 0),
365 F(19200000, P_BI_TCXO, 1, 0, 0),
366 { }
367};
368
369static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
370 .cmd_rcgr = 0x6b02c,
371 .mnd_width = 16,
372 .hid_width = 5,
373 .parent_map = gcc_parent_map_2,
374 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
375 .clkr.hw.init = &(struct clk_init_data){
376 .name = "gcc_pcie_0_aux_clk_src",
377 .parent_data = gcc_parents_2,
378 .num_parents = 3,
379 .flags = CLK_SET_RATE_PARENT,
380 .ops = &clk_rcg2_ops,
381 },
382};
383
384static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
385 .cmd_rcgr = 0x8d02c,
386 .mnd_width = 16,
387 .hid_width = 5,
388 .parent_map = gcc_parent_map_2,
389 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
390 .clkr.hw.init = &(struct clk_init_data){
391 .name = "gcc_pcie_1_aux_clk_src",
392 .parent_data = gcc_parents_2,
393 .num_parents = 3,
394 .flags = CLK_SET_RATE_PARENT,
395 .ops = &clk_rcg2_ops,
396 },
397};
398
399static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
400 F(19200000, P_BI_TCXO, 1, 0, 0),
401 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
402 { }
403};
404
405static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
406 .cmd_rcgr = 0x6f014,
407 .mnd_width = 0,
408 .hid_width = 5,
409 .parent_map = gcc_parent_map_0,
410 .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
411 .clkr.hw.init = &(struct clk_init_data){
412 .name = "gcc_pcie_phy_refgen_clk_src",
413 .parent_data = gcc_parents_0,
414 .num_parents = 4,
415 .flags = CLK_SET_RATE_PARENT,
416 .ops = &clk_rcg2_ops,
417 },
418};
419
420static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
421 F(9600000, P_BI_TCXO, 2, 0, 0),
422 F(19200000, P_BI_TCXO, 1, 0, 0),
423 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
424 { }
425};
426
427static struct clk_rcg2 gcc_pdm2_clk_src = {
428 .cmd_rcgr = 0x33010,
429 .mnd_width = 0,
430 .hid_width = 5,
431 .parent_map = gcc_parent_map_0,
432 .freq_tbl = ftbl_gcc_pdm2_clk_src,
433 .clkr.hw.init = &(struct clk_init_data){
434 .name = "gcc_pdm2_clk_src",
435 .parent_data = gcc_parents_0,
436 .num_parents = 4,
437 .flags = CLK_SET_RATE_PARENT,
438 .ops = &clk_rcg2_ops,
439 },
440};
441
442static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
443 F(19200000, P_BI_TCXO, 1, 0, 0),
444 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
445 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
446 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
447 { }
448};
449
450static struct clk_rcg2 gcc_qspi_core_clk_src = {
451 .cmd_rcgr = 0x4b008,
452 .mnd_width = 0,
453 .hid_width = 5,
454 .parent_map = gcc_parent_map_0,
455 .freq_tbl = ftbl_gcc_qspi_core_clk_src,
456 .clkr.hw.init = &(struct clk_init_data){
457 .name = "gcc_qspi_core_clk_src",
458 .parent_data = gcc_parents_0,
459 .num_parents = 4,
460 .flags = CLK_SET_RATE_PARENT,
461 .ops = &clk_rcg2_ops,
462 },
463};
464
465static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
466 F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
467 F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
468 F(19200000, P_BI_TCXO, 1, 0, 0),
469 F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
470 F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
471 F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
472 F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
473 F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
474 F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
475 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
476 F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
477 F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
478 F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
479 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
480 F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
481 { }
482};
483
484static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
485 .cmd_rcgr = 0x17148,
486 .mnd_width = 16,
487 .hid_width = 5,
488 .parent_map = gcc_parent_map_0,
489 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
490 .clkr.hw.init = &(struct clk_init_data){
491 .name = "gcc_qupv3_wrap0_s0_clk_src",
492 .parent_data = gcc_parents_0,
493 .num_parents = 4,
494 .flags = CLK_SET_RATE_PARENT,
495 .ops = &clk_rcg2_ops,
496 },
497};
498
499static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
500 .cmd_rcgr = 0x17278,
501 .mnd_width = 16,
502 .hid_width = 5,
503 .parent_map = gcc_parent_map_0,
504 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
505 .clkr.hw.init = &(struct clk_init_data){
506 .name = "gcc_qupv3_wrap0_s1_clk_src",
507 .parent_data = gcc_parents_0,
508 .num_parents = 4,
509 .flags = CLK_SET_RATE_PARENT,
510 .ops = &clk_rcg2_ops,
511 },
512};
513
514static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
515 .cmd_rcgr = 0x173a8,
516 .mnd_width = 16,
517 .hid_width = 5,
518 .parent_map = gcc_parent_map_0,
519 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
520 .clkr.hw.init = &(struct clk_init_data){
521 .name = "gcc_qupv3_wrap0_s2_clk_src",
522 .parent_data = gcc_parents_0,
523 .num_parents = 4,
524 .flags = CLK_SET_RATE_PARENT,
525 .ops = &clk_rcg2_ops,
526 },
527};
528
529static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
530 .cmd_rcgr = 0x174d8,
531 .mnd_width = 16,
532 .hid_width = 5,
533 .parent_map = gcc_parent_map_0,
534 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
535 .clkr.hw.init = &(struct clk_init_data){
536 .name = "gcc_qupv3_wrap0_s3_clk_src",
537 .parent_data = gcc_parents_0,
538 .num_parents = 4,
539 .flags = CLK_SET_RATE_PARENT,
540 .ops = &clk_rcg2_ops,
541 },
542};
543
544static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
545 .cmd_rcgr = 0x17608,
546 .mnd_width = 16,
547 .hid_width = 5,
548 .parent_map = gcc_parent_map_0,
549 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
550 .clkr.hw.init = &(struct clk_init_data){
551 .name = "gcc_qupv3_wrap0_s4_clk_src",
552 .parent_data = gcc_parents_0,
553 .num_parents = 4,
554 .flags = CLK_SET_RATE_PARENT,
555 .ops = &clk_rcg2_ops,
556 },
557};
558
559static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
560 .cmd_rcgr = 0x17738,
561 .mnd_width = 16,
562 .hid_width = 5,
563 .parent_map = gcc_parent_map_0,
564 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
565 .clkr.hw.init = &(struct clk_init_data){
566 .name = "gcc_qupv3_wrap0_s5_clk_src",
567 .parent_data = gcc_parents_0,
568 .num_parents = 4,
569 .flags = CLK_SET_RATE_PARENT,
570 .ops = &clk_rcg2_ops,
571 },
572};
573
574static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
575 .cmd_rcgr = 0x17868,
576 .mnd_width = 16,
577 .hid_width = 5,
578 .parent_map = gcc_parent_map_0,
579 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
580 .clkr.hw.init = &(struct clk_init_data){
581 .name = "gcc_qupv3_wrap0_s6_clk_src",
582 .parent_data = gcc_parents_0,
583 .num_parents = 4,
584 .flags = CLK_SET_RATE_PARENT,
585 .ops = &clk_rcg2_ops,
586 },
587};
588
589static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
590 .cmd_rcgr = 0x17998,
591 .mnd_width = 16,
592 .hid_width = 5,
593 .parent_map = gcc_parent_map_0,
594 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
595 .clkr.hw.init = &(struct clk_init_data){
596 .name = "gcc_qupv3_wrap0_s7_clk_src",
597 .parent_data = gcc_parents_0,
598 .num_parents = 4,
599 .flags = CLK_SET_RATE_PARENT,
600 .ops = &clk_rcg2_ops,
601 },
602};
603
604static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
605 .cmd_rcgr = 0x18148,
606 .mnd_width = 16,
607 .hid_width = 5,
608 .parent_map = gcc_parent_map_0,
609 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
610 .clkr.hw.init = &(struct clk_init_data){
611 .name = "gcc_qupv3_wrap1_s0_clk_src",
612 .parent_data = gcc_parents_0,
613 .num_parents = 4,
614 .flags = CLK_SET_RATE_PARENT,
615 .ops = &clk_rcg2_ops,
616 },
617};
618
619static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
620 .cmd_rcgr = 0x18278,
621 .mnd_width = 16,
622 .hid_width = 5,
623 .parent_map = gcc_parent_map_0,
624 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
625 .clkr.hw.init = &(struct clk_init_data){
626 .name = "gcc_qupv3_wrap1_s1_clk_src",
627 .parent_data = gcc_parents_0,
628 .num_parents = 4,
629 .flags = CLK_SET_RATE_PARENT,
630 .ops = &clk_rcg2_ops,
631 },
632};
633
634static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
635 .cmd_rcgr = 0x183a8,
636 .mnd_width = 16,
637 .hid_width = 5,
638 .parent_map = gcc_parent_map_0,
639 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
640 .clkr.hw.init = &(struct clk_init_data){
641 .name = "gcc_qupv3_wrap1_s2_clk_src",
642 .parent_data = gcc_parents_0,
643 .num_parents = 4,
644 .flags = CLK_SET_RATE_PARENT,
645 .ops = &clk_rcg2_ops,
646 },
647};
648
649static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
650 .cmd_rcgr = 0x184d8,
651 .mnd_width = 16,
652 .hid_width = 5,
653 .parent_map = gcc_parent_map_0,
654 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
655 .clkr.hw.init = &(struct clk_init_data){
656 .name = "gcc_qupv3_wrap1_s3_clk_src",
657 .parent_data = gcc_parents_0,
658 .num_parents = 4,
659 .flags = CLK_SET_RATE_PARENT,
660 .ops = &clk_rcg2_ops,
661 },
662};
663
664static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
665 .cmd_rcgr = 0x18608,
666 .mnd_width = 16,
667 .hid_width = 5,
668 .parent_map = gcc_parent_map_0,
669 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
670 .clkr.hw.init = &(struct clk_init_data){
671 .name = "gcc_qupv3_wrap1_s4_clk_src",
672 .parent_data = gcc_parents_0,
673 .num_parents = 4,
674 .flags = CLK_SET_RATE_PARENT,
675 .ops = &clk_rcg2_ops,
676 },
677};
678
679static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
680 .cmd_rcgr = 0x18738,
681 .mnd_width = 16,
682 .hid_width = 5,
683 .parent_map = gcc_parent_map_0,
684 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
685 .clkr.hw.init = &(struct clk_init_data){
686 .name = "gcc_qupv3_wrap1_s5_clk_src",
687 .parent_data = gcc_parents_0,
688 .num_parents = 4,
689 .flags = CLK_SET_RATE_PARENT,
690 .ops = &clk_rcg2_ops,
691 },
692};
693
694static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
695 .cmd_rcgr = 0x1e148,
696 .mnd_width = 16,
697 .hid_width = 5,
698 .parent_map = gcc_parent_map_0,
699 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
700 .clkr.hw.init = &(struct clk_init_data){
701 .name = "gcc_qupv3_wrap2_s0_clk_src",
702 .parent_data = gcc_parents_0,
703 .num_parents = 4,
704 .flags = CLK_SET_RATE_PARENT,
705 .ops = &clk_rcg2_ops,
706 },
707};
708
709static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
710 .cmd_rcgr = 0x1e278,
711 .mnd_width = 16,
712 .hid_width = 5,
713 .parent_map = gcc_parent_map_0,
714 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
715 .clkr.hw.init = &(struct clk_init_data){
716 .name = "gcc_qupv3_wrap2_s1_clk_src",
717 .parent_data = gcc_parents_0,
718 .num_parents = 4,
719 .flags = CLK_SET_RATE_PARENT,
720 .ops = &clk_rcg2_ops,
721 },
722};
723
724static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
725 .cmd_rcgr = 0x1e3a8,
726 .mnd_width = 16,
727 .hid_width = 5,
728 .parent_map = gcc_parent_map_0,
729 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
730 .clkr.hw.init = &(struct clk_init_data){
731 .name = "gcc_qupv3_wrap2_s2_clk_src",
732 .parent_data = gcc_parents_0,
733 .num_parents = 4,
734 .flags = CLK_SET_RATE_PARENT,
735 .ops = &clk_rcg2_ops,
736 },
737};
738
739static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
740 .cmd_rcgr = 0x1e4d8,
741 .mnd_width = 16,
742 .hid_width = 5,
743 .parent_map = gcc_parent_map_0,
744 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
745 .clkr.hw.init = &(struct clk_init_data){
746 .name = "gcc_qupv3_wrap2_s3_clk_src",
747 .parent_data = gcc_parents_0,
748 .num_parents = 4,
749 .flags = CLK_SET_RATE_PARENT,
750 .ops = &clk_rcg2_ops,
751 },
752};
753
754static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
755 .cmd_rcgr = 0x1e608,
756 .mnd_width = 16,
757 .hid_width = 5,
758 .parent_map = gcc_parent_map_0,
759 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
760 .clkr.hw.init = &(struct clk_init_data){
761 .name = "gcc_qupv3_wrap2_s4_clk_src",
762 .parent_data = gcc_parents_0,
763 .num_parents = 4,
764 .flags = CLK_SET_RATE_PARENT,
765 .ops = &clk_rcg2_ops,
766 },
767};
768
769static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
770 .cmd_rcgr = 0x1e738,
771 .mnd_width = 16,
772 .hid_width = 5,
773 .parent_map = gcc_parent_map_0,
774 .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
775 .clkr.hw.init = &(struct clk_init_data){
776 .name = "gcc_qupv3_wrap2_s5_clk_src",
777 .parent_data = gcc_parents_0,
778 .num_parents = 4,
779 .flags = CLK_SET_RATE_PARENT,
780 .ops = &clk_rcg2_ops,
781 },
782};
783
784static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
785 F(400000, P_BI_TCXO, 12, 1, 4),
786 F(9600000, P_BI_TCXO, 2, 0, 0),
787 F(19200000, P_BI_TCXO, 1, 0, 0),
788 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
789 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
790 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
791 F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
792 { }
793};
794
795static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
796 .cmd_rcgr = 0x1400c,
797 .mnd_width = 8,
798 .hid_width = 5,
799 .parent_map = gcc_parent_map_6,
800 .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
801 .clkr.hw.init = &(struct clk_init_data){
802 .name = "gcc_sdcc2_apps_clk_src",
803 .parent_data = gcc_parents_6,
804 .num_parents = 5,
805 .flags = CLK_SET_RATE_PARENT,
806 .ops = &clk_rcg2_floor_ops,
807 },
808};
809
810static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
811 F(400000, P_BI_TCXO, 12, 1, 4),
812 F(9600000, P_BI_TCXO, 2, 0, 0),
813 F(19200000, P_BI_TCXO, 1, 0, 0),
814 F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
815 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
816 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
817 { }
818};
819
820static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
821 .cmd_rcgr = 0x1600c,
822 .mnd_width = 8,
823 .hid_width = 5,
824 .parent_map = gcc_parent_map_3,
825 .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
826 .clkr.hw.init = &(struct clk_init_data){
827 .name = "gcc_sdcc4_apps_clk_src",
828 .parent_data = gcc_parents_3,
829 .num_parents = 3,
830 .flags = CLK_SET_RATE_PARENT,
831 .ops = &clk_rcg2_floor_ops,
832 },
833};
834
835static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
836 F(105495, P_BI_TCXO, 2, 1, 91),
837 { }
838};
839
840static struct clk_rcg2 gcc_tsif_ref_clk_src = {
841 .cmd_rcgr = 0x36010,
842 .mnd_width = 8,
843 .hid_width = 5,
844 .parent_map = gcc_parent_map_7,
845 .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
846 .clkr.hw.init = &(struct clk_init_data){
847 .name = "gcc_tsif_ref_clk_src",
848 .parent_data = gcc_parents_7,
849 .num_parents = 5,
850 .flags = CLK_SET_RATE_PARENT,
851 .ops = &clk_rcg2_ops,
852 },
853};
854
855static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
856 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
857 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
858 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
859 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
860 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
861 { }
862};
863
864static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
865 .cmd_rcgr = 0x75020,
866 .mnd_width = 8,
867 .hid_width = 5,
868 .parent_map = gcc_parent_map_0,
869 .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
870 .clkr.hw.init = &(struct clk_init_data){
871 .name = "gcc_ufs_card_axi_clk_src",
872 .parent_data = gcc_parents_0,
873 .num_parents = 4,
874 .flags = CLK_SET_RATE_PARENT,
875 .ops = &clk_rcg2_ops,
876 },
877};
878
879static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
880 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
881 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
882 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
883 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
884 { }
885};
886
887static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
888 .cmd_rcgr = 0x75060,
889 .mnd_width = 0,
890 .hid_width = 5,
891 .parent_map = gcc_parent_map_0,
892 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
893 .clkr.hw.init = &(struct clk_init_data){
894 .name = "gcc_ufs_card_ice_core_clk_src",
895 .parent_data = gcc_parents_0,
896 .num_parents = 4,
897 .flags = CLK_SET_RATE_PARENT,
898 .ops = &clk_rcg2_ops,
899 },
900};
901
902static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
903 F(19200000, P_BI_TCXO, 1, 0, 0),
904 { }
905};
906
907static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
908 .cmd_rcgr = 0x75094,
909 .mnd_width = 0,
910 .hid_width = 5,
911 .parent_map = gcc_parent_map_4,
912 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
913 .clkr.hw.init = &(struct clk_init_data){
914 .name = "gcc_ufs_card_phy_aux_clk_src",
915 .parent_data = gcc_parents_4,
916 .num_parents = 2,
917 .flags = CLK_SET_RATE_PARENT,
918 .ops = &clk_rcg2_ops,
919 },
920};
921
922static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
923 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
924 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
925 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
926 { }
927};
928
929static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
930 .cmd_rcgr = 0x75078,
931 .mnd_width = 0,
932 .hid_width = 5,
933 .parent_map = gcc_parent_map_0,
934 .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
935 .clkr.hw.init = &(struct clk_init_data){
936 .name = "gcc_ufs_card_unipro_core_clk_src",
937 .parent_data = gcc_parents_0,
938 .num_parents = 4,
939 .flags = CLK_SET_RATE_PARENT,
940 .ops = &clk_rcg2_ops,
941 },
942};
943
944static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
945 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
946 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
947 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
948 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
949 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
950 { }
951};
952
953static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
954 .cmd_rcgr = 0x77020,
955 .mnd_width = 8,
956 .hid_width = 5,
957 .parent_map = gcc_parent_map_0,
958 .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
959 .clkr.hw.init = &(struct clk_init_data){
960 .name = "gcc_ufs_phy_axi_clk_src",
961 .parent_data = gcc_parents_0,
962 .num_parents = 4,
963 .flags = CLK_SET_RATE_PARENT,
964 .ops = &clk_rcg2_ops,
965 },
966};
967
968static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
969 .cmd_rcgr = 0x77060,
970 .mnd_width = 0,
971 .hid_width = 5,
972 .parent_map = gcc_parent_map_0,
973 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
974 .clkr.hw.init = &(struct clk_init_data){
975 .name = "gcc_ufs_phy_ice_core_clk_src",
976 .parent_data = gcc_parents_0,
977 .num_parents = 4,
978 .flags = CLK_SET_RATE_PARENT,
979 .ops = &clk_rcg2_ops,
980 },
981};
982
983static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
984 .cmd_rcgr = 0x77094,
985 .mnd_width = 0,
986 .hid_width = 5,
987 .parent_map = gcc_parent_map_4,
988 .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
989 .clkr.hw.init = &(struct clk_init_data){
990 .name = "gcc_ufs_phy_phy_aux_clk_src",
991 .parent_data = gcc_parents_4,
992 .num_parents = 2,
993 .flags = CLK_SET_RATE_PARENT,
994 .ops = &clk_rcg2_ops,
995 },
996};
997
998static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
999 .cmd_rcgr = 0x77078,
1000 .mnd_width = 0,
1001 .hid_width = 5,
1002 .parent_map = gcc_parent_map_0,
1003 .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
1004 .clkr.hw.init = &(struct clk_init_data){
1005 .name = "gcc_ufs_phy_unipro_core_clk_src",
1006 .parent_data = gcc_parents_0,
1007 .num_parents = 4,
1008 .flags = CLK_SET_RATE_PARENT,
1009 .ops = &clk_rcg2_ops,
1010 },
1011};
1012
1013static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
1014 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
1015 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
1016 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1017 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
1018 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1019 { }
1020};
1021
1022static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
1023 .cmd_rcgr = 0xf01c,
1024 .mnd_width = 8,
1025 .hid_width = 5,
1026 .parent_map = gcc_parent_map_0,
1027 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1028 .clkr.hw.init = &(struct clk_init_data){
1029 .name = "gcc_usb30_prim_master_clk_src",
1030 .parent_data = gcc_parents_0,
1031 .num_parents = 4,
1032 .flags = CLK_SET_RATE_PARENT,
1033 .ops = &clk_rcg2_ops,
1034 },
1035};
1036
1037static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
1038 F(19200000, P_BI_TCXO, 1, 0, 0),
1039 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
1040 F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
1041 { }
1042};
1043
1044static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
1045 .cmd_rcgr = 0xf034,
1046 .mnd_width = 0,
1047 .hid_width = 5,
1048 .parent_map = gcc_parent_map_0,
1049 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1050 .clkr.hw.init = &(struct clk_init_data){
1051 .name = "gcc_usb30_prim_mock_utmi_clk_src",
1052 .parent_data = gcc_parents_0,
1053 .num_parents = 4,
1054 .flags = CLK_SET_RATE_PARENT,
1055 .ops = &clk_rcg2_ops,
1056 },
1057};
1058
1059static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
1060 .cmd_rcgr = 0x1001c,
1061 .mnd_width = 8,
1062 .hid_width = 5,
1063 .parent_map = gcc_parent_map_0,
1064 .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
1065 .clkr.hw.init = &(struct clk_init_data){
1066 .name = "gcc_usb30_sec_master_clk_src",
1067 .parent_data = gcc_parents_0,
1068 .num_parents = 4,
1069 .flags = CLK_SET_RATE_PARENT,
1070 .ops = &clk_rcg2_ops,
1071 },
1072};
1073
1074static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
1075 .cmd_rcgr = 0x10034,
1076 .mnd_width = 0,
1077 .hid_width = 5,
1078 .parent_map = gcc_parent_map_0,
1079 .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
1080 .clkr.hw.init = &(struct clk_init_data){
1081 .name = "gcc_usb30_sec_mock_utmi_clk_src",
1082 .parent_data = gcc_parents_0,
1083 .num_parents = 4,
1084 .flags = CLK_SET_RATE_PARENT,
1085 .ops = &clk_rcg2_ops,
1086 },
1087};
1088
1089static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
1090 .cmd_rcgr = 0xf060,
1091 .mnd_width = 0,
1092 .hid_width = 5,
1093 .parent_map = gcc_parent_map_2,
1094 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1095 .clkr.hw.init = &(struct clk_init_data){
1096 .name = "gcc_usb3_prim_phy_aux_clk_src",
1097 .parent_data = gcc_parents_2,
1098 .num_parents = 3,
1099 .flags = CLK_SET_RATE_PARENT,
1100 .ops = &clk_rcg2_ops,
1101 },
1102};
1103
1104static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
1105 .cmd_rcgr = 0x10060,
1106 .mnd_width = 0,
1107 .hid_width = 5,
1108 .parent_map = gcc_parent_map_2,
1109 .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
1110 .clkr.hw.init = &(struct clk_init_data){
1111 .name = "gcc_usb3_sec_phy_aux_clk_src",
1112 .parent_data = gcc_parents_2,
1113 .num_parents = 3,
1114 .flags = CLK_SET_RATE_PARENT,
1115 .ops = &clk_rcg2_ops,
1116 },
1117};
1118
1119static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
1120 .halt_reg = 0x90018,
1121 .halt_check = BRANCH_HALT,
1122 .clkr = {
1123 .enable_reg = 0x90018,
1124 .enable_mask = BIT(0),
1125 .hw.init = &(struct clk_init_data){
1126 .name = "gcc_aggre_noc_pcie_tbu_clk",
1127 .ops = &clk_branch2_ops,
1128 },
1129 },
1130};
1131
1132static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
1133 .halt_reg = 0x750c0,
1134 .halt_check = BRANCH_HALT,
1135 .hwcg_reg = 0x750c0,
1136 .hwcg_bit = 1,
1137 .clkr = {
1138 .enable_reg = 0x750c0,
1139 .enable_mask = BIT(0),
1140 .hw.init = &(struct clk_init_data){
1141 .name = "gcc_aggre_ufs_card_axi_clk",
1142 .parent_hws = (const struct clk_hw *[]){
1143 &gcc_ufs_card_axi_clk_src.clkr.hw },
1144 .num_parents = 1,
1145 .flags = CLK_SET_RATE_PARENT,
1146 .ops = &clk_branch2_ops,
1147 },
1148 },
1149};
1150
1151static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
1152 .halt_reg = 0x750c0,
1153 .halt_check = BRANCH_HALT,
1154 .hwcg_reg = 0x750c0,
1155 .hwcg_bit = 1,
1156 .clkr = {
1157 .enable_reg = 0x750c0,
1158 .enable_mask = BIT(1),
1159 .hw.init = &(struct clk_init_data){
1160 .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
1161 .parent_hws = (const struct clk_hw *[]){
1162 &gcc_aggre_ufs_card_axi_clk.clkr.hw },
1163 .num_parents = 1,
1164 .flags = CLK_SET_RATE_PARENT,
1165 .ops = &clk_branch_simple_ops,
1166 },
1167 },
1168};
1169
1170static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
1171 .halt_reg = 0x770c0,
1172 .halt_check = BRANCH_HALT,
1173 .hwcg_reg = 0x770c0,
1174 .hwcg_bit = 1,
1175 .clkr = {
1176 .enable_reg = 0x770c0,
1177 .enable_mask = BIT(0),
1178 .hw.init = &(struct clk_init_data){
1179 .name = "gcc_aggre_ufs_phy_axi_clk",
1180 .parent_hws = (const struct clk_hw *[]){
1181 &gcc_ufs_phy_axi_clk_src.clkr.hw },
1182 .num_parents = 1,
1183 .flags = CLK_SET_RATE_PARENT,
1184 .ops = &clk_branch2_ops,
1185 },
1186 },
1187};
1188
1189static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1190 .halt_reg = 0x770c0,
1191 .halt_check = BRANCH_HALT,
1192 .hwcg_reg = 0x770c0,
1193 .hwcg_bit = 1,
1194 .clkr = {
1195 .enable_reg = 0x770c0,
1196 .enable_mask = BIT(1),
1197 .hw.init = &(struct clk_init_data){
1198 .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1199 .parent_hws = (const struct clk_hw *[]){
1200 &gcc_aggre_ufs_phy_axi_clk.clkr.hw },
1201 .num_parents = 1,
1202 .flags = CLK_SET_RATE_PARENT,
1203 .ops = &clk_branch_simple_ops,
1204 },
1205 },
1206};
1207
1208static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
1209 .halt_reg = 0xf07c,
1210 .halt_check = BRANCH_HALT,
1211 .clkr = {
1212 .enable_reg = 0xf07c,
1213 .enable_mask = BIT(0),
1214 .hw.init = &(struct clk_init_data){
1215 .name = "gcc_aggre_usb3_prim_axi_clk",
1216 .parent_hws = (const struct clk_hw *[]){
1217 &gcc_usb30_prim_master_clk_src.clkr.hw },
1218 .num_parents = 1,
1219 .flags = CLK_SET_RATE_PARENT,
1220 .ops = &clk_branch2_ops,
1221 },
1222 },
1223};
1224
1225static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
1226 .halt_reg = 0x1007c,
1227 .halt_check = BRANCH_HALT,
1228 .clkr = {
1229 .enable_reg = 0x1007c,
1230 .enable_mask = BIT(0),
1231 .hw.init = &(struct clk_init_data){
1232 .name = "gcc_aggre_usb3_sec_axi_clk",
1233 .parent_hws = (const struct clk_hw *[]){
1234 &gcc_usb30_sec_master_clk_src.clkr.hw },
1235 .num_parents = 1,
1236 .flags = CLK_SET_RATE_PARENT,
1237 .ops = &clk_branch2_ops,
1238 },
1239 },
1240};
1241
1242static struct clk_branch gcc_boot_rom_ahb_clk = {
1243 .halt_reg = 0x38004,
1244 .halt_check = BRANCH_HALT_VOTED,
1245 .hwcg_reg = 0x38004,
1246 .hwcg_bit = 1,
1247 .clkr = {
1248 .enable_reg = 0x52004,
1249 .enable_mask = BIT(10),
1250 .hw.init = &(struct clk_init_data){
1251 .name = "gcc_boot_rom_ahb_clk",
1252 .ops = &clk_branch2_ops,
1253 },
1254 },
1255};
1256
1257/*
1258 * Clock ON depends on external parent 'config noc', so cant poll
1259 * delay and also mark as crtitical for camss boot
1260 */
1261static struct clk_branch gcc_camera_ahb_clk = {
1262 .halt_reg = 0xb008,
1263 .halt_check = BRANCH_HALT_DELAY,
1264 .hwcg_reg = 0xb008,
1265 .hwcg_bit = 1,
1266 .clkr = {
1267 .enable_reg = 0xb008,
1268 .enable_mask = BIT(0),
1269 .hw.init = &(struct clk_init_data){
1270 .name = "gcc_camera_ahb_clk",
1271 .flags = CLK_IS_CRITICAL,
1272 .ops = &clk_branch2_ops,
1273 },
1274 },
1275};
1276
1277static struct clk_branch gcc_camera_hf_axi_clk = {
1278 .halt_reg = 0xb030,
1279 .halt_check = BRANCH_HALT,
1280 .clkr = {
1281 .enable_reg = 0xb030,
1282 .enable_mask = BIT(0),
1283 .hw.init = &(struct clk_init_data){
1284 .name = "gcc_camera_hf_axi_clk",
1285 .ops = &clk_branch2_ops,
1286 },
1287 },
1288};
1289
1290static struct clk_branch gcc_camera_sf_axi_clk = {
1291 .halt_reg = 0xb034,
1292 .halt_check = BRANCH_HALT,
1293 .clkr = {
1294 .enable_reg = 0xb034,
1295 .enable_mask = BIT(0),
1296 .hw.init = &(struct clk_init_data){
1297 .name = "gcc_camera_sf_axi_clk",
1298 .ops = &clk_branch2_ops,
1299 },
1300 },
1301};
1302
1303/* XO critical input to camss, so no need to poll */
1304static struct clk_branch gcc_camera_xo_clk = {
1305 .halt_reg = 0xb044,
1306 .halt_check = BRANCH_HALT_DELAY,
1307 .clkr = {
1308 .enable_reg = 0xb044,
1309 .enable_mask = BIT(0),
1310 .hw.init = &(struct clk_init_data){
1311 .name = "gcc_camera_xo_clk",
1312 .flags = CLK_IS_CRITICAL,
1313 .ops = &clk_branch2_ops,
1314 },
1315 },
1316};
1317
1318static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
1319 .halt_reg = 0xf078,
1320 .halt_check = BRANCH_HALT,
1321 .clkr = {
1322 .enable_reg = 0xf078,
1323 .enable_mask = BIT(0),
1324 .hw.init = &(struct clk_init_data){
1325 .name = "gcc_cfg_noc_usb3_prim_axi_clk",
1326 .parent_hws = (const struct clk_hw *[]){
1327 &gcc_usb30_prim_master_clk_src.clkr.hw },
1328 .num_parents = 1,
1329 .flags = CLK_SET_RATE_PARENT,
1330 .ops = &clk_branch2_ops,
1331 },
1332 },
1333};
1334
1335static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
1336 .halt_reg = 0x10078,
1337 .halt_check = BRANCH_HALT,
1338 .clkr = {
1339 .enable_reg = 0x10078,
1340 .enable_mask = BIT(0),
1341 .hw.init = &(struct clk_init_data){
1342 .name = "gcc_cfg_noc_usb3_sec_axi_clk",
1343 .parent_hws = (const struct clk_hw *[]){
1344 &gcc_usb30_sec_master_clk_src.clkr.hw },
1345 .num_parents = 1,
1346 .flags = CLK_SET_RATE_PARENT,
1347 .ops = &clk_branch2_ops,
1348 },
1349 },
1350};
1351
1352static struct clk_branch gcc_cpuss_ahb_clk = {
1353 .halt_reg = 0x48000,
1354 .halt_check = BRANCH_HALT_VOTED,
1355 .clkr = {
1356 .enable_reg = 0x52004,
1357 .enable_mask = BIT(21),
1358 .hw.init = &(struct clk_init_data){
1359 .name = "gcc_cpuss_ahb_clk",
1360 .parent_hws = (const struct clk_hw *[]){
1361 &gcc_cpuss_ahb_clk_src.clkr.hw },
1362 .num_parents = 1,
1363 /* required for cpuss */
1364 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1365 .ops = &clk_branch2_ops,
1366 },
1367 },
1368};
1369
1370static struct clk_branch gcc_cpuss_dvm_bus_clk = {
1371 .halt_reg = 0x48190,
1372 .halt_check = BRANCH_HALT,
1373 .clkr = {
1374 .enable_reg = 0x48190,
1375 .enable_mask = BIT(0),
1376 .hw.init = &(struct clk_init_data){
1377 .name = "gcc_cpuss_dvm_bus_clk",
1378 /* required for cpuss */
1379 .flags = CLK_IS_CRITICAL,
1380 .ops = &clk_branch2_ops,
1381 },
1382 },
1383};
1384
1385static struct clk_branch gcc_cpuss_gnoc_clk = {
1386 .halt_reg = 0x48004,
1387 .halt_check = BRANCH_HALT_VOTED,
1388 .hwcg_reg = 0x48004,
1389 .hwcg_bit = 1,
1390 .clkr = {
1391 .enable_reg = 0x52004,
1392 .enable_mask = BIT(22),
1393 .hw.init = &(struct clk_init_data){
1394 .name = "gcc_cpuss_gnoc_clk",
1395 /* required for cpuss */
1396 .flags = CLK_IS_CRITICAL,
1397 .ops = &clk_branch2_ops,
1398 },
1399 },
1400};
1401
1402static struct clk_branch gcc_cpuss_rbcpr_clk = {
1403 .halt_reg = 0x48008,
1404 .halt_check = BRANCH_HALT,
1405 .clkr = {
1406 .enable_reg = 0x48008,
1407 .enable_mask = BIT(0),
1408 .hw.init = &(struct clk_init_data){
1409 .name = "gcc_cpuss_rbcpr_clk",
1410 .ops = &clk_branch2_ops,
1411 },
1412 },
1413};
1414
1415static struct clk_branch gcc_ddrss_gpu_axi_clk = {
1416 .halt_reg = 0x71154,
1417 .halt_check = BRANCH_VOTED,
1418 .clkr = {
1419 .enable_reg = 0x71154,
1420 .enable_mask = BIT(0),
1421 .hw.init = &(struct clk_init_data){
1422 .name = "gcc_ddrss_gpu_axi_clk",
1423 .ops = &clk_branch2_ops,
1424 },
1425 },
1426};
1427
1428/*
1429 * Clock ON depends on external parent 'config noc', so cant poll
1430 * delay and also mark as crtitical for disp boot
1431 */
1432static struct clk_branch gcc_disp_ahb_clk = {
1433 .halt_reg = 0xb00c,
1434 .halt_check = BRANCH_HALT_DELAY,
1435 .hwcg_reg = 0xb00c,
1436 .hwcg_bit = 1,
1437 .clkr = {
1438 .enable_reg = 0xb00c,
1439 .enable_mask = BIT(0),
1440 .hw.init = &(struct clk_init_data){
1441 .name = "gcc_disp_ahb_clk",
1442 .flags = CLK_IS_CRITICAL,
1443 .ops = &clk_branch2_ops,
1444 },
1445 },
1446};
1447
1448static struct clk_branch gcc_disp_hf_axi_clk = {
1449 .halt_reg = 0xb038,
1450 .halt_check = BRANCH_HALT,
1451 .clkr = {
1452 .enable_reg = 0xb038,
1453 .enable_mask = BIT(0),
1454 .hw.init = &(struct clk_init_data){
1455 .name = "gcc_disp_hf_axi_clk",
1456 .ops = &clk_branch2_ops,
1457 },
1458 },
1459};
1460
1461static struct clk_branch gcc_disp_sf_axi_clk = {
1462 .halt_reg = 0xb03c,
1463 .halt_check = BRANCH_HALT,
1464 .clkr = {
1465 .enable_reg = 0xb03c,
1466 .enable_mask = BIT(0),
1467 .hw.init = &(struct clk_init_data){
1468 .name = "gcc_disp_sf_axi_clk",
1469 .ops = &clk_branch2_ops,
1470 },
1471 },
1472};
1473
1474/* XO critical input to disp, so no need to poll */
1475static struct clk_branch gcc_disp_xo_clk = {
1476 .halt_reg = 0xb048,
1477 .halt_check = BRANCH_HALT_DELAY,
1478 .clkr = {
1479 .enable_reg = 0xb048,
1480 .enable_mask = BIT(0),
1481 .hw.init = &(struct clk_init_data){
1482 .name = "gcc_disp_xo_clk",
1483 .flags = CLK_IS_CRITICAL,
1484 .ops = &clk_branch2_ops,
1485 },
1486 },
1487};
1488
1489static struct clk_branch gcc_emac_axi_clk = {
1490 .halt_reg = 0x6010,
1491 .halt_check = BRANCH_HALT,
1492 .clkr = {
1493 .enable_reg = 0x6010,
1494 .enable_mask = BIT(0),
1495 .hw.init = &(struct clk_init_data){
1496 .name = "gcc_emac_axi_clk",
1497 .ops = &clk_branch2_ops,
1498 },
1499 },
1500};
1501
1502static struct clk_branch gcc_emac_ptp_clk = {
1503 .halt_reg = 0x6034,
1504 .halt_check = BRANCH_HALT,
1505 .clkr = {
1506 .enable_reg = 0x6034,
1507 .enable_mask = BIT(0),
1508 .hw.init = &(struct clk_init_data){
1509 .name = "gcc_emac_ptp_clk",
1510 .parent_hws = (const struct clk_hw *[]){
1511 &gcc_emac_ptp_clk_src.clkr.hw },
1512 .num_parents = 1,
1513 .flags = CLK_SET_RATE_PARENT,
1514 .ops = &clk_branch2_ops,
1515 },
1516 },
1517};
1518
1519static struct clk_branch gcc_emac_rgmii_clk = {
1520 .halt_reg = 0x6018,
1521 .halt_check = BRANCH_HALT,
1522 .clkr = {
1523 .enable_reg = 0x6018,
1524 .enable_mask = BIT(0),
1525 .hw.init = &(struct clk_init_data){
1526 .name = "gcc_emac_rgmii_clk",
1527 .parent_hws = (const struct clk_hw *[]){
1528 &gcc_emac_rgmii_clk_src.clkr.hw },
1529 .num_parents = 1,
1530 .flags = CLK_SET_RATE_PARENT,
1531 .ops = &clk_branch2_ops,
1532 },
1533 },
1534};
1535
1536static struct clk_branch gcc_emac_slv_ahb_clk = {
1537 .halt_reg = 0x6014,
1538 .halt_check = BRANCH_HALT,
1539 .hwcg_reg = 0x6014,
1540 .hwcg_bit = 1,
1541 .clkr = {
1542 .enable_reg = 0x6014,
1543 .enable_mask = BIT(0),
1544 .hw.init = &(struct clk_init_data){
1545 .name = "gcc_emac_slv_ahb_clk",
1546 .ops = &clk_branch2_ops,
1547 },
1548 },
1549};
1550
1551static struct clk_branch gcc_gp1_clk = {
1552 .halt_reg = 0x64000,
1553 .halt_check = BRANCH_HALT,
1554 .clkr = {
1555 .enable_reg = 0x64000,
1556 .enable_mask = BIT(0),
1557 .hw.init = &(struct clk_init_data){
1558 .name = "gcc_gp1_clk",
1559 .parent_hws = (const struct clk_hw *[]){
1560 &gcc_gp1_clk_src.clkr.hw },
1561 .num_parents = 1,
1562 .flags = CLK_SET_RATE_PARENT,
1563 .ops = &clk_branch2_ops,
1564 },
1565 },
1566};
1567
1568static struct clk_branch gcc_gp2_clk = {
1569 .halt_reg = 0x65000,
1570 .halt_check = BRANCH_HALT,
1571 .clkr = {
1572 .enable_reg = 0x65000,
1573 .enable_mask = BIT(0),
1574 .hw.init = &(struct clk_init_data){
1575 .name = "gcc_gp2_clk",
1576 .parent_hws = (const struct clk_hw *[]){
1577 &gcc_gp2_clk_src.clkr.hw },
1578 .num_parents = 1,
1579 .flags = CLK_SET_RATE_PARENT,
1580 .ops = &clk_branch2_ops,
1581 },
1582 },
1583};
1584
1585static struct clk_branch gcc_gp3_clk = {
1586 .halt_reg = 0x66000,
1587 .halt_check = BRANCH_HALT,
1588 .clkr = {
1589 .enable_reg = 0x66000,
1590 .enable_mask = BIT(0),
1591 .hw.init = &(struct clk_init_data){
1592 .name = "gcc_gp3_clk",
1593 .parent_hws = (const struct clk_hw *[]){
1594 &gcc_gp3_clk_src.clkr.hw },
1595 .num_parents = 1,
1596 .flags = CLK_SET_RATE_PARENT,
1597 .ops = &clk_branch2_ops,
1598 },
1599 },
1600};
1601
1602static struct clk_branch gcc_gpu_cfg_ahb_clk = {
1603 .halt_reg = 0x71004,
1604 .halt_check = BRANCH_HALT,
1605 .hwcg_reg = 0x71004,
1606 .hwcg_bit = 1,
1607 .clkr = {
1608 .enable_reg = 0x71004,
1609 .enable_mask = BIT(0),
1610 .hw.init = &(struct clk_init_data){
1611 .name = "gcc_gpu_cfg_ahb_clk",
1612 /* required for gpu */
1613 .flags = CLK_IS_CRITICAL,
1614 .ops = &clk_branch2_ops,
1615 },
1616 },
1617};
1618
1619static struct clk_branch gcc_gpu_iref_clk = {
1620 .halt_reg = 0x8c010,
1621 .halt_check = BRANCH_HALT,
1622 .clkr = {
1623 .enable_reg = 0x8c010,
1624 .enable_mask = BIT(0),
1625 .hw.init = &(struct clk_init_data){
1626 .name = "gcc_gpu_iref_clk",
1627 .ops = &clk_branch2_ops,
1628 },
1629 },
1630};
1631
1632static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
1633 .halt_reg = 0x7100c,
1634 .halt_check = BRANCH_VOTED,
1635 .clkr = {
1636 .enable_reg = 0x7100c,
1637 .enable_mask = BIT(0),
1638 .hw.init = &(struct clk_init_data){
1639 .name = "gcc_gpu_memnoc_gfx_clk",
1640 .ops = &clk_branch2_ops,
1641 },
1642 },
1643};
1644
1645static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
1646 .halt_reg = 0x71018,
1647 .halt_check = BRANCH_HALT,
1648 .clkr = {
1649 .enable_reg = 0x71018,
1650 .enable_mask = BIT(0),
1651 .hw.init = &(struct clk_init_data){
1652 .name = "gcc_gpu_snoc_dvm_gfx_clk",
1653 .ops = &clk_branch2_ops,
1654 },
1655 },
1656};
1657
1658static struct clk_branch gcc_npu_at_clk = {
1659 .halt_reg = 0x4d010,
1660 .halt_check = BRANCH_VOTED,
1661 .clkr = {
1662 .enable_reg = 0x4d010,
1663 .enable_mask = BIT(0),
1664 .hw.init = &(struct clk_init_data){
1665 .name = "gcc_npu_at_clk",
1666 .ops = &clk_branch2_ops,
1667 },
1668 },
1669};
1670
1671static struct clk_branch gcc_npu_axi_clk = {
1672 .halt_reg = 0x4d008,
1673 .halt_check = BRANCH_VOTED,
1674 .clkr = {
1675 .enable_reg = 0x4d008,
1676 .enable_mask = BIT(0),
1677 .hw.init = &(struct clk_init_data){
1678 .name = "gcc_npu_axi_clk",
1679 .ops = &clk_branch2_ops,
1680 },
1681 },
1682};
1683
1684static struct clk_branch gcc_npu_cfg_ahb_clk = {
1685 .halt_reg = 0x4d004,
1686 .halt_check = BRANCH_HALT,
1687 .hwcg_reg = 0x4d004,
1688 .hwcg_bit = 1,
1689 .clkr = {
1690 .enable_reg = 0x4d004,
1691 .enable_mask = BIT(0),
1692 .hw.init = &(struct clk_init_data){
1693 .name = "gcc_npu_cfg_ahb_clk",
1694 /* required for npu */
1695 .flags = CLK_IS_CRITICAL,
1696 .ops = &clk_branch2_ops,
1697 },
1698 },
1699};
1700
1701static struct clk_branch gcc_npu_trig_clk = {
1702 .halt_reg = 0x4d00c,
1703 .halt_check = BRANCH_VOTED,
1704 .clkr = {
1705 .enable_reg = 0x4d00c,
1706 .enable_mask = BIT(0),
1707 .hw.init = &(struct clk_init_data){
1708 .name = "gcc_npu_trig_clk",
1709 .ops = &clk_branch2_ops,
1710 },
1711 },
1712};
1713
1714static struct clk_branch gcc_pcie0_phy_refgen_clk = {
1715 .halt_reg = 0x6f02c,
1716 .halt_check = BRANCH_HALT,
1717 .clkr = {
1718 .enable_reg = 0x6f02c,
1719 .enable_mask = BIT(0),
1720 .hw.init = &(struct clk_init_data){
1721 .name = "gcc_pcie0_phy_refgen_clk",
1722 .parent_hws = (const struct clk_hw *[]){
1723 &gcc_pcie_phy_refgen_clk_src.clkr.hw },
1724 .num_parents = 1,
1725 .flags = CLK_SET_RATE_PARENT,
1726 .ops = &clk_branch2_ops,
1727 },
1728 },
1729};
1730
1731static struct clk_branch gcc_pcie1_phy_refgen_clk = {
1732 .halt_reg = 0x6f030,
1733 .halt_check = BRANCH_HALT,
1734 .clkr = {
1735 .enable_reg = 0x6f030,
1736 .enable_mask = BIT(0),
1737 .hw.init = &(struct clk_init_data){
1738 .name = "gcc_pcie1_phy_refgen_clk",
1739 .parent_hws = (const struct clk_hw *[]){
1740 &gcc_pcie_phy_refgen_clk_src.clkr.hw },
1741 .num_parents = 1,
1742 .flags = CLK_SET_RATE_PARENT,
1743 .ops = &clk_branch2_ops,
1744 },
1745 },
1746};
1747
1748static struct clk_branch gcc_pcie_0_aux_clk = {
1749 .halt_reg = 0x6b020,
1750 .halt_check = BRANCH_HALT_VOTED,
1751 .clkr = {
1752 .enable_reg = 0x5200c,
1753 .enable_mask = BIT(3),
1754 .hw.init = &(struct clk_init_data){
1755 .name = "gcc_pcie_0_aux_clk",
1756 .parent_hws = (const struct clk_hw *[]){
1757 &gcc_pcie_0_aux_clk_src.clkr.hw },
1758 .num_parents = 1,
1759 .flags = CLK_SET_RATE_PARENT,
1760 .ops = &clk_branch2_ops,
1761 },
1762 },
1763};
1764
1765static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1766 .halt_reg = 0x6b01c,
1767 .halt_check = BRANCH_HALT_VOTED,
1768 .hwcg_reg = 0x6b01c,
1769 .hwcg_bit = 1,
1770 .clkr = {
1771 .enable_reg = 0x5200c,
1772 .enable_mask = BIT(2),
1773 .hw.init = &(struct clk_init_data){
1774 .name = "gcc_pcie_0_cfg_ahb_clk",
1775 .ops = &clk_branch2_ops,
1776 },
1777 },
1778};
1779
1780static struct clk_branch gcc_pcie_0_clkref_clk = {
1781 .halt_reg = 0x8c00c,
1782 .halt_check = BRANCH_HALT,
1783 .clkr = {
1784 .enable_reg = 0x8c00c,
1785 .enable_mask = BIT(0),
1786 .hw.init = &(struct clk_init_data){
1787 .name = "gcc_pcie_0_clkref_clk",
1788 .ops = &clk_branch2_ops,
1789 },
1790 },
1791};
1792
1793static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1794 .halt_reg = 0x6b018,
1795 .halt_check = BRANCH_HALT_VOTED,
1796 .clkr = {
1797 .enable_reg = 0x5200c,
1798 .enable_mask = BIT(1),
1799 .hw.init = &(struct clk_init_data){
1800 .name = "gcc_pcie_0_mstr_axi_clk",
1801 .ops = &clk_branch2_ops,
1802 },
1803 },
1804};
1805
1806/* Clock ON depends on external parent 'PIPE' clock, so dont poll */
1807static struct clk_branch gcc_pcie_0_pipe_clk = {
1808 .halt_reg = 0x6b024,
1809 .halt_check = BRANCH_HALT_DELAY,
1810 .clkr = {
1811 .enable_reg = 0x5200c,
1812 .enable_mask = BIT(4),
1813 .hw.init = &(struct clk_init_data){
1814 .name = "gcc_pcie_0_pipe_clk",
1815 .ops = &clk_branch2_ops,
1816 },
1817 },
1818};
1819
1820static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1821 .halt_reg = 0x6b014,
1822 .halt_check = BRANCH_HALT_VOTED,
1823 .hwcg_reg = 0x6b014,
1824 .hwcg_bit = 1,
1825 .clkr = {
1826 .enable_reg = 0x5200c,
1827 .enable_mask = BIT(0),
1828 .hw.init = &(struct clk_init_data){
1829 .name = "gcc_pcie_0_slv_axi_clk",
1830 .ops = &clk_branch2_ops,
1831 },
1832 },
1833};
1834
1835static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
1836 .halt_reg = 0x6b010,
1837 .halt_check = BRANCH_HALT_VOTED,
1838 .clkr = {
1839 .enable_reg = 0x5200c,
1840 .enable_mask = BIT(5),
1841 .hw.init = &(struct clk_init_data){
1842 .name = "gcc_pcie_0_slv_q2a_axi_clk",
1843 .ops = &clk_branch2_ops,
1844 },
1845 },
1846};
1847
1848static struct clk_branch gcc_pcie_1_aux_clk = {
1849 .halt_reg = 0x8d020,
1850 .halt_check = BRANCH_HALT_VOTED,
1851 .clkr = {
1852 .enable_reg = 0x52004,
1853 .enable_mask = BIT(29),
1854 .hw.init = &(struct clk_init_data){
1855 .name = "gcc_pcie_1_aux_clk",
1856 .parent_hws = (const struct clk_hw *[]){
1857 &gcc_pcie_1_aux_clk_src.clkr.hw },
1858 .num_parents = 1,
1859 .flags = CLK_SET_RATE_PARENT,
1860 .ops = &clk_branch2_ops,
1861 },
1862 },
1863};
1864
1865static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1866 .halt_reg = 0x8d01c,
1867 .halt_check = BRANCH_HALT_VOTED,
1868 .hwcg_reg = 0x8d01c,
1869 .hwcg_bit = 1,
1870 .clkr = {
1871 .enable_reg = 0x52004,
1872 .enable_mask = BIT(28),
1873 .hw.init = &(struct clk_init_data){
1874 .name = "gcc_pcie_1_cfg_ahb_clk",
1875 .ops = &clk_branch2_ops,
1876 },
1877 },
1878};
1879
1880static struct clk_branch gcc_pcie_1_clkref_clk = {
1881 .halt_reg = 0x8c02c,
1882 .halt_check = BRANCH_HALT,
1883 .clkr = {
1884 .enable_reg = 0x8c02c,
1885 .enable_mask = BIT(0),
1886 .hw.init = &(struct clk_init_data){
1887 .name = "gcc_pcie_1_clkref_clk",
1888 .ops = &clk_branch2_ops,
1889 },
1890 },
1891};
1892
1893static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1894 .halt_reg = 0x8d018,
1895 .halt_check = BRANCH_HALT_VOTED,
1896 .clkr = {
1897 .enable_reg = 0x52004,
1898 .enable_mask = BIT(27),
1899 .hw.init = &(struct clk_init_data){
1900 .name = "gcc_pcie_1_mstr_axi_clk",
1901 .ops = &clk_branch2_ops,
1902 },
1903 },
1904};
1905
1906/* Clock ON depends on external parent 'PIPE' clock, so dont poll */
1907static struct clk_branch gcc_pcie_1_pipe_clk = {
1908 .halt_reg = 0x8d024,
1909 .halt_check = BRANCH_HALT_DELAY,
1910 .clkr = {
1911 .enable_reg = 0x52004,
1912 .enable_mask = BIT(30),
1913 .hw.init = &(struct clk_init_data){
1914 .name = "gcc_pcie_1_pipe_clk",
1915 .ops = &clk_branch2_ops,
1916 },
1917 },
1918};
1919
1920static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1921 .halt_reg = 0x8d014,
1922 .halt_check = BRANCH_HALT_VOTED,
1923 .hwcg_reg = 0x8d014,
1924 .hwcg_bit = 1,
1925 .clkr = {
1926 .enable_reg = 0x52004,
1927 .enable_mask = BIT(26),
1928 .hw.init = &(struct clk_init_data){
1929 .name = "gcc_pcie_1_slv_axi_clk",
1930 .ops = &clk_branch2_ops,
1931 },
1932 },
1933};
1934
1935static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
1936 .halt_reg = 0x8d010,
1937 .halt_check = BRANCH_HALT_VOTED,
1938 .clkr = {
1939 .enable_reg = 0x52004,
1940 .enable_mask = BIT(25),
1941 .hw.init = &(struct clk_init_data){
1942 .name = "gcc_pcie_1_slv_q2a_axi_clk",
1943 .ops = &clk_branch2_ops,
1944 },
1945 },
1946};
1947
1948static struct clk_branch gcc_pcie_phy_aux_clk = {
1949 .halt_reg = 0x6f004,
1950 .halt_check = BRANCH_HALT,
1951 .clkr = {
1952 .enable_reg = 0x6f004,
1953 .enable_mask = BIT(0),
1954 .hw.init = &(struct clk_init_data){
1955 .name = "gcc_pcie_phy_aux_clk",
1956 .parent_hws = (const struct clk_hw *[]){
1957 &gcc_pcie_0_aux_clk_src.clkr.hw },
1958 .num_parents = 1,
1959 .flags = CLK_SET_RATE_PARENT,
1960 .ops = &clk_branch2_ops,
1961 },
1962 },
1963};
1964
1965static struct clk_branch gcc_pdm2_clk = {
1966 .halt_reg = 0x3300c,
1967 .halt_check = BRANCH_HALT,
1968 .clkr = {
1969 .enable_reg = 0x3300c,
1970 .enable_mask = BIT(0),
1971 .hw.init = &(struct clk_init_data){
1972 .name = "gcc_pdm2_clk",
1973 .parent_hws = (const struct clk_hw *[]){
1974 &gcc_pdm2_clk_src.clkr.hw },
1975 .num_parents = 1,
1976 .flags = CLK_SET_RATE_PARENT,
1977 .ops = &clk_branch2_ops,
1978 },
1979 },
1980};
1981
1982static struct clk_branch gcc_pdm_ahb_clk = {
1983 .halt_reg = 0x33004,
1984 .halt_check = BRANCH_HALT,
1985 .hwcg_reg = 0x33004,
1986 .hwcg_bit = 1,
1987 .clkr = {
1988 .enable_reg = 0x33004,
1989 .enable_mask = BIT(0),
1990 .hw.init = &(struct clk_init_data){
1991 .name = "gcc_pdm_ahb_clk",
1992 .ops = &clk_branch2_ops,
1993 },
1994 },
1995};
1996
1997static struct clk_branch gcc_pdm_xo4_clk = {
1998 .halt_reg = 0x33008,
1999 .halt_check = BRANCH_HALT,
2000 .clkr = {
2001 .enable_reg = 0x33008,
2002 .enable_mask = BIT(0),
2003 .hw.init = &(struct clk_init_data){
2004 .name = "gcc_pdm_xo4_clk",
2005 .ops = &clk_branch2_ops,
2006 },
2007 },
2008};
2009
2010static struct clk_branch gcc_prng_ahb_clk = {
2011 .halt_reg = 0x34004,
2012 .halt_check = BRANCH_HALT_VOTED,
2013 .clkr = {
2014 .enable_reg = 0x52004,
2015 .enable_mask = BIT(13),
2016 .hw.init = &(struct clk_init_data){
2017 .name = "gcc_prng_ahb_clk",
2018 .ops = &clk_branch2_ops,
2019 },
2020 },
2021};
2022
2023static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
2024 .halt_reg = 0xb018,
2025 .halt_check = BRANCH_HALT,
2026 .hwcg_reg = 0xb018,
2027 .hwcg_bit = 1,
2028 .clkr = {
2029 .enable_reg = 0xb018,
2030 .enable_mask = BIT(0),
2031 .hw.init = &(struct clk_init_data){
2032 .name = "gcc_qmip_camera_nrt_ahb_clk",
2033 .ops = &clk_branch2_ops,
2034 },
2035 },
2036};
2037
2038static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
2039 .halt_reg = 0xb01c,
2040 .halt_check = BRANCH_HALT,
2041 .hwcg_reg = 0xb01c,
2042 .hwcg_bit = 1,
2043 .clkr = {
2044 .enable_reg = 0xb01c,
2045 .enable_mask = BIT(0),
2046 .hw.init = &(struct clk_init_data){
2047 .name = "gcc_qmip_camera_rt_ahb_clk",
2048 .ops = &clk_branch2_ops,
2049 },
2050 },
2051};
2052
2053static struct clk_branch gcc_qmip_disp_ahb_clk = {
2054 .halt_reg = 0xb020,
2055 .halt_check = BRANCH_HALT,
2056 .hwcg_reg = 0xb020,
2057 .hwcg_bit = 1,
2058 .clkr = {
2059 .enable_reg = 0xb020,
2060 .enable_mask = BIT(0),
2061 .hw.init = &(struct clk_init_data){
2062 .name = "gcc_qmip_disp_ahb_clk",
2063 .ops = &clk_branch2_ops,
2064 },
2065 },
2066};
2067
2068static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
2069 .halt_reg = 0xb010,
2070 .halt_check = BRANCH_HALT,
2071 .hwcg_reg = 0xb010,
2072 .hwcg_bit = 1,
2073 .clkr = {
2074 .enable_reg = 0xb010,
2075 .enable_mask = BIT(0),
2076 .hw.init = &(struct clk_init_data){
2077 .name = "gcc_qmip_video_cvp_ahb_clk",
2078 .ops = &clk_branch2_ops,
2079 },
2080 },
2081};
2082
2083static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
2084 .halt_reg = 0xb014,
2085 .halt_check = BRANCH_HALT,
2086 .hwcg_reg = 0xb014,
2087 .hwcg_bit = 1,
2088 .clkr = {
2089 .enable_reg = 0xb014,
2090 .enable_mask = BIT(0),
2091 .hw.init = &(struct clk_init_data){
2092 .name = "gcc_qmip_video_vcodec_ahb_clk",
2093 .ops = &clk_branch2_ops,
2094 },
2095 },
2096};
2097
2098static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
2099 .halt_reg = 0x4b000,
2100 .halt_check = BRANCH_HALT,
2101 .clkr = {
2102 .enable_reg = 0x4b000,
2103 .enable_mask = BIT(0),
2104 .hw.init = &(struct clk_init_data){
2105 .name = "gcc_qspi_cnoc_periph_ahb_clk",
2106 .ops = &clk_branch2_ops,
2107 },
2108 },
2109};
2110
2111static struct clk_branch gcc_qspi_core_clk = {
2112 .halt_reg = 0x4b004,
2113 .halt_check = BRANCH_HALT,
2114 .clkr = {
2115 .enable_reg = 0x4b004,
2116 .enable_mask = BIT(0),
2117 .hw.init = &(struct clk_init_data){
2118 .name = "gcc_qspi_core_clk",
2119 .parent_hws = (const struct clk_hw *[]){
2120 &gcc_qspi_core_clk_src.clkr.hw },
2121 .num_parents = 1,
2122 .flags = CLK_SET_RATE_PARENT,
2123 .ops = &clk_branch2_ops,
2124 },
2125 },
2126};
2127
2128static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
2129 .halt_reg = 0x17144,
2130 .halt_check = BRANCH_HALT_VOTED,
2131 .clkr = {
2132 .enable_reg = 0x5200c,
2133 .enable_mask = BIT(10),
2134 .hw.init = &(struct clk_init_data){
2135 .name = "gcc_qupv3_wrap0_s0_clk",
2136 .parent_hws = (const struct clk_hw *[]){
2137 &gcc_qupv3_wrap0_s0_clk_src.clkr.hw },
2138 .num_parents = 1,
2139 .flags = CLK_SET_RATE_PARENT,
2140 .ops = &clk_branch2_ops,
2141 },
2142 },
2143};
2144
2145static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
2146 .halt_reg = 0x17274,
2147 .halt_check = BRANCH_HALT_VOTED,
2148 .clkr = {
2149 .enable_reg = 0x5200c,
2150 .enable_mask = BIT(11),
2151 .hw.init = &(struct clk_init_data){
2152 .name = "gcc_qupv3_wrap0_s1_clk",
2153 .parent_hws = (const struct clk_hw *[]){
2154 &gcc_qupv3_wrap0_s1_clk_src.clkr.hw },
2155 .num_parents = 1,
2156 .flags = CLK_SET_RATE_PARENT,
2157 .ops = &clk_branch2_ops,
2158 },
2159 },
2160};
2161
2162static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
2163 .halt_reg = 0x173a4,
2164 .halt_check = BRANCH_HALT_VOTED,
2165 .clkr = {
2166 .enable_reg = 0x5200c,
2167 .enable_mask = BIT(12),
2168 .hw.init = &(struct clk_init_data){
2169 .name = "gcc_qupv3_wrap0_s2_clk",
2170 .parent_hws = (const struct clk_hw *[]){
2171 &gcc_qupv3_wrap0_s2_clk_src.clkr.hw },
2172 .num_parents = 1,
2173 .flags = CLK_SET_RATE_PARENT,
2174 .ops = &clk_branch2_ops,
2175 },
2176 },
2177};
2178
2179static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
2180 .halt_reg = 0x174d4,
2181 .halt_check = BRANCH_HALT_VOTED,
2182 .clkr = {
2183 .enable_reg = 0x5200c,
2184 .enable_mask = BIT(13),
2185 .hw.init = &(struct clk_init_data){
2186 .name = "gcc_qupv3_wrap0_s3_clk",
2187 .parent_hws = (const struct clk_hw *[]){
2188 &gcc_qupv3_wrap0_s3_clk_src.clkr.hw },
2189 .num_parents = 1,
2190 .flags = CLK_SET_RATE_PARENT,
2191 .ops = &clk_branch2_ops,
2192 },
2193 },
2194};
2195
2196static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
2197 .halt_reg = 0x17604,
2198 .halt_check = BRANCH_HALT_VOTED,
2199 .clkr = {
2200 .enable_reg = 0x5200c,
2201 .enable_mask = BIT(14),
2202 .hw.init = &(struct clk_init_data){
2203 .name = "gcc_qupv3_wrap0_s4_clk",
2204 .parent_hws = (const struct clk_hw *[]){
2205 &gcc_qupv3_wrap0_s4_clk_src.clkr.hw },
2206 .num_parents = 1,
2207 .flags = CLK_SET_RATE_PARENT,
2208 .ops = &clk_branch2_ops,
2209 },
2210 },
2211};
2212
2213static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
2214 .halt_reg = 0x17734,
2215 .halt_check = BRANCH_HALT_VOTED,
2216 .clkr = {
2217 .enable_reg = 0x5200c,
2218 .enable_mask = BIT(15),
2219 .hw.init = &(struct clk_init_data){
2220 .name = "gcc_qupv3_wrap0_s5_clk",
2221 .parent_hws = (const struct clk_hw *[]){
2222 &gcc_qupv3_wrap0_s5_clk_src.clkr.hw },
2223 .num_parents = 1,
2224 .flags = CLK_SET_RATE_PARENT,
2225 .ops = &clk_branch2_ops,
2226 },
2227 },
2228};
2229
2230static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
2231 .halt_reg = 0x17864,
2232 .halt_check = BRANCH_HALT_VOTED,
2233 .clkr = {
2234 .enable_reg = 0x5200c,
2235 .enable_mask = BIT(16),
2236 .hw.init = &(struct clk_init_data){
2237 .name = "gcc_qupv3_wrap0_s6_clk",
2238 .parent_hws = (const struct clk_hw *[]){
2239 &gcc_qupv3_wrap0_s6_clk_src.clkr.hw },
2240 .num_parents = 1,
2241 .flags = CLK_SET_RATE_PARENT,
2242 .ops = &clk_branch2_ops,
2243 },
2244 },
2245};
2246
2247static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
2248 .halt_reg = 0x17994,
2249 .halt_check = BRANCH_HALT_VOTED,
2250 .clkr = {
2251 .enable_reg = 0x5200c,
2252 .enable_mask = BIT(17),
2253 .hw.init = &(struct clk_init_data){
2254 .name = "gcc_qupv3_wrap0_s7_clk",
2255 .parent_hws = (const struct clk_hw *[]){
2256 &gcc_qupv3_wrap0_s7_clk_src.clkr.hw },
2257 .num_parents = 1,
2258 .flags = CLK_SET_RATE_PARENT,
2259 .ops = &clk_branch2_ops,
2260 },
2261 },
2262};
2263
2264static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
2265 .halt_reg = 0x18144,
2266 .halt_check = BRANCH_HALT_VOTED,
2267 .clkr = {
2268 .enable_reg = 0x5200c,
2269 .enable_mask = BIT(22),
2270 .hw.init = &(struct clk_init_data){
2271 .name = "gcc_qupv3_wrap1_s0_clk",
2272 .parent_hws = (const struct clk_hw *[]){
2273 &gcc_qupv3_wrap1_s0_clk_src.clkr.hw },
2274 .num_parents = 1,
2275 .flags = CLK_SET_RATE_PARENT,
2276 .ops = &clk_branch2_ops,
2277 },
2278 },
2279};
2280
2281static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
2282 .halt_reg = 0x18274,
2283 .halt_check = BRANCH_HALT_VOTED,
2284 .clkr = {
2285 .enable_reg = 0x5200c,
2286 .enable_mask = BIT(23),
2287 .hw.init = &(struct clk_init_data){
2288 .name = "gcc_qupv3_wrap1_s1_clk",
2289 .parent_hws = (const struct clk_hw *[]){
2290 &gcc_qupv3_wrap1_s1_clk_src.clkr.hw },
2291 .num_parents = 1,
2292 .flags = CLK_SET_RATE_PARENT,
2293 .ops = &clk_branch2_ops,
2294 },
2295 },
2296};
2297
2298static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
2299 .halt_reg = 0x183a4,
2300 .halt_check = BRANCH_HALT_VOTED,
2301 .clkr = {
2302 .enable_reg = 0x5200c,
2303 .enable_mask = BIT(24),
2304 .hw.init = &(struct clk_init_data){
2305 .name = "gcc_qupv3_wrap1_s2_clk",
2306 .parent_hws = (const struct clk_hw *[]){
2307 &gcc_qupv3_wrap1_s2_clk_src.clkr.hw },
2308 .num_parents = 1,
2309 .flags = CLK_SET_RATE_PARENT,
2310 .ops = &clk_branch2_ops,
2311 },
2312 },
2313};
2314
2315static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
2316 .halt_reg = 0x184d4,
2317 .halt_check = BRANCH_HALT_VOTED,
2318 .clkr = {
2319 .enable_reg = 0x5200c,
2320 .enable_mask = BIT(25),
2321 .hw.init = &(struct clk_init_data){
2322 .name = "gcc_qupv3_wrap1_s3_clk",
2323 .parent_hws = (const struct clk_hw *[]){
2324 &gcc_qupv3_wrap1_s3_clk_src.clkr.hw },
2325 .num_parents = 1,
2326 .flags = CLK_SET_RATE_PARENT,
2327 .ops = &clk_branch2_ops,
2328 },
2329 },
2330};
2331
2332static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
2333 .halt_reg = 0x18604,
2334 .halt_check = BRANCH_HALT_VOTED,
2335 .clkr = {
2336 .enable_reg = 0x5200c,
2337 .enable_mask = BIT(26),
2338 .hw.init = &(struct clk_init_data){
2339 .name = "gcc_qupv3_wrap1_s4_clk",
2340 .parent_hws = (const struct clk_hw *[]){
2341 &gcc_qupv3_wrap1_s4_clk_src.clkr.hw },
2342 .num_parents = 1,
2343 .flags = CLK_SET_RATE_PARENT,
2344 .ops = &clk_branch2_ops,
2345 },
2346 },
2347};
2348
2349static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
2350 .halt_reg = 0x18734,
2351 .halt_check = BRANCH_HALT_VOTED,
2352 .clkr = {
2353 .enable_reg = 0x5200c,
2354 .enable_mask = BIT(27),
2355 .hw.init = &(struct clk_init_data){
2356 .name = "gcc_qupv3_wrap1_s5_clk",
2357 .parent_hws = (const struct clk_hw *[]){
2358 &gcc_qupv3_wrap1_s5_clk_src.clkr.hw },
2359 .num_parents = 1,
2360 .flags = CLK_SET_RATE_PARENT,
2361 .ops = &clk_branch2_ops,
2362 },
2363 },
2364};
2365
2366static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
2367 .halt_reg = 0x1e144,
2368 .halt_check = BRANCH_HALT_VOTED,
2369 .clkr = {
2370 .enable_reg = 0x52014,
2371 .enable_mask = BIT(4),
2372 .hw.init = &(struct clk_init_data){
2373 .name = "gcc_qupv3_wrap2_s0_clk",
2374 .parent_hws = (const struct clk_hw *[]){
2375 &gcc_qupv3_wrap2_s0_clk_src.clkr.hw },
2376 .num_parents = 1,
2377 .flags = CLK_SET_RATE_PARENT,
2378 .ops = &clk_branch2_ops,
2379 },
2380 },
2381};
2382
2383static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
2384 .halt_reg = 0x1e274,
2385 .halt_check = BRANCH_HALT_VOTED,
2386 .clkr = {
2387 .enable_reg = 0x52014,
2388 .enable_mask = BIT(5),
2389 .hw.init = &(struct clk_init_data){
2390 .name = "gcc_qupv3_wrap2_s1_clk",
2391 .parent_hws = (const struct clk_hw *[]){
2392 &gcc_qupv3_wrap2_s1_clk_src.clkr.hw },
2393 .num_parents = 1,
2394 .flags = CLK_SET_RATE_PARENT,
2395 .ops = &clk_branch2_ops,
2396 },
2397 },
2398};
2399
2400static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
2401 .halt_reg = 0x1e3a4,
2402 .halt_check = BRANCH_HALT_VOTED,
2403 .clkr = {
2404 .enable_reg = 0x52014,
2405 .enable_mask = BIT(6),
2406 .hw.init = &(struct clk_init_data){
2407 .name = "gcc_qupv3_wrap2_s2_clk",
2408 .parent_hws = (const struct clk_hw *[]){
2409 &gcc_qupv3_wrap2_s2_clk_src.clkr.hw },
2410 .num_parents = 1,
2411 .flags = CLK_SET_RATE_PARENT,
2412 .ops = &clk_branch2_ops,
2413 },
2414 },
2415};
2416
2417static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
2418 .halt_reg = 0x1e4d4,
2419 .halt_check = BRANCH_HALT_VOTED,
2420 .clkr = {
2421 .enable_reg = 0x52014,
2422 .enable_mask = BIT(7),
2423 .hw.init = &(struct clk_init_data){
2424 .name = "gcc_qupv3_wrap2_s3_clk",
2425 .parent_hws = (const struct clk_hw *[]){
2426 &gcc_qupv3_wrap2_s3_clk_src.clkr.hw },
2427 .num_parents = 1,
2428 .flags = CLK_SET_RATE_PARENT,
2429 .ops = &clk_branch2_ops,
2430 },
2431 },
2432};
2433
2434static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
2435 .halt_reg = 0x1e604,
2436 .halt_check = BRANCH_HALT_VOTED,
2437 .clkr = {
2438 .enable_reg = 0x52014,
2439 .enable_mask = BIT(8),
2440 .hw.init = &(struct clk_init_data){
2441 .name = "gcc_qupv3_wrap2_s4_clk",
2442 .parent_hws = (const struct clk_hw *[]){
2443 &gcc_qupv3_wrap2_s4_clk_src.clkr.hw },
2444 .num_parents = 1,
2445 .flags = CLK_SET_RATE_PARENT,
2446 .ops = &clk_branch2_ops,
2447 },
2448 },
2449};
2450
2451static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
2452 .halt_reg = 0x1e734,
2453 .halt_check = BRANCH_HALT_VOTED,
2454 .clkr = {
2455 .enable_reg = 0x52014,
2456 .enable_mask = BIT(9),
2457 .hw.init = &(struct clk_init_data){
2458 .name = "gcc_qupv3_wrap2_s5_clk",
2459 .parent_hws = (const struct clk_hw *[]){
2460 &gcc_qupv3_wrap2_s5_clk_src.clkr.hw },
2461 .num_parents = 1,
2462 .flags = CLK_SET_RATE_PARENT,
2463 .ops = &clk_branch2_ops,
2464 },
2465 },
2466};
2467
2468static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
2469 .halt_reg = 0x17004,
2470 .halt_check = BRANCH_HALT_VOTED,
2471 .clkr = {
2472 .enable_reg = 0x5200c,
2473 .enable_mask = BIT(6),
2474 .hw.init = &(struct clk_init_data){
2475 .name = "gcc_qupv3_wrap_0_m_ahb_clk",
2476 .ops = &clk_branch2_ops,
2477 },
2478 },
2479};
2480
2481static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
2482 .halt_reg = 0x17008,
2483 .halt_check = BRANCH_HALT_VOTED,
2484 .hwcg_reg = 0x17008,
2485 .hwcg_bit = 1,
2486 .clkr = {
2487 .enable_reg = 0x5200c,
2488 .enable_mask = BIT(7),
2489 .hw.init = &(struct clk_init_data){
2490 .name = "gcc_qupv3_wrap_0_s_ahb_clk",
2491 .ops = &clk_branch2_ops,
2492 },
2493 },
2494};
2495
2496static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
2497 .halt_reg = 0x18004,
2498 .halt_check = BRANCH_HALT_VOTED,
2499 .clkr = {
2500 .enable_reg = 0x5200c,
2501 .enable_mask = BIT(20),
2502 .hw.init = &(struct clk_init_data){
2503 .name = "gcc_qupv3_wrap_1_m_ahb_clk",
2504 .ops = &clk_branch2_ops,
2505 },
2506 },
2507};
2508
2509static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
2510 .halt_reg = 0x18008,
2511 .halt_check = BRANCH_HALT_VOTED,
2512 .hwcg_reg = 0x18008,
2513 .hwcg_bit = 1,
2514 .clkr = {
2515 .enable_reg = 0x5200c,
2516 .enable_mask = BIT(21),
2517 .hw.init = &(struct clk_init_data){
2518 .name = "gcc_qupv3_wrap_1_s_ahb_clk",
2519 .ops = &clk_branch2_ops,
2520 },
2521 },
2522};
2523
2524static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
2525 .halt_reg = 0x1e004,
2526 .halt_check = BRANCH_HALT_VOTED,
2527 .clkr = {
2528 .enable_reg = 0x52014,
2529 .enable_mask = BIT(2),
2530 .hw.init = &(struct clk_init_data){
2531 .name = "gcc_qupv3_wrap_2_m_ahb_clk",
2532 .ops = &clk_branch2_ops,
2533 },
2534 },
2535};
2536
2537static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
2538 .halt_reg = 0x1e008,
2539 .halt_check = BRANCH_HALT_VOTED,
2540 .hwcg_reg = 0x1e008,
2541 .hwcg_bit = 1,
2542 .clkr = {
2543 .enable_reg = 0x52014,
2544 .enable_mask = BIT(1),
2545 .hw.init = &(struct clk_init_data){
2546 .name = "gcc_qupv3_wrap_2_s_ahb_clk",
2547 .ops = &clk_branch2_ops,
2548 },
2549 },
2550};
2551
2552static struct clk_branch gcc_sdcc2_ahb_clk = {
2553 .halt_reg = 0x14008,
2554 .halt_check = BRANCH_HALT,
2555 .clkr = {
2556 .enable_reg = 0x14008,
2557 .enable_mask = BIT(0),
2558 .hw.init = &(struct clk_init_data){
2559 .name = "gcc_sdcc2_ahb_clk",
2560 .ops = &clk_branch2_ops,
2561 },
2562 },
2563};
2564
2565static struct clk_branch gcc_sdcc2_apps_clk = {
2566 .halt_reg = 0x14004,
2567 .halt_check = BRANCH_HALT,
2568 .clkr = {
2569 .enable_reg = 0x14004,
2570 .enable_mask = BIT(0),
2571 .hw.init = &(struct clk_init_data){
2572 .name = "gcc_sdcc2_apps_clk",
2573 .parent_hws = (const struct clk_hw *[]){
2574 &gcc_sdcc2_apps_clk_src.clkr.hw },
2575 .num_parents = 1,
2576 .flags = CLK_SET_RATE_PARENT,
2577 .ops = &clk_branch2_ops,
2578 },
2579 },
2580};
2581
2582static struct clk_branch gcc_sdcc4_ahb_clk = {
2583 .halt_reg = 0x16008,
2584 .halt_check = BRANCH_HALT,
2585 .clkr = {
2586 .enable_reg = 0x16008,
2587 .enable_mask = BIT(0),
2588 .hw.init = &(struct clk_init_data){
2589 .name = "gcc_sdcc4_ahb_clk",
2590 .ops = &clk_branch2_ops,
2591 },
2592 },
2593};
2594
2595static struct clk_branch gcc_sdcc4_apps_clk = {
2596 .halt_reg = 0x16004,
2597 .halt_check = BRANCH_HALT,
2598 .clkr = {
2599 .enable_reg = 0x16004,
2600 .enable_mask = BIT(0),
2601 .hw.init = &(struct clk_init_data){
2602 .name = "gcc_sdcc4_apps_clk",
2603 .parent_hws = (const struct clk_hw *[]){
2604 &gcc_sdcc4_apps_clk_src.clkr.hw },
2605 .num_parents = 1,
2606 .flags = CLK_SET_RATE_PARENT,
2607 .ops = &clk_branch2_ops,
2608 },
2609 },
2610};
2611
2612static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
2613 .halt_reg = 0x4819c,
2614 .halt_check = BRANCH_HALT_VOTED,
2615 .clkr = {
2616 .enable_reg = 0x52004,
2617 .enable_mask = BIT(0),
2618 .hw.init = &(struct clk_init_data){
2619 .name = "gcc_sys_noc_cpuss_ahb_clk",
2620 .parent_hws = (const struct clk_hw *[]){
2621 &gcc_cpuss_ahb_clk_src.clkr.hw },
2622 .num_parents = 1,
2623 /* required for cpuss */
2624 .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
2625 .ops = &clk_branch2_ops,
2626 },
2627 },
2628};
2629
2630static struct clk_branch gcc_tsif_ahb_clk = {
2631 .halt_reg = 0x36004,
2632 .halt_check = BRANCH_HALT,
2633 .clkr = {
2634 .enable_reg = 0x36004,
2635 .enable_mask = BIT(0),
2636 .hw.init = &(struct clk_init_data){
2637 .name = "gcc_tsif_ahb_clk",
2638 .ops = &clk_branch2_ops,
2639 },
2640 },
2641};
2642
2643static struct clk_branch gcc_tsif_inactivity_timers_clk = {
2644 .halt_reg = 0x3600c,
2645 .halt_check = BRANCH_HALT,
2646 .clkr = {
2647 .enable_reg = 0x3600c,
2648 .enable_mask = BIT(0),
2649 .hw.init = &(struct clk_init_data){
2650 .name = "gcc_tsif_inactivity_timers_clk",
2651 .ops = &clk_branch2_ops,
2652 },
2653 },
2654};
2655
2656static struct clk_branch gcc_tsif_ref_clk = {
2657 .halt_reg = 0x36008,
2658 .halt_check = BRANCH_HALT,
2659 .clkr = {
2660 .enable_reg = 0x36008,
2661 .enable_mask = BIT(0),
2662 .hw.init = &(struct clk_init_data){
2663 .name = "gcc_tsif_ref_clk",
2664 .parent_hws = (const struct clk_hw *[]){
2665 &gcc_tsif_ref_clk_src.clkr.hw },
2666 .num_parents = 1,
2667 .flags = CLK_SET_RATE_PARENT,
2668 .ops = &clk_branch2_ops,
2669 },
2670 },
2671};
2672
2673static struct clk_branch gcc_ufs_card_ahb_clk = {
2674 .halt_reg = 0x75014,
2675 .halt_check = BRANCH_HALT,
2676 .hwcg_reg = 0x75014,
2677 .hwcg_bit = 1,
2678 .clkr = {
2679 .enable_reg = 0x75014,
2680 .enable_mask = BIT(0),
2681 .hw.init = &(struct clk_init_data){
2682 .name = "gcc_ufs_card_ahb_clk",
2683 .ops = &clk_branch2_ops,
2684 },
2685 },
2686};
2687
2688static struct clk_branch gcc_ufs_card_axi_clk = {
2689 .halt_reg = 0x75010,
2690 .halt_check = BRANCH_HALT,
2691 .hwcg_reg = 0x75010,
2692 .hwcg_bit = 1,
2693 .clkr = {
2694 .enable_reg = 0x75010,
2695 .enable_mask = BIT(0),
2696 .hw.init = &(struct clk_init_data){
2697 .name = "gcc_ufs_card_axi_clk",
2698 .parent_hws = (const struct clk_hw *[]){
2699 &gcc_ufs_card_axi_clk_src.clkr.hw },
2700 .num_parents = 1,
2701 .flags = CLK_SET_RATE_PARENT,
2702 .ops = &clk_branch2_ops,
2703 },
2704 },
2705};
2706
2707static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
2708 .halt_reg = 0x75010,
2709 .halt_check = BRANCH_HALT,
2710 .hwcg_reg = 0x75010,
2711 .hwcg_bit = 1,
2712 .clkr = {
2713 .enable_reg = 0x75010,
2714 .enable_mask = BIT(1),
2715 .hw.init = &(struct clk_init_data){
2716 .name = "gcc_ufs_card_axi_hw_ctl_clk",
2717 .parent_hws = (const struct clk_hw *[]){
2718 &gcc_ufs_card_axi_clk.clkr.hw },
2719 .num_parents = 1,
2720 .flags = CLK_SET_RATE_PARENT,
2721 .ops = &clk_branch_simple_ops,
2722 },
2723 },
2724};
2725
2726static struct clk_branch gcc_ufs_card_clkref_clk = {
2727 .halt_reg = 0x8c004,
2728 .halt_check = BRANCH_HALT,
2729 .clkr = {
2730 .enable_reg = 0x8c004,
2731 .enable_mask = BIT(0),
2732 .hw.init = &(struct clk_init_data){
2733 .name = "gcc_ufs_card_clkref_clk",
2734 .ops = &clk_branch2_ops,
2735 },
2736 },
2737};
2738
2739static struct clk_branch gcc_ufs_card_ice_core_clk = {
2740 .halt_reg = 0x7505c,
2741 .halt_check = BRANCH_HALT,
2742 .hwcg_reg = 0x7505c,
2743 .hwcg_bit = 1,
2744 .clkr = {
2745 .enable_reg = 0x7505c,
2746 .enable_mask = BIT(0),
2747 .hw.init = &(struct clk_init_data){
2748 .name = "gcc_ufs_card_ice_core_clk",
2749 .parent_hws = (const struct clk_hw *[]){
2750 &gcc_ufs_card_ice_core_clk_src.clkr.hw },
2751 .num_parents = 1,
2752 .flags = CLK_SET_RATE_PARENT,
2753 .ops = &clk_branch2_ops,
2754 },
2755 },
2756};
2757
2758static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
2759 .halt_reg = 0x7505c,
2760 .halt_check = BRANCH_HALT,
2761 .hwcg_reg = 0x7505c,
2762 .hwcg_bit = 1,
2763 .clkr = {
2764 .enable_reg = 0x7505c,
2765 .enable_mask = BIT(1),
2766 .hw.init = &(struct clk_init_data){
2767 .name = "gcc_ufs_card_ice_core_hw_ctl_clk",
2768 .parent_hws = (const struct clk_hw *[]){
2769 &gcc_ufs_card_ice_core_clk.clkr.hw },
2770 .num_parents = 1,
2771 .flags = CLK_SET_RATE_PARENT,
2772 .ops = &clk_branch_simple_ops,
2773 },
2774 },
2775};
2776
2777static struct clk_branch gcc_ufs_card_phy_aux_clk = {
2778 .halt_reg = 0x75090,
2779 .halt_check = BRANCH_HALT,
2780 .hwcg_reg = 0x75090,
2781 .hwcg_bit = 1,
2782 .clkr = {
2783 .enable_reg = 0x75090,
2784 .enable_mask = BIT(0),
2785 .hw.init = &(struct clk_init_data){
2786 .name = "gcc_ufs_card_phy_aux_clk",
2787 .parent_hws = (const struct clk_hw *[]){
2788 &gcc_ufs_card_phy_aux_clk_src.clkr.hw },
2789 .num_parents = 1,
2790 .flags = CLK_SET_RATE_PARENT,
2791 .ops = &clk_branch2_ops,
2792 },
2793 },
2794};
2795
2796static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
2797 .halt_reg = 0x75090,
2798 .halt_check = BRANCH_HALT,
2799 .hwcg_reg = 0x75090,
2800 .hwcg_bit = 1,
2801 .clkr = {
2802 .enable_reg = 0x75090,
2803 .enable_mask = BIT(1),
2804 .hw.init = &(struct clk_init_data){
2805 .name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
2806 .parent_hws = (const struct clk_hw *[]){
2807 &gcc_ufs_card_phy_aux_clk.clkr.hw },
2808 .num_parents = 1,
2809 .flags = CLK_SET_RATE_PARENT,
2810 .ops = &clk_branch_simple_ops,
2811 },
2812 },
2813};
2814
2815static struct clk_branch gcc_ufs_card_unipro_core_clk = {
2816 .halt_reg = 0x75058,
2817 .halt_check = BRANCH_HALT,
2818 .hwcg_reg = 0x75058,
2819 .hwcg_bit = 1,
2820 .clkr = {
2821 .enable_reg = 0x75058,
2822 .enable_mask = BIT(0),
2823 .hw.init = &(struct clk_init_data){
2824 .name = "gcc_ufs_card_unipro_core_clk",
2825 .parent_hws = (const struct clk_hw *[]){
2826 &gcc_ufs_card_unipro_core_clk_src.clkr.hw },
2827 .num_parents = 1,
2828 .flags = CLK_SET_RATE_PARENT,
2829 .ops = &clk_branch2_ops,
2830 },
2831 },
2832};
2833
2834static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
2835 .halt_reg = 0x75058,
2836 .halt_check = BRANCH_HALT,
2837 .hwcg_reg = 0x75058,
2838 .hwcg_bit = 1,
2839 .clkr = {
2840 .enable_reg = 0x75058,
2841 .enable_mask = BIT(1),
2842 .hw.init = &(struct clk_init_data){
2843 .name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
2844 .parent_hws = (const struct clk_hw *[]){
2845 &gcc_ufs_card_unipro_core_clk.clkr.hw },
2846 .num_parents = 1,
2847 .flags = CLK_SET_RATE_PARENT,
2848 .ops = &clk_branch_simple_ops,
2849 },
2850 },
2851};
2852
2853static struct clk_branch gcc_ufs_mem_clkref_clk = {
2854 .halt_reg = 0x8c000,
2855 .halt_check = BRANCH_HALT,
2856 .clkr = {
2857 .enable_reg = 0x8c000,
2858 .enable_mask = BIT(0),
2859 .hw.init = &(struct clk_init_data){
2860 .name = "gcc_ufs_mem_clkref_clk",
2861 .ops = &clk_branch2_ops,
2862 },
2863 },
2864};
2865
2866static struct clk_branch gcc_ufs_phy_ahb_clk = {
2867 .halt_reg = 0x77014,
2868 .halt_check = BRANCH_HALT,
2869 .hwcg_reg = 0x77014,
2870 .hwcg_bit = 1,
2871 .clkr = {
2872 .enable_reg = 0x77014,
2873 .enable_mask = BIT(0),
2874 .hw.init = &(struct clk_init_data){
2875 .name = "gcc_ufs_phy_ahb_clk",
2876 .ops = &clk_branch2_ops,
2877 },
2878 },
2879};
2880
2881static struct clk_branch gcc_ufs_phy_axi_clk = {
2882 .halt_reg = 0x77010,
2883 .halt_check = BRANCH_HALT,
2884 .hwcg_reg = 0x77010,
2885 .hwcg_bit = 1,
2886 .clkr = {
2887 .enable_reg = 0x77010,
2888 .enable_mask = BIT(0),
2889 .hw.init = &(struct clk_init_data){
2890 .name = "gcc_ufs_phy_axi_clk",
2891 .parent_hws = (const struct clk_hw *[]){
2892 &gcc_ufs_phy_axi_clk_src.clkr.hw },
2893 .num_parents = 1,
2894 .flags = CLK_SET_RATE_PARENT,
2895 .ops = &clk_branch2_ops,
2896 },
2897 },
2898};
2899
2900static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
2901 .halt_reg = 0x77010,
2902 .halt_check = BRANCH_HALT,
2903 .hwcg_reg = 0x77010,
2904 .hwcg_bit = 1,
2905 .clkr = {
2906 .enable_reg = 0x77010,
2907 .enable_mask = BIT(1),
2908 .hw.init = &(struct clk_init_data){
2909 .name = "gcc_ufs_phy_axi_hw_ctl_clk",
2910 .parent_hws = (const struct clk_hw *[]){
2911 &gcc_ufs_phy_axi_clk.clkr.hw },
2912 .num_parents = 1,
2913 .flags = CLK_SET_RATE_PARENT,
2914 .ops = &clk_branch_simple_ops,
2915 },
2916 },
2917};
2918
2919static struct clk_branch gcc_ufs_phy_ice_core_clk = {
2920 .halt_reg = 0x7705c,
2921 .halt_check = BRANCH_HALT,
2922 .hwcg_reg = 0x7705c,
2923 .hwcg_bit = 1,
2924 .clkr = {
2925 .enable_reg = 0x7705c,
2926 .enable_mask = BIT(0),
2927 .hw.init = &(struct clk_init_data){
2928 .name = "gcc_ufs_phy_ice_core_clk",
2929 .parent_hws = (const struct clk_hw *[]){
2930 &gcc_ufs_phy_ice_core_clk_src.clkr.hw },
2931 .num_parents = 1,
2932 .flags = CLK_SET_RATE_PARENT,
2933 .ops = &clk_branch2_ops,
2934 },
2935 },
2936};
2937
2938static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
2939 .halt_reg = 0x7705c,
2940 .halt_check = BRANCH_HALT,
2941 .hwcg_reg = 0x7705c,
2942 .hwcg_bit = 1,
2943 .clkr = {
2944 .enable_reg = 0x7705c,
2945 .enable_mask = BIT(1),
2946 .hw.init = &(struct clk_init_data){
2947 .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
2948 .parent_hws = (const struct clk_hw *[]){
2949 &gcc_ufs_phy_ice_core_clk.clkr.hw },
2950 .num_parents = 1,
2951 .flags = CLK_SET_RATE_PARENT,
2952 .ops = &clk_branch_simple_ops,
2953 },
2954 },
2955};
2956
2957static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
2958 .halt_reg = 0x77090,
2959 .halt_check = BRANCH_HALT,
2960 .hwcg_reg = 0x77090,
2961 .hwcg_bit = 1,
2962 .clkr = {
2963 .enable_reg = 0x77090,
2964 .enable_mask = BIT(0),
2965 .hw.init = &(struct clk_init_data){
2966 .name = "gcc_ufs_phy_phy_aux_clk",
2967 .parent_hws = (const struct clk_hw *[]){
2968 &gcc_ufs_phy_phy_aux_clk_src.clkr.hw },
2969 .num_parents = 1,
2970 .flags = CLK_SET_RATE_PARENT,
2971 .ops = &clk_branch2_ops,
2972 },
2973 },
2974};
2975
2976static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
2977 .halt_reg = 0x77090,
2978 .halt_check = BRANCH_HALT,
2979 .hwcg_reg = 0x77090,
2980 .hwcg_bit = 1,
2981 .clkr = {
2982 .enable_reg = 0x77090,
2983 .enable_mask = BIT(1),
2984 .hw.init = &(struct clk_init_data){
2985 .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
2986 .parent_hws = (const struct clk_hw *[]){
2987 &gcc_ufs_phy_phy_aux_clk.clkr.hw },
2988 .num_parents = 1,
2989 .flags = CLK_SET_RATE_PARENT,
2990 .ops = &clk_branch_simple_ops,
2991 },
2992 },
2993};
2994
2995static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
2996 .halt_reg = 0x77058,
2997 .halt_check = BRANCH_HALT,
2998 .hwcg_reg = 0x77058,
2999 .hwcg_bit = 1,
3000 .clkr = {
3001 .enable_reg = 0x77058,
3002 .enable_mask = BIT(0),
3003 .hw.init = &(struct clk_init_data){
3004 .name = "gcc_ufs_phy_unipro_core_clk",
3005 .parent_hws = (const struct clk_hw *[]){
3006 &gcc_ufs_phy_unipro_core_clk_src.clkr.hw },
3007 .num_parents = 1,
3008 .flags = CLK_SET_RATE_PARENT,
3009 .ops = &clk_branch2_ops,
3010 },
3011 },
3012};
3013
3014static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
3015 .halt_reg = 0x77058,
3016 .halt_check = BRANCH_HALT,
3017 .hwcg_reg = 0x77058,
3018 .hwcg_bit = 1,
3019 .clkr = {
3020 .enable_reg = 0x77058,
3021 .enable_mask = BIT(1),
3022 .hw.init = &(struct clk_init_data){
3023 .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
3024 .parent_hws = (const struct clk_hw *[]){
3025 &gcc_ufs_phy_unipro_core_clk.clkr.hw },
3026 .num_parents = 1,
3027 .flags = CLK_SET_RATE_PARENT,
3028 .ops = &clk_branch_simple_ops,
3029 },
3030 },
3031};
3032
3033static struct clk_branch gcc_usb30_prim_master_clk = {
3034 .halt_reg = 0xf010,
3035 .halt_check = BRANCH_HALT,
3036 .clkr = {
3037 .enable_reg = 0xf010,
3038 .enable_mask = BIT(0),
3039 .hw.init = &(struct clk_init_data){
3040 .name = "gcc_usb30_prim_master_clk",
3041 .parent_hws = (const struct clk_hw *[]){
3042 &gcc_usb30_prim_master_clk_src.clkr.hw },
3043 .num_parents = 1,
3044 .flags = CLK_SET_RATE_PARENT,
3045 .ops = &clk_branch2_ops,
3046 },
3047 },
3048};
3049
3050static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
3051 .halt_reg = 0xf018,
3052 .halt_check = BRANCH_HALT,
3053 .clkr = {
3054 .enable_reg = 0xf018,
3055 .enable_mask = BIT(0),
3056 .hw.init = &(struct clk_init_data){
3057 .name = "gcc_usb30_prim_mock_utmi_clk",
3058 .parent_hws = (const struct clk_hw *[]){
3059 &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw },
3060 .num_parents = 1,
3061 .flags = CLK_SET_RATE_PARENT,
3062 .ops = &clk_branch2_ops,
3063 },
3064 },
3065};
3066
3067static struct clk_branch gcc_usb30_prim_sleep_clk = {
3068 .halt_reg = 0xf014,
3069 .halt_check = BRANCH_HALT,
3070 .clkr = {
3071 .enable_reg = 0xf014,
3072 .enable_mask = BIT(0),
3073 .hw.init = &(struct clk_init_data){
3074 .name = "gcc_usb30_prim_sleep_clk",
3075 .ops = &clk_branch2_ops,
3076 },
3077 },
3078};
3079
3080static struct clk_branch gcc_usb30_sec_master_clk = {
3081 .halt_reg = 0x10010,
3082 .halt_check = BRANCH_HALT,
3083 .clkr = {
3084 .enable_reg = 0x10010,
3085 .enable_mask = BIT(0),
3086 .hw.init = &(struct clk_init_data){
3087 .name = "gcc_usb30_sec_master_clk",
3088 .parent_hws = (const struct clk_hw *[]){
3089 &gcc_usb30_sec_master_clk_src.clkr.hw },
3090 .num_parents = 1,
3091 .flags = CLK_SET_RATE_PARENT,
3092 .ops = &clk_branch2_ops,
3093 },
3094 },
3095};
3096
3097static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
3098 .halt_reg = 0x10018,
3099 .halt_check = BRANCH_HALT,
3100 .clkr = {
3101 .enable_reg = 0x10018,
3102 .enable_mask = BIT(0),
3103 .hw.init = &(struct clk_init_data){
3104 .name = "gcc_usb30_sec_mock_utmi_clk",
3105 .parent_hws = (const struct clk_hw *[]){
3106 &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw },
3107 .num_parents = 1,
3108 .flags = CLK_SET_RATE_PARENT,
3109 .ops = &clk_branch2_ops,
3110 },
3111 },
3112};
3113
3114static struct clk_branch gcc_usb30_sec_sleep_clk = {
3115 .halt_reg = 0x10014,
3116 .halt_check = BRANCH_HALT,
3117 .clkr = {
3118 .enable_reg = 0x10014,
3119 .enable_mask = BIT(0),
3120 .hw.init = &(struct clk_init_data){
3121 .name = "gcc_usb30_sec_sleep_clk",
3122 .ops = &clk_branch2_ops,
3123 },
3124 },
3125};
3126
3127static struct clk_branch gcc_usb3_prim_clkref_clk = {
3128 .halt_reg = 0x8c008,
3129 .halt_check = BRANCH_HALT,
3130 .clkr = {
3131 .enable_reg = 0x8c008,
3132 .enable_mask = BIT(0),
3133 .hw.init = &(struct clk_init_data){
3134 .name = "gcc_usb3_prim_clkref_clk",
3135 .ops = &clk_branch2_ops,
3136 },
3137 },
3138};
3139
3140static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
3141 .halt_reg = 0xf050,
3142 .halt_check = BRANCH_HALT,
3143 .clkr = {
3144 .enable_reg = 0xf050,
3145 .enable_mask = BIT(0),
3146 .hw.init = &(struct clk_init_data){
3147 .name = "gcc_usb3_prim_phy_aux_clk",
3148 .parent_hws = (const struct clk_hw *[]){
3149 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
3150 .num_parents = 1,
3151 .flags = CLK_SET_RATE_PARENT,
3152 .ops = &clk_branch2_ops,
3153 },
3154 },
3155};
3156
3157static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
3158 .halt_reg = 0xf054,
3159 .halt_check = BRANCH_HALT,
3160 .clkr = {
3161 .enable_reg = 0xf054,
3162 .enable_mask = BIT(0),
3163 .hw.init = &(struct clk_init_data){
3164 .name = "gcc_usb3_prim_phy_com_aux_clk",
3165 .parent_hws = (const struct clk_hw *[]){
3166 &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
3167 .num_parents = 1,
3168 .flags = CLK_SET_RATE_PARENT,
3169 .ops = &clk_branch2_ops,
3170 },
3171 },
3172};
3173
3174static struct clk_branch gcc_usb3_sec_clkref_clk = {
3175 .halt_reg = 0x8c028,
3176 .halt_check = BRANCH_HALT,
3177 .clkr = {
3178 .enable_reg = 0x8c028,
3179 .enable_mask = BIT(0),
3180 .hw.init = &(struct clk_init_data){
3181 .name = "gcc_usb3_sec_clkref_clk",
3182 .ops = &clk_branch2_ops,
3183 },
3184 },
3185};
3186
3187static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
3188 .halt_reg = 0x10050,
3189 .halt_check = BRANCH_HALT,
3190 .clkr = {
3191 .enable_reg = 0x10050,
3192 .enable_mask = BIT(0),
3193 .hw.init = &(struct clk_init_data){
3194 .name = "gcc_usb3_sec_phy_aux_clk",
3195 .parent_hws = (const struct clk_hw *[]){
3196 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
3197 .num_parents = 1,
3198 .flags = CLK_SET_RATE_PARENT,
3199 .ops = &clk_branch2_ops,
3200 },
3201 },
3202};
3203
3204static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
3205 .halt_reg = 0x10054,
3206 .halt_check = BRANCH_HALT,
3207 .clkr = {
3208 .enable_reg = 0x10054,
3209 .enable_mask = BIT(0),
3210 .hw.init = &(struct clk_init_data){
3211 .name = "gcc_usb3_sec_phy_com_aux_clk",
3212 .parent_hws = (const struct clk_hw *[]){
3213 &gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
3214 .num_parents = 1,
3215 .flags = CLK_SET_RATE_PARENT,
3216 .ops = &clk_branch2_ops,
3217 },
3218 },
3219};
3220
3221/*
3222 * Clock ON depends on external parent 'config noc', so cant poll
3223 * delay and also mark as crtitical for video boot
3224 */
3225static struct clk_branch gcc_video_ahb_clk = {
3226 .halt_reg = 0xb004,
3227 .halt_check = BRANCH_HALT_DELAY,
3228 .hwcg_reg = 0xb004,
3229 .hwcg_bit = 1,
3230 .clkr = {
3231 .enable_reg = 0xb004,
3232 .enable_mask = BIT(0),
3233 .hw.init = &(struct clk_init_data){
3234 .name = "gcc_video_ahb_clk",
3235 .flags = CLK_IS_CRITICAL,
3236 .ops = &clk_branch2_ops,
3237 },
3238 },
3239};
3240
3241static struct clk_branch gcc_video_axi0_clk = {
3242 .halt_reg = 0xb024,
3243 .halt_check = BRANCH_HALT,
3244 .clkr = {
3245 .enable_reg = 0xb024,
3246 .enable_mask = BIT(0),
3247 .hw.init = &(struct clk_init_data){
3248 .name = "gcc_video_axi0_clk",
3249 .ops = &clk_branch2_ops,
3250 },
3251 },
3252};
3253
3254static struct clk_branch gcc_video_axi1_clk = {
3255 .halt_reg = 0xb028,
3256 .halt_check = BRANCH_HALT,
3257 .clkr = {
3258 .enable_reg = 0xb028,
3259 .enable_mask = BIT(0),
3260 .hw.init = &(struct clk_init_data){
3261 .name = "gcc_video_axi1_clk",
3262 .ops = &clk_branch2_ops,
3263 },
3264 },
3265};
3266
3267static struct clk_branch gcc_video_axic_clk = {
3268 .halt_reg = 0xb02c,
3269 .halt_check = BRANCH_HALT,
3270 .clkr = {
3271 .enable_reg = 0xb02c,
3272 .enable_mask = BIT(0),
3273 .hw.init = &(struct clk_init_data){
3274 .name = "gcc_video_axic_clk",
3275 .ops = &clk_branch2_ops,
3276 },
3277 },
3278};
3279
3280/* XO critical input to video, so no need to poll */
3281static struct clk_branch gcc_video_xo_clk = {
3282 .halt_reg = 0xb040,
3283 .halt_check = BRANCH_HALT_DELAY,
3284 .clkr = {
3285 .enable_reg = 0xb040,
3286 .enable_mask = BIT(0),
3287 .hw.init = &(struct clk_init_data){
3288 .name = "gcc_video_xo_clk",
3289 .flags = CLK_IS_CRITICAL,
3290 .ops = &clk_branch2_ops,
3291 },
3292 },
3293};
3294
3295static struct clk_regmap *gcc_sm8150_clocks[] = {
3296 [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
3297 [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
3298 [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] =
3299 &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
3300 [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
3301 [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] =
3302 &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
3303 [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
3304 [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
3305 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
3306 [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
3307 [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
3308 [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
3309 [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
3310 [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
3311 [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
3312 [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
3313 [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
3314 [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
3315 [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
3316 [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
3317 [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
3318 [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
3319 [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
3320 [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
3321 [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
3322 [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr,
3323 [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr,
3324 [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,
3325 [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr,
3326 [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr,
3327 [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr,
3328 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
3329 [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
3330 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
3331 [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
3332 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
3333 [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
3334 [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
3335 [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
3336 [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
3337 [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
3338 [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,
3339 [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
3340 [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
3341 [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr,
3342 [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
3343 [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
3344 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
3345 [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
3346 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
3347 [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
3348 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
3349 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
3350 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
3351 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
3352 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
3353 [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
3354 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
3355 [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
3356 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
3357 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
3358 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
3359 [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
3360 [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
3361 [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
3362 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
3363 [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
3364 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
3365 [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
3366 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3367 [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
3368 [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
3369 [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
3370 [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
3371 [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
3372 [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
3373 [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
3374 [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
3375 [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
3376 [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
3377 [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
3378 [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
3379 [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
3380 [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
3381 [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
3382 [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
3383 [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
3384 [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
3385 [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
3386 [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
3387 [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
3388 [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
3389 [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
3390 [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
3391 [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
3392 [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
3393 [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
3394 [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
3395 [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
3396 [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
3397 [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
3398 [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
3399 [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
3400 [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
3401 [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
3402 [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
3403 [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
3404 [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
3405 [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
3406 [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
3407 [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
3408 [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
3409 [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
3410 [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
3411 [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
3412 [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
3413 [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
3414 [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
3415 [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
3416 [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
3417 [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
3418 [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
3419 [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
3420 [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
3421 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3422 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3423 [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
3424 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
3425 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
3426 [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
3427 [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
3428 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
3429 [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
3430 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
3431 [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
3432 [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
3433 [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
3434 [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
3435 [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
3436 [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
3437 [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
3438 [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
3439 [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] =
3440 &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
3441 [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
3442 [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
3443 [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] =
3444 &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
3445 [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
3446 [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
3447 &gcc_ufs_card_unipro_core_clk_src.clkr,
3448 [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] =
3449 &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
3450 [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
3451 [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
3452 [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
3453 [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
3454 [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
3455 [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
3456 [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
3457 [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] =
3458 &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
3459 [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
3460 [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
3461 [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
3462 [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
3463 [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
3464 &gcc_ufs_phy_unipro_core_clk_src.clkr,
3465 [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =
3466 &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
3467 [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
3468 [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
3469 [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
3470 [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
3471 &gcc_usb30_prim_mock_utmi_clk_src.clkr,
3472 [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
3473 [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
3474 [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
3475 [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
3476 [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
3477 &gcc_usb30_sec_mock_utmi_clk_src.clkr,
3478 [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
3479 [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
3480 [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
3481 [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
3482 [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
3483 [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
3484 [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
3485 [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
3486 [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
3487 [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
3488 [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
3489 [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
3490 [GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr,
3491 [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
3492 [GPLL0] = &gpll0.clkr,
3493 [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
3494 [GPLL7] = &gpll7.clkr,
3495 [GPLL9] = &gpll9.clkr,
3496};
3497
3498static const struct qcom_reset_map gcc_sm8150_resets[] = {
3499 [GCC_EMAC_BCR] = { 0x6000 },
3500 [GCC_GPU_BCR] = { 0x71000 },
3501 [GCC_MMSS_BCR] = { 0xb000 },
3502 [GCC_NPU_BCR] = { 0x4d000 },
3503 [GCC_PCIE_0_BCR] = { 0x6b000 },
3504 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
3505 [GCC_PCIE_1_BCR] = { 0x8d000 },
3506 [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
3507 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
3508 [GCC_PDM_BCR] = { 0x33000 },
3509 [GCC_PRNG_BCR] = { 0x34000 },
3510 [GCC_QSPI_BCR] = { 0x24008 },
3511 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
3512 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
3513 [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
3514 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
3515 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
3516 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
3517 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
3518 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
3519 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
3520 [GCC_SDCC2_BCR] = { 0x14000 },
3521 [GCC_SDCC4_BCR] = { 0x16000 },
3522 [GCC_TSIF_BCR] = { 0x36000 },
3523 [GCC_UFS_CARD_BCR] = { 0x75000 },
3524 [GCC_UFS_PHY_BCR] = { 0x77000 },
3525 [GCC_USB30_PRIM_BCR] = { 0xf000 },
3526 [GCC_USB30_SEC_BCR] = { 0x10000 },
3527 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
3528};
3529
3530static const struct regmap_config gcc_sm8150_regmap_config = {
3531 .reg_bits = 32,
3532 .reg_stride = 4,
3533 .val_bits = 32,
3534 .max_register = 0x9c040,
3535 .fast_io = true,
3536};
3537
3538static const struct qcom_cc_desc gcc_sm8150_desc = {
3539 .config = &gcc_sm8150_regmap_config,
3540 .clks = gcc_sm8150_clocks,
3541 .num_clks = ARRAY_SIZE(gcc_sm8150_clocks),
3542 .resets = gcc_sm8150_resets,
3543 .num_resets = ARRAY_SIZE(gcc_sm8150_resets),
3544};
3545
3546static const struct of_device_id gcc_sm8150_match_table[] = {
3547 { .compatible = "qcom,gcc-sm8150" },
3548 { }
3549};
3550MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table);
3551
3552static int gcc_sm8150_probe(struct platform_device *pdev)
3553{
3554 struct regmap *regmap;
3555
3556 regmap = qcom_cc_map(pdev, &gcc_sm8150_desc);
3557 if (IS_ERR(regmap))
3558 return PTR_ERR(regmap);
3559
3560 /* Disable the GPLL0 active input to NPU and GPU via MISC registers */
3561 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
3562 regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
3563
3564 return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap);
3565}
3566
3567static struct platform_driver gcc_sm8150_driver = {
3568 .probe = gcc_sm8150_probe,
3569 .driver = {
3570 .name = "gcc-sm8150",
3571 .of_match_table = gcc_sm8150_match_table,
3572 },
3573};
3574
3575static int __init gcc_sm8150_init(void)
3576{
3577 return platform_driver_register(&gcc_sm8150_driver);
3578}
3579subsys_initcall(gcc_sm8150_init);
3580
3581static void __exit gcc_sm8150_exit(void)
3582{
3583 platform_driver_unregister(&gcc_sm8150_driver);
3584}
3585module_exit(gcc_sm8150_exit);
3586
3587MODULE_DESCRIPTION("QTI GCC SM8150 Driver");
3588MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/qcom/lpasscc-sdm845.c b/drivers/clk/qcom/lpasscc-sdm845.c
index e246b99dfbc6..56d3e9928892 100644
--- a/drivers/clk/qcom/lpasscc-sdm845.c
+++ b/drivers/clk/qcom/lpasscc-sdm845.c
@@ -112,25 +112,6 @@ static const struct qcom_cc_desc lpass_qdsp6ss_sdm845_desc = {
112 .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sdm845_clocks), 112 .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sdm845_clocks),
113}; 113};
114 114
115static int lpass_clocks_sdm845_probe(struct platform_device *pdev, int index,
116 const struct qcom_cc_desc *desc)
117{
118 struct regmap *regmap;
119 struct resource *res;
120 void __iomem *base;
121
122 res = platform_get_resource(pdev, IORESOURCE_MEM, index);
123 base = devm_ioremap_resource(&pdev->dev, res);
124 if (IS_ERR(base))
125 return PTR_ERR(base);
126
127 regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config);
128 if (IS_ERR(regmap))
129 return PTR_ERR(regmap);
130
131 return qcom_cc_really_probe(pdev, desc, regmap);
132}
133
134static int lpass_cc_sdm845_probe(struct platform_device *pdev) 115static int lpass_cc_sdm845_probe(struct platform_device *pdev)
135{ 116{
136 const struct qcom_cc_desc *desc; 117 const struct qcom_cc_desc *desc;
@@ -139,14 +120,14 @@ static int lpass_cc_sdm845_probe(struct platform_device *pdev)
139 lpass_regmap_config.name = "cc"; 120 lpass_regmap_config.name = "cc";
140 desc = &lpass_cc_sdm845_desc; 121 desc = &lpass_cc_sdm845_desc;
141 122
142 ret = lpass_clocks_sdm845_probe(pdev, 0, desc); 123 ret = qcom_cc_probe_by_index(pdev, 0, desc);
143 if (ret) 124 if (ret)
144 return ret; 125 return ret;
145 126
146 lpass_regmap_config.name = "qdsp6ss"; 127 lpass_regmap_config.name = "qdsp6ss";
147 desc = &lpass_qdsp6ss_sdm845_desc; 128 desc = &lpass_qdsp6ss_sdm845_desc;
148 129
149 return lpass_clocks_sdm845_probe(pdev, 1, desc); 130 return qcom_cc_probe_by_index(pdev, 1, desc);
150} 131}
151 132
152static const struct of_device_id lpass_cc_sdm845_match_table[] = { 133static const struct of_device_id lpass_cc_sdm845_match_table[] = {
diff --git a/drivers/clk/qcom/turingcc-qcs404.c b/drivers/clk/qcom/turingcc-qcs404.c
index aa859e6ec9bd..4cfbbf5bf4d9 100644
--- a/drivers/clk/qcom/turingcc-qcs404.c
+++ b/drivers/clk/qcom/turingcc-qcs404.c
@@ -96,7 +96,7 @@ static const struct regmap_config turingcc_regmap_config = {
96 .reg_bits = 32, 96 .reg_bits = 32,
97 .reg_stride = 4, 97 .reg_stride = 4,
98 .val_bits = 32, 98 .val_bits = 32,
99 .max_register = 0x30000, 99 .max_register = 0x23004,
100 .fast_io = true, 100 .fast_io = true,
101}; 101};
102 102
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index d18e49b4976f..4413b6e04a8e 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -326,6 +326,7 @@ static void __init st_of_flexgen_setup(struct device_node *np)
326 return; 326 return;
327 327
328 reg = of_iomap(pnode, 0); 328 reg = of_iomap(pnode, 0);
329 of_node_put(pnode);
329 if (!reg) 330 if (!reg)
330 return; 331 return;
331 332
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index ca1ccdb8a3b1..a156bd0c6af7 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -67,7 +67,6 @@ struct clkgen_quadfs_data {
67}; 67};
68 68
69static const struct clk_ops st_quadfs_pll_c32_ops; 69static const struct clk_ops st_quadfs_pll_c32_ops;
70static const struct clk_ops st_quadfs_fs660c32_ops;
71 70
72static int clk_fs660c32_dig_get_params(unsigned long input, 71static int clk_fs660c32_dig_get_params(unsigned long input,
73 unsigned long output, struct stm_fs *fs); 72 unsigned long output, struct stm_fs *fs);
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index d8a688bd45ec..c3952f2c42ba 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -61,19 +61,6 @@ static const struct clk_ops stm_pll3200c32_ops;
61static const struct clk_ops stm_pll3200c32_a9_ops; 61static const struct clk_ops stm_pll3200c32_a9_ops;
62static const struct clk_ops stm_pll4600c28_ops; 62static const struct clk_ops stm_pll4600c28_ops;
63 63
64static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
65 /* 407 A0 */
66 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
67 .pdn_ctrl = CLKGEN_FIELD(0x2a0, 0x1, 8),
68 .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
69 .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
70 .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
71 .num_odfs = 1,
72 .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
73 .odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
74 .ops = &stm_pll3200c32_ops,
75};
76
77static const struct clkgen_pll_data st_pll3200c32_cx_0 = { 64static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
78 /* 407 C0 PLL0 */ 65 /* 407 C0 PLL0 */
79 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8), 66 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
diff --git a/drivers/clk/ti/clk-814x.c b/drivers/clk/ti/clk-814x.c
index e8cee6f3b4a0..087cfa75ac24 100644
--- a/drivers/clk/ti/clk-814x.c
+++ b/drivers/clk/ti/clk-814x.c
@@ -66,6 +66,7 @@ static int __init dm814x_adpll_early_init(void)
66 } 66 }
67 67
68 of_platform_populate(np, NULL, NULL, NULL); 68 of_platform_populate(np, NULL, NULL, NULL);
69 of_node_put(np);
69 70
70 return 0; 71 return 0;
71} 72}
diff --git a/drivers/clk/versatile/clk-versatile.c b/drivers/clk/versatile/clk-versatile.c
index 90bb0b041b7a..fd54d5c0251c 100644
--- a/drivers/clk/versatile/clk-versatile.c
+++ b/drivers/clk/versatile/clk-versatile.c
@@ -70,6 +70,7 @@ static void __init cm_osc_setup(struct device_node *np,
70 return; 70 return;
71 } 71 }
72 cm_base = of_iomap(parent, 0); 72 cm_base = of_iomap(parent, 0);
73 of_node_put(parent);
73 if (!cm_base) { 74 if (!cm_base) {
74 pr_err("could not remap core module base\n"); 75 pr_err("could not remap core module base\n");
75 return; 76 return;
diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
new file mode 100644
index 000000000000..38074a5f7296
--- /dev/null
+++ b/include/dt-bindings/clock/ast2600-clock.h
@@ -0,0 +1,113 @@
1/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */
2#ifndef DT_BINDINGS_AST2600_CLOCK_H
3#define DT_BINDINGS_AST2600_CLOCK_H
4
5#define ASPEED_CLK_GATE_ECLK 0
6#define ASPEED_CLK_GATE_GCLK 1
7
8#define ASPEED_CLK_GATE_MCLK 2
9
10#define ASPEED_CLK_GATE_VCLK 3
11#define ASPEED_CLK_GATE_BCLK 4
12#define ASPEED_CLK_GATE_DCLK 5
13
14#define ASPEED_CLK_GATE_LCLK 6
15#define ASPEED_CLK_GATE_LHCCLK 7
16
17#define ASPEED_CLK_GATE_D1CLK 8
18#define ASPEED_CLK_GATE_YCLK 9
19
20#define ASPEED_CLK_GATE_REF0CLK 10
21#define ASPEED_CLK_GATE_REF1CLK 11
22
23#define ASPEED_CLK_GATE_ESPICLK 12
24
25#define ASPEED_CLK_GATE_USBUHCICLK 13
26#define ASPEED_CLK_GATE_USBPORT1CLK 14
27#define ASPEED_CLK_GATE_USBPORT2CLK 15
28
29#define ASPEED_CLK_GATE_RSACLK 16
30#define ASPEED_CLK_GATE_RVASCLK 17
31
32#define ASPEED_CLK_GATE_MAC1CLK 18
33#define ASPEED_CLK_GATE_MAC2CLK 19
34#define ASPEED_CLK_GATE_MAC3CLK 20
35#define ASPEED_CLK_GATE_MAC4CLK 21
36
37#define ASPEED_CLK_GATE_UART1CLK 22
38#define ASPEED_CLK_GATE_UART2CLK 23
39#define ASPEED_CLK_GATE_UART3CLK 24
40#define ASPEED_CLK_GATE_UART4CLK 25
41#define ASPEED_CLK_GATE_UART5CLK 26
42#define ASPEED_CLK_GATE_UART6CLK 27
43#define ASPEED_CLK_GATE_UART7CLK 28
44#define ASPEED_CLK_GATE_UART8CLK 29
45#define ASPEED_CLK_GATE_UART9CLK 30
46#define ASPEED_CLK_GATE_UART10CLK 31
47#define ASPEED_CLK_GATE_UART11CLK 32
48#define ASPEED_CLK_GATE_UART12CLK 33
49#define ASPEED_CLK_GATE_UART13CLK 34
50
51#define ASPEED_CLK_GATE_SDCLK 35
52#define ASPEED_CLK_GATE_EMMCCLK 36
53
54#define ASPEED_CLK_GATE_I3C0CLK 37
55#define ASPEED_CLK_GATE_I3C1CLK 38
56#define ASPEED_CLK_GATE_I3C2CLK 39
57#define ASPEED_CLK_GATE_I3C3CLK 40
58#define ASPEED_CLK_GATE_I3C4CLK 41
59#define ASPEED_CLK_GATE_I3C5CLK 42
60#define ASPEED_CLK_GATE_I3C6CLK 43
61#define ASPEED_CLK_GATE_I3C7CLK 44
62
63#define ASPEED_CLK_GATE_FSICLK 45
64
65#define ASPEED_CLK_HPLL 46
66#define ASPEED_CLK_MPLL 47
67#define ASPEED_CLK_DPLL 48
68#define ASPEED_CLK_EPLL 49
69#define ASPEED_CLK_APLL 50
70#define ASPEED_CLK_AHB 51
71#define ASPEED_CLK_APB1 52
72#define ASPEED_CLK_APB2 53
73#define ASPEED_CLK_BCLK 54
74#define ASPEED_CLK_D1CLK 55
75#define ASPEED_CLK_VCLK 56
76#define ASPEED_CLK_LHCLK 57
77#define ASPEED_CLK_UART 58
78#define ASPEED_CLK_UARTX 59
79#define ASPEED_CLK_SDIO 60
80#define ASPEED_CLK_EMMC 61
81#define ASPEED_CLK_ECLK 62
82#define ASPEED_CLK_ECLK_MUX 63
83#define ASPEED_CLK_MAC12 64
84#define ASPEED_CLK_MAC34 65
85#define ASPEED_CLK_USBPHY_40M 66
86
87/* Only list resets here that are not part of a gate */
88#define ASPEED_RESET_ADC 55
89#define ASPEED_RESET_JTAG_MASTER2 54
90#define ASPEED_RESET_I3C_DMA 39
91#define ASPEED_RESET_PWM 37
92#define ASPEED_RESET_PECI 36
93#define ASPEED_RESET_MII 35
94#define ASPEED_RESET_I2C 34
95#define ASPEED_RESET_H2X 31
96#define ASPEED_RESET_GP_MCU 30
97#define ASPEED_RESET_DP_MCU 29
98#define ASPEED_RESET_DP 28
99#define ASPEED_RESET_RC_XDMA 27
100#define ASPEED_RESET_GRAPHICS 26
101#define ASPEED_RESET_DEV_XDMA 25
102#define ASPEED_RESET_DEV_MCTP 24
103#define ASPEED_RESET_RC_MCTP 23
104#define ASPEED_RESET_JTAG_MASTER 22
105#define ASPEED_RESET_PCIE_DEV_O 21
106#define ASPEED_RESET_PCIE_DEV_OEN 20
107#define ASPEED_RESET_PCIE_RC_O 19
108#define ASPEED_RESET_PCIE_RC_OEN 18
109#define ASPEED_RESET_PCI_DP 5
110#define ASPEED_RESET_AHB 1
111#define ASPEED_RESET_SDRAM 0
112
113#endif
diff --git a/include/dt-bindings/clock/mt6779-clk.h b/include/dt-bindings/clock/mt6779-clk.h
new file mode 100644
index 000000000000..b083139afbd2
--- /dev/null
+++ b/include/dt-bindings/clock/mt6779-clk.h
@@ -0,0 +1,436 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Wendell Lin <wendell.lin@mediatek.com>
5 */
6
7#ifndef _DT_BINDINGS_CLK_MT6779_H
8#define _DT_BINDINGS_CLK_MT6779_H
9
10/* TOPCKGEN */
11#define CLK_TOP_AXI 1
12#define CLK_TOP_MM 2
13#define CLK_TOP_CAM 3
14#define CLK_TOP_MFG 4
15#define CLK_TOP_CAMTG 5
16#define CLK_TOP_UART 6
17#define CLK_TOP_SPI 7
18#define CLK_TOP_MSDC50_0_HCLK 8
19#define CLK_TOP_MSDC50_0 9
20#define CLK_TOP_MSDC30_1 10
21#define CLK_TOP_MSDC30_2 11
22#define CLK_TOP_AUD 12
23#define CLK_TOP_AUD_INTBUS 13
24#define CLK_TOP_FPWRAP_ULPOSC 14
25#define CLK_TOP_SCP 15
26#define CLK_TOP_ATB 16
27#define CLK_TOP_SSPM 17
28#define CLK_TOP_DPI0 18
29#define CLK_TOP_SCAM 19
30#define CLK_TOP_AUD_1 20
31#define CLK_TOP_AUD_2 21
32#define CLK_TOP_DISP_PWM 22
33#define CLK_TOP_SSUSB_TOP_XHCI 23
34#define CLK_TOP_USB_TOP 24
35#define CLK_TOP_SPM 25
36#define CLK_TOP_I2C 26
37#define CLK_TOP_F52M_MFG 27
38#define CLK_TOP_SENINF 28
39#define CLK_TOP_DXCC 29
40#define CLK_TOP_CAMTG2 30
41#define CLK_TOP_AUD_ENG1 31
42#define CLK_TOP_AUD_ENG2 32
43#define CLK_TOP_FAES_UFSFDE 33
44#define CLK_TOP_FUFS 34
45#define CLK_TOP_IMG 35
46#define CLK_TOP_DSP 36
47#define CLK_TOP_DSP1 37
48#define CLK_TOP_DSP2 38
49#define CLK_TOP_IPU_IF 39
50#define CLK_TOP_CAMTG3 40
51#define CLK_TOP_CAMTG4 41
52#define CLK_TOP_PMICSPI 42
53#define CLK_TOP_MAINPLL_CK 43
54#define CLK_TOP_MAINPLL_D2 44
55#define CLK_TOP_MAINPLL_D3 45
56#define CLK_TOP_MAINPLL_D5 46
57#define CLK_TOP_MAINPLL_D7 47
58#define CLK_TOP_MAINPLL_D2_D2 48
59#define CLK_TOP_MAINPLL_D2_D4 49
60#define CLK_TOP_MAINPLL_D2_D8 50
61#define CLK_TOP_MAINPLL_D2_D16 51
62#define CLK_TOP_MAINPLL_D3_D2 52
63#define CLK_TOP_MAINPLL_D3_D4 53
64#define CLK_TOP_MAINPLL_D3_D8 54
65#define CLK_TOP_MAINPLL_D5_D2 55
66#define CLK_TOP_MAINPLL_D5_D4 56
67#define CLK_TOP_MAINPLL_D7_D2 57
68#define CLK_TOP_MAINPLL_D7_D4 58
69#define CLK_TOP_UNIVPLL_CK 59
70#define CLK_TOP_UNIVPLL_D2 60
71#define CLK_TOP_UNIVPLL_D3 61
72#define CLK_TOP_UNIVPLL_D5 62
73#define CLK_TOP_UNIVPLL_D7 63
74#define CLK_TOP_UNIVPLL_D2_D2 64
75#define CLK_TOP_UNIVPLL_D2_D4 65
76#define CLK_TOP_UNIVPLL_D2_D8 66
77#define CLK_TOP_UNIVPLL_D3_D2 67
78#define CLK_TOP_UNIVPLL_D3_D4 68
79#define CLK_TOP_UNIVPLL_D3_D8 69
80#define CLK_TOP_UNIVPLL_D5_D2 70
81#define CLK_TOP_UNIVPLL_D5_D4 71
82#define CLK_TOP_UNIVPLL_D5_D8 72
83#define CLK_TOP_APLL1_CK 73
84#define CLK_TOP_APLL1_D2 74
85#define CLK_TOP_APLL1_D4 75
86#define CLK_TOP_APLL1_D8 76
87#define CLK_TOP_APLL2_CK 77
88#define CLK_TOP_APLL2_D2 78
89#define CLK_TOP_APLL2_D4 79
90#define CLK_TOP_APLL2_D8 80
91#define CLK_TOP_TVDPLL_CK 81
92#define CLK_TOP_TVDPLL_D2 82
93#define CLK_TOP_TVDPLL_D4 83
94#define CLK_TOP_TVDPLL_D8 84
95#define CLK_TOP_TVDPLL_D16 85
96#define CLK_TOP_MSDCPLL_CK 86
97#define CLK_TOP_MSDCPLL_D2 87
98#define CLK_TOP_MSDCPLL_D4 88
99#define CLK_TOP_MSDCPLL_D8 89
100#define CLK_TOP_MSDCPLL_D16 90
101#define CLK_TOP_AD_OSC_CK 91
102#define CLK_TOP_OSC_D2 92
103#define CLK_TOP_OSC_D4 93
104#define CLK_TOP_OSC_D8 94
105#define CLK_TOP_OSC_D16 95
106#define CLK_TOP_F26M_CK_D2 96
107#define CLK_TOP_MFGPLL_CK 97
108#define CLK_TOP_UNIVP_192M_CK 98
109#define CLK_TOP_UNIVP_192M_D2 99
110#define CLK_TOP_UNIVP_192M_D4 100
111#define CLK_TOP_UNIVP_192M_D8 101
112#define CLK_TOP_UNIVP_192M_D16 102
113#define CLK_TOP_UNIVP_192M_D32 103
114#define CLK_TOP_MMPLL_CK 104
115#define CLK_TOP_MMPLL_D4 105
116#define CLK_TOP_MMPLL_D4_D2 106
117#define CLK_TOP_MMPLL_D4_D4 107
118#define CLK_TOP_MMPLL_D5 108
119#define CLK_TOP_MMPLL_D5_D2 109
120#define CLK_TOP_MMPLL_D5_D4 110
121#define CLK_TOP_MMPLL_D6 111
122#define CLK_TOP_MMPLL_D7 112
123#define CLK_TOP_CLK26M 113
124#define CLK_TOP_CLK13M 114
125#define CLK_TOP_ADSP 115
126#define CLK_TOP_DPMAIF 116
127#define CLK_TOP_VENC 117
128#define CLK_TOP_VDEC 118
129#define CLK_TOP_CAMTM 119
130#define CLK_TOP_PWM 120
131#define CLK_TOP_ADSPPLL_CK 121
132#define CLK_TOP_I2S0_M_SEL 122
133#define CLK_TOP_I2S1_M_SEL 123
134#define CLK_TOP_I2S2_M_SEL 124
135#define CLK_TOP_I2S3_M_SEL 125
136#define CLK_TOP_I2S4_M_SEL 126
137#define CLK_TOP_I2S5_M_SEL 127
138#define CLK_TOP_APLL12_DIV0 128
139#define CLK_TOP_APLL12_DIV1 129
140#define CLK_TOP_APLL12_DIV2 130
141#define CLK_TOP_APLL12_DIV3 131
142#define CLK_TOP_APLL12_DIV4 132
143#define CLK_TOP_APLL12_DIVB 133
144#define CLK_TOP_APLL12_DIV5 134
145#define CLK_TOP_IPE 135
146#define CLK_TOP_DPE 136
147#define CLK_TOP_CCU 137
148#define CLK_TOP_DSP3 138
149#define CLK_TOP_SENINF1 139
150#define CLK_TOP_SENINF2 140
151#define CLK_TOP_AUD_H 141
152#define CLK_TOP_CAMTG5 142
153#define CLK_TOP_TVDPLL_MAINPLL_D2_CK 143
154#define CLK_TOP_AD_OSC2_CK 144
155#define CLK_TOP_OSC2_D2 145
156#define CLK_TOP_OSC2_D3 146
157#define CLK_TOP_FMEM_466M_CK 147
158#define CLK_TOP_ADSPPLL_D4 148
159#define CLK_TOP_ADSPPLL_D5 149
160#define CLK_TOP_ADSPPLL_D6 150
161#define CLK_TOP_OSC_D10 151
162#define CLK_TOP_UNIVPLL_D3_D16 152
163#define CLK_TOP_NR_CLK 153
164
165/* APMIXED */
166#define CLK_APMIXED_ARMPLL_LL 1
167#define CLK_APMIXED_ARMPLL_BL 2
168#define CLK_APMIXED_ARMPLL_BB 3
169#define CLK_APMIXED_CCIPLL 4
170#define CLK_APMIXED_MAINPLL 5
171#define CLK_APMIXED_UNIV2PLL 6
172#define CLK_APMIXED_MSDCPLL 7
173#define CLK_APMIXED_ADSPPLL 8
174#define CLK_APMIXED_MMPLL 9
175#define CLK_APMIXED_MFGPLL 10
176#define CLK_APMIXED_TVDPLL 11
177#define CLK_APMIXED_APLL1 12
178#define CLK_APMIXED_APLL2 13
179#define CLK_APMIXED_SSUSB26M 14
180#define CLK_APMIXED_APPLL26M 15
181#define CLK_APMIXED_MIPIC0_26M 16
182#define CLK_APMIXED_MDPLLGP26M 17
183#define CLK_APMIXED_MM_F26M 18
184#define CLK_APMIXED_UFS26M 19
185#define CLK_APMIXED_MIPIC1_26M 20
186#define CLK_APMIXED_MEMPLL26M 21
187#define CLK_APMIXED_CLKSQ_LVPLL_26M 22
188#define CLK_APMIXED_MIPID0_26M 23
189#define CLK_APMIXED_MIPID1_26M 24
190#define CLK_APMIXED_NR_CLK 25
191
192/* CAMSYS */
193#define CLK_CAM_LARB10 1
194#define CLK_CAM_DFP_VAD 2
195#define CLK_CAM_LARB11 3
196#define CLK_CAM_LARB9 4
197#define CLK_CAM_CAM 5
198#define CLK_CAM_CAMTG 6
199#define CLK_CAM_SENINF 7
200#define CLK_CAM_CAMSV0 8
201#define CLK_CAM_CAMSV1 9
202#define CLK_CAM_CAMSV2 10
203#define CLK_CAM_CAMSV3 11
204#define CLK_CAM_CCU 12
205#define CLK_CAM_FAKE_ENG 13
206#define CLK_CAM_NR_CLK 14
207
208/* INFRA */
209#define CLK_INFRA_PMIC_TMR 1
210#define CLK_INFRA_PMIC_AP 2
211#define CLK_INFRA_PMIC_MD 3
212#define CLK_INFRA_PMIC_CONN 4
213#define CLK_INFRA_SCPSYS 5
214#define CLK_INFRA_SEJ 6
215#define CLK_INFRA_APXGPT 7
216#define CLK_INFRA_ICUSB 8
217#define CLK_INFRA_GCE 9
218#define CLK_INFRA_THERM 10
219#define CLK_INFRA_I2C0 11
220#define CLK_INFRA_I2C1 12
221#define CLK_INFRA_I2C2 13
222#define CLK_INFRA_I2C3 14
223#define CLK_INFRA_PWM_HCLK 15
224#define CLK_INFRA_PWM1 16
225#define CLK_INFRA_PWM2 17
226#define CLK_INFRA_PWM3 18
227#define CLK_INFRA_PWM4 19
228#define CLK_INFRA_PWM 20
229#define CLK_INFRA_UART0 21
230#define CLK_INFRA_UART1 22
231#define CLK_INFRA_UART2 23
232#define CLK_INFRA_UART3 24
233#define CLK_INFRA_GCE_26M 25
234#define CLK_INFRA_CQ_DMA_FPC 26
235#define CLK_INFRA_BTIF 27
236#define CLK_INFRA_SPI0 28
237#define CLK_INFRA_MSDC0 29
238#define CLK_INFRA_MSDC1 30
239#define CLK_INFRA_MSDC2 31
240#define CLK_INFRA_MSDC0_SCK 32
241#define CLK_INFRA_DVFSRC 33
242#define CLK_INFRA_GCPU 34
243#define CLK_INFRA_TRNG 35
244#define CLK_INFRA_AUXADC 36
245#define CLK_INFRA_CPUM 37
246#define CLK_INFRA_CCIF1_AP 38
247#define CLK_INFRA_CCIF1_MD 39
248#define CLK_INFRA_AUXADC_MD 40
249#define CLK_INFRA_MSDC1_SCK 41
250#define CLK_INFRA_MSDC2_SCK 42
251#define CLK_INFRA_AP_DMA 43
252#define CLK_INFRA_XIU 44
253#define CLK_INFRA_DEVICE_APC 45
254#define CLK_INFRA_CCIF_AP 46
255#define CLK_INFRA_DEBUGSYS 47
256#define CLK_INFRA_AUD 48
257#define CLK_INFRA_CCIF_MD 49
258#define CLK_INFRA_DXCC_SEC_CORE 50
259#define CLK_INFRA_DXCC_AO 51
260#define CLK_INFRA_DRAMC_F26M 52
261#define CLK_INFRA_IRTX 53
262#define CLK_INFRA_DISP_PWM 54
263#define CLK_INFRA_DPMAIF_CK 55
264#define CLK_INFRA_AUD_26M_BCLK 56
265#define CLK_INFRA_SPI1 57
266#define CLK_INFRA_I2C4 58
267#define CLK_INFRA_MODEM_TEMP_SHARE 59
268#define CLK_INFRA_SPI2 60
269#define CLK_INFRA_SPI3 61
270#define CLK_INFRA_UNIPRO_SCK 62
271#define CLK_INFRA_UNIPRO_TICK 63
272#define CLK_INFRA_UFS_MP_SAP_BCLK 64
273#define CLK_INFRA_MD32_BCLK 65
274#define CLK_INFRA_SSPM 66
275#define CLK_INFRA_UNIPRO_MBIST 67
276#define CLK_INFRA_SSPM_BUS_HCLK 68
277#define CLK_INFRA_I2C5 69
278#define CLK_INFRA_I2C5_ARBITER 70
279#define CLK_INFRA_I2C5_IMM 71
280#define CLK_INFRA_I2C1_ARBITER 72
281#define CLK_INFRA_I2C1_IMM 73
282#define CLK_INFRA_I2C2_ARBITER 74
283#define CLK_INFRA_I2C2_IMM 75
284#define CLK_INFRA_SPI4 76
285#define CLK_INFRA_SPI5 77
286#define CLK_INFRA_CQ_DMA 78
287#define CLK_INFRA_UFS 79
288#define CLK_INFRA_AES_UFSFDE 80
289#define CLK_INFRA_UFS_TICK 81
290#define CLK_INFRA_MSDC0_SELF 82
291#define CLK_INFRA_MSDC1_SELF 83
292#define CLK_INFRA_MSDC2_SELF 84
293#define CLK_INFRA_SSPM_26M_SELF 85
294#define CLK_INFRA_SSPM_32K_SELF 86
295#define CLK_INFRA_UFS_AXI 87
296#define CLK_INFRA_I2C6 88
297#define CLK_INFRA_AP_MSDC0 89
298#define CLK_INFRA_MD_MSDC0 90
299#define CLK_INFRA_USB 91
300#define CLK_INFRA_DEVMPU_BCLK 92
301#define CLK_INFRA_CCIF2_AP 93
302#define CLK_INFRA_CCIF2_MD 94
303#define CLK_INFRA_CCIF3_AP 95
304#define CLK_INFRA_CCIF3_MD 96
305#define CLK_INFRA_SEJ_F13M 97
306#define CLK_INFRA_AES_BCLK 98
307#define CLK_INFRA_I2C7 99
308#define CLK_INFRA_I2C8 100
309#define CLK_INFRA_FBIST2FPC 101
310#define CLK_INFRA_CCIF4_AP 102
311#define CLK_INFRA_CCIF4_MD 103
312#define CLK_INFRA_FADSP 104
313#define CLK_INFRA_SSUSB_XHCI 105
314#define CLK_INFRA_SPI6 106
315#define CLK_INFRA_SPI7 107
316#define CLK_INFRA_NR_CLK 108
317
318/* MFGCFG */
319#define CLK_MFGCFG_BG3D 1
320#define CLK_MFGCFG_NR_CLK 2
321
322/* IMG */
323#define CLK_IMG_WPE_A 1
324#define CLK_IMG_MFB 2
325#define CLK_IMG_DIP 3
326#define CLK_IMG_LARB6 4
327#define CLK_IMG_LARB5 5
328#define CLK_IMG_NR_CLK 6
329
330/* IPE */
331#define CLK_IPE_LARB7 1
332#define CLK_IPE_LARB8 2
333#define CLK_IPE_SMI_SUBCOM 3
334#define CLK_IPE_FD 4
335#define CLK_IPE_FE 5
336#define CLK_IPE_RSC 6
337#define CLK_IPE_DPE 7
338#define CLK_IPE_NR_CLK 8
339
340/* MM_CONFIG */
341#define CLK_MM_SMI_COMMON 1
342#define CLK_MM_SMI_LARB0 2
343#define CLK_MM_SMI_LARB1 3
344#define CLK_MM_GALS_COMM0 4
345#define CLK_MM_GALS_COMM1 5
346#define CLK_MM_GALS_CCU2MM 6
347#define CLK_MM_GALS_IPU12MM 7
348#define CLK_MM_GALS_IMG2MM 8
349#define CLK_MM_GALS_CAM2MM 9
350#define CLK_MM_GALS_IPU2MM 10
351#define CLK_MM_MDP_DL_TXCK 11
352#define CLK_MM_IPU_DL_TXCK 12
353#define CLK_MM_MDP_RDMA0 13
354#define CLK_MM_MDP_RDMA1 14
355#define CLK_MM_MDP_RSZ0 15
356#define CLK_MM_MDP_RSZ1 16
357#define CLK_MM_MDP_TDSHP 17
358#define CLK_MM_MDP_WROT0 18
359#define CLK_MM_FAKE_ENG 19
360#define CLK_MM_DISP_OVL0 20
361#define CLK_MM_DISP_OVL0_2L 21
362#define CLK_MM_DISP_OVL1_2L 22
363#define CLK_MM_DISP_RDMA0 23
364#define CLK_MM_DISP_RDMA1 24
365#define CLK_MM_DISP_WDMA0 25
366#define CLK_MM_DISP_COLOR0 26
367#define CLK_MM_DISP_CCORR0 27
368#define CLK_MM_DISP_AAL0 28
369#define CLK_MM_DISP_GAMMA0 29
370#define CLK_MM_DISP_DITHER0 30
371#define CLK_MM_DISP_SPLIT 31
372#define CLK_MM_DSI0_MM_CK 32
373#define CLK_MM_DSI0_IF_CK 33
374#define CLK_MM_DPI_MM_CK 34
375#define CLK_MM_DPI_IF_CK 35
376#define CLK_MM_FAKE_ENG2 36
377#define CLK_MM_MDP_DL_RX_CK 37
378#define CLK_MM_IPU_DL_RX_CK 38
379#define CLK_MM_26M 39
380#define CLK_MM_MM_R2Y 40
381#define CLK_MM_DISP_RSZ 41
382#define CLK_MM_MDP_WDMA0 42
383#define CLK_MM_MDP_AAL 43
384#define CLK_MM_MDP_HDR 44
385#define CLK_MM_DBI_MM_CK 45
386#define CLK_MM_DBI_IF_CK 46
387#define CLK_MM_MDP_WROT1 47
388#define CLK_MM_DISP_POSTMASK0 48
389#define CLK_MM_DISP_HRT_BW 49
390#define CLK_MM_DISP_OVL_FBDC 50
391#define CLK_MM_NR_CLK 51
392
393/* VDEC_GCON */
394#define CLK_VDEC_VDEC 1
395#define CLK_VDEC_LARB1 2
396#define CLK_VDEC_GCON_NR_CLK 3
397
398/* VENC_GCON */
399#define CLK_VENC_GCON_LARB 1
400#define CLK_VENC_GCON_VENC 2
401#define CLK_VENC_GCON_JPGENC 3
402#define CLK_VENC_GCON_GALS 4
403#define CLK_VENC_GCON_NR_CLK 5
404
405/* AUD */
406#define CLK_AUD_AFE 1
407#define CLK_AUD_22M 2
408#define CLK_AUD_24M 3
409#define CLK_AUD_APLL2_TUNER 4
410#define CLK_AUD_APLL_TUNER 5
411#define CLK_AUD_TDM 6
412#define CLK_AUD_ADC 7
413#define CLK_AUD_DAC 8
414#define CLK_AUD_DAC_PREDIS 9
415#define CLK_AUD_TML 10
416#define CLK_AUD_NLE 11
417#define CLK_AUD_I2S1_BCLK_SW 12
418#define CLK_AUD_I2S2_BCLK_SW 13
419#define CLK_AUD_I2S3_BCLK_SW 14
420#define CLK_AUD_I2S4_BCLK_SW 15
421#define CLK_AUD_I2S5_BCLK_SW 16
422#define CLK_AUD_CONN_I2S_ASRC 17
423#define CLK_AUD_GENERAL1_ASRC 18
424#define CLK_AUD_GENERAL2_ASRC 19
425#define CLK_AUD_DAC_HIRES 20
426#define CLK_AUD_PDN_ADDA6_ADC 21
427#define CLK_AUD_ADC_HIRES 22
428#define CLK_AUD_ADC_HIRES_TML 23
429#define CLK_AUD_ADDA6_ADC_HIRES 24
430#define CLK_AUD_3RD_DAC 25
431#define CLK_AUD_3RD_DAC_PREDIS 26
432#define CLK_AUD_3RD_DAC_TML 27
433#define CLK_AUD_3RD_DAC_HIRES 28
434#define CLK_AUD_NR_CLK 29
435
436#endif /* _DT_BINDINGS_CLK_MT6779_H */
diff --git a/include/dt-bindings/clock/mt8183-clk.h b/include/dt-bindings/clock/mt8183-clk.h
index 0046506eb24c..a7b470b0ec8a 100644
--- a/include/dt-bindings/clock/mt8183-clk.h
+++ b/include/dt-bindings/clock/mt8183-clk.h
@@ -284,6 +284,10 @@
284#define CLK_INFRA_FBIST2FPC 100 284#define CLK_INFRA_FBIST2FPC 100
285#define CLK_INFRA_NR_CLK 101 285#define CLK_INFRA_NR_CLK 101
286 286
287/* PERICFG */
288#define CLK_PERI_AXI 0
289#define CLK_PERI_NR_CLK 1
290
287/* MFGCFG */ 291/* MFGCFG */
288#define CLK_MFG_BG3D 0 292#define CLK_MFG_BG3D 0
289#define CLK_MFG_NR_CLK 1 293#define CLK_MFG_NR_CLK 1
diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
index 2cd62c98561f..bc3051543347 100644
--- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
+++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
@@ -146,6 +146,8 @@
146#define GCC_MDP_TBU_CLK 138 146#define GCC_MDP_TBU_CLK 138
147#define GCC_QDSS_DAP_CLK 139 147#define GCC_QDSS_DAP_CLK 139
148#define GCC_DCC_XO_CLK 140 148#define GCC_DCC_XO_CLK 140
149#define GCC_WCSS_Q6_AHB_CLK 141
150#define GCC_WCSS_Q6_AXIM_CLK 142
149#define GCC_CDSP_CFG_AHB_CLK 143 151#define GCC_CDSP_CFG_AHB_CLK 143
150#define GCC_BIMC_CDSP_CLK 144 152#define GCC_BIMC_CDSP_CLK 144
151#define GCC_CDSP_TBU_CLK 145 153#define GCC_CDSP_TBU_CLK 145
@@ -173,5 +175,6 @@
173#define GCC_PCIE_0_CORE_STICKY_ARES 19 175#define GCC_PCIE_0_CORE_STICKY_ARES 19
174#define GCC_PCIE_0_SLEEP_ARES 20 176#define GCC_PCIE_0_SLEEP_ARES 20
175#define GCC_PCIE_0_PIPE_ARES 21 177#define GCC_PCIE_0_PIPE_ARES 21
178#define GCC_WDSP_RESTART 22
176 179
177#endif 180#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h
new file mode 100644
index 000000000000..90d60ef94c64
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h
@@ -0,0 +1,243 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8150_H
7#define _DT_BINDINGS_CLK_QCOM_GCC_SM8150_H
8
9/* GCC clocks */
10#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0
11#define GCC_AGGRE_UFS_CARD_AXI_CLK 1
12#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 2
13#define GCC_AGGRE_UFS_PHY_AXI_CLK 3
14#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 4
15#define GCC_AGGRE_USB3_PRIM_AXI_CLK 5
16#define GCC_AGGRE_USB3_SEC_AXI_CLK 6
17#define GCC_BOOT_ROM_AHB_CLK 7
18#define GCC_CAMERA_AHB_CLK 8
19#define GCC_CAMERA_HF_AXI_CLK 9
20#define GCC_CAMERA_SF_AXI_CLK 10
21#define GCC_CAMERA_XO_CLK 11
22#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12
23#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13
24#define GCC_CPUSS_AHB_CLK 14
25#define GCC_CPUSS_AHB_CLK_SRC 15
26#define GCC_CPUSS_DVM_BUS_CLK 16
27#define GCC_CPUSS_GNOC_CLK 17
28#define GCC_CPUSS_RBCPR_CLK 18
29#define GCC_DDRSS_GPU_AXI_CLK 19
30#define GCC_DISP_AHB_CLK 20
31#define GCC_DISP_HF_AXI_CLK 21
32#define GCC_DISP_SF_AXI_CLK 22
33#define GCC_DISP_XO_CLK 23
34#define GCC_EMAC_AXI_CLK 24
35#define GCC_EMAC_PTP_CLK 25
36#define GCC_EMAC_PTP_CLK_SRC 26
37#define GCC_EMAC_RGMII_CLK 27
38#define GCC_EMAC_RGMII_CLK_SRC 28
39#define GCC_EMAC_SLV_AHB_CLK 29
40#define GCC_GP1_CLK 30
41#define GCC_GP1_CLK_SRC 31
42#define GCC_GP2_CLK 32
43#define GCC_GP2_CLK_SRC 33
44#define GCC_GP3_CLK 34
45#define GCC_GP3_CLK_SRC 35
46#define GCC_GPU_CFG_AHB_CLK 36
47#define GCC_GPU_GPLL0_CLK_SRC 37
48#define GCC_GPU_GPLL0_DIV_CLK_SRC 38
49#define GCC_GPU_IREF_CLK 39
50#define GCC_GPU_MEMNOC_GFX_CLK 40
51#define GCC_GPU_SNOC_DVM_GFX_CLK 41
52#define GCC_NPU_AT_CLK 42
53#define GCC_NPU_AXI_CLK 43
54#define GCC_NPU_CFG_AHB_CLK 44
55#define GCC_NPU_GPLL0_CLK_SRC 45
56#define GCC_NPU_GPLL0_DIV_CLK_SRC 46
57#define GCC_NPU_TRIG_CLK 47
58#define GCC_PCIE0_PHY_REFGEN_CLK 48
59#define GCC_PCIE1_PHY_REFGEN_CLK 49
60#define GCC_PCIE_0_AUX_CLK 50
61#define GCC_PCIE_0_AUX_CLK_SRC 51
62#define GCC_PCIE_0_CFG_AHB_CLK 52
63#define GCC_PCIE_0_CLKREF_CLK 53
64#define GCC_PCIE_0_MSTR_AXI_CLK 54
65#define GCC_PCIE_0_PIPE_CLK 55
66#define GCC_PCIE_0_SLV_AXI_CLK 56
67#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57
68#define GCC_PCIE_1_AUX_CLK 58
69#define GCC_PCIE_1_AUX_CLK_SRC 59
70#define GCC_PCIE_1_CFG_AHB_CLK 60
71#define GCC_PCIE_1_CLKREF_CLK 61
72#define GCC_PCIE_1_MSTR_AXI_CLK 62
73#define GCC_PCIE_1_PIPE_CLK 63
74#define GCC_PCIE_1_SLV_AXI_CLK 64
75#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 65
76#define GCC_PCIE_PHY_AUX_CLK 66
77#define GCC_PCIE_PHY_REFGEN_CLK_SRC 67
78#define GCC_PDM2_CLK 68
79#define GCC_PDM2_CLK_SRC 69
80#define GCC_PDM_AHB_CLK 70
81#define GCC_PDM_XO4_CLK 71
82#define GCC_PRNG_AHB_CLK 72
83#define GCC_QMIP_CAMERA_NRT_AHB_CLK 73
84#define GCC_QMIP_CAMERA_RT_AHB_CLK 74
85#define GCC_QMIP_DISP_AHB_CLK 75
86#define GCC_QMIP_VIDEO_CVP_AHB_CLK 76
87#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 77
88#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 78
89#define GCC_QSPI_CORE_CLK 79
90#define GCC_QSPI_CORE_CLK_SRC 80
91#define GCC_QUPV3_WRAP0_S0_CLK 81
92#define GCC_QUPV3_WRAP0_S0_CLK_SRC 82
93#define GCC_QUPV3_WRAP0_S1_CLK 83
94#define GCC_QUPV3_WRAP0_S1_CLK_SRC 84
95#define GCC_QUPV3_WRAP0_S2_CLK 85
96#define GCC_QUPV3_WRAP0_S2_CLK_SRC 86
97#define GCC_QUPV3_WRAP0_S3_CLK 87
98#define GCC_QUPV3_WRAP0_S3_CLK_SRC 88
99#define GCC_QUPV3_WRAP0_S4_CLK 89
100#define GCC_QUPV3_WRAP0_S4_CLK_SRC 90
101#define GCC_QUPV3_WRAP0_S5_CLK 91
102#define GCC_QUPV3_WRAP0_S5_CLK_SRC 92
103#define GCC_QUPV3_WRAP0_S6_CLK 93
104#define GCC_QUPV3_WRAP0_S6_CLK_SRC 94
105#define GCC_QUPV3_WRAP0_S7_CLK 95
106#define GCC_QUPV3_WRAP0_S7_CLK_SRC 96
107#define GCC_QUPV3_WRAP1_S0_CLK 97
108#define GCC_QUPV3_WRAP1_S0_CLK_SRC 98
109#define GCC_QUPV3_WRAP1_S1_CLK 99
110#define GCC_QUPV3_WRAP1_S1_CLK_SRC 100
111#define GCC_QUPV3_WRAP1_S2_CLK 101
112#define GCC_QUPV3_WRAP1_S2_CLK_SRC 102
113#define GCC_QUPV3_WRAP1_S3_CLK 103
114#define GCC_QUPV3_WRAP1_S3_CLK_SRC 104
115#define GCC_QUPV3_WRAP1_S4_CLK 105
116#define GCC_QUPV3_WRAP1_S4_CLK_SRC 106
117#define GCC_QUPV3_WRAP1_S5_CLK 107
118#define GCC_QUPV3_WRAP1_S5_CLK_SRC 108
119#define GCC_QUPV3_WRAP2_S0_CLK 109
120#define GCC_QUPV3_WRAP2_S0_CLK_SRC 110
121#define GCC_QUPV3_WRAP2_S1_CLK 111
122#define GCC_QUPV3_WRAP2_S1_CLK_SRC 112
123#define GCC_QUPV3_WRAP2_S2_CLK 113
124#define GCC_QUPV3_WRAP2_S2_CLK_SRC 114
125#define GCC_QUPV3_WRAP2_S3_CLK 115
126#define GCC_QUPV3_WRAP2_S3_CLK_SRC 116
127#define GCC_QUPV3_WRAP2_S4_CLK 117
128#define GCC_QUPV3_WRAP2_S4_CLK_SRC 118
129#define GCC_QUPV3_WRAP2_S5_CLK 119
130#define GCC_QUPV3_WRAP2_S5_CLK_SRC 120
131#define GCC_QUPV3_WRAP_0_M_AHB_CLK 121
132#define GCC_QUPV3_WRAP_0_S_AHB_CLK 122
133#define GCC_QUPV3_WRAP_1_M_AHB_CLK 123
134#define GCC_QUPV3_WRAP_1_S_AHB_CLK 124
135#define GCC_QUPV3_WRAP_2_M_AHB_CLK 125
136#define GCC_QUPV3_WRAP_2_S_AHB_CLK 126
137#define GCC_SDCC2_AHB_CLK 127
138#define GCC_SDCC2_APPS_CLK 128
139#define GCC_SDCC2_APPS_CLK_SRC 129
140#define GCC_SDCC4_AHB_CLK 130
141#define GCC_SDCC4_APPS_CLK 131
142#define GCC_SDCC4_APPS_CLK_SRC 132
143#define GCC_SYS_NOC_CPUSS_AHB_CLK 133
144#define GCC_TSIF_AHB_CLK 134
145#define GCC_TSIF_INACTIVITY_TIMERS_CLK 135
146#define GCC_TSIF_REF_CLK 136
147#define GCC_TSIF_REF_CLK_SRC 137
148#define GCC_UFS_CARD_AHB_CLK 138
149#define GCC_UFS_CARD_AXI_CLK 139
150#define GCC_UFS_CARD_AXI_CLK_SRC 140
151#define GCC_UFS_CARD_AXI_HW_CTL_CLK 141
152#define GCC_UFS_CARD_CLKREF_CLK 142
153#define GCC_UFS_CARD_ICE_CORE_CLK 143
154#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 144
155#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 145
156#define GCC_UFS_CARD_PHY_AUX_CLK 146
157#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 147
158#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 148
159#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 149
160#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 150
161#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 151
162#define GCC_UFS_CARD_UNIPRO_CORE_CLK 152
163#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 153
164#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 154
165#define GCC_UFS_MEM_CLKREF_CLK 155
166#define GCC_UFS_PHY_AHB_CLK 156
167#define GCC_UFS_PHY_AXI_CLK 157
168#define GCC_UFS_PHY_AXI_CLK_SRC 158
169#define GCC_UFS_PHY_AXI_HW_CTL_CLK 159
170#define GCC_UFS_PHY_ICE_CORE_CLK 160
171#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 161
172#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 162
173#define GCC_UFS_PHY_PHY_AUX_CLK 163
174#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 164
175#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 165
176#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 166
177#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 167
178#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 168
179#define GCC_UFS_PHY_UNIPRO_CORE_CLK 169
180#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 170
181#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 171
182#define GCC_USB30_PRIM_MASTER_CLK 172
183#define GCC_USB30_PRIM_MASTER_CLK_SRC 173
184#define GCC_USB30_PRIM_MOCK_UTMI_CLK 174
185#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 175
186#define GCC_USB30_PRIM_SLEEP_CLK 176
187#define GCC_USB30_SEC_MASTER_CLK 177
188#define GCC_USB30_SEC_MASTER_CLK_SRC 178
189#define GCC_USB30_SEC_MOCK_UTMI_CLK 179
190#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 180
191#define GCC_USB30_SEC_SLEEP_CLK 181
192#define GCC_USB3_PRIM_CLKREF_CLK 182
193#define GCC_USB3_PRIM_PHY_AUX_CLK 183
194#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 184
195#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 185
196#define GCC_USB3_PRIM_PHY_PIPE_CLK 186
197#define GCC_USB3_SEC_CLKREF_CLK 187
198#define GCC_USB3_SEC_PHY_AUX_CLK 188
199#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 189
200#define GCC_USB3_SEC_PHY_COM_AUX_CLK 190
201#define GCC_USB3_SEC_PHY_PIPE_CLK 191
202#define GCC_VIDEO_AHB_CLK 192
203#define GCC_VIDEO_AXI0_CLK 193
204#define GCC_VIDEO_AXI1_CLK 194
205#define GCC_VIDEO_AXIC_CLK 195
206#define GCC_VIDEO_XO_CLK 196
207#define GPLL0 197
208#define GPLL0_OUT_EVEN 198
209#define GPLL7 199
210#define GPLL9 200
211
212/* Reset clocks */
213#define GCC_EMAC_BCR 0
214#define GCC_GPU_BCR 1
215#define GCC_MMSS_BCR 2
216#define GCC_NPU_BCR 3
217#define GCC_PCIE_0_BCR 4
218#define GCC_PCIE_0_PHY_BCR 5
219#define GCC_PCIE_1_BCR 6
220#define GCC_PCIE_1_PHY_BCR 7
221#define GCC_PCIE_PHY_BCR 8
222#define GCC_PDM_BCR 9
223#define GCC_PRNG_BCR 10
224#define GCC_QSPI_BCR 11
225#define GCC_QUPV3_WRAPPER_0_BCR 12
226#define GCC_QUPV3_WRAPPER_1_BCR 13
227#define GCC_QUPV3_WRAPPER_2_BCR 14
228#define GCC_QUSB2PHY_PRIM_BCR 15
229#define GCC_QUSB2PHY_SEC_BCR 16
230#define GCC_USB3_PHY_PRIM_BCR 17
231#define GCC_USB3_DP_PHY_PRIM_BCR 18
232#define GCC_USB3_PHY_SEC_BCR 19
233#define GCC_USB3PHY_PHY_SEC_BCR 20
234#define GCC_SDCC2_BCR 21
235#define GCC_SDCC4_BCR 22
236#define GCC_TSIF_BCR 23
237#define GCC_UFS_CARD_BCR 24
238#define GCC_UFS_PHY_BCR 25
239#define GCC_USB30_PRIM_BCR 26
240#define GCC_USB30_SEC_BCR 27
241#define GCC_USB_PHY_CFG_AHB2PHY_BCR 28
242
243#endif
diff --git a/include/dt-bindings/reset-controller/mt8183-resets.h b/include/dt-bindings/reset-controller/mt8183-resets.h
new file mode 100644
index 000000000000..8804e34ebdd4
--- /dev/null
+++ b/include/dt-bindings/reset-controller/mt8183-resets.h
@@ -0,0 +1,81 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2019 MediaTek Inc.
4 * Author: Yong Liang <yong.liang@mediatek.com>
5 */
6
7#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8183
8#define _DT_BINDINGS_RESET_CONTROLLER_MT8183
9
10/* INFRACFG AO resets */
11#define MT8183_INFRACFG_AO_THERM_SW_RST 0
12#define MT8183_INFRACFG_AO_USB_TOP_SW_RST 1
13#define MT8183_INFRACFG_AO_MM_IOMMU_SW_RST 3
14#define MT8183_INFRACFG_AO_MSDC3_SW_RST 4
15#define MT8183_INFRACFG_AO_MSDC2_SW_RST 5
16#define MT8183_INFRACFG_AO_MSDC1_SW_RST 6
17#define MT8183_INFRACFG_AO_MSDC0_SW_RST 7
18#define MT8183_INFRACFG_AO_APDMA_SW_RST 9
19#define MT8183_INFRACFG_AO_MIMP_D_SW_RST 10
20#define MT8183_INFRACFG_AO_BTIF_SW_RST 12
21#define MT8183_INFRACFG_AO_DISP_PWM_SW_RST 14
22#define MT8183_INFRACFG_AO_AUXADC_SW_RST 15
23
24#define MT8183_INFRACFG_AO_IRTX_SW_RST 32
25#define MT8183_INFRACFG_AO_SPI0_SW_RST 33
26#define MT8183_INFRACFG_AO_I2C0_SW_RST 34
27#define MT8183_INFRACFG_AO_I2C1_SW_RST 35
28#define MT8183_INFRACFG_AO_I2C2_SW_RST 36
29#define MT8183_INFRACFG_AO_I2C3_SW_RST 37
30#define MT8183_INFRACFG_AO_UART0_SW_RST 38
31#define MT8183_INFRACFG_AO_UART1_SW_RST 39
32#define MT8183_INFRACFG_AO_UART2_SW_RST 40
33#define MT8183_INFRACFG_AO_PWM_SW_RST 41
34#define MT8183_INFRACFG_AO_SPI1_SW_RST 42
35#define MT8183_INFRACFG_AO_I2C4_SW_RST 43
36#define MT8183_INFRACFG_AO_DVFSP_SW_RST 44
37#define MT8183_INFRACFG_AO_SPI2_SW_RST 45
38#define MT8183_INFRACFG_AO_SPI3_SW_RST 46
39#define MT8183_INFRACFG_AO_UFSHCI_SW_RST 47
40
41#define MT8183_INFRACFG_AO_PMIC_WRAP_SW_RST 64
42#define MT8183_INFRACFG_AO_SPM_SW_RST 65
43#define MT8183_INFRACFG_AO_USBSIF_SW_RST 66
44#define MT8183_INFRACFG_AO_KP_SW_RST 68
45#define MT8183_INFRACFG_AO_APXGPT_SW_RST 69
46#define MT8183_INFRACFG_AO_CLDMA_AO_SW_RST 70
47#define MT8183_INFRACFG_AO_UNIPRO_UFS_SW_RST 71
48#define MT8183_INFRACFG_AO_DX_CC_SW_RST 72
49#define MT8183_INFRACFG_AO_UFSPHY_SW_RST 73
50
51#define MT8183_INFRACFG_AO_DX_CC_SEC_SW_RST 96
52#define MT8183_INFRACFG_AO_GCE_SW_RST 97
53#define MT8183_INFRACFG_AO_CLDMA_SW_RST 98
54#define MT8183_INFRACFG_AO_TRNG_SW_RST 99
55#define MT8183_INFRACFG_AO_AP_MD_CCIF_1_SW_RST 103
56#define MT8183_INFRACFG_AO_AP_MD_CCIF_SW_RST 104
57#define MT8183_INFRACFG_AO_I2C1_IMM_SW_RST 105
58#define MT8183_INFRACFG_AO_I2C1_ARB_SW_RST 106
59#define MT8183_INFRACFG_AO_I2C2_IMM_SW_RST 107
60#define MT8183_INFRACFG_AO_I2C2_ARB_SW_RST 108
61#define MT8183_INFRACFG_AO_I2C5_SW_RST 109
62#define MT8183_INFRACFG_AO_I2C5_IMM_SW_RST 110
63#define MT8183_INFRACFG_AO_I2C5_ARB_SW_RST 111
64#define MT8183_INFRACFG_AO_SPI4_SW_RST 112
65#define MT8183_INFRACFG_AO_SPI5_SW_RST 113
66#define MT8183_INFRACFG_AO_INFRA2MFGAXI_CBIP_CLAS_SW_RST 114
67#define MT8183_INFRACFG_AO_MFGAXI2INFRA_M0_CBIP_GLAS_OUT_SW_RST 115
68#define MT8183_INFRACFG_AO_MFGAXI2INFRA_M1_CBIP_GLAS_OUT_SW_RST 116
69#define MT8183_INFRACFG_AO_UFS_AES_SW_RST 117
70#define MT8183_INFRACFG_AO_CCU_I2C_IRQ_SW_RST 118
71#define MT8183_INFRACFG_AO_CCU_I2C_DMA_SW_RST 119
72#define MT8183_INFRACFG_AO_I2C6_SW_RST 120
73#define MT8183_INFRACFG_AO_CCU_GALS_SW_RST 121
74#define MT8183_INFRACFG_AO_IPU_GALS_SW_RST 122
75#define MT8183_INFRACFG_AO_CONN2AP_GALS_SW_RST 123
76#define MT8183_INFRACFG_AO_AP_MD_CCIF2_SW_RST 124
77#define MT8183_INFRACFG_AO_AP_MD_CCIF3_SW_RST 125
78#define MT8183_INFRACFG_AO_I2C7_SW_RST 126
79#define MT8183_INFRACFG_AO_I2C8_SW_RST 127
80
81#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8183 */
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 3c096c7a51dc..7a795fd6d141 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -239,7 +239,8 @@ static inline int clk_prepare(struct clk *clk)
239 return 0; 239 return 0;
240} 240}
241 241
242static inline int __must_check clk_bulk_prepare(int num_clks, struct clk_bulk_data *clks) 242static inline int __must_check
243clk_bulk_prepare(int num_clks, const struct clk_bulk_data *clks)
243{ 244{
244 might_sleep(); 245 might_sleep();
245 return 0; 246 return 0;
@@ -263,7 +264,8 @@ static inline void clk_unprepare(struct clk *clk)
263{ 264{
264 might_sleep(); 265 might_sleep();
265} 266}
266static inline void clk_bulk_unprepare(int num_clks, struct clk_bulk_data *clks) 267static inline void clk_bulk_unprepare(int num_clks,
268 const struct clk_bulk_data *clks)
267{ 269{
268 might_sleep(); 270 might_sleep();
269} 271}
@@ -819,7 +821,8 @@ static inline int clk_enable(struct clk *clk)
819 return 0; 821 return 0;
820} 822}
821 823
822static inline int __must_check clk_bulk_enable(int num_clks, struct clk_bulk_data *clks) 824static inline int __must_check clk_bulk_enable(int num_clks,
825 const struct clk_bulk_data *clks)
823{ 826{
824 return 0; 827 return 0;
825} 828}
@@ -828,7 +831,7 @@ static inline void clk_disable(struct clk *clk) {}
828 831
829 832
830static inline void clk_bulk_disable(int num_clks, 833static inline void clk_bulk_disable(int num_clks,
831 struct clk_bulk_data *clks) {} 834 const struct clk_bulk_data *clks) {}
832 835
833static inline unsigned long clk_get_rate(struct clk *clk) 836static inline unsigned long clk_get_rate(struct clk *clk)
834{ 837{
@@ -917,8 +920,8 @@ static inline void clk_disable_unprepare(struct clk *clk)
917 clk_unprepare(clk); 920 clk_unprepare(clk);
918} 921}
919 922
920static inline int __must_check clk_bulk_prepare_enable(int num_clks, 923static inline int __must_check
921 struct clk_bulk_data *clks) 924clk_bulk_prepare_enable(int num_clks, const struct clk_bulk_data *clks)
922{ 925{
923 int ret; 926 int ret;
924 927
@@ -933,7 +936,7 @@ static inline int __must_check clk_bulk_prepare_enable(int num_clks,
933} 936}
934 937
935static inline void clk_bulk_disable_unprepare(int num_clks, 938static inline void clk_bulk_disable_unprepare(int num_clks,
936 struct clk_bulk_data *clks) 939 const struct clk_bulk_data *clks)
937{ 940{
938 clk_bulk_disable(num_clks, clks); 941 clk_bulk_disable(num_clks, clks);
939 clk_bulk_unprepare(num_clks, clks); 942 clk_bulk_unprepare(num_clks, clks);
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-10 20:25:19 -0400