74 files changed, 9087 insertions, 1523 deletions

diff --git a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
index 7b8b8eb0191f..26410fbb85be 100644
--- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
@@ -18,17 +18,19 @@ Clocks:
 -------
 
 
-The Device Tree node representing the AP806 system controller provides
-a number of clocks:
+The Device Tree node representing the AP806/AP807 system controller
+provides a number of clocks:
 
- - 0: clock of CPU cluster 0
- - 1: clock of CPU cluster 1
+ - 0: reference clock of CPU cluster 0
+ - 1: reference clock of CPU cluster 1
  - 2: fixed PLL at 1200 Mhz
  - 3: MSS clock, derived from the fixed PLL
 
 Required properties:
 
- - compatible: must be: "marvell,ap806-clock"
+ - compatible: must be one of:
+   * "marvell,ap806-clock"
+   * "marvell,ap807-clock"
  - #clock-cells: must be set to 1
 
 Pinctrl:
@@ -143,3 +145,33 @@ ap_syscon1: system-controller@6f8000 {
                 #thermal-sensor-cells = <1>;
         };
 };
+
+Cluster clocks:
+---------------
+
+Device Tree Clock bindings for cluster clock of Marvell
+AP806/AP807. Each cluster contain up to 2 CPUs running at the same
+frequency.
+
+Required properties:
+ - compatible: must be one of:
+   * "marvell,ap806-cpu-clock"
+   * "marvell,ap807-cpu-clock"
+- #clock-cells : should be set to 1.
+
+- clocks : shall be the input parent clock(s) phandle for the clock
+           (one per cluster)
+
+- reg: register range associated with the cluster clocks
+
+ap_syscon1: system-controller@6f8000 {
+        compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd";
+        reg = <0x6f8000 0x1000>;
+
+        cpu_clk: clock-cpu@278 {
+                compatible = "marvell,ap806-cpu-clock";
+                clocks = <&ap_clk 0>, <&ap_clk 1>;
+                #clock-cells = <1>;
+                reg = <0x278 0xa30>;
+        };
+};
diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
index 0f777749f4f1..b3957d10d241 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
@@ -22,6 +22,7 @@ Required Properties:
                                        components.
 - resets        : phandle of the internal reset line
 - #clock-cells  : should be 1.
+- #reset-cells  : should be 1 on the g12a (and following) soc family
 
 Each clock is assigned an identifier and client nodes can use this identifier
 to specify the clock which they consume. All available clocks are defined as
diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
index 6eaa52092313..7ccecd5c02c1 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
@@ -11,6 +11,7 @@ Required Properties:
                 "amlogic,axg-clkc" for AXG SoC.
                 "amlogic,g12a-clkc" for G12A SoC.
                 "amlogic,g12b-clkc" for G12B SoC.
+                "amlogic,sm1-clkc" for SM1 SoC.
 - clocks : list of clock phandle, one for each entry clock-names.
 - clock-names : should contain the following:
   * "xtal": the platform xtal
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 8661c3cd3ccf..d14362ad4132 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -23,6 +23,7 @@ Required properties :
                         "qcom,gcc-sdm630"
                         "qcom,gcc-sdm660"
                         "qcom,gcc-sdm845"
+                        "qcom,gcc-sm8150"
 
 - reg : shall contain base register location and length
 - #clock-cells : shall contain 1
@@ -38,6 +39,13 @@ Documentation/devicetree/bindings/thermal/qcom-tsens.txt
 - protected-clocks : Protected clock specifier list as per common clock
  binding.
 
+For SM8150 only:
+       - clocks: a list of phandles and clock-specifier pairs,
+                 one for each entry in clock-names.
+       - clock-names: "bi_tcxo" (required)
+                      "sleep_clk" (optional)
+                      "aud_ref_clock" (optional)
+
 Example:
         clock-controller@900000 {
                 compatible = "qcom,gcc-msm8960";
@@ -71,3 +79,16 @@ Example of GCC with protected-clocks properties:
                                    <GCC_LPASS_Q6_AXI_CLK>,
                                    <GCC_LPASS_SWAY_CLK>;
         };
+
+Example of GCC with clocks
+        gcc: clock-controller@100000 {
+                compatible = "qcom,gcc-sm8150";
+                reg = <0x00100000 0x1f0000>;
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+                #power-domain-cells = <1>;
+                clock-names = "bi_tcxo",
+                              "sleep_clk";
+                clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+                         <&sleep_clk>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt b/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt
index 3c007653da31..365bbde599b1 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmh-clk.txt
@@ -6,9 +6,14 @@ some Qualcomm Technologies Inc. SoCs. It accepts clock requests from
 other hardware subsystems via RSC to control clocks.
 
 Required properties :
-- compatible : shall contain "qcom,sdm845-rpmh-clk"
+- compatible : must be one of:
+               "qcom,sdm845-rpmh-clk"
+               "qcom,sm8150-rpmh-clk"
 
 - #clock-cells : must contain 1
+- clocks: a list of phandles and clock-specifier pairs,
+          one for each entry in clock-names.
+- clock-names: Parent board clock: "xo".
 
 Example :
 
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0cad76021297..0138fb14e6f8 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_ARCH_EFM32)		+= clk-efm32gg.o
 obj-$(CONFIG_COMMON_CLK_FIXED_MMIO)     += clk-fixed-mmio.o
 obj-$(CONFIG_COMMON_CLK_GEMINI)         += clk-gemini.o
 obj-$(CONFIG_COMMON_CLK_ASPEED)         += clk-aspeed.o
+obj-$(CONFIG_MACH_ASPEED_G6)            += clk-ast2600.o
 obj-$(CONFIG_ARCH_HIGHBANK)             += clk-highbank.o
 obj-$(CONFIG_CLK_HSDK)                  += clk-hsdk-pll.o
 obj-$(CONFIG_COMMON_CLK_LOCHNAGAR)      += clk-lochnagar.o
diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
index 42b4df6ba249..abf06fb6453e 100644
--- a/drivers/clk/clk-aspeed.c
+++ b/drivers/clk/clk-aspeed.c
@@ -1,19 +1,19 @@
 // SPDX-License-Identifier: GPL-2.0+
+// Copyright IBM Corp
 
 #define pr_fmt(fmt) "clk-aspeed: " fmt
 
-#include <linux/clk-provider.h>
 #include <linux/mfd/syscon.h>
 #include <linux/of_address.h>
 #include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
-#include <linux/reset-controller.h>
 #include <linux/slab.h>
-#include <linux/spinlock.h>
 
 #include <dt-bindings/clock/aspeed-clock.h>
 
+#include "clk-aspeed.h"
+
 #define ASPEED_NUM_CLKS         36
 
 #define ASPEED_RESET2_OFFSET    32
@@ -42,48 +42,6 @@ static struct clk_hw_onecell_data *aspeed_clk_data;
 
 static void __iomem *scu_base;
 
-/**
- * struct aspeed_gate_data - Aspeed gated clocks
- * @clock_idx: bit used to gate this clock in the clock register
- * @reset_idx: bit used to reset this IP in the reset register. -1 if no
- *             reset is required when enabling the clock
- * @name: the clock name
- * @parent_name: the name of the parent clock
- * @flags: standard clock framework flags
- */
-struct aspeed_gate_data {
-        u8              clock_idx;
-        s8              reset_idx;
-        const char      *name;
-        const char      *parent_name;
-        unsigned long   flags;
-};
-
-/**
- * struct aspeed_clk_gate - Aspeed specific clk_gate structure
- * @hw:         handle between common and hardware-specific interfaces
- * @reg:        register controlling gate
- * @clock_idx:  bit used to gate this clock in the clock register
- * @reset_idx:  bit used to reset this IP in the reset register. -1 if no
- *              reset is required when enabling the clock
- * @flags:      hardware-specific flags
- * @lock:       register lock
- *
- * Some of the clocks in the Aspeed SoC must be put in reset before enabling.
- * This modified version of clk_gate allows an optional reset bit to be
- * specified.
- */
-struct aspeed_clk_gate {
-        struct clk_hw   hw;
-        struct regmap   *map;
-        u8              clock_idx;
-        s8              reset_idx;
-        u8              flags;
-        spinlock_t      *lock;
-};
-
-#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
-
 /* TODO: ask Aspeed about the actual parent data */
 static const struct aspeed_gate_data aspeed_gates[] = {
         /*                               clk rst   name                 parent  flags */
@@ -208,13 +166,6 @@ static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val)
                         mult, div);
 }
 
-struct aspeed_clk_soc_data {
-        const struct clk_div_table *div_table;
-        const struct clk_div_table *eclk_div_table;
-        const struct clk_div_table *mac_div_table;
-        struct clk_hw *(*calc_pll)(const char *name, u32 val);
-};
-
 static const struct aspeed_clk_soc_data ast2500_data = {
         .div_table = ast2500_div_table,
         .eclk_div_table = ast2500_eclk_div_table,
@@ -315,18 +266,6 @@ static const struct clk_ops aspeed_clk_gate_ops = {
         .is_enabled = aspeed_clk_is_enabled,
 };
 
-/**
- * struct aspeed_reset - Aspeed reset controller
- * @map: regmap to access the containing system controller
- * @rcdev: reset controller device
- */
-struct aspeed_reset {
-        struct regmap                   *map;
-        struct reset_controller_dev     rcdev;
-};
-
-#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
-
 static const u8 aspeed_resets[] = {
         /* SCU04 resets */
         [ASPEED_RESET_XDMA]     = 25,
@@ -500,9 +439,14 @@ static int aspeed_clk_probe(struct platform_device *pdev)
                 return PTR_ERR(hw);
         aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw;
 
-        /* SD/SDIO clock divider (TODO: There's a gate too) */
-        hw = clk_hw_register_divider_table(dev, "sdio", "hpll", 0,
-                        scu_base + ASPEED_CLK_SELECTION, 12, 3, 0,
+        /* SD/SDIO clock divider and gate */
+        hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
+                                  scu_base + ASPEED_CLK_SELECTION, 15, 0,
+                                  &aspeed_clk_lock);
+        if (IS_ERR(hw))
+                return PTR_ERR(hw);
+        hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
+                        0, scu_base + ASPEED_CLK_SELECTION, 12, 3, 0,
                         soc_data->div_table,
                         &aspeed_clk_lock);
         if (IS_ERR(hw))
diff --git a/drivers/clk/clk-aspeed.h b/drivers/clk/clk-aspeed.h
new file mode 100644
index 000000000000..5296b15b1c88
--- /dev/null
+++ b/drivers/clk/clk-aspeed.h
@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Structures used by ASPEED clock drivers
+ *
+ * Copyright 2019 IBM Corp.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+#include <linux/reset-controller.h>
+#include <linux/spinlock.h>
+
+struct clk_div_table;
+struct regmap;
+
+/**
+ * struct aspeed_gate_data - Aspeed gated clocks
+ * @clock_idx: bit used to gate this clock in the clock register
+ * @reset_idx: bit used to reset this IP in the reset register. -1 if no
+ *             reset is required when enabling the clock
+ * @name: the clock name
+ * @parent_name: the name of the parent clock
+ * @flags: standard clock framework flags
+ */
+struct aspeed_gate_data {
+        u8              clock_idx;
+        s8              reset_idx;
+        const char      *name;
+        const char      *parent_name;
+        unsigned long   flags;
+};
+
+/**
+ * struct aspeed_clk_gate - Aspeed specific clk_gate structure
+ * @hw:         handle between common and hardware-specific interfaces
+ * @reg:        register controlling gate
+ * @clock_idx:  bit used to gate this clock in the clock register
+ * @reset_idx:  bit used to reset this IP in the reset register. -1 if no
+ *              reset is required when enabling the clock
+ * @flags:      hardware-specific flags
+ * @lock:       register lock
+ *
+ * Some of the clocks in the Aspeed SoC must be put in reset before enabling.
+ * This modified version of clk_gate allows an optional reset bit to be
+ * specified.
+ */
+struct aspeed_clk_gate {
+        struct clk_hw   hw;
+        struct regmap   *map;
+        u8              clock_idx;
+        s8              reset_idx;
+        u8              flags;
+        spinlock_t      *lock;
+};
+
+#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
+
+/**
+ * struct aspeed_reset - Aspeed reset controller
+ * @map: regmap to access the containing system controller
+ * @rcdev: reset controller device
+ */
+struct aspeed_reset {
+        struct regmap                   *map;
+        struct reset_controller_dev     rcdev;
+};
+
+#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
+
+/**
+ * struct aspeed_clk_soc_data - Aspeed SoC specific divisor information
+ * @div_table: Common divider lookup table
+ * @eclk_div_table: Divider lookup table for ECLK
+ * @mac_div_table: Divider lookup table for MAC (Ethernet) clocks
+ * @calc_pll: Callback to maculate common PLL settings
+ */
+struct aspeed_clk_soc_data {
+        const struct clk_div_table *div_table;
+        const struct clk_div_table *eclk_div_table;
+        const struct clk_div_table *mac_div_table;
+        struct clk_hw *(*calc_pll)(const char *name, u32 val);
+};
diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
new file mode 100644
index 000000000000..1c1bb39bb04e
--- /dev/null
+++ b/drivers/clk/clk-ast2600.c
@@ -0,0 +1,704 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright IBM Corp
+// Copyright ASPEED Technology
+
+#define pr_fmt(fmt) "clk-ast2600: " fmt
+
+#include <linux/mfd/syscon.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/clock/ast2600-clock.h>
+
+#include "clk-aspeed.h"
+
+#define ASPEED_G6_NUM_CLKS              67
+
+#define ASPEED_G6_SILICON_REV           0x004
+
+#define ASPEED_G6_RESET_CTRL            0x040
+#define ASPEED_G6_RESET_CTRL2           0x050
+
+#define ASPEED_G6_CLK_STOP_CTRL         0x080
+#define ASPEED_G6_CLK_STOP_CTRL2        0x090
+
+#define ASPEED_G6_MISC_CTRL             0x0C0
+#define  UART_DIV13_EN                  BIT(12)
+
+#define ASPEED_G6_CLK_SELECTION1        0x300
+#define ASPEED_G6_CLK_SELECTION2        0x304
+#define ASPEED_G6_CLK_SELECTION4        0x310
+
+#define ASPEED_HPLL_PARAM               0x200
+#define ASPEED_APLL_PARAM               0x210
+#define ASPEED_MPLL_PARAM               0x220
+#define ASPEED_EPLL_PARAM               0x240
+#define ASPEED_DPLL_PARAM               0x260
+
+#define ASPEED_G6_STRAP1                0x500
+
+/* Globally visible clocks */
+static DEFINE_SPINLOCK(aspeed_g6_clk_lock);
+
+/* Keeps track of all clocks */
+static struct clk_hw_onecell_data *aspeed_g6_clk_data;
+
+static void __iomem *scu_g6_base;
+
+/*
+ * Clocks marked with CLK_IS_CRITICAL:
+ *
+ *  ref0 and ref1 are essential for the SoC to operate
+ *  mpll is required if SDRAM is used
+ */
+static const struct aspeed_gate_data aspeed_g6_gates[] = {
+        /*                                  clk rst  name               parent   flags */
+        [ASPEED_CLK_GATE_MCLK]          = {  0, -1, "mclk-gate",        "mpll",  CLK_IS_CRITICAL }, /* SDRAM */
+        [ASPEED_CLK_GATE_ECLK]          = {  1, -1, "eclk-gate",        "eclk",  0 },   /* Video Engine */
+        [ASPEED_CLK_GATE_GCLK]          = {  2,  7, "gclk-gate",        NULL,    0 },   /* 2D engine */
+        /* vclk parent - dclk/d1clk/hclk/mclk */
+        [ASPEED_CLK_GATE_VCLK]          = {  3,  6, "vclk-gate",        NULL,    0 },   /* Video Capture */
+        [ASPEED_CLK_GATE_BCLK]          = {  4,  8, "bclk-gate",        "bclk",  0 }, /* PCIe/PCI */
+        /* From dpll */
+        [ASPEED_CLK_GATE_DCLK]          = {  5, -1, "dclk-gate",        NULL,    CLK_IS_CRITICAL }, /* DAC */
+        [ASPEED_CLK_GATE_REF0CLK]       = {  6, -1, "ref0clk-gate",     "clkin", CLK_IS_CRITICAL },
+        [ASPEED_CLK_GATE_USBPORT2CLK]   = {  7,  3, "usb-port2-gate",   NULL,    0 },   /* USB2.0 Host port 2 */
+        /* Reserved 8 */
+        [ASPEED_CLK_GATE_USBUHCICLK]    = {  9, 15, "usb-uhci-gate",    NULL,    0 },   /* USB1.1 (requires port 2 enabled) */
+        /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */
+        [ASPEED_CLK_GATE_D1CLK]         = { 10, 13, "d1clk-gate",       "d1clk", 0 },   /* GFX CRT */
+        /* Reserved 11/12 */
+        [ASPEED_CLK_GATE_YCLK]          = { 13,  4, "yclk-gate",        NULL,    0 },   /* HAC */
+        [ASPEED_CLK_GATE_USBPORT1CLK]   = { 14, 14, "usb-port1-gate",   NULL,    0 },   /* USB2 hub/USB2 host port 1/USB1.1 dev */
+        [ASPEED_CLK_GATE_UART5CLK]      = { 15, -1, "uart5clk-gate",    "uart",  0 },   /* UART5 */
+        /* Reserved 16/19 */
+        [ASPEED_CLK_GATE_MAC1CLK]       = { 20, 11, "mac1clk-gate",     "mac12", 0 },   /* MAC1 */
+        [ASPEED_CLK_GATE_MAC2CLK]       = { 21, 12, "mac2clk-gate",     "mac12", 0 },   /* MAC2 */
+        /* Reserved 22/23 */
+        [ASPEED_CLK_GATE_RSACLK]        = { 24,  4, "rsaclk-gate",      NULL,    0 },   /* HAC */
+        [ASPEED_CLK_GATE_RVASCLK]       = { 25,  9, "rvasclk-gate",     NULL,    0 },   /* RVAS */
+        /* Reserved 26 */
+        [ASPEED_CLK_GATE_EMMCCLK]       = { 27, 16, "emmcclk-gate",     NULL,    0 },   /* For card clk */
+        /* Reserved 28/29/30 */
+        [ASPEED_CLK_GATE_LCLK]          = { 32, 32, "lclk-gate",        NULL,    0 }, /* LPC */
+        [ASPEED_CLK_GATE_ESPICLK]       = { 33, -1, "espiclk-gate",     NULL,    0 }, /* eSPI */
+        [ASPEED_CLK_GATE_REF1CLK]       = { 34, -1, "ref1clk-gate",     "clkin", CLK_IS_CRITICAL },
+        /* Reserved 35 */
+        [ASPEED_CLK_GATE_SDCLK]         = { 36, 56, "sdclk-gate",       NULL,    0 },   /* SDIO/SD */
+        [ASPEED_CLK_GATE_LHCCLK]        = { 37, -1, "lhclk-gate",       "lhclk", 0 },   /* LPC master/LPC+ */
+        /* Reserved 38 RSA: no longer used */
+        /* Reserved 39 */
+        [ASPEED_CLK_GATE_I3C0CLK]       = { 40,  40, "i3c0clk-gate",    NULL,    0 },   /* I3C0 */
+        [ASPEED_CLK_GATE_I3C1CLK]       = { 41,  41, "i3c1clk-gate",    NULL,    0 },   /* I3C1 */
+        [ASPEED_CLK_GATE_I3C2CLK]       = { 42,  42, "i3c2clk-gate",    NULL,    0 },   /* I3C2 */
+        [ASPEED_CLK_GATE_I3C3CLK]       = { 43,  43, "i3c3clk-gate",    NULL,    0 },   /* I3C3 */
+        [ASPEED_CLK_GATE_I3C4CLK]       = { 44,  44, "i3c4clk-gate",    NULL,    0 },   /* I3C4 */
+        [ASPEED_CLK_GATE_I3C5CLK]       = { 45,  45, "i3c5clk-gate",    NULL,    0 },   /* I3C5 */
+        [ASPEED_CLK_GATE_I3C6CLK]       = { 46,  46, "i3c6clk-gate",    NULL,    0 },   /* I3C6 */
+        [ASPEED_CLK_GATE_I3C7CLK]       = { 47,  47, "i3c7clk-gate",    NULL,    0 },   /* I3C7 */
+        [ASPEED_CLK_GATE_UART1CLK]      = { 48,  -1, "uart1clk-gate",   "uart",  0 },   /* UART1 */
+        [ASPEED_CLK_GATE_UART2CLK]      = { 49,  -1, "uart2clk-gate",   "uart",  0 },   /* UART2 */
+        [ASPEED_CLK_GATE_UART3CLK]      = { 50,  -1, "uart3clk-gate",   "uart",  0 },   /* UART3 */
+        [ASPEED_CLK_GATE_UART4CLK]      = { 51,  -1, "uart4clk-gate",   "uart",  0 },   /* UART4 */
+        [ASPEED_CLK_GATE_MAC3CLK]       = { 52,  52, "mac3clk-gate",    "mac34", 0 },   /* MAC3 */
+        [ASPEED_CLK_GATE_MAC4CLK]       = { 53,  53, "mac4clk-gate",    "mac34", 0 },   /* MAC4 */
+        [ASPEED_CLK_GATE_UART6CLK]      = { 54,  -1, "uart6clk-gate",   "uartx", 0 },   /* UART6 */
+        [ASPEED_CLK_GATE_UART7CLK]      = { 55,  -1, "uart7clk-gate",   "uartx", 0 },   /* UART7 */
+        [ASPEED_CLK_GATE_UART8CLK]      = { 56,  -1, "uart8clk-gate",   "uartx", 0 },   /* UART8 */
+        [ASPEED_CLK_GATE_UART9CLK]      = { 57,  -1, "uart9clk-gate",   "uartx", 0 },   /* UART9 */
+        [ASPEED_CLK_GATE_UART10CLK]     = { 58,  -1, "uart10clk-gate",  "uartx", 0 },   /* UART10 */
+        [ASPEED_CLK_GATE_UART11CLK]     = { 59,  -1, "uart11clk-gate",  "uartx", 0 },   /* UART11 */
+        [ASPEED_CLK_GATE_UART12CLK]     = { 60,  -1, "uart12clk-gate",  "uartx", 0 },   /* UART12 */
+        [ASPEED_CLK_GATE_UART13CLK]     = { 61,  -1, "uart13clk-gate",  "uartx", 0 },   /* UART13 */
+        [ASPEED_CLK_GATE_FSICLK]        = { 62,  59, "fsiclk-gate",     NULL,    0 },   /* FSI */
+};
+
+static const char * const eclk_parent_names[] = { "mpll", "hpll", "dpll" };
+
+static const struct clk_div_table ast2600_eclk_div_table[] = {
+        { 0x0, 2 },
+        { 0x1, 2 },
+        { 0x2, 3 },
+        { 0x3, 4 },
+        { 0x4, 5 },
+        { 0x5, 6 },
+        { 0x6, 7 },
+        { 0x7, 8 },
+        { 0 }
+};
+
+static const struct clk_div_table ast2600_mac_div_table[] = {
+        { 0x0, 4 },
+        { 0x1, 4 },
+        { 0x2, 6 },
+        { 0x3, 8 },
+        { 0x4, 10 },
+        { 0x5, 12 },
+        { 0x6, 14 },
+        { 0x7, 16 },
+        { 0 }
+};
+
+static const struct clk_div_table ast2600_div_table[] = {
+        { 0x0, 4 },
+        { 0x1, 8 },
+        { 0x2, 12 },
+        { 0x3, 16 },
+        { 0x4, 20 },
+        { 0x5, 24 },
+        { 0x6, 28 },
+        { 0x7, 32 },
+        { 0 }
+};
+
+/* For hpll/dpll/epll/mpll */
+static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
+{
+        unsigned int mult, div;
+
+        if (val & BIT(24)) {
+                /* Pass through mode */
+                mult = div = 1;
+        } else {
+                /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
+                u32 m = val  & 0x1fff;
+                u32 n = (val >> 13) & 0x3f;
+                u32 p = (val >> 19) & 0xf;
+                mult = (m + 1) / (n + 1);
+                div = (p + 1);
+        }
+        return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
+                        mult, div);
+};
+
+static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)
+{
+        unsigned int mult, div;
+
+        if (val & BIT(20)) {
+                /* Pass through mode */
+                mult = div = 1;
+        } else {
+                /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
+                u32 m = (val >> 5) & 0x3f;
+                u32 od = (val >> 4) & 0x1;
+                u32 n = val & 0xf;
+
+                mult = (2 - od) * (m + 2);
+                div = n + 1;
+        }
+        return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
+                        mult, div);
+};
+
+static u32 get_bit(u8 idx)
+{
+        return BIT(idx % 32);
+}
+
+static u32 get_reset_reg(struct aspeed_clk_gate *gate)
+{
+        if (gate->reset_idx < 32)
+                return ASPEED_G6_RESET_CTRL;
+
+        return ASPEED_G6_RESET_CTRL2;
+}
+
+static u32 get_clock_reg(struct aspeed_clk_gate *gate)
+{
+        if (gate->clock_idx < 32)
+                return ASPEED_G6_CLK_STOP_CTRL;
+
+        return ASPEED_G6_CLK_STOP_CTRL2;
+}
+
+static int aspeed_g6_clk_is_enabled(struct clk_hw *hw)
+{
+        struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
+        u32 clk = get_bit(gate->clock_idx);
+        u32 rst = get_bit(gate->reset_idx);
+        u32 reg;
+        u32 enval;
+
+        /*
+         * If the IP is in reset, treat the clock as not enabled,
+         * this happens with some clocks such as the USB one when
+         * coming from cold reset. Without this, aspeed_clk_enable()
+         * will fail to lift the reset.
+         */
+        if (gate->reset_idx >= 0) {
+                regmap_read(gate->map, get_reset_reg(gate), &reg);
+
+                if (reg & rst)
+                        return 0;
+        }
+
+        regmap_read(gate->map, get_clock_reg(gate), &reg);
+
+        enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
+
+        return ((reg & clk) == enval) ? 1 : 0;
+}
+
+static int aspeed_g6_clk_enable(struct clk_hw *hw)
+{
+        struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
+        unsigned long flags;
+        u32 clk = get_bit(gate->clock_idx);
+        u32 rst = get_bit(gate->reset_idx);
+
+        spin_lock_irqsave(gate->lock, flags);
+
+        if (aspeed_g6_clk_is_enabled(hw)) {
+                spin_unlock_irqrestore(gate->lock, flags);
+                return 0;
+        }
+
+        if (gate->reset_idx >= 0) {
+                /* Put IP in reset */
+                regmap_write(gate->map, get_reset_reg(gate), rst);
+                /* Delay 100us */
+                udelay(100);
+        }
+
+        /* Enable clock */
+        if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
+                regmap_write(gate->map, get_clock_reg(gate), clk);
+        } else {
+                /* Use set to clear register */
+                regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk);
+        }
+
+        if (gate->reset_idx >= 0) {
+                /* A delay of 10ms is specified by the ASPEED docs */
+                mdelay(10);
+                /* Take IP out of reset */
+                regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst);
+        }
+
+        spin_unlock_irqrestore(gate->lock, flags);
+
+        return 0;
+}
+
+static void aspeed_g6_clk_disable(struct clk_hw *hw)
+{
+        struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
+        unsigned long flags;
+        u32 clk = get_bit(gate->clock_idx);
+
+        spin_lock_irqsave(gate->lock, flags);
+
+        if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
+                regmap_write(gate->map, get_clock_reg(gate), clk);
+        } else {
+                /* Use set to clear register */
+                regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk);
+        }
+
+        spin_unlock_irqrestore(gate->lock, flags);
+}
+
+static const struct clk_ops aspeed_g6_clk_gate_ops = {
+        .enable = aspeed_g6_clk_enable,
+        .disable = aspeed_g6_clk_disable,
+        .is_enabled = aspeed_g6_clk_is_enabled,
+};
+
+static int aspeed_g6_reset_deassert(struct reset_controller_dev *rcdev,
+                                    unsigned long id)
+{
+        struct aspeed_reset *ar = to_aspeed_reset(rcdev);
+        u32 rst = get_bit(id);
+        u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
+
+        /* Use set to clear register */
+        return regmap_write(ar->map, reg + 0x04, rst);
+}
+
+static int aspeed_g6_reset_assert(struct reset_controller_dev *rcdev,
+                                  unsigned long id)
+{
+        struct aspeed_reset *ar = to_aspeed_reset(rcdev);
+        u32 rst = get_bit(id);
+        u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
+
+        return regmap_write(ar->map, reg, rst);
+}
+
+static int aspeed_g6_reset_status(struct reset_controller_dev *rcdev,
+                                  unsigned long id)
+{
+        struct aspeed_reset *ar = to_aspeed_reset(rcdev);
+        int ret;
+        u32 val;
+        u32 rst = get_bit(id);
+        u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
+
+        ret = regmap_read(ar->map, reg, &val);
+        if (ret)
+                return ret;
+
+        return !!(val & rst);
+}
+
+static const struct reset_control_ops aspeed_g6_reset_ops = {
+        .assert = aspeed_g6_reset_assert,
+        .deassert = aspeed_g6_reset_deassert,
+        .status = aspeed_g6_reset_status,
+};
+
+static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev,
+                const char *name, const char *parent_name, unsigned long flags,
+                struct regmap *map, u8 clock_idx, u8 reset_idx,
+                u8 clk_gate_flags, spinlock_t *lock)
+{
+        struct aspeed_clk_gate *gate;
+        struct clk_init_data init;
+        struct clk_hw *hw;
+        int ret;
+
+        gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+        if (!gate)
+                return ERR_PTR(-ENOMEM);
+
+        init.name = name;
+        init.ops = &aspeed_g6_clk_gate_ops;
+        init.flags = flags;
+        init.parent_names = parent_name ? &parent_name : NULL;
+        init.num_parents = parent_name ? 1 : 0;
+
+        gate->map = map;
+        gate->clock_idx = clock_idx;
+        gate->reset_idx = reset_idx;
+        gate->flags = clk_gate_flags;
+        gate->lock = lock;
+        gate->hw.init = &init;
+
+        hw = &gate->hw;
+        ret = clk_hw_register(dev, hw);
+        if (ret) {
+                kfree(gate);
+                hw = ERR_PTR(ret);
+        }
+
+        return hw;
+}
+
+static const char * const vclk_parent_names[] = {
+        "dpll",
+        "d1pll",
+        "hclk",
+        "mclk",
+};
+
+static const char * const d1clk_parent_names[] = {
+        "dpll",
+        "epll",
+        "usb-phy-40m",
+        "gpioc6_clkin",
+        "dp_phy_pll",
+};
+
+static int aspeed_g6_clk_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct aspeed_reset *ar;
+        struct regmap *map;
+        struct clk_hw *hw;
+        u32 val, rate;
+        int i, ret;
+
+        map = syscon_node_to_regmap(dev->of_node);
+        if (IS_ERR(map)) {
+                dev_err(dev, "no syscon regmap\n");
+                return PTR_ERR(map);
+        }
+
+        ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
+        if (!ar)
+                return -ENOMEM;
+
+        ar->map = map;
+
+        ar->rcdev.owner = THIS_MODULE;
+        ar->rcdev.nr_resets = 64;
+        ar->rcdev.ops = &aspeed_g6_reset_ops;
+        ar->rcdev.of_node = dev->of_node;
+
+        ret = devm_reset_controller_register(dev, &ar->rcdev);
+        if (ret) {
+                dev_err(dev, "could not register reset controller\n");
+                return ret;
+        }
+
+        /* UART clock div13 setting */
+        regmap_read(map, ASPEED_G6_MISC_CTRL, &val);
+        if (val & UART_DIV13_EN)
+                rate = 24000000 / 13;
+        else
+                rate = 24000000;
+        hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
+        if (IS_ERR(hw))
+                return PTR_ERR(hw);
+        aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw;
+
+        /* UART6~13 clock div13 setting */
+        regmap_read(map, 0x80, &val);
+        if (val & BIT(31))
+                rate = 24000000 / 13;
+        else
+                rate = 24000000;
+        hw = clk_hw_register_fixed_rate(dev, "uartx", NULL, 0, rate);
+        if (IS_ERR(hw))
+                return PTR_ERR(hw);
+        aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw;
+
+        /* EMMC ext clock divider */
+        hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "hpll", 0,
+                        scu_g6_base + ASPEED_G6_CLK_SELECTION1, 15, 0,
+                        &aspeed_g6_clk_lock);
+        if (IS_ERR(hw))
+                return PTR_ERR(hw);
+        hw = clk_hw_register_divider_table(dev, "emmc_extclk", "emmc_extclk_gate", 0,
+                        scu_g6_base + ASPEED_G6_CLK_SELECTION1, 12, 3, 0,
+                        ast2600_div_table,
+                        &aspeed_g6_clk_lock);
+        if (IS_ERR(hw))
+                return PTR_ERR(hw);
+        aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw;
+
+        /* SD/SDIO clock divider and gate */
+        hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
+                        scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0,
+                        &aspeed_g6_clk_lock);
+        if (IS_ERR(hw))
+                return PTR_ERR(hw);
+        hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
+                        0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0,
+                        ast2600_div_table,
+                        &aspeed_g6_clk_lock);
+        if (IS_ERR(hw))
+                return PTR_ERR(hw);
+        aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw;
+
+        /* MAC1/2 AHB bus clock divider */
+        hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0,
+                        scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0,
+                        ast2600_mac_div_table,
+                        &aspeed_g6_clk_lock);
+        if (IS_ERR(hw))
+                return PTR_ERR(hw);
+        aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw;
+
+        /* MAC3/4 AHB bus clock divider */
+        hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0,
+                        scu_g6_base + 0x310, 24, 3, 0,
+                        ast2600_mac_div_table,
+                        &aspeed_g6_clk_lock);
+        if (IS_ERR(hw))
+                return PTR_ERR(hw);
+        aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw;
+
+        /* LPC Host (LHCLK) clock divider */
+        hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
+                        scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
+                        ast2600_div_table,
+                        &aspeed_g6_clk_lock);
+        if (IS_ERR(hw))
+                return PTR_ERR(hw);
+        aspeed_g6_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
+
+        /* gfx d1clk : use dp clk */
+        regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10));
+        /* SoC Display clock selection */
+        hw = clk_hw_register_mux(dev, "d1clk", d1clk_parent_names,
+                        ARRAY_SIZE(d1clk_parent_names), 0,
+                        scu_g6_base + ASPEED_G6_CLK_SELECTION1, 8, 3, 0,
+                        &aspeed_g6_clk_lock);
+        if (IS_ERR(hw))
+                return PTR_ERR(hw);
+        aspeed_g6_clk_data->hws[ASPEED_CLK_D1CLK] = hw;
+
+        /* d1 clk div 0x308[17:15] x [14:12] - 8,7,6,5,4,3,2,1 */
+        regmap_write(map, 0x308, 0x12000); /* 3x3 = 9 */
+
+        /* P-Bus (BCLK) clock divider */
+        hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
+                        scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
+                        ast2600_div_table,
+                        &aspeed_g6_clk_lock);
+        if (IS_ERR(hw))
+                return PTR_ERR(hw);
+        aspeed_g6_clk_data->hws[ASPEED_CLK_BCLK] = hw;
+
+        /* Video Capture clock selection */
+        hw = clk_hw_register_mux(dev, "vclk", vclk_parent_names,
+                        ARRAY_SIZE(vclk_parent_names), 0,
+                        scu_g6_base + ASPEED_G6_CLK_SELECTION2, 12, 3, 0,
+                        &aspeed_g6_clk_lock);
+        if (IS_ERR(hw))
+                return PTR_ERR(hw);
+        aspeed_g6_clk_data->hws[ASPEED_CLK_VCLK] = hw;
+
+        /* Video Engine clock divider */
+        hw = clk_hw_register_divider_table(dev, "eclk", NULL, 0,
+                        scu_g6_base + ASPEED_G6_CLK_SELECTION1, 28, 3, 0,
+                        ast2600_eclk_div_table,
+                        &aspeed_g6_clk_lock);
+        if (IS_ERR(hw))
+                return PTR_ERR(hw);
+        aspeed_g6_clk_data->hws[ASPEED_CLK_ECLK] = hw;
+
+        for (i = 0; i < ARRAY_SIZE(aspeed_g6_gates); i++) {
+                const struct aspeed_gate_data *gd = &aspeed_g6_gates[i];
+                u32 gate_flags;
+
+                /*
+                 * Special case: the USB port 1 clock (bit 14) is always
+                 * working the opposite way from the other ones.
+                 */
+                gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
+                hw = aspeed_g6_clk_hw_register_gate(dev,
+                                gd->name,
+                                gd->parent_name,
+                                gd->flags,
+                                map,
+                                gd->clock_idx,
+                                gd->reset_idx,
+                                gate_flags,
+                                &aspeed_g6_clk_lock);
+                if (IS_ERR(hw))
+                        return PTR_ERR(hw);
+                aspeed_g6_clk_data->hws[i] = hw;
+        }
+
+        return 0;
+};
+
+static const struct of_device_id aspeed_g6_clk_dt_ids[] = {
+        { .compatible = "aspeed,ast2600-scu" },
+        { }
+};
+
+static struct platform_driver aspeed_g6_clk_driver = {
+        .probe  = aspeed_g6_clk_probe,
+        .driver = {
+                .name = "ast2600-clk",
+                .of_match_table = aspeed_g6_clk_dt_ids,
+                .suppress_bind_attrs = true,
+        },
+};
+builtin_platform_driver(aspeed_g6_clk_driver);
+
+static const u32 ast2600_a0_axi_ahb_div_table[] = {
+        2, 2, 3, 5,
+};
+
+static const u32 ast2600_a1_axi_ahb_div_table[] = {
+        4, 6, 2, 4,
+};
+
+static void __init aspeed_g6_cc(struct regmap *map)
+{
+        struct clk_hw *hw;
+        u32 val, div, chip_id, axi_div, ahb_div;
+
+        clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
+
+        /*
+         * High-speed PLL clock derived from the crystal. This the CPU clock,
+         * and we assume that it is enabled
+         */
+        regmap_read(map, ASPEED_HPLL_PARAM, &val);
+        aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val);
+
+        regmap_read(map, ASPEED_MPLL_PARAM, &val);
+        aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val);
+
+        regmap_read(map, ASPEED_DPLL_PARAM, &val);
+        aspeed_g6_clk_data->hws[ASPEED_CLK_DPLL] = ast2600_calc_pll("dpll", val);
+
+        regmap_read(map, ASPEED_EPLL_PARAM, &val);
+        aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val);
+
+        regmap_read(map, ASPEED_APLL_PARAM, &val);
+        aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val);
+
+        /* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/
+        regmap_read(map, ASPEED_G6_STRAP1, &val);
+        if (val & BIT(16))
+                axi_div = 1;
+        else
+                axi_div = 2;
+
+        regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);
+        if (chip_id & BIT(16))
+                ahb_div = ast2600_a1_axi_ahb_div_table[(val >> 11) & 0x3];
+        else
+                ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3];
+
+        hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div);
+        aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw;
+
+        regmap_read(map, ASPEED_G6_CLK_SELECTION1, &val);
+        val = (val >> 23) & 0x7;
+        div = 4 * (val + 1);
+        hw = clk_hw_register_fixed_factor(NULL, "apb1", "hpll", 0, 1, div);
+        aspeed_g6_clk_data->hws[ASPEED_CLK_APB1] = hw;
+
+        regmap_read(map, ASPEED_G6_CLK_SELECTION4, &val);
+        val = (val >> 9) & 0x7;
+        div = 2 * (val + 1);
+        hw = clk_hw_register_fixed_factor(NULL, "apb2", "ahb", 0, 1, div);
+        aspeed_g6_clk_data->hws[ASPEED_CLK_APB2] = hw;
+
+        /* USB 2.0 port1 phy 40MHz clock */
+        hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000);
+        aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw;
+};
+
+static void __init aspeed_g6_cc_init(struct device_node *np)
+{
+        struct regmap *map;
+        int ret;
+        int i;
+
+        scu_g6_base = of_iomap(np, 0);
+        if (!scu_g6_base)
+                return;
+
+        aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws,
+                                      ASPEED_G6_NUM_CLKS), GFP_KERNEL);
+        if (!aspeed_g6_clk_data)
+                return;
+
+        /*
+         * This way all clocks fetched before the platform device probes,
+         * except those we assign here for early use, will be deferred.
+         */
+        for (i = 0; i < ASPEED_G6_NUM_CLKS; i++)
+                aspeed_g6_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
+
+        /*
+         * We check that the regmap works on this very first access,
+         * but as this is an MMIO-backed regmap, subsequent regmap
+         * access is not going to fail and we skip error checks from
+         * this point.
+         */
+        map = syscon_node_to_regmap(np);
+        if (IS_ERR(map)) {
+                pr_err("no syscon regmap\n");
+                return;
+        }
+
+        aspeed_g6_cc(map);
+        aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
+        ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);
+        if (ret)
+                pr_err("failed to add DT provider: %d\n", ret);
+};
+CLK_OF_DECLARE_DRIVER(aspeed_cc_g6, "aspeed,ast2600-scu", aspeed_g6_cc_init);
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index b06038b8f658..4f13a681ddfc 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -3,7 +3,6 @@
  * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
  */
 
-#include <linux/clk.h>
 #include <linux/clk-provider.h>
 #include <linux/err.h>
 #include <linux/slab.h>
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 07f3b252f3e0..bed140f7375f 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -686,7 +686,7 @@ static const struct clockgen_chipinfo chipinfo[] = {
                 .guts_compat = "fsl,qoriq-device-config-1.0",
                 .init_periph = p5020_init_periph,
                 .cmux_groups = {
-                        &p2041_cmux_grp1, &p2041_cmux_grp2
+                        &p5020_cmux_grp1, &p5020_cmux_grp2
                 },
                 .cmux_to_group = {
                         0, 1, -1
diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c
index 72424eb7e5f8..6e780c2a9e6b 100644
--- a/drivers/clk/clk-si5341.c
+++ b/drivers/clk/clk-si5341.c
@@ -547,7 +547,6 @@ static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
         bool is_integer;
 
         n_num = synth->data->freq_vco;
-        n_den = rate;
 
         /* see if there's an integer solution */
         r = do_div(n_num, rate);
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index c0990703ce54..1b291a6e169b 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -593,6 +593,8 @@ static void clk_core_get_boundaries(struct clk_core *core,
 {
         struct clk *clk_user;
 
+        lockdep_assert_held(&prepare_lock);
+
         *min_rate = core->min_rate;
         *max_rate = core->max_rate;
 
@@ -2487,6 +2489,12 @@ runtime_put:
         return ret;
 }
 
+int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *parent)
+{
+        return clk_core_set_parent_nolock(hw->core, parent->core);
+}
+EXPORT_SYMBOL_GPL(clk_hw_set_parent);
+
 /**
  * clk_set_parent - switch the parent of a mux clk
  * @clk: the mux clk whose input we are switching
@@ -2847,9 +2855,6 @@ static struct hlist_head *orphan_list[] = {
 static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
                                  int level)
 {
-        if (!c)
-                return;
-
         seq_printf(s, "%*s%-*s %7d %8d %8d %11lu %10lu %5d %6d\n",
                    level * 3 + 1, "",
                    30 - level * 3, c->name,
@@ -2864,9 +2869,6 @@ static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
 {
         struct clk_core *child;
 
-        if (!c)
-                return;
-
         clk_summary_show_one(s, c, level);
 
         hlist_for_each_entry(child, &c->children, child_node)
@@ -2896,8 +2898,9 @@ DEFINE_SHOW_ATTRIBUTE(clk_summary);
 
 static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
 {
-        if (!c)
-                return;
+        unsigned long min_rate, max_rate;
+
+        clk_core_get_boundaries(c, &min_rate, &max_rate);
 
         /* This should be JSON format, i.e. elements separated with a comma */
         seq_printf(s, "\"%s\": { ", c->name);
@@ -2905,6 +2908,8 @@ static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
         seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
         seq_printf(s, "\"protect_count\": %d,", c->protect_count);
         seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c));
+        seq_printf(s, "\"min_rate\": %lu,", min_rate);
+        seq_printf(s, "\"max_rate\": %lu,", max_rate);
         seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c));
         seq_printf(s, "\"phase\": %d,", clk_core_get_phase(c));
         seq_printf(s, "\"duty_cycle\": %u",
@@ -2915,9 +2920,6 @@ static void clk_dump_subtree(struct seq_file *s, struct clk_core *c, int level)
 {
         struct clk_core *child;
 
-        if (!c)
-                return;
-
         clk_dump_one(s, c, level);
 
         hlist_for_each_entry(child, &c->children, child_node) {
@@ -3013,15 +3015,15 @@ static void possible_parent_show(struct seq_file *s, struct clk_core *core,
          */
         parent = clk_core_get_parent_by_index(core, i);
         if (parent)
-                seq_printf(s, "%s", parent->name);
+                seq_puts(s, parent->name);
         else if (core->parents[i].name)
-                seq_printf(s, "%s", core->parents[i].name);
+                seq_puts(s, core->parents[i].name);
         else if (core->parents[i].fw_name)
                 seq_printf(s, "<%s>(fw)", core->parents[i].fw_name);
         else if (core->parents[i].index >= 0)
-                seq_printf(s, "%s",
-                           of_clk_get_parent_name(core->of_node,
-                                                  core->parents[i].index));
+                seq_puts(s,
+                         of_clk_get_parent_name(core->of_node,
+                                                core->parents[i].index));
         else
                 seq_puts(s, "(missing)");
 
@@ -3064,6 +3066,34 @@ static int clk_duty_cycle_show(struct seq_file *s, void *data)
 }
 DEFINE_SHOW_ATTRIBUTE(clk_duty_cycle);
 
+static int clk_min_rate_show(struct seq_file *s, void *data)
+{
+        struct clk_core *core = s->private;
+        unsigned long min_rate, max_rate;
+
+        clk_prepare_lock();
+        clk_core_get_boundaries(core, &min_rate, &max_rate);
+        clk_prepare_unlock();
+        seq_printf(s, "%lu\n", min_rate);
+
+        return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(clk_min_rate);
+
+static int clk_max_rate_show(struct seq_file *s, void *data)
+{
+        struct clk_core *core = s->private;
+        unsigned long min_rate, max_rate;
+
+        clk_prepare_lock();
+        clk_core_get_boundaries(core, &min_rate, &max_rate);
+        clk_prepare_unlock();
+        seq_printf(s, "%lu\n", max_rate);
+
+        return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(clk_max_rate);
+
 static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
 {
         struct dentry *root;
@@ -3075,6 +3105,8 @@ static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
         core->dentry = root;
 
         debugfs_create_ulong("clk_rate", 0444, root, &core->rate);
+        debugfs_create_file("clk_min_rate", 0444, root, core, &clk_min_rate_fops);
+        debugfs_create_file("clk_max_rate", 0444, root, core, &clk_max_rate_fops);
         debugfs_create_ulong("clk_accuracy", 0444, root, &core->accuracy);
         debugfs_create_u32("clk_phase", 0444, root, &core->phase);
         debugfs_create_file("clk_flags", 0444, root, core, &clk_flags_fops);
diff --git a/drivers/clk/davinci/pll.c b/drivers/clk/davinci/pll.c
index 1c99e992d638..1ac11b6a47a3 100644
--- a/drivers/clk/davinci/pll.c
+++ b/drivers/clk/davinci/pll.c
@@ -778,12 +778,15 @@ int of_davinci_pll_init(struct device *dev, struct device_node *node,
                 int i;
 
                 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
-                if (!clk_data)
+                if (!clk_data) {
+                        of_node_put(child);
                         return -ENOMEM;
+                }
 
                 clks = kmalloc_array(n_clks, sizeof(*clks), GFP_KERNEL);
                 if (!clks) {
                         kfree(clk_data);
+                        of_node_put(child);
                         return -ENOMEM;
                 }
 
diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c
index 2642d36d1e2c..a3b4635f6278 100644
--- a/drivers/clk/ingenic/jz4725b-cgu.c
+++ b/drivers/clk/ingenic/jz4725b-cgu.c
@@ -257,4 +257,4 @@ static void __init jz4725b_cgu_init(struct device_node *np)
 
         ingenic_cgu_register_syscore_ops(cgu);
 }
-CLK_OF_DECLARE(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init);
+CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init);
diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index 4c0a20949c2c..978f32dd424a 100644
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -53,6 +53,10 @@ static const u8 jz4740_cgu_cpccr_div_table[] = {
         1, 2, 3, 4, 6, 8, 12, 16, 24, 32,
 };
 
+static const u8 jz4740_cgu_pll_half_div_table[] = {
+        2, 1,
+};
+
 static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
 
         /* External clocks */
@@ -86,7 +90,10 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
         [JZ4740_CLK_PLL_HALF] = {
                 "pll half", CGU_CLK_DIV,
                 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
-                .div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1 },
+                .div = {
+                        CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
+                        jz4740_cgu_pll_half_div_table,
+                },
         },
 
         [JZ4740_CLK_CCLK] = {
@@ -241,4 +248,4 @@ static void __init jz4740_cgu_init(struct device_node *np)
 
         ingenic_cgu_register_syscore_ops(cgu);
 }
-CLK_OF_DECLARE(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);
+CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);
diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c
index eebc1bea3841..956dd653a43d 100644
--- a/drivers/clk/ingenic/jz4770-cgu.c
+++ b/drivers/clk/ingenic/jz4770-cgu.c
@@ -443,4 +443,4 @@ static void __init jz4770_cgu_init(struct device_node *np)
 }
 
 /* We only probe via devicetree, no need for a platform driver */
-CLK_OF_DECLARE(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init);
+CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-cgu", jz4770_cgu_init);
diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c
index 8c67f89df25e..ea905ff72bf0 100644
--- a/drivers/clk/ingenic/jz4780-cgu.c
+++ b/drivers/clk/ingenic/jz4780-cgu.c
@@ -725,4 +725,4 @@ static void __init jz4780_cgu_init(struct device_node *np)
 
         ingenic_cgu_register_syscore_ops(cgu);
 }
-CLK_OF_DECLARE(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init);
+CLK_OF_DECLARE_DRIVER(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init);
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index a6b20e123e0c..dabeb435d067 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -1,7 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0-only
-config COMMON_CLK_MESON_INPUT
-        tristate
-
 config COMMON_CLK_MESON_REGMAP
         tristate
         select REGMAP
@@ -33,13 +30,15 @@ config COMMON_CLK_MESON_VID_PLL_DIV
 config COMMON_CLK_MESON_AO_CLKC
         tristate
         select COMMON_CLK_MESON_REGMAP
-        select COMMON_CLK_MESON_INPUT
         select RESET_CONTROLLER
 
 config COMMON_CLK_MESON_EE_CLKC
         tristate
         select COMMON_CLK_MESON_REGMAP
-        select COMMON_CLK_MESON_INPUT
+
+config COMMON_CLK_MESON_CPU_DYNDIV
+        tristate
+        select COMMON_CLK_MESON_REGMAP
 
 config COMMON_CLK_MESON8B
         bool
@@ -86,7 +85,6 @@ config COMMON_CLK_AXG
 config COMMON_CLK_AXG_AUDIO
         tristate "Meson AXG Audio Clock Controller Driver"
         depends on ARCH_MESON
-        select COMMON_CLK_MESON_INPUT
         select COMMON_CLK_MESON_REGMAP
         select COMMON_CLK_MESON_PHASE
         select COMMON_CLK_MESON_SCLK_DIV
@@ -104,6 +102,7 @@ config COMMON_CLK_G12A
         select COMMON_CLK_MESON_PLL
         select COMMON_CLK_MESON_AO_CLKC
         select COMMON_CLK_MESON_EE_CLKC
+        select COMMON_CLK_MESON_CPU_DYNDIV
         select MFD_SYSCON
         help
           Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index bc35a4efd6b7..3939f218587a 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -2,9 +2,9 @@
 # Amlogic clock drivers
 
 obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) += meson-aoclk.o
+obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) += clk-cpu-dyndiv.o
 obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) += clk-dualdiv.o
 obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) += meson-eeclk.o
-obj-$(CONFIG_COMMON_CLK_MESON_INPUT) += clk-input.o
 obj-$(CONFIG_COMMON_CLK_MESON_MPLL) += clk-mpll.o
 obj-$(CONFIG_COMMON_CLK_MESON_PHASE) += clk-phase.o
 obj-$(CONFIG_COMMON_CLK_MESON_PLL) += clk-pll.o
diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c
index 0086f31288eb..b488b40c9d0e 100644
--- a/drivers/clk/meson/axg-aoclk.c
+++ b/drivers/clk/meson/axg-aoclk.c
@@ -18,8 +18,6 @@
 #include "clk-regmap.h"
 #include "clk-dualdiv.h"
 
-#define IN_PREFIX "ao-in-"
-
 /*
  * AO Configuration Clock registers offsets
  * Register offsets from the data sheet must be multiplied by 4.
@@ -42,7 +40,9 @@ static struct clk_regmap axg_aoclk_##_name = {				\
         .hw.init = &(struct clk_init_data) {                            \
                 .name =  "axg_ao_" #_name,                              \
                 .ops = &clk_regmap_gate_ops,                            \
-                .parent_names = (const char *[]){ IN_PREFIX "mpeg-clk" }, \
+                .parent_data = &(const struct clk_parent_data) {        \
+                        .fw_name = "mpeg-clk",                          \
+                },                                                      \
                 .num_parents = 1,                                       \
                 .flags = CLK_IGNORE_UNUSED,                             \
         },                                                              \
@@ -64,7 +64,9 @@ static struct clk_regmap axg_aoclk_cts_oscin = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_oscin",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
         },
 };
@@ -77,7 +79,9 @@ static struct clk_regmap axg_aoclk_32k_pre = {
         .hw.init = &(struct clk_init_data){
                 .name = "axg_ao_32k_pre",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "cts_oscin" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_aoclk_cts_oscin.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -124,7 +128,9 @@ static struct clk_regmap axg_aoclk_32k_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "axg_ao_32k_div",
                 .ops = &meson_clk_dualdiv_ops,
-                .parent_names = (const char *[]){ "axg_ao_32k_pre" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_aoclk_32k_pre.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -139,8 +145,10 @@ static struct clk_regmap axg_aoclk_32k_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "axg_ao_32k_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "axg_ao_32k_div",
-                                                  "axg_ao_32k_pre" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_aoclk_32k_div.hw,
+                        &axg_aoclk_32k_pre.hw,
+                },
                 .num_parents = 2,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -154,7 +162,9 @@ static struct clk_regmap axg_aoclk_32k = {
         .hw.init = &(struct clk_init_data){
                 .name = "axg_ao_32k",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "axg_ao_32k_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_aoclk_32k_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -170,8 +180,10 @@ static struct clk_regmap axg_aoclk_cts_rtc_oscin = {
         .hw.init = &(struct clk_init_data){
                 .name = "axg_ao_cts_rtc_oscin",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "axg_ao_32k",
-                                                  IN_PREFIX "ext_32k-0" },
+                .parent_data = (const struct clk_parent_data []) {
+                        { .hw = &axg_aoclk_32k.hw },
+                        { .fw_name = "ext_32k-0", },
+                },
                 .num_parents = 2,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -187,8 +199,10 @@ static struct clk_regmap axg_aoclk_clk81 = {
         .hw.init = &(struct clk_init_data){
                 .name = "axg_ao_clk81",
                 .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "mpeg-clk",
-                                                  "axg_ao_cts_rtc_oscin"},
+                .parent_data = (const struct clk_parent_data []) {
+                        { .fw_name = "mpeg-clk", },
+                        { .hw = &axg_aoclk_cts_rtc_oscin.hw },
+                },
                 .num_parents = 2,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -203,8 +217,10 @@ static struct clk_regmap axg_aoclk_saradc_mux = {
         .hw.init = &(struct clk_init_data){
                 .name = "axg_ao_saradc_mux",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal",
-                                                  "axg_ao_clk81" },
+                .parent_data = (const struct clk_parent_data []) {
+                        { .fw_name = "xtal", },
+                        { .hw = &axg_aoclk_clk81.hw },
+                },
                 .num_parents = 2,
         },
 };
@@ -218,7 +234,9 @@ static struct clk_regmap axg_aoclk_saradc_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "axg_ao_saradc_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "axg_ao_saradc_mux" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_aoclk_saradc_mux.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -232,7 +250,9 @@ static struct clk_regmap axg_aoclk_saradc_gate = {
         .hw.init = &(struct clk_init_data){
                 .name = "axg_ao_saradc_gate",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "axg_ao_saradc_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_aoclk_saradc_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -290,12 +310,6 @@ static const struct clk_hw_onecell_data axg_aoclk_onecell_data = {
         .num = NR_CLKS,
 };
 
-static const struct meson_aoclk_input axg_aoclk_inputs[] = {
-        { .name = "xtal",       .required = true  },
-        { .name = "mpeg-clk",   .required = true  },
-        { .name = "ext-32k-0",  .required = false },
-};
-
 static const struct meson_aoclk_data axg_aoclkc_data = {
         .reset_reg      = AO_RTI_GEN_CNTL_REG0,
         .num_reset      = ARRAY_SIZE(axg_aoclk_reset),
@@ -303,9 +317,6 @@ static const struct meson_aoclk_data axg_aoclkc_data = {
         .num_clks       = ARRAY_SIZE(axg_aoclk_regmap),
         .clks           = axg_aoclk_regmap,
         .hw_data        = &axg_aoclk_onecell_data,
-        .inputs         = axg_aoclk_inputs,
-        .num_inputs     = ARRAY_SIZE(axg_aoclk_inputs),
-        .input_prefix   = IN_PREFIX,
 };
 
 static const struct of_device_id axg_aoclkc_match_table[] = {
diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index 8028ff6f6610..6be9df1efce5 100644
--- a/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
@@ -12,10 +12,10 @@
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
 #include <linux/reset.h>
+#include <linux/reset-controller.h>
 #include <linux/slab.h>
 
 #include "axg-audio.h"
-#include "clk-input.h"
 #include "clk-regmap.h"
 #include "clk-phase.h"
 #include "sclk-div.h"
@@ -24,7 +24,7 @@
 #define AUD_SLV_SCLK_COUNT      10
 #define AUD_SLV_LRCLK_COUNT     10
 
-#define AUD_GATE(_name, _reg, _bit, _pname, _iflags)                    \
+#define AUD_GATE(_name, _reg, _bit, _phws, _iflags)                     \
 struct clk_regmap aud_##_name = {                                       \
         .data = &(struct clk_regmap_gate_data){                         \
                 .offset = (_reg),                                       \
@@ -33,13 +33,13 @@ struct clk_regmap aud_##_name = {					\
         .hw.init = &(struct clk_init_data) {                            \
                 .name = "aud_"#_name,                                   \
                 .ops = &clk_regmap_gate_ops,                            \
-                .parent_names = (const char *[]){ _pname },             \
+                .parent_hws = (const struct clk_hw *[]) { &_phws.hw },  \
                 .num_parents = 1,                                       \
                 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags),             \
         },                                                              \
 }
 
-#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pnames, _iflags)  \
+#define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags)   \
 struct clk_regmap aud_##_name = {                                       \
         .data = &(struct clk_regmap_mux_data){                          \
                 .offset = (_reg),                                       \
@@ -50,13 +50,13 @@ struct clk_regmap aud_##_name = {					\
         .hw.init = &(struct clk_init_data){                             \
                 .name = "aud_"#_name,                                   \
                 .ops = &clk_regmap_mux_ops,                             \
-                .parent_names = (_pnames),                              \
-                .num_parents = ARRAY_SIZE(_pnames),                     \
+                .parent_data = _pdata,                                  \
+                .num_parents = ARRAY_SIZE(_pdata),                      \
                 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags),             \
         },                                                              \
 }
 
-#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags)  \
+#define AUD_DIV(_name, _reg, _shift, _width, _dflags, _phws, _iflags)   \
 struct clk_regmap aud_##_name = {                                       \
         .data = &(struct clk_regmap_div_data){                          \
                 .offset = (_reg),                                       \
@@ -67,15 +67,27 @@ struct clk_regmap aud_##_name = {					\
         .hw.init = &(struct clk_init_data){                             \
                 .name = "aud_"#_name,                                   \
                 .ops = &clk_regmap_divider_ops,                         \
-                .parent_names = (const char *[]) { _pname },            \
+                .parent_hws = (const struct clk_hw *[]) { &_phws.hw },  \
                 .num_parents = 1,                                       \
                 .flags = (_iflags),                                     \
         },                                                              \
 }
 
 #define AUD_PCLK_GATE(_name, _bit)                              \
-        AUD_GATE(_name, AUDIO_CLK_GATE_EN, _bit, "audio_pclk", 0)
-
+struct clk_regmap aud_##_name = {                                       \
+        .data = &(struct clk_regmap_gate_data){                         \
+                .offset = (AUDIO_CLK_GATE_EN),                          \
+                .bit_idx = (_bit),                                      \
+        },                                                              \
+        .hw.init = &(struct clk_init_data) {                            \
+                .name = "aud_"#_name,                                   \
+                .ops = &clk_regmap_gate_ops,                            \
+                .parent_data = &(const struct clk_parent_data) {        \
+                        .fw_name = "pclk",                              \
+                },                                                      \
+                .num_parents = 1,                                       \
+        },                                                              \
+}
 /* Audio peripheral clocks */
 static AUD_PCLK_GATE(ddr_arb,      0);
 static AUD_PCLK_GATE(pdm,          1);
@@ -100,14 +112,20 @@ static AUD_PCLK_GATE(power_detect, 19);
 static AUD_PCLK_GATE(spdifout_b,   21);
 
 /* Audio Master Clocks */
-static const char * const mst_mux_parent_names[] = {
-        "aud_mst_in0", "aud_mst_in1", "aud_mst_in2", "aud_mst_in3",
-        "aud_mst_in4", "aud_mst_in5", "aud_mst_in6", "aud_mst_in7",
+static const struct clk_parent_data mst_mux_parent_data[] = {
+        { .fw_name = "mst_in0", },
+        { .fw_name = "mst_in1", },
+        { .fw_name = "mst_in2", },
+        { .fw_name = "mst_in3", },
+        { .fw_name = "mst_in4", },
+        { .fw_name = "mst_in5", },
+        { .fw_name = "mst_in6", },
+        { .fw_name = "mst_in7", },
 };
 
 #define AUD_MST_MUX(_name, _reg, _flag)                         \
         AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag,              \
-                mst_mux_parent_names, CLK_SET_RATE_PARENT)
+                mst_mux_parent_data, 0)
 
 #define AUD_MST_MCLK_MUX(_name, _reg)                           \
         AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
@@ -129,7 +147,7 @@ static AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
 
 #define AUD_MST_DIV(_name, _reg, _flag)                         \
         AUD_DIV(_name##_div, _reg, 0, 16, _flag,                \
-                    "aud_"#_name"_sel", CLK_SET_RATE_PARENT)    \
+                    aud_##_name##_sel, CLK_SET_RATE_PARENT)     \
 
 #define AUD_MST_MCLK_DIV(_name, _reg)                           \
         AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
@@ -150,7 +168,7 @@ static AUD_MST_SYS_DIV(pdm_sysclk,    AUDIO_CLK_PDMIN_CTRL1);
 static AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
 
 #define AUD_MST_MCLK_GATE(_name, _reg)                          \
-        AUD_GATE(_name, _reg, 31,  "aud_"#_name"_div",  \
+        AUD_GATE(_name, _reg, 31,  aud_##_name##_div,           \
                  CLK_SET_RATE_PARENT)
 
 static AUD_MST_MCLK_GATE(mst_a_mclk,   AUDIO_MCLK_A_CTRL);
@@ -168,7 +186,7 @@ static AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
 /* Sample Clocks */
 #define AUD_MST_SCLK_PRE_EN(_name, _reg)                        \
         AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31,           \
-                 "aud_mst_"#_name"_mclk", 0)
+                 aud_mst_##_name##_mclk, 0)
 
 static AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
 static AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
@@ -178,7 +196,7 @@ static AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
 static AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
 
 #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width,               \
-                         _hi_shift, _hi_width, _pname, _iflags)         \
+                         _hi_shift, _hi_width, _phws, _iflags)          \
 struct clk_regmap aud_##_name = {                                       \
         .data = &(struct meson_sclk_div_data) {                         \
                 .div = {                                                \
@@ -195,7 +213,7 @@ struct clk_regmap aud_##_name = {					\
         .hw.init = &(struct clk_init_data) {                            \
                 .name = "aud_"#_name,                                   \
                 .ops = &meson_sclk_div_ops,                             \
-                .parent_names = (const char *[]) { _pname },            \
+                .parent_hws = (const struct clk_hw *[]) { &_phws.hw },  \
                 .num_parents = 1,                                       \
                 .flags = (_iflags),                                     \
         },                                                              \
@@ -203,7 +221,7 @@ struct clk_regmap aud_##_name = {					\
 
 #define AUD_MST_SCLK_DIV(_name, _reg)                                   \
         AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0,        \
-                     "aud_mst_"#_name"_sclk_pre_en",                    \
+                     aud_mst_##_name##_sclk_pre_en,                     \
                      CLK_SET_RATE_PARENT)
 
 static AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
@@ -214,8 +232,8 @@ static AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
 static AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
 
 #define AUD_MST_SCLK_POST_EN(_name, _reg)                               \
-        AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30,          \
-                 "aud_mst_"#_name"_sclk_div", CLK_SET_RATE_PARENT)
+        AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30,                  \
+                 aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT)
 
 static AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
 static AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
@@ -224,8 +242,8 @@ static AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
 static AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
 static AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
 
-#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \
-                         _pname, _iflags)                               \
+#define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2,    \
+                         _phws, _iflags)                                \
 struct clk_regmap aud_##_name = {                                       \
         .data = &(struct meson_clk_triphase_data) {                     \
                 .ph0 = {                                                \
@@ -247,7 +265,7 @@ struct clk_regmap aud_##_name = {					\
         .hw.init = &(struct clk_init_data) {                            \
                 .name = "aud_"#_name,                                   \
                 .ops = &meson_clk_triphase_ops,                         \
-                .parent_names = (const char *[]) { _pname },            \
+                .parent_hws = (const struct clk_hw *[]) { &_phws.hw },  \
                 .num_parents = 1,                                       \
                 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags),             \
         },                                                              \
@@ -255,7 +273,7 @@ struct clk_regmap aud_##_name = {					\
 
 #define AUD_MST_SCLK(_name, _reg)                                       \
         AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4,              \
-                     "aud_mst_"#_name"_sclk_post_en", CLK_SET_RATE_PARENT)
+                     aud_mst_##_name##_sclk_post_en, CLK_SET_RATE_PARENT)
 
 static AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
 static AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
@@ -266,7 +284,7 @@ static AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
 
 #define AUD_MST_LRCLK_DIV(_name, _reg)                                  \
         AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10,      \
-                     "aud_mst_"#_name"_sclk_post_en", 0)                \
+                     aud_mst_##_name##_sclk_post_en, 0)                 \
 
 static AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
 static AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
@@ -277,7 +295,7 @@ static AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
 
 #define AUD_MST_LRCLK(_name, _reg)                                      \
         AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5,             \
-                     "aud_mst_"#_name"_lrclk_div", CLK_SET_RATE_PARENT)
+                     aud_mst_##_name##_lrclk_div, CLK_SET_RATE_PARENT)
 
 static AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
 static AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
@@ -286,19 +304,29 @@ static AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
 static AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
 static AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
 
-static const char * const tdm_sclk_parent_names[] = {
-        "aud_mst_a_sclk", "aud_mst_b_sclk", "aud_mst_c_sclk",
-        "aud_mst_d_sclk", "aud_mst_e_sclk", "aud_mst_f_sclk",
-        "aud_slv_sclk0", "aud_slv_sclk1", "aud_slv_sclk2",
-        "aud_slv_sclk3", "aud_slv_sclk4", "aud_slv_sclk5",
-        "aud_slv_sclk6", "aud_slv_sclk7", "aud_slv_sclk8",
-        "aud_slv_sclk9"
+static const struct clk_parent_data tdm_sclk_parent_data[] = {
+        { .hw = &aud_mst_a_sclk.hw, },
+        { .hw = &aud_mst_b_sclk.hw, },
+        { .hw = &aud_mst_c_sclk.hw, },
+        { .hw = &aud_mst_d_sclk.hw, },
+        { .hw = &aud_mst_e_sclk.hw, },
+        { .hw = &aud_mst_f_sclk.hw, },
+        { .fw_name = "slv_sclk0", },
+        { .fw_name = "slv_sclk1", },
+        { .fw_name = "slv_sclk2", },
+        { .fw_name = "slv_sclk3", },
+        { .fw_name = "slv_sclk4", },
+        { .fw_name = "slv_sclk5", },
+        { .fw_name = "slv_sclk6", },
+        { .fw_name = "slv_sclk7", },
+        { .fw_name = "slv_sclk8", },
+        { .fw_name = "slv_sclk9", },
 };
 
 #define AUD_TDM_SCLK_MUX(_name, _reg)                           \
         AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24,           \
                     CLK_MUX_ROUND_CLOSEST,                      \
-                    tdm_sclk_parent_names, 0)
+                    tdm_sclk_parent_data, 0)
 
 static AUD_TDM_SCLK_MUX(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
 static AUD_TDM_SCLK_MUX(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
@@ -310,7 +338,7 @@ static AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
 
 #define AUD_TDM_SCLK_PRE_EN(_name, _reg)                                \
         AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31,                    \
-                 "aud_tdm"#_name"_sclk_sel", CLK_SET_RATE_PARENT)
+                 aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT)
 
 static AUD_TDM_SCLK_PRE_EN(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
 static AUD_TDM_SCLK_PRE_EN(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
@@ -322,7 +350,7 @@ static AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
 
 #define AUD_TDM_SCLK_POST_EN(_name, _reg)                               \
         AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30,                   \
-                 "aud_tdm"#_name"_sclk_pre_en", CLK_SET_RATE_PARENT)
+                 aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT)
 
 static AUD_TDM_SCLK_POST_EN(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
 static AUD_TDM_SCLK_POST_EN(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
@@ -344,8 +372,9 @@ static AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
         .hw.init = &(struct clk_init_data) {                            \
                 .name = "aud_tdm"#_name"_sclk",                         \
                 .ops = &meson_clk_phase_ops,                            \
-                .parent_names = (const char *[])                        \
-                { "aud_tdm"#_name"_sclk_post_en" },                     \
+                .parent_hws = (const struct clk_hw *[]) {               \
+                        &aud_tdm##_name##_sclk_post_en.hw               \
+                },                                                      \
                 .num_parents = 1,                                       \
                 .flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT,   \
         },                                                              \
@@ -359,19 +388,29 @@ static AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
 static AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
 static AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
 
-static const char * const tdm_lrclk_parent_names[] = {
-        "aud_mst_a_lrclk", "aud_mst_b_lrclk", "aud_mst_c_lrclk",
-        "aud_mst_d_lrclk", "aud_mst_e_lrclk", "aud_mst_f_lrclk",
-        "aud_slv_lrclk0", "aud_slv_lrclk1", "aud_slv_lrclk2",
-        "aud_slv_lrclk3", "aud_slv_lrclk4", "aud_slv_lrclk5",
-        "aud_slv_lrclk6", "aud_slv_lrclk7", "aud_slv_lrclk8",
-        "aud_slv_lrclk9"
+static const struct clk_parent_data tdm_lrclk_parent_data[] = {
+        { .hw = &aud_mst_a_lrclk.hw, },
+        { .hw = &aud_mst_b_lrclk.hw, },
+        { .hw = &aud_mst_c_lrclk.hw, },
+        { .hw = &aud_mst_d_lrclk.hw, },
+        { .hw = &aud_mst_e_lrclk.hw, },
+        { .hw = &aud_mst_f_lrclk.hw, },
+        { .fw_name = "slv_lrclk0", },
+        { .fw_name = "slv_lrclk1", },
+        { .fw_name = "slv_lrclk2", },
+        { .fw_name = "slv_lrclk3", },
+        { .fw_name = "slv_lrclk4", },
+        { .fw_name = "slv_lrclk5", },
+        { .fw_name = "slv_lrclk6", },
+        { .fw_name = "slv_lrclk7", },
+        { .fw_name = "slv_lrclk8", },
+        { .fw_name = "slv_lrclk9", },
 };
 
-#define AUD_TDM_LRLCK(_name, _reg)                     \
-        AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20,     \
-                CLK_MUX_ROUND_CLOSEST,                 \
-                tdm_lrclk_parent_names, 0)
+#define AUD_TDM_LRLCK(_name, _reg)                      \
+        AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20,      \
+                CLK_MUX_ROUND_CLOSEST,                  \
+                tdm_lrclk_parent_data, 0)
 
 static AUD_TDM_LRLCK(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
 static AUD_TDM_LRLCK(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
@@ -386,39 +425,51 @@ static AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
         AUD_MUX(tdm_##_name, _reg, 0x7, _shift, 0, _parents,    \
                 CLK_SET_RATE_NO_REPARENT)
 
-static const char * const mclk_pad_ctrl_parent_names[] = {
-        "aud_mst_a_mclk", "aud_mst_b_mclk", "aud_mst_c_mclk",
-        "aud_mst_d_mclk", "aud_mst_e_mclk", "aud_mst_f_mclk",
+static const struct clk_parent_data mclk_pad_ctrl_parent_data[] = {
+        { .hw = &aud_mst_a_mclk.hw },
+        { .hw = &aud_mst_b_mclk.hw },
+        { .hw = &aud_mst_c_mclk.hw },
+        { .hw = &aud_mst_d_mclk.hw },
+        { .hw = &aud_mst_e_mclk.hw },
+        { .hw = &aud_mst_f_mclk.hw },
 };
 
 static AUD_TDM_PAD_CTRL(mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0,
-                        mclk_pad_ctrl_parent_names);
+                        mclk_pad_ctrl_parent_data);
 static AUD_TDM_PAD_CTRL(mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4,
-                        mclk_pad_ctrl_parent_names);
-
-static const char * const lrclk_pad_ctrl_parent_names[] = {
-        "aud_mst_a_lrclk", "aud_mst_b_lrclk", "aud_mst_c_lrclk",
-        "aud_mst_d_lrclk", "aud_mst_e_lrclk", "aud_mst_f_lrclk",
+                        mclk_pad_ctrl_parent_data);
+
+static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = {
+        { .hw = &aud_mst_a_lrclk.hw },
+        { .hw = &aud_mst_b_lrclk.hw },
+        { .hw = &aud_mst_c_lrclk.hw },
+        { .hw = &aud_mst_d_lrclk.hw },
+        { .hw = &aud_mst_e_lrclk.hw },
+        { .hw = &aud_mst_f_lrclk.hw },
 };
 
 static AUD_TDM_PAD_CTRL(lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16,
-                        lrclk_pad_ctrl_parent_names);
+                        lrclk_pad_ctrl_parent_data);
 static AUD_TDM_PAD_CTRL(lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20,
-                        lrclk_pad_ctrl_parent_names);
+                        lrclk_pad_ctrl_parent_data);
 static AUD_TDM_PAD_CTRL(lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24,
-                        lrclk_pad_ctrl_parent_names);
-
-static const char * const sclk_pad_ctrl_parent_names[] = {
-        "aud_mst_a_sclk", "aud_mst_b_sclk", "aud_mst_c_sclk",
-        "aud_mst_d_sclk", "aud_mst_e_sclk", "aud_mst_f_sclk",
+                        lrclk_pad_ctrl_parent_data);
+
+static const struct clk_parent_data sclk_pad_ctrl_parent_data[] = {
+        { .hw = &aud_mst_a_sclk.hw },
+        { .hw = &aud_mst_b_sclk.hw },
+        { .hw = &aud_mst_c_sclk.hw },
+        { .hw = &aud_mst_d_sclk.hw },
+        { .hw = &aud_mst_e_sclk.hw },
+        { .hw = &aud_mst_f_sclk.hw },
 };
 
 static AUD_TDM_PAD_CTRL(sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0,
-                        sclk_pad_ctrl_parent_names);
+                        sclk_pad_ctrl_parent_data);
 static AUD_TDM_PAD_CTRL(sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4,
-                        sclk_pad_ctrl_parent_names);
+                        sclk_pad_ctrl_parent_data);
 static AUD_TDM_PAD_CTRL(sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8,
-                        sclk_pad_ctrl_parent_names);
+                        sclk_pad_ctrl_parent_data);
 
 /*
  * Array of all clocks provided by this provider
@@ -868,54 +919,84 @@ static int devm_clk_get_enable(struct device *dev, char *id)
         return 0;
 }
 
-static int axg_register_clk_hw_input(struct device *dev,
-                                     const char *name)
+struct axg_audio_reset_data {
+        struct reset_controller_dev rstc;
+        struct regmap *map;
+        unsigned int offset;
+};
+
+static void axg_audio_reset_reg_and_bit(struct axg_audio_reset_data *rst,
+                                        unsigned long id,
+                                        unsigned int *reg,
+                                        unsigned int *bit)
+{
+        unsigned int stride = regmap_get_reg_stride(rst->map);
+
+        *reg = (id / (stride * BITS_PER_BYTE)) * stride;
+        *reg += rst->offset;
+        *bit = id % (stride * BITS_PER_BYTE);
+}
+
+static int axg_audio_reset_update(struct reset_controller_dev *rcdev,
+                                unsigned long id, bool assert)
 {
-        char *clk_name;
-        struct clk_hw *hw;
-        int err = 0;
+        struct axg_audio_reset_data *rst =
+                container_of(rcdev, struct axg_audio_reset_data, rstc);
+        unsigned int offset, bit;
 
-        clk_name = kasprintf(GFP_KERNEL, "aud_%s", name);
-        if (!clk_name)
-                return -ENOMEM;
+        axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
 
-        hw = meson_clk_hw_register_input(dev, name, clk_name, 0);
-        if (IS_ERR(hw)) {
-                /* It is ok if an input clock is missing */
-                if (PTR_ERR(hw) == -ENOENT) {
-                        dev_dbg(dev, "%s not provided", name);
-                } else {
-                        err = PTR_ERR(hw);
-                        if (err != -EPROBE_DEFER)
-                                dev_err(dev, "failed to get %s clock", name);
-                }
-        }
+        regmap_update_bits(rst->map, offset, BIT(bit),
+                        assert ? BIT(bit) : 0);
 
-        kfree(clk_name);
-        return err;
+        return 0;
 }
 
-static int axg_register_clk_hw_inputs(struct device *dev,
-                                      const char *basename,
-                                      unsigned int count)
+static int axg_audio_reset_status(struct reset_controller_dev *rcdev,
+                                unsigned long id)
 {
-        char *name;
-        int i, ret;
+        struct axg_audio_reset_data *rst =
+                container_of(rcdev, struct axg_audio_reset_data, rstc);
+        unsigned int val, offset, bit;
 
-        for (i = 0; i < count; i++) {
-                name = kasprintf(GFP_KERNEL, "%s%d", basename, i);
-                if (!name)
-                        return -ENOMEM;
+        axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
 
-                ret = axg_register_clk_hw_input(dev, name);
-                kfree(name);
-                if (ret)
-                        return ret;
-        }
+        regmap_read(rst->map, offset, &val);
 
-        return 0;
+        return !!(val & BIT(bit));
 }
 
+static int axg_audio_reset_assert(struct reset_controller_dev *rcdev,
+                                unsigned long id)
+{
+        return axg_audio_reset_update(rcdev, id, true);
+}
+
+static int axg_audio_reset_deassert(struct reset_controller_dev *rcdev,
+                                unsigned long id)
+{
+        return axg_audio_reset_update(rcdev, id, false);
+}
+
+static int axg_audio_reset_toggle(struct reset_controller_dev *rcdev,
+                                unsigned long id)
+{
+        int ret;
+
+        ret = axg_audio_reset_assert(rcdev, id);
+        if (ret)
+                return ret;
+
+        return axg_audio_reset_deassert(rcdev, id);
+}
+
+static const struct reset_control_ops axg_audio_rstc_ops = {
+        .assert = axg_audio_reset_assert,
+        .deassert = axg_audio_reset_deassert,
+        .reset = axg_audio_reset_toggle,
+        .status = axg_audio_reset_status,
+};
+
 static const struct regmap_config axg_audio_regmap_cfg = {
         .reg_bits       = 32,
         .val_bits       = 32,
@@ -925,12 +1006,15 @@ static const struct regmap_config axg_audio_regmap_cfg = {
 
 struct audioclk_data {
         struct clk_hw_onecell_data *hw_onecell_data;
+        unsigned int reset_offset;
+        unsigned int reset_num;
 };
 
 static int axg_audio_clkc_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         const struct audioclk_data *data;
+        struct axg_audio_reset_data *rst;
         struct regmap *map;
         struct resource *res;
         void __iomem *regs;
@@ -963,29 +1047,6 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
                 return ret;
         }
 
-        /* Register the peripheral input clock */
-        hw = meson_clk_hw_register_input(dev, "pclk", "audio_pclk", 0);
-        if (IS_ERR(hw))
-                return PTR_ERR(hw);
-
-        /* Register optional input master clocks */
-        ret = axg_register_clk_hw_inputs(dev, "mst_in",
-                                         AUD_MST_IN_COUNT);
-        if (ret)
-                return ret;
-
-        /* Register optional input slave sclks */
-        ret = axg_register_clk_hw_inputs(dev, "slv_sclk",
-                                         AUD_SLV_SCLK_COUNT);
-        if (ret)
-                return ret;
-
-        /* Register optional input slave lrclks */
-        ret = axg_register_clk_hw_inputs(dev, "slv_lrclk",
-                                         AUD_SLV_LRCLK_COUNT);
-        if (ret)
-                return ret;
-
         /* Populate regmap for the regmap backed clocks */
         for (i = 0; i < ARRAY_SIZE(aud_clk_regmaps); i++)
                 aud_clk_regmaps[i]->map = map;
@@ -1005,8 +1066,27 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
                 }
         }
 
-        return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
-                                           data->hw_onecell_data);
+        ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+                                        data->hw_onecell_data);
+        if (ret)
+                return ret;
+
+        /* Stop here if there is no reset */
+        if (!data->reset_num)
+                return 0;
+
+        rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
+        if (!rst)
+                return -ENOMEM;
+
+        rst->map = map;
+        rst->offset = data->reset_offset;
+        rst->rstc.nr_resets = data->reset_num;
+        rst->rstc.ops = &axg_audio_rstc_ops;
+        rst->rstc.of_node = dev->of_node;
+        rst->rstc.owner = THIS_MODULE;
+
+        return devm_reset_controller_register(dev, &rst->rstc);
 }
 
 static const struct audioclk_data axg_audioclk_data = {
@@ -1015,6 +1095,8 @@ static const struct audioclk_data axg_audioclk_data = {
 
 static const struct audioclk_data g12a_audioclk_data = {
         .hw_onecell_data = &g12a_audio_hw_onecell_data,
+        .reset_offset = AUDIO_SW_RESET,
+        .reset_num = 26,
 };
 
 static const struct of_device_id clkc_match_table[] = {
diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h
index 5d972d55d6c7..c00e28b2e1a9 100644
--- a/drivers/clk/meson/axg-audio.h
+++ b/drivers/clk/meson/axg-audio.h
@@ -22,6 +22,7 @@
 #define AUDIO_MCLK_F_CTRL       0x018
 #define AUDIO_MST_PAD_CTRL0     0x01c
 #define AUDIO_MST_PAD_CTRL1     0x020
+#define AUDIO_SW_RESET          0x024
 #define AUDIO_MST_A_SCLK_CTRL0  0x040
 #define AUDIO_MST_A_SCLK_CTRL1  0x044
 #define AUDIO_MST_B_SCLK_CTRL0  0x048
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 3ddd0efc9ee0..13fc0006f63d 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -14,7 +14,6 @@
 #include <linux/of_device.h>
 #include <linux/platform_device.h>
 
-#include "clk-input.h"
 #include "clk-regmap.h"
 #include "clk-pll.h"
 #include "clk-mpll.h"
@@ -59,7 +58,9 @@ static struct clk_regmap axg_fixed_pll_dco = {
         .hw.init = &(struct clk_init_data){
                 .name = "fixed_pll_dco",
                 .ops = &meson_clk_pll_ro_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
         },
 };
@@ -74,7 +75,9 @@ static struct clk_regmap axg_fixed_pll = {
         .hw.init = &(struct clk_init_data){
                 .name = "fixed_pll",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "fixed_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_fixed_pll_dco.hw
+                },
                 .num_parents = 1,
                 /*
                  * This clock won't ever change at runtime so
@@ -114,7 +117,9 @@ static struct clk_regmap axg_sys_pll_dco = {
         .hw.init = &(struct clk_init_data){
                 .name = "sys_pll_dco",
                 .ops = &meson_clk_pll_ro_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
         },
 };
@@ -129,7 +134,9 @@ static struct clk_regmap axg_sys_pll = {
         .hw.init = &(struct clk_init_data){
                 .name = "sys_pll",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "sys_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_sys_pll_dco.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -215,7 +222,9 @@ static struct clk_regmap axg_gp0_pll_dco = {
         .hw.init = &(struct clk_init_data){
                 .name = "gp0_pll_dco",
                 .ops = &meson_clk_pll_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
         },
 };
@@ -230,7 +239,9 @@ static struct clk_regmap axg_gp0_pll = {
         .hw.init = &(struct clk_init_data){
                 .name = "gp0_pll",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "gp0_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_gp0_pll_dco.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -284,7 +295,9 @@ static struct clk_regmap axg_hifi_pll_dco = {
         .hw.init = &(struct clk_init_data){
                 .name = "hifi_pll_dco",
                 .ops = &meson_clk_pll_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
         },
 };
@@ -299,7 +312,9 @@ static struct clk_regmap axg_hifi_pll = {
         .hw.init = &(struct clk_init_data){
                 .name = "hifi_pll",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "hifi_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_hifi_pll_dco.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -311,7 +326,7 @@ static struct clk_fixed_factor axg_fclk_div2_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div2_div",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
                 .num_parents = 1,
         },
 };
@@ -324,7 +339,9 @@ static struct clk_regmap axg_fclk_div2 = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div2",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div2_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_fclk_div2_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_IS_CRITICAL,
         },
@@ -336,7 +353,7 @@ static struct clk_fixed_factor axg_fclk_div3_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div3_div",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
                 .num_parents = 1,
         },
 };
@@ -349,7 +366,9 @@ static struct clk_regmap axg_fclk_div3 = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div3",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div3_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_fclk_div3_div.hw
+                },
                 .num_parents = 1,
                 /*
                  * FIXME:
@@ -372,7 +391,7 @@ static struct clk_fixed_factor axg_fclk_div4_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div4_div",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
                 .num_parents = 1,
         },
 };
@@ -385,7 +404,9 @@ static struct clk_regmap axg_fclk_div4 = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div4",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div4_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_fclk_div4_div.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -396,7 +417,7 @@ static struct clk_fixed_factor axg_fclk_div5_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div5_div",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) { &axg_fixed_pll.hw },
                 .num_parents = 1,
         },
 };
@@ -409,7 +430,9 @@ static struct clk_regmap axg_fclk_div5 = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div5",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div5_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_fclk_div5_div.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -420,7 +443,9 @@ static struct clk_fixed_factor axg_fclk_div7_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div7_div",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_fixed_pll.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -433,7 +458,9 @@ static struct clk_regmap axg_fclk_div7 = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div7",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div7_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_fclk_div7_div.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -447,7 +474,9 @@ static struct clk_regmap axg_mpll_prediv = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll_prediv",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_fixed_pll.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -480,7 +509,9 @@ static struct clk_regmap axg_mpll0_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll0_div",
                 .ops = &meson_clk_mpll_ops,
-                .parent_names = (const char *[]){ "mpll_prediv" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_mpll_prediv.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -493,7 +524,9 @@ static struct clk_regmap axg_mpll0 = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mpll0_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_mpll0_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -527,7 +560,9 @@ static struct clk_regmap axg_mpll1_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll1_div",
                 .ops = &meson_clk_mpll_ops,
-                .parent_names = (const char *[]){ "mpll_prediv" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_mpll_prediv.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -540,7 +575,9 @@ static struct clk_regmap axg_mpll1 = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll1",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mpll1_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_mpll1_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -579,7 +616,9 @@ static struct clk_regmap axg_mpll2_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll2_div",
                 .ops = &meson_clk_mpll_ops,
-                .parent_names = (const char *[]){ "mpll_prediv" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_mpll_prediv.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -592,7 +631,9 @@ static struct clk_regmap axg_mpll2 = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll2",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mpll2_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_mpll2_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -626,7 +667,9 @@ static struct clk_regmap axg_mpll3_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll3_div",
                 .ops = &meson_clk_mpll_ops,
-                .parent_names = (const char *[]){ "mpll_prediv" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_mpll_prediv.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -639,7 +682,9 @@ static struct clk_regmap axg_mpll3 = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll3",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mpll3_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_mpll3_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -702,7 +747,9 @@ static struct clk_regmap axg_pcie_pll_dco = {
         .hw.init = &(struct clk_init_data){
                 .name = "pcie_pll_dco",
                 .ops = &meson_clk_pll_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
         },
 };
@@ -717,7 +764,9 @@ static struct clk_regmap axg_pcie_pll_od = {
         .hw.init = &(struct clk_init_data){
                 .name = "pcie_pll_od",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "pcie_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_pcie_pll_dco.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -733,7 +782,9 @@ static struct clk_regmap axg_pcie_pll = {
         .hw.init = &(struct clk_init_data){
                 .name = "pcie_pll",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "pcie_pll_od" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_pcie_pll_od.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -750,7 +801,7 @@ static struct clk_regmap axg_pcie_mux = {
         .hw.init = &(struct clk_init_data){
                 .name = "pcie_mux",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "pcie_pll" },
+                .parent_hws = (const struct clk_hw *[]) { &axg_pcie_pll.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -767,7 +818,7 @@ static struct clk_regmap axg_pcie_ref = {
         .hw.init = &(struct clk_init_data){
                 .name = "pcie_ref",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "pcie_mux" },
+                .parent_hws = (const struct clk_hw *[]) { &axg_pcie_mux.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -781,7 +832,7 @@ static struct clk_regmap axg_pcie_cml_en0 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "pcie_cml_en0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "pcie_ref" },
+                .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
 
@@ -796,16 +847,21 @@ static struct clk_regmap axg_pcie_cml_en1 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "pcie_cml_en1",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "pcie_ref" },
+                .parent_hws = (const struct clk_hw *[]) { &axg_pcie_ref.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
 
 static u32 mux_table_clk81[]    = { 0, 2, 3, 4, 5, 6, 7 };
-static const char * const clk81_parent_names[] = {
-        IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
-        "fclk_div3", "fclk_div5"
+static const struct clk_parent_data clk81_parent_data[] = {
+        { .fw_name = "xtal", },
+        { .hw = &axg_fclk_div7.hw },
+        { .hw = &axg_mpll1.hw },
+        { .hw = &axg_mpll2.hw },
+        { .hw = &axg_fclk_div4.hw },
+        { .hw = &axg_fclk_div3.hw },
+        { .hw = &axg_fclk_div5.hw },
 };
 
 static struct clk_regmap axg_mpeg_clk_sel = {
@@ -818,8 +874,8 @@ static struct clk_regmap axg_mpeg_clk_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpeg_clk_sel",
                 .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = clk81_parent_names,
-                .num_parents = ARRAY_SIZE(clk81_parent_names),
+                .parent_data = clk81_parent_data,
+                .num_parents = ARRAY_SIZE(clk81_parent_data),
         },
 };
 
@@ -832,7 +888,9 @@ static struct clk_regmap axg_mpeg_clk_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpeg_clk_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "mpeg_clk_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_mpeg_clk_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -846,15 +904,20 @@ static struct clk_regmap axg_clk81 = {
         .hw.init = &(struct clk_init_data){
                 .name = "clk81",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mpeg_clk_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_mpeg_clk_div.hw
+                },
                 .num_parents = 1,
                 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
         },
 };
 
-static const char * const axg_sd_emmc_clk0_parent_names[] = {
-        IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
-
+static const struct clk_parent_data axg_sd_emmc_clk0_parent_data[] = {
+        { .fw_name = "xtal", },
+        { .hw = &axg_fclk_div2.hw },
+        { .hw = &axg_fclk_div3.hw },
+        { .hw = &axg_fclk_div5.hw },
+        { .hw = &axg_fclk_div7.hw },
         /*
          * Following these parent clocks, we should also have had mpll2, mpll3
          * and gp0_pll but these clocks are too precious to be used here. All
@@ -873,8 +936,8 @@ static struct clk_regmap axg_sd_emmc_b_clk0_sel = {
         .hw.init = &(struct clk_init_data) {
                 .name = "sd_emmc_b_clk0_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = axg_sd_emmc_clk0_parent_names,
-                .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
+                .parent_data = axg_sd_emmc_clk0_parent_data,
+                .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -889,7 +952,9 @@ static struct clk_regmap axg_sd_emmc_b_clk0_div = {
         .hw.init = &(struct clk_init_data) {
                 .name = "sd_emmc_b_clk0_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_sd_emmc_b_clk0_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -903,7 +968,9 @@ static struct clk_regmap axg_sd_emmc_b_clk0 = {
         .hw.init = &(struct clk_init_data){
                 .name = "sd_emmc_b_clk0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_sd_emmc_b_clk0_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -919,8 +986,8 @@ static struct clk_regmap axg_sd_emmc_c_clk0_sel = {
         .hw.init = &(struct clk_init_data) {
                 .name = "sd_emmc_c_clk0_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = axg_sd_emmc_clk0_parent_names,
-                .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
+                .parent_data = axg_sd_emmc_clk0_parent_data,
+                .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_data),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -935,7 +1002,9 @@ static struct clk_regmap axg_sd_emmc_c_clk0_div = {
         .hw.init = &(struct clk_init_data) {
                 .name = "sd_emmc_c_clk0_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_sd_emmc_c_clk0_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -949,7 +1018,9 @@ static struct clk_regmap axg_sd_emmc_c_clk0 = {
         .hw.init = &(struct clk_init_data){
                 .name = "sd_emmc_c_clk0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_sd_emmc_c_clk0_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -957,9 +1028,18 @@ static struct clk_regmap axg_sd_emmc_c_clk0 = {
 
 static u32 mux_table_gen_clk[]  = { 0, 4, 5, 6, 7, 8,
                                     9, 10, 11, 13, 14, };
-static const char * const gen_clk_parent_names[] = {
-        IN_PREFIX "xtal", "hifi_pll", "mpll0", "mpll1", "mpll2", "mpll3",
-        "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
+static const struct clk_parent_data gen_clk_parent_data[] = {
+        { .fw_name = "xtal", },
+        { .hw = &axg_hifi_pll.hw },
+        { .hw = &axg_mpll0.hw },
+        { .hw = &axg_mpll1.hw },
+        { .hw = &axg_mpll2.hw },
+        { .hw = &axg_mpll3.hw },
+        { .hw = &axg_fclk_div4.hw },
+        { .hw = &axg_fclk_div3.hw },
+        { .hw = &axg_fclk_div5.hw },
+        { .hw = &axg_fclk_div7.hw },
+        { .hw = &axg_gp0_pll.hw },
 };
 
 static struct clk_regmap axg_gen_clk_sel = {
@@ -978,8 +1058,8 @@ static struct clk_regmap axg_gen_clk_sel = {
                  * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,
                  * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
                  */
-                .parent_names = gen_clk_parent_names,
-                .num_parents = ARRAY_SIZE(gen_clk_parent_names),
+                .parent_data = gen_clk_parent_data,
+                .num_parents = ARRAY_SIZE(gen_clk_parent_data),
         },
 };
 
@@ -992,7 +1072,9 @@ static struct clk_regmap axg_gen_clk_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "gen_clk_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "gen_clk_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_gen_clk_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1006,12 +1088,17 @@ static struct clk_regmap axg_gen_clk = {
         .hw.init = &(struct clk_init_data){
                 .name = "gen_clk",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "gen_clk_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &axg_gen_clk_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
 
+#define MESON_GATE(_name, _reg, _bit) \
+        MESON_PCLK(_name, _reg, _bit, &axg_clk81.hw)
+
 /* Everything Else (EE) domain gates */
 static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
 static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
diff --git a/drivers/clk/meson/clk-cpu-dyndiv.c b/drivers/clk/meson/clk-cpu-dyndiv.c
new file mode 100644
index 000000000000..36976927fe82
--- /dev/null
+++ b/drivers/clk/meson/clk-cpu-dyndiv.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+
+#include "clk-regmap.h"
+#include "clk-cpu-dyndiv.h"
+
+static inline struct meson_clk_cpu_dyndiv_data *
+meson_clk_cpu_dyndiv_data(struct clk_regmap *clk)
+{
+        return (struct meson_clk_cpu_dyndiv_data *)clk->data;
+}
+
+static unsigned long meson_clk_cpu_dyndiv_recalc_rate(struct clk_hw *hw,
+                                                      unsigned long prate)
+{
+        struct clk_regmap *clk = to_clk_regmap(hw);
+        struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);
+
+        return divider_recalc_rate(hw, prate,
+                                   meson_parm_read(clk->map, &data->div),
+                                   NULL, 0, data->div.width);
+}
+
+static long meson_clk_cpu_dyndiv_round_rate(struct clk_hw *hw,
+                                            unsigned long rate,
+                                            unsigned long *prate)
+{
+        struct clk_regmap *clk = to_clk_regmap(hw);
+        struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);
+
+        return divider_round_rate(hw, rate, prate, NULL, data->div.width, 0);
+}
+
+static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate,
+                                          unsigned long parent_rate)
+{
+        struct clk_regmap *clk = to_clk_regmap(hw);
+        struct meson_clk_cpu_dyndiv_data *data = meson_clk_cpu_dyndiv_data(clk);
+        unsigned int val;
+        int ret;
+
+        ret = divider_get_val(rate, parent_rate, NULL, data->div.width, 0);
+        if (ret < 0)
+                return ret;
+
+        val = (unsigned int)ret << data->div.shift;
+
+        /* Write the SYS_CPU_DYN_ENABLE bit before changing the divider */
+        meson_parm_write(clk->map, &data->dyn, 1);
+
+        /* Update the divider while removing the SYS_CPU_DYN_ENABLE bit */
+        return regmap_update_bits(clk->map, data->div.reg_off,
+                                  SETPMASK(data->div.width, data->div.shift) |
+                                  SETPMASK(data->dyn.width, data->dyn.shift),
+                                  val);
+};
+
+const struct clk_ops meson_clk_cpu_dyndiv_ops = {
+        .recalc_rate = meson_clk_cpu_dyndiv_recalc_rate,
+        .round_rate = meson_clk_cpu_dyndiv_round_rate,
+        .set_rate = meson_clk_cpu_dyndiv_set_rate,
+};
+EXPORT_SYMBOL_GPL(meson_clk_cpu_dyndiv_ops);
+
+MODULE_DESCRIPTION("Amlogic CPU Dynamic Clock divider");
+MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/meson/clk-cpu-dyndiv.h b/drivers/clk/meson/clk-cpu-dyndiv.h
new file mode 100644
index 000000000000..f4908404792e
--- /dev/null
+++ b/drivers/clk/meson/clk-cpu-dyndiv.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#ifndef __MESON_CLK_CPU_DYNDIV_H
+#define __MESON_CLK_CPU_DYNDIV_H
+
+#include <linux/clk-provider.h>
+#include "parm.h"
+
+struct meson_clk_cpu_dyndiv_data {
+        struct parm div;
+        struct parm dyn;
+};
+
+extern const struct clk_ops meson_clk_cpu_dyndiv_ops;
+
+#endif /* __MESON_CLK_CPU_DYNDIV_H */
diff --git a/drivers/clk/meson/clk-input.c b/drivers/clk/meson/clk-input.c
deleted file mode 100644
index 086226e9dba6..000000000000
--- a/drivers/clk/meson/clk-input.c
+++ /dev/null
@@ -1,49 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/*
- * Copyright (c) 2018 BayLibre, SAS.
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- */
-
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/device.h>
-#include <linux/module.h>
-#include "clk-input.h"
-
-static const struct clk_ops meson_clk_no_ops = {};
-
-struct clk_hw *meson_clk_hw_register_input(struct device *dev,
-                                           const char *of_name,
-                                           const char *clk_name,
-                                           unsigned long flags)
-{
-        struct clk *parent_clk = devm_clk_get(dev, of_name);
-        struct clk_init_data init;
-        const char *parent_name;
-        struct clk_hw *hw;
-        int ret;
-
-        if (IS_ERR(parent_clk))
-                return (struct clk_hw *)parent_clk;
-
-        hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL);
-        if (!hw)
-                return ERR_PTR(-ENOMEM);
-
-        parent_name = __clk_get_name(parent_clk);
-        init.name = clk_name;
-        init.ops = &meson_clk_no_ops;
-        init.flags = flags;
-        init.parent_names = &parent_name;
-        init.num_parents = 1;
-        hw->init = &init;
-
-        ret = devm_clk_hw_register(dev, hw);
-
-        return ret ? ERR_PTR(ret) : hw;
-}
-EXPORT_SYMBOL_GPL(meson_clk_hw_register_input);
-
-MODULE_DESCRIPTION("Amlogic clock input helper");
-MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/meson/clk-input.h b/drivers/clk/meson/clk-input.h
deleted file mode 100644
index 4a541b9685a6..000000000000
--- a/drivers/clk/meson/clk-input.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2019 BayLibre, SAS.
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- */
-
-#ifndef __MESON_CLK_INPUT_H
-#define __MESON_CLK_INPUT_H
-
-#include <linux/clk-provider.h>
-
-struct device;
-
-struct clk_hw *meson_clk_hw_register_input(struct device *dev,
-                                           const char *of_name,
-                                           const char *clk_name,
-                                           unsigned long flags);
-
-#endif /* __MESON_CLK_INPUT_H */
diff --git a/drivers/clk/meson/clk-regmap.h b/drivers/clk/meson/clk-regmap.h
index 1dd0abe3ba91..c4a39604cffd 100644
--- a/drivers/clk/meson/clk-regmap.h
+++ b/drivers/clk/meson/clk-regmap.h
@@ -111,7 +111,7 @@ clk_get_regmap_mux_data(struct clk_regmap *clk)
 extern const struct clk_ops clk_regmap_mux_ops;
 extern const struct clk_ops clk_regmap_mux_ro_ops;
 
-#define __MESON_GATE(_name, _reg, _bit, _ops)                           \
+#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname)                   \
 struct clk_regmap _name = {                                             \
         .data = &(struct clk_regmap_gate_data){                         \
                 .offset = (_reg),                                       \
@@ -120,15 +120,15 @@ struct clk_regmap _name = {						\
         .hw.init = &(struct clk_init_data) {                            \
                 .name = #_name,                                         \
                 .ops = _ops,                                            \
-                .parent_names = (const char *[]){ "clk81" },            \
+                .parent_hws = (const struct clk_hw *[]) { _pname },     \
                 .num_parents = 1,                                       \
                 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),     \
         },                                                              \
 }
 
-#define MESON_GATE(_name, _reg, _bit)   \
-        __MESON_GATE(_name, _reg, _bit, &clk_regmap_gate_ops)
+#define MESON_PCLK(_name, _reg, _bit, _pname)   \
+        __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname)
 
-#define MESON_GATE_RO(_name, _reg, _bit)        \
-        __MESON_GATE(_name, _reg, _bit, &clk_regmap_gate_ro_ops)
+#define MESON_PCLK_RO(_name, _reg, _bit, _pname)        \
+        __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname)
 #endif /* __CLK_REGMAP_H */
diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c
index 1994e735396b..62499563e4f5 100644
--- a/drivers/clk/meson/g12a-aoclk.c
+++ b/drivers/clk/meson/g12a-aoclk.c
@@ -18,8 +18,6 @@
 #include "clk-regmap.h"
 #include "clk-dualdiv.h"
 
-#define IN_PREFIX "ao-in-"
-
 /*
  * AO Configuration Clock registers offsets
  * Register offsets from the data sheet must be multiplied by 4.
@@ -51,7 +49,9 @@ static struct clk_regmap g12a_aoclk_##_name = {				\
         .hw.init = &(struct clk_init_data) {                            \
                 .name =  "g12a_ao_" #_name,                             \
                 .ops = &clk_regmap_gate_ops,                            \
-                .parent_names = (const char *[]){ IN_PREFIX "mpeg-clk" }, \
+                .parent_data = &(const struct clk_parent_data) {        \
+                        .fw_name = "mpeg-clk",                          \
+                },                                                      \
                 .num_parents = 1,                                       \
                 .flags = CLK_IGNORE_UNUSED,                             \
         },                                                              \
@@ -81,7 +81,9 @@ static struct clk_regmap g12a_aoclk_cts_oscin = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_oscin",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
         },
 };
@@ -106,7 +108,9 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_pre = {
         .hw.init = &(struct clk_init_data){
                 .name = "g12a_ao_32k_by_oscin_pre",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "cts_oscin" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_aoclk_cts_oscin.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -143,7 +147,9 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "g12a_ao_32k_by_oscin_div",
                 .ops = &meson_clk_dualdiv_ops,
-                .parent_names = (const char *[]){ "g12a_ao_32k_by_oscin_pre" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_aoclk_32k_by_oscin_pre.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -158,8 +164,10 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "g12a_ao_32k_by_oscin_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "g12a_ao_32k_by_oscin_div",
-                                                  "g12a_ao_32k_by_oscin_pre" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_aoclk_32k_by_oscin_div.hw,
+                        &g12a_aoclk_32k_by_oscin_pre.hw,
+                },
                 .num_parents = 2,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -173,7 +181,9 @@ static struct clk_regmap g12a_aoclk_32k_by_oscin = {
         .hw.init = &(struct clk_init_data){
                 .name = "g12a_ao_32k_by_oscin",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "g12a_ao_32k_by_oscin_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_aoclk_32k_by_oscin_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -189,7 +199,9 @@ static struct clk_regmap g12a_aoclk_cec_pre = {
         .hw.init = &(struct clk_init_data){
                 .name = "g12a_ao_cec_pre",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "cts_oscin" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_aoclk_cts_oscin.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -226,7 +238,9 @@ static struct clk_regmap g12a_aoclk_cec_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "g12a_ao_cec_div",
                 .ops = &meson_clk_dualdiv_ops,
-                .parent_names = (const char *[]){ "g12a_ao_cec_pre" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_aoclk_cec_pre.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -241,8 +255,10 @@ static struct clk_regmap g12a_aoclk_cec_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "g12a_ao_cec_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "g12a_ao_cec_div",
-                                                  "g12a_ao_cec_pre" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_aoclk_cec_div.hw,
+                        &g12a_aoclk_cec_pre.hw,
+                },
                 .num_parents = 2,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -256,7 +272,9 @@ static struct clk_regmap g12a_aoclk_cec = {
         .hw.init = &(struct clk_init_data){
                 .name = "g12a_ao_cec",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "g12a_ao_cec_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_aoclk_cec_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -272,8 +290,10 @@ static struct clk_regmap g12a_aoclk_cts_rtc_oscin = {
         .hw.init = &(struct clk_init_data){
                 .name = "g12a_ao_cts_rtc_oscin",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "g12a_ao_32k_by_oscin",
-                                                  IN_PREFIX "ext_32k-0" },
+                .parent_data = (const struct clk_parent_data []) {
+                        { .hw = &g12a_aoclk_32k_by_oscin.hw },
+                        { .fw_name = "ext-32k-0", },
+                },
                 .num_parents = 2,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -289,8 +309,10 @@ static struct clk_regmap g12a_aoclk_clk81 = {
         .hw.init = &(struct clk_init_data){
                 .name = "g12a_ao_clk81",
                 .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "mpeg-clk",
-                                                  "g12a_ao_cts_rtc_oscin"},
+                .parent_data = (const struct clk_parent_data []) {
+                        { .fw_name = "mpeg-clk", },
+                        { .hw = &g12a_aoclk_cts_rtc_oscin.hw },
+                },
                 .num_parents = 2,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -305,8 +327,10 @@ static struct clk_regmap g12a_aoclk_saradc_mux = {
         .hw.init = &(struct clk_init_data){
                 .name = "g12a_ao_saradc_mux",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal",
-                                                  "g12a_ao_clk81" },
+                .parent_data = (const struct clk_parent_data []) {
+                        { .fw_name = "xtal", },
+                        { .hw = &g12a_aoclk_clk81.hw },
+                },
                 .num_parents = 2,
         },
 };
@@ -320,7 +344,9 @@ static struct clk_regmap g12a_aoclk_saradc_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "g12a_ao_saradc_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "g12a_ao_saradc_mux" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_aoclk_saradc_mux.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -334,7 +360,9 @@ static struct clk_regmap g12a_aoclk_saradc_gate = {
         .hw.init = &(struct clk_init_data){
                 .name = "g12a_ao_saradc_gate",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "g12a_ao_saradc_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_aoclk_saradc_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -417,12 +445,6 @@ static const struct clk_hw_onecell_data g12a_aoclk_onecell_data = {
         .num = NR_CLKS,
 };
 
-static const struct meson_aoclk_input g12a_aoclk_inputs[] = {
-        { .name = "xtal",       .required = true  },
-        { .name = "mpeg-clk",   .required = true  },
-        { .name = "ext-32k-0",  .required = false },
-};
-
 static const struct meson_aoclk_data g12a_aoclkc_data = {
         .reset_reg      = AO_RTI_GEN_CNTL_REG0,
         .num_reset      = ARRAY_SIZE(g12a_aoclk_reset),
@@ -430,9 +452,6 @@ static const struct meson_aoclk_data g12a_aoclkc_data = {
         .num_clks       = ARRAY_SIZE(g12a_aoclk_regmap),
         .clks           = g12a_aoclk_regmap,
         .hw_data        = &g12a_aoclk_onecell_data,
-        .inputs         = g12a_aoclk_inputs,
-        .num_inputs     = ARRAY_SIZE(g12a_aoclk_inputs),
-        .input_prefix   = IN_PREFIX,
 };
 
 static const struct of_device_id g12a_aoclkc_match_table[] = {
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index db1c4ed9d54e..ea4c791f106d 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -14,11 +14,12 @@
 #include <linux/init.h>
 #include <linux/of_device.h>
 #include <linux/platform_device.h>
+#include <linux/clk.h>
 
-#include "clk-input.h"
 #include "clk-mpll.h"
 #include "clk-pll.h"
 #include "clk-regmap.h"
+#include "clk-cpu-dyndiv.h"
 #include "vid-pll-div.h"
 #include "meson-eeclk.h"
 #include "g12a.h"
@@ -61,7 +62,9 @@ static struct clk_regmap g12a_fixed_pll_dco = {
         .hw.init = &(struct clk_init_data){
                 .name = "fixed_pll_dco",
                 .ops = &meson_clk_pll_ro_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
         },
 };
@@ -76,7 +79,9 @@ static struct clk_regmap g12a_fixed_pll = {
         .hw.init = &(struct clk_init_data){
                 .name = "fixed_pll",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "fixed_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_fixed_pll_dco.hw
+                },
                 .num_parents = 1,
                 /*
                  * This clock won't ever change at runtime so
@@ -85,16 +90,9 @@ static struct clk_regmap g12a_fixed_pll = {
         },
 };
 
-/*
- * Internal sys pll emulation configuration parameters
- */
-static const struct reg_sequence g12a_sys_init_regs[] = {
-        { .reg = HHI_SYS_PLL_CNTL1,     .def = 0x00000000 },
-        { .reg = HHI_SYS_PLL_CNTL2,     .def = 0x00000000 },
-        { .reg = HHI_SYS_PLL_CNTL3,     .def = 0x48681c00 },
-        { .reg = HHI_SYS_PLL_CNTL4,     .def = 0x88770290 },
-        { .reg = HHI_SYS_PLL_CNTL5,     .def = 0x39272000 },
-        { .reg = HHI_SYS_PLL_CNTL6,     .def = 0x56540000 },
+static const struct pll_mult_range g12a_sys_pll_mult_range = {
+        .min = 128,
+        .max = 250,
 };
 
 static struct clk_regmap g12a_sys_pll_dco = {
@@ -124,14 +122,17 @@ static struct clk_regmap g12a_sys_pll_dco = {
                         .shift   = 29,
                         .width   = 1,
                 },
-                .init_regs = g12a_sys_init_regs,
-                .init_count = ARRAY_SIZE(g12a_sys_init_regs),
+                .range = &g12a_sys_pll_mult_range,
         },
         .hw.init = &(struct clk_init_data){
                 .name = "sys_pll_dco",
-                .ops = &meson_clk_pll_ro_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .ops = &meson_clk_pll_ops,
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
+                /* This clock feeds the CPU, avoid disabling it */
+                .flags = CLK_IS_CRITICAL,
         },
 };
 
@@ -144,9 +145,12 @@ static struct clk_regmap g12a_sys_pll = {
         },
         .hw.init = &(struct clk_init_data){
                 .name = "sys_pll",
-                .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "sys_pll_dco" },
+                .ops = &clk_regmap_divider_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_sys_pll_dco.hw
+                },
                 .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT,
         },
 };
 
@@ -177,12 +181,17 @@ static struct clk_regmap g12b_sys1_pll_dco = {
                         .shift   = 29,
                         .width   = 1,
                 },
+                .range = &g12a_sys_pll_mult_range,
         },
         .hw.init = &(struct clk_init_data){
                 .name = "sys1_pll_dco",
-                .ops = &meson_clk_pll_ro_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .ops = &meson_clk_pll_ops,
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
+                /* This clock feeds the CPU, avoid disabling it */
+                .flags = CLK_IS_CRITICAL,
         },
 };
 
@@ -195,9 +204,12 @@ static struct clk_regmap g12b_sys1_pll = {
         },
         .hw.init = &(struct clk_init_data){
                 .name = "sys1_pll",
-                .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "sys1_pll_dco" },
+                .ops = &clk_regmap_divider_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_sys1_pll_dco.hw
+                },
                 .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT,
         },
 };
 
@@ -209,7 +221,7 @@ static struct clk_regmap g12a_sys_pll_div16_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "sys_pll_div16_en",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "sys_pll" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_sys_pll.hw },
                 .num_parents = 1,
                 /*
                  * This clock is used to debug the sys_pll range
@@ -226,7 +238,9 @@ static struct clk_regmap g12b_sys1_pll_div16_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "sys1_pll_div16_en",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "sys1_pll" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_sys1_pll.hw
+                },
                 .num_parents = 1,
                 /*
                  * This clock is used to debug the sys_pll range
@@ -241,7 +255,9 @@ static struct clk_fixed_factor g12a_sys_pll_div16 = {
         .hw.init = &(struct clk_init_data){
                 .name = "sys_pll_div16",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "sys_pll_div16_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_sys_pll_div16_en.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -252,11 +268,75 @@ static struct clk_fixed_factor g12b_sys1_pll_div16 = {
         .hw.init = &(struct clk_init_data){
                 .name = "sys1_pll_div16",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "sys1_pll_div16_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_sys1_pll_div16_en.hw
+                },
+                .num_parents = 1,
+        },
+};
+
+static struct clk_fixed_factor g12a_fclk_div2_div = {
+        .mult = 1,
+        .div = 2,
+        .hw.init = &(struct clk_init_data){
+                .name = "fclk_div2_div",
+                .ops = &clk_fixed_factor_ops,
+                .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
+                .num_parents = 1,
+        },
+};
+
+static struct clk_regmap g12a_fclk_div2 = {
+        .data = &(struct clk_regmap_gate_data){
+                .offset = HHI_FIX_PLL_CNTL1,
+                .bit_idx = 24,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "fclk_div2",
+                .ops = &clk_regmap_gate_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_fclk_div2_div.hw
+                },
+                .num_parents = 1,
+        },
+};
+
+static struct clk_fixed_factor g12a_fclk_div3_div = {
+        .mult = 1,
+        .div = 3,
+        .hw.init = &(struct clk_init_data){
+                .name = "fclk_div3_div",
+                .ops = &clk_fixed_factor_ops,
+                .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
                 .num_parents = 1,
         },
 };
 
+static struct clk_regmap g12a_fclk_div3 = {
+        .data = &(struct clk_regmap_gate_data){
+                .offset = HHI_FIX_PLL_CNTL1,
+                .bit_idx = 20,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "fclk_div3",
+                .ops = &clk_regmap_gate_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_fclk_div3_div.hw
+                },
+                .num_parents = 1,
+                /*
+                 * This clock is used by the resident firmware and is required
+                 * by the platform to operate correctly.
+                 * Until the following condition are met, we need this clock to
+                 * be marked as critical:
+                 * a) Mark the clock used by a firmware resource, if possible
+                 * b) CCF has a clock hand-off mechanism to make the sure the
+                 *    clock stays on until the proper driver comes along
+                 */
+                .flags = CLK_IS_CRITICAL,
+        },
+};
+
 /* Datasheet names this field as "premux0" */
 static struct clk_regmap g12a_cpu_clk_premux0 = {
         .data = &(struct clk_regmap_mux_data){
@@ -266,26 +346,61 @@ static struct clk_regmap g12a_cpu_clk_premux0 = {
         },
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk_dyn0_sel",
-                .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal",
-                                                  "fclk_div2",
-                                                  "fclk_div3" },
+                .ops = &clk_regmap_mux_ops,
+                .parent_data = (const struct clk_parent_data []) {
+                        { .fw_name = "xtal", },
+                        { .hw = &g12a_fclk_div2.hw },
+                        { .hw = &g12a_fclk_div3.hw },
+                },
+                .num_parents = 3,
+                /* This sub-tree is used a parking clock */
+                .flags = CLK_SET_RATE_NO_REPARENT,
+        },
+};
+
+/* Datasheet names this field as "premux1" */
+static struct clk_regmap g12a_cpu_clk_premux1 = {
+        .data = &(struct clk_regmap_mux_data){
+                .offset = HHI_SYS_CPU_CLK_CNTL0,
+                .mask = 0x3,
+                .shift = 16,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "cpu_clk_dyn1_sel",
+                .ops = &clk_regmap_mux_ops,
+                .parent_data = (const struct clk_parent_data []) {
+                        { .fw_name = "xtal", },
+                        { .hw = &g12a_fclk_div2.hw },
+                        { .hw = &g12a_fclk_div3.hw },
+                },
                 .num_parents = 3,
+                /* This sub-tree is used a parking clock */
+                .flags = CLK_SET_RATE_NO_REPARENT
         },
 };
 
 /* Datasheet names this field as "mux0_divn_tcnt" */
 static struct clk_regmap g12a_cpu_clk_mux0_div = {
-        .data = &(struct clk_regmap_div_data){
-                .offset = HHI_SYS_CPU_CLK_CNTL0,
-                .shift = 4,
-                .width = 6,
+        .data = &(struct meson_clk_cpu_dyndiv_data){
+                .div = {
+                        .reg_off = HHI_SYS_CPU_CLK_CNTL0,
+                        .shift = 4,
+                        .width = 6,
+                },
+                .dyn = {
+                        .reg_off = HHI_SYS_CPU_CLK_CNTL0,
+                        .shift = 26,
+                        .width = 1,
+                },
         },
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk_dyn0_div",
-                .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "cpu_clk_dyn0_sel" },
+                .ops = &meson_clk_cpu_dyndiv_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_cpu_clk_premux0.hw
+                },
                 .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT,
         },
 };
 
@@ -298,27 +413,13 @@ static struct clk_regmap g12a_cpu_clk_postmux0 = {
         },
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk_dyn0",
-                .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ "cpu_clk_dyn0_sel",
-                                                  "cpu_clk_dyn0_div" },
+                .ops = &clk_regmap_mux_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_cpu_clk_premux0.hw,
+                        &g12a_cpu_clk_mux0_div.hw,
+                },
                 .num_parents = 2,
-        },
-};
-
-/* Datasheet names this field as "premux1" */
-static struct clk_regmap g12a_cpu_clk_premux1 = {
-        .data = &(struct clk_regmap_mux_data){
-                .offset = HHI_SYS_CPU_CLK_CNTL0,
-                .mask = 0x3,
-                .shift = 16,
-        },
-        .hw.init = &(struct clk_init_data){
-                .name = "cpu_clk_dyn1_sel",
-                .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal",
-                                                  "fclk_div2",
-                                                  "fclk_div3" },
-                .num_parents = 3,
+                .flags = CLK_SET_RATE_PARENT,
         },
 };
 
@@ -332,7 +433,9 @@ static struct clk_regmap g12a_cpu_clk_mux1_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk_dyn1_div",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "cpu_clk_dyn1_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_cpu_clk_premux1.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -346,10 +449,14 @@ static struct clk_regmap g12a_cpu_clk_postmux1 = {
         },
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk_dyn1",
-                .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ "cpu_clk_dyn1_sel",
-                                                  "cpu_clk_dyn1_div" },
+                .ops = &clk_regmap_mux_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_cpu_clk_premux1.hw,
+                        &g12a_cpu_clk_mux1_div.hw,
+                },
                 .num_parents = 2,
+                /* This sub-tree is used a parking clock */
+                .flags = CLK_SET_RATE_NO_REPARENT,
         },
 };
 
@@ -362,10 +469,13 @@ static struct clk_regmap g12a_cpu_clk_dyn = {
         },
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk_dyn",
-                .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ "cpu_clk_dyn0",
-                                                  "cpu_clk_dyn1" },
+                .ops = &clk_regmap_mux_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_cpu_clk_postmux0.hw,
+                        &g12a_cpu_clk_postmux1.hw,
+                },
                 .num_parents = 2,
+                .flags = CLK_SET_RATE_PARENT,
         },
 };
 
@@ -378,10 +488,13 @@ static struct clk_regmap g12a_cpu_clk = {
         },
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk",
-                .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ "cpu_clk_dyn",
-                                                  "sys_pll" },
+                .ops = &clk_regmap_mux_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_cpu_clk_dyn.hw,
+                        &g12a_sys_pll.hw,
+                },
                 .num_parents = 2,
+                .flags = CLK_SET_RATE_PARENT,
         },
 };
 
@@ -394,10 +507,13 @@ static struct clk_regmap g12b_cpu_clk = {
         },
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk",
-                .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ "cpu_clk_dyn",
-                                                  "sys1_pll" },
+                .ops = &clk_regmap_mux_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_cpu_clk_dyn.hw,
+                        &g12b_sys1_pll.hw
+                },
                 .num_parents = 2,
+                .flags = CLK_SET_RATE_PARENT,
         },
 };
 
@@ -410,26 +526,38 @@ static struct clk_regmap g12b_cpub_clk_premux0 = {
         },
         .hw.init = &(struct clk_init_data){
                 .name = "cpub_clk_dyn0_sel",
-                .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal",
-                                                  "fclk_div2",
-                                                  "fclk_div3" },
+                .ops = &clk_regmap_mux_ops,
+                .parent_data = (const struct clk_parent_data []) {
+                        { .fw_name = "xtal", },
+                        { .hw = &g12a_fclk_div2.hw },
+                        { .hw = &g12a_fclk_div3.hw },
+                },
                 .num_parents = 3,
         },
 };
 
 /* Datasheet names this field as "mux0_divn_tcnt" */
 static struct clk_regmap g12b_cpub_clk_mux0_div = {
-        .data = &(struct clk_regmap_div_data){
-                .offset = HHI_SYS_CPUB_CLK_CNTL,
-                .shift = 4,
-                .width = 6,
+        .data = &(struct meson_clk_cpu_dyndiv_data){
+                .div = {
+                        .reg_off = HHI_SYS_CPUB_CLK_CNTL,
+                        .shift = 4,
+                        .width = 6,
+                },
+                .dyn = {
+                        .reg_off = HHI_SYS_CPUB_CLK_CNTL,
+                        .shift = 26,
+                        .width = 1,
+                },
         },
         .hw.init = &(struct clk_init_data){
                 .name = "cpub_clk_dyn0_div",
-                .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "cpub_clk_dyn0_sel" },
+                .ops = &meson_clk_cpu_dyndiv_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk_premux0.hw
+                },
                 .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT,
         },
 };
 
@@ -442,10 +570,13 @@ static struct clk_regmap g12b_cpub_clk_postmux0 = {
         },
         .hw.init = &(struct clk_init_data){
                 .name = "cpub_clk_dyn0",
-                .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ "cpub_clk_dyn0_sel",
-                                                  "cpub_clk_dyn0_div" },
+                .ops = &clk_regmap_mux_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk_premux0.hw,
+                        &g12b_cpub_clk_mux0_div.hw
+                },
                 .num_parents = 2,
+                .flags = CLK_SET_RATE_PARENT,
         },
 };
 
@@ -458,11 +589,15 @@ static struct clk_regmap g12b_cpub_clk_premux1 = {
         },
         .hw.init = &(struct clk_init_data){
                 .name = "cpub_clk_dyn1_sel",
-                .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal",
-                                                  "fclk_div2",
-                                                  "fclk_div3" },
+                .ops = &clk_regmap_mux_ops,
+                .parent_data = (const struct clk_parent_data []) {
+                        { .fw_name = "xtal", },
+                        { .hw = &g12a_fclk_div2.hw },
+                        { .hw = &g12a_fclk_div3.hw },
+                },
                 .num_parents = 3,
+                /* This sub-tree is used a parking clock */
+                .flags = CLK_SET_RATE_NO_REPARENT,
         },
 };
 
@@ -476,7 +611,9 @@ static struct clk_regmap g12b_cpub_clk_mux1_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpub_clk_dyn1_div",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "cpub_clk_dyn1_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk_premux1.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -490,10 +627,14 @@ static struct clk_regmap g12b_cpub_clk_postmux1 = {
         },
         .hw.init = &(struct clk_init_data){
                 .name = "cpub_clk_dyn1",
-                .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ "cpub_clk_dyn1_sel",
-                                                  "cpub_clk_dyn1_div" },
+                .ops = &clk_regmap_mux_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk_premux1.hw,
+                        &g12b_cpub_clk_mux1_div.hw
+                },
                 .num_parents = 2,
+                /* This sub-tree is used a parking clock */
+                .flags = CLK_SET_RATE_NO_REPARENT,
         },
 };
 
@@ -506,10 +647,13 @@ static struct clk_regmap g12b_cpub_clk_dyn = {
         },
         .hw.init = &(struct clk_init_data){
                 .name = "cpub_clk_dyn",
-                .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ "cpub_clk_dyn0",
-                                                  "cpub_clk_dyn1" },
+                .ops = &clk_regmap_mux_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk_postmux0.hw,
+                        &g12b_cpub_clk_postmux1.hw
+                },
                 .num_parents = 2,
+                .flags = CLK_SET_RATE_PARENT,
         },
 };
 
@@ -522,13 +666,447 @@ static struct clk_regmap g12b_cpub_clk = {
         },
         .hw.init = &(struct clk_init_data){
                 .name = "cpub_clk",
+                .ops = &clk_regmap_mux_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk_dyn.hw,
+                        &g12a_sys_pll.hw
+                },
+                .num_parents = 2,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
+static struct clk_regmap sm1_gp1_pll;
+
+/* Datasheet names this field as "premux0" */
+static struct clk_regmap sm1_dsu_clk_premux0 = {
+        .data = &(struct clk_regmap_mux_data){
+                .offset = HHI_SYS_CPU_CLK_CNTL5,
+                .mask = 0x3,
+                .shift = 0,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "dsu_clk_dyn0_sel",
+                .ops = &clk_regmap_mux_ro_ops,
+                .parent_data = (const struct clk_parent_data []) {
+                        { .fw_name = "xtal", },
+                        { .hw = &g12a_fclk_div2.hw },
+                        { .hw = &g12a_fclk_div3.hw },
+                        { .hw = &sm1_gp1_pll.hw },
+                },
+                .num_parents = 4,
+        },
+};
+
+/* Datasheet names this field as "premux1" */
+static struct clk_regmap sm1_dsu_clk_premux1 = {
+        .data = &(struct clk_regmap_mux_data){
+                .offset = HHI_SYS_CPU_CLK_CNTL5,
+                .mask = 0x3,
+                .shift = 16,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "dsu_clk_dyn1_sel",
                 .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ "cpub_clk_dyn",
-                                                  "sys_pll" },
+                .parent_data = (const struct clk_parent_data []) {
+                        { .fw_name = "xtal", },
+                        { .hw = &g12a_fclk_div2.hw },
+                        { .hw = &g12a_fclk_div3.hw },
+                        { .hw = &sm1_gp1_pll.hw },
+                },
+                .num_parents = 4,
+        },
+};
+
+/* Datasheet names this field as "Mux0_divn_tcnt" */
+static struct clk_regmap sm1_dsu_clk_mux0_div = {
+        .data = &(struct clk_regmap_div_data){
+                .offset = HHI_SYS_CPU_CLK_CNTL5,
+                .shift = 4,
+                .width = 6,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "dsu_clk_dyn0_div",
+                .ops = &clk_regmap_divider_ro_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &sm1_dsu_clk_premux0.hw
+                },
+                .num_parents = 1,
+        },
+};
+
+/* Datasheet names this field as "postmux0" */
+static struct clk_regmap sm1_dsu_clk_postmux0 = {
+        .data = &(struct clk_regmap_mux_data){
+                .offset = HHI_SYS_CPU_CLK_CNTL5,
+                .mask = 0x1,
+                .shift = 2,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "dsu_clk_dyn0",
+                .ops = &clk_regmap_mux_ro_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &sm1_dsu_clk_premux0.hw,
+                        &sm1_dsu_clk_mux0_div.hw,
+                },
                 .num_parents = 2,
         },
 };
 
+/* Datasheet names this field as "Mux1_divn_tcnt" */
+static struct clk_regmap sm1_dsu_clk_mux1_div = {
+        .data = &(struct clk_regmap_div_data){
+                .offset = HHI_SYS_CPU_CLK_CNTL5,
+                .shift = 20,
+                .width = 6,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "dsu_clk_dyn1_div",
+                .ops = &clk_regmap_divider_ro_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &sm1_dsu_clk_premux1.hw
+                },
+                .num_parents = 1,
+        },
+};
+
+/* Datasheet names this field as "postmux1" */
+static struct clk_regmap sm1_dsu_clk_postmux1 = {
+        .data = &(struct clk_regmap_mux_data){
+                .offset = HHI_SYS_CPU_CLK_CNTL5,
+                .mask = 0x1,
+                .shift = 18,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "dsu_clk_dyn1",
+                .ops = &clk_regmap_mux_ro_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &sm1_dsu_clk_premux1.hw,
+                        &sm1_dsu_clk_mux1_div.hw,
+                },
+                .num_parents = 2,
+        },
+};
+
+/* Datasheet names this field as "Final_dyn_mux_sel" */
+static struct clk_regmap sm1_dsu_clk_dyn = {
+        .data = &(struct clk_regmap_mux_data){
+                .offset = HHI_SYS_CPU_CLK_CNTL5,
+                .mask = 0x1,
+                .shift = 10,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "dsu_clk_dyn",
+                .ops = &clk_regmap_mux_ro_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &sm1_dsu_clk_postmux0.hw,
+                        &sm1_dsu_clk_postmux1.hw,
+                },
+                .num_parents = 2,
+        },
+};
+
+/* Datasheet names this field as "Final_mux_sel" */
+static struct clk_regmap sm1_dsu_final_clk = {
+        .data = &(struct clk_regmap_mux_data){
+                .offset = HHI_SYS_CPU_CLK_CNTL5,
+                .mask = 0x1,
+                .shift = 11,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "dsu_clk_final",
+                .ops = &clk_regmap_mux_ro_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &sm1_dsu_clk_dyn.hw,
+                        &g12a_sys_pll.hw,
+                },
+                .num_parents = 2,
+        },
+};
+
+/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 0 */
+static struct clk_regmap sm1_cpu1_clk = {
+        .data = &(struct clk_regmap_mux_data){
+                .offset = HHI_SYS_CPU_CLK_CNTL6,
+                .mask = 0x1,
+                .shift = 24,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "cpu1_clk",
+                .ops = &clk_regmap_mux_ro_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_cpu_clk.hw,
+                        /* This CPU also have a dedicated clock tree */
+                },
+                .num_parents = 1,
+        },
+};
+
+/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 1 */
+static struct clk_regmap sm1_cpu2_clk = {
+        .data = &(struct clk_regmap_mux_data){
+                .offset = HHI_SYS_CPU_CLK_CNTL6,
+                .mask = 0x1,
+                .shift = 25,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "cpu2_clk",
+                .ops = &clk_regmap_mux_ro_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_cpu_clk.hw,
+                        /* This CPU also have a dedicated clock tree */
+                },
+                .num_parents = 1,
+        },
+};
+
+/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 2 */
+static struct clk_regmap sm1_cpu3_clk = {
+        .data = &(struct clk_regmap_mux_data){
+                .offset = HHI_SYS_CPU_CLK_CNTL6,
+                .mask = 0x1,
+                .shift = 26,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "cpu3_clk",
+                .ops = &clk_regmap_mux_ro_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_cpu_clk.hw,
+                        /* This CPU also have a dedicated clock tree */
+                },
+                .num_parents = 1,
+        },
+};
+
+/* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */
+static struct clk_regmap sm1_dsu_clk = {
+        .data = &(struct clk_regmap_mux_data){
+                .offset = HHI_SYS_CPU_CLK_CNTL6,
+                .mask = 0x1,
+                .shift = 27,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "dsu_clk",
+                .ops = &clk_regmap_mux_ro_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_cpu_clk.hw,
+                        &sm1_dsu_final_clk.hw,
+                },
+                .num_parents = 2,
+        },
+};
+
+static int g12a_cpu_clk_mux_notifier_cb(struct notifier_block *nb,
+                                        unsigned long event, void *data)
+{
+        if (event == POST_RATE_CHANGE || event == PRE_RATE_CHANGE) {
+                /* Wait for clock propagation before/after changing the mux */
+                udelay(100);
+                return NOTIFY_OK;
+        }
+
+        return NOTIFY_DONE;
+}
+
+static struct notifier_block g12a_cpu_clk_mux_nb = {
+        .notifier_call = g12a_cpu_clk_mux_notifier_cb,
+};
+
+struct g12a_cpu_clk_postmux_nb_data {
+        struct notifier_block nb;
+        struct clk_hw *xtal;
+        struct clk_hw *cpu_clk_dyn;
+        struct clk_hw *cpu_clk_postmux0;
+        struct clk_hw *cpu_clk_postmux1;
+        struct clk_hw *cpu_clk_premux1;
+};
+
+static int g12a_cpu_clk_postmux_notifier_cb(struct notifier_block *nb,
+                                            unsigned long event, void *data)
+{
+        struct g12a_cpu_clk_postmux_nb_data *nb_data =
+                container_of(nb, struct g12a_cpu_clk_postmux_nb_data, nb);
+
+        switch (event) {
+        case PRE_RATE_CHANGE:
+                /*
+                 * This notifier means cpu_clk_postmux0 clock will be changed
+                 * to feed cpu_clk, this is the current path :
+                 * cpu_clk
+                 *    \- cpu_clk_dyn
+                 *          \- cpu_clk_postmux0
+                 *                \- cpu_clk_muxX_div
+                 *                      \- cpu_clk_premux0
+                 *                              \- fclk_div3 or fclk_div2
+                 *              OR
+                 *                \- cpu_clk_premux0
+                 *                      \- fclk_div3 or fclk_div2
+                 */
+
+                /* Setup cpu_clk_premux1 to xtal */
+                clk_hw_set_parent(nb_data->cpu_clk_premux1,
+                                  nb_data->xtal);
+
+                /* Setup cpu_clk_postmux1 to bypass divider */
+                clk_hw_set_parent(nb_data->cpu_clk_postmux1,
+                                  nb_data->cpu_clk_premux1);
+
+                /* Switch to parking clk on cpu_clk_postmux1 */
+                clk_hw_set_parent(nb_data->cpu_clk_dyn,
+                                  nb_data->cpu_clk_postmux1);
+
+                /*
+                 * Now, cpu_clk is 24MHz in the current path :
+                 * cpu_clk
+                 *    \- cpu_clk_dyn
+                 *          \- cpu_clk_postmux1
+                 *                \- cpu_clk_premux1
+                 *                      \- xtal
+                 */
+
+                udelay(100);
+
+                return NOTIFY_OK;
+
+        case POST_RATE_CHANGE:
+                /*
+                 * The cpu_clk_postmux0 has ben updated, now switch back
+                 * cpu_clk_dyn to cpu_clk_postmux0 and take the changes
+                 * in account.
+                 */
+
+                /* Configure cpu_clk_dyn back to cpu_clk_postmux0 */
+                clk_hw_set_parent(nb_data->cpu_clk_dyn,
+                                  nb_data->cpu_clk_postmux0);
+
+                /*
+                 * new path :
+                 * cpu_clk
+                 *    \- cpu_clk_dyn
+                 *          \- cpu_clk_postmux0
+                 *                \- cpu_clk_muxX_div
+                 *                      \- cpu_clk_premux0
+                 *                              \- fclk_div3 or fclk_div2
+                 *              OR
+                 *                \- cpu_clk_premux0
+                 *                      \- fclk_div3 or fclk_div2
+                 */
+
+                udelay(100);
+
+                return NOTIFY_OK;
+
+        default:
+                return NOTIFY_DONE;
+        }
+}
+
+static struct g12a_cpu_clk_postmux_nb_data g12a_cpu_clk_postmux0_nb_data = {
+        .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
+        .cpu_clk_postmux0 = &g12a_cpu_clk_postmux0.hw,
+        .cpu_clk_postmux1 = &g12a_cpu_clk_postmux1.hw,
+        .cpu_clk_premux1 = &g12a_cpu_clk_premux1.hw,
+        .nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
+};
+
+static struct g12a_cpu_clk_postmux_nb_data g12b_cpub_clk_postmux0_nb_data = {
+        .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
+        .cpu_clk_postmux0 = &g12b_cpub_clk_postmux0.hw,
+        .cpu_clk_postmux1 = &g12b_cpub_clk_postmux1.hw,
+        .cpu_clk_premux1 = &g12b_cpub_clk_premux1.hw,
+        .nb.notifier_call = g12a_cpu_clk_postmux_notifier_cb,
+};
+
+struct g12a_sys_pll_nb_data {
+        struct notifier_block nb;
+        struct clk_hw *sys_pll;
+        struct clk_hw *cpu_clk;
+        struct clk_hw *cpu_clk_dyn;
+};
+
+static int g12a_sys_pll_notifier_cb(struct notifier_block *nb,
+                                    unsigned long event, void *data)
+{
+        struct g12a_sys_pll_nb_data *nb_data =
+                container_of(nb, struct g12a_sys_pll_nb_data, nb);
+
+        switch (event) {
+        case PRE_RATE_CHANGE:
+                /*
+                 * This notifier means sys_pll clock will be changed
+                 * to feed cpu_clk, this the current path :
+                 * cpu_clk
+                 *    \- sys_pll
+                 *          \- sys_pll_dco
+                 */
+
+                /* Configure cpu_clk to use cpu_clk_dyn */
+                clk_hw_set_parent(nb_data->cpu_clk,
+                                  nb_data->cpu_clk_dyn);
+
+                /*
+                 * Now, cpu_clk uses the dyn path
+                 * cpu_clk
+                 *    \- cpu_clk_dyn
+                 *          \- cpu_clk_dynX
+                 *                \- cpu_clk_dynX_sel
+                 *                   \- cpu_clk_dynX_div
+                 *                      \- xtal/fclk_div2/fclk_div3
+                 *                   \- xtal/fclk_div2/fclk_div3
+                 */
+
+                udelay(100);
+
+                return NOTIFY_OK;
+
+        case POST_RATE_CHANGE:
+                /*
+                 * The sys_pll has ben updated, now switch back cpu_clk to
+                 * sys_pll
+                 */
+
+                /* Configure cpu_clk to use sys_pll */
+                clk_hw_set_parent(nb_data->cpu_clk,
+                                  nb_data->sys_pll);
+
+                udelay(100);
+
+                /* new path :
+                 * cpu_clk
+                 *    \- sys_pll
+                 *          \- sys_pll_dco
+                 */
+
+                return NOTIFY_OK;
+
+        default:
+                return NOTIFY_DONE;
+        }
+}
+
+static struct g12a_sys_pll_nb_data g12a_sys_pll_nb_data = {
+        .sys_pll = &g12a_sys_pll.hw,
+        .cpu_clk = &g12a_cpu_clk.hw,
+        .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
+        .nb.notifier_call = g12a_sys_pll_notifier_cb,
+};
+
+/* G12B first CPU cluster uses sys1_pll */
+static struct g12a_sys_pll_nb_data g12b_cpu_clk_sys1_pll_nb_data = {
+        .sys_pll = &g12b_sys1_pll.hw,
+        .cpu_clk = &g12b_cpu_clk.hw,
+        .cpu_clk_dyn = &g12a_cpu_clk_dyn.hw,
+        .nb.notifier_call = g12a_sys_pll_notifier_cb,
+};
+
+/* G12B second CPU cluster uses sys_pll */
+static struct g12a_sys_pll_nb_data g12b_cpub_clk_sys_pll_nb_data = {
+        .sys_pll = &g12a_sys_pll.hw,
+        .cpu_clk = &g12b_cpub_clk.hw,
+        .cpu_clk_dyn = &g12b_cpub_clk_dyn.hw,
+        .nb.notifier_call = g12a_sys_pll_notifier_cb,
+};
+
 static struct clk_regmap g12a_cpu_clk_div16_en = {
         .data = &(struct clk_regmap_gate_data){
                 .offset = HHI_SYS_CPU_CLK_CNTL1,
@@ -537,7 +1115,9 @@ static struct clk_regmap g12a_cpu_clk_div16_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "cpu_clk_div16_en",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "cpu_clk" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_cpu_clk.hw
+                },
                 .num_parents = 1,
                 /*
                  * This clock is used to debug the cpu_clk range
@@ -554,7 +1134,9 @@ static struct clk_regmap g12b_cpub_clk_div16_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "cpub_clk_div16_en",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "cpub_clk" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk.hw
+                },
                 .num_parents = 1,
                 /*
                  * This clock is used to debug the cpu_clk range
@@ -569,7 +1151,9 @@ static struct clk_fixed_factor g12a_cpu_clk_div16 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk_div16",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "cpu_clk_div16_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_cpu_clk_div16_en.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -580,7 +1164,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div16 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpub_clk_div16",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "cpub_clk_div16_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk_div16_en.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -595,7 +1181,7 @@ static struct clk_regmap g12a_cpu_clk_apb_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk_apb_div",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "cpu_clk" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
                 .num_parents = 1,
         },
 };
@@ -608,7 +1194,9 @@ static struct clk_regmap g12a_cpu_clk_apb = {
         .hw.init = &(struct clk_init_data) {
                 .name = "cpu_clk_apb",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "cpu_clk_apb_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_cpu_clk_apb_div.hw
+                },
                 .num_parents = 1,
                 /*
                  * This clock is set by the ROM monitor code,
@@ -627,7 +1215,7 @@ static struct clk_regmap g12a_cpu_clk_atb_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk_atb_div",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "cpu_clk" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
                 .num_parents = 1,
         },
 };
@@ -640,7 +1228,9 @@ static struct clk_regmap g12a_cpu_clk_atb = {
         .hw.init = &(struct clk_init_data) {
                 .name = "cpu_clk_atb",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "cpu_clk_atb_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_cpu_clk_atb_div.hw
+                },
                 .num_parents = 1,
                 /*
                  * This clock is set by the ROM monitor code,
@@ -659,7 +1249,7 @@ static struct clk_regmap g12a_cpu_clk_axi_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk_axi_div",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "cpu_clk" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_cpu_clk.hw },
                 .num_parents = 1,
         },
 };
@@ -672,7 +1262,9 @@ static struct clk_regmap g12a_cpu_clk_axi = {
         .hw.init = &(struct clk_init_data) {
                 .name = "cpu_clk_axi",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "cpu_clk_axi_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_cpu_clk_axi_div.hw
+                },
                 .num_parents = 1,
                 /*
                  * This clock is set by the ROM monitor code,
@@ -691,7 +1283,17 @@ static struct clk_regmap g12a_cpu_clk_trace_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk_trace_div",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "cpu_clk" },
+                .parent_data = &(const struct clk_parent_data) {
+                        /*
+                         * Note:
+                         * G12A and G12B have different cpu_clks (with
+                         * different struct clk_hw). We fallback to the global
+                         * naming string mechanism so cpu_clk_trace_div picks
+                         * up the appropriate one.
+                         */
+                        .name = "cpu_clk",
+                        .index = -1,
+                },
                 .num_parents = 1,
         },
 };
@@ -704,7 +1306,9 @@ static struct clk_regmap g12a_cpu_clk_trace = {
         .hw.init = &(struct clk_init_data) {
                 .name = "cpu_clk_trace",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "cpu_clk_trace_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_cpu_clk_trace_div.hw
+                },
                 .num_parents = 1,
                 /*
                  * This clock is set by the ROM monitor code,
@@ -719,7 +1323,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div2 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpub_clk_div2",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "cpub_clk" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -730,7 +1336,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div3 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpub_clk_div3",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "cpub_clk" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -741,7 +1349,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div4 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpub_clk_div4",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "cpub_clk" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -752,7 +1362,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div5 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpub_clk_div5",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "cpub_clk" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -763,7 +1375,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div6 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpub_clk_div6",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "cpub_clk" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -774,7 +1388,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div7 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpub_clk_div7",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "cpub_clk" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -785,7 +1401,9 @@ static struct clk_fixed_factor g12b_cpub_clk_div8 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpub_clk_div8",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "cpub_clk" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -801,13 +1419,15 @@ static struct clk_regmap g12b_cpub_clk_apb_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpub_clk_apb_sel",
                 .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ "cpub_clk_div2",
-                                                  "cpub_clk_div3",
-                                                  "cpub_clk_div4",
-                                                  "cpub_clk_div5",
-                                                  "cpub_clk_div6",
-                                                  "cpub_clk_div7",
-                                                  "cpub_clk_div8" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk_div2.hw,
+                        &g12b_cpub_clk_div3.hw,
+                        &g12b_cpub_clk_div4.hw,
+                        &g12b_cpub_clk_div5.hw,
+                        &g12b_cpub_clk_div6.hw,
+                        &g12b_cpub_clk_div7.hw,
+                        &g12b_cpub_clk_div8.hw
+                },
                 .num_parents = 7,
         },
 };
@@ -821,7 +1441,9 @@ static struct clk_regmap g12b_cpub_clk_apb = {
         .hw.init = &(struct clk_init_data) {
                 .name = "cpub_clk_apb",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "cpub_clk_apb_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk_apb_sel.hw
+                },
                 .num_parents = 1,
                 /*
                  * This clock is set by the ROM monitor code,
@@ -840,13 +1462,15 @@ static struct clk_regmap g12b_cpub_clk_atb_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpub_clk_atb_sel",
                 .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ "cpub_clk_div2",
-                                                  "cpub_clk_div3",
-                                                  "cpub_clk_div4",
-                                                  "cpub_clk_div5",
-                                                  "cpub_clk_div6",
-                                                  "cpub_clk_div7",
-                                                  "cpub_clk_div8" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk_div2.hw,
+                        &g12b_cpub_clk_div3.hw,
+                        &g12b_cpub_clk_div4.hw,
+                        &g12b_cpub_clk_div5.hw,
+                        &g12b_cpub_clk_div6.hw,
+                        &g12b_cpub_clk_div7.hw,
+                        &g12b_cpub_clk_div8.hw
+                },
                 .num_parents = 7,
         },
 };
@@ -860,7 +1484,9 @@ static struct clk_regmap g12b_cpub_clk_atb = {
         .hw.init = &(struct clk_init_data) {
                 .name = "cpub_clk_atb",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "cpub_clk_atb_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk_atb_sel.hw
+                },
                 .num_parents = 1,
                 /*
                  * This clock is set by the ROM monitor code,
@@ -879,13 +1505,15 @@ static struct clk_regmap g12b_cpub_clk_axi_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpub_clk_axi_sel",
                 .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ "cpub_clk_div2",
-                                                  "cpub_clk_div3",
-                                                  "cpub_clk_div4",
-                                                  "cpub_clk_div5",
-                                                  "cpub_clk_div6",
-                                                  "cpub_clk_div7",
-                                                  "cpub_clk_div8" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk_div2.hw,
+                        &g12b_cpub_clk_div3.hw,
+                        &g12b_cpub_clk_div4.hw,
+                        &g12b_cpub_clk_div5.hw,
+                        &g12b_cpub_clk_div6.hw,
+                        &g12b_cpub_clk_div7.hw,
+                        &g12b_cpub_clk_div8.hw
+                },
                 .num_parents = 7,
         },
 };
@@ -899,7 +1527,9 @@ static struct clk_regmap g12b_cpub_clk_axi = {
         .hw.init = &(struct clk_init_data) {
                 .name = "cpub_clk_axi",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "cpub_clk_axi_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk_axi_sel.hw
+                },
                 .num_parents = 1,
                 /*
                  * This clock is set by the ROM monitor code,
@@ -918,13 +1548,15 @@ static struct clk_regmap g12b_cpub_clk_trace_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpub_clk_trace_sel",
                 .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ "cpub_clk_div2",
-                                                  "cpub_clk_div3",
-                                                  "cpub_clk_div4",
-                                                  "cpub_clk_div5",
-                                                  "cpub_clk_div6",
-                                                  "cpub_clk_div7",
-                                                  "cpub_clk_div8" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk_div2.hw,
+                        &g12b_cpub_clk_div3.hw,
+                        &g12b_cpub_clk_div4.hw,
+                        &g12b_cpub_clk_div5.hw,
+                        &g12b_cpub_clk_div6.hw,
+                        &g12b_cpub_clk_div7.hw,
+                        &g12b_cpub_clk_div8.hw
+                },
                 .num_parents = 7,
         },
 };
@@ -938,7 +1570,9 @@ static struct clk_regmap g12b_cpub_clk_trace = {
         .hw.init = &(struct clk_init_data) {
                 .name = "cpub_clk_trace",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "cpub_clk_trace_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12b_cpub_clk_trace_sel.hw
+                },
                 .num_parents = 1,
                 /*
                  * This clock is set by the ROM monitor code,
@@ -1003,7 +1637,9 @@ static struct clk_regmap g12a_gp0_pll_dco = {
         .hw.init = &(struct clk_init_data){
                 .name = "gp0_pll_dco",
                 .ops = &meson_clk_pll_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
         },
 };
@@ -1019,12 +1655,77 @@ static struct clk_regmap g12a_gp0_pll = {
         .hw.init = &(struct clk_init_data){
                 .name = "gp0_pll",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "gp0_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_gp0_pll_dco.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
 
+static struct clk_regmap sm1_gp1_pll_dco = {
+        .data = &(struct meson_clk_pll_data){
+                .en = {
+                        .reg_off = HHI_GP1_PLL_CNTL0,
+                        .shift   = 28,
+                        .width   = 1,
+                },
+                .m = {
+                        .reg_off = HHI_GP1_PLL_CNTL0,
+                        .shift   = 0,
+                        .width   = 8,
+                },
+                .n = {
+                        .reg_off = HHI_GP1_PLL_CNTL0,
+                        .shift   = 10,
+                        .width   = 5,
+                },
+                .frac = {
+                        .reg_off = HHI_GP1_PLL_CNTL1,
+                        .shift   = 0,
+                        .width   = 17,
+                },
+                .l = {
+                        .reg_off = HHI_GP1_PLL_CNTL0,
+                        .shift   = 31,
+                        .width   = 1,
+                },
+                .rst = {
+                        .reg_off = HHI_GP1_PLL_CNTL0,
+                        .shift   = 29,
+                        .width   = 1,
+                },
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "gp1_pll_dco",
+                .ops = &meson_clk_pll_ro_ops,
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
+                .num_parents = 1,
+                /* This clock feeds the DSU, avoid disabling it */
+                .flags = CLK_IS_CRITICAL,
+        },
+};
+
+static struct clk_regmap sm1_gp1_pll = {
+        .data = &(struct clk_regmap_div_data){
+                .offset = HHI_GP1_PLL_CNTL0,
+                .shift = 16,
+                .width = 3,
+                .flags = (CLK_DIVIDER_POWER_OF_TWO |
+                          CLK_DIVIDER_ROUND_CLOSEST),
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "gp1_pll",
+                .ops = &clk_regmap_divider_ro_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &sm1_gp1_pll_dco.hw
+                },
+                .num_parents = 1,
+        },
+};
+
 /*
  * Internal hifi pll emulation configuration parameters
  */
@@ -1077,7 +1778,9 @@ static struct clk_regmap g12a_hifi_pll_dco = {
         .hw.init = &(struct clk_init_data){
                 .name = "hifi_pll_dco",
                 .ops = &meson_clk_pll_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
         },
 };
@@ -1093,7 +1796,9 @@ static struct clk_regmap g12a_hifi_pll = {
         .hw.init = &(struct clk_init_data){
                 .name = "hifi_pll",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "hifi_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_hifi_pll_dco.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1164,7 +1869,9 @@ static struct clk_regmap g12a_pcie_pll_dco = {
         .hw.init = &(struct clk_init_data){
                 .name = "pcie_pll_dco",
                 .ops = &meson_clk_pcie_pll_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
         },
 };
@@ -1175,7 +1882,9 @@ static struct clk_fixed_factor g12a_pcie_pll_dco_div2 = {
         .hw.init = &(struct clk_init_data){
                 .name = "pcie_pll_dco_div2",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "pcie_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_pcie_pll_dco.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1193,7 +1902,9 @@ static struct clk_regmap g12a_pcie_pll_od = {
         .hw.init = &(struct clk_init_data){
                 .name = "pcie_pll_od",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "pcie_pll_dco_div2" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_pcie_pll_dco_div2.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1205,7 +1916,9 @@ static struct clk_fixed_factor g12a_pcie_pll = {
         .hw.init = &(struct clk_init_data){
                 .name = "pcie_pll_pll",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "pcie_pll_od" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_pcie_pll_od.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1247,7 +1960,9 @@ static struct clk_regmap g12a_hdmi_pll_dco = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_pll_dco",
                 .ops = &meson_clk_pll_ro_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
                 /*
                  * Display directly handle hdmi pll registers ATM, we need
@@ -1267,7 +1982,9 @@ static struct clk_regmap g12a_hdmi_pll_od = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_pll_od",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "hdmi_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_hdmi_pll_dco.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
         },
@@ -1283,7 +2000,9 @@ static struct clk_regmap g12a_hdmi_pll_od2 = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_pll_od2",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "hdmi_pll_od" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_hdmi_pll_od.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
         },
@@ -1299,77 +2018,21 @@ static struct clk_regmap g12a_hdmi_pll = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_pll",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "hdmi_pll_od2" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_hdmi_pll_od2.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
         },
 };
 
-static struct clk_fixed_factor g12a_fclk_div2_div = {
-        .mult = 1,
-        .div = 2,
-        .hw.init = &(struct clk_init_data){
-                .name = "fclk_div2_div",
-                .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
-                .num_parents = 1,
-        },
-};
-
-static struct clk_regmap g12a_fclk_div2 = {
-        .data = &(struct clk_regmap_gate_data){
-                .offset = HHI_FIX_PLL_CNTL1,
-                .bit_idx = 24,
-        },
-        .hw.init = &(struct clk_init_data){
-                .name = "fclk_div2",
-                .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div2_div" },
-                .num_parents = 1,
-        },
-};
-
-static struct clk_fixed_factor g12a_fclk_div3_div = {
-        .mult = 1,
-        .div = 3,
-        .hw.init = &(struct clk_init_data){
-                .name = "fclk_div3_div",
-                .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
-                .num_parents = 1,
-        },
-};
-
-static struct clk_regmap g12a_fclk_div3 = {
-        .data = &(struct clk_regmap_gate_data){
-                .offset = HHI_FIX_PLL_CNTL1,
-                .bit_idx = 20,
-        },
-        .hw.init = &(struct clk_init_data){
-                .name = "fclk_div3",
-                .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div3_div" },
-                .num_parents = 1,
-                /*
-                 * This clock is used by the resident firmware and is required
-                 * by the platform to operate correctly.
-                 * Until the following condition are met, we need this clock to
-                 * be marked as critical:
-                 * a) Mark the clock used by a firmware resource, if possible
-                 * b) CCF has a clock hand-off mechanism to make the sure the
-                 *    clock stays on until the proper driver comes along
-                 */
-                .flags = CLK_IS_CRITICAL,
-        },
-};
-
 static struct clk_fixed_factor g12a_fclk_div4_div = {
         .mult = 1,
         .div = 4,
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div4_div",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
                 .num_parents = 1,
         },
 };
@@ -1382,7 +2045,9 @@ static struct clk_regmap g12a_fclk_div4 = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div4",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div4_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_fclk_div4_div.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -1393,7 +2058,7 @@ static struct clk_fixed_factor g12a_fclk_div5_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div5_div",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
                 .num_parents = 1,
         },
 };
@@ -1406,7 +2071,9 @@ static struct clk_regmap g12a_fclk_div5 = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div5",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div5_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_fclk_div5_div.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -1417,7 +2084,7 @@ static struct clk_fixed_factor g12a_fclk_div7_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div7_div",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_fixed_pll.hw },
                 .num_parents = 1,
         },
 };
@@ -1430,7 +2097,9 @@ static struct clk_regmap g12a_fclk_div7 = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div7",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div7_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_fclk_div7_div.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -1441,7 +2110,9 @@ static struct clk_fixed_factor g12a_fclk_div2p5_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div2p5_div",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_fixed_pll_dco.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -1454,7 +2125,9 @@ static struct clk_regmap g12a_fclk_div2p5 = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div2p5",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div2p5_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_fclk_div2p5_div.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -1465,7 +2138,9 @@ static struct clk_fixed_factor g12a_mpll_50m_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll_50m_div",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_fixed_pll_dco.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -1479,8 +2154,10 @@ static struct clk_regmap g12a_mpll_50m = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll_50m",
                 .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal",
-                                                  "mpll_50m_div" },
+                .parent_data = (const struct clk_parent_data []) {
+                        { .fw_name = "xtal", },
+                        { .hw = &g12a_mpll_50m_div.hw },
+                },
                 .num_parents = 2,
         },
 };
@@ -1491,7 +2168,9 @@ static struct clk_fixed_factor g12a_mpll_prediv = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll_prediv",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_fixed_pll_dco.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -1529,7 +2208,9 @@ static struct clk_regmap g12a_mpll0_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll0_div",
                 .ops = &meson_clk_mpll_ops,
-                .parent_names = (const char *[]){ "mpll_prediv" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_mpll_prediv.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -1542,7 +2223,7 @@ static struct clk_regmap g12a_mpll0 = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mpll0_div" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_mpll0_div.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1581,7 +2262,9 @@ static struct clk_regmap g12a_mpll1_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll1_div",
                 .ops = &meson_clk_mpll_ops,
-                .parent_names = (const char *[]){ "mpll_prediv" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_mpll_prediv.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -1594,7 +2277,7 @@ static struct clk_regmap g12a_mpll1 = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll1",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mpll1_div" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_mpll1_div.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1633,7 +2316,9 @@ static struct clk_regmap g12a_mpll2_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll2_div",
                 .ops = &meson_clk_mpll_ops,
-                .parent_names = (const char *[]){ "mpll_prediv" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_mpll_prediv.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -1646,7 +2331,7 @@ static struct clk_regmap g12a_mpll2 = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll2",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mpll2_div" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_mpll2_div.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1685,7 +2370,9 @@ static struct clk_regmap g12a_mpll3_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll3_div",
                 .ops = &meson_clk_mpll_ops,
-                .parent_names = (const char *[]){ "mpll_prediv" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_mpll_prediv.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -1698,16 +2385,21 @@ static struct clk_regmap g12a_mpll3 = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll3",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mpll3_div" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_mpll3_div.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
 
 static u32 mux_table_clk81[]    = { 0, 2, 3, 4, 5, 6, 7 };
-static const char * const clk81_parent_names[] = {
-        IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
-        "fclk_div3", "fclk_div5"
+static const struct clk_parent_data clk81_parent_data[] = {
+        { .fw_name = "xtal", },
+        { .hw = &g12a_fclk_div7.hw },
+        { .hw = &g12a_mpll1.hw },
+        { .hw = &g12a_mpll2.hw },
+        { .hw = &g12a_fclk_div4.hw },
+        { .hw = &g12a_fclk_div3.hw },
+        { .hw = &g12a_fclk_div5.hw },
 };
 
 static struct clk_regmap g12a_mpeg_clk_sel = {
@@ -1720,8 +2412,8 @@ static struct clk_regmap g12a_mpeg_clk_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpeg_clk_sel",
                 .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = clk81_parent_names,
-                .num_parents = ARRAY_SIZE(clk81_parent_names),
+                .parent_data = clk81_parent_data,
+                .num_parents = ARRAY_SIZE(clk81_parent_data),
         },
 };
 
@@ -1734,7 +2426,9 @@ static struct clk_regmap g12a_mpeg_clk_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpeg_clk_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "mpeg_clk_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_mpeg_clk_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1748,15 +2442,20 @@ static struct clk_regmap g12a_clk81 = {
         .hw.init = &(struct clk_init_data){
                 .name = "clk81",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mpeg_clk_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_mpeg_clk_div.hw
+                },
                 .num_parents = 1,
                 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
         },
 };
 
-static const char * const g12a_sd_emmc_clk0_parent_names[] = {
-        IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
-
+static const struct clk_parent_data g12a_sd_emmc_clk0_parent_data[] = {
+        { .fw_name = "xtal", },
+        { .hw = &g12a_fclk_div2.hw },
+        { .hw = &g12a_fclk_div3.hw },
+        { .hw = &g12a_fclk_div5.hw },
+        { .hw = &g12a_fclk_div7.hw },
         /*
          * Following these parent clocks, we should also have had mpll2, mpll3
          * and gp0_pll but these clocks are too precious to be used here. All
@@ -1775,8 +2474,8 @@ static struct clk_regmap g12a_sd_emmc_a_clk0_sel = {
         .hw.init = &(struct clk_init_data) {
                 .name = "sd_emmc_a_clk0_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = g12a_sd_emmc_clk0_parent_names,
-                .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names),
+                .parent_data = g12a_sd_emmc_clk0_parent_data,
+                .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -1790,7 +2489,9 @@ static struct clk_regmap g12a_sd_emmc_a_clk0_div = {
         .hw.init = &(struct clk_init_data) {
                 .name = "sd_emmc_a_clk0_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_sd_emmc_a_clk0_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1804,7 +2505,9 @@ static struct clk_regmap g12a_sd_emmc_a_clk0 = {
         .hw.init = &(struct clk_init_data){
                 .name = "sd_emmc_a_clk0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_sd_emmc_a_clk0_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1820,8 +2523,8 @@ static struct clk_regmap g12a_sd_emmc_b_clk0_sel = {
         .hw.init = &(struct clk_init_data) {
                 .name = "sd_emmc_b_clk0_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = g12a_sd_emmc_clk0_parent_names,
-                .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names),
+                .parent_data = g12a_sd_emmc_clk0_parent_data,
+                .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -1835,7 +2538,9 @@ static struct clk_regmap g12a_sd_emmc_b_clk0_div = {
         .hw.init = &(struct clk_init_data) {
                 .name = "sd_emmc_b_clk0_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_sd_emmc_b_clk0_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1849,7 +2554,9 @@ static struct clk_regmap g12a_sd_emmc_b_clk0 = {
         .hw.init = &(struct clk_init_data){
                 .name = "sd_emmc_b_clk0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_sd_emmc_b_clk0_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1865,8 +2572,8 @@ static struct clk_regmap g12a_sd_emmc_c_clk0_sel = {
         .hw.init = &(struct clk_init_data) {
                 .name = "sd_emmc_c_clk0_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = g12a_sd_emmc_clk0_parent_names,
-                .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_names),
+                .parent_data = g12a_sd_emmc_clk0_parent_data,
+                .num_parents = ARRAY_SIZE(g12a_sd_emmc_clk0_parent_data),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -1880,7 +2587,9 @@ static struct clk_regmap g12a_sd_emmc_c_clk0_div = {
         .hw.init = &(struct clk_init_data) {
                 .name = "sd_emmc_c_clk0_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_sd_emmc_c_clk0_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1894,17 +2603,89 @@ static struct clk_regmap g12a_sd_emmc_c_clk0 = {
         .hw.init = &(struct clk_init_data){
                 .name = "sd_emmc_c_clk0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_sd_emmc_c_clk0_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
 
+/* Video Clocks */
+
+static struct clk_regmap g12a_vid_pll_div = {
+        .data = &(struct meson_vid_pll_div_data){
+                .val = {
+                        .reg_off = HHI_VID_PLL_CLK_DIV,
+                        .shift   = 0,
+                        .width   = 15,
+                },
+                .sel = {
+                        .reg_off = HHI_VID_PLL_CLK_DIV,
+                        .shift   = 16,
+                        .width   = 2,
+                },
+        },
+        .hw.init = &(struct clk_init_data) {
+                .name = "vid_pll_div",
+                .ops = &meson_vid_pll_div_ro_ops,
+                .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_pll.hw },
+                .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+        },
+};
+
+static const struct clk_hw *g12a_vid_pll_parent_hws[] = {
+        &g12a_vid_pll_div.hw,
+        &g12a_hdmi_pll.hw,
+};
+
+static struct clk_regmap g12a_vid_pll_sel = {
+        .data = &(struct clk_regmap_mux_data){
+                .offset = HHI_VID_PLL_CLK_DIV,
+                .mask = 0x1,
+                .shift = 18,
+        },
+        .hw.init = &(struct clk_init_data){
+                .name = "vid_pll_sel",
+                .ops = &clk_regmap_mux_ops,
+                /*
+                 * bit 18 selects from 2 possible parents:
+                 * vid_pll_div or hdmi_pll
+                 */
+                .parent_hws = g12a_vid_pll_parent_hws,
+                .num_parents = ARRAY_SIZE(g12a_vid_pll_parent_hws),
+                .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
+        },
+};
+
+static struct clk_regmap g12a_vid_pll = {
+        .data = &(struct clk_regmap_gate_data){
+                .offset = HHI_VID_PLL_CLK_DIV,
+                .bit_idx = 19,
+        },
+        .hw.init = &(struct clk_init_data) {
+                .name = "vid_pll",
+                .ops = &clk_regmap_gate_ops,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vid_pll_sel.hw
+                },
+                .num_parents = 1,
+                .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+        },
+};
+
 /* VPU Clock */
 
-static const char * const g12a_vpu_parent_names[] = {
-        "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7",
-        "mpll1", "vid_pll", "hifi_pll", "gp0_pll",
+static const struct clk_hw *g12a_vpu_parent_hws[] = {
+        &g12a_fclk_div3.hw,
+        &g12a_fclk_div4.hw,
+        &g12a_fclk_div5.hw,
+        &g12a_fclk_div7.hw,
+        &g12a_mpll1.hw,
+        &g12a_vid_pll.hw,
+        &g12a_hifi_pll.hw,
+        &g12a_gp0_pll.hw,
 };
 
 static struct clk_regmap g12a_vpu_0_sel = {
@@ -1916,8 +2697,8 @@ static struct clk_regmap g12a_vpu_0_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vpu_0_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = g12a_vpu_parent_names,
-                .num_parents = ARRAY_SIZE(g12a_vpu_parent_names),
+                .parent_hws = g12a_vpu_parent_hws,
+                .num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
 };
@@ -1931,7 +2712,7 @@ static struct clk_regmap g12a_vpu_0_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vpu_0_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vpu_0_sel" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_sel.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1945,7 +2726,7 @@ static struct clk_regmap g12a_vpu_0 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vpu_0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vpu_0_div" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_0_div.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -1960,8 +2741,8 @@ static struct clk_regmap g12a_vpu_1_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vpu_1_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = g12a_vpu_parent_names,
-                .num_parents = ARRAY_SIZE(g12a_vpu_parent_names),
+                .parent_hws = g12a_vpu_parent_hws,
+                .num_parents = ARRAY_SIZE(g12a_vpu_parent_hws),
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
 };
@@ -1975,7 +2756,7 @@ static struct clk_regmap g12a_vpu_1_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vpu_1_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vpu_1_sel" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_sel.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1989,7 +2770,7 @@ static struct clk_regmap g12a_vpu_1 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vpu_1",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vpu_1_div" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_vpu_1_div.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2008,7 +2789,10 @@ static struct clk_regmap g12a_vpu = {
                  * bit 31 selects from 2 possible parents:
                  * vpu_0 or vpu_1
                  */
-                .parent_names = (const char *[]){ "vpu_0", "vpu_1" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vpu_0.hw,
+                        &g12a_vpu_1.hw,
+                },
                 .num_parents = 2,
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
@@ -2016,9 +2800,14 @@ static struct clk_regmap g12a_vpu = {
 
 /* VDEC clocks */
 
-static const char * const g12a_vdec_parent_names[] = {
-        "fclk_div2p5", "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7",
-        "hifi_pll", "gp0_pll",
+static const struct clk_hw *g12a_vdec_parent_hws[] = {
+        &g12a_fclk_div2p5.hw,
+        &g12a_fclk_div3.hw,
+        &g12a_fclk_div4.hw,
+        &g12a_fclk_div5.hw,
+        &g12a_fclk_div7.hw,
+        &g12a_hifi_pll.hw,
+        &g12a_gp0_pll.hw,
 };
 
 static struct clk_regmap g12a_vdec_1_sel = {
@@ -2031,8 +2820,8 @@ static struct clk_regmap g12a_vdec_1_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vdec_1_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = g12a_vdec_parent_names,
-                .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
+                .parent_hws = g12a_vdec_parent_hws,
+                .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -2047,7 +2836,9 @@ static struct clk_regmap g12a_vdec_1_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vdec_1_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vdec_1_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vdec_1_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2061,7 +2852,9 @@ static struct clk_regmap g12a_vdec_1 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vdec_1",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vdec_1_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vdec_1_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2077,8 +2870,8 @@ static struct clk_regmap g12a_vdec_hevcf_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vdec_hevcf_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = g12a_vdec_parent_names,
-                .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
+                .parent_hws = g12a_vdec_parent_hws,
+                .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -2093,7 +2886,9 @@ static struct clk_regmap g12a_vdec_hevcf_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vdec_hevcf_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vdec_hevcf_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vdec_hevcf_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2107,7 +2902,9 @@ static struct clk_regmap g12a_vdec_hevcf = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vdec_hevcf",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vdec_hevcf_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vdec_hevcf_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2123,8 +2920,8 @@ static struct clk_regmap g12a_vdec_hevc_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vdec_hevc_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = g12a_vdec_parent_names,
-                .num_parents = ARRAY_SIZE(g12a_vdec_parent_names),
+                .parent_hws = g12a_vdec_parent_hws,
+                .num_parents = ARRAY_SIZE(g12a_vdec_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -2139,7 +2936,9 @@ static struct clk_regmap g12a_vdec_hevc_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vdec_hevc_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vdec_hevc_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vdec_hevc_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2153,7 +2952,9 @@ static struct clk_regmap g12a_vdec_hevc = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vdec_hevc",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vdec_hevc_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vdec_hevc_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2161,9 +2962,15 @@ static struct clk_regmap g12a_vdec_hevc = {
 
 /* VAPB Clock */
 
-static const char * const g12a_vapb_parent_names[] = {
-        "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7",
-        "mpll1", "vid_pll", "mpll2", "fclk_div2p5",
+static const struct clk_hw *g12a_vapb_parent_hws[] = {
+        &g12a_fclk_div4.hw,
+        &g12a_fclk_div3.hw,
+        &g12a_fclk_div5.hw,
+        &g12a_fclk_div7.hw,
+        &g12a_mpll1.hw,
+        &g12a_vid_pll.hw,
+        &g12a_mpll2.hw,
+        &g12a_fclk_div2p5.hw,
 };
 
 static struct clk_regmap g12a_vapb_0_sel = {
@@ -2175,8 +2982,8 @@ static struct clk_regmap g12a_vapb_0_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vapb_0_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = g12a_vapb_parent_names,
-                .num_parents = ARRAY_SIZE(g12a_vapb_parent_names),
+                .parent_hws = g12a_vapb_parent_hws,
+                .num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
 };
@@ -2190,7 +2997,9 @@ static struct clk_regmap g12a_vapb_0_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vapb_0_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vapb_0_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vapb_0_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2204,7 +3013,9 @@ static struct clk_regmap g12a_vapb_0 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vapb_0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vapb_0_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vapb_0_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2219,8 +3030,8 @@ static struct clk_regmap g12a_vapb_1_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vapb_1_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = g12a_vapb_parent_names,
-                .num_parents = ARRAY_SIZE(g12a_vapb_parent_names),
+                .parent_hws = g12a_vapb_parent_hws,
+                .num_parents = ARRAY_SIZE(g12a_vapb_parent_hws),
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
 };
@@ -2234,7 +3045,9 @@ static struct clk_regmap g12a_vapb_1_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vapb_1_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vapb_1_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vapb_1_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2248,7 +3061,9 @@ static struct clk_regmap g12a_vapb_1 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vapb_1",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vapb_1_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vapb_1_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2267,7 +3082,10 @@ static struct clk_regmap g12a_vapb_sel = {
                  * bit 31 selects from 2 possible parents:
                  * vapb_0 or vapb_1
                  */
-                .parent_names = (const char *[]){ "vapb_0", "vapb_1" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vapb_0.hw,
+                        &g12a_vapb_1.hw,
+                },
                 .num_parents = 2,
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
@@ -2281,75 +3099,21 @@ static struct clk_regmap g12a_vapb = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vapb",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vapb_sel" },
-                .num_parents = 1,
-                .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
-        },
-};
-
-/* Video Clocks */
-
-static struct clk_regmap g12a_vid_pll_div = {
-        .data = &(struct meson_vid_pll_div_data){
-                .val = {
-                        .reg_off = HHI_VID_PLL_CLK_DIV,
-                        .shift   = 0,
-                        .width   = 15,
-                },
-                .sel = {
-                        .reg_off = HHI_VID_PLL_CLK_DIV,
-                        .shift   = 16,
-                        .width   = 2,
-                },
-        },
-        .hw.init = &(struct clk_init_data) {
-                .name = "vid_pll_div",
-                .ops = &meson_vid_pll_div_ro_ops,
-                .parent_names = (const char *[]){ "hdmi_pll" },
-                .num_parents = 1,
-                .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
-        },
-};
-
-static const char * const g12a_vid_pll_parent_names[] = { "vid_pll_div",
-                                                          "hdmi_pll" };
-
-static struct clk_regmap g12a_vid_pll_sel = {
-        .data = &(struct clk_regmap_mux_data){
-                .offset = HHI_VID_PLL_CLK_DIV,
-                .mask = 0x1,
-                .shift = 18,
-        },
-        .hw.init = &(struct clk_init_data){
-                .name = "vid_pll_sel",
-                .ops = &clk_regmap_mux_ops,
-                /*
-                 * bit 18 selects from 2 possible parents:
-                 * vid_pll_div or hdmi_pll
-                 */
-                .parent_names = g12a_vid_pll_parent_names,
-                .num_parents = ARRAY_SIZE(g12a_vid_pll_parent_names),
-                .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
-        },
-};
-
-static struct clk_regmap g12a_vid_pll = {
-        .data = &(struct clk_regmap_gate_data){
-                .offset = HHI_VID_PLL_CLK_DIV,
-                .bit_idx = 19,
-        },
-        .hw.init = &(struct clk_init_data) {
-                .name = "vid_pll",
-                .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vid_pll_sel" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_vapb_sel.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
 };
 
-static const char * const g12a_vclk_parent_names[] = {
-        "vid_pll", "gp0_pll", "hifi_pll", "mpll1", "fclk_div3", "fclk_div4",
-        "fclk_div5", "fclk_div7"
+static const struct clk_hw *g12a_vclk_parent_hws[] = {
+        &g12a_vid_pll.hw,
+        &g12a_gp0_pll.hw,
+        &g12a_hifi_pll.hw,
+        &g12a_mpll1.hw,
+        &g12a_fclk_div3.hw,
+        &g12a_fclk_div4.hw,
+        &g12a_fclk_div5.hw,
+        &g12a_fclk_div7.hw,
 };
 
 static struct clk_regmap g12a_vclk_sel = {
@@ -2361,8 +3125,8 @@ static struct clk_regmap g12a_vclk_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = g12a_vclk_parent_names,
-                .num_parents = ARRAY_SIZE(g12a_vclk_parent_names),
+                .parent_hws = g12a_vclk_parent_hws,
+                .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
         },
 };
@@ -2376,8 +3140,8 @@ static struct clk_regmap g12a_vclk2_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = g12a_vclk_parent_names,
-                .num_parents = ARRAY_SIZE(g12a_vclk_parent_names),
+                .parent_hws = g12a_vclk_parent_hws,
+                .num_parents = ARRAY_SIZE(g12a_vclk_parent_hws),
                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
         },
 };
@@ -2390,7 +3154,7 @@ static struct clk_regmap g12a_vclk_input = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk_input",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk_sel" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_sel.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2404,7 +3168,7 @@ static struct clk_regmap g12a_vclk2_input = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk2_input",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk2_sel" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_sel.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2419,7 +3183,9 @@ static struct clk_regmap g12a_vclk_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vclk_input" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vclk_input.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_GET_RATE_NOCACHE,
         },
@@ -2434,7 +3200,9 @@ static struct clk_regmap g12a_vclk2_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vclk2_input" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vclk2_input.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_GET_RATE_NOCACHE,
         },
@@ -2448,7 +3216,7 @@ static struct clk_regmap g12a_vclk = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk_div" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_vclk_div.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2462,7 +3230,7 @@ static struct clk_regmap g12a_vclk2 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk2",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk2_div" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2_div.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2476,7 +3244,7 @@ static struct clk_regmap g12a_vclk_div1 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk_div1",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2490,7 +3258,7 @@ static struct clk_regmap g12a_vclk_div2_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk_div2_en",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2504,7 +3272,7 @@ static struct clk_regmap g12a_vclk_div4_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk_div4_en",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2518,7 +3286,7 @@ static struct clk_regmap g12a_vclk_div6_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk_div6_en",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2532,7 +3300,7 @@ static struct clk_regmap g12a_vclk_div12_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk_div12_en",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_vclk.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2546,7 +3314,7 @@ static struct clk_regmap g12a_vclk2_div1 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk2_div1",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk2" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2560,7 +3328,7 @@ static struct clk_regmap g12a_vclk2_div2_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk2_div2_en",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk2" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2574,7 +3342,7 @@ static struct clk_regmap g12a_vclk2_div4_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk2_div4_en",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk2" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2588,7 +3356,7 @@ static struct clk_regmap g12a_vclk2_div6_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk2_div6_en",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk2" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2602,7 +3370,7 @@ static struct clk_regmap g12a_vclk2_div12_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk2_div12_en",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk2" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_vclk2.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2614,7 +3382,9 @@ static struct clk_fixed_factor g12a_vclk_div2 = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_div2",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk_div2_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vclk_div2_en.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -2625,7 +3395,9 @@ static struct clk_fixed_factor g12a_vclk_div4 = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_div4",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk_div4_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vclk_div4_en.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -2636,7 +3408,9 @@ static struct clk_fixed_factor g12a_vclk_div6 = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_div6",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk_div6_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vclk_div6_en.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -2647,7 +3421,9 @@ static struct clk_fixed_factor g12a_vclk_div12 = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_div12",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk_div12_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vclk_div12_en.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -2658,7 +3434,9 @@ static struct clk_fixed_factor g12a_vclk2_div2 = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_div2",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk2_div2_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vclk2_div2_en.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -2669,7 +3447,9 @@ static struct clk_fixed_factor g12a_vclk2_div4 = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_div4",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk2_div4_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vclk2_div4_en.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -2680,7 +3460,9 @@ static struct clk_fixed_factor g12a_vclk2_div6 = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_div6",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk2_div6_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vclk2_div6_en.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -2691,16 +3473,25 @@ static struct clk_fixed_factor g12a_vclk2_div12 = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_div12",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk2_div12_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_vclk2_div12_en.hw
+                },
                 .num_parents = 1,
         },
 };
 
 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
-static const char * const g12a_cts_parent_names[] = {
-        "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
-        "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
-        "vclk2_div6", "vclk2_div12"
+static const struct clk_hw *g12a_cts_parent_hws[] = {
+        &g12a_vclk_div1.hw,
+        &g12a_vclk_div2.hw,
+        &g12a_vclk_div4.hw,
+        &g12a_vclk_div6.hw,
+        &g12a_vclk_div12.hw,
+        &g12a_vclk2_div1.hw,
+        &g12a_vclk2_div2.hw,
+        &g12a_vclk2_div4.hw,
+        &g12a_vclk2_div6.hw,
+        &g12a_vclk2_div12.hw,
 };
 
 static struct clk_regmap g12a_cts_enci_sel = {
@@ -2713,8 +3504,8 @@ static struct clk_regmap g12a_cts_enci_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_enci_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = g12a_cts_parent_names,
-                .num_parents = ARRAY_SIZE(g12a_cts_parent_names),
+                .parent_hws = g12a_cts_parent_hws,
+                .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
         },
 };
@@ -2729,8 +3520,8 @@ static struct clk_regmap g12a_cts_encp_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_encp_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = g12a_cts_parent_names,
-                .num_parents = ARRAY_SIZE(g12a_cts_parent_names),
+                .parent_hws = g12a_cts_parent_hws,
+                .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
         },
 };
@@ -2745,18 +3536,25 @@ static struct clk_regmap g12a_cts_vdac_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_vdac_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = g12a_cts_parent_names,
-                .num_parents = ARRAY_SIZE(g12a_cts_parent_names),
+                .parent_hws = g12a_cts_parent_hws,
+                .num_parents = ARRAY_SIZE(g12a_cts_parent_hws),
                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
         },
 };
 
 /* TOFIX: add support for cts_tcon */
 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
-static const char * const g12a_cts_hdmi_tx_parent_names[] = {
-        "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
-        "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
-        "vclk2_div6", "vclk2_div12"
+static const struct clk_hw *g12a_cts_hdmi_tx_parent_hws[] = {
+        &g12a_vclk_div1.hw,
+        &g12a_vclk_div2.hw,
+        &g12a_vclk_div4.hw,
+        &g12a_vclk_div6.hw,
+        &g12a_vclk_div12.hw,
+        &g12a_vclk2_div1.hw,
+        &g12a_vclk2_div2.hw,
+        &g12a_vclk2_div4.hw,
+        &g12a_vclk2_div6.hw,
+        &g12a_vclk2_div12.hw,
 };
 
 static struct clk_regmap g12a_hdmi_tx_sel = {
@@ -2769,8 +3567,8 @@ static struct clk_regmap g12a_hdmi_tx_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_tx_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = g12a_cts_hdmi_tx_parent_names,
-                .num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_names),
+                .parent_hws = g12a_cts_hdmi_tx_parent_hws,
+                .num_parents = ARRAY_SIZE(g12a_cts_hdmi_tx_parent_hws),
                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
         },
 };
@@ -2783,7 +3581,9 @@ static struct clk_regmap g12a_cts_enci = {
         .hw.init = &(struct clk_init_data) {
                 .name = "cts_enci",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "cts_enci_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_cts_enci_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2797,7 +3597,9 @@ static struct clk_regmap g12a_cts_encp = {
         .hw.init = &(struct clk_init_data) {
                 .name = "cts_encp",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "cts_encp_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_cts_encp_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2811,7 +3613,9 @@ static struct clk_regmap g12a_cts_vdac = {
         .hw.init = &(struct clk_init_data) {
                 .name = "cts_vdac",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "cts_vdac_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_cts_vdac_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2825,7 +3629,9 @@ static struct clk_regmap g12a_hdmi_tx = {
         .hw.init = &(struct clk_init_data) {
                 .name = "hdmi_tx",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "hdmi_tx_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_hdmi_tx_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2833,8 +3639,11 @@ static struct clk_regmap g12a_hdmi_tx = {
 
 /* HDMI Clocks */
 
-static const char * const g12a_hdmi_parent_names[] = {
-        IN_PREFIX "xtal", "fclk_div4", "fclk_div3", "fclk_div5"
+static const struct clk_parent_data g12a_hdmi_parent_data[] = {
+        { .fw_name = "xtal", },
+        { .hw = &g12a_fclk_div4.hw },
+        { .hw = &g12a_fclk_div3.hw },
+        { .hw = &g12a_fclk_div5.hw },
 };
 
 static struct clk_regmap g12a_hdmi_sel = {
@@ -2847,8 +3656,8 @@ static struct clk_regmap g12a_hdmi_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = g12a_hdmi_parent_names,
-                .num_parents = ARRAY_SIZE(g12a_hdmi_parent_names),
+                .parent_data = g12a_hdmi_parent_data,
+                .num_parents = ARRAY_SIZE(g12a_hdmi_parent_data),
                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
         },
 };
@@ -2862,7 +3671,7 @@ static struct clk_regmap g12a_hdmi_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "hdmi_sel" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_sel.hw },
                 .num_parents = 1,
                 .flags = CLK_GET_RATE_NOCACHE,
         },
@@ -2876,7 +3685,7 @@ static struct clk_regmap g12a_hdmi = {
         .hw.init = &(struct clk_init_data) {
                 .name = "hdmi",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "hdmi_div" },
+                .parent_hws = (const struct clk_hw *[]) { &g12a_hdmi_div.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2886,10 +3695,15 @@ static struct clk_regmap g12a_hdmi = {
  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
  * muxed by a glitch-free switch.
  */
-
-static const char * const g12a_mali_0_1_parent_names[] = {
-        IN_PREFIX "xtal", "gp0_pll", "hihi_pll", "fclk_div2p5",
-        "fclk_div3", "fclk_div4", "fclk_div5", "fclk_div7"
+static const struct clk_parent_data g12a_mali_0_1_parent_data[] = {
+        { .fw_name = "xtal", },
+        { .hw = &g12a_gp0_pll.hw },
+        { .hw = &g12a_hifi_pll.hw },
+        { .hw = &g12a_fclk_div2p5.hw },
+        { .hw = &g12a_fclk_div3.hw },
+        { .hw = &g12a_fclk_div4.hw },
+        { .hw = &g12a_fclk_div5.hw },
+        { .hw = &g12a_fclk_div7.hw },
 };
 
 static struct clk_regmap g12a_mali_0_sel = {
@@ -2901,7 +3715,7 @@ static struct clk_regmap g12a_mali_0_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "mali_0_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = g12a_mali_0_1_parent_names,
+                .parent_data = g12a_mali_0_1_parent_data,
                 .num_parents = 8,
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
@@ -2916,7 +3730,9 @@ static struct clk_regmap g12a_mali_0_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mali_0_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "mali_0_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_mali_0_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
@@ -2930,7 +3746,9 @@ static struct clk_regmap g12a_mali_0 = {
         .hw.init = &(struct clk_init_data){
                 .name = "mali_0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mali_0_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_mali_0_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2945,7 +3763,7 @@ static struct clk_regmap g12a_mali_1_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "mali_1_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = g12a_mali_0_1_parent_names,
+                .parent_data = g12a_mali_0_1_parent_data,
                 .num_parents = 8,
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
@@ -2960,7 +3778,9 @@ static struct clk_regmap g12a_mali_1_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mali_1_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "mali_1_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_mali_1_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
@@ -2974,14 +3794,17 @@ static struct clk_regmap g12a_mali_1 = {
         .hw.init = &(struct clk_init_data){
                 .name = "mali_1",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mali_1_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_mali_1_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
 
-static const char * const g12a_mali_parent_names[] = {
-        "mali_0", "mali_1"
+static const struct clk_hw *g12a_mali_parent_hws[] = {
+        &g12a_mali_0.hw,
+        &g12a_mali_1.hw,
 };
 
 static struct clk_regmap g12a_mali = {
@@ -2993,7 +3816,7 @@ static struct clk_regmap g12a_mali = {
         .hw.init = &(struct clk_init_data){
                 .name = "mali",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = g12a_mali_parent_names,
+                .parent_hws = g12a_mali_parent_hws,
                 .num_parents = 2,
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
@@ -3008,7 +3831,9 @@ static struct clk_regmap g12a_ts_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "ts_div",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "xtal" },
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
         },
 };
@@ -3021,11 +3846,19 @@ static struct clk_regmap g12a_ts = {
         .hw.init = &(struct clk_init_data){
                 .name = "ts",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "ts_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &g12a_ts_div.hw
+                },
                 .num_parents = 1,
         },
 };
 
+#define MESON_GATE(_name, _reg, _bit) \
+        MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
+
+#define MESON_GATE_RO(_name, _reg, _bit) \
+        MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw)
+
 /* Everything Else (EE) domain gates */
 static MESON_GATE(g12a_ddr,                     HHI_GCLK_MPEG0, 0);
 static MESON_GATE(g12a_dos,                     HHI_GCLK_MPEG0, 1);
@@ -3571,6 +4404,240 @@ static struct clk_hw_onecell_data g12b_hw_onecell_data = {
         .num = NR_CLKS,
 };
 
+static struct clk_hw_onecell_data sm1_hw_onecell_data = {
+        .hws = {
+                [CLKID_SYS_PLL]                 = &g12a_sys_pll.hw,
+                [CLKID_FIXED_PLL]               = &g12a_fixed_pll.hw,
+                [CLKID_FCLK_DIV2]               = &g12a_fclk_div2.hw,
+                [CLKID_FCLK_DIV3]               = &g12a_fclk_div3.hw,
+                [CLKID_FCLK_DIV4]               = &g12a_fclk_div4.hw,
+                [CLKID_FCLK_DIV5]               = &g12a_fclk_div5.hw,
+                [CLKID_FCLK_DIV7]               = &g12a_fclk_div7.hw,
+                [CLKID_FCLK_DIV2P5]             = &g12a_fclk_div2p5.hw,
+                [CLKID_GP0_PLL]                 = &g12a_gp0_pll.hw,
+                [CLKID_MPEG_SEL]                = &g12a_mpeg_clk_sel.hw,
+                [CLKID_MPEG_DIV]                = &g12a_mpeg_clk_div.hw,
+                [CLKID_CLK81]                   = &g12a_clk81.hw,
+                [CLKID_MPLL0]                   = &g12a_mpll0.hw,
+                [CLKID_MPLL1]                   = &g12a_mpll1.hw,
+                [CLKID_MPLL2]                   = &g12a_mpll2.hw,
+                [CLKID_MPLL3]                   = &g12a_mpll3.hw,
+                [CLKID_DDR]                     = &g12a_ddr.hw,
+                [CLKID_DOS]                     = &g12a_dos.hw,
+                [CLKID_AUDIO_LOCKER]            = &g12a_audio_locker.hw,
+                [CLKID_MIPI_DSI_HOST]           = &g12a_mipi_dsi_host.hw,
+                [CLKID_ETH_PHY]                 = &g12a_eth_phy.hw,
+                [CLKID_ISA]                     = &g12a_isa.hw,
+                [CLKID_PL301]                   = &g12a_pl301.hw,
+                [CLKID_PERIPHS]                 = &g12a_periphs.hw,
+                [CLKID_SPICC0]                  = &g12a_spicc_0.hw,
+                [CLKID_I2C]                     = &g12a_i2c.hw,
+                [CLKID_SANA]                    = &g12a_sana.hw,
+                [CLKID_SD]                      = &g12a_sd.hw,
+                [CLKID_RNG0]                    = &g12a_rng0.hw,
+                [CLKID_UART0]                   = &g12a_uart0.hw,
+                [CLKID_SPICC1]                  = &g12a_spicc_1.hw,
+                [CLKID_HIU_IFACE]               = &g12a_hiu_reg.hw,
+                [CLKID_MIPI_DSI_PHY]            = &g12a_mipi_dsi_phy.hw,
+                [CLKID_ASSIST_MISC]             = &g12a_assist_misc.hw,
+                [CLKID_SD_EMMC_A]               = &g12a_emmc_a.hw,
+                [CLKID_SD_EMMC_B]               = &g12a_emmc_b.hw,
+                [CLKID_SD_EMMC_C]               = &g12a_emmc_c.hw,
+                [CLKID_AUDIO_CODEC]             = &g12a_audio_codec.hw,
+                [CLKID_AUDIO]                   = &g12a_audio.hw,
+                [CLKID_ETH]                     = &g12a_eth_core.hw,
+                [CLKID_DEMUX]                   = &g12a_demux.hw,
+                [CLKID_AUDIO_IFIFO]             = &g12a_audio_ififo.hw,
+                [CLKID_ADC]                     = &g12a_adc.hw,
+                [CLKID_UART1]                   = &g12a_uart1.hw,
+                [CLKID_G2D]                     = &g12a_g2d.hw,
+                [CLKID_RESET]                   = &g12a_reset.hw,
+                [CLKID_PCIE_COMB]               = &g12a_pcie_comb.hw,
+                [CLKID_PARSER]                  = &g12a_parser.hw,
+                [CLKID_USB]                     = &g12a_usb_general.hw,
+                [CLKID_PCIE_PHY]                = &g12a_pcie_phy.hw,
+                [CLKID_AHB_ARB0]                = &g12a_ahb_arb0.hw,
+                [CLKID_AHB_DATA_BUS]            = &g12a_ahb_data_bus.hw,
+                [CLKID_AHB_CTRL_BUS]            = &g12a_ahb_ctrl_bus.hw,
+                [CLKID_HTX_HDCP22]              = &g12a_htx_hdcp22.hw,
+                [CLKID_HTX_PCLK]                = &g12a_htx_pclk.hw,
+                [CLKID_BT656]                   = &g12a_bt656.hw,
+                [CLKID_USB1_DDR_BRIDGE]         = &g12a_usb1_to_ddr.hw,
+                [CLKID_MMC_PCLK]                = &g12a_mmc_pclk.hw,
+                [CLKID_UART2]                   = &g12a_uart2.hw,
+                [CLKID_VPU_INTR]                = &g12a_vpu_intr.hw,
+                [CLKID_GIC]                     = &g12a_gic.hw,
+                [CLKID_SD_EMMC_A_CLK0_SEL]      = &g12a_sd_emmc_a_clk0_sel.hw,
+                [CLKID_SD_EMMC_A_CLK0_DIV]      = &g12a_sd_emmc_a_clk0_div.hw,
+                [CLKID_SD_EMMC_A_CLK0]          = &g12a_sd_emmc_a_clk0.hw,
+                [CLKID_SD_EMMC_B_CLK0_SEL]      = &g12a_sd_emmc_b_clk0_sel.hw,
+                [CLKID_SD_EMMC_B_CLK0_DIV]      = &g12a_sd_emmc_b_clk0_div.hw,
+                [CLKID_SD_EMMC_B_CLK0]          = &g12a_sd_emmc_b_clk0.hw,
+                [CLKID_SD_EMMC_C_CLK0_SEL]      = &g12a_sd_emmc_c_clk0_sel.hw,
+                [CLKID_SD_EMMC_C_CLK0_DIV]      = &g12a_sd_emmc_c_clk0_div.hw,
+                [CLKID_SD_EMMC_C_CLK0]          = &g12a_sd_emmc_c_clk0.hw,
+                [CLKID_MPLL0_DIV]               = &g12a_mpll0_div.hw,
+                [CLKID_MPLL1_DIV]               = &g12a_mpll1_div.hw,
+                [CLKID_MPLL2_DIV]               = &g12a_mpll2_div.hw,
+                [CLKID_MPLL3_DIV]               = &g12a_mpll3_div.hw,
+                [CLKID_FCLK_DIV2_DIV]           = &g12a_fclk_div2_div.hw,
+                [CLKID_FCLK_DIV3_DIV]           = &g12a_fclk_div3_div.hw,
+                [CLKID_FCLK_DIV4_DIV]           = &g12a_fclk_div4_div.hw,
+                [CLKID_FCLK_DIV5_DIV]           = &g12a_fclk_div5_div.hw,
+                [CLKID_FCLK_DIV7_DIV]           = &g12a_fclk_div7_div.hw,
+                [CLKID_FCLK_DIV2P5_DIV]         = &g12a_fclk_div2p5_div.hw,
+                [CLKID_HIFI_PLL]                = &g12a_hifi_pll.hw,
+                [CLKID_VCLK2_VENCI0]            = &g12a_vclk2_venci0.hw,
+                [CLKID_VCLK2_VENCI1]            = &g12a_vclk2_venci1.hw,
+                [CLKID_VCLK2_VENCP0]            = &g12a_vclk2_vencp0.hw,
+                [CLKID_VCLK2_VENCP1]            = &g12a_vclk2_vencp1.hw,
+                [CLKID_VCLK2_VENCT0]            = &g12a_vclk2_venct0.hw,
+                [CLKID_VCLK2_VENCT1]            = &g12a_vclk2_venct1.hw,
+                [CLKID_VCLK2_OTHER]             = &g12a_vclk2_other.hw,
+                [CLKID_VCLK2_ENCI]              = &g12a_vclk2_enci.hw,
+                [CLKID_VCLK2_ENCP]              = &g12a_vclk2_encp.hw,
+                [CLKID_DAC_CLK]                 = &g12a_dac_clk.hw,
+                [CLKID_AOCLK]                   = &g12a_aoclk_gate.hw,
+                [CLKID_IEC958]                  = &g12a_iec958_gate.hw,
+                [CLKID_ENC480P]                 = &g12a_enc480p.hw,
+                [CLKID_RNG1]                    = &g12a_rng1.hw,
+                [CLKID_VCLK2_ENCT]              = &g12a_vclk2_enct.hw,
+                [CLKID_VCLK2_ENCL]              = &g12a_vclk2_encl.hw,
+                [CLKID_VCLK2_VENCLMMC]          = &g12a_vclk2_venclmmc.hw,
+                [CLKID_VCLK2_VENCL]             = &g12a_vclk2_vencl.hw,
+                [CLKID_VCLK2_OTHER1]            = &g12a_vclk2_other1.hw,
+                [CLKID_FIXED_PLL_DCO]           = &g12a_fixed_pll_dco.hw,
+                [CLKID_SYS_PLL_DCO]             = &g12a_sys_pll_dco.hw,
+                [CLKID_GP0_PLL_DCO]             = &g12a_gp0_pll_dco.hw,
+                [CLKID_HIFI_PLL_DCO]            = &g12a_hifi_pll_dco.hw,
+                [CLKID_DMA]                     = &g12a_dma.hw,
+                [CLKID_EFUSE]                   = &g12a_efuse.hw,
+                [CLKID_ROM_BOOT]                = &g12a_rom_boot.hw,
+                [CLKID_RESET_SEC]               = &g12a_reset_sec.hw,
+                [CLKID_SEC_AHB_APB3]            = &g12a_sec_ahb_apb3.hw,
+                [CLKID_MPLL_PREDIV]             = &g12a_mpll_prediv.hw,
+                [CLKID_VPU_0_SEL]               = &g12a_vpu_0_sel.hw,
+                [CLKID_VPU_0_DIV]               = &g12a_vpu_0_div.hw,
+                [CLKID_VPU_0]                   = &g12a_vpu_0.hw,
+                [CLKID_VPU_1_SEL]               = &g12a_vpu_1_sel.hw,
+                [CLKID_VPU_1_DIV]               = &g12a_vpu_1_div.hw,
+                [CLKID_VPU_1]                   = &g12a_vpu_1.hw,
+                [CLKID_VPU]                     = &g12a_vpu.hw,
+                [CLKID_VAPB_0_SEL]              = &g12a_vapb_0_sel.hw,
+                [CLKID_VAPB_0_DIV]              = &g12a_vapb_0_div.hw,
+                [CLKID_VAPB_0]                  = &g12a_vapb_0.hw,
+                [CLKID_VAPB_1_SEL]              = &g12a_vapb_1_sel.hw,
+                [CLKID_VAPB_1_DIV]              = &g12a_vapb_1_div.hw,
+                [CLKID_VAPB_1]                  = &g12a_vapb_1.hw,
+                [CLKID_VAPB_SEL]                = &g12a_vapb_sel.hw,
+                [CLKID_VAPB]                    = &g12a_vapb.hw,
+                [CLKID_HDMI_PLL_DCO]            = &g12a_hdmi_pll_dco.hw,
+                [CLKID_HDMI_PLL_OD]             = &g12a_hdmi_pll_od.hw,
+                [CLKID_HDMI_PLL_OD2]            = &g12a_hdmi_pll_od2.hw,
+                [CLKID_HDMI_PLL]                = &g12a_hdmi_pll.hw,
+                [CLKID_VID_PLL]                 = &g12a_vid_pll_div.hw,
+                [CLKID_VID_PLL_SEL]             = &g12a_vid_pll_sel.hw,
+                [CLKID_VID_PLL_DIV]             = &g12a_vid_pll.hw,
+                [CLKID_VCLK_SEL]                = &g12a_vclk_sel.hw,
+                [CLKID_VCLK2_SEL]               = &g12a_vclk2_sel.hw,
+                [CLKID_VCLK_INPUT]              = &g12a_vclk_input.hw,
+                [CLKID_VCLK2_INPUT]             = &g12a_vclk2_input.hw,
+                [CLKID_VCLK_DIV]                = &g12a_vclk_div.hw,
+                [CLKID_VCLK2_DIV]               = &g12a_vclk2_div.hw,
+                [CLKID_VCLK]                    = &g12a_vclk.hw,
+                [CLKID_VCLK2]                   = &g12a_vclk2.hw,
+                [CLKID_VCLK_DIV1]               = &g12a_vclk_div1.hw,
+                [CLKID_VCLK_DIV2_EN]            = &g12a_vclk_div2_en.hw,
+                [CLKID_VCLK_DIV4_EN]            = &g12a_vclk_div4_en.hw,
+                [CLKID_VCLK_DIV6_EN]            = &g12a_vclk_div6_en.hw,
+                [CLKID_VCLK_DIV12_EN]           = &g12a_vclk_div12_en.hw,
+                [CLKID_VCLK2_DIV1]              = &g12a_vclk2_div1.hw,
+                [CLKID_VCLK2_DIV2_EN]           = &g12a_vclk2_div2_en.hw,
+                [CLKID_VCLK2_DIV4_EN]           = &g12a_vclk2_div4_en.hw,
+                [CLKID_VCLK2_DIV6_EN]           = &g12a_vclk2_div6_en.hw,
+                [CLKID_VCLK2_DIV12_EN]          = &g12a_vclk2_div12_en.hw,
+                [CLKID_VCLK_DIV2]               = &g12a_vclk_div2.hw,
+                [CLKID_VCLK_DIV4]               = &g12a_vclk_div4.hw,
+                [CLKID_VCLK_DIV6]               = &g12a_vclk_div6.hw,
+                [CLKID_VCLK_DIV12]              = &g12a_vclk_div12.hw,
+                [CLKID_VCLK2_DIV2]              = &g12a_vclk2_div2.hw,
+                [CLKID_VCLK2_DIV4]              = &g12a_vclk2_div4.hw,
+                [CLKID_VCLK2_DIV6]              = &g12a_vclk2_div6.hw,
+                [CLKID_VCLK2_DIV12]             = &g12a_vclk2_div12.hw,
+                [CLKID_CTS_ENCI_SEL]            = &g12a_cts_enci_sel.hw,
+                [CLKID_CTS_ENCP_SEL]            = &g12a_cts_encp_sel.hw,
+                [CLKID_CTS_VDAC_SEL]            = &g12a_cts_vdac_sel.hw,
+                [CLKID_HDMI_TX_SEL]             = &g12a_hdmi_tx_sel.hw,
+                [CLKID_CTS_ENCI]                = &g12a_cts_enci.hw,
+                [CLKID_CTS_ENCP]                = &g12a_cts_encp.hw,
+                [CLKID_CTS_VDAC]                = &g12a_cts_vdac.hw,
+                [CLKID_HDMI_TX]                 = &g12a_hdmi_tx.hw,
+                [CLKID_HDMI_SEL]                = &g12a_hdmi_sel.hw,
+                [CLKID_HDMI_DIV]                = &g12a_hdmi_div.hw,
+                [CLKID_HDMI]                    = &g12a_hdmi.hw,
+                [CLKID_MALI_0_SEL]              = &g12a_mali_0_sel.hw,
+                [CLKID_MALI_0_DIV]              = &g12a_mali_0_div.hw,
+                [CLKID_MALI_0]                  = &g12a_mali_0.hw,
+                [CLKID_MALI_1_SEL]              = &g12a_mali_1_sel.hw,
+                [CLKID_MALI_1_DIV]              = &g12a_mali_1_div.hw,
+                [CLKID_MALI_1]                  = &g12a_mali_1.hw,
+                [CLKID_MALI]                    = &g12a_mali.hw,
+                [CLKID_MPLL_50M_DIV]            = &g12a_mpll_50m_div.hw,
+                [CLKID_MPLL_50M]                = &g12a_mpll_50m.hw,
+                [CLKID_SYS_PLL_DIV16_EN]        = &g12a_sys_pll_div16_en.hw,
+                [CLKID_SYS_PLL_DIV16]           = &g12a_sys_pll_div16.hw,
+                [CLKID_CPU_CLK_DYN0_SEL]        = &g12a_cpu_clk_premux0.hw,
+                [CLKID_CPU_CLK_DYN0_DIV]        = &g12a_cpu_clk_mux0_div.hw,
+                [CLKID_CPU_CLK_DYN0]            = &g12a_cpu_clk_postmux0.hw,
+                [CLKID_CPU_CLK_DYN1_SEL]        = &g12a_cpu_clk_premux1.hw,
+                [CLKID_CPU_CLK_DYN1_DIV]        = &g12a_cpu_clk_mux1_div.hw,
+                [CLKID_CPU_CLK_DYN1]            = &g12a_cpu_clk_postmux1.hw,
+                [CLKID_CPU_CLK_DYN]             = &g12a_cpu_clk_dyn.hw,
+                [CLKID_CPU_CLK]                 = &g12a_cpu_clk.hw,
+                [CLKID_CPU_CLK_DIV16_EN]        = &g12a_cpu_clk_div16_en.hw,
+                [CLKID_CPU_CLK_DIV16]           = &g12a_cpu_clk_div16.hw,
+                [CLKID_CPU_CLK_APB_DIV]         = &g12a_cpu_clk_apb_div.hw,
+                [CLKID_CPU_CLK_APB]             = &g12a_cpu_clk_apb.hw,
+                [CLKID_CPU_CLK_ATB_DIV]         = &g12a_cpu_clk_atb_div.hw,
+                [CLKID_CPU_CLK_ATB]             = &g12a_cpu_clk_atb.hw,
+                [CLKID_CPU_CLK_AXI_DIV]         = &g12a_cpu_clk_axi_div.hw,
+                [CLKID_CPU_CLK_AXI]             = &g12a_cpu_clk_axi.hw,
+                [CLKID_CPU_CLK_TRACE_DIV]       = &g12a_cpu_clk_trace_div.hw,
+                [CLKID_CPU_CLK_TRACE]           = &g12a_cpu_clk_trace.hw,
+                [CLKID_PCIE_PLL_DCO]            = &g12a_pcie_pll_dco.hw,
+                [CLKID_PCIE_PLL_DCO_DIV2]       = &g12a_pcie_pll_dco_div2.hw,
+                [CLKID_PCIE_PLL_OD]             = &g12a_pcie_pll_od.hw,
+                [CLKID_PCIE_PLL]                = &g12a_pcie_pll.hw,
+                [CLKID_VDEC_1_SEL]              = &g12a_vdec_1_sel.hw,
+                [CLKID_VDEC_1_DIV]              = &g12a_vdec_1_div.hw,
+                [CLKID_VDEC_1]                  = &g12a_vdec_1.hw,
+                [CLKID_VDEC_HEVC_SEL]           = &g12a_vdec_hevc_sel.hw,
+                [CLKID_VDEC_HEVC_DIV]           = &g12a_vdec_hevc_div.hw,
+                [CLKID_VDEC_HEVC]               = &g12a_vdec_hevc.hw,
+                [CLKID_VDEC_HEVCF_SEL]          = &g12a_vdec_hevcf_sel.hw,
+                [CLKID_VDEC_HEVCF_DIV]          = &g12a_vdec_hevcf_div.hw,
+                [CLKID_VDEC_HEVCF]              = &g12a_vdec_hevcf.hw,
+                [CLKID_TS_DIV]                  = &g12a_ts_div.hw,
+                [CLKID_TS]                      = &g12a_ts.hw,
+                [CLKID_GP1_PLL_DCO]             = &sm1_gp1_pll_dco.hw,
+                [CLKID_GP1_PLL]                 = &sm1_gp1_pll.hw,
+                [CLKID_DSU_CLK_DYN0_SEL]        = &sm1_dsu_clk_premux0.hw,
+                [CLKID_DSU_CLK_DYN0_DIV]        = &sm1_dsu_clk_premux1.hw,
+                [CLKID_DSU_CLK_DYN0]            = &sm1_dsu_clk_mux0_div.hw,
+                [CLKID_DSU_CLK_DYN1_SEL]        = &sm1_dsu_clk_postmux0.hw,
+                [CLKID_DSU_CLK_DYN1_DIV]        = &sm1_dsu_clk_mux1_div.hw,
+                [CLKID_DSU_CLK_DYN1]            = &sm1_dsu_clk_postmux1.hw,
+                [CLKID_DSU_CLK_DYN]             = &sm1_dsu_clk_dyn.hw,
+                [CLKID_DSU_CLK_FINAL]           = &sm1_dsu_final_clk.hw,
+                [CLKID_DSU_CLK]                 = &sm1_dsu_clk.hw,
+                [CLKID_CPU1_CLK]                = &sm1_cpu1_clk.hw,
+                [CLKID_CPU2_CLK]                = &sm1_cpu2_clk.hw,
+                [CLKID_CPU3_CLK]                = &sm1_cpu3_clk.hw,
+                [NR_CLKS]                       = NULL,
+        },
+        .num = NR_CLKS,
+};
+
 /* Convenience table to populate regmap in .probe */
 static struct clk_regmap *const g12a_clk_regmaps[] = {
         &g12a_clk81,
@@ -3786,34 +4853,243 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
         &g12b_cpub_clk_axi,
         &g12b_cpub_clk_trace_sel,
         &g12b_cpub_clk_trace,
+        &sm1_gp1_pll_dco,
+        &sm1_gp1_pll,
+        &sm1_dsu_clk_premux0,
+        &sm1_dsu_clk_premux1,
+        &sm1_dsu_clk_mux0_div,
+        &sm1_dsu_clk_postmux0,
+        &sm1_dsu_clk_mux1_div,
+        &sm1_dsu_clk_postmux1,
+        &sm1_dsu_clk_dyn,
+        &sm1_dsu_final_clk,
+        &sm1_dsu_clk,
+        &sm1_cpu1_clk,
+        &sm1_cpu2_clk,
+        &sm1_cpu3_clk,
 };
 
 static const struct reg_sequence g12a_init_regs[] = {
         { .reg = HHI_MPLL_CNTL0,        .def = 0x00000543 },
 };
 
-static const struct meson_eeclkc_data g12a_clkc_data = {
-        .regmap_clks = g12a_clk_regmaps,
-        .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
-        .hw_onecell_data = &g12a_hw_onecell_data,
-        .init_regs = g12a_init_regs,
-        .init_count = ARRAY_SIZE(g12a_init_regs),
-};
-
-static const struct meson_eeclkc_data g12b_clkc_data = {
-        .regmap_clks = g12a_clk_regmaps,
-        .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
-        .hw_onecell_data = &g12b_hw_onecell_data
+static int meson_g12a_dvfs_setup_common(struct platform_device *pdev,
+                                        struct clk_hw **hws)
+{
+        const char *notifier_clk_name;
+        struct clk *notifier_clk;
+        struct clk_hw *xtal;
+        int ret;
+
+        xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
+
+        /* Setup clock notifier for cpu_clk_postmux0 */
+        g12a_cpu_clk_postmux0_nb_data.xtal = xtal;
+        notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_postmux0.hw);
+        notifier_clk = __clk_lookup(notifier_clk_name);
+        ret = clk_notifier_register(notifier_clk,
+                                    &g12a_cpu_clk_postmux0_nb_data.nb);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to register the cpu_clk_postmux0 notifier\n");
+                return ret;
+        }
+
+        /* Setup clock notifier for cpu_clk_dyn mux */
+        notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk_dyn.hw);
+        notifier_clk = __clk_lookup(notifier_clk_name);
+        ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to register the cpu_clk_dyn notifier\n");
+                return ret;
+        }
+
+        return 0;
+}
+
+static int meson_g12b_dvfs_setup(struct platform_device *pdev)
+{
+        struct clk_hw **hws = g12b_hw_onecell_data.hws;
+        const char *notifier_clk_name;
+        struct clk *notifier_clk;
+        struct clk_hw *xtal;
+        int ret;
+
+        ret = meson_g12a_dvfs_setup_common(pdev, hws);
+        if (ret)
+                return ret;
+
+        xtal = clk_hw_get_parent_by_index(hws[CLKID_CPU_CLK_DYN1_SEL], 0);
+
+        /* Setup clock notifier for cpu_clk mux */
+        notifier_clk_name = clk_hw_get_name(&g12b_cpu_clk.hw);
+        notifier_clk = __clk_lookup(notifier_clk_name);
+        ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to register the cpu_clk notifier\n");
+                return ret;
+        }
+
+        /* Setup clock notifier for sys1_pll */
+        notifier_clk_name = clk_hw_get_name(&g12b_sys1_pll.hw);
+        notifier_clk = __clk_lookup(notifier_clk_name);
+        ret = clk_notifier_register(notifier_clk,
+                                    &g12b_cpu_clk_sys1_pll_nb_data.nb);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to register the sys1_pll notifier\n");
+                return ret;
+        }
+
+        /* Add notifiers for the second CPU cluster */
+
+        /* Setup clock notifier for cpub_clk_postmux0 */
+        g12b_cpub_clk_postmux0_nb_data.xtal = xtal;
+        notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_postmux0.hw);
+        notifier_clk = __clk_lookup(notifier_clk_name);
+        ret = clk_notifier_register(notifier_clk,
+                                    &g12b_cpub_clk_postmux0_nb_data.nb);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to register the cpub_clk_postmux0 notifier\n");
+                return ret;
+        }
+
+        /* Setup clock notifier for cpub_clk_dyn mux */
+        notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk_dyn.hw);
+        notifier_clk = __clk_lookup(notifier_clk_name);
+        ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to register the cpub_clk_dyn notifier\n");
+                return ret;
+        }
+
+        /* Setup clock notifier for cpub_clk mux */
+        notifier_clk_name = clk_hw_get_name(&g12b_cpub_clk.hw);
+        notifier_clk = __clk_lookup(notifier_clk_name);
+        ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to register the cpub_clk notifier\n");
+                return ret;
+        }
+
+        /* Setup clock notifier for sys_pll */
+        notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw);
+        notifier_clk = __clk_lookup(notifier_clk_name);
+        ret = clk_notifier_register(notifier_clk,
+                                    &g12b_cpub_clk_sys_pll_nb_data.nb);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to register the sys_pll notifier\n");
+                return ret;
+        }
+
+        return 0;
+}
+
+static int meson_g12a_dvfs_setup(struct platform_device *pdev)
+{
+        struct clk_hw **hws = g12a_hw_onecell_data.hws;
+        const char *notifier_clk_name;
+        struct clk *notifier_clk;
+        int ret;
+
+        ret = meson_g12a_dvfs_setup_common(pdev, hws);
+        if (ret)
+                return ret;
+
+        /* Setup clock notifier for cpu_clk mux */
+        notifier_clk_name = clk_hw_get_name(&g12a_cpu_clk.hw);
+        notifier_clk = __clk_lookup(notifier_clk_name);
+        ret = clk_notifier_register(notifier_clk, &g12a_cpu_clk_mux_nb);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to register the cpu_clk notifier\n");
+                return ret;
+        }
+
+        /* Setup clock notifier for sys_pll */
+        notifier_clk_name = clk_hw_get_name(&g12a_sys_pll.hw);
+        notifier_clk = __clk_lookup(notifier_clk_name);
+        ret = clk_notifier_register(notifier_clk, &g12a_sys_pll_nb_data.nb);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to register the sys_pll notifier\n");
+                return ret;
+        }
+
+        return 0;
+}
+
+struct meson_g12a_data {
+        const struct meson_eeclkc_data eeclkc_data;
+        int (*dvfs_setup)(struct platform_device *pdev);
+};
+
+static int meson_g12a_probe(struct platform_device *pdev)
+{
+        const struct meson_eeclkc_data *eeclkc_data;
+        const struct meson_g12a_data *g12a_data;
+        int ret;
+
+        eeclkc_data = of_device_get_match_data(&pdev->dev);
+        if (!eeclkc_data)
+                return -EINVAL;
+
+        ret = meson_eeclkc_probe(pdev);
+        if (ret)
+                return ret;
+
+        g12a_data = container_of(eeclkc_data, struct meson_g12a_data,
+                                 eeclkc_data);
+
+        if (g12a_data->dvfs_setup)
+                return g12a_data->dvfs_setup(pdev);
+
+        return 0;
+}
+
+static const struct meson_g12a_data g12a_clkc_data = {
+        .eeclkc_data = {
+                .regmap_clks = g12a_clk_regmaps,
+                .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
+                .hw_onecell_data = &g12a_hw_onecell_data,
+                .init_regs = g12a_init_regs,
+                .init_count = ARRAY_SIZE(g12a_init_regs),
+        },
+        .dvfs_setup = meson_g12a_dvfs_setup,
+};
+
+static const struct meson_g12a_data g12b_clkc_data = {
+        .eeclkc_data = {
+                .regmap_clks = g12a_clk_regmaps,
+                .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
+                .hw_onecell_data = &g12b_hw_onecell_data,
+        },
+        .dvfs_setup = meson_g12b_dvfs_setup,
+};
+
+static const struct meson_g12a_data sm1_clkc_data = {
+        .eeclkc_data = {
+                .regmap_clks = g12a_clk_regmaps,
+                .regmap_clk_num = ARRAY_SIZE(g12a_clk_regmaps),
+                .hw_onecell_data = &sm1_hw_onecell_data,
+        },
+        .dvfs_setup = meson_g12a_dvfs_setup,
 };
 
 static const struct of_device_id clkc_match_table[] = {
-        { .compatible = "amlogic,g12a-clkc", .data = &g12a_clkc_data },
-        { .compatible = "amlogic,g12b-clkc", .data = &g12b_clkc_data },
+        {
+                .compatible = "amlogic,g12a-clkc",
+                .data = &g12a_clkc_data.eeclkc_data
+        },
+        {
+                .compatible = "amlogic,g12b-clkc",
+                .data = &g12b_clkc_data.eeclkc_data
+        },
+        {
+                .compatible = "amlogic,sm1-clkc",
+                .data = &sm1_clkc_data.eeclkc_data
+        },
         {}
 };
 
 static struct platform_driver g12a_driver = {
-        .probe          = meson_eeclkc_probe,
+        .probe          = meson_g12a_probe,
         .driver         = {
                 .name   = "g12a-clkc",
                 .of_match_table = clkc_match_table,
diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index c8aed31fbe17..9df4068aced1 100644
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -29,6 +29,14 @@
 #define HHI_GP0_PLL_CNTL5               0x054
 #define HHI_GP0_PLL_CNTL6               0x058
 #define HHI_GP0_PLL_STS                 0x05C
+#define HHI_GP1_PLL_CNTL0               0x060
+#define HHI_GP1_PLL_CNTL1               0x064
+#define HHI_GP1_PLL_CNTL2               0x068
+#define HHI_GP1_PLL_CNTL3               0x06C
+#define HHI_GP1_PLL_CNTL4               0x070
+#define HHI_GP1_PLL_CNTL5               0x074
+#define HHI_GP1_PLL_CNTL6               0x078
+#define HHI_GP1_PLL_STS                 0x07C
 #define HHI_PCIE_PLL_CNTL0              0x098
 #define HHI_PCIE_PLL_CNTL1              0x09C
 #define HHI_PCIE_PLL_CNTL2              0x0A0
@@ -72,6 +80,11 @@
 #define HHI_SYS_CPUB_CLK_CNTL1          0x200
 #define HHI_SYS_CPUB_CLK_CNTL           0x208
 #define HHI_VPU_CLKB_CNTL               0x20C
+#define HHI_SYS_CPU_CLK_CNTL2           0x210
+#define HHI_SYS_CPU_CLK_CNTL3           0x214
+#define HHI_SYS_CPU_CLK_CNTL4           0x218
+#define HHI_SYS_CPU_CLK_CNTL5           0x21c
+#define HHI_SYS_CPU_CLK_CNTL6           0x220
 #define HHI_GEN_CLK_CNTL                0x228
 #define HHI_VDIN_MEAS_CLK_CNTL          0x250
 #define HHI_MIPIDSI_PHY_CLK_CNTL        0x254
@@ -216,7 +229,6 @@
 #define CLKID_CPUB_CLK_DYN1_DIV                 221
 #define CLKID_CPUB_CLK_DYN1                     222
 #define CLKID_CPUB_CLK_DYN                      223
-#define CLKID_CPUB_CLK                          224
 #define CLKID_CPUB_CLK_DIV16_EN                 225
 #define CLKID_CPUB_CLK_DIV16                    226
 #define CLKID_CPUB_CLK_DIV2                     227
@@ -234,8 +246,17 @@
 #define CLKID_CPUB_CLK_AXI                      239
 #define CLKID_CPUB_CLK_TRACE_SEL                240
 #define CLKID_CPUB_CLK_TRACE                    241
+#define CLKID_GP1_PLL_DCO                       242
+#define CLKID_DSU_CLK_DYN0_SEL                  244
+#define CLKID_DSU_CLK_DYN0_DIV                  245
+#define CLKID_DSU_CLK_DYN0                      246
+#define CLKID_DSU_CLK_DYN1_SEL                  247
+#define CLKID_DSU_CLK_DYN1_DIV                  248
+#define CLKID_DSU_CLK_DYN1                      249
+#define CLKID_DSU_CLK_DYN                       250
+#define CLKID_DSU_CLK_FINAL                     251
 
-#define NR_CLKS                                 242
+#define NR_CLKS                                 256
 
 /* include the CLKIDs that have been made part of the DT binding */
 #include <dt-bindings/clock/g12a-clkc.h>
diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c
index 449f6ac189d8..e940861a396b 100644
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
@@ -11,8 +11,6 @@
 #include "clk-regmap.h"
 #include "clk-dualdiv.h"
 
-#define IN_PREFIX "ao-in-"
-
 /* AO Configuration Clock registers offsets */
 #define AO_RTI_PWR_CNTL_REG1    0x0c
 #define AO_RTI_PWR_CNTL_REG0    0x10
@@ -31,7 +29,9 @@ static struct clk_regmap _name##_ao = {					\
         .hw.init = &(struct clk_init_data) {                            \
                 .name = #_name "_ao",                                   \
                 .ops = &clk_regmap_gate_ops,                            \
-                .parent_names = (const char *[]){ IN_PREFIX "mpeg-clk" }, \
+                .parent_data = &(const struct clk_parent_data) {        \
+                        .fw_name = "mpeg-clk",                          \
+                },                                                      \
                 .num_parents = 1,                                       \
                 .flags = CLK_IGNORE_UNUSED,                             \
         },                                                              \
@@ -52,7 +52,9 @@ static struct clk_regmap ao_cts_oscin = {
         .hw.init = &(struct clk_init_data){
                 .name = "ao_cts_oscin",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
         },
 };
@@ -65,7 +67,7 @@ static struct clk_regmap ao_32k_pre = {
         .hw.init = &(struct clk_init_data){
                 .name = "ao_32k_pre",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "ao_cts_oscin" },
+                .parent_hws = (const struct clk_hw *[]) { &ao_cts_oscin.hw },
                 .num_parents = 1,
         },
 };
@@ -112,7 +114,7 @@ static struct clk_regmap ao_32k_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "ao_32k_div",
                 .ops = &meson_clk_dualdiv_ops,
-                .parent_names = (const char *[]){ "ao_32k_pre" },
+                .parent_hws = (const struct clk_hw *[]) { &ao_32k_pre.hw },
                 .num_parents = 1,
         },
 };
@@ -127,8 +129,10 @@ static struct clk_regmap ao_32k_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "ao_32k_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "ao_32k_div",
-                                                  "ao_32k_pre" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &ao_32k_div.hw,
+                        &ao_32k_pre.hw
+                },
                 .num_parents = 2,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -142,7 +146,7 @@ static struct clk_regmap ao_32k = {
         .hw.init = &(struct clk_init_data){
                 .name = "ao_32k",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "ao_32k_sel" },
+                .parent_hws = (const struct clk_hw *[]) { &ao_32k_sel.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -159,10 +163,12 @@ static struct clk_regmap ao_cts_rtc_oscin = {
         .hw.init = &(struct clk_init_data){
                 .name = "ao_cts_rtc_oscin",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "ext-32k-0",
-                                                  IN_PREFIX "ext-32k-1",
-                                                  IN_PREFIX "ext-32k-2",
-                                                  "ao_32k" },
+                .parent_data = (const struct clk_parent_data []) {
+                        { .fw_name = "ext-32k-0", },
+                        { .fw_name = "ext-32k-1", },
+                        { .fw_name = "ext-32k-2", },
+                        { .hw = &ao_32k.hw },
+                },
                 .num_parents = 4,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -178,8 +184,10 @@ static struct clk_regmap ao_clk81 = {
         .hw.init = &(struct clk_init_data){
                 .name = "ao_clk81",
                 .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "mpeg-clk",
-                                                  "ao_cts_rtc_oscin" },
+                .parent_data = (const struct clk_parent_data []) {
+                        { .fw_name = "mpeg-clk", },
+                        { .hw = &ao_cts_rtc_oscin.hw },
+                },
                 .num_parents = 2,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -208,8 +216,10 @@ static struct clk_regmap ao_cts_cec = {
                  * Until CCF gets fixed, adding this fake parent that won't
                  * ever be registered should work around the problem
                  */
-                .parent_names = (const char *[]){ "fixme",
-                                                  "ao_cts_rtc_oscin" },
+                .parent_data = (const struct clk_parent_data []) {
+                        { .name = "fixme", .index = -1, },
+                        { .hw = &ao_cts_rtc_oscin.hw },
+                },
                 .num_parents = 2,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -261,14 +271,6 @@ static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
         .num = NR_CLKS,
 };
 
-static const struct meson_aoclk_input gxbb_aoclk_inputs[] = {
-        { .name = "xtal",       .required = true,  },
-        { .name = "mpeg-clk",   .required = true,  },
-        {. name = "ext-32k-0",  .required = false, },
-        {. name = "ext-32k-1",  .required = false, },
-        {. name = "ext-32k-2",  .required = false, },
-};
-
 static const struct meson_aoclk_data gxbb_aoclkc_data = {
         .reset_reg      = AO_RTI_GEN_CNTL_REG0,
         .num_reset      = ARRAY_SIZE(gxbb_aoclk_reset),
@@ -276,9 +278,6 @@ static const struct meson_aoclk_data gxbb_aoclkc_data = {
         .num_clks       = ARRAY_SIZE(gxbb_aoclk),
         .clks           = gxbb_aoclk,
         .hw_data        = &gxbb_aoclk_onecell_data,
-        .inputs         = gxbb_aoclk_inputs,
-        .num_inputs     = ARRAY_SIZE(gxbb_aoclk_inputs),
-        .input_prefix   = IN_PREFIX,
 };
 
 static const struct of_device_id gxbb_aoclkc_match_table[] = {
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index dab16d9b1af8..7cfb998eeb3e 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -10,15 +10,12 @@
 #include <linux/platform_device.h>
 
 #include "gxbb.h"
-#include "clk-input.h"
 #include "clk-regmap.h"
 #include "clk-pll.h"
 #include "clk-mpll.h"
 #include "meson-eeclk.h"
 #include "vid-pll-div.h"
 
-#define IN_PREFIX "ee-in-"
-
 static DEFINE_SPINLOCK(meson_clk_lock);
 
 static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
@@ -121,7 +118,9 @@ static struct clk_regmap gxbb_fixed_pll_dco = {
         .hw.init = &(struct clk_init_data){
                 .name = "fixed_pll_dco",
                 .ops = &meson_clk_pll_ro_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
         },
 };
@@ -136,7 +135,9 @@ static struct clk_regmap gxbb_fixed_pll = {
         .hw.init = &(struct clk_init_data){
                 .name = "fixed_pll",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "fixed_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_fixed_pll_dco.hw
+                },
                 .num_parents = 1,
                 /*
                  * This clock won't ever change at runtime so
@@ -151,7 +152,9 @@ static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_pll_pre_mult",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
         },
 };
@@ -192,7 +195,9 @@ static struct clk_regmap gxbb_hdmi_pll_dco = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_pll_dco",
                 .ops = &meson_clk_pll_ro_ops,
-                .parent_names = (const char *[]){ "hdmi_pll_pre_mult" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_hdmi_pll_pre_mult.hw
+                },
                 .num_parents = 1,
                 /*
                  * Display directly handle hdmi pll registers ATM, we need
@@ -244,7 +249,9 @@ static struct clk_regmap gxl_hdmi_pll_dco = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_pll_dco",
                 .ops = &meson_clk_pll_ro_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
                 /*
                  * Display directly handle hdmi pll registers ATM, we need
@@ -264,7 +271,9 @@ static struct clk_regmap gxbb_hdmi_pll_od = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_pll_od",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "hdmi_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_hdmi_pll_dco.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
         },
@@ -280,7 +289,9 @@ static struct clk_regmap gxbb_hdmi_pll_od2 = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_pll_od2",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "hdmi_pll_od" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_hdmi_pll_od.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
         },
@@ -296,7 +307,9 @@ static struct clk_regmap gxbb_hdmi_pll = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_pll",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "hdmi_pll_od2" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_hdmi_pll_od2.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
         },
@@ -312,7 +325,9 @@ static struct clk_regmap gxl_hdmi_pll_od = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_pll_od",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "hdmi_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxl_hdmi_pll_dco.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
         },
@@ -328,7 +343,9 @@ static struct clk_regmap gxl_hdmi_pll_od2 = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_pll_od2",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "hdmi_pll_od" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxl_hdmi_pll_od.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
         },
@@ -344,7 +361,9 @@ static struct clk_regmap gxl_hdmi_pll = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_pll",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "hdmi_pll_od2" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxl_hdmi_pll_od2.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
         },
@@ -381,7 +400,9 @@ static struct clk_regmap gxbb_sys_pll_dco = {
         .hw.init = &(struct clk_init_data){
                 .name = "sys_pll_dco",
                 .ops = &meson_clk_pll_ro_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
         },
 };
@@ -396,7 +417,9 @@ static struct clk_regmap gxbb_sys_pll = {
         .hw.init = &(struct clk_init_data){
                 .name = "sys_pll",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "sys_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_sys_pll_dco.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -442,7 +465,9 @@ static struct clk_regmap gxbb_gp0_pll_dco = {
         .hw.init = &(struct clk_init_data){
                 .name = "gp0_pll_dco",
                 .ops = &meson_clk_pll_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
         },
 };
@@ -494,7 +519,9 @@ static struct clk_regmap gxl_gp0_pll_dco = {
         .hw.init = &(struct clk_init_data){
                 .name = "gp0_pll_dco",
                 .ops = &meson_clk_pll_ops,
-                .parent_names = (const char *[]){ IN_PREFIX "xtal" },
+                .parent_data = &(const struct clk_parent_data) {
+                        .fw_name = "xtal",
+                },
                 .num_parents = 1,
         },
 };
@@ -509,7 +536,17 @@ static struct clk_regmap gxbb_gp0_pll = {
         .hw.init = &(struct clk_init_data){
                 .name = "gp0_pll",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "gp0_pll_dco" },
+                .parent_data = &(const struct clk_parent_data) {
+                        /*
+                         * Note:
+                         * GXL and GXBB have different gp0_pll_dco (with
+                         * different struct clk_hw). We fallback to the global
+                         * naming string mechanism so gp0_pll picks up the
+                         * appropriate one.
+                         */
+                        .name = "gp0_pll_dco",
+                        .index = -1,
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -521,7 +558,9 @@ static struct clk_fixed_factor gxbb_fclk_div2_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div2_div",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_fixed_pll.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -534,7 +573,9 @@ static struct clk_regmap gxbb_fclk_div2 = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div2",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div2_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_fclk_div2_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_IS_CRITICAL,
         },
@@ -546,7 +587,7 @@ static struct clk_fixed_factor gxbb_fclk_div3_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div3_div",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
                 .num_parents = 1,
         },
 };
@@ -559,7 +600,9 @@ static struct clk_regmap gxbb_fclk_div3 = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div3",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div3_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_fclk_div3_div.hw
+                },
                 .num_parents = 1,
                 /*
                  * FIXME:
@@ -582,7 +625,7 @@ static struct clk_fixed_factor gxbb_fclk_div4_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div4_div",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
                 .num_parents = 1,
         },
 };
@@ -595,7 +638,9 @@ static struct clk_regmap gxbb_fclk_div4 = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div4",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div4_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_fclk_div4_div.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -606,7 +651,7 @@ static struct clk_fixed_factor gxbb_fclk_div5_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div5_div",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
                 .num_parents = 1,
         },
 };
@@ -619,7 +664,9 @@ static struct clk_regmap gxbb_fclk_div5 = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div5",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div5_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_fclk_div5_div.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -630,7 +677,7 @@ static struct clk_fixed_factor gxbb_fclk_div7_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div7_div",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
                 .num_parents = 1,
         },
 };
@@ -643,7 +690,9 @@ static struct clk_regmap gxbb_fclk_div7 = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div7",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div7_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_fclk_div7_div.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -657,7 +706,7 @@ static struct clk_regmap gxbb_mpll_prediv = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll_prediv",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
                 .num_parents = 1,
         },
 };
@@ -684,7 +733,9 @@ static struct clk_regmap gxbb_mpll0_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll0_div",
                 .ops = &meson_clk_mpll_ops,
-                .parent_names = (const char *[]){ "mpll_prediv" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_mpll_prediv.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -697,7 +748,7 @@ static struct clk_regmap gxbb_mpll0 = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mpll0_div" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll0_div.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -725,7 +776,9 @@ static struct clk_regmap gxbb_mpll1_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll1_div",
                 .ops = &meson_clk_mpll_ops,
-                .parent_names = (const char *[]){ "mpll_prediv" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_mpll_prediv.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -738,7 +791,7 @@ static struct clk_regmap gxbb_mpll1 = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll1",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mpll1_div" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -766,7 +819,9 @@ static struct clk_regmap gxbb_mpll2_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll2_div",
                 .ops = &meson_clk_mpll_ops,
-                .parent_names = (const char *[]){ "mpll_prediv" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_mpll_prediv.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -779,16 +834,21 @@ static struct clk_regmap gxbb_mpll2 = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll2",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mpll2_div" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
 
 static u32 mux_table_clk81[]    = { 0, 2, 3, 4, 5, 6, 7 };
-static const char * const clk81_parent_names[] = {
-        IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
-        "fclk_div3", "fclk_div5"
+static const struct clk_parent_data clk81_parent_data[] = {
+        { .fw_name = "xtal", },
+        { .hw = &gxbb_fclk_div7.hw },
+        { .hw = &gxbb_mpll1.hw },
+        { .hw = &gxbb_mpll2.hw },
+        { .hw = &gxbb_fclk_div4.hw },
+        { .hw = &gxbb_fclk_div3.hw },
+        { .hw = &gxbb_fclk_div5.hw },
 };
 
 static struct clk_regmap gxbb_mpeg_clk_sel = {
@@ -806,8 +866,8 @@ static struct clk_regmap gxbb_mpeg_clk_sel = {
                  * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
                  * fclk_div4, fclk_div3, fclk_div5
                  */
-                .parent_names = clk81_parent_names,
-                .num_parents = ARRAY_SIZE(clk81_parent_names),
+                .parent_data = clk81_parent_data,
+                .num_parents = ARRAY_SIZE(clk81_parent_data),
         },
 };
 
@@ -820,7 +880,9 @@ static struct clk_regmap gxbb_mpeg_clk_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpeg_clk_div",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "mpeg_clk_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_mpeg_clk_sel.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -834,7 +896,9 @@ static struct clk_regmap gxbb_clk81 = {
         .hw.init = &(struct clk_init_data){
                 .name = "clk81",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mpeg_clk_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_mpeg_clk_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_IS_CRITICAL,
         },
@@ -850,7 +914,10 @@ static struct clk_regmap gxbb_sar_adc_clk_sel = {
                 .name = "sar_adc_clk_sel",
                 .ops = &clk_regmap_mux_ops,
                 /* NOTE: The datasheet doesn't list the parents for bit 10 */
-                .parent_names = (const char *[]){ IN_PREFIX "xtal", "clk81", },
+                .parent_data = (const struct clk_parent_data []) {
+                        { .fw_name = "xtal", },
+                        { .hw = &gxbb_clk81.hw },
+                },
                 .num_parents = 2,
         },
 };
@@ -864,7 +931,9 @@ static struct clk_regmap gxbb_sar_adc_clk_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "sar_adc_clk_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "sar_adc_clk_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_sar_adc_clk_sel.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -877,7 +946,9 @@ static struct clk_regmap gxbb_sar_adc_clk = {
         .hw.init = &(struct clk_init_data){
                 .name = "sar_adc_clk",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "sar_adc_clk_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_sar_adc_clk_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -888,9 +959,15 @@ static struct clk_regmap gxbb_sar_adc_clk = {
  * muxed by a glitch-free switch.
  */
 
-static const char * const gxbb_mali_0_1_parent_names[] = {
-        IN_PREFIX "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
-        "fclk_div4", "fclk_div3", "fclk_div5"
+static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = {
+        { .fw_name = "xtal", },
+        { .hw = &gxbb_gp0_pll.hw },
+        { .hw = &gxbb_mpll2.hw },
+        { .hw = &gxbb_mpll1.hw },
+        { .hw = &gxbb_fclk_div7.hw },
+        { .hw = &gxbb_fclk_div4.hw },
+        { .hw = &gxbb_fclk_div3.hw },
+        { .hw = &gxbb_fclk_div5.hw },
 };
 
 static struct clk_regmap gxbb_mali_0_sel = {
@@ -907,7 +984,7 @@ static struct clk_regmap gxbb_mali_0_sel = {
                  * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
                  * fclk_div4, fclk_div3, fclk_div5
                  */
-                .parent_names = gxbb_mali_0_1_parent_names,
+                .parent_data = gxbb_mali_0_1_parent_data,
                 .num_parents = 8,
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
@@ -922,7 +999,9 @@ static struct clk_regmap gxbb_mali_0_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mali_0_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "mali_0_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_mali_0_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
@@ -936,7 +1015,9 @@ static struct clk_regmap gxbb_mali_0 = {
         .hw.init = &(struct clk_init_data){
                 .name = "mali_0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mali_0_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_mali_0_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -956,7 +1037,7 @@ static struct clk_regmap gxbb_mali_1_sel = {
                  * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
                  * fclk_div4, fclk_div3, fclk_div5
                  */
-                .parent_names = gxbb_mali_0_1_parent_names,
+                .parent_data = gxbb_mali_0_1_parent_data,
                 .num_parents = 8,
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
@@ -971,7 +1052,9 @@ static struct clk_regmap gxbb_mali_1_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mali_1_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "mali_1_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_mali_1_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
@@ -985,14 +1068,17 @@ static struct clk_regmap gxbb_mali_1 = {
         .hw.init = &(struct clk_init_data){
                 .name = "mali_1",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mali_1_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_mali_1_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
 
-static const char * const gxbb_mali_parent_names[] = {
-        "mali_0", "mali_1"
+static const struct clk_hw *gxbb_mali_parent_hws[] = {
+        &gxbb_mali_0.hw,
+        &gxbb_mali_1.hw,
 };
 
 static struct clk_regmap gxbb_mali = {
@@ -1004,7 +1090,7 @@ static struct clk_regmap gxbb_mali = {
         .hw.init = &(struct clk_init_data){
                 .name = "mali",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = gxbb_mali_parent_names,
+                .parent_hws = gxbb_mali_parent_hws,
                 .num_parents = 2,
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
@@ -1021,7 +1107,11 @@ static struct clk_regmap gxbb_cts_amclk_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_amclk_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_mpll0.hw,
+                        &gxbb_mpll1.hw,
+                        &gxbb_mpll2.hw,
+                },
                 .num_parents = 3,
         },
 };
@@ -1036,7 +1126,9 @@ static struct clk_regmap gxbb_cts_amclk_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_amclk_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "cts_amclk_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_cts_amclk_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1050,7 +1142,9 @@ static struct clk_regmap gxbb_cts_amclk = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_amclk",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "cts_amclk_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_cts_amclk_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1067,7 +1161,11 @@ static struct clk_regmap gxbb_cts_mclk_i958_sel = {
         .hw.init = &(struct clk_init_data) {
                 .name = "cts_mclk_i958_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_mpll0.hw,
+                        &gxbb_mpll1.hw,
+                        &gxbb_mpll2.hw,
+                },
                 .num_parents = 3,
         },
 };
@@ -1082,7 +1180,9 @@ static struct clk_regmap gxbb_cts_mclk_i958_div = {
         .hw.init = &(struct clk_init_data) {
                 .name = "cts_mclk_i958_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "cts_mclk_i958_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_cts_mclk_i958_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1096,7 +1196,9 @@ static struct clk_regmap gxbb_cts_mclk_i958 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_mclk_i958",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "cts_mclk_i958_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_cts_mclk_i958_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1111,7 +1213,10 @@ static struct clk_regmap gxbb_cts_i958 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_i958",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_cts_amclk.hw,
+                        &gxbb_cts_mclk_i958.hw
+                },
                 .num_parents = 2,
                 /*
                  *The parent is specific to origin of the audio data. Let the
@@ -1121,6 +1226,33 @@ static struct clk_regmap gxbb_cts_i958 = {
         },
 };
 
+static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {
+        { .fw_name = "xtal", },
+        /*
+         * FIXME: This clock is provided by the ao clock controller but the
+         * clock is not yet part of the binding of this controller, so string
+         * name must be use to set this parent.
+         */
+        { .name = "cts_slow_oscin", .index = -1 },
+        { .hw = &gxbb_fclk_div3.hw },
+        { .hw = &gxbb_fclk_div5.hw },
+};
+
+static struct clk_regmap gxbb_32k_clk_sel = {
+        .data = &(struct clk_regmap_mux_data){
+                .offset = HHI_32K_CLK_CNTL,
+                .mask = 0x3,
+                .shift = 16,
+                },
+        .hw.init = &(struct clk_init_data){
+                .name = "32k_clk_sel",
+                .ops = &clk_regmap_mux_ops,
+                .parent_data = gxbb_32k_clk_parent_data,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+        },
+};
+
 static struct clk_regmap gxbb_32k_clk_div = {
         .data = &(struct clk_regmap_div_data){
                 .offset = HHI_32K_CLK_CNTL,
@@ -1130,7 +1262,9 @@ static struct clk_regmap gxbb_32k_clk_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "32k_clk_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "32k_clk_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_32k_clk_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
         },
@@ -1144,34 +1278,20 @@ static struct clk_regmap gxbb_32k_clk = {
         .hw.init = &(struct clk_init_data){
                 .name = "32k_clk",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "32k_clk_div" },
-                .num_parents = 1,
-                .flags = CLK_SET_RATE_PARENT,
-        },
-};
-
-static const char * const gxbb_32k_clk_parent_names[] = {
-        IN_PREFIX "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
-};
-
-static struct clk_regmap gxbb_32k_clk_sel = {
-        .data = &(struct clk_regmap_mux_data){
-                .offset = HHI_32K_CLK_CNTL,
-                .mask = 0x3,
-                .shift = 16,
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_32k_clk_div.hw
                 },
-        .hw.init = &(struct clk_init_data){
-                .name = "32k_clk_sel",
-                .ops = &clk_regmap_mux_ops,
-                .parent_names = gxbb_32k_clk_parent_names,
-                .num_parents = 4,
+                .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
 
-static const char * const gxbb_sd_emmc_clk0_parent_names[] = {
-        IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
-
+static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = {
+        { .fw_name = "xtal", },
+        { .hw = &gxbb_fclk_div2.hw },
+        { .hw = &gxbb_fclk_div3.hw },
+        { .hw = &gxbb_fclk_div5.hw },
+        { .hw = &gxbb_fclk_div7.hw },
         /*
          * Following these parent clocks, we should also have had mpll2, mpll3
          * and gp0_pll but these clocks are too precious to be used here. All
@@ -1190,8 +1310,8 @@ static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
         .hw.init = &(struct clk_init_data) {
                 .name = "sd_emmc_a_clk0_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = gxbb_sd_emmc_clk0_parent_names,
-                .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
+                .parent_data = gxbb_sd_emmc_clk0_parent_data,
+                .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -1206,7 +1326,9 @@ static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
         .hw.init = &(struct clk_init_data) {
                 .name = "sd_emmc_a_clk0_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_sd_emmc_a_clk0_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1220,7 +1342,9 @@ static struct clk_regmap gxbb_sd_emmc_a_clk0 = {
         .hw.init = &(struct clk_init_data){
                 .name = "sd_emmc_a_clk0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_sd_emmc_a_clk0_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1236,8 +1360,8 @@ static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
         .hw.init = &(struct clk_init_data) {
                 .name = "sd_emmc_b_clk0_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = gxbb_sd_emmc_clk0_parent_names,
-                .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
+                .parent_data = gxbb_sd_emmc_clk0_parent_data,
+                .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -1252,7 +1376,9 @@ static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
         .hw.init = &(struct clk_init_data) {
                 .name = "sd_emmc_b_clk0_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_sd_emmc_b_clk0_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1266,7 +1392,9 @@ static struct clk_regmap gxbb_sd_emmc_b_clk0 = {
         .hw.init = &(struct clk_init_data){
                 .name = "sd_emmc_b_clk0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_sd_emmc_b_clk0_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1282,8 +1410,8 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
         .hw.init = &(struct clk_init_data) {
                 .name = "sd_emmc_c_clk0_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = gxbb_sd_emmc_clk0_parent_names,
-                .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
+                .parent_data = gxbb_sd_emmc_clk0_parent_data,
+                .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -1298,7 +1426,9 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
         .hw.init = &(struct clk_init_data) {
                 .name = "sd_emmc_c_clk0_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_sd_emmc_c_clk0_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1312,7 +1442,9 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
         .hw.init = &(struct clk_init_data){
                 .name = "sd_emmc_c_clk0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_sd_emmc_c_clk0_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1320,8 +1452,11 @@ static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
 
 /* VPU Clock */
 
-static const char * const gxbb_vpu_parent_names[] = {
-        "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
+static const struct clk_hw *gxbb_vpu_parent_hws[] = {
+        &gxbb_fclk_div4.hw,
+        &gxbb_fclk_div3.hw,
+        &gxbb_fclk_div5.hw,
+        &gxbb_fclk_div7.hw,
 };
 
 static struct clk_regmap gxbb_vpu_0_sel = {
@@ -1337,8 +1472,8 @@ static struct clk_regmap gxbb_vpu_0_sel = {
                  * bits 9:10 selects from 4 possible parents:
                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
                  */
-                .parent_names = gxbb_vpu_parent_names,
-                .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
+                .parent_hws = gxbb_vpu_parent_hws,
+                .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
 };
@@ -1352,7 +1487,7 @@ static struct clk_regmap gxbb_vpu_0_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vpu_0_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vpu_0_sel" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1366,7 +1501,7 @@ static struct clk_regmap gxbb_vpu_0 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vpu_0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vpu_0_div" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -1385,8 +1520,8 @@ static struct clk_regmap gxbb_vpu_1_sel = {
                  * bits 25:26 selects from 4 possible parents:
                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
                  */
-                .parent_names = gxbb_vpu_parent_names,
-                .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
+                .parent_hws = gxbb_vpu_parent_hws,
+                .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
 };
@@ -1400,7 +1535,7 @@ static struct clk_regmap gxbb_vpu_1_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vpu_1_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vpu_1_sel" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1414,7 +1549,7 @@ static struct clk_regmap gxbb_vpu_1 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vpu_1",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vpu_1_div" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -1433,7 +1568,10 @@ static struct clk_regmap gxbb_vpu = {
                  * bit 31 selects from 2 possible parents:
                  * vpu_0 or vpu_1
                  */
-                .parent_names = (const char *[]){ "vpu_0", "vpu_1" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vpu_0.hw,
+                        &gxbb_vpu_1.hw
+                },
                 .num_parents = 2,
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
@@ -1441,8 +1579,11 @@ static struct clk_regmap gxbb_vpu = {
 
 /* VAPB Clock */
 
-static const char * const gxbb_vapb_parent_names[] = {
-        "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
+static const struct clk_hw *gxbb_vapb_parent_hws[] = {
+        &gxbb_fclk_div4.hw,
+        &gxbb_fclk_div3.hw,
+        &gxbb_fclk_div5.hw,
+        &gxbb_fclk_div7.hw,
 };
 
 static struct clk_regmap gxbb_vapb_0_sel = {
@@ -1458,8 +1599,8 @@ static struct clk_regmap gxbb_vapb_0_sel = {
                  * bits 9:10 selects from 4 possible parents:
                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
                  */
-                .parent_names = gxbb_vapb_parent_names,
-                .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
+                .parent_hws = gxbb_vapb_parent_hws,
+                .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
 };
@@ -1473,7 +1614,9 @@ static struct clk_regmap gxbb_vapb_0_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vapb_0_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vapb_0_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vapb_0_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1487,7 +1630,9 @@ static struct clk_regmap gxbb_vapb_0 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vapb_0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vapb_0_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vapb_0_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -1506,8 +1651,8 @@ static struct clk_regmap gxbb_vapb_1_sel = {
                  * bits 25:26 selects from 4 possible parents:
                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
                  */
-                .parent_names = gxbb_vapb_parent_names,
-                .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
+                .parent_hws = gxbb_vapb_parent_hws,
+                .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
 };
@@ -1521,7 +1666,9 @@ static struct clk_regmap gxbb_vapb_1_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vapb_1_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vapb_1_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vapb_1_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1535,7 +1682,9 @@ static struct clk_regmap gxbb_vapb_1 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vapb_1",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vapb_1_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vapb_1_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -1554,7 +1703,10 @@ static struct clk_regmap gxbb_vapb_sel = {
                  * bit 31 selects from 2 possible parents:
                  * vapb_0 or vapb_1
                  */
-                .parent_names = (const char *[]){ "vapb_0", "vapb_1" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vapb_0.hw,
+                        &gxbb_vapb_1.hw
+                },
                 .num_parents = 2,
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
@@ -1568,7 +1720,7 @@ static struct clk_regmap gxbb_vapb = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vapb",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vapb_sel" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -1592,13 +1744,33 @@ static struct clk_regmap gxbb_vid_pll_div = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vid_pll_div",
                 .ops = &meson_vid_pll_div_ro_ops,
-                .parent_names = (const char *[]){ "hdmi_pll" },
+                .parent_data = &(const struct clk_parent_data) {
+                        /*
+                         * Note:
+                         * GXL and GXBB have different hdmi_plls (with
+                         * different struct clk_hw). We fallback to the global
+                         * naming string mechanism so vid_pll_div picks up the
+                         * appropriate one.
+                         */
+                        .name = "hdmi_pll",
+                        .index = -1,
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
         },
 };
 
-static const char * const gxbb_vid_pll_parent_names[] = { "vid_pll_div", "hdmi_pll" };
+static const struct clk_parent_data gxbb_vid_pll_parent_data[] = {
+        { .hw = &gxbb_vid_pll_div.hw },
+        /*
+         * Note:
+         * GXL and GXBB have different hdmi_plls (with
+         * different struct clk_hw). We fallback to the global
+         * naming string mechanism so vid_pll_div picks up the
+         * appropriate one.
+         */
+        { .name = "hdmi_pll", .index = -1 },
+};
 
 static struct clk_regmap gxbb_vid_pll_sel = {
         .data = &(struct clk_regmap_mux_data){
@@ -1613,8 +1785,8 @@ static struct clk_regmap gxbb_vid_pll_sel = {
                  * bit 18 selects from 2 possible parents:
                  * vid_pll_div or hdmi_pll
                  */
-                .parent_names = gxbb_vid_pll_parent_names,
-                .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_names),
+                .parent_data = gxbb_vid_pll_parent_data,
+                .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data),
                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
         },
 };
@@ -1627,15 +1799,22 @@ static struct clk_regmap gxbb_vid_pll = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vid_pll",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vid_pll_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vid_pll_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
 };
 
-static const char * const gxbb_vclk_parent_names[] = {
-        "vid_pll", "fclk_div4", "fclk_div3", "fclk_div5", "vid_pll",
-        "fclk_div7", "mpll1",
+static const struct clk_hw *gxbb_vclk_parent_hws[] = {
+        &gxbb_vid_pll.hw,
+        &gxbb_fclk_div4.hw,
+        &gxbb_fclk_div3.hw,
+        &gxbb_fclk_div5.hw,
+        &gxbb_vid_pll.hw,
+        &gxbb_fclk_div7.hw,
+        &gxbb_mpll1.hw,
 };
 
 static struct clk_regmap gxbb_vclk_sel = {
@@ -1652,8 +1831,8 @@ static struct clk_regmap gxbb_vclk_sel = {
                  * vid_pll, fclk_div4, fclk_div3, fclk_div5,
                  * vid_pll, fclk_div7, mp1
                  */
-                .parent_names = gxbb_vclk_parent_names,
-                .num_parents = ARRAY_SIZE(gxbb_vclk_parent_names),
+                .parent_hws = gxbb_vclk_parent_hws,
+                .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
         },
 };
@@ -1672,8 +1851,8 @@ static struct clk_regmap gxbb_vclk2_sel = {
                  * vid_pll, fclk_div4, fclk_div3, fclk_div5,
                  * vid_pll, fclk_div7, mp1
                  */
-                .parent_names = gxbb_vclk_parent_names,
-                .num_parents = ARRAY_SIZE(gxbb_vclk_parent_names),
+                .parent_hws = gxbb_vclk_parent_hws,
+                .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
         },
 };
@@ -1686,7 +1865,7 @@ static struct clk_regmap gxbb_vclk_input = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk_input",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk_sel" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -1700,7 +1879,7 @@ static struct clk_regmap gxbb_vclk2_input = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk2_input",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk2_sel" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -1715,7 +1894,9 @@ static struct clk_regmap gxbb_vclk_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vclk_input" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vclk_input.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_GET_RATE_NOCACHE,
         },
@@ -1730,7 +1911,9 @@ static struct clk_regmap gxbb_vclk2_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vclk2_input" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vclk2_input.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_GET_RATE_NOCACHE,
         },
@@ -1744,7 +1927,7 @@ static struct clk_regmap gxbb_vclk = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk_div" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -1758,7 +1941,7 @@ static struct clk_regmap gxbb_vclk2 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk2",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk2_div" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -1772,7 +1955,7 @@ static struct clk_regmap gxbb_vclk_div1 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk_div1",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -1786,7 +1969,7 @@ static struct clk_regmap gxbb_vclk_div2_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk_div2_en",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -1800,7 +1983,7 @@ static struct clk_regmap gxbb_vclk_div4_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk_div4_en",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -1814,7 +1997,7 @@ static struct clk_regmap gxbb_vclk_div6_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk_div6_en",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -1828,7 +2011,7 @@ static struct clk_regmap gxbb_vclk_div12_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk_div12_en",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -1842,7 +2025,7 @@ static struct clk_regmap gxbb_vclk2_div1 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk2_div1",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk2" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -1856,7 +2039,7 @@ static struct clk_regmap gxbb_vclk2_div2_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk2_div2_en",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk2" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -1870,7 +2053,7 @@ static struct clk_regmap gxbb_vclk2_div4_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk2_div4_en",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk2" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -1884,7 +2067,7 @@ static struct clk_regmap gxbb_vclk2_div6_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk2_div6_en",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk2" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -1898,7 +2081,7 @@ static struct clk_regmap gxbb_vclk2_div12_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vclk2_div12_en",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vclk2" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -1910,7 +2093,9 @@ static struct clk_fixed_factor gxbb_vclk_div2 = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_div2",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk_div2_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vclk_div2_en.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -1921,7 +2106,9 @@ static struct clk_fixed_factor gxbb_vclk_div4 = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_div4",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk_div4_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vclk_div4_en.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -1932,7 +2119,9 @@ static struct clk_fixed_factor gxbb_vclk_div6 = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_div6",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk_div6_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vclk_div6_en.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -1943,7 +2132,9 @@ static struct clk_fixed_factor gxbb_vclk_div12 = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_div12",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk_div12_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vclk_div12_en.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -1954,7 +2145,9 @@ static struct clk_fixed_factor gxbb_vclk2_div2 = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_div2",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk2_div2_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vclk2_div2_en.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -1965,7 +2158,9 @@ static struct clk_fixed_factor gxbb_vclk2_div4 = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_div4",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk2_div4_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vclk2_div4_en.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -1976,7 +2171,9 @@ static struct clk_fixed_factor gxbb_vclk2_div6 = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_div6",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk2_div6_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vclk2_div6_en.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -1987,16 +2184,25 @@ static struct clk_fixed_factor gxbb_vclk2_div12 = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_div12",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk2_div12_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vclk2_div12_en.hw
+                },
                 .num_parents = 1,
         },
 };
 
 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
-static const char * const gxbb_cts_parent_names[] = {
-        "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
-        "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
-        "vclk2_div6", "vclk2_div12"
+static const struct clk_hw *gxbb_cts_parent_hws[] = {
+        &gxbb_vclk_div1.hw,
+        &gxbb_vclk_div2.hw,
+        &gxbb_vclk_div4.hw,
+        &gxbb_vclk_div6.hw,
+        &gxbb_vclk_div12.hw,
+        &gxbb_vclk2_div1.hw,
+        &gxbb_vclk2_div2.hw,
+        &gxbb_vclk2_div4.hw,
+        &gxbb_vclk2_div6.hw,
+        &gxbb_vclk2_div12.hw,
 };
 
 static struct clk_regmap gxbb_cts_enci_sel = {
@@ -2009,8 +2215,8 @@ static struct clk_regmap gxbb_cts_enci_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_enci_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = gxbb_cts_parent_names,
-                .num_parents = ARRAY_SIZE(gxbb_cts_parent_names),
+                .parent_hws = gxbb_cts_parent_hws,
+                .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
         },
 };
@@ -2025,8 +2231,8 @@ static struct clk_regmap gxbb_cts_encp_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_encp_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = gxbb_cts_parent_names,
-                .num_parents = ARRAY_SIZE(gxbb_cts_parent_names),
+                .parent_hws = gxbb_cts_parent_hws,
+                .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
         },
 };
@@ -2041,18 +2247,25 @@ static struct clk_regmap gxbb_cts_vdac_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_vdac_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = gxbb_cts_parent_names,
-                .num_parents = ARRAY_SIZE(gxbb_cts_parent_names),
+                .parent_hws = gxbb_cts_parent_hws,
+                .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
         },
 };
 
 /* TOFIX: add support for cts_tcon */
 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
-static const char * const gxbb_cts_hdmi_tx_parent_names[] = {
-        "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
-        "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
-        "vclk2_div6", "vclk2_div12"
+static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = {
+        &gxbb_vclk_div1.hw,
+        &gxbb_vclk_div2.hw,
+        &gxbb_vclk_div4.hw,
+        &gxbb_vclk_div6.hw,
+        &gxbb_vclk_div12.hw,
+        &gxbb_vclk2_div1.hw,
+        &gxbb_vclk2_div2.hw,
+        &gxbb_vclk2_div4.hw,
+        &gxbb_vclk2_div6.hw,
+        &gxbb_vclk2_div12.hw,
 };
 
 static struct clk_regmap gxbb_hdmi_tx_sel = {
@@ -2071,8 +2284,8 @@ static struct clk_regmap gxbb_hdmi_tx_sel = {
                  * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
                  * cts_tcon
                  */
-                .parent_names = gxbb_cts_hdmi_tx_parent_names,
-                .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_names),
+                .parent_hws = gxbb_cts_hdmi_tx_parent_hws,
+                .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws),
                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
         },
 };
@@ -2085,7 +2298,9 @@ static struct clk_regmap gxbb_cts_enci = {
         .hw.init = &(struct clk_init_data) {
                 .name = "cts_enci",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "cts_enci_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_cts_enci_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2099,7 +2314,9 @@ static struct clk_regmap gxbb_cts_encp = {
         .hw.init = &(struct clk_init_data) {
                 .name = "cts_encp",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "cts_encp_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_cts_encp_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2113,7 +2330,9 @@ static struct clk_regmap gxbb_cts_vdac = {
         .hw.init = &(struct clk_init_data) {
                 .name = "cts_vdac",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "cts_vdac_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_cts_vdac_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2127,7 +2346,9 @@ static struct clk_regmap gxbb_hdmi_tx = {
         .hw.init = &(struct clk_init_data) {
                 .name = "hdmi_tx",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "hdmi_tx_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_hdmi_tx_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2135,8 +2356,11 @@ static struct clk_regmap gxbb_hdmi_tx = {
 
 /* HDMI Clocks */
 
-static const char * const gxbb_hdmi_parent_names[] = {
-        IN_PREFIX "xtal", "fclk_div4", "fclk_div3", "fclk_div5"
+static const struct clk_parent_data gxbb_hdmi_parent_data[] = {
+        { .fw_name = "xtal", },
+        { .hw = &gxbb_fclk_div4.hw },
+        { .hw = &gxbb_fclk_div3.hw },
+        { .hw = &gxbb_fclk_div5.hw },
 };
 
 static struct clk_regmap gxbb_hdmi_sel = {
@@ -2149,8 +2373,8 @@ static struct clk_regmap gxbb_hdmi_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = gxbb_hdmi_parent_names,
-                .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_names),
+                .parent_data = gxbb_hdmi_parent_data,
+                .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data),
                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
         },
 };
@@ -2164,7 +2388,7 @@ static struct clk_regmap gxbb_hdmi_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "hdmi_sel" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw },
                 .num_parents = 1,
                 .flags = CLK_GET_RATE_NOCACHE,
         },
@@ -2178,7 +2402,7 @@ static struct clk_regmap gxbb_hdmi = {
         .hw.init = &(struct clk_init_data) {
                 .name = "hdmi",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "hdmi_div" },
+                .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
         },
@@ -2186,8 +2410,11 @@ static struct clk_regmap gxbb_hdmi = {
 
 /* VDEC clocks */
 
-static const char * const gxbb_vdec_parent_names[] = {
-        "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
+static const struct clk_hw *gxbb_vdec_parent_hws[] = {
+        &gxbb_fclk_div4.hw,
+        &gxbb_fclk_div3.hw,
+        &gxbb_fclk_div5.hw,
+        &gxbb_fclk_div7.hw,
 };
 
 static struct clk_regmap gxbb_vdec_1_sel = {
@@ -2200,8 +2427,8 @@ static struct clk_regmap gxbb_vdec_1_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vdec_1_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = gxbb_vdec_parent_names,
-                .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
+                .parent_hws = gxbb_vdec_parent_hws,
+                .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -2216,7 +2443,9 @@ static struct clk_regmap gxbb_vdec_1_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vdec_1_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vdec_1_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vdec_1_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2230,7 +2459,9 @@ static struct clk_regmap gxbb_vdec_1 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vdec_1",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vdec_1_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vdec_1_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2246,8 +2477,8 @@ static struct clk_regmap gxbb_vdec_hevc_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vdec_hevc_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = gxbb_vdec_parent_names,
-                .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
+                .parent_hws = gxbb_vdec_parent_hws,
+                .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -2262,7 +2493,9 @@ static struct clk_regmap gxbb_vdec_hevc_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vdec_hevc_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vdec_hevc_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vdec_hevc_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2276,7 +2509,9 @@ static struct clk_regmap gxbb_vdec_hevc = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vdec_hevc",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vdec_hevc_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_vdec_hevc_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2284,9 +2519,18 @@ static struct clk_regmap gxbb_vdec_hevc = {
 
 static u32 mux_table_gen_clk[]  = { 0, 4, 5, 6, 7, 8,
                                     9, 10, 11, 13, 14, };
-static const char * const gen_clk_parent_names[] = {
-        IN_PREFIX "xtal", "vdec_1", "vdec_hevc", "mpll0", "mpll1", "mpll2",
-        "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
+static const struct clk_parent_data gen_clk_parent_data[] = {
+        { .fw_name = "xtal", },
+        { .hw = &gxbb_vdec_1.hw },
+        { .hw = &gxbb_vdec_hevc.hw },
+        { .hw = &gxbb_mpll0.hw },
+        { .hw = &gxbb_mpll1.hw },
+        { .hw = &gxbb_mpll2.hw },
+        { .hw = &gxbb_fclk_div4.hw },
+        { .hw = &gxbb_fclk_div3.hw },
+        { .hw = &gxbb_fclk_div5.hw },
+        { .hw = &gxbb_fclk_div7.hw },
+        { .hw = &gxbb_gp0_pll.hw },
 };
 
 static struct clk_regmap gxbb_gen_clk_sel = {
@@ -2305,8 +2549,8 @@ static struct clk_regmap gxbb_gen_clk_sel = {
                  * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
                  * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
                  */
-                .parent_names = gen_clk_parent_names,
-                .num_parents = ARRAY_SIZE(gen_clk_parent_names),
+                .parent_data = gen_clk_parent_data,
+                .num_parents = ARRAY_SIZE(gen_clk_parent_data),
         },
 };
 
@@ -2319,7 +2563,9 @@ static struct clk_regmap gxbb_gen_clk_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "gen_clk_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "gen_clk_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_gen_clk_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2333,12 +2579,17 @@ static struct clk_regmap gxbb_gen_clk = {
         .hw.init = &(struct clk_init_data){
                 .name = "gen_clk",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "gen_clk_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &gxbb_gen_clk_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
 
+#define MESON_GATE(_name, _reg, _bit) \
+        MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)
+
 /* Everything Else (EE) domain gates */
 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aoclk.c
index b67951909e04..bf8bea675d24 100644
--- a/drivers/clk/meson/meson-aoclk.c
+++ b/drivers/clk/meson/meson-aoclk.c
@@ -17,8 +17,6 @@
 #include <linux/slab.h>
 #include "meson-aoclk.h"
 
-#include "clk-input.h"
-
 static int meson_aoclk_do_reset(struct reset_controller_dev *rcdev,
                                unsigned long id)
 {
@@ -33,37 +31,6 @@ static const struct reset_control_ops meson_aoclk_reset_ops = {
         .reset = meson_aoclk_do_reset,
 };
 
-static int meson_aoclkc_register_inputs(struct device *dev,
-                                        struct meson_aoclk_data *data)
-{
-        struct clk_hw *hw;
-        char *str;
-        int i;
-
-        for (i = 0; i < data->num_inputs; i++) {
-                const struct meson_aoclk_input *in = &data->inputs[i];
-
-                str = kasprintf(GFP_KERNEL, "%s%s", data->input_prefix,
-                                in->name);
-                if (!str)
-                        return -ENOMEM;
-
-                hw = meson_clk_hw_register_input(dev, in->name, str, 0);
-                kfree(str);
-
-                if (IS_ERR(hw)) {
-                        if (!in->required && PTR_ERR(hw) == -ENOENT)
-                                continue;
-                        else if (PTR_ERR(hw) != -EPROBE_DEFER)
-                                dev_err(dev, "failed to register input %s\n",
-                                        in->name);
-                        return PTR_ERR(hw);
-                }
-        }
-
-        return 0;
-}
-
 int meson_aoclkc_probe(struct platform_device *pdev)
 {
         struct meson_aoclk_reset_controller *rstc;
@@ -86,10 +53,6 @@ int meson_aoclkc_probe(struct platform_device *pdev)
                 return PTR_ERR(regmap);
         }
 
-        ret = meson_aoclkc_register_inputs(dev, data);
-        if (ret)
-                return ret;
-
         /* Reset Controller */
         rstc->data = data;
         rstc->regmap = regmap;
diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aoclk.h
index 999cde3868f7..605b43855a69 100644
--- a/drivers/clk/meson/meson-aoclk.h
+++ b/drivers/clk/meson/meson-aoclk.h
@@ -18,20 +18,12 @@
 
 #include "clk-regmap.h"
 
-struct meson_aoclk_input {
-        const char *name;
-        bool required;
-};
-
 struct meson_aoclk_data {
         const unsigned int                      reset_reg;
         const int                               num_reset;
         const unsigned int                      *reset;
         const int                               num_clks;
         struct clk_regmap                       **clks;
-        const int                               num_inputs;
-        const struct meson_aoclk_input          *inputs;
-        const char                              *input_prefix;
         const struct clk_hw_onecell_data        *hw_data;
 };
 
diff --git a/drivers/clk/meson/meson-eeclk.c b/drivers/clk/meson/meson-eeclk.c
index 6ba2094be257..a7cb1e7aedc4 100644
--- a/drivers/clk/meson/meson-eeclk.c
+++ b/drivers/clk/meson/meson-eeclk.c
@@ -10,7 +10,6 @@
 #include <linux/mfd/syscon.h>
 #include <linux/regmap.h>
 
-#include "clk-input.h"
 #include "clk-regmap.h"
 #include "meson-eeclk.h"
 
@@ -18,7 +17,6 @@ int meson_eeclkc_probe(struct platform_device *pdev)
 {
         const struct meson_eeclkc_data *data;
         struct device *dev = &pdev->dev;
-        struct clk_hw *input;
         struct regmap *map;
         int ret, i;
 
@@ -37,14 +35,6 @@ int meson_eeclkc_probe(struct platform_device *pdev)
         if (data->init_count)
                 regmap_multi_reg_write(map, data->init_regs, data->init_count);
 
-        input = meson_clk_hw_register_input(dev, "xtal", IN_PREFIX "xtal", 0);
-        if (IS_ERR(input)) {
-                ret = PTR_ERR(input);
-                if (ret != -EPROBE_DEFER)
-                        dev_err(dev, "failed to get input clock");
-                return ret;
-        }
-
         /* Populate regmap for the regmap backed clocks */
         for (i = 0; i < data->regmap_clk_num; i++)
                 data->regmap_clks[i]->map = map;
diff --git a/drivers/clk/meson/meson-eeclk.h b/drivers/clk/meson/meson-eeclk.h
index 9ab5d6fa7ccb..77316207bde1 100644
--- a/drivers/clk/meson/meson-eeclk.h
+++ b/drivers/clk/meson/meson-eeclk.h
@@ -10,8 +10,6 @@
 #include <linux/clk-provider.h>
 #include "clk-regmap.h"
 
-#define IN_PREFIX "ee-in-"
-
 struct platform_device;
 
 struct meson_eeclkc_data {
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 537219fa573e..67e6691e080c 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -97,7 +97,9 @@ static struct clk_regmap meson8b_fixed_pll_dco = {
         .hw.init = &(struct clk_init_data){
                 .name = "fixed_pll_dco",
                 .ops = &meson_clk_pll_ro_ops,
-                .parent_names = (const char *[]){ "xtal" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_xtal.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -112,7 +114,9 @@ static struct clk_regmap meson8b_fixed_pll = {
         .hw.init = &(struct clk_init_data){
                 .name = "fixed_pll",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "fixed_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_fixed_pll_dco.hw
+                },
                 .num_parents = 1,
                 /*
                  * This clock won't ever change at runtime so
@@ -158,7 +162,9 @@ static struct clk_regmap meson8b_hdmi_pll_dco = {
                 /* sometimes also called "HPLL" or "HPLL PLL" */
                 .name = "hdmi_pll_dco",
                 .ops = &meson_clk_pll_ro_ops,
-                .parent_names = (const char *[]){ "xtal" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_xtal.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -173,7 +179,9 @@ static struct clk_regmap meson8b_hdmi_pll_lvds_out = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_pll_lvds_out",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "hdmi_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_hdmi_pll_dco.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -189,7 +197,9 @@ static struct clk_regmap meson8b_hdmi_pll_hdmi_out = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_pll_hdmi_out",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "hdmi_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_hdmi_pll_dco.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -227,7 +237,9 @@ static struct clk_regmap meson8b_sys_pll_dco = {
         .hw.init = &(struct clk_init_data){
                 .name = "sys_pll_dco",
                 .ops = &meson_clk_pll_ops,
-                .parent_names = (const char *[]){ "xtal" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_xtal.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -242,7 +254,9 @@ static struct clk_regmap meson8b_sys_pll = {
         .hw.init = &(struct clk_init_data){
                 .name = "sys_pll",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "sys_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_sys_pll_dco.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -254,7 +268,9 @@ static struct clk_fixed_factor meson8b_fclk_div2_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div2_div",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_fixed_pll.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -267,7 +283,9 @@ static struct clk_regmap meson8b_fclk_div2 = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div2",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div2_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_fclk_div2_div.hw
+                },
                 .num_parents = 1,
                 /*
                  * FIXME: Ethernet with a RGMII PHYs is not working if
@@ -285,7 +303,9 @@ static struct clk_fixed_factor meson8b_fclk_div3_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div3_div",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_fixed_pll.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -298,7 +318,9 @@ static struct clk_regmap meson8b_fclk_div3 = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div3",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div3_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_fclk_div3_div.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -309,7 +331,9 @@ static struct clk_fixed_factor meson8b_fclk_div4_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div4_div",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_fixed_pll.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -322,7 +346,9 @@ static struct clk_regmap meson8b_fclk_div4 = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div4",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div4_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_fclk_div4_div.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -333,7 +359,9 @@ static struct clk_fixed_factor meson8b_fclk_div5_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div5_div",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_fixed_pll.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -346,7 +374,9 @@ static struct clk_regmap meson8b_fclk_div5 = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div5",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div5_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_fclk_div5_div.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -357,7 +387,9 @@ static struct clk_fixed_factor meson8b_fclk_div7_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div7_div",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_fixed_pll.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -370,7 +402,9 @@ static struct clk_regmap meson8b_fclk_div7 = {
         .hw.init = &(struct clk_init_data){
                 .name = "fclk_div7",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "fclk_div7_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_fclk_div7_div.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -384,7 +418,9 @@ static struct clk_regmap meson8b_mpll_prediv = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll_prediv",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "fixed_pll" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_fixed_pll.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -416,7 +452,9 @@ static struct clk_regmap meson8b_mpll0_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll0_div",
                 .ops = &meson_clk_mpll_ops,
-                .parent_names = (const char *[]){ "mpll_prediv" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_mpll_prediv.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -429,7 +467,9 @@ static struct clk_regmap meson8b_mpll0 = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mpll0_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_mpll0_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -457,7 +497,9 @@ static struct clk_regmap meson8b_mpll1_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll1_div",
                 .ops = &meson_clk_mpll_ops,
-                .parent_names = (const char *[]){ "mpll_prediv" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_mpll_prediv.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -470,7 +512,9 @@ static struct clk_regmap meson8b_mpll1 = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll1",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mpll1_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_mpll1_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -498,7 +542,9 @@ static struct clk_regmap meson8b_mpll2_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll2_div",
                 .ops = &meson_clk_mpll_ops,
-                .parent_names = (const char *[]){ "mpll_prediv" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_mpll_prediv.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -511,7 +557,9 @@ static struct clk_regmap meson8b_mpll2 = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpll2",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mpll2_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_mpll2_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -533,8 +581,11 @@ static struct clk_regmap meson8b_mpeg_clk_sel = {
                  * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
                  * fclk_div4, fclk_div3, fclk_div5
                  */
-                .parent_names = (const char *[]){ "fclk_div3", "fclk_div4",
-                        "fclk_div5" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_fclk_div3.hw,
+                        &meson8b_fclk_div4.hw,
+                        &meson8b_fclk_div5.hw,
+                },
                 .num_parents = 3,
         },
 };
@@ -548,7 +599,9 @@ static struct clk_regmap meson8b_mpeg_clk_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mpeg_clk_div",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "mpeg_clk_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_mpeg_clk_sel.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -561,7 +614,9 @@ static struct clk_regmap meson8b_clk81 = {
         .hw.init = &(struct clk_init_data){
                 .name = "clk81",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mpeg_clk_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_mpeg_clk_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_IS_CRITICAL,
         },
@@ -576,7 +631,10 @@ static struct clk_regmap meson8b_cpu_in_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_in_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "xtal", "sys_pll" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_xtal.hw,
+                        &meson8b_sys_pll.hw,
+                },
                 .num_parents = 2,
                 .flags = (CLK_SET_RATE_PARENT |
                           CLK_SET_RATE_NO_REPARENT),
@@ -589,7 +647,9 @@ static struct clk_fixed_factor meson8b_cpu_in_div2 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_in_div2",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "cpu_in_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cpu_in_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -601,7 +661,9 @@ static struct clk_fixed_factor meson8b_cpu_in_div3 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_in_div3",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "cpu_in_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cpu_in_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -630,7 +692,9 @@ static struct clk_regmap meson8b_cpu_scale_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_scale_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "cpu_in_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cpu_in_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -649,13 +713,15 @@ static struct clk_regmap meson8b_cpu_scale_out_sel = {
                 .ops = &clk_regmap_mux_ops,
                 /*
                  * NOTE: We are skipping the parent with value 0x2 (which is
-                 * "cpu_in_div3") because it results in a duty cycle of 33%
-                 * which makes the system unstable and can result in a lockup
-                 * of the whole system.
+                 * meson8b_cpu_in_div3) because it results in a duty cycle of
+                 * 33% which makes the system unstable and can result in a
+                 * lockup of the whole system.
                  */
-                .parent_names = (const char *[]) { "cpu_in_sel",
-                                                   "cpu_in_div2",
-                                                   "cpu_scale_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cpu_in_sel.hw,
+                        &meson8b_cpu_in_div2.hw,
+                        &meson8b_cpu_scale_div.hw,
+                },
                 .num_parents = 3,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -670,8 +736,10 @@ static struct clk_regmap meson8b_cpu_clk = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "xtal",
-                                                  "cpu_scale_out_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_xtal.hw,
+                        &meson8b_cpu_scale_out_sel.hw,
+                },
                 .num_parents = 2,
                 .flags = (CLK_SET_RATE_PARENT |
                           CLK_SET_RATE_NO_REPARENT |
@@ -690,8 +758,13 @@ static struct clk_regmap meson8b_nand_clk_sel = {
                 .name = "nand_clk_sel",
                 .ops = &clk_regmap_mux_ops,
                 /* FIXME all other parents are unknown: */
-                .parent_names = (const char *[]){ "fclk_div4", "fclk_div3",
-                        "fclk_div5", "fclk_div7", "xtal" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_fclk_div4.hw,
+                        &meson8b_fclk_div3.hw,
+                        &meson8b_fclk_div5.hw,
+                        &meson8b_fclk_div7.hw,
+                        &meson8b_xtal.hw,
+                },
                 .num_parents = 5,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -707,7 +780,9 @@ static struct clk_regmap meson8b_nand_clk_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "nand_clk_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "nand_clk_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_nand_clk_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -721,7 +796,9 @@ static struct clk_regmap meson8b_nand_clk_gate = {
         .hw.init = &(struct clk_init_data){
                 .name = "nand_clk_gate",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "nand_clk_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_nand_clk_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -733,7 +810,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div2 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk_div2",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "cpu_clk" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cpu_clk.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -744,7 +823,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div3 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk_div3",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "cpu_clk" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cpu_clk.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -755,7 +836,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div4 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk_div4",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "cpu_clk" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cpu_clk.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -766,7 +849,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div5 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk_div5",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "cpu_clk" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cpu_clk.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -777,7 +862,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div6 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk_div6",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "cpu_clk" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cpu_clk.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -788,7 +875,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div7 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk_div7",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "cpu_clk" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cpu_clk.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -799,7 +888,9 @@ static struct clk_fixed_factor meson8b_cpu_clk_div8 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cpu_clk_div8",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "cpu_clk" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cpu_clk.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -815,13 +906,15 @@ static struct clk_regmap meson8b_apb_clk_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "apb_clk_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "cpu_clk_div2",
-                                                  "cpu_clk_div3",
-                                                  "cpu_clk_div4",
-                                                  "cpu_clk_div5",
-                                                  "cpu_clk_div6",
-                                                  "cpu_clk_div7",
-                                                  "cpu_clk_div8", },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cpu_clk_div2.hw,
+                        &meson8b_cpu_clk_div3.hw,
+                        &meson8b_cpu_clk_div4.hw,
+                        &meson8b_cpu_clk_div5.hw,
+                        &meson8b_cpu_clk_div6.hw,
+                        &meson8b_cpu_clk_div7.hw,
+                        &meson8b_cpu_clk_div8.hw,
+                },
                 .num_parents = 7,
         },
 };
@@ -835,7 +928,9 @@ static struct clk_regmap meson8b_apb_clk_gate = {
         .hw.init = &(struct clk_init_data){
                 .name = "apb_clk_dis",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "apb_clk_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_apb_clk_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -850,13 +945,15 @@ static struct clk_regmap meson8b_periph_clk_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "periph_clk_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "cpu_clk_div2",
-                                                  "cpu_clk_div3",
-                                                  "cpu_clk_div4",
-                                                  "cpu_clk_div5",
-                                                  "cpu_clk_div6",
-                                                  "cpu_clk_div7",
-                                                  "cpu_clk_div8", },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cpu_clk_div2.hw,
+                        &meson8b_cpu_clk_div3.hw,
+                        &meson8b_cpu_clk_div4.hw,
+                        &meson8b_cpu_clk_div5.hw,
+                        &meson8b_cpu_clk_div6.hw,
+                        &meson8b_cpu_clk_div7.hw,
+                        &meson8b_cpu_clk_div8.hw,
+                },
                 .num_parents = 7,
         },
 };
@@ -870,7 +967,9 @@ static struct clk_regmap meson8b_periph_clk_gate = {
         .hw.init = &(struct clk_init_data){
                 .name = "periph_clk_dis",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "periph_clk_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_periph_clk_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -887,13 +986,15 @@ static struct clk_regmap meson8b_axi_clk_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "axi_clk_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "cpu_clk_div2",
-                                                  "cpu_clk_div3",
-                                                  "cpu_clk_div4",
-                                                  "cpu_clk_div5",
-                                                  "cpu_clk_div6",
-                                                  "cpu_clk_div7",
-                                                  "cpu_clk_div8", },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cpu_clk_div2.hw,
+                        &meson8b_cpu_clk_div3.hw,
+                        &meson8b_cpu_clk_div4.hw,
+                        &meson8b_cpu_clk_div5.hw,
+                        &meson8b_cpu_clk_div6.hw,
+                        &meson8b_cpu_clk_div7.hw,
+                        &meson8b_cpu_clk_div8.hw,
+                },
                 .num_parents = 7,
         },
 };
@@ -907,7 +1008,9 @@ static struct clk_regmap meson8b_axi_clk_gate = {
         .hw.init = &(struct clk_init_data){
                 .name = "axi_clk_dis",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "axi_clk_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_axi_clk_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -922,13 +1025,15 @@ static struct clk_regmap meson8b_l2_dram_clk_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "l2_dram_clk_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "cpu_clk_div2",
-                                                  "cpu_clk_div3",
-                                                  "cpu_clk_div4",
-                                                  "cpu_clk_div5",
-                                                  "cpu_clk_div6",
-                                                  "cpu_clk_div7",
-                                                  "cpu_clk_div8", },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cpu_clk_div2.hw,
+                        &meson8b_cpu_clk_div3.hw,
+                        &meson8b_cpu_clk_div4.hw,
+                        &meson8b_cpu_clk_div5.hw,
+                        &meson8b_cpu_clk_div6.hw,
+                        &meson8b_cpu_clk_div7.hw,
+                        &meson8b_cpu_clk_div8.hw,
+                },
                 .num_parents = 7,
         },
 };
@@ -942,7 +1047,9 @@ static struct clk_regmap meson8b_l2_dram_clk_gate = {
         .hw.init = &(struct clk_init_data){
                 .name = "l2_dram_clk_dis",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "l2_dram_clk_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_l2_dram_clk_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -963,7 +1070,9 @@ static struct clk_regmap meson8b_vid_pll_in_sel = {
                  * Meson8b: hdmi_pll_dco
                  * Meson8m2: vid2_pll
                  */
-                .parent_names = (const char *[]){ "hdmi_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_hdmi_pll_dco.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -977,7 +1086,9 @@ static struct clk_regmap meson8b_vid_pll_in_en = {
         .hw.init = &(struct clk_init_data){
                 .name = "vid_pll_in_en",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "vid_pll_in_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vid_pll_in_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -992,7 +1103,9 @@ static struct clk_regmap meson8b_vid_pll_pre_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vid_pll_pre_div",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "vid_pll_in_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vid_pll_in_en.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1007,7 +1120,9 @@ static struct clk_regmap meson8b_vid_pll_post_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vid_pll_post_div",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "vid_pll_pre_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vid_pll_pre_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1023,8 +1138,10 @@ static struct clk_regmap meson8b_vid_pll = {
                 .name = "vid_pll",
                 .ops = &clk_regmap_mux_ro_ops,
                 /* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */
-                .parent_names = (const char *[]){ "vid_pll_pre_div",
-                                                  "vid_pll_post_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vid_pll_pre_div.hw,
+                        &meson8b_vid_pll_post_div.hw,
+                },
                 .num_parents = 2,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1039,15 +1156,22 @@ static struct clk_regmap meson8b_vid_pll_final_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vid_pll_final_div",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "vid_pll" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vid_pll.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
 
-static const char * const meson8b_vclk_mux_parents[] = {
-        "vid_pll_final_div", "fclk_div4", "fclk_div3", "fclk_div5",
-        "vid_pll_final_div", "fclk_div7", "mpll1"
+static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = {
+        &meson8b_vid_pll_final_div.hw,
+        &meson8b_fclk_div4.hw,
+        &meson8b_fclk_div3.hw,
+        &meson8b_fclk_div5.hw,
+        &meson8b_vid_pll_final_div.hw,
+        &meson8b_fclk_div7.hw,
+        &meson8b_mpll1.hw,
 };
 
 static struct clk_regmap meson8b_vclk_in_sel = {
@@ -1059,8 +1183,8 @@ static struct clk_regmap meson8b_vclk_in_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_in_sel",
                 .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = meson8b_vclk_mux_parents,
-                .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parents),
+                .parent_hws = meson8b_vclk_mux_parent_hws,
+                .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -1073,7 +1197,9 @@ static struct clk_regmap meson8b_vclk_in_en = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_in_en",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "vclk_in_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vclk_in_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1087,7 +1213,9 @@ static struct clk_regmap meson8b_vclk_div1_gate = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_div1_en",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "vclk_in_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vclk_in_en.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1099,7 +1227,9 @@ static struct clk_fixed_factor meson8b_vclk_div2_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_div2",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk_in_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vclk_in_en.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         }
@@ -1113,7 +1243,9 @@ static struct clk_regmap meson8b_vclk_div2_div_gate = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_div2_en",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "vclk_div2" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vclk_div2_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1125,7 +1257,9 @@ static struct clk_fixed_factor meson8b_vclk_div4_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_div4",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk_in_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vclk_in_en.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         }
@@ -1139,7 +1273,9 @@ static struct clk_regmap meson8b_vclk_div4_div_gate = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_div4_en",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "vclk_div4" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vclk_div4_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1151,7 +1287,9 @@ static struct clk_fixed_factor meson8b_vclk_div6_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_div6",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk_in_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vclk_in_en.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         }
@@ -1165,7 +1303,9 @@ static struct clk_regmap meson8b_vclk_div6_div_gate = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_div6_en",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "vclk_div6" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vclk_div6_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1177,7 +1317,9 @@ static struct clk_fixed_factor meson8b_vclk_div12_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_div12",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk_in_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vclk_in_en.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         }
@@ -1191,7 +1333,9 @@ static struct clk_regmap meson8b_vclk_div12_div_gate = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk_div12_en",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "vclk_div12" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vclk_div12_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1206,8 +1350,8 @@ static struct clk_regmap meson8b_vclk2_in_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_in_sel",
                 .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = meson8b_vclk_mux_parents,
-                .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parents),
+                .parent_hws = meson8b_vclk_mux_parent_hws,
+                .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -1220,7 +1364,9 @@ static struct clk_regmap meson8b_vclk2_clk_in_en = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_in_en",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "vclk2_in_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vclk2_in_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1234,7 +1380,9 @@ static struct clk_regmap meson8b_vclk2_div1_gate = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_div1_en",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "vclk2_in_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vclk2_clk_in_en.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1246,7 +1394,9 @@ static struct clk_fixed_factor meson8b_vclk2_div2_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_div2",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk2_in_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vclk2_clk_in_en.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         }
@@ -1260,7 +1410,9 @@ static struct clk_regmap meson8b_vclk2_div2_div_gate = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_div2_en",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "vclk2_div2" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vclk2_div2_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1272,7 +1424,9 @@ static struct clk_fixed_factor meson8b_vclk2_div4_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_div4",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk2_in_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vclk2_clk_in_en.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         }
@@ -1286,7 +1440,9 @@ static struct clk_regmap meson8b_vclk2_div4_div_gate = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_div4_en",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "vclk2_div4" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vclk2_div4_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1298,7 +1454,9 @@ static struct clk_fixed_factor meson8b_vclk2_div6_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_div6",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk2_in_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vclk2_clk_in_en.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         }
@@ -1312,7 +1470,9 @@ static struct clk_regmap meson8b_vclk2_div6_div_gate = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_div6_en",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "vclk2_div6" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vclk2_div6_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1324,7 +1484,9 @@ static struct clk_fixed_factor meson8b_vclk2_div12_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_div12",
                 .ops = &clk_fixed_factor_ops,
-                .parent_names = (const char *[]){ "vclk2_in_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vclk2_clk_in_en.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         }
@@ -1338,15 +1500,20 @@ static struct clk_regmap meson8b_vclk2_div12_div_gate = {
         .hw.init = &(struct clk_init_data){
                 .name = "vclk2_div12_en",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "vclk2_div12" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vclk2_div12_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
 
-static const char * const meson8b_vclk_enc_mux_parents[] = {
-        "vclk_div1_en", "vclk_div2_en", "vclk_div4_en", "vclk_div6_en",
-        "vclk_div12_en",
+static const struct clk_hw *meson8b_vclk_enc_mux_parent_hws[] = {
+        &meson8b_vclk_div1_gate.hw,
+        &meson8b_vclk_div2_div_gate.hw,
+        &meson8b_vclk_div4_div_gate.hw,
+        &meson8b_vclk_div6_div_gate.hw,
+        &meson8b_vclk_div12_div_gate.hw,
 };
 
 static struct clk_regmap meson8b_cts_enct_sel = {
@@ -1358,8 +1525,8 @@ static struct clk_regmap meson8b_cts_enct_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_enct_sel",
                 .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = meson8b_vclk_enc_mux_parents,
-                .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents),
+                .parent_hws = meson8b_vclk_enc_mux_parent_hws,
+                .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -1372,7 +1539,9 @@ static struct clk_regmap meson8b_cts_enct = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_enct",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "cts_enct_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cts_enct_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1387,8 +1556,8 @@ static struct clk_regmap meson8b_cts_encp_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_encp_sel",
                 .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = meson8b_vclk_enc_mux_parents,
-                .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents),
+                .parent_hws = meson8b_vclk_enc_mux_parent_hws,
+                .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -1401,7 +1570,9 @@ static struct clk_regmap meson8b_cts_encp = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_encp",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "cts_encp_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cts_encp_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1416,8 +1587,8 @@ static struct clk_regmap meson8b_cts_enci_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_enci_sel",
                 .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = meson8b_vclk_enc_mux_parents,
-                .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents),
+                .parent_hws = meson8b_vclk_enc_mux_parent_hws,
+                .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -1430,7 +1601,9 @@ static struct clk_regmap meson8b_cts_enci = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_enci",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "cts_enci_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cts_enci_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1445,8 +1618,8 @@ static struct clk_regmap meson8b_hdmi_tx_pixel_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_tx_pixel_sel",
                 .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = meson8b_vclk_enc_mux_parents,
-                .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents),
+                .parent_hws = meson8b_vclk_enc_mux_parent_hws,
+                .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -1459,15 +1632,20 @@ static struct clk_regmap meson8b_hdmi_tx_pixel = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_tx_pixel",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "hdmi_tx_pixel_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_hdmi_tx_pixel_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
 
-static const char * const meson8b_vclk2_enc_mux_parents[] = {
-        "vclk2_div1_en", "vclk2_div2_en", "vclk2_div4_en", "vclk2_div6_en",
-        "vclk2_div12_en",
+static const struct clk_hw *meson8b_vclk2_enc_mux_parent_hws[] = {
+        &meson8b_vclk2_div1_gate.hw,
+        &meson8b_vclk2_div2_div_gate.hw,
+        &meson8b_vclk2_div4_div_gate.hw,
+        &meson8b_vclk2_div6_div_gate.hw,
+        &meson8b_vclk2_div12_div_gate.hw,
 };
 
 static struct clk_regmap meson8b_cts_encl_sel = {
@@ -1479,8 +1657,8 @@ static struct clk_regmap meson8b_cts_encl_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_encl_sel",
                 .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = meson8b_vclk2_enc_mux_parents,
-                .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parents),
+                .parent_hws = meson8b_vclk2_enc_mux_parent_hws,
+                .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -1493,7 +1671,9 @@ static struct clk_regmap meson8b_cts_encl = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_encl",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "cts_encl_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cts_encl_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1508,8 +1688,8 @@ static struct clk_regmap meson8b_cts_vdac0_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_vdac0_sel",
                 .ops = &clk_regmap_mux_ro_ops,
-                .parent_names = meson8b_vclk2_enc_mux_parents,
-                .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parents),
+                .parent_hws = meson8b_vclk2_enc_mux_parent_hws,
+                .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -1522,7 +1702,9 @@ static struct clk_regmap meson8b_cts_vdac0 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_vdac0",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "cts_vdac0_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cts_vdac0_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1539,7 +1721,9 @@ static struct clk_regmap meson8b_hdmi_sys_sel = {
                 .name = "hdmi_sys_sel",
                 .ops = &clk_regmap_mux_ro_ops,
                 /* FIXME: all other parents are unknown */
-                .parent_names = (const char *[]){ "xtal" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_xtal.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
@@ -1554,7 +1738,9 @@ static struct clk_regmap meson8b_hdmi_sys_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "hdmi_sys_div",
                 .ops = &clk_regmap_divider_ro_ops,
-                .parent_names = (const char *[]){ "hdmi_sys_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_hdmi_sys_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1568,7 +1754,9 @@ static struct clk_regmap meson8b_hdmi_sys = {
         .hw.init = &(struct clk_init_data) {
                 .name = "hdmi_sys",
                 .ops = &clk_regmap_gate_ro_ops,
-                .parent_names = (const char *[]){ "hdmi_sys_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_hdmi_sys_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1579,9 +1767,14 @@ static struct clk_regmap meson8b_hdmi_sys = {
  * muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only
  * has mali_0 and no glitch-free mux.
  */
-static const char * const meson8b_mali_0_1_parent_names[] = {
-        "xtal", "mpll2", "mpll1", "fclk_div7", "fclk_div4", "fclk_div3",
-        "fclk_div5"
+static const struct clk_hw *meson8b_mali_0_1_parent_hws[] = {
+        &meson8b_xtal.hw,
+        &meson8b_mpll2.hw,
+        &meson8b_mpll1.hw,
+        &meson8b_fclk_div7.hw,
+        &meson8b_fclk_div4.hw,
+        &meson8b_fclk_div3.hw,
+        &meson8b_fclk_div5.hw,
 };
 
 static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 };
@@ -1596,8 +1789,8 @@ static struct clk_regmap meson8b_mali_0_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "mali_0_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = meson8b_mali_0_1_parent_names,
-                .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_names),
+                .parent_hws = meson8b_mali_0_1_parent_hws,
+                .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_hws),
                 /*
                  * Don't propagate rate changes up because the only changeable
                  * parents are mpll1 and mpll2 but we need those for audio and
@@ -1617,7 +1810,9 @@ static struct clk_regmap meson8b_mali_0_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mali_0_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "mali_0_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_mali_0_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1631,7 +1826,9 @@ static struct clk_regmap meson8b_mali_0 = {
         .hw.init = &(struct clk_init_data){
                 .name = "mali_0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mali_0_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_mali_0_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1647,8 +1844,8 @@ static struct clk_regmap meson8b_mali_1_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "mali_1_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = meson8b_mali_0_1_parent_names,
-                .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_names),
+                .parent_hws = meson8b_mali_0_1_parent_hws,
+                .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_hws),
                 /*
                  * Don't propagate rate changes up because the only changeable
                  * parents are mpll1 and mpll2 but we need those for audio and
@@ -1668,7 +1865,9 @@ static struct clk_regmap meson8b_mali_1_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "mali_1_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "mali_1_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_mali_1_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1682,7 +1881,9 @@ static struct clk_regmap meson8b_mali_1 = {
         .hw.init = &(struct clk_init_data){
                 .name = "mali_1",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "mali_1_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_mali_1_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1697,7 +1898,10 @@ static struct clk_regmap meson8b_mali = {
         .hw.init = &(struct clk_init_data){
                 .name = "mali",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "mali_0", "mali_1" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_mali_0.hw,
+                        &meson8b_mali_1.hw,
+                },
                 .num_parents = 2,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1740,7 +1944,9 @@ static struct clk_regmap meson8m2_gp_pll_dco = {
         .hw.init = &(struct clk_init_data){
                 .name = "gp_pll_dco",
                 .ops = &meson_clk_pll_ops,
-                .parent_names = (const char *[]){ "xtal" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_xtal.hw
+                },
                 .num_parents = 1,
         },
 };
@@ -1755,18 +1961,26 @@ static struct clk_regmap meson8m2_gp_pll = {
         .hw.init = &(struct clk_init_data){
                 .name = "gp_pll",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "gp_pll_dco" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8m2_gp_pll_dco.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
 
-static const char * const meson8b_vpu_0_1_parent_names[] = {
-        "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
+static const struct clk_hw *meson8b_vpu_0_1_parent_hws[] = {
+        &meson8b_fclk_div4.hw,
+        &meson8b_fclk_div3.hw,
+        &meson8b_fclk_div5.hw,
+        &meson8b_fclk_div7.hw,
 };
 
-static const char * const mmeson8m2_vpu_0_1_parent_names[] = {
-        "fclk_div4", "fclk_div3", "fclk_div5", "gp_pll"
+static const struct clk_hw *mmeson8m2_vpu_0_1_parent_hws[] = {
+        &meson8b_fclk_div4.hw,
+        &meson8b_fclk_div3.hw,
+        &meson8b_fclk_div5.hw,
+        &meson8m2_gp_pll.hw,
 };
 
 static struct clk_regmap meson8b_vpu_0_sel = {
@@ -1778,8 +1992,8 @@ static struct clk_regmap meson8b_vpu_0_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vpu_0_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = meson8b_vpu_0_1_parent_names,
-                .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_names),
+                .parent_hws = meson8b_vpu_0_1_parent_hws,
+                .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -1793,8 +2007,8 @@ static struct clk_regmap meson8m2_vpu_0_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vpu_0_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = mmeson8m2_vpu_0_1_parent_names,
-                .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_names),
+                .parent_hws = mmeson8m2_vpu_0_1_parent_hws,
+                .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -1808,7 +2022,17 @@ static struct clk_regmap meson8b_vpu_0_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vpu_0_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vpu_0_sel" },
+                .parent_data = &(const struct clk_parent_data) {
+                        /*
+                         * Note:
+                         * meson8b and meson8m2 have different vpu_0_sels (with
+                         * different struct clk_hw). We fallback to the global
+                         * naming string mechanism so vpu_0_div picks up the
+                         * appropriate one.
+                         */
+                        .name = "vpu_0_sel",
+                        .index = -1,
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1822,7 +2046,9 @@ static struct clk_regmap meson8b_vpu_0 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vpu_0",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vpu_0_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vpu_0_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1837,8 +2063,8 @@ static struct clk_regmap meson8b_vpu_1_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vpu_1_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = meson8b_vpu_0_1_parent_names,
-                .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_names),
+                .parent_hws = meson8b_vpu_0_1_parent_hws,
+                .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -1852,8 +2078,8 @@ static struct clk_regmap meson8m2_vpu_1_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vpu_1_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = mmeson8m2_vpu_0_1_parent_names,
-                .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_names),
+                .parent_hws = mmeson8m2_vpu_0_1_parent_hws,
+                .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -1867,7 +2093,17 @@ static struct clk_regmap meson8b_vpu_1_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vpu_1_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vpu_1_sel" },
+                .parent_data = &(const struct clk_parent_data) {
+                        /*
+                         * Note:
+                         * meson8b and meson8m2 have different vpu_1_sels (with
+                         * different struct clk_hw). We fallback to the global
+                         * naming string mechanism so vpu_1_div picks up the
+                         * appropriate one.
+                         */
+                        .name = "vpu_1_sel",
+                        .index = -1,
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1881,7 +2117,9 @@ static struct clk_regmap meson8b_vpu_1 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vpu_1",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vpu_1_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vpu_1_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1896,14 +2134,22 @@ static struct clk_regmap meson8b_vpu = {
         .hw.init = &(struct clk_init_data){
                 .name = "vpu",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "vpu_0", "vpu_1" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vpu_0.hw,
+                        &meson8b_vpu_1.hw,
+                },
                 .num_parents = 2,
                 .flags = CLK_SET_RATE_NO_REPARENT,
         },
 };
 
-static const char * const meson8b_vdec_parent_names[] = {
-        "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "mpll2", "mpll1"
+static const struct clk_hw *meson8b_vdec_parent_hws[] = {
+        &meson8b_fclk_div4.hw,
+        &meson8b_fclk_div3.hw,
+        &meson8b_fclk_div5.hw,
+        &meson8b_fclk_div7.hw,
+        &meson8b_mpll2.hw,
+        &meson8b_mpll1.hw,
 };
 
 static struct clk_regmap meson8b_vdec_1_sel = {
@@ -1916,8 +2162,8 @@ static struct clk_regmap meson8b_vdec_1_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vdec_1_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = meson8b_vdec_parent_names,
-                .num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
+                .parent_hws = meson8b_vdec_parent_hws,
+                .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -1932,7 +2178,9 @@ static struct clk_regmap meson8b_vdec_1_1_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vdec_1_1_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vdec_1_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vdec_1_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1946,7 +2194,9 @@ static struct clk_regmap meson8b_vdec_1_1 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vdec_1_1",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vdec_1_1_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vdec_1_1_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1962,7 +2212,9 @@ static struct clk_regmap meson8b_vdec_1_2_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vdec_1_2_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vdec_1_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vdec_1_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1976,7 +2228,9 @@ static struct clk_regmap meson8b_vdec_1_2 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vdec_1_2",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vdec_1_2_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vdec_1_2_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -1992,7 +2246,10 @@ static struct clk_regmap meson8b_vdec_1 = {
         .hw.init = &(struct clk_init_data){
                 .name = "vdec_1",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "vdec_1_1", "vdec_1_2" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vdec_1_1.hw,
+                        &meson8b_vdec_1_2.hw,
+                },
                 .num_parents = 2,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2008,8 +2265,8 @@ static struct clk_regmap meson8b_vdec_hcodec_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vdec_hcodec_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = meson8b_vdec_parent_names,
-                .num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
+                .parent_hws = meson8b_vdec_parent_hws,
+                .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -2024,7 +2281,9 @@ static struct clk_regmap meson8b_vdec_hcodec_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vdec_hcodec_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vdec_hcodec_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vdec_hcodec_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2038,7 +2297,9 @@ static struct clk_regmap meson8b_vdec_hcodec = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vdec_hcodec",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vdec_hcodec_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vdec_hcodec_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2054,8 +2315,8 @@ static struct clk_regmap meson8b_vdec_2_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vdec_2_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = meson8b_vdec_parent_names,
-                .num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
+                .parent_hws = meson8b_vdec_parent_hws,
+                .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -2070,7 +2331,9 @@ static struct clk_regmap meson8b_vdec_2_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vdec_2_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vdec_2_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vdec_2_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2084,7 +2347,9 @@ static struct clk_regmap meson8b_vdec_2 = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vdec_2",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vdec_2_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vdec_2_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2100,8 +2365,8 @@ static struct clk_regmap meson8b_vdec_hevc_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "vdec_hevc_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = meson8b_vdec_parent_names,
-                .num_parents = ARRAY_SIZE(meson8b_vdec_parent_names),
+                .parent_hws = meson8b_vdec_parent_hws,
+                .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
@@ -2116,7 +2381,9 @@ static struct clk_regmap meson8b_vdec_hevc_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "vdec_hevc_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "vdec_hevc_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vdec_hevc_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2130,7 +2397,9 @@ static struct clk_regmap meson8b_vdec_hevc_en = {
         .hw.init = &(struct clk_init_data) {
                 .name = "vdec_hevc_en",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "vdec_hevc_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vdec_hevc_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2147,15 +2416,19 @@ static struct clk_regmap meson8b_vdec_hevc = {
                 .name = "vdec_hevc",
                 .ops = &clk_regmap_mux_ops,
                 /* TODO: The second parent is currently unknown */
-                .parent_names = (const char *[]){ "vdec_hevc_en" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_vdec_hevc_en.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
 
 /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
-static const char * const meson8b_cts_amclk_parent_names[] = {
-        "mpll0", "mpll1", "mpll2"
+static const struct clk_hw *meson8b_cts_amclk_parent_hws[] = {
+        &meson8b_mpll0.hw,
+        &meson8b_mpll1.hw,
+        &meson8b_mpll2.hw
 };
 
 static u32 meson8b_cts_amclk_mux_table[] = { 1, 2, 3 };
@@ -2171,8 +2444,8 @@ static struct clk_regmap meson8b_cts_amclk_sel = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_amclk_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = meson8b_cts_amclk_parent_names,
-                .num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_names),
+                .parent_hws = meson8b_cts_amclk_parent_hws,
+                .num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_hws),
         },
 };
 
@@ -2186,7 +2459,9 @@ static struct clk_regmap meson8b_cts_amclk_div = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_amclk_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "cts_amclk_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cts_amclk_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2200,15 +2475,19 @@ static struct clk_regmap meson8b_cts_amclk = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_amclk",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "cts_amclk_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cts_amclk_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
 };
 
 /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
-static const char * const meson8b_cts_mclk_i958_parent_names[] = {
-        "mpll0", "mpll1", "mpll2"
+static const struct clk_hw *meson8b_cts_mclk_i958_parent_hws[] = {
+        &meson8b_mpll0.hw,
+        &meson8b_mpll1.hw,
+        &meson8b_mpll2.hw
 };
 
 static u32 meson8b_cts_mclk_i958_mux_table[] = { 1, 2, 3 };
@@ -2224,8 +2503,8 @@ static struct clk_regmap meson8b_cts_mclk_i958_sel = {
         .hw.init = &(struct clk_init_data) {
                 .name = "cts_mclk_i958_sel",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = meson8b_cts_mclk_i958_parent_names,
-                .num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_names),
+                .parent_hws = meson8b_cts_mclk_i958_parent_hws,
+                .num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_hws),
         },
 };
 
@@ -2239,7 +2518,9 @@ static struct clk_regmap meson8b_cts_mclk_i958_div = {
         .hw.init = &(struct clk_init_data) {
                 .name = "cts_mclk_i958_div",
                 .ops = &clk_regmap_divider_ops,
-                .parent_names = (const char *[]){ "cts_mclk_i958_sel" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cts_mclk_i958_sel.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2253,7 +2534,9 @@ static struct clk_regmap meson8b_cts_mclk_i958 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_mclk_i958",
                 .ops = &clk_regmap_gate_ops,
-                .parent_names = (const char *[]){ "cts_mclk_i958_div" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cts_mclk_i958_div.hw
+                },
                 .num_parents = 1,
                 .flags = CLK_SET_RATE_PARENT,
         },
@@ -2268,8 +2551,10 @@ static struct clk_regmap meson8b_cts_i958 = {
         .hw.init = &(struct clk_init_data){
                 .name = "cts_i958",
                 .ops = &clk_regmap_mux_ops,
-                .parent_names = (const char *[]){ "cts_amclk",
-                                                  "cts_mclk_i958" },
+                .parent_hws = (const struct clk_hw *[]) {
+                        &meson8b_cts_amclk.hw,
+                        &meson8b_cts_mclk_i958.hw
+                },
                 .num_parents = 2,
                 /*
                  * The parent is specific to origin of the audio data. Let the
@@ -2279,6 +2564,9 @@ static struct clk_regmap meson8b_cts_i958 = {
         },
 };
 
+#define MESON_GATE(_name, _reg, _bit) \
+        MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw)
+
 /* Everything Else (EE) domain gates */
 
 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index b09f6ded0a30..415e6906a113 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -8,6 +8,9 @@ config MVEBU_CLK_CPU
 config MVEBU_CLK_COREDIV
         bool
 
+config ARMADA_AP_CP_HELPER
+        bool
+
 config ARMADA_370_CLK
         bool
         select MVEBU_CLK_COMMON
@@ -35,9 +38,14 @@ config ARMADA_XP_CLK
 
 config ARMADA_AP806_SYSCON
         bool
+        select ARMADA_AP_CP_HELPER
+
+config ARMADA_AP_CPU_CLK
+        bool
 
 config ARMADA_CP110_SYSCON
         bool
+        select ARMADA_AP_CP_HELPER
 
 config DOVE_CLK
         bool
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 93ac3685271f..04464cef0f06 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -2,6 +2,7 @@
 obj-$(CONFIG_MVEBU_CLK_COMMON)  += common.o
 obj-$(CONFIG_MVEBU_CLK_CPU)     += clk-cpu.o
 obj-$(CONFIG_MVEBU_CLK_COREDIV) += clk-corediv.o
+obj-$(CONFIG_ARMADA_AP_CP_HELPER) += armada_ap_cp_helper.o
 
 obj-$(CONFIG_ARMADA_370_CLK)    += armada-370.o
 obj-$(CONFIG_ARMADA_375_CLK)    += armada-375.o
@@ -12,6 +13,7 @@ obj-$(CONFIG_ARMADA_37XX_CLK)	+= armada-37xx-tbg.o
 obj-$(CONFIG_ARMADA_37XX_CLK)   += armada-37xx-periph.o
 obj-$(CONFIG_ARMADA_XP_CLK)     += armada-xp.o mv98dx3236.o
 obj-$(CONFIG_ARMADA_AP806_SYSCON) += ap806-system-controller.o
+obj-$(CONFIG_ARMADA_AP_CPU_CLK) += ap-cpu-clk.o
 obj-$(CONFIG_ARMADA_CP110_SYSCON) += cp110-system-controller.o
 obj-$(CONFIG_DOVE_CLK)          += dove.o dove-divider.o
 obj-$(CONFIG_KIRKWOOD_CLK)      += kirkwood.o
diff --git a/drivers/clk/mvebu/ap-cpu-clk.c b/drivers/clk/mvebu/ap-cpu-clk.c
new file mode 100644
index 000000000000..af5e5acad370
--- /dev/null
+++ b/drivers/clk/mvebu/ap-cpu-clk.c
@@ -0,0 +1,356 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Marvell Armada AP CPU Clock Controller
+ *
+ * Copyright (C) 2018 Marvell
+ *
+ * Omri Itach <omrii@marvell.com>
+ * Gregory Clement <gregory.clement@bootlin.com>
+ */
+
+#define pr_fmt(fmt) "ap-cpu-clk: " fmt
+
+#include <linux/clk-provider.h>
+#include <linux/clk.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include "armada_ap_cp_helper.h"
+
+#define AP806_CPU_CLUSTER0              0
+#define AP806_CPU_CLUSTER1              1
+#define AP806_CPUS_PER_CLUSTER          2
+#define APN806_CPU1_MASK                0x1
+
+#define APN806_CLUSTER_NUM_OFFSET       8
+#define APN806_CLUSTER_NUM_MASK         BIT(APN806_CLUSTER_NUM_OFFSET)
+
+#define APN806_MAX_DIVIDER              32
+
+/**
+ * struct cpu_dfs_regs: CPU DFS register mapping
+ * @divider_reg: full integer ratio from PLL frequency to CPU clock frequency
+ * @force_reg: request to force new ratio regardless of relation to other clocks
+ * @ratio_reg: central request to switch ratios
+ */
+struct cpu_dfs_regs {
+        unsigned int divider_reg;
+        unsigned int force_reg;
+        unsigned int ratio_reg;
+        unsigned int ratio_state_reg;
+        unsigned int divider_mask;
+        unsigned int cluster_offset;
+        unsigned int force_mask;
+        int divider_offset;
+        int divider_ratio;
+        int ratio_offset;
+        int ratio_state_offset;
+        int ratio_state_cluster_offset;
+};
+
+/* AP806 CPU DFS register mapping*/
+#define AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET             0x278
+#define AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET             0x280
+#define AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET             0x284
+#define AP806_CA72MP2_0_PLL_SR_REG_OFFSET               0xC94
+
+#define AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET           0x14
+#define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET         0
+#define AP806_PLL_CR_CPU_CLK_DIV_RATIO                  0
+#define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \
+                        (0x3f << AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
+#define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET      24
+#define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK \
+                        (0x1 << AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET)
+#define AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET      16
+#define AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET 0
+#define AP806_CA72MP2_0_PLL_RATIO_STATE                 11
+
+#define STATUS_POLL_PERIOD_US           1
+#define STATUS_POLL_TIMEOUT_US          1000000
+
+#define to_ap_cpu_clk(_hw) container_of(_hw, struct ap_cpu_clk, hw)
+
+static const struct cpu_dfs_regs ap806_dfs_regs = {
+        .divider_reg = AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET,
+        .force_reg = AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET,
+        .ratio_reg = AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET,
+        .ratio_state_reg = AP806_CA72MP2_0_PLL_SR_REG_OFFSET,
+        .divider_mask = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK,
+        .cluster_offset = AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET,
+        .force_mask = AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK,
+        .divider_offset = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET,
+        .divider_ratio = AP806_PLL_CR_CPU_CLK_DIV_RATIO,
+        .ratio_offset = AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET,
+        .ratio_state_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET,
+        .ratio_state_cluster_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET,
+};
+
+/* AP807 CPU DFS register mapping */
+#define AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET              0x278
+#define AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET              0x27c
+#define AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET                0xc98
+#define AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET                   0x8
+#define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET                 18
+#define AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \
+                (0x3f << AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
+#define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET                 12
+#define AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK \
+                (0x3f << AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET)
+#define AP807_PLL_CR_CPU_CLK_DIV_RATIO                          3
+#define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET              0
+#define AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK \
+                (0x3 << AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET)
+#define AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET              6
+#define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET          20
+#define AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET  3
+
+static const struct cpu_dfs_regs ap807_dfs_regs = {
+        .divider_reg = AP807_DEVICE_GENERAL_CONTROL_10_REG_OFFSET,
+        .force_reg = AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET,
+        .ratio_reg = AP807_DEVICE_GENERAL_CONTROL_11_REG_OFFSET,
+        .ratio_state_reg = AP807_DEVICE_GENERAL_STATUS_6_REG_OFFSET,
+        .divider_mask = AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK,
+        .cluster_offset = AP807_CA72MP2_0_PLL_CR_CLUSTER_OFFSET,
+        .force_mask = AP807_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK,
+        .divider_offset = AP807_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET,
+        .divider_ratio = AP807_PLL_CR_CPU_CLK_DIV_RATIO,
+        .ratio_offset = AP807_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET,
+        .ratio_state_offset = AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_OFFSET,
+        .ratio_state_cluster_offset =
+                AP807_CA72MP2_0_PLL_CLKDIV_RATIO_STABLE_CLUSTER_OFFSET
+};
+
+/*
+ * struct ap806_clk: CPU cluster clock controller instance
+ * @cluster: Cluster clock controller index
+ * @clk_name: Cluster clock controller name
+ * @dev : Cluster clock device
+ * @hw: HW specific structure of Cluster clock controller
+ * @pll_cr_base: CA72MP2 Register base (Device Sample at Reset register)
+ */
+struct ap_cpu_clk {
+        unsigned int cluster;
+        const char *clk_name;
+        struct device *dev;
+        struct clk_hw hw;
+        struct regmap *pll_cr_base;
+        const struct cpu_dfs_regs *pll_regs;
+};
+
+static unsigned long ap_cpu_clk_recalc_rate(struct clk_hw *hw,
+                                            unsigned long parent_rate)
+{
+        struct ap_cpu_clk *clk = to_ap_cpu_clk(hw);
+        unsigned int cpu_clkdiv_reg;
+        int cpu_clkdiv_ratio;
+
+        cpu_clkdiv_reg = clk->pll_regs->divider_reg +
+                (clk->cluster * clk->pll_regs->cluster_offset);
+        regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &cpu_clkdiv_ratio);
+        cpu_clkdiv_ratio &= clk->pll_regs->divider_mask;
+        cpu_clkdiv_ratio >>= clk->pll_regs->divider_offset;
+
+        return parent_rate / cpu_clkdiv_ratio;
+}
+
+static int ap_cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long parent_rate)
+{
+        struct ap_cpu_clk *clk = to_ap_cpu_clk(hw);
+        int ret, reg, divider = parent_rate / rate;
+        unsigned int cpu_clkdiv_reg, cpu_force_reg, cpu_ratio_reg, stable_bit;
+
+        cpu_clkdiv_reg = clk->pll_regs->divider_reg +
+                (clk->cluster * clk->pll_regs->cluster_offset);
+        cpu_force_reg = clk->pll_regs->force_reg +
+                (clk->cluster * clk->pll_regs->cluster_offset);
+        cpu_ratio_reg = clk->pll_regs->ratio_reg +
+                (clk->cluster * clk->pll_regs->cluster_offset);
+
+        regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &reg);
+        reg &= ~(clk->pll_regs->divider_mask);
+        reg |= (divider << clk->pll_regs->divider_offset);
+
+        /*
+         * AP807 CPU divider has two channels with ratio 1:3 and divider_ratio
+         * is 1. Otherwise, in the case of the AP806, divider_ratio is 0.
+         */
+        if (clk->pll_regs->divider_ratio) {
+                reg &= ~(AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_MASK);
+                reg |= ((divider * clk->pll_regs->divider_ratio) <<
+                                AP807_PLL_CR_1_CPU_CLK_DIV_RATIO_OFFSET);
+        }
+        regmap_write(clk->pll_cr_base, cpu_clkdiv_reg, reg);
+
+
+        regmap_update_bits(clk->pll_cr_base, cpu_force_reg,
+                           clk->pll_regs->force_mask,
+                           clk->pll_regs->force_mask);
+
+        regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg,
+                           BIT(clk->pll_regs->ratio_offset),
+                           BIT(clk->pll_regs->ratio_offset));
+
+        stable_bit = BIT(clk->pll_regs->ratio_state_offset +
+                         clk->cluster *
+                         clk->pll_regs->ratio_state_cluster_offset),
+        ret = regmap_read_poll_timeout(clk->pll_cr_base,
+                                       clk->pll_regs->ratio_state_reg, reg,
+                                       reg & stable_bit, STATUS_POLL_PERIOD_US,
+                                       STATUS_POLL_TIMEOUT_US);
+        if (ret)
+                return ret;
+
+        regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg,
+                           BIT(clk->pll_regs->ratio_offset), 0);
+
+        return 0;
+}
+
+static long ap_cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                                  unsigned long *parent_rate)
+{
+        int divider = *parent_rate / rate;
+
+        divider = min(divider, APN806_MAX_DIVIDER);
+
+        return *parent_rate / divider;
+}
+
+static const struct clk_ops ap_cpu_clk_ops = {
+        .recalc_rate    = ap_cpu_clk_recalc_rate,
+        .round_rate     = ap_cpu_clk_round_rate,
+        .set_rate       = ap_cpu_clk_set_rate,
+};
+
+static int ap_cpu_clock_probe(struct platform_device *pdev)
+{
+        int ret, nclusters = 0, cluster_index = 0;
+        struct device *dev = &pdev->dev;
+        struct device_node *dn, *np = dev->of_node;
+        struct clk_hw_onecell_data *ap_cpu_data;
+        struct ap_cpu_clk *ap_cpu_clk;
+        struct regmap *regmap;
+
+        regmap = syscon_node_to_regmap(np->parent);
+        if (IS_ERR(regmap)) {
+                pr_err("cannot get pll_cr_base regmap\n");
+                return PTR_ERR(regmap);
+        }
+
+        /*
+         * AP806 has 4 cpus and DFS for AP806 is controlled per
+         * cluster (2 CPUs per cluster), cpu0 and cpu1 are fixed to
+         * cluster0 while cpu2 and cpu3 are fixed to cluster1 whether
+         * they are enabled or not.  Since cpu0 is the boot cpu, then
+         * cluster0 must exist.  If cpu2 or cpu3 is enabled, cluster1
+         * will exist and the cluster number is 2; otherwise the
+         * cluster number is 1.
+         */
+        nclusters = 1;
+        for_each_of_cpu_node(dn) {
+                int cpu, err;
+
+                err = of_property_read_u32(dn, "reg", &cpu);
+                if (WARN_ON(err))
+                        return err;
+
+                /* If cpu2 or cpu3 is enabled */
+                if (cpu & APN806_CLUSTER_NUM_MASK) {
+                        nclusters = 2;
+                        break;
+                }
+        }
+        /*
+         * DFS for AP806 is controlled per cluster (2 CPUs per cluster),
+         * so allocate structs per cluster
+         */
+        ap_cpu_clk = devm_kcalloc(dev, nclusters, sizeof(*ap_cpu_clk),
+                                  GFP_KERNEL);
+        if (!ap_cpu_clk)
+                return -ENOMEM;
+
+        ap_cpu_data = devm_kzalloc(dev, sizeof(*ap_cpu_data) +
+                                sizeof(struct clk_hw *) * nclusters,
+                                GFP_KERNEL);
+        if (!ap_cpu_data)
+                return -ENOMEM;
+
+        for_each_of_cpu_node(dn) {
+                char *clk_name = "cpu-cluster-0";
+                struct clk_init_data init;
+                const char *parent_name;
+                struct clk *parent;
+                int cpu, err;
+
+                err = of_property_read_u32(dn, "reg", &cpu);
+                if (WARN_ON(err))
+                        return err;
+
+                cluster_index = cpu & APN806_CLUSTER_NUM_MASK;
+                cluster_index >>= APN806_CLUSTER_NUM_OFFSET;
+
+                /* Initialize once for one cluster */
+                if (ap_cpu_data->hws[cluster_index])
+                        continue;
+
+                parent = of_clk_get(np, cluster_index);
+                if (IS_ERR(parent)) {
+                        dev_err(dev, "Could not get the clock parent\n");
+                        return -EINVAL;
+                }
+                parent_name =  __clk_get_name(parent);
+                clk_name[12] += cluster_index;
+                ap_cpu_clk[cluster_index].clk_name =
+                        ap_cp_unique_name(dev, np->parent, clk_name);
+                ap_cpu_clk[cluster_index].cluster = cluster_index;
+                ap_cpu_clk[cluster_index].pll_cr_base = regmap;
+                ap_cpu_clk[cluster_index].hw.init = &init;
+                ap_cpu_clk[cluster_index].dev = dev;
+                ap_cpu_clk[cluster_index].pll_regs = of_device_get_match_data(&pdev->dev);
+
+                init.name = ap_cpu_clk[cluster_index].clk_name;
+                init.ops = &ap_cpu_clk_ops;
+                init.num_parents = 1;
+                init.parent_names = &parent_name;
+
+                ret = devm_clk_hw_register(dev, &ap_cpu_clk[cluster_index].hw);
+                if (ret)
+                        return ret;
+                ap_cpu_data->hws[cluster_index] = &ap_cpu_clk[cluster_index].hw;
+        }
+
+        ap_cpu_data->num = cluster_index + 1;
+
+        ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, ap_cpu_data);
+        if (ret)
+                dev_err(dev, "failed to register OF clock provider\n");
+
+        return ret;
+}
+
+static const struct of_device_id ap_cpu_clock_of_match[] = {
+        {
+                .compatible = "marvell,ap806-cpu-clock",
+                .data = &ap806_dfs_regs,
+        },
+        {
+                .compatible = "marvell,ap807-cpu-clock",
+                .data = &ap807_dfs_regs,
+        },
+        { }
+};
+
+static struct platform_driver ap_cpu_clock_driver = {
+        .probe = ap_cpu_clock_probe,
+        .driver         = {
+                .name   = "marvell-ap-cpu-clock",
+                .of_match_table = ap_cpu_clock_of_match,
+                .suppress_bind_attrs = true,
+        },
+};
+builtin_platform_driver(ap_cpu_clock_driver);
diff --git a/drivers/clk/mvebu/ap806-system-controller.c b/drivers/clk/mvebu/ap806-system-controller.c
index ea54a874bbda..948bd1e71aea 100644
--- a/drivers/clk/mvebu/ap806-system-controller.c
+++ b/drivers/clk/mvebu/ap806-system-controller.c
@@ -10,18 +10,18 @@
 
 #define pr_fmt(fmt) "ap806-system-controller: " fmt
 
+#include "armada_ap_cp_helper.h"
 #include <linux/clk-provider.h>
 #include <linux/mfd/syscon.h>
 #include <linux/init.h>
 #include <linux/of.h>
-#include <linux/of_address.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
 
 #define AP806_SAR_REG                   0x400
 #define AP806_SAR_CLKFREQ_MODE_MASK     0x1f
 
-#define AP806_CLK_NUM                   5
+#define AP806_CLK_NUM                   6
 
 static struct clk *ap806_clks[AP806_CLK_NUM];
 
@@ -30,86 +30,149 @@ static struct clk_onecell_data ap806_clk_data = {
         .clk_num = AP806_CLK_NUM,
 };
 
-static char *ap806_unique_name(struct device *dev, struct device_node *np,
-                               char *name)
+static int ap806_get_sar_clocks(unsigned int freq_mode,
+                                unsigned int *cpuclk_freq,
+                                unsigned int *dclk_freq)
 {
-        const __be32 *reg;
-        u64 addr;
-
-        reg = of_get_property(np, "reg", NULL);
-        addr = of_translate_address(np, reg);
-        return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s",
-                        (unsigned long long)addr, name);
-}
-
-static int ap806_syscon_common_probe(struct platform_device *pdev,
-                                     struct device_node *syscon_node)
-{
-        unsigned int freq_mode, cpuclk_freq;
-        const char *name, *fixedclk_name;
-        struct device *dev = &pdev->dev;
-        struct device_node *np = dev->of_node;
-        struct regmap *regmap;
-        u32 reg;
-        int ret;
-
-        regmap = syscon_node_to_regmap(syscon_node);
-        if (IS_ERR(regmap)) {
-                dev_err(dev, "cannot get regmap\n");
-                return PTR_ERR(regmap);
-        }
-
-        ret = regmap_read(regmap, AP806_SAR_REG, &reg);
-        if (ret) {
-                dev_err(dev, "cannot read from regmap\n");
-                return ret;
-        }
-
-        freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
         switch (freq_mode) {
         case 0x0:
+                *cpuclk_freq = 2000;
+                *dclk_freq = 600;
+                break;
         case 0x1:
-                cpuclk_freq = 2000;
+                *cpuclk_freq = 2000;
+                *dclk_freq = 525;
                 break;
         case 0x6:
+                *cpuclk_freq = 1800;
+                *dclk_freq = 600;
+                break;
         case 0x7:
-                cpuclk_freq = 1800;
+                *cpuclk_freq = 1800;
+                *dclk_freq = 525;
                 break;
         case 0x4:
+                *cpuclk_freq = 1600;
+                *dclk_freq = 400;
+                break;
         case 0xB:
+                *cpuclk_freq = 1600;
+                *dclk_freq = 450;
+                break;
         case 0xD:
-                cpuclk_freq = 1600;
+                *cpuclk_freq = 1600;
+                *dclk_freq = 525;
                 break;
         case 0x1a:
-                cpuclk_freq = 1400;
+                *cpuclk_freq = 1400;
+                *dclk_freq = 400;
                 break;
         case 0x14:
+                *cpuclk_freq = 1300;
+                *dclk_freq = 400;
+                break;
         case 0x17:
-                cpuclk_freq = 1300;
+                *cpuclk_freq = 1300;
+                *dclk_freq = 325;
                 break;
         case 0x19:
-                cpuclk_freq = 1200;
+                *cpuclk_freq = 1200;
+                *dclk_freq = 400;
                 break;
         case 0x13:
+                *cpuclk_freq = 1000;
+                *dclk_freq = 325;
+                break;
         case 0x1d:
-                cpuclk_freq = 1000;
+                *cpuclk_freq = 1000;
+                *dclk_freq = 400;
                 break;
         case 0x1c:
-                cpuclk_freq = 800;
+                *cpuclk_freq = 800;
+                *dclk_freq = 400;
                 break;
         case 0x1b:
-                cpuclk_freq = 600;
+                *cpuclk_freq = 600;
+                *dclk_freq = 400;
                 break;
         default:
-                dev_err(dev, "invalid SAR value\n");
                 return -EINVAL;
         }
 
+        return 0;
+}
+
+static int ap807_get_sar_clocks(unsigned int freq_mode,
+                                unsigned int *cpuclk_freq,
+                                unsigned int *dclk_freq)
+{
+        switch (freq_mode) {
+        case 0x0:
+                *cpuclk_freq = 2000;
+                *dclk_freq = 1200;
+                break;
+        case 0x6:
+                *cpuclk_freq = 2200;
+                *dclk_freq = 1200;
+                break;
+        case 0xD:
+                *cpuclk_freq = 1600;
+                *dclk_freq = 1200;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int ap806_syscon_common_probe(struct platform_device *pdev,
+                                     struct device_node *syscon_node)
+{
+        unsigned int freq_mode, cpuclk_freq, dclk_freq;
+        const char *name, *fixedclk_name;
+        struct device *dev = &pdev->dev;
+        struct device_node *np = dev->of_node;
+        struct regmap *regmap;
+        u32 reg;
+        int ret;
+
+        regmap = syscon_node_to_regmap(syscon_node);
+        if (IS_ERR(regmap)) {
+                dev_err(dev, "cannot get regmap\n");
+                return PTR_ERR(regmap);
+        }
+
+        ret = regmap_read(regmap, AP806_SAR_REG, &reg);
+        if (ret) {
+                dev_err(dev, "cannot read from regmap\n");
+                return ret;
+        }
+
+        freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
+
+        if (of_device_is_compatible(pdev->dev.of_node,
+                                    "marvell,ap806-clock")) {
+                ret = ap806_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
+        } else if (of_device_is_compatible(pdev->dev.of_node,
+                                           "marvell,ap807-clock")) {
+                ret = ap807_get_sar_clocks(freq_mode, &cpuclk_freq, &dclk_freq);
+        } else {
+                dev_err(dev, "compatible not supported\n");
+                return -EINVAL;
+        }
+
+        if (ret) {
+                dev_err(dev, "invalid Sample at Reset value\n");
+                return ret;
+        }
+
         /* Convert to hertz */
         cpuclk_freq *= 1000 * 1000;
+        dclk_freq *= 1000 * 1000;
 
         /* CPU clocks depend on the Sample At Reset configuration */
-        name = ap806_unique_name(dev, syscon_node, "cpu-cluster-0");
+        name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-0");
         ap806_clks[0] = clk_register_fixed_rate(dev, name, NULL,
                                                 0, cpuclk_freq);
         if (IS_ERR(ap806_clks[0])) {
@@ -117,7 +180,7 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
                 goto fail0;
         }
 
-        name = ap806_unique_name(dev, syscon_node, "cpu-cluster-1");
+        name = ap_cp_unique_name(dev, syscon_node, "pll-cluster-1");
         ap806_clks[1] = clk_register_fixed_rate(dev, name, NULL, 0,
                                                 cpuclk_freq);
         if (IS_ERR(ap806_clks[1])) {
@@ -126,7 +189,7 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
         }
 
         /* Fixed clock is always 1200 Mhz */
-        fixedclk_name = ap806_unique_name(dev, syscon_node, "fixed");
+        fixedclk_name = ap_cp_unique_name(dev, syscon_node, "fixed");
         ap806_clks[2] = clk_register_fixed_rate(dev, fixedclk_name, NULL,
                                                 0, 1200 * 1000 * 1000);
         if (IS_ERR(ap806_clks[2])) {
@@ -135,7 +198,7 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
         }
 
         /* MSS Clock is fixed clock divided by 6 */
-        name = ap806_unique_name(dev, syscon_node, "mss");
+        name = ap_cp_unique_name(dev, syscon_node, "mss");
         ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
                                                   0, 1, 6);
         if (IS_ERR(ap806_clks[3])) {
@@ -144,7 +207,7 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
         }
 
         /* SDIO(/eMMC) Clock is fixed clock divided by 3 */
-        name = ap806_unique_name(dev, syscon_node, "sdio");
+        name = ap_cp_unique_name(dev, syscon_node, "sdio");
         ap806_clks[4] = clk_register_fixed_factor(NULL, name,
                                                   fixedclk_name,
                                                   0, 1, 3);
@@ -153,6 +216,14 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
                 goto fail4;
         }
 
+        /* AP-DCLK(HCLK) Clock is DDR clock divided by 2 */
+        name = ap_cp_unique_name(dev, syscon_node, "ap-dclk");
+        ap806_clks[5] = clk_register_fixed_rate(dev, name, NULL, 0, dclk_freq);
+        if (IS_ERR(ap806_clks[5])) {
+                ret = PTR_ERR(ap806_clks[5]);
+                goto fail5;
+        }
+
         ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
         if (ret)
                 goto fail_clk_add;
@@ -160,6 +231,8 @@ static int ap806_syscon_common_probe(struct platform_device *pdev,
         return 0;
 
 fail_clk_add:
+        clk_unregister_fixed_factor(ap806_clks[5]);
+fail5:
         clk_unregister_fixed_factor(ap806_clks[4]);
 fail4:
         clk_unregister_fixed_factor(ap806_clks[3]);
@@ -206,6 +279,7 @@ builtin_platform_driver(ap806_syscon_legacy_driver);
 
 static const struct of_device_id ap806_clock_of_match[] = {
         { .compatible = "marvell,ap806-clock", },
+        { .compatible = "marvell,ap807-clock", },
         { }
 };
 
diff --git a/drivers/clk/mvebu/armada_ap_cp_helper.c b/drivers/clk/mvebu/armada_ap_cp_helper.c
new file mode 100644
index 000000000000..6a930f697ee5
--- /dev/null
+++ b/drivers/clk/mvebu/armada_ap_cp_helper.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Marvell Armada AP and CP110 helper
+ *
+ * Copyright (C) 2018 Marvell
+ *
+ * Gregory Clement <gregory.clement@bootlin.com>
+ *
+ */
+
+#include "armada_ap_cp_helper.h"
+#include <linux/device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+char *ap_cp_unique_name(struct device *dev, struct device_node *np,
+                        const char *name)
+{
+        const __be32 *reg;
+        u64 addr;
+
+        /* Do not create a name if there is no clock */
+        if (!name)
+                return NULL;
+
+        reg = of_get_property(np, "reg", NULL);
+        addr = of_translate_address(np, reg);
+        return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s",
+                              (unsigned long long)addr, name);
+}
diff --git a/drivers/clk/mvebu/armada_ap_cp_helper.h b/drivers/clk/mvebu/armada_ap_cp_helper.h
new file mode 100644
index 000000000000..810af1e5dfa4
--- /dev/null
+++ b/drivers/clk/mvebu/armada_ap_cp_helper.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __ARMADA_AP_CP_HELPER_H
+#define __ARMADA_AP_CP_HELPER_H
+
+struct device;
+struct device_node;
+
+char *ap_cp_unique_name(struct device *dev, struct device_node *np,
+                        const char *name);
+#endif
diff --git a/drivers/clk/mvebu/cp110-system-controller.c b/drivers/clk/mvebu/cp110-system-controller.c
index b6de283f45e3..808463276145 100644
--- a/drivers/clk/mvebu/cp110-system-controller.c
+++ b/drivers/clk/mvebu/cp110-system-controller.c
@@ -26,11 +26,11 @@
 
 #define pr_fmt(fmt) "cp110-system-controller: " fmt
 
+#include "armada_ap_cp_helper.h"
 #include <linux/clk-provider.h>
 #include <linux/mfd/syscon.h>
 #include <linux/init.h>
 #include <linux/of.h>
-#include <linux/of_address.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
 #include <linux/slab.h>
@@ -212,22 +212,6 @@ static struct clk_hw *cp110_of_clk_get(struct of_phandle_args *clkspec,
         return ERR_PTR(-EINVAL);
 }
 
-static char *cp110_unique_name(struct device *dev, struct device_node *np,
-                               const char *name)
-{
-        const __be32 *reg;
-        u64 addr;
-
-        /* Do not create a name if there is no clock */
-        if (!name)
-                return NULL;
-
-        reg = of_get_property(np, "reg", NULL);
-        addr = of_translate_address(np, reg);
-        return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s",
-                              (unsigned long long)addr, name);
-}
-
 static int cp110_syscon_common_probe(struct platform_device *pdev,
                                      struct device_node *syscon_node)
 {
@@ -261,7 +245,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
         cp110_clk_data->num = CP110_CLK_NUM;
 
         /* Register the PLL0 which is the root of the hw tree */
-        pll0_name = cp110_unique_name(dev, syscon_node, "pll0");
+        pll0_name = ap_cp_unique_name(dev, syscon_node, "pll0");
         hw = clk_hw_register_fixed_rate(NULL, pll0_name, NULL, 0,
                                         1000 * 1000 * 1000);
         if (IS_ERR(hw)) {
@@ -272,7 +256,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
         cp110_clks[CP110_CORE_PLL0] = hw;
 
         /* PPv2 is PLL0/3 */
-        ppv2_name = cp110_unique_name(dev, syscon_node, "ppv2-core");
+        ppv2_name = ap_cp_unique_name(dev, syscon_node, "ppv2-core");
         hw = clk_hw_register_fixed_factor(NULL, ppv2_name, pll0_name, 0, 1, 3);
         if (IS_ERR(hw)) {
                 ret = PTR_ERR(hw);
@@ -282,7 +266,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
         cp110_clks[CP110_CORE_PPV2] = hw;
 
         /* X2CORE clock is PLL0/2 */
-        x2core_name = cp110_unique_name(dev, syscon_node, "x2core");
+        x2core_name = ap_cp_unique_name(dev, syscon_node, "x2core");
         hw = clk_hw_register_fixed_factor(NULL, x2core_name, pll0_name,
                                           0, 1, 2);
         if (IS_ERR(hw)) {
@@ -293,7 +277,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
         cp110_clks[CP110_CORE_X2CORE] = hw;
 
         /* Core clock is X2CORE/2 */
-        core_name = cp110_unique_name(dev, syscon_node, "core");
+        core_name = ap_cp_unique_name(dev, syscon_node, "core");
         hw = clk_hw_register_fixed_factor(NULL, core_name, x2core_name,
                                           0, 1, 2);
         if (IS_ERR(hw)) {
@@ -303,7 +287,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
 
         cp110_clks[CP110_CORE_CORE] = hw;
         /* NAND can be either PLL0/2.5 or core clock */
-        nand_name = cp110_unique_name(dev, syscon_node, "nand-core");
+        nand_name = ap_cp_unique_name(dev, syscon_node, "nand-core");
         if (nand_clk_ctrl & NF_CLOCK_SEL_400_MASK)
                 hw = clk_hw_register_fixed_factor(NULL, nand_name,
                                                    pll0_name, 0, 2, 5);
@@ -318,7 +302,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
         cp110_clks[CP110_CORE_NAND] = hw;
 
         /* SDIO clock is PLL0/2.5 */
-        sdio_name = cp110_unique_name(dev, syscon_node, "sdio-core");
+        sdio_name = ap_cp_unique_name(dev, syscon_node, "sdio-core");
         hw = clk_hw_register_fixed_factor(NULL, sdio_name,
                                           pll0_name, 0, 2, 5);
         if (IS_ERR(hw)) {
@@ -330,7 +314,7 @@ static int cp110_syscon_common_probe(struct platform_device *pdev,
 
         /* create the unique name for all the gate clocks */
         for (i = 0; i < ARRAY_SIZE(gate_base_names); i++)
-                gate_name[i] =  cp110_unique_name(dev, syscon_node,
+                gate_name[i] =  ap_cp_unique_name(dev, syscon_node,
                                                   gate_base_names[i]);
 
         for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) {
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index e1ff83cc361e..32dbb4f09492 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -21,7 +21,6 @@ if COMMON_CLK_QCOM
 
 config QCOM_A53PLL
         tristate "MSM8916 A53 PLL"
-        default ARCH_QCOM
         help
           Support for the A53 PLL on MSM8916 devices. It provides
           the CPU with frequencies above 1GHz.
@@ -31,7 +30,6 @@ config QCOM_A53PLL
 config QCOM_CLK_APCS_MSM8916
         tristate "MSM8916 APCS Clock Controller"
         depends on QCOM_APCS_IPC || COMPILE_TEST
-        default ARCH_QCOM
         help
           Support for the APCS Clock Controller on msm8916 devices. The
           APCS is managing the mux and divider which feeds the CPUs.
@@ -292,6 +290,13 @@ config SDM_LPASSCC_845
           Say Y if you want to use the LPASS branch clocks of the LPASS clock
           controller to reset the LPASS subsystem.
 
+config SM_GCC_8150
+        tristate "SM8150 Global Clock Controller"
+        help
+          Support for the global clock controller on SM8150 devices.
+          Say Y if you want to use peripheral devices such as UART,
+          SPI, I2C, USB, SD/UFS, PCIe etc.
+
 config SPMI_PMIC_CLKDIV
         tristate "SPMI PMIC clkdiv Support"
         depends on SPMI || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index f0768fb1f037..4a813b4055d0 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
 obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
 obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
 obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
+obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
 obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
 obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
 obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 0ced4a5a9a17..055318f97991 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -32,6 +32,7 @@
 # define PLL_LOCK_DET           BIT(31)
 
 #define PLL_L_VAL(p)            ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
+#define PLL_CAL_L_VAL(p)        ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
 #define PLL_ALPHA_VAL(p)        ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
 #define PLL_ALPHA_VAL_U(p)      ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
 
@@ -44,14 +45,17 @@
 # define PLL_VCO_MASK           0x3
 
 #define PLL_USER_CTL_U(p)       ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
+#define PLL_USER_CTL_U1(p)      ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
 
 #define PLL_CONFIG_CTL(p)       ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
 #define PLL_CONFIG_CTL_U(p)     ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
+#define PLL_CONFIG_CTL_U1(p)    ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
 #define PLL_TEST_CTL(p)         ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
 #define PLL_TEST_CTL_U(p)       ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
 #define PLL_STATUS(p)           ((p)->offset + (p)->regs[PLL_OFF_STATUS])
 #define PLL_OPMODE(p)           ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
 #define PLL_FRAC(p)             ((p)->offset + (p)->regs[PLL_OFF_FRAC])
+#define PLL_CAL_VAL(p)          ((p)->offset + (p)->regs[PLL_OFF_CAL_VAL])
 
 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
         [CLK_ALPHA_PLL_TYPE_DEFAULT] =  {
@@ -96,6 +100,22 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
                 [PLL_OFF_OPMODE] = 0x2c,
                 [PLL_OFF_FRAC] = 0x38,
         },
+        [CLK_ALPHA_PLL_TYPE_TRION] = {
+                [PLL_OFF_L_VAL] = 0x04,
+                [PLL_OFF_CAL_L_VAL] = 0x08,
+                [PLL_OFF_USER_CTL] = 0x0c,
+                [PLL_OFF_USER_CTL_U] = 0x10,
+                [PLL_OFF_USER_CTL_U1] = 0x14,
+                [PLL_OFF_CONFIG_CTL] = 0x18,
+                [PLL_OFF_CONFIG_CTL_U] = 0x1c,
+                [PLL_OFF_CONFIG_CTL_U1] = 0x20,
+                [PLL_OFF_TEST_CTL] = 0x24,
+                [PLL_OFF_TEST_CTL_U] = 0x28,
+                [PLL_OFF_STATUS] = 0x30,
+                [PLL_OFF_OPMODE] = 0x38,
+                [PLL_OFF_ALPHA_VAL] = 0x40,
+                [PLL_OFF_CAL_VAL] = 0x44,
+        },
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
 
@@ -120,6 +140,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
 #define FABIA_PLL_OUT_MASK      0x7
 #define FABIA_PLL_RATE_MARGIN   500
 
+#define TRION_PLL_STANDBY       0x0
+#define TRION_PLL_RUN           0x1
+#define TRION_PLL_OUT_MASK      0x7
+
 #define pll_alpha_width(p)                                      \
                 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
                                  ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
@@ -730,6 +754,130 @@ static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
         return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
 }
 
+static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
+                                struct regmap *regmap)
+{
+        u32 mode_regval, opmode_regval;
+        int ret;
+
+        ret = regmap_read(regmap, PLL_MODE(pll), &mode_regval);
+        ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_regval);
+        if (ret)
+                return 0;
+
+        return ((opmode_regval & TRION_PLL_RUN) && (mode_regval & PLL_OUTCTRL));
+}
+
+static int clk_trion_pll_is_enabled(struct clk_hw *hw)
+{
+        struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+
+        return trion_pll_is_enabled(pll, pll->clkr.regmap);
+}
+
+static int clk_trion_pll_enable(struct clk_hw *hw)
+{
+        struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+        struct regmap *regmap = pll->clkr.regmap;
+        u32 val;
+        int ret;
+
+        ret = regmap_read(regmap, PLL_MODE(pll), &val);
+        if (ret)
+                return ret;
+
+        /* If in FSM mode, just vote for it */
+        if (val & PLL_VOTE_FSM_ENA) {
+                ret = clk_enable_regmap(hw);
+                if (ret)
+                        return ret;
+                return wait_for_pll_enable_active(pll);
+        }
+
+        /* Set operation mode to RUN */
+        regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_RUN);
+
+        ret = wait_for_pll_enable_lock(pll);
+        if (ret)
+                return ret;
+
+        /* Enable the PLL outputs */
+        ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
+                                 TRION_PLL_OUT_MASK, TRION_PLL_OUT_MASK);
+        if (ret)
+                return ret;
+
+        /* Enable the global PLL outputs */
+        return regmap_update_bits(regmap, PLL_MODE(pll),
+                                 PLL_OUTCTRL, PLL_OUTCTRL);
+}
+
+static void clk_trion_pll_disable(struct clk_hw *hw)
+{
+        struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+        struct regmap *regmap = pll->clkr.regmap;
+        u32 val;
+        int ret;
+
+        ret = regmap_read(regmap, PLL_MODE(pll), &val);
+        if (ret)
+                return;
+
+        /* If in FSM mode, just unvote it */
+        if (val & PLL_VOTE_FSM_ENA) {
+                clk_disable_regmap(hw);
+                return;
+        }
+
+        /* Disable the global PLL output */
+        ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
+        if (ret)
+                return;
+
+        /* Disable the PLL outputs */
+        ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
+                                 TRION_PLL_OUT_MASK, 0);
+        if (ret)
+                return;
+
+        /* Place the PLL mode in STANDBY */
+        regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_STANDBY);
+        regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
+}
+
+static unsigned long
+clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+        struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+        struct regmap *regmap = pll->clkr.regmap;
+        u32 l, frac;
+        u64 prate = parent_rate;
+
+        regmap_read(regmap, PLL_L_VAL(pll), &l);
+        regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
+
+        return alpha_pll_calc_rate(prate, l, frac, ALPHA_REG_16BIT_WIDTH);
+}
+
+static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+                                     unsigned long *prate)
+{
+        struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+        unsigned long min_freq, max_freq;
+        u32 l;
+        u64 a;
+
+        rate = alpha_pll_round_rate(rate, *prate,
+                                    &l, &a, ALPHA_REG_16BIT_WIDTH);
+        if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
+                return rate;
+
+        min_freq = pll->vco_table[0].min_freq;
+        max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
+
+        return clamp(rate, min_freq, max_freq);
+}
+
 const struct clk_ops clk_alpha_pll_ops = {
         .enable = clk_alpha_pll_enable,
         .disable = clk_alpha_pll_disable,
@@ -760,6 +908,15 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = {
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
 
+const struct clk_ops clk_trion_fixed_pll_ops = {
+        .enable = clk_trion_pll_enable,
+        .disable = clk_trion_pll_disable,
+        .is_enabled = clk_trion_pll_is_enabled,
+        .recalc_rate = clk_trion_pll_recalc_rate,
+        .round_rate = clk_trion_pll_round_rate,
+};
+EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);
+
 static unsigned long
 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 {
@@ -832,7 +989,7 @@ static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
         int div;
 
         /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
-        div = DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
+        div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1;
 
         return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
                                   PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
@@ -1036,11 +1193,6 @@ static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
         u32 i, div = 1, val;
         int ret;
 
-        if (!pll->post_div_table) {
-                pr_err("Missing the post_div_table for the PLL\n");
-                return -EINVAL;
-        }
-
         ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
         if (ret)
                 return ret;
@@ -1058,16 +1210,71 @@ static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
         return (parent_rate / div);
 }
 
-static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
-                                unsigned long rate, unsigned long *prate)
+static unsigned long
+clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 {
         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
+        struct regmap *regmap = pll->clkr.regmap;
+        u32 i, div = 1, val;
 
-        if (!pll->post_div_table) {
-                pr_err("Missing the post_div_table for the PLL\n");
-                return -EINVAL;
+        regmap_read(regmap, PLL_USER_CTL(pll), &val);
+
+        val >>= pll->post_div_shift;
+        val &= PLL_POST_DIV_MASK(pll);
+
+        for (i = 0; i < pll->num_post_div; i++) {
+                if (pll->post_div_table[i].val == val) {
+                        div = pll->post_div_table[i].div;
+                        break;
+                }
+        }
+
+        return (parent_rate / div);
+}
+
+static long
+clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
+                                 unsigned long *prate)
+{
+        struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
+
+        return divider_round_rate(hw, rate, prate, pll->post_div_table,
+                                  pll->width, CLK_DIVIDER_ROUND_CLOSEST);
+};
+
+static int
+clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
+                               unsigned long parent_rate)
+{
+        struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
+        struct regmap *regmap = pll->clkr.regmap;
+        int i, val = 0, div;
+
+        div = DIV_ROUND_UP_ULL(parent_rate, rate);
+        for (i = 0; i < pll->num_post_div; i++) {
+                if (pll->post_div_table[i].div == div) {
+                        val = pll->post_div_table[i].val;
+                        break;
+                }
         }
 
+        return regmap_update_bits(regmap, PLL_USER_CTL(pll),
+                                  PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
+                                  val << PLL_POST_DIV_SHIFT);
+}
+
+const struct clk_ops clk_trion_pll_postdiv_ops = {
+        .recalc_rate = clk_trion_pll_postdiv_recalc_rate,
+        .round_rate = clk_trion_pll_postdiv_round_rate,
+        .set_rate = clk_trion_pll_postdiv_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_trion_pll_postdiv_ops);
+
+static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
+                                unsigned long rate, unsigned long *prate)
+{
+        struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
+
         return divider_round_rate(hw, rate, prate, pll->post_div_table,
                                 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
 }
@@ -1089,12 +1296,7 @@ static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
         if (val & PLL_VOTE_FSM_ENA)
                 return 0;
 
-        if (!pll->post_div_table) {
-                pr_err("Missing the post_div_table for the PLL\n");
-                return -EINVAL;
-        }
-
-        div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+        div = DIV_ROUND_UP_ULL(parent_rate, rate);
         for (i = 0; i < pll->num_post_div; i++) {
                 if (pll->post_div_table[i].div == div) {
                         val = pll->post_div_table[i].val;
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index 66755f0f84fc..15f27f4b06df 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -13,22 +13,27 @@ enum {
         CLK_ALPHA_PLL_TYPE_HUAYRA,
         CLK_ALPHA_PLL_TYPE_BRAMMO,
         CLK_ALPHA_PLL_TYPE_FABIA,
+        CLK_ALPHA_PLL_TYPE_TRION,
         CLK_ALPHA_PLL_TYPE_MAX,
 };
 
 enum {
         PLL_OFF_L_VAL,
+        PLL_OFF_CAL_L_VAL,
         PLL_OFF_ALPHA_VAL,
         PLL_OFF_ALPHA_VAL_U,
         PLL_OFF_USER_CTL,
         PLL_OFF_USER_CTL_U,
+        PLL_OFF_USER_CTL_U1,
         PLL_OFF_CONFIG_CTL,
         PLL_OFF_CONFIG_CTL_U,
+        PLL_OFF_CONFIG_CTL_U1,
         PLL_OFF_TEST_CTL,
         PLL_OFF_TEST_CTL_U,
         PLL_OFF_STATUS,
         PLL_OFF_OPMODE,
         PLL_OFF_FRAC,
+        PLL_OFF_CAL_VAL,
         PLL_OFF_MAX_REGS
 };
 
@@ -117,5 +122,7 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
                              const struct alpha_pll_config *config);
 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
                                 const struct alpha_pll_config *config);
+extern const struct clk_ops clk_trion_fixed_pll_ops;
+extern const struct clk_ops clk_trion_pll_postdiv_ops;
 
 #endif
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 8c02bffe50df..57dbac9a590e 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -119,7 +119,7 @@ static int update_config(struct clk_rcg2 *rcg)
         }
 
         WARN(1, "%s: rcg didn't update its configuration.", name);
-        return 0;
+        return -EBUSY;
 }
 
 static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index c3fd632af119..49694082e9ec 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -95,7 +95,10 @@ static DEFINE_MUTEX(rpmh_clk_lock);
                 .hw.init = &(struct clk_init_data){                     \
                         .ops = &clk_rpmh_ops,                           \
                         .name = #_name,                                 \
-                        .parent_names = (const char *[]){ "xo_board" }, \
+                        .parent_data =  &(const struct clk_parent_data){ \
+                                        .fw_name = "xo",                \
+                                        .name = "xo_board",             \
+                        },                                              \
                         .num_parents = 1,                               \
                 },                                                      \
         };                                                              \
@@ -110,7 +113,10 @@ static DEFINE_MUTEX(rpmh_clk_lock);
                 .hw.init = &(struct clk_init_data){                     \
                         .ops = &clk_rpmh_ops,                           \
                         .name = #_name_active,                          \
-                        .parent_names = (const char *[]){ "xo_board" }, \
+                        .parent_data =  &(const struct clk_parent_data){ \
+                                        .fw_name = "xo",                \
+                                        .name = "xo_board",             \
+                        },                                              \
                         .num_parents = 1,                               \
                 },                                                      \
         }
@@ -368,6 +374,33 @@ static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
         .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),
 };
 
+DEFINE_CLK_RPMH_ARC(sm8150, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
+DEFINE_CLK_RPMH_VRM(sm8150, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
+DEFINE_CLK_RPMH_VRM(sm8150, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
+DEFINE_CLK_RPMH_VRM(sm8150, rf_clk1, rf_clk1_ao, "rfclka1", 1);
+DEFINE_CLK_RPMH_VRM(sm8150, rf_clk2, rf_clk2_ao, "rfclka2", 1);
+DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1);
+
+static struct clk_hw *sm8150_rpmh_clocks[] = {
+        [RPMH_CXO_CLK]          = &sm8150_bi_tcxo.hw,
+        [RPMH_CXO_CLK_A]        = &sm8150_bi_tcxo_ao.hw,
+        [RPMH_LN_BB_CLK2]       = &sm8150_ln_bb_clk2.hw,
+        [RPMH_LN_BB_CLK2_A]     = &sm8150_ln_bb_clk2_ao.hw,
+        [RPMH_LN_BB_CLK3]       = &sm8150_ln_bb_clk3.hw,
+        [RPMH_LN_BB_CLK3_A]     = &sm8150_ln_bb_clk3_ao.hw,
+        [RPMH_RF_CLK1]          = &sm8150_rf_clk1.hw,
+        [RPMH_RF_CLK1_A]        = &sm8150_rf_clk1_ao.hw,
+        [RPMH_RF_CLK2]          = &sm8150_rf_clk2.hw,
+        [RPMH_RF_CLK2_A]        = &sm8150_rf_clk2_ao.hw,
+        [RPMH_RF_CLK3]          = &sm8150_rf_clk3.hw,
+        [RPMH_RF_CLK3_A]        = &sm8150_rf_clk3_ao.hw,
+};
+
+static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
+        .clks = sm8150_rpmh_clocks,
+        .num_clks = ARRAY_SIZE(sm8150_rpmh_clocks),
+};
+
 static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
                                          void *data)
 {
@@ -447,6 +480,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
 
 static const struct of_device_id clk_rpmh_match_table[] = {
         { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
+        { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
         { }
 };
 MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index a6b2f86112d8..28ddc747d703 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -306,4 +306,24 @@ int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc)
 }
 EXPORT_SYMBOL_GPL(qcom_cc_probe);
 
+int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
+                           const struct qcom_cc_desc *desc)
+{
+        struct regmap *regmap;
+        struct resource *res;
+        void __iomem *base;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, index);
+        base = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(base))
+                return -ENOMEM;
+
+        regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config);
+        if (IS_ERR(regmap))
+                return PTR_ERR(regmap);
+
+        return qcom_cc_really_probe(pdev, desc, regmap);
+}
+EXPORT_SYMBOL_GPL(qcom_cc_probe_by_index);
+
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index 1e2a8bdac55a..bb39a7e106d8 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -61,5 +61,7 @@ extern int qcom_cc_really_probe(struct platform_device *pdev,
                                 struct regmap *regmap);
 extern int qcom_cc_probe(struct platform_device *pdev,
                          const struct qcom_cc_desc *desc);
+extern int qcom_cc_probe_by_index(struct platform_device *pdev, int index,
+                                  const struct qcom_cc_desc *desc);
 
 #endif
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index 39ade58b4ada..e01f5f591d1e 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -1108,7 +1108,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
                 .name = "sdcc2_apps_clk_src",
                 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
                 .num_parents = 4,
-                .ops = &clk_rcg2_ops,
+                .ops = &clk_rcg2_floor_ops,
         },
 };
 
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index 033688264c7b..091acd59c1d6 100644
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -1042,7 +1042,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
                 .name = "sdcc2_apps_clk_src",
                 .parent_names = gcc_parent_names_4,
                 .num_parents = 4,
-                .ops = &clk_rcg2_ops,
+                .ops = &clk_rcg2_floor_ops,
         },
 };
 
@@ -1066,7 +1066,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
                 .name = "sdcc4_apps_clk_src",
                 .parent_names = gcc_parent_names_1,
                 .num_parents = 3,
-                .ops = &clk_rcg2_ops,
+                .ops = &clk_rcg2_floor_ops,
         },
 };
 
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index 29cf464dd2c8..bd32212f37e6 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -1057,7 +1057,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
                 .name = "sdcc1_apps_clk_src",
                 .parent_names = gcc_parent_names_13,
                 .num_parents = 5,
-                .ops = &clk_rcg2_ops,
+                .ops = &clk_rcg2_floor_ops,
         },
 };
 
@@ -1103,7 +1103,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
                 .name = "sdcc2_apps_clk_src",
                 .parent_names = gcc_parent_names_14,
                 .num_parents = 4,
-                .ops = &clk_rcg2_ops,
+                .ops = &clk_rcg2_floor_ops,
         },
 };
 
@@ -2604,6 +2604,32 @@ static struct clk_branch gcc_usb_hs_system_clk = {
         },
 };
 
+static struct clk_branch gcc_wdsp_q6ss_ahbs_clk = {
+        .halt_reg = 0x1e004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x1e004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_wdsp_q6ss_ahbs_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_wdsp_q6ss_axim_clk = {
+        .halt_reg = 0x1e008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x1e008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_wdsp_q6ss_axim_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
 static struct clk_hw *gcc_qcs404_hws[] = {
         &cxo.hw,
 };
@@ -2749,6 +2775,9 @@ static struct clk_regmap *gcc_qcs404_clocks[] = {
         [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
         [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
         [GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr,
+        [GCC_WCSS_Q6_AHB_CLK] = &gcc_wdsp_q6ss_ahbs_clk.clkr,
+        [GCC_WCSS_Q6_AXIM_CLK] =  &gcc_wdsp_q6ss_axim_clk.clkr,
+
 };
 
 static const struct qcom_reset_map gcc_qcs404_resets[] = {
@@ -2774,6 +2803,7 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = {
         [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
         [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
         [GCC_EMAC_BCR] = { 0x4e000 },
+        [GCC_WDSP_RESTART] = {0x19000},
 };
 
 static const struct regmap_config gcc_qcs404_regmap_config = {
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
index 8827db23066f..bf5730832ef3 100644
--- a/drivers/clk/qcom/gcc-sdm660.c
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -787,7 +787,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
                 .name = "sdcc2_apps_clk_src",
                 .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4,
                 .num_parents = 4,
-                .ops = &clk_rcg2_ops,
+                .ops = &clk_rcg2_floor_ops,
         },
 };
 
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index 7131dcf9b060..95be125c3bdd 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -685,7 +685,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
                 .name = "gcc_sdcc2_apps_clk_src",
                 .parent_names = gcc_parent_names_10,
                 .num_parents = 5,
-                .ops = &clk_rcg2_ops,
+                .ops = &clk_rcg2_floor_ops,
         },
 };
 
@@ -709,7 +709,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
                 .name = "gcc_sdcc4_apps_clk_src",
                 .parent_names = gcc_parent_names_0,
                 .num_parents = 4,
-                .ops = &clk_rcg2_ops,
+                .ops = &clk_rcg2_floor_ops,
         },
 };
 
diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
new file mode 100644
index 000000000000..20877214acff
--- /dev/null
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -0,0 +1,3588 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
+
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/clock/qcom,gcc-sm8150.h>
+
+#include "common.h"
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "reset.h"
+
+enum {
+        P_BI_TCXO,
+        P_AUD_REF_CLK,
+        P_CORE_BI_PLL_TEST_SE,
+        P_GPLL0_OUT_EVEN,
+        P_GPLL0_OUT_MAIN,
+        P_GPLL7_OUT_MAIN,
+        P_GPLL9_OUT_MAIN,
+        P_SLEEP_CLK,
+};
+
+static const struct pll_vco trion_vco[] = {
+        { 249600000, 2000000000, 0 },
+};
+
+static struct clk_alpha_pll gpll0 = {
+        .offset = 0x0,
+        .vco_table = trion_vco,
+        .num_vco = ARRAY_SIZE(trion_vco),
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
+        .clkr = {
+                .enable_reg = 0x52000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gpll0",
+                        .parent_data = &(const struct clk_parent_data){
+                                .fw_name = "bi_tcxo",
+                                .name = "bi_tcxo",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_trion_fixed_pll_ops,
+                },
+        },
+};
+
+static const struct clk_div_table post_div_table_trion_even[] = {
+        { 0x0, 1 },
+        { 0x1, 2 },
+        { 0x3, 4 },
+        { 0x7, 8 },
+        { }
+};
+
+static struct clk_alpha_pll_postdiv gpll0_out_even = {
+        .offset = 0x0,
+        .post_div_shift = 8,
+        .post_div_table = post_div_table_trion_even,
+        .num_post_div = ARRAY_SIZE(post_div_table_trion_even),
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
+        .width = 4,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gpll0_out_even",
+                .parent_data = &(const struct clk_parent_data){
+                        .fw_name = "bi_tcxo",
+                        .name = "bi_tcxo",
+                },
+                .num_parents = 1,
+                .ops = &clk_trion_pll_postdiv_ops,
+        },
+};
+
+static struct clk_alpha_pll gpll7 = {
+        .offset = 0x1a000,
+        .vco_table = trion_vco,
+        .num_vco = ARRAY_SIZE(trion_vco),
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
+        .clkr = {
+                .enable_reg = 0x52000,
+                .enable_mask = BIT(7),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gpll7",
+                        .parent_data = &(const struct clk_parent_data){
+                                .fw_name = "bi_tcxo",
+                                .name = "bi_tcxo",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_trion_fixed_pll_ops,
+                },
+        },
+};
+
+static struct clk_alpha_pll gpll9 = {
+        .offset = 0x1c000,
+        .vco_table = trion_vco,
+        .num_vco = ARRAY_SIZE(trion_vco),
+        .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
+        .clkr = {
+                .enable_reg = 0x52000,
+                .enable_mask = BIT(9),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gpll9",
+                        .parent_data = &(const struct clk_parent_data){
+                                .fw_name = "bi_tcxo",
+                                .name = "bi_tcxo",
+                        },
+                        .num_parents = 1,
+                        .ops = &clk_trion_fixed_pll_ops,
+                },
+        },
+};
+
+static const struct parent_map gcc_parent_map_0[] = {
+        { P_BI_TCXO, 0 },
+        { P_GPLL0_OUT_MAIN, 1 },
+        { P_GPLL0_OUT_EVEN, 6 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data gcc_parents_0[] = {
+        { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+        { .hw = &gpll0.clkr.hw },
+        { .hw = &gpll0_out_even.clkr.hw },
+        { .fw_name = "core_bi_pll_test_se" },
+};
+
+static const struct parent_map gcc_parent_map_1[] = {
+        { P_BI_TCXO, 0 },
+        { P_GPLL0_OUT_MAIN, 1 },
+        { P_SLEEP_CLK, 5 },
+        { P_GPLL0_OUT_EVEN, 6 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data gcc_parents_1[] = {
+        { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+        { .hw = &gpll0.clkr.hw },
+        { .fw_name = "sleep_clk", .name = "sleep_clk" },
+        { .hw = &gpll0_out_even.clkr.hw },
+        { .fw_name = "core_bi_pll_test_se" },
+};
+
+static const struct parent_map gcc_parent_map_2[] = {
+        { P_BI_TCXO, 0 },
+        { P_SLEEP_CLK, 5 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data gcc_parents_2[] = {
+        { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+        { .fw_name = "sleep_clk", .name = "sleep_clk" },
+        { .fw_name = "core_bi_pll_test_se" },
+};
+
+static const struct parent_map gcc_parent_map_3[] = {
+        { P_BI_TCXO, 0 },
+        { P_GPLL0_OUT_MAIN, 1 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data gcc_parents_3[] = {
+        { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+        { .hw = &gpll0.clkr.hw },
+        { .fw_name = "core_bi_pll_test_se"},
+};
+
+static const struct parent_map gcc_parent_map_4[] = {
+        { P_BI_TCXO, 0 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data gcc_parents_4[] = {
+        { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+        { .fw_name = "core_bi_pll_test_se" },
+};
+
+static const struct parent_map gcc_parent_map_5[] = {
+        { P_BI_TCXO, 0 },
+        { P_GPLL0_OUT_MAIN, 1 },
+        { P_GPLL7_OUT_MAIN, 3 },
+        { P_GPLL0_OUT_EVEN, 6 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data gcc_parents_5[] = {
+        { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+        { .hw = &gpll0.clkr.hw },
+        { .hw = &gpll7.clkr.hw },
+        { .hw = &gpll0_out_even.clkr.hw },
+        { .fw_name = "core_bi_pll_test_se" },
+};
+
+static const struct parent_map gcc_parent_map_6[] = {
+        { P_BI_TCXO, 0 },
+        { P_GPLL0_OUT_MAIN, 1 },
+        { P_GPLL9_OUT_MAIN, 2 },
+        { P_GPLL0_OUT_EVEN, 6 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data gcc_parents_6[] = {
+        { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+        { .hw = &gpll0.clkr.hw },
+        { .hw = &gpll9.clkr.hw },
+        { .hw = &gpll0_out_even.clkr.hw },
+        { .fw_name = "core_bi_pll_test_se" },
+};
+
+static const struct parent_map gcc_parent_map_7[] = {
+        { P_BI_TCXO, 0 },
+        { P_GPLL0_OUT_MAIN, 1 },
+        { P_AUD_REF_CLK, 2 },
+        { P_GPLL0_OUT_EVEN, 6 },
+        { P_CORE_BI_PLL_TEST_SE, 7 },
+};
+
+static const struct clk_parent_data gcc_parents_7[] = {
+        { .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+        { .hw = &gpll0.clkr.hw },
+        { .fw_name = "aud_ref_clk", .name = "aud_ref_clk" },
+        { .hw = &gpll0_out_even.clkr.hw },
+        { .fw_name = "core_bi_pll_test_se" },
+};
+
+static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
+        F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
+        .cmd_rcgr = 0x48014,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_cpuss_ahb_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = {
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
+        F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
+        F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_emac_ptp_clk_src = {
+        .cmd_rcgr = 0x6038,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_5,
+        .freq_tbl = ftbl_gcc_emac_ptp_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_emac_ptp_clk_src",
+                .parent_data = gcc_parents_5,
+                .num_parents = 5,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
+        F(2500000, P_BI_TCXO, 1, 25, 192),
+        F(5000000, P_BI_TCXO, 1, 25, 96),
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
+        F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
+        F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
+        F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
+        .cmd_rcgr = 0x601c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_5,
+        .freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_emac_rgmii_clk_src",
+                .parent_data = gcc_parents_5,
+                .num_parents = 5,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
+        F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
+        F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+        F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_gp1_clk_src = {
+        .cmd_rcgr = 0x64004,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_gcc_gp1_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_gp1_clk_src",
+                .parent_data = gcc_parents_1,
+                .num_parents = 5,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_gp2_clk_src = {
+        .cmd_rcgr = 0x65004,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_gcc_gp1_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_gp2_clk_src",
+                .parent_data = gcc_parents_1,
+                .num_parents = 5,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_gp3_clk_src = {
+        .cmd_rcgr = 0x66004,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_1,
+        .freq_tbl = ftbl_gcc_gp1_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_gp3_clk_src",
+                .parent_data = gcc_parents_1,
+                .num_parents = 5,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
+        F(9600000, P_BI_TCXO, 2, 0, 0),
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
+        .cmd_rcgr = 0x6b02c,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_2,
+        .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_pcie_0_aux_clk_src",
+                .parent_data = gcc_parents_2,
+                .num_parents = 3,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
+        .cmd_rcgr = 0x8d02c,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_2,
+        .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_pcie_1_aux_clk_src",
+                .parent_data = gcc_parents_2,
+                .num_parents = 3,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = {
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
+        .cmd_rcgr = 0x6f014,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_pcie_phy_refgen_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
+        F(9600000, P_BI_TCXO, 2, 0, 0),
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_pdm2_clk_src = {
+        .cmd_rcgr = 0x33010,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_pdm2_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_pdm2_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_qspi_core_clk_src[] = {
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
+        F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+        F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_qspi_core_clk_src = {
+        .cmd_rcgr = 0x4b008,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qspi_core_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qspi_core_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
+        F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625),
+        F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625),
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        F(29491200, P_GPLL0_OUT_EVEN, 1, 1536, 15625),
+        F(32000000, P_GPLL0_OUT_EVEN, 1, 8, 75),
+        F(48000000, P_GPLL0_OUT_EVEN, 1, 4, 25),
+        F(64000000, P_GPLL0_OUT_EVEN, 1, 16, 75),
+        F(80000000, P_GPLL0_OUT_EVEN, 1, 4, 15),
+        F(96000000, P_GPLL0_OUT_EVEN, 1, 8, 25),
+        F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
+        F(102400000, P_GPLL0_OUT_EVEN, 1, 128, 375),
+        F(112000000, P_GPLL0_OUT_EVEN, 1, 28, 75),
+        F(117964800, P_GPLL0_OUT_EVEN, 1, 6144, 15625),
+        F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
+        F(128000000, P_GPLL0_OUT_MAIN, 1, 16, 75),
+        { }
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
+        .cmd_rcgr = 0x17148,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap0_s0_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
+        .cmd_rcgr = 0x17278,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap0_s1_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
+        .cmd_rcgr = 0x173a8,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap0_s2_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
+        .cmd_rcgr = 0x174d8,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap0_s3_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
+        .cmd_rcgr = 0x17608,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap0_s4_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
+        .cmd_rcgr = 0x17738,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap0_s5_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
+        .cmd_rcgr = 0x17868,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap0_s6_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
+        .cmd_rcgr = 0x17998,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap0_s7_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
+        .cmd_rcgr = 0x18148,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap1_s0_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
+        .cmd_rcgr = 0x18278,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap1_s1_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
+        .cmd_rcgr = 0x183a8,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap1_s2_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
+        .cmd_rcgr = 0x184d8,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap1_s3_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
+        .cmd_rcgr = 0x18608,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap1_s4_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
+        .cmd_rcgr = 0x18738,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap1_s5_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
+        .cmd_rcgr = 0x1e148,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap2_s0_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
+        .cmd_rcgr = 0x1e278,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap2_s1_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
+        .cmd_rcgr = 0x1e3a8,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap2_s2_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
+        .cmd_rcgr = 0x1e4d8,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap2_s3_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
+        .cmd_rcgr = 0x1e608,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap2_s4_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
+        .cmd_rcgr = 0x1e738,
+        .mnd_width = 16,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_qupv3_wrap2_s5_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
+        F(400000, P_BI_TCXO, 12, 1, 4),
+        F(9600000, P_BI_TCXO, 2, 0, 0),
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
+        F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
+        F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+        F(202000000, P_GPLL9_OUT_MAIN, 4, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
+        .cmd_rcgr = 0x1400c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_6,
+        .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_sdcc2_apps_clk_src",
+                .parent_data = gcc_parents_6,
+                .num_parents = 5,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_floor_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
+        F(400000, P_BI_TCXO, 12, 1, 4),
+        F(9600000, P_BI_TCXO, 2, 0, 0),
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),
+        F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
+        F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
+        .cmd_rcgr = 0x1600c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_3,
+        .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_sdcc4_apps_clk_src",
+                .parent_data = gcc_parents_3,
+                .num_parents = 3,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_floor_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = {
+        F(105495, P_BI_TCXO, 2, 1, 91),
+        { }
+};
+
+static struct clk_rcg2 gcc_tsif_ref_clk_src = {
+        .cmd_rcgr = 0x36010,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_7,
+        .freq_tbl = ftbl_gcc_tsif_ref_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_tsif_ref_clk_src",
+                .parent_data = gcc_parents_7,
+                .num_parents = 5,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = {
+        F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
+        F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
+        F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
+        F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+        F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
+        .cmd_rcgr = 0x75020,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_ufs_card_axi_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = {
+        F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
+        F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
+        F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+        F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
+        .cmd_rcgr = 0x75060,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_ufs_card_ice_core_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = {
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
+        .cmd_rcgr = 0x75094,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_4,
+        .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_ufs_card_phy_aux_clk_src",
+                .parent_data = gcc_parents_4,
+                .num_parents = 2,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = {
+        F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
+        F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
+        F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
+        .cmd_rcgr = 0x75078,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_ufs_card_unipro_core_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
+        F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
+        F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
+        F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
+        F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
+        F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
+        .cmd_rcgr = 0x77020,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_ufs_phy_axi_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
+        .cmd_rcgr = 0x77060,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_ufs_phy_ice_core_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
+        .cmd_rcgr = 0x77094,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_4,
+        .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_ufs_phy_phy_aux_clk_src",
+                .parent_data = gcc_parents_4,
+                .num_parents = 2,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
+        .cmd_rcgr = 0x77078,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_ufs_phy_unipro_core_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
+        F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
+        F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
+        F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
+        F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
+        F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
+        .cmd_rcgr = 0xf01c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_usb30_prim_master_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_mock_utmi_clk_src[] = {
+        F(19200000, P_BI_TCXO, 1, 0, 0),
+        F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
+        F(60000000, P_GPLL0_OUT_EVEN, 5, 0, 0),
+        { }
+};
+
+static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
+        .cmd_rcgr = 0xf034,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_usb30_prim_mock_utmi_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
+        .cmd_rcgr = 0x1001c,
+        .mnd_width = 8,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_usb30_sec_master_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
+        .cmd_rcgr = 0x10034,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_0,
+        .freq_tbl = ftbl_gcc_usb30_prim_mock_utmi_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_usb30_sec_mock_utmi_clk_src",
+                .parent_data = gcc_parents_0,
+                .num_parents = 4,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
+        .cmd_rcgr = 0xf060,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_2,
+        .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_usb3_prim_phy_aux_clk_src",
+                .parent_data = gcc_parents_2,
+                .num_parents = 3,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
+        .cmd_rcgr = 0x10060,
+        .mnd_width = 0,
+        .hid_width = 5,
+        .parent_map = gcc_parent_map_2,
+        .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src,
+        .clkr.hw.init = &(struct clk_init_data){
+                .name = "gcc_usb3_sec_phy_aux_clk_src",
+                .parent_data = gcc_parents_2,
+                .num_parents = 3,
+                .flags = CLK_SET_RATE_PARENT,
+                .ops = &clk_rcg2_ops,
+        },
+};
+
+static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = {
+        .halt_reg = 0x90018,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x90018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_aggre_noc_pcie_tbu_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
+        .halt_reg = 0x750c0,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x750c0,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x750c0,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_aggre_ufs_card_axi_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_ufs_card_axi_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_aggre_ufs_card_axi_hw_ctl_clk = {
+        .halt_reg = 0x750c0,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x750c0,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x750c0,
+                .enable_mask = BIT(1),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_aggre_ufs_card_axi_hw_ctl_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_aggre_ufs_card_axi_clk.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch_simple_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
+        .halt_reg = 0x770c0,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x770c0,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x770c0,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_aggre_ufs_phy_axi_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_ufs_phy_axi_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
+        .halt_reg = 0x770c0,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x770c0,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x770c0,
+                .enable_mask = BIT(1),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_aggre_ufs_phy_axi_clk.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch_simple_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
+        .halt_reg = 0xf07c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xf07c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_aggre_usb3_prim_axi_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_usb30_prim_master_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
+        .halt_reg = 0x1007c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x1007c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_aggre_usb3_sec_axi_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_usb30_sec_master_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_boot_rom_ahb_clk = {
+        .halt_reg = 0x38004,
+        .halt_check = BRANCH_HALT_VOTED,
+        .hwcg_reg = 0x38004,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(10),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_boot_rom_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+/*
+ * Clock ON depends on external parent 'config noc', so cant poll
+ * delay and also mark as crtitical for camss boot
+ */
+static struct clk_branch gcc_camera_ahb_clk = {
+        .halt_reg = 0xb008,
+        .halt_check = BRANCH_HALT_DELAY,
+        .hwcg_reg = 0xb008,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0xb008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camera_ahb_clk",
+                        .flags = CLK_IS_CRITICAL,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camera_hf_axi_clk = {
+        .halt_reg = 0xb030,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xb030,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camera_hf_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_camera_sf_axi_clk = {
+        .halt_reg = 0xb034,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xb034,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camera_sf_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+/* XO critical input to camss, so no need to poll */
+static struct clk_branch gcc_camera_xo_clk = {
+        .halt_reg = 0xb044,
+        .halt_check = BRANCH_HALT_DELAY,
+        .clkr = {
+                .enable_reg = 0xb044,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_camera_xo_clk",
+                        .flags = CLK_IS_CRITICAL,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
+        .halt_reg = 0xf078,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xf078,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_cfg_noc_usb3_prim_axi_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_usb30_prim_master_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
+        .halt_reg = 0x10078,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x10078,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_cfg_noc_usb3_sec_axi_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_usb30_sec_master_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_cpuss_ahb_clk = {
+        .halt_reg = 0x48000,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(21),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_cpuss_ahb_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_cpuss_ahb_clk_src.clkr.hw },
+                        .num_parents = 1,
+                         /* required for cpuss */
+                        .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_cpuss_dvm_bus_clk = {
+        .halt_reg = 0x48190,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x48190,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_cpuss_dvm_bus_clk",
+                         /* required for cpuss */
+                        .flags = CLK_IS_CRITICAL,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_cpuss_gnoc_clk = {
+        .halt_reg = 0x48004,
+        .halt_check = BRANCH_HALT_VOTED,
+        .hwcg_reg = 0x48004,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(22),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_cpuss_gnoc_clk",
+                         /* required for cpuss */
+                        .flags = CLK_IS_CRITICAL,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_cpuss_rbcpr_clk = {
+        .halt_reg = 0x48008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x48008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_cpuss_rbcpr_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ddrss_gpu_axi_clk = {
+        .halt_reg = 0x71154,
+        .halt_check = BRANCH_VOTED,
+        .clkr = {
+                .enable_reg = 0x71154,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ddrss_gpu_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+/*
+ * Clock ON depends on external parent 'config noc', so cant poll
+ * delay and also mark as crtitical for disp boot
+ */
+static struct clk_branch gcc_disp_ahb_clk = {
+        .halt_reg = 0xb00c,
+        .halt_check = BRANCH_HALT_DELAY,
+        .hwcg_reg = 0xb00c,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0xb00c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_disp_ahb_clk",
+                        .flags = CLK_IS_CRITICAL,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_disp_hf_axi_clk = {
+        .halt_reg = 0xb038,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xb038,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_disp_hf_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_disp_sf_axi_clk = {
+        .halt_reg = 0xb03c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xb03c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_disp_sf_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+/* XO critical input to disp, so no need to poll */
+static struct clk_branch gcc_disp_xo_clk = {
+        .halt_reg = 0xb048,
+        .halt_check = BRANCH_HALT_DELAY,
+        .clkr = {
+                .enable_reg = 0xb048,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_disp_xo_clk",
+                        .flags = CLK_IS_CRITICAL,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_emac_axi_clk = {
+        .halt_reg = 0x6010,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x6010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_emac_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_emac_ptp_clk = {
+        .halt_reg = 0x6034,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x6034,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_emac_ptp_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_emac_ptp_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_emac_rgmii_clk = {
+        .halt_reg = 0x6018,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x6018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_emac_rgmii_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_emac_rgmii_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_emac_slv_ahb_clk = {
+        .halt_reg = 0x6014,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x6014,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x6014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_emac_slv_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+        .halt_reg = 0x64000,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x64000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gp1_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_gp1_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+        .halt_reg = 0x65000,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x65000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gp2_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_gp2_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gp3_clk = {
+        .halt_reg = 0x66000,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x66000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gp3_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_gp3_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gpu_cfg_ahb_clk = {
+        .halt_reg = 0x71004,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x71004,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x71004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gpu_cfg_ahb_clk",
+                         /* required for gpu */
+                        .flags = CLK_IS_CRITICAL,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gpu_iref_clk = {
+        .halt_reg = 0x8c010,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x8c010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gpu_iref_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gpu_memnoc_gfx_clk = {
+        .halt_reg = 0x7100c,
+        .halt_check = BRANCH_VOTED,
+        .clkr = {
+                .enable_reg = 0x7100c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gpu_memnoc_gfx_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = {
+        .halt_reg = 0x71018,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x71018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_gpu_snoc_dvm_gfx_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_npu_at_clk = {
+        .halt_reg = 0x4d010,
+        .halt_check = BRANCH_VOTED,
+        .clkr = {
+                .enable_reg = 0x4d010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_npu_at_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_npu_axi_clk = {
+        .halt_reg = 0x4d008,
+        .halt_check = BRANCH_VOTED,
+        .clkr = {
+                .enable_reg = 0x4d008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_npu_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_npu_cfg_ahb_clk = {
+        .halt_reg = 0x4d004,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x4d004,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x4d004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_npu_cfg_ahb_clk",
+                         /* required for npu */
+                        .flags = CLK_IS_CRITICAL,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_npu_trig_clk = {
+        .halt_reg = 0x4d00c,
+        .halt_check = BRANCH_VOTED,
+        .clkr = {
+                .enable_reg = 0x4d00c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_npu_trig_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie0_phy_refgen_clk = {
+        .halt_reg = 0x6f02c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x6f02c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie0_phy_refgen_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_pcie_phy_refgen_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie1_phy_refgen_clk = {
+        .halt_reg = 0x6f030,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x6f030,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie1_phy_refgen_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_pcie_phy_refgen_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_aux_clk = {
+        .halt_reg = 0x6b020,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(3),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_aux_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_pcie_0_aux_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
+        .halt_reg = 0x6b01c,
+        .halt_check = BRANCH_HALT_VOTED,
+        .hwcg_reg = 0x6b01c,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(2),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_cfg_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_clkref_clk = {
+        .halt_reg = 0x8c00c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x8c00c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_clkref_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
+        .halt_reg = 0x6b018,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(1),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_mstr_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+/* Clock ON depends on external parent 'PIPE' clock, so dont poll */
+static struct clk_branch gcc_pcie_0_pipe_clk = {
+        .halt_reg = 0x6b024,
+        .halt_check = BRANCH_HALT_DELAY,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(4),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_pipe_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_slv_axi_clk = {
+        .halt_reg = 0x6b014,
+        .halt_check = BRANCH_HALT_VOTED,
+        .hwcg_reg = 0x6b014,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_slv_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
+        .halt_reg = 0x6b010,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(5),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_0_slv_q2a_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_1_aux_clk = {
+        .halt_reg = 0x8d020,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(29),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_1_aux_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_pcie_1_aux_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
+        .halt_reg = 0x8d01c,
+        .halt_check = BRANCH_HALT_VOTED,
+        .hwcg_reg = 0x8d01c,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(28),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_1_cfg_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_1_clkref_clk = {
+        .halt_reg = 0x8c02c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x8c02c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_1_clkref_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
+        .halt_reg = 0x8d018,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(27),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_1_mstr_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+/* Clock ON depends on external parent 'PIPE' clock, so dont poll */
+static struct clk_branch gcc_pcie_1_pipe_clk = {
+        .halt_reg = 0x8d024,
+        .halt_check = BRANCH_HALT_DELAY,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(30),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_1_pipe_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_1_slv_axi_clk = {
+        .halt_reg = 0x8d014,
+        .halt_check = BRANCH_HALT_VOTED,
+        .hwcg_reg = 0x8d014,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(26),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_1_slv_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
+        .halt_reg = 0x8d010,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(25),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_1_slv_q2a_axi_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pcie_phy_aux_clk = {
+        .halt_reg = 0x6f004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x6f004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pcie_phy_aux_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_pcie_0_aux_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pdm2_clk = {
+        .halt_reg = 0x3300c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x3300c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pdm2_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_pdm2_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pdm_ahb_clk = {
+        .halt_reg = 0x33004,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x33004,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x33004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pdm_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_pdm_xo4_clk = {
+        .halt_reg = 0x33008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x33008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_pdm_xo4_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_prng_ahb_clk = {
+        .halt_reg = 0x34004,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(13),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_prng_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
+        .halt_reg = 0xb018,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0xb018,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0xb018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qmip_camera_nrt_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
+        .halt_reg = 0xb01c,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0xb01c,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0xb01c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qmip_camera_rt_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qmip_disp_ahb_clk = {
+        .halt_reg = 0xb020,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0xb020,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0xb020,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qmip_disp_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qmip_video_cvp_ahb_clk = {
+        .halt_reg = 0xb010,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0xb010,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0xb010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qmip_video_cvp_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
+        .halt_reg = 0xb014,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0xb014,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0xb014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qmip_video_vcodec_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qspi_cnoc_periph_ahb_clk = {
+        .halt_reg = 0x4b000,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x4b000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qspi_cnoc_periph_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qspi_core_clk = {
+        .halt_reg = 0x4b004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x4b004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qspi_core_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qspi_core_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
+        .halt_reg = 0x17144,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(10),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap0_s0_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qupv3_wrap0_s0_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
+        .halt_reg = 0x17274,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(11),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap0_s1_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qupv3_wrap0_s1_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
+        .halt_reg = 0x173a4,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(12),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap0_s2_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qupv3_wrap0_s2_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
+        .halt_reg = 0x174d4,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(13),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap0_s3_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qupv3_wrap0_s3_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
+        .halt_reg = 0x17604,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(14),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap0_s4_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qupv3_wrap0_s4_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
+        .halt_reg = 0x17734,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(15),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap0_s5_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qupv3_wrap0_s5_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
+        .halt_reg = 0x17864,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(16),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap0_s6_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qupv3_wrap0_s6_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
+        .halt_reg = 0x17994,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(17),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap0_s7_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qupv3_wrap0_s7_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
+        .halt_reg = 0x18144,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(22),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap1_s0_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qupv3_wrap1_s0_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
+        .halt_reg = 0x18274,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(23),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap1_s1_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qupv3_wrap1_s1_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
+        .halt_reg = 0x183a4,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(24),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap1_s2_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qupv3_wrap1_s2_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
+        .halt_reg = 0x184d4,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(25),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap1_s3_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qupv3_wrap1_s3_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
+        .halt_reg = 0x18604,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(26),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap1_s4_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qupv3_wrap1_s4_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
+        .halt_reg = 0x18734,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(27),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap1_s5_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qupv3_wrap1_s5_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
+        .halt_reg = 0x1e144,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52014,
+                .enable_mask = BIT(4),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap2_s0_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qupv3_wrap2_s0_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
+        .halt_reg = 0x1e274,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52014,
+                .enable_mask = BIT(5),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap2_s1_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qupv3_wrap2_s1_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
+        .halt_reg = 0x1e3a4,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52014,
+                .enable_mask = BIT(6),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap2_s2_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qupv3_wrap2_s2_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
+        .halt_reg = 0x1e4d4,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52014,
+                .enable_mask = BIT(7),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap2_s3_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qupv3_wrap2_s3_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
+        .halt_reg = 0x1e604,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52014,
+                .enable_mask = BIT(8),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap2_s4_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qupv3_wrap2_s4_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
+        .halt_reg = 0x1e734,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52014,
+                .enable_mask = BIT(9),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap2_s5_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_qupv3_wrap2_s5_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = {
+        .halt_reg = 0x17004,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(6),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap_0_m_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = {
+        .halt_reg = 0x17008,
+        .halt_check = BRANCH_HALT_VOTED,
+        .hwcg_reg = 0x17008,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(7),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap_0_s_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
+        .halt_reg = 0x18004,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(20),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap_1_m_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
+        .halt_reg = 0x18008,
+        .halt_check = BRANCH_HALT_VOTED,
+        .hwcg_reg = 0x18008,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x5200c,
+                .enable_mask = BIT(21),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap_1_s_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
+        .halt_reg = 0x1e004,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52014,
+                .enable_mask = BIT(2),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap_2_m_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
+        .halt_reg = 0x1e008,
+        .halt_check = BRANCH_HALT_VOTED,
+        .hwcg_reg = 0x1e008,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x52014,
+                .enable_mask = BIT(1),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_qupv3_wrap_2_s_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc2_ahb_clk = {
+        .halt_reg = 0x14008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x14008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc2_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc2_apps_clk = {
+        .halt_reg = 0x14004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x14004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc2_apps_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_sdcc2_apps_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc4_ahb_clk = {
+        .halt_reg = 0x16008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x16008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc4_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sdcc4_apps_clk = {
+        .halt_reg = 0x16004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x16004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sdcc4_apps_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_sdcc4_apps_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = {
+        .halt_reg = 0x4819c,
+        .halt_check = BRANCH_HALT_VOTED,
+        .clkr = {
+                .enable_reg = 0x52004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_sys_noc_cpuss_ahb_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_cpuss_ahb_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        /* required for cpuss */
+                        .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_tsif_ahb_clk = {
+        .halt_reg = 0x36004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x36004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_tsif_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_tsif_inactivity_timers_clk = {
+        .halt_reg = 0x3600c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x3600c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_tsif_inactivity_timers_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_tsif_ref_clk = {
+        .halt_reg = 0x36008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x36008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_tsif_ref_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_tsif_ref_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_card_ahb_clk = {
+        .halt_reg = 0x75014,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x75014,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x75014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_card_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_card_axi_clk = {
+        .halt_reg = 0x75010,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x75010,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x75010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_card_axi_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_ufs_card_axi_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_card_axi_hw_ctl_clk = {
+        .halt_reg = 0x75010,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x75010,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x75010,
+                .enable_mask = BIT(1),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_card_axi_hw_ctl_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_ufs_card_axi_clk.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch_simple_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_card_clkref_clk = {
+        .halt_reg = 0x8c004,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x8c004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_card_clkref_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_card_ice_core_clk = {
+        .halt_reg = 0x7505c,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x7505c,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x7505c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_card_ice_core_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_ufs_card_ice_core_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_card_ice_core_hw_ctl_clk = {
+        .halt_reg = 0x7505c,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x7505c,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x7505c,
+                .enable_mask = BIT(1),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_card_ice_core_hw_ctl_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_ufs_card_ice_core_clk.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch_simple_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_card_phy_aux_clk = {
+        .halt_reg = 0x75090,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x75090,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x75090,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_card_phy_aux_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_ufs_card_phy_aux_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
+        .halt_reg = 0x75090,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x75090,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x75090,
+                .enable_mask = BIT(1),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_card_phy_aux_hw_ctl_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_ufs_card_phy_aux_clk.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch_simple_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_card_unipro_core_clk = {
+        .halt_reg = 0x75058,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x75058,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x75058,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_card_unipro_core_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                &gcc_ufs_card_unipro_core_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_card_unipro_core_hw_ctl_clk = {
+        .halt_reg = 0x75058,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x75058,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x75058,
+                .enable_mask = BIT(1),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_card_unipro_core_hw_ctl_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_ufs_card_unipro_core_clk.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch_simple_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_mem_clkref_clk = {
+        .halt_reg = 0x8c000,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x8c000,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_mem_clkref_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_phy_ahb_clk = {
+        .halt_reg = 0x77014,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x77014,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x77014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_phy_ahb_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_phy_axi_clk = {
+        .halt_reg = 0x77010,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x77010,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x77010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_phy_axi_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                &gcc_ufs_phy_axi_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
+        .halt_reg = 0x77010,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x77010,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x77010,
+                .enable_mask = BIT(1),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_phy_axi_hw_ctl_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_ufs_phy_axi_clk.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch_simple_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_phy_ice_core_clk = {
+        .halt_reg = 0x7705c,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x7705c,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x7705c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_phy_ice_core_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_ufs_phy_ice_core_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
+        .halt_reg = 0x7705c,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x7705c,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x7705c,
+                .enable_mask = BIT(1),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_ufs_phy_ice_core_clk.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch_simple_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
+        .halt_reg = 0x77090,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x77090,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x77090,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_phy_phy_aux_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_ufs_phy_phy_aux_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
+        .halt_reg = 0x77090,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x77090,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x77090,
+                .enable_mask = BIT(1),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_ufs_phy_phy_aux_clk.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch_simple_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
+        .halt_reg = 0x77058,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x77058,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x77058,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_phy_unipro_core_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                &gcc_ufs_phy_unipro_core_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
+        .halt_reg = 0x77058,
+        .halt_check = BRANCH_HALT,
+        .hwcg_reg = 0x77058,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0x77058,
+                .enable_mask = BIT(1),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_ufs_phy_unipro_core_clk.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch_simple_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb30_prim_master_clk = {
+        .halt_reg = 0xf010,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xf010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb30_prim_master_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_usb30_prim_master_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
+        .halt_reg = 0xf018,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xf018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb30_prim_mock_utmi_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb30_prim_sleep_clk = {
+        .halt_reg = 0xf014,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xf014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb30_prim_sleep_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb30_sec_master_clk = {
+        .halt_reg = 0x10010,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x10010,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb30_sec_master_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_usb30_sec_master_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb30_sec_mock_utmi_clk = {
+        .halt_reg = 0x10018,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x10018,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb30_sec_mock_utmi_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb30_sec_sleep_clk = {
+        .halt_reg = 0x10014,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x10014,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb30_sec_sleep_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb3_prim_clkref_clk = {
+        .halt_reg = 0x8c008,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x8c008,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb3_prim_clkref_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
+        .halt_reg = 0xf050,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xf050,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb3_prim_phy_aux_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
+        .halt_reg = 0xf054,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xf054,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb3_prim_phy_com_aux_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_usb3_prim_phy_aux_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb3_sec_clkref_clk = {
+        .halt_reg = 0x8c028,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x8c028,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb3_sec_clkref_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
+        .halt_reg = 0x10050,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x10050,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb3_sec_phy_aux_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
+        .halt_reg = 0x10054,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0x10054,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_usb3_sec_phy_com_aux_clk",
+                        .parent_hws = (const struct clk_hw *[]){
+                                      &gcc_usb3_sec_phy_aux_clk_src.clkr.hw },
+                        .num_parents = 1,
+                        .flags = CLK_SET_RATE_PARENT,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+/*
+ * Clock ON depends on external parent 'config noc', so cant poll
+ * delay and also mark as crtitical for video boot
+ */
+static struct clk_branch gcc_video_ahb_clk = {
+        .halt_reg = 0xb004,
+        .halt_check = BRANCH_HALT_DELAY,
+        .hwcg_reg = 0xb004,
+        .hwcg_bit = 1,
+        .clkr = {
+                .enable_reg = 0xb004,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_video_ahb_clk",
+                        .flags = CLK_IS_CRITICAL,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_video_axi0_clk = {
+        .halt_reg = 0xb024,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xb024,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_video_axi0_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_video_axi1_clk = {
+        .halt_reg = 0xb028,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xb028,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_video_axi1_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_branch gcc_video_axic_clk = {
+        .halt_reg = 0xb02c,
+        .halt_check = BRANCH_HALT,
+        .clkr = {
+                .enable_reg = 0xb02c,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_video_axic_clk",
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+/* XO critical input to video, so no need to poll */
+static struct clk_branch gcc_video_xo_clk = {
+        .halt_reg = 0xb040,
+        .halt_check = BRANCH_HALT_DELAY,
+        .clkr = {
+                .enable_reg = 0xb040,
+                .enable_mask = BIT(0),
+                .hw.init = &(struct clk_init_data){
+                        .name = "gcc_video_xo_clk",
+                        .flags = CLK_IS_CRITICAL,
+                        .ops = &clk_branch2_ops,
+                },
+        },
+};
+
+static struct clk_regmap *gcc_sm8150_clocks[] = {
+        [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
+        [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
+        [GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK] =
+                &gcc_aggre_ufs_card_axi_hw_ctl_clk.clkr,
+        [GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
+        [GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] =
+                &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
+        [GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
+        [GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
+        [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
+        [GCC_CAMERA_AHB_CLK] = &gcc_camera_ahb_clk.clkr,
+        [GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
+        [GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
+        [GCC_CAMERA_XO_CLK] = &gcc_camera_xo_clk.clkr,
+        [GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
+        [GCC_CFG_NOC_USB3_SEC_AXI_CLK] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr,
+        [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr,
+        [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr,
+        [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
+        [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
+        [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr,
+        [GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
+        [GCC_DISP_AHB_CLK] = &gcc_disp_ahb_clk.clkr,
+        [GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
+        [GCC_DISP_SF_AXI_CLK] = &gcc_disp_sf_axi_clk.clkr,
+        [GCC_DISP_XO_CLK] = &gcc_disp_xo_clk.clkr,
+        [GCC_EMAC_AXI_CLK] = &gcc_emac_axi_clk.clkr,
+        [GCC_EMAC_PTP_CLK] = &gcc_emac_ptp_clk.clkr,
+        [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr,
+        [GCC_EMAC_RGMII_CLK] = &gcc_emac_rgmii_clk.clkr,
+        [GCC_EMAC_RGMII_CLK_SRC] = &gcc_emac_rgmii_clk_src.clkr,
+        [GCC_EMAC_SLV_AHB_CLK] = &gcc_emac_slv_ahb_clk.clkr,
+        [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+        [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
+        [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+        [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
+        [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+        [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
+        [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
+        [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
+        [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
+        [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
+        [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,
+        [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
+        [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
+        [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr,
+        [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
+        [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
+        [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
+        [GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
+        [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
+        [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr,
+        [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
+        [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
+        [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
+        [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
+        [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
+        [GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
+        [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
+        [GCC_PCIE_1_CLKREF_CLK] = &gcc_pcie_1_clkref_clk.clkr,
+        [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
+        [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
+        [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
+        [GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
+        [GCC_PCIE_PHY_AUX_CLK] = &gcc_pcie_phy_aux_clk.clkr,
+        [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr,
+        [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
+        [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
+        [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
+        [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
+        [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+        [GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
+        [GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
+        [GCC_QMIP_DISP_AHB_CLK] = &gcc_qmip_disp_ahb_clk.clkr,
+        [GCC_QMIP_VIDEO_CVP_AHB_CLK] = &gcc_qmip_video_cvp_ahb_clk.clkr,
+        [GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
+        [GCC_QSPI_CNOC_PERIPH_AHB_CLK] = &gcc_qspi_cnoc_periph_ahb_clk.clkr,
+        [GCC_QSPI_CORE_CLK] = &gcc_qspi_core_clk.clkr,
+        [GCC_QSPI_CORE_CLK_SRC] = &gcc_qspi_core_clk_src.clkr,
+        [GCC_QUPV3_WRAP0_S0_CLK] = &gcc_qupv3_wrap0_s0_clk.clkr,
+        [GCC_QUPV3_WRAP0_S0_CLK_SRC] = &gcc_qupv3_wrap0_s0_clk_src.clkr,
+        [GCC_QUPV3_WRAP0_S1_CLK] = &gcc_qupv3_wrap0_s1_clk.clkr,
+        [GCC_QUPV3_WRAP0_S1_CLK_SRC] = &gcc_qupv3_wrap0_s1_clk_src.clkr,
+        [GCC_QUPV3_WRAP0_S2_CLK] = &gcc_qupv3_wrap0_s2_clk.clkr,
+        [GCC_QUPV3_WRAP0_S2_CLK_SRC] = &gcc_qupv3_wrap0_s2_clk_src.clkr,
+        [GCC_QUPV3_WRAP0_S3_CLK] = &gcc_qupv3_wrap0_s3_clk.clkr,
+        [GCC_QUPV3_WRAP0_S3_CLK_SRC] = &gcc_qupv3_wrap0_s3_clk_src.clkr,
+        [GCC_QUPV3_WRAP0_S4_CLK] = &gcc_qupv3_wrap0_s4_clk.clkr,
+        [GCC_QUPV3_WRAP0_S4_CLK_SRC] = &gcc_qupv3_wrap0_s4_clk_src.clkr,
+        [GCC_QUPV3_WRAP0_S5_CLK] = &gcc_qupv3_wrap0_s5_clk.clkr,
+        [GCC_QUPV3_WRAP0_S5_CLK_SRC] = &gcc_qupv3_wrap0_s5_clk_src.clkr,
+        [GCC_QUPV3_WRAP0_S6_CLK] = &gcc_qupv3_wrap0_s6_clk.clkr,
+        [GCC_QUPV3_WRAP0_S6_CLK_SRC] = &gcc_qupv3_wrap0_s6_clk_src.clkr,
+        [GCC_QUPV3_WRAP0_S7_CLK] = &gcc_qupv3_wrap0_s7_clk.clkr,
+        [GCC_QUPV3_WRAP0_S7_CLK_SRC] = &gcc_qupv3_wrap0_s7_clk_src.clkr,
+        [GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
+        [GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
+        [GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
+        [GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
+        [GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
+        [GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
+        [GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
+        [GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
+        [GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
+        [GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
+        [GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
+        [GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
+        [GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
+        [GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
+        [GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
+        [GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
+        [GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
+        [GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
+        [GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
+        [GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
+        [GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
+        [GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
+        [GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
+        [GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
+        [GCC_QUPV3_WRAP_0_M_AHB_CLK] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr,
+        [GCC_QUPV3_WRAP_0_S_AHB_CLK] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr,
+        [GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
+        [GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
+        [GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
+        [GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
+        [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
+        [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
+        [GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
+        [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
+        [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
+        [GCC_SDCC4_APPS_CLK_SRC] = &gcc_sdcc4_apps_clk_src.clkr,
+        [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
+        [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
+        [GCC_TSIF_INACTIVITY_TIMERS_CLK] = &gcc_tsif_inactivity_timers_clk.clkr,
+        [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
+        [GCC_TSIF_REF_CLK_SRC] = &gcc_tsif_ref_clk_src.clkr,
+        [GCC_UFS_CARD_AHB_CLK] = &gcc_ufs_card_ahb_clk.clkr,
+        [GCC_UFS_CARD_AXI_CLK] = &gcc_ufs_card_axi_clk.clkr,
+        [GCC_UFS_CARD_AXI_CLK_SRC] = &gcc_ufs_card_axi_clk_src.clkr,
+        [GCC_UFS_CARD_AXI_HW_CTL_CLK] = &gcc_ufs_card_axi_hw_ctl_clk.clkr,
+        [GCC_UFS_CARD_CLKREF_CLK] = &gcc_ufs_card_clkref_clk.clkr,
+        [GCC_UFS_CARD_ICE_CORE_CLK] = &gcc_ufs_card_ice_core_clk.clkr,
+        [GCC_UFS_CARD_ICE_CORE_CLK_SRC] = &gcc_ufs_card_ice_core_clk_src.clkr,
+        [GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK] =
+                &gcc_ufs_card_ice_core_hw_ctl_clk.clkr,
+        [GCC_UFS_CARD_PHY_AUX_CLK] = &gcc_ufs_card_phy_aux_clk.clkr,
+        [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
+        [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] =
+                &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
+        [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
+        [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
+                &gcc_ufs_card_unipro_core_clk_src.clkr,
+        [GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK] =
+                &gcc_ufs_card_unipro_core_hw_ctl_clk.clkr,
+        [GCC_UFS_MEM_CLKREF_CLK] = &gcc_ufs_mem_clkref_clk.clkr,
+        [GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
+        [GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
+        [GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
+        [GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
+        [GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
+        [GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
+        [GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] =
+                &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
+        [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
+        [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
+        [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
+        [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
+        [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
+                &gcc_ufs_phy_unipro_core_clk_src.clkr,
+        [GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] =
+                &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
+        [GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
+        [GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
+        [GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
+        [GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] =
+                &gcc_usb30_prim_mock_utmi_clk_src.clkr,
+        [GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
+        [GCC_USB30_SEC_MASTER_CLK] = &gcc_usb30_sec_master_clk.clkr,
+        [GCC_USB30_SEC_MASTER_CLK_SRC] = &gcc_usb30_sec_master_clk_src.clkr,
+        [GCC_USB30_SEC_MOCK_UTMI_CLK] = &gcc_usb30_sec_mock_utmi_clk.clkr,
+        [GCC_USB30_SEC_MOCK_UTMI_CLK_SRC] =
+                &gcc_usb30_sec_mock_utmi_clk_src.clkr,
+        [GCC_USB30_SEC_SLEEP_CLK] = &gcc_usb30_sec_sleep_clk.clkr,
+        [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr,
+        [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
+        [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
+        [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
+        [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
+        [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
+        [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
+        [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
+        [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
+        [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
+        [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
+        [GCC_VIDEO_AXIC_CLK] = &gcc_video_axic_clk.clkr,
+        [GCC_VIDEO_XO_CLK] = &gcc_video_xo_clk.clkr,
+        [GPLL0] = &gpll0.clkr,
+        [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr,
+        [GPLL7] = &gpll7.clkr,
+        [GPLL9] = &gpll9.clkr,
+};
+
+static const struct qcom_reset_map gcc_sm8150_resets[] = {
+        [GCC_EMAC_BCR] = { 0x6000 },
+        [GCC_GPU_BCR] = { 0x71000 },
+        [GCC_MMSS_BCR] = { 0xb000 },
+        [GCC_NPU_BCR] = { 0x4d000 },
+        [GCC_PCIE_0_BCR] = { 0x6b000 },
+        [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
+        [GCC_PCIE_1_BCR] = { 0x8d000 },
+        [GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
+        [GCC_PCIE_PHY_BCR] = { 0x6f000 },
+        [GCC_PDM_BCR] = { 0x33000 },
+        [GCC_PRNG_BCR] = { 0x34000 },
+        [GCC_QSPI_BCR] = { 0x24008 },
+        [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
+        [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
+        [GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
+        [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
+        [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
+        [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
+        [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
+        [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
+        [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
+        [GCC_SDCC2_BCR] = { 0x14000 },
+        [GCC_SDCC4_BCR] = { 0x16000 },
+        [GCC_TSIF_BCR] = { 0x36000 },
+        [GCC_UFS_CARD_BCR] = { 0x75000 },
+        [GCC_UFS_PHY_BCR] = { 0x77000 },
+        [GCC_USB30_PRIM_BCR] = { 0xf000 },
+        [GCC_USB30_SEC_BCR] = { 0x10000 },
+        [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
+};
+
+static const struct regmap_config gcc_sm8150_regmap_config = {
+        .reg_bits       = 32,
+        .reg_stride     = 4,
+        .val_bits       = 32,
+        .max_register   = 0x9c040,
+        .fast_io        = true,
+};
+
+static const struct qcom_cc_desc gcc_sm8150_desc = {
+        .config = &gcc_sm8150_regmap_config,
+        .clks = gcc_sm8150_clocks,
+        .num_clks = ARRAY_SIZE(gcc_sm8150_clocks),
+        .resets = gcc_sm8150_resets,
+        .num_resets = ARRAY_SIZE(gcc_sm8150_resets),
+};
+
+static const struct of_device_id gcc_sm8150_match_table[] = {
+        { .compatible = "qcom,gcc-sm8150" },
+        { }
+};
+MODULE_DEVICE_TABLE(of, gcc_sm8150_match_table);
+
+static int gcc_sm8150_probe(struct platform_device *pdev)
+{
+        struct regmap *regmap;
+
+        regmap = qcom_cc_map(pdev, &gcc_sm8150_desc);
+        if (IS_ERR(regmap))
+                return PTR_ERR(regmap);
+
+        /* Disable the GPLL0 active input to NPU and GPU via MISC registers */
+        regmap_update_bits(regmap, 0x4d110, 0x3, 0x3);
+        regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
+
+        return qcom_cc_really_probe(pdev, &gcc_sm8150_desc, regmap);
+}
+
+static struct platform_driver gcc_sm8150_driver = {
+        .probe          = gcc_sm8150_probe,
+        .driver         = {
+                .name   = "gcc-sm8150",
+                .of_match_table = gcc_sm8150_match_table,
+        },
+};
+
+static int __init gcc_sm8150_init(void)
+{
+        return platform_driver_register(&gcc_sm8150_driver);
+}
+subsys_initcall(gcc_sm8150_init);
+
+static void __exit gcc_sm8150_exit(void)
+{
+        platform_driver_unregister(&gcc_sm8150_driver);
+}
+module_exit(gcc_sm8150_exit);
+
+MODULE_DESCRIPTION("QTI GCC SM8150 Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/qcom/lpasscc-sdm845.c b/drivers/clk/qcom/lpasscc-sdm845.c
index e246b99dfbc6..56d3e9928892 100644
--- a/drivers/clk/qcom/lpasscc-sdm845.c
+++ b/drivers/clk/qcom/lpasscc-sdm845.c
@@ -112,25 +112,6 @@ static const struct qcom_cc_desc lpass_qdsp6ss_sdm845_desc = {
         .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sdm845_clocks),
 };
 
-static int lpass_clocks_sdm845_probe(struct platform_device *pdev, int index,
-                                     const struct qcom_cc_desc *desc)
-{
-        struct regmap *regmap;
-        struct resource *res;
-        void __iomem *base;
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, index);
-        base = devm_ioremap_resource(&pdev->dev, res);
-        if (IS_ERR(base))
-                return PTR_ERR(base);
-
-        regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config);
-        if (IS_ERR(regmap))
-                return PTR_ERR(regmap);
-
-        return qcom_cc_really_probe(pdev, desc, regmap);
-}
-
 static int lpass_cc_sdm845_probe(struct platform_device *pdev)
 {
         const struct qcom_cc_desc *desc;
@@ -139,14 +120,14 @@ static int lpass_cc_sdm845_probe(struct platform_device *pdev)
         lpass_regmap_config.name = "cc";
         desc = &lpass_cc_sdm845_desc;
 
-        ret = lpass_clocks_sdm845_probe(pdev, 0, desc);
+        ret = qcom_cc_probe_by_index(pdev, 0, desc);
         if (ret)
                 return ret;
 
         lpass_regmap_config.name = "qdsp6ss";
         desc = &lpass_qdsp6ss_sdm845_desc;
 
-        return lpass_clocks_sdm845_probe(pdev, 1, desc);
+        return qcom_cc_probe_by_index(pdev, 1, desc);
 }
 
 static const struct of_device_id lpass_cc_sdm845_match_table[] = {
diff --git a/drivers/clk/qcom/turingcc-qcs404.c b/drivers/clk/qcom/turingcc-qcs404.c
index aa859e6ec9bd..4cfbbf5bf4d9 100644
--- a/drivers/clk/qcom/turingcc-qcs404.c
+++ b/drivers/clk/qcom/turingcc-qcs404.c
@@ -96,7 +96,7 @@ static const struct regmap_config turingcc_regmap_config = {
         .reg_bits       = 32,
         .reg_stride     = 4,
         .val_bits       = 32,
-        .max_register   = 0x30000,
+        .max_register   = 0x23004,
         .fast_io        = true,
 };
 
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index d18e49b4976f..4413b6e04a8e 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -326,6 +326,7 @@ static void __init st_of_flexgen_setup(struct device_node *np)
                 return;
 
         reg = of_iomap(pnode, 0);
+        of_node_put(pnode);
         if (!reg)
                 return;
 
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index ca1ccdb8a3b1..a156bd0c6af7 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -67,7 +67,6 @@ struct clkgen_quadfs_data {
 };
 
 static const struct clk_ops st_quadfs_pll_c32_ops;
-static const struct clk_ops st_quadfs_fs660c32_ops;
 
 static int clk_fs660c32_dig_get_params(unsigned long input,
                 unsigned long output, struct stm_fs *fs);
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index d8a688bd45ec..c3952f2c42ba 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -61,19 +61,6 @@ static const struct clk_ops stm_pll3200c32_ops;
 static const struct clk_ops stm_pll3200c32_a9_ops;
 static const struct clk_ops stm_pll4600c28_ops;
 
-static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
-        /* 407 A0 */
-        .pdn_status     = CLKGEN_FIELD(0x2a0,   0x1,                    8),
-        .pdn_ctrl       = CLKGEN_FIELD(0x2a0,   0x1,                    8),
-        .locked_status  = CLKGEN_FIELD(0x2a0,   0x1,                    24),
-        .ndiv           = CLKGEN_FIELD(0x2a4,   C32_NDIV_MASK,          16),
-        .idf            = CLKGEN_FIELD(0x2a4,   C32_IDF_MASK,           0x0),
-        .num_odfs = 1,
-        .odf            = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK,           0) },
-        .odf_gate       = { CLKGEN_FIELD(0x2b4, 0x1,                    6) },
-        .ops            = &stm_pll3200c32_ops,
-};
-
 static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
         /* 407 C0 PLL0 */
         .pdn_status     = CLKGEN_FIELD(0x2a0,   0x1,                    8),
diff --git a/drivers/clk/ti/clk-814x.c b/drivers/clk/ti/clk-814x.c
index e8cee6f3b4a0..087cfa75ac24 100644
--- a/drivers/clk/ti/clk-814x.c
+++ b/drivers/clk/ti/clk-814x.c
@@ -66,6 +66,7 @@ static int __init dm814x_adpll_early_init(void)
         }
 
         of_platform_populate(np, NULL, NULL, NULL);
+        of_node_put(np);
 
         return 0;
 }
diff --git a/drivers/clk/versatile/clk-versatile.c b/drivers/clk/versatile/clk-versatile.c
index 90bb0b041b7a..fd54d5c0251c 100644
--- a/drivers/clk/versatile/clk-versatile.c
+++ b/drivers/clk/versatile/clk-versatile.c
@@ -70,6 +70,7 @@ static void __init cm_osc_setup(struct device_node *np,
                         return;
                 }
                 cm_base = of_iomap(parent, 0);
+                of_node_put(parent);
                 if (!cm_base) {
                         pr_err("could not remap core module base\n");
                         return;
diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
new file mode 100644
index 000000000000..38074a5f7296
--- /dev/null
+++ b/include/dt-bindings/clock/ast2600-clock.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */
+#ifndef DT_BINDINGS_AST2600_CLOCK_H
+#define DT_BINDINGS_AST2600_CLOCK_H
+
+#define ASPEED_CLK_GATE_ECLK            0
+#define ASPEED_CLK_GATE_GCLK            1
+
+#define ASPEED_CLK_GATE_MCLK            2
+
+#define ASPEED_CLK_GATE_VCLK            3
+#define ASPEED_CLK_GATE_BCLK            4
+#define ASPEED_CLK_GATE_DCLK            5
+
+#define ASPEED_CLK_GATE_LCLK            6
+#define ASPEED_CLK_GATE_LHCCLK          7
+
+#define ASPEED_CLK_GATE_D1CLK           8
+#define ASPEED_CLK_GATE_YCLK            9
+
+#define ASPEED_CLK_GATE_REF0CLK         10
+#define ASPEED_CLK_GATE_REF1CLK         11
+
+#define ASPEED_CLK_GATE_ESPICLK         12
+
+#define ASPEED_CLK_GATE_USBUHCICLK      13
+#define ASPEED_CLK_GATE_USBPORT1CLK     14
+#define ASPEED_CLK_GATE_USBPORT2CLK     15
+
+#define ASPEED_CLK_GATE_RSACLK          16
+#define ASPEED_CLK_GATE_RVASCLK         17
+
+#define ASPEED_CLK_GATE_MAC1CLK         18
+#define ASPEED_CLK_GATE_MAC2CLK         19
+#define ASPEED_CLK_GATE_MAC3CLK         20
+#define ASPEED_CLK_GATE_MAC4CLK         21
+
+#define ASPEED_CLK_GATE_UART1CLK        22
+#define ASPEED_CLK_GATE_UART2CLK        23
+#define ASPEED_CLK_GATE_UART3CLK        24
+#define ASPEED_CLK_GATE_UART4CLK        25
+#define ASPEED_CLK_GATE_UART5CLK        26
+#define ASPEED_CLK_GATE_UART6CLK        27
+#define ASPEED_CLK_GATE_UART7CLK        28
+#define ASPEED_CLK_GATE_UART8CLK        29
+#define ASPEED_CLK_GATE_UART9CLK        30
+#define ASPEED_CLK_GATE_UART10CLK       31
+#define ASPEED_CLK_GATE_UART11CLK       32
+#define ASPEED_CLK_GATE_UART12CLK       33
+#define ASPEED_CLK_GATE_UART13CLK       34
+
+#define ASPEED_CLK_GATE_SDCLK           35
+#define ASPEED_CLK_GATE_EMMCCLK         36
+
+#define ASPEED_CLK_GATE_I3C0CLK         37
+#define ASPEED_CLK_GATE_I3C1CLK         38
+#define ASPEED_CLK_GATE_I3C2CLK         39
+#define ASPEED_CLK_GATE_I3C3CLK         40
+#define ASPEED_CLK_GATE_I3C4CLK         41
+#define ASPEED_CLK_GATE_I3C5CLK         42
+#define ASPEED_CLK_GATE_I3C6CLK         43
+#define ASPEED_CLK_GATE_I3C7CLK         44
+
+#define ASPEED_CLK_GATE_FSICLK          45
+
+#define ASPEED_CLK_HPLL                 46
+#define ASPEED_CLK_MPLL                 47
+#define ASPEED_CLK_DPLL                 48
+#define ASPEED_CLK_EPLL                 49
+#define ASPEED_CLK_APLL                 50
+#define ASPEED_CLK_AHB                  51
+#define ASPEED_CLK_APB1                 52
+#define ASPEED_CLK_APB2                 53
+#define ASPEED_CLK_BCLK                 54
+#define ASPEED_CLK_D1CLK                55
+#define ASPEED_CLK_VCLK                 56
+#define ASPEED_CLK_LHCLK                57
+#define ASPEED_CLK_UART                 58
+#define ASPEED_CLK_UARTX                59
+#define ASPEED_CLK_SDIO                 60
+#define ASPEED_CLK_EMMC                 61
+#define ASPEED_CLK_ECLK                 62
+#define ASPEED_CLK_ECLK_MUX             63
+#define ASPEED_CLK_MAC12                64
+#define ASPEED_CLK_MAC34                65
+#define ASPEED_CLK_USBPHY_40M           66
+
+/* Only list resets here that are not part of a gate */
+#define ASPEED_RESET_ADC                55
+#define ASPEED_RESET_JTAG_MASTER2       54
+#define ASPEED_RESET_I3C_DMA            39
+#define ASPEED_RESET_PWM                37
+#define ASPEED_RESET_PECI               36
+#define ASPEED_RESET_MII                35
+#define ASPEED_RESET_I2C                34
+#define ASPEED_RESET_H2X                31
+#define ASPEED_RESET_GP_MCU             30
+#define ASPEED_RESET_DP_MCU             29
+#define ASPEED_RESET_DP                 28
+#define ASPEED_RESET_RC_XDMA            27
+#define ASPEED_RESET_GRAPHICS           26
+#define ASPEED_RESET_DEV_XDMA           25
+#define ASPEED_RESET_DEV_MCTP           24
+#define ASPEED_RESET_RC_MCTP            23
+#define ASPEED_RESET_JTAG_MASTER        22
+#define ASPEED_RESET_PCIE_DEV_O         21
+#define ASPEED_RESET_PCIE_DEV_OEN       20
+#define ASPEED_RESET_PCIE_RC_O          19
+#define ASPEED_RESET_PCIE_RC_OEN        18
+#define ASPEED_RESET_PCI_DP             5
+#define ASPEED_RESET_AHB                1
+#define ASPEED_RESET_SDRAM              0
+
+#endif
diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h
index b6b127e45634..0837c1a7ae49 100644
--- a/include/dt-bindings/clock/g12a-clkc.h
+++ b/include/dt-bindings/clock/g12a-clkc.h
@@ -137,5 +137,11 @@
 #define CLKID_VDEC_HEVC                         207
 #define CLKID_VDEC_HEVCF                        210
 #define CLKID_TS                                212
+#define CLKID_CPUB_CLK                          224
+#define CLKID_GP1_PLL                           243
+#define CLKID_DSU_CLK                           252
+#define CLKID_CPU1_CLK                          253
+#define CLKID_CPU2_CLK                          254
+#define CLKID_CPU3_CLK                          255
 
 #endif /* __G12A_CLKC_H */
diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
index 2cd62c98561f..bc3051543347 100644
--- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
+++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
@@ -146,6 +146,8 @@
 #define GCC_MDP_TBU_CLK                                 138
 #define GCC_QDSS_DAP_CLK                                139
 #define GCC_DCC_XO_CLK                                  140
+#define GCC_WCSS_Q6_AHB_CLK                             141
+#define GCC_WCSS_Q6_AXIM_CLK                            142
 #define GCC_CDSP_CFG_AHB_CLK                            143
 #define GCC_BIMC_CDSP_CLK                               144
 #define GCC_CDSP_TBU_CLK                                145
@@ -173,5 +175,6 @@
 #define GCC_PCIE_0_CORE_STICKY_ARES                     19
 #define GCC_PCIE_0_SLEEP_ARES                           20
 #define GCC_PCIE_0_PIPE_ARES                            21
+#define GCC_WDSP_RESTART                                22
 
 #endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h
new file mode 100644
index 000000000000..90d60ef94c64
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h
@@ -0,0 +1,243 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8150_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_SM8150_H
+
+/* GCC clocks */
+#define GCC_AGGRE_NOC_PCIE_TBU_CLK                              0
+#define GCC_AGGRE_UFS_CARD_AXI_CLK                              1
+#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK                       2
+#define GCC_AGGRE_UFS_PHY_AXI_CLK                               3
+#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK                        4
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK                             5
+#define GCC_AGGRE_USB3_SEC_AXI_CLK                              6
+#define GCC_BOOT_ROM_AHB_CLK                                    7
+#define GCC_CAMERA_AHB_CLK                                      8
+#define GCC_CAMERA_HF_AXI_CLK                                   9
+#define GCC_CAMERA_SF_AXI_CLK                                   10
+#define GCC_CAMERA_XO_CLK                                       11
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK                           12
+#define GCC_CFG_NOC_USB3_SEC_AXI_CLK                            13
+#define GCC_CPUSS_AHB_CLK                                       14
+#define GCC_CPUSS_AHB_CLK_SRC                                   15
+#define GCC_CPUSS_DVM_BUS_CLK                                   16
+#define GCC_CPUSS_GNOC_CLK                                      17
+#define GCC_CPUSS_RBCPR_CLK                                     18
+#define GCC_DDRSS_GPU_AXI_CLK                                   19
+#define GCC_DISP_AHB_CLK                                        20
+#define GCC_DISP_HF_AXI_CLK                                     21
+#define GCC_DISP_SF_AXI_CLK                                     22
+#define GCC_DISP_XO_CLK                                         23
+#define GCC_EMAC_AXI_CLK                                        24
+#define GCC_EMAC_PTP_CLK                                        25
+#define GCC_EMAC_PTP_CLK_SRC                                    26
+#define GCC_EMAC_RGMII_CLK                                      27
+#define GCC_EMAC_RGMII_CLK_SRC                                  28
+#define GCC_EMAC_SLV_AHB_CLK                                    29
+#define GCC_GP1_CLK                                             30
+#define GCC_GP1_CLK_SRC                                         31
+#define GCC_GP2_CLK                                             32
+#define GCC_GP2_CLK_SRC                                         33
+#define GCC_GP3_CLK                                             34
+#define GCC_GP3_CLK_SRC                                         35
+#define GCC_GPU_CFG_AHB_CLK                                     36
+#define GCC_GPU_GPLL0_CLK_SRC                                   37
+#define GCC_GPU_GPLL0_DIV_CLK_SRC                               38
+#define GCC_GPU_IREF_CLK                                        39
+#define GCC_GPU_MEMNOC_GFX_CLK                                  40
+#define GCC_GPU_SNOC_DVM_GFX_CLK                                41
+#define GCC_NPU_AT_CLK                                          42
+#define GCC_NPU_AXI_CLK                                         43
+#define GCC_NPU_CFG_AHB_CLK                                     44
+#define GCC_NPU_GPLL0_CLK_SRC                                   45
+#define GCC_NPU_GPLL0_DIV_CLK_SRC                               46
+#define GCC_NPU_TRIG_CLK                                        47
+#define GCC_PCIE0_PHY_REFGEN_CLK                                48
+#define GCC_PCIE1_PHY_REFGEN_CLK                                49
+#define GCC_PCIE_0_AUX_CLK                                      50
+#define GCC_PCIE_0_AUX_CLK_SRC                                  51
+#define GCC_PCIE_0_CFG_AHB_CLK                                  52
+#define GCC_PCIE_0_CLKREF_CLK                                   53
+#define GCC_PCIE_0_MSTR_AXI_CLK                                 54
+#define GCC_PCIE_0_PIPE_CLK                                     55
+#define GCC_PCIE_0_SLV_AXI_CLK                                  56
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK                              57
+#define GCC_PCIE_1_AUX_CLK                                      58
+#define GCC_PCIE_1_AUX_CLK_SRC                                  59
+#define GCC_PCIE_1_CFG_AHB_CLK                                  60
+#define GCC_PCIE_1_CLKREF_CLK                                   61
+#define GCC_PCIE_1_MSTR_AXI_CLK                                 62
+#define GCC_PCIE_1_PIPE_CLK                                     63
+#define GCC_PCIE_1_SLV_AXI_CLK                                  64
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK                              65
+#define GCC_PCIE_PHY_AUX_CLK                                    66
+#define GCC_PCIE_PHY_REFGEN_CLK_SRC                             67
+#define GCC_PDM2_CLK                                            68
+#define GCC_PDM2_CLK_SRC                                        69
+#define GCC_PDM_AHB_CLK                                         70
+#define GCC_PDM_XO4_CLK                                         71
+#define GCC_PRNG_AHB_CLK                                        72
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK                             73
+#define GCC_QMIP_CAMERA_RT_AHB_CLK                              74
+#define GCC_QMIP_DISP_AHB_CLK                                   75
+#define GCC_QMIP_VIDEO_CVP_AHB_CLK                              76
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK                           77
+#define GCC_QSPI_CNOC_PERIPH_AHB_CLK                            78
+#define GCC_QSPI_CORE_CLK                                       79
+#define GCC_QSPI_CORE_CLK_SRC                                   80
+#define GCC_QUPV3_WRAP0_S0_CLK                                  81
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC                              82
+#define GCC_QUPV3_WRAP0_S1_CLK                                  83
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC                              84
+#define GCC_QUPV3_WRAP0_S2_CLK                                  85
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC                              86
+#define GCC_QUPV3_WRAP0_S3_CLK                                  87
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC                              88
+#define GCC_QUPV3_WRAP0_S4_CLK                                  89
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC                              90
+#define GCC_QUPV3_WRAP0_S5_CLK                                  91
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC                              92
+#define GCC_QUPV3_WRAP0_S6_CLK                                  93
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC                              94
+#define GCC_QUPV3_WRAP0_S7_CLK                                  95
+#define GCC_QUPV3_WRAP0_S7_CLK_SRC                              96
+#define GCC_QUPV3_WRAP1_S0_CLK                                  97
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC                              98
+#define GCC_QUPV3_WRAP1_S1_CLK                                  99
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC                              100
+#define GCC_QUPV3_WRAP1_S2_CLK                                  101
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC                              102
+#define GCC_QUPV3_WRAP1_S3_CLK                                  103
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC                              104
+#define GCC_QUPV3_WRAP1_S4_CLK                                  105
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC                              106
+#define GCC_QUPV3_WRAP1_S5_CLK                                  107
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC                              108
+#define GCC_QUPV3_WRAP2_S0_CLK                                  109
+#define GCC_QUPV3_WRAP2_S0_CLK_SRC                              110
+#define GCC_QUPV3_WRAP2_S1_CLK                                  111
+#define GCC_QUPV3_WRAP2_S1_CLK_SRC                              112
+#define GCC_QUPV3_WRAP2_S2_CLK                                  113
+#define GCC_QUPV3_WRAP2_S2_CLK_SRC                              114
+#define GCC_QUPV3_WRAP2_S3_CLK                                  115
+#define GCC_QUPV3_WRAP2_S3_CLK_SRC                              116
+#define GCC_QUPV3_WRAP2_S4_CLK                                  117
+#define GCC_QUPV3_WRAP2_S4_CLK_SRC                              118
+#define GCC_QUPV3_WRAP2_S5_CLK                                  119
+#define GCC_QUPV3_WRAP2_S5_CLK_SRC                              120
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK                              121
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK                              122
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK                              123
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK                              124
+#define GCC_QUPV3_WRAP_2_M_AHB_CLK                              125
+#define GCC_QUPV3_WRAP_2_S_AHB_CLK                              126
+#define GCC_SDCC2_AHB_CLK                                       127
+#define GCC_SDCC2_APPS_CLK                                      128
+#define GCC_SDCC2_APPS_CLK_SRC                                  129
+#define GCC_SDCC4_AHB_CLK                                       130
+#define GCC_SDCC4_APPS_CLK                                      131
+#define GCC_SDCC4_APPS_CLK_SRC                                  132
+#define GCC_SYS_NOC_CPUSS_AHB_CLK                               133
+#define GCC_TSIF_AHB_CLK                                        134
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK                          135
+#define GCC_TSIF_REF_CLK                                        136
+#define GCC_TSIF_REF_CLK_SRC                                    137
+#define GCC_UFS_CARD_AHB_CLK                                    138
+#define GCC_UFS_CARD_AXI_CLK                                    139
+#define GCC_UFS_CARD_AXI_CLK_SRC                                140
+#define GCC_UFS_CARD_AXI_HW_CTL_CLK                             141
+#define GCC_UFS_CARD_CLKREF_CLK                                 142
+#define GCC_UFS_CARD_ICE_CORE_CLK                               143
+#define GCC_UFS_CARD_ICE_CORE_CLK_SRC                           144
+#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK                        145
+#define GCC_UFS_CARD_PHY_AUX_CLK                                146
+#define GCC_UFS_CARD_PHY_AUX_CLK_SRC                            147
+#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK                         148
+#define GCC_UFS_CARD_RX_SYMBOL_0_CLK                            149
+#define GCC_UFS_CARD_RX_SYMBOL_1_CLK                            150
+#define GCC_UFS_CARD_TX_SYMBOL_0_CLK                            151
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK                            152
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC                        153
+#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK                     154
+#define GCC_UFS_MEM_CLKREF_CLK                                  155
+#define GCC_UFS_PHY_AHB_CLK                                     156
+#define GCC_UFS_PHY_AXI_CLK                                     157
+#define GCC_UFS_PHY_AXI_CLK_SRC                                 158
+#define GCC_UFS_PHY_AXI_HW_CTL_CLK                              159
+#define GCC_UFS_PHY_ICE_CORE_CLK                                160
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC                            161
+#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK                         162
+#define GCC_UFS_PHY_PHY_AUX_CLK                                 163
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC                             164
+#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK                          165
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK                             166
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK                             167
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK                             168
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK                             169
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC                         170
+#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK                      171
+#define GCC_USB30_PRIM_MASTER_CLK                               172
+#define GCC_USB30_PRIM_MASTER_CLK_SRC                           173
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK                            174
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC                        175
+#define GCC_USB30_PRIM_SLEEP_CLK                                176
+#define GCC_USB30_SEC_MASTER_CLK                                177
+#define GCC_USB30_SEC_MASTER_CLK_SRC                            178
+#define GCC_USB30_SEC_MOCK_UTMI_CLK                             179
+#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC                         180
+#define GCC_USB30_SEC_SLEEP_CLK                                 181
+#define GCC_USB3_PRIM_CLKREF_CLK                                182
+#define GCC_USB3_PRIM_PHY_AUX_CLK                               183
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC                           184
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK                           185
+#define GCC_USB3_PRIM_PHY_PIPE_CLK                              186
+#define GCC_USB3_SEC_CLKREF_CLK                                 187
+#define GCC_USB3_SEC_PHY_AUX_CLK                                188
+#define GCC_USB3_SEC_PHY_AUX_CLK_SRC                            189
+#define GCC_USB3_SEC_PHY_COM_AUX_CLK                            190
+#define GCC_USB3_SEC_PHY_PIPE_CLK                               191
+#define GCC_VIDEO_AHB_CLK                                       192
+#define GCC_VIDEO_AXI0_CLK                                      193
+#define GCC_VIDEO_AXI1_CLK                                      194
+#define GCC_VIDEO_AXIC_CLK                                      195
+#define GCC_VIDEO_XO_CLK                                        196
+#define GPLL0                                                   197
+#define GPLL0_OUT_EVEN                                          198
+#define GPLL7                                                   199
+#define GPLL9                                                   200
+
+/* Reset clocks */
+#define GCC_EMAC_BCR                                            0
+#define GCC_GPU_BCR                                             1
+#define GCC_MMSS_BCR                                            2
+#define GCC_NPU_BCR                                             3
+#define GCC_PCIE_0_BCR                                          4
+#define GCC_PCIE_0_PHY_BCR                                      5
+#define GCC_PCIE_1_BCR                                          6
+#define GCC_PCIE_1_PHY_BCR                                      7
+#define GCC_PCIE_PHY_BCR                                        8
+#define GCC_PDM_BCR                                             9
+#define GCC_PRNG_BCR                                            10
+#define GCC_QSPI_BCR                                            11
+#define GCC_QUPV3_WRAPPER_0_BCR                                 12
+#define GCC_QUPV3_WRAPPER_1_BCR                                 13
+#define GCC_QUPV3_WRAPPER_2_BCR                                 14
+#define GCC_QUSB2PHY_PRIM_BCR                                   15
+#define GCC_QUSB2PHY_SEC_BCR                                    16
+#define GCC_USB3_PHY_PRIM_BCR                                   17
+#define GCC_USB3_DP_PHY_PRIM_BCR                                18
+#define GCC_USB3_PHY_SEC_BCR                                    19
+#define GCC_USB3PHY_PHY_SEC_BCR                                 20
+#define GCC_SDCC2_BCR                                           21
+#define GCC_SDCC4_BCR                                           22
+#define GCC_TSIF_BCR                                            23
+#define GCC_UFS_CARD_BCR                                        24
+#define GCC_UFS_PHY_BCR                                         25
+#define GCC_USB30_PRIM_BCR                                      26
+#define GCC_USB30_SEC_BCR                                       27
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR                             28
+
+#endif
diff --git a/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h b/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
new file mode 100644
index 000000000000..14b78dabed0e
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-g12a-audio-reset.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Jerome Brunet <jbrunet@baylibre.com>
+ *
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON_G12A_AUDIO_RESET_H
+
+#define AUD_RESET_PDM           0
+#define AUD_RESET_TDMIN_A       1
+#define AUD_RESET_TDMIN_B       2
+#define AUD_RESET_TDMIN_C       3
+#define AUD_RESET_TDMIN_LB      4
+#define AUD_RESET_LOOPBACK      5
+#define AUD_RESET_TODDR_A       6
+#define AUD_RESET_TODDR_B       7
+#define AUD_RESET_TODDR_C       8
+#define AUD_RESET_FRDDR_A       9
+#define AUD_RESET_FRDDR_B       10
+#define AUD_RESET_FRDDR_C       11
+#define AUD_RESET_TDMOUT_A      12
+#define AUD_RESET_TDMOUT_B      13
+#define AUD_RESET_TDMOUT_C      14
+#define AUD_RESET_SPDIFOUT      15
+#define AUD_RESET_SPDIFOUT_B    16
+#define AUD_RESET_SPDIFIN       17
+#define AUD_RESET_EQDRC         18
+#define AUD_RESET_RESAMPLE      19
+#define AUD_RESET_DDRARB        20
+#define AUD_RESET_POWDET        21
+#define AUD_RESET_TORAM         22
+#define AUD_RESET_TOACODEC      23
+#define AUD_RESET_TOHDMITX      24
+#define AUD_RESET_CLKTREE       25
+
+#endif
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 2ae7604783dd..dce5521a9bf6 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -817,6 +817,7 @@ unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
                                           unsigned int index);
+int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
 unsigned int __clk_get_enable_count(struct clk *clk);
 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
 unsigned long __clk_get_flags(struct clk *clk);
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 3c096c7a51dc..7a795fd6d141 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -239,7 +239,8 @@ static inline int clk_prepare(struct clk *clk)
         return 0;
 }
 
-static inline int __must_check clk_bulk_prepare(int num_clks, struct clk_bulk_data *clks)
+static inline int __must_check
+clk_bulk_prepare(int num_clks, const struct clk_bulk_data *clks)
 {
         might_sleep();
         return 0;
@@ -263,7 +264,8 @@ static inline void clk_unprepare(struct clk *clk)
 {
         might_sleep();
 }
-static inline void clk_bulk_unprepare(int num_clks, struct clk_bulk_data *clks)
+static inline void clk_bulk_unprepare(int num_clks,
+                                      const struct clk_bulk_data *clks)
 {
         might_sleep();
 }
@@ -819,7 +821,8 @@ static inline int clk_enable(struct clk *clk)
         return 0;
 }
 
-static inline int __must_check clk_bulk_enable(int num_clks, struct clk_bulk_data *clks)
+static inline int __must_check clk_bulk_enable(int num_clks,
+                                               const struct clk_bulk_data *clks)
 {
         return 0;
 }
@@ -828,7 +831,7 @@ static inline void clk_disable(struct clk *clk) {}
 
 
 static inline void clk_bulk_disable(int num_clks,
-                                    struct clk_bulk_data *clks) {}
+                                    const struct clk_bulk_data *clks) {}
 
 static inline unsigned long clk_get_rate(struct clk *clk)
 {
@@ -917,8 +920,8 @@ static inline void clk_disable_unprepare(struct clk *clk)
         clk_unprepare(clk);
 }
 
-static inline int __must_check clk_bulk_prepare_enable(int num_clks,
-                                        struct clk_bulk_data *clks)
+static inline int __must_check
+clk_bulk_prepare_enable(int num_clks, const struct clk_bulk_data *clks)
 {
         int ret;
 
@@ -933,7 +936,7 @@ static inline int __must_check clk_bulk_prepare_enable(int num_clks,
 }
 
 static inline void clk_bulk_disable_unprepare(int num_clks,
-                                              struct clk_bulk_data *clks)
+                                              const struct clk_bulk_data *clks)
 {
         clk_bulk_disable(num_clks, clks);
         clk_bulk_unprepare(num_clks, clks);