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-rw-r--r--arch/arm/mm/proc-v7-2level.S6
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index 10405b8d31af..6f2f8f3cb33c 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -36,14 +36,16 @@
36 * 36 *
37 * It is assumed that: 37 * It is assumed that:
38 * - we are not using split page tables 38 * - we are not using split page tables
39 *
40 * Note that we always need to flush BTAC/BTB if IBE is set
41 * even on Cortex-A8 revisions not affected by 430973.
42 * If IBE is not set, the flush BTAC/BTB won't do anything.
39 */ 43 */
40ENTRY(cpu_ca8_switch_mm) 44ENTRY(cpu_ca8_switch_mm)
41#ifdef CONFIG_MMU 45#ifdef CONFIG_MMU
42 mov r2, #0 46 mov r2, #0
43#ifdef CONFIG_ARM_ERRATA_430973
44 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 47 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
45#endif 48#endif
46#endif
47ENTRY(cpu_v7_switch_mm) 49ENTRY(cpu_v7_switch_mm)
48#ifdef CONFIG_MMU 50#ifdef CONFIG_MMU
49 mmid r1, r1 @ get mm->context.id 51 mmid r1, r1 @ get mm->context.id