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-rw-r--r--Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt6
-rw-r--r--Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt3
-rw-r--r--Documentation/devicetree/bindings/clock/idt,versaclock5.txt16
-rw-r--r--Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt (renamed from Documentation/devicetree/bindings/clock/rockchip,rk1108-cru.txt)12
-rw-r--r--Documentation/devicetree/bindings/clock/sunxi-ccu.txt18
-rw-r--r--MAINTAINERS10
-rw-r--r--arch/arm/boot/dts/rk1108.dtsi2
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_dpllcore.c3
-rw-r--r--arch/arm/mach-omap2/clock.c35
-rw-r--r--arch/arm/mach-omap2/clock.h2
-rw-r--r--arch/arm/mach-omap2/cm.h5
-rw-r--r--arch/arm/mach-omap2/cm2xxx.c9
-rw-r--r--arch/arm/mach-omap2/cm3xxx.c10
-rw-r--r--arch/arm/mach-omap2/cm_common.c2
-rw-r--r--drivers/clk/bcm/clk-iproc-pll.c2
-rw-r--r--drivers/clk/clk-cs2000-cp.c33
-rw-r--r--drivers/clk/clk-stm32f4.c56
-rw-r--r--drivers/clk/clk-versaclock5.c76
-rw-r--r--drivers/clk/clk.c37
-rw-r--r--drivers/clk/hisilicon/clk-hi6220.c1
-rw-r--r--drivers/clk/imx/clk-imx6ul.c11
-rw-r--r--drivers/clk/imx/clk-imx7d.c8
-rw-r--r--drivers/clk/meson/Makefile2
-rw-r--r--drivers/clk/meson/clk-audio-divider.c144
-rw-r--r--drivers/clk/meson/clk-mpll.c154
-rw-r--r--drivers/clk/meson/clk-pll.c53
-rw-r--r--drivers/clk/meson/clkc.h39
-rw-r--r--drivers/clk/meson/gxbb.c649
-rw-r--r--drivers/clk/meson/gxbb.h30
-rw-r--r--drivers/clk/meson/meson8b.c127
-rw-r--r--drivers/clk/meson/meson8b.h20
-rw-r--r--drivers/clk/qcom/mmcc-msm8996.c2
-rw-r--r--drivers/clk/renesas/r8a7795-cpg-mssr.c221
-rw-r--r--drivers/clk/renesas/r8a7796-cpg-mssr.c18
-rw-r--r--drivers/clk/renesas/rcar-gen3-cpg.c64
-rw-r--r--drivers/clk/renesas/rcar-gen3-cpg.h2
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.c50
-rw-r--r--drivers/clk/renesas/renesas-cpg-mssr.h22
-rw-r--r--drivers/clk/rockchip/Makefile2
-rw-r--r--drivers/clk/rockchip/clk-pll.c3
-rw-r--r--drivers/clk/rockchip/clk-rk3036.c9
-rw-r--r--drivers/clk/rockchip/clk-rk3328.c9
-rw-r--r--drivers/clk/rockchip/clk-rk3368.c27
-rw-r--r--drivers/clk/rockchip/clk-rk3399.c8
-rw-r--r--drivers/clk/rockchip/clk-rv1108.c (renamed from drivers/clk/rockchip/clk-rk1108.c)414
-rw-r--r--drivers/clk/rockchip/clk.h28
-rw-r--r--drivers/clk/sunxi-ng/Kconfig19
-rw-r--r--drivers/clk/sunxi-ng/Makefile1
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun50i-a64.c2
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun5i.c2
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun6i-a31.c2
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-a33.c29
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-h3.c327
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-h3.h3
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-r.c213
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun8i-r.h27
-rw-r--r--drivers/clk/sunxi-ng/ccu-sun9i-a80.c70
-rw-r--r--drivers/clk/sunxi-ng/ccu_common.c53
-rw-r--r--drivers/clk/sunxi-ng/ccu_common.h12
-rw-r--r--drivers/clk/sunxi-ng/ccu_gate.c47
-rw-r--r--drivers/clk/sunxi-ng/ccu_mp.c8
-rw-r--r--drivers/clk/sunxi-ng/ccu_mult.c2
-rw-r--r--drivers/clk/sunxi-ng/ccu_mult.h2
-rw-r--r--drivers/clk/sunxi-ng/ccu_nkmp.c2
-rw-r--r--drivers/clk/tegra/clk-id.h17
-rw-r--r--drivers/clk/tegra/clk-periph-gate.c3
-rw-r--r--drivers/clk/tegra/clk-periph.c6
-rw-r--r--drivers/clk/tegra/clk-pll.c174
-rw-r--r--drivers/clk/tegra/clk-super.c87
-rw-r--r--drivers/clk/tegra/clk-tegra-audio.c85
-rw-r--r--drivers/clk/tegra/clk-tegra-periph.c41
-rw-r--r--drivers/clk/tegra/clk-tegra-pmc.c6
-rw-r--r--drivers/clk/tegra/clk-tegra114.c1
-rw-r--r--drivers/clk/tegra/clk-tegra124.c1
-rw-r--r--drivers/clk/tegra/clk-tegra210.c499
-rw-r--r--drivers/clk/tegra/clk-tegra30.c1
-rw-r--r--drivers/clk/tegra/clk.c16
-rw-r--r--drivers/clk/tegra/clk.h15
-rw-r--r--drivers/clk/ti/apll.c50
-rw-r--r--drivers/clk/ti/autoidle.c18
-rw-r--r--drivers/clk/ti/clk-3xxx.c55
-rw-r--r--drivers/clk/ti/clk-44xx.c188
-rw-r--r--drivers/clk/ti/clk-dra7-atl.c11
-rw-r--r--drivers/clk/ti/clk.c157
-rw-r--r--drivers/clk/ti/clkt_dflt.c61
-rw-r--r--drivers/clk/ti/clkt_dpll.c6
-rw-r--r--drivers/clk/ti/clkt_iclk.c29
-rw-r--r--drivers/clk/ti/clock.h41
-rw-r--r--drivers/clk/ti/clockdomain.c38
-rw-r--r--drivers/clk/ti/composite.c18
-rw-r--r--drivers/clk/ti/divider.c111
-rw-r--r--drivers/clk/ti/dpll.c59
-rw-r--r--drivers/clk/ti/dpll3xxx.c38
-rw-r--r--drivers/clk/ti/dpll44xx.c14
-rw-r--r--drivers/clk/ti/fixed-factor.c1
-rw-r--r--drivers/clk/ti/gate.c44
-rw-r--r--drivers/clk/ti/interface.c25
-rw-r--r--drivers/clk/ti/mux.c59
-rw-r--r--drivers/clk/zte/clk-zx296718.c32
-rw-r--r--drivers/clk/zte/clk.c12
-rw-r--r--drivers/clk/zte/clk.h6
-rw-r--r--include/dt-bindings/clock/gxbb-clkc.h11
-rw-r--r--include/dt-bindings/clock/hi6220-clock.h5
-rw-r--r--include/dt-bindings/clock/r8a7795-cpg-mssr.h7
-rw-r--r--include/dt-bindings/clock/rk3328-cru.h1
-rw-r--r--include/dt-bindings/clock/rk3368-cru.h19
-rw-r--r--include/dt-bindings/clock/rv1108-cru.h (renamed from include/dt-bindings/clock/rk1108-cru.h)6
-rw-r--r--include/dt-bindings/clock/sun8i-h3-ccu.h5
-rw-r--r--include/dt-bindings/clock/sun8i-r-ccu.h59
-rw-r--r--include/dt-bindings/clock/tegra114-car.h2
-rw-r--r--include/dt-bindings/clock/tegra124-car-common.h2
-rw-r--r--include/dt-bindings/clock/tegra210-car.h33
-rw-r--r--include/dt-bindings/clock/tegra30-car.h2
-rw-r--r--include/dt-bindings/reset/sun8i-h3-ccu.h5
-rw-r--r--include/dt-bindings/reset/sun8i-r-ccu.h53
-rw-r--r--include/dt-bindings/reset/tegra210-car.h13
-rw-r--r--include/linux/clk/tegra.h3
-rw-r--r--include/linux/clk/ti.h55
118 files changed, 4211 insertions, 1370 deletions
diff --git a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
index 30c546900b60..07dbb358182c 100644
--- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
@@ -45,7 +45,7 @@ The following clocks are available:
45 - 1 15 SATA 45 - 1 15 SATA
46 - 1 16 SATA USB 46 - 1 16 SATA USB
47 - 1 17 Main 47 - 1 17 Main
48 - 1 18 SD/MMC 48 - 1 18 SD/MMC/GOP
49 - 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART) 49 - 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART)
50 - 1 22 USB3H0 50 - 1 22 USB3H0
51 - 1 23 USB3H1 51 - 1 23 USB3H1
@@ -65,7 +65,7 @@ Required properties:
65 "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio", 65 "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
66 "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none", 66 "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
67 "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata", 67 "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
68 "cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io", 68 "cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",
69 "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197"; 69 "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
70 70
71Example: 71Example:
@@ -78,6 +78,6 @@ Example:
78 gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio", 78 gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
79 "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none", 79 "cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
80 "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata", 80 "cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
81 "cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io", 81 "cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",
82 "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197"; 82 "cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
83 }; 83 };
diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
index ce06435d28ed..a09d627b5508 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
@@ -5,7 +5,8 @@ controllers within the SoC.
5 5
6Required Properties: 6Required Properties:
7 7
8- compatible: should be "amlogic,gxbb-clkc" 8- compatible: should be "amlogic,gxbb-clkc" for GXBB SoC,
9 or "amlogic,gxl-clkc" for GXL and GXM SoC.
9- reg: physical base address of the clock controller and length of memory 10- reg: physical base address of the clock controller and length of memory
10 mapped region. 11 mapped region.
11 12
diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
index 87e9c47a89a3..53d7e50ed875 100644
--- a/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
+++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.txt
@@ -6,18 +6,21 @@ from 3 to 12 output clocks.
6==I2C device node== 6==I2C device node==
7 7
8Required properties: 8Required properties:
9- compatible: shall be one of "idt,5p49v5923" , "idt,5p49v5933". 9- compatible: shall be one of "idt,5p49v5923" , "idt,5p49v5933" ,
10 "idt,5p49v5935".
10- reg: i2c device address, shall be 0x68 or 0x6a. 11- reg: i2c device address, shall be 0x68 or 0x6a.
11- #clock-cells: from common clock binding; shall be set to 1. 12- #clock-cells: from common clock binding; shall be set to 1.
12- clocks: from common clock binding; list of parent clock handles, 13- clocks: from common clock binding; list of parent clock handles,
13 - 5p49v5923: (required) either or both of XTAL or CLKIN 14 - 5p49v5923: (required) either or both of XTAL or CLKIN
14 reference clock. 15 reference clock.
15 - 5p49v5933: (optional) property not present (internal 16 - 5p49v5933 and
17 - 5p49v5935: (optional) property not present (internal
16 Xtal used) or CLKIN reference 18 Xtal used) or CLKIN reference
17 clock. 19 clock.
18- clock-names: from common clock binding; clock input names, can be 20- clock-names: from common clock binding; clock input names, can be
19 - 5p49v5923: (required) either or both of "xin", "clkin". 21 - 5p49v5923: (required) either or both of "xin", "clkin".
20 - 5p49v5933: (optional) property not present or "clkin". 22 - 5p49v5933 and
23 - 5p49v5935: (optional) property not present or "clkin".
21 24
22==Mapping between clock specifier and physical pins== 25==Mapping between clock specifier and physical pins==
23 26
@@ -34,6 +37,13 @@ clock specifier, the following mapping applies:
34 1 -- OUT1 37 1 -- OUT1
35 2 -- OUT4 38 2 -- OUT4
36 39
405P49V5935:
41 0 -- OUT0_SEL_I2CB
42 1 -- OUT1
43 2 -- OUT2
44 3 -- OUT3
45 4 -- OUT4
46
37==Example== 47==Example==
38 48
39/* 25MHz reference crystal */ 49/* 25MHz reference crystal */
diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk1108-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt
index 4da126116cf0..161326a4f9c1 100644
--- a/Documentation/devicetree/bindings/clock/rockchip,rk1108-cru.txt
+++ b/Documentation/devicetree/bindings/clock/rockchip,rv1108-cru.txt
@@ -1,12 +1,12 @@
1* Rockchip RK1108 Clock and Reset Unit 1* Rockchip RV1108 Clock and Reset Unit
2 2
3The RK1108 clock controller generates and supplies clock to various 3The RV1108 clock controller generates and supplies clock to various
4controllers within the SoC and also implements a reset controller for SoC 4controllers within the SoC and also implements a reset controller for SoC
5peripherals. 5peripherals.
6 6
7Required Properties: 7Required Properties:
8 8
9- compatible: should be "rockchip,rk1108-cru" 9- compatible: should be "rockchip,rv1108-cru"
10- reg: physical base address of the controller and length of memory mapped 10- reg: physical base address of the controller and length of memory mapped
11 region. 11 region.
12- #clock-cells: should be 1. 12- #clock-cells: should be 1.
@@ -19,7 +19,7 @@ Optional Properties:
19 19
20Each clock is assigned an identifier and client nodes can use this identifier 20Each clock is assigned an identifier and client nodes can use this identifier
21to specify the clock which they consume. All available clocks are defined as 21to specify the clock which they consume. All available clocks are defined as
22preprocessor macros in the dt-bindings/clock/rk1108-cru.h headers and can be 22preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be
23used in device tree sources. Similar macros exist for the reset sources in 23used in device tree sources. Similar macros exist for the reset sources in
24these files. 24these files.
25 25
@@ -38,7 +38,7 @@ clock-output-names:
38Example: Clock controller node: 38Example: Clock controller node:
39 39
40 cru: cru@20200000 { 40 cru: cru@20200000 {
41 compatible = "rockchip,rk1108-cru"; 41 compatible = "rockchip,rv1108-cru";
42 reg = <0x20200000 0x1000>; 42 reg = <0x20200000 0x1000>;
43 rockchip,grf = <&grf>; 43 rockchip,grf = <&grf>;
44 44
@@ -50,7 +50,7 @@ Example: UART controller node that consumes the clock generated by the clock
50 controller: 50 controller:
51 51
52 uart0: serial@10230000 { 52 uart0: serial@10230000 {
53 compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart"; 53 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
54 reg = <0x10230000 0x100>; 54 reg = <0x10230000 0x100>;
55 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 55 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
56 reg-shift = <2>; 56 reg-shift = <2>;
diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index bae5668cf427..e9c5a1d9834a 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -7,9 +7,12 @@ Required properties :
7 - "allwinner,sun8i-a23-ccu" 7 - "allwinner,sun8i-a23-ccu"
8 - "allwinner,sun8i-a33-ccu" 8 - "allwinner,sun8i-a33-ccu"
9 - "allwinner,sun8i-h3-ccu" 9 - "allwinner,sun8i-h3-ccu"
10 - "allwinner,sun8i-h3-r-ccu"
10 - "allwinner,sun8i-v3s-ccu" 11 - "allwinner,sun8i-v3s-ccu"
11 - "allwinner,sun9i-a80-ccu" 12 - "allwinner,sun9i-a80-ccu"
12 - "allwinner,sun50i-a64-ccu" 13 - "allwinner,sun50i-a64-ccu"
14 - "allwinner,sun50i-a64-r-ccu"
15 - "allwinner,sun50i-h5-ccu"
13 16
14- reg: Must contain the registers base address and length 17- reg: Must contain the registers base address and length
15- clocks: phandle to the oscillators feeding the CCU. Two are needed: 18- clocks: phandle to the oscillators feeding the CCU. Two are needed:
@@ -19,7 +22,10 @@ Required properties :
19- #clock-cells : must contain 1 22- #clock-cells : must contain 1
20- #reset-cells : must contain 1 23- #reset-cells : must contain 1
21 24
22Example: 25For the PRCM CCUs on H3/A64, one more clock is needed:
26- "iosc": the SoC's internal frequency oscillator
27
28Example for generic CCU:
23ccu: clock@01c20000 { 29ccu: clock@01c20000 {
24 compatible = "allwinner,sun8i-h3-ccu"; 30 compatible = "allwinner,sun8i-h3-ccu";
25 reg = <0x01c20000 0x400>; 31 reg = <0x01c20000 0x400>;
@@ -28,3 +34,13 @@ ccu: clock@01c20000 {
28 #clock-cells = <1>; 34 #clock-cells = <1>;
29 #reset-cells = <1>; 35 #reset-cells = <1>;
30}; 36};
37
38Example for PRCM CCU:
39r_ccu: clock@01f01400 {
40 compatible = "allwinner,sun50i-a64-r-ccu";
41 reg = <0x01f01400 0x100>;
42 clocks = <&osc24M>, <&osc32k>, <&iosc>;
43 clock-names = "hosc", "losc", "iosc";
44 #clock-cells = <1>;
45 #reset-cells = <1>;
46};
diff --git a/MAINTAINERS b/MAINTAINERS
index c265a5fe4848..8cb237925b06 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1069,6 +1069,16 @@ F: drivers/pinctrl/meson/
1069F: drivers/mmc/host/meson* 1069F: drivers/mmc/host/meson*
1070N: meson 1070N: meson
1071 1071
1072ARM/Amlogic Meson SoC CLOCK FRAMEWORK
1073M: Neil Armstrong <narmstrong@baylibre.com>
1074M: Jerome Brunet <jbrunet@baylibre.com>
1075L: linux-amlogic@lists.infradead.org
1076S: Maintained
1077F: drivers/clk/meson/
1078F: include/dt-bindings/clock/meson*
1079F: include/dt-bindings/clock/gxbb*
1080F: Documentation/devicetree/bindings/clock/amlogic*
1081
1072ARM/Annapurna Labs ALPINE ARCHITECTURE 1082ARM/Annapurna Labs ALPINE ARCHITECTURE
1073M: Tsahee Zidenberg <tsahee@annapurnalabs.com> 1083M: Tsahee Zidenberg <tsahee@annapurnalabs.com>
1074M: Antoine Tenart <antoine.tenart@free-electrons.com> 1084M: Antoine Tenart <antoine.tenart@free-electrons.com>
diff --git a/arch/arm/boot/dts/rk1108.dtsi b/arch/arm/boot/dts/rk1108.dtsi
index d6194bff7afe..4867342b88d4 100644
--- a/arch/arm/boot/dts/rk1108.dtsi
+++ b/arch/arm/boot/dts/rk1108.dtsi
@@ -41,7 +41,7 @@
41#include <dt-bindings/gpio/gpio.h> 41#include <dt-bindings/gpio/gpio.h>
42#include <dt-bindings/interrupt-controller/irq.h> 42#include <dt-bindings/interrupt-controller/irq.h>
43#include <dt-bindings/interrupt-controller/arm-gic.h> 43#include <dt-bindings/interrupt-controller/arm-gic.h>
44#include <dt-bindings/clock/rk1108-cru.h> 44#include <dt-bindings/clock/rv1108-cru.h>
45#include <dt-bindings/pinctrl/rockchip.h> 45#include <dt-bindings/pinctrl/rockchip.h>
46/ { 46/ {
47 #address-cells = <1>; 47 #address-cells = <1>;
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
index 59cf310bc1e9..e8d417309f33 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -138,7 +138,8 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
138 if (!dd) 138 if (!dd)
139 return -EINVAL; 139 return -EINVAL;
140 140
141 tmpset.cm_clksel1_pll = readl_relaxed(dd->mult_div1_reg); 141 tmpset.cm_clksel1_pll =
142 omap_clk_ll_ops.clk_readl(&dd->mult_div1_reg);
142 tmpset.cm_clksel1_pll &= ~(dd->mult_mask | 143 tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
143 dd->div1_mask); 144 dd->div1_mask);
144 div = ((curr_prcm_set->xtal_speed / 1000000) - 1); 145 div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 1270afdcacdf..42881f21cede 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -54,9 +54,10 @@ u16 cpu_mask;
54#define OMAP3PLUS_DPLL_FINT_MIN 32000 54#define OMAP3PLUS_DPLL_FINT_MIN 32000
55#define OMAP3PLUS_DPLL_FINT_MAX 52000000 55#define OMAP3PLUS_DPLL_FINT_MAX 52000000
56 56
57static struct ti_clk_ll_ops omap_clk_ll_ops = { 57struct ti_clk_ll_ops omap_clk_ll_ops = {
58 .clkdm_clk_enable = clkdm_clk_enable, 58 .clkdm_clk_enable = clkdm_clk_enable,
59 .clkdm_clk_disable = clkdm_clk_disable, 59 .clkdm_clk_disable = clkdm_clk_disable,
60 .clkdm_lookup = clkdm_lookup,
60 .cm_wait_module_ready = omap_cm_wait_module_ready, 61 .cm_wait_module_ready = omap_cm_wait_module_ready,
61 .cm_split_idlest_reg = cm_split_idlest_reg, 62 .cm_split_idlest_reg = cm_split_idlest_reg,
62}; 63};
@@ -78,38 +79,6 @@ int __init omap2_clk_setup_ll_ops(void)
78 * OMAP2+ specific clock functions 79 * OMAP2+ specific clock functions
79 */ 80 */
80 81
81/* Public functions */
82
83/**
84 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
85 * @clk: OMAP clock struct ptr to use
86 *
87 * Convert a clockdomain name stored in a struct clk 'clk' into a
88 * clockdomain pointer, and save it into the struct clk. Intended to be
89 * called during clk_register(). No return value.
90 */
91void omap2_init_clk_clkdm(struct clk_hw *hw)
92{
93 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
94 struct clockdomain *clkdm;
95 const char *clk_name;
96
97 if (!clk->clkdm_name)
98 return;
99
100 clk_name = __clk_get_name(hw->clk);
101
102 clkdm = clkdm_lookup(clk->clkdm_name);
103 if (clkdm) {
104 pr_debug("clock: associated clk %s to clkdm %s\n",
105 clk_name, clk->clkdm_name);
106 clk->clkdm = clkdm;
107 } else {
108 pr_debug("clock: could not associate clk %s to clkdm %s\n",
109 clk_name, clk->clkdm_name);
110 }
111}
112
113/** 82/**
114 * ti_clk_init_features - init clock features struct for the SoC 83 * ti_clk_init_features - init clock features struct for the SoC
115 * 84 *
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 4e66295dca25..cf45550197e6 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -64,6 +64,8 @@
64#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 64#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
65#define OMAP4XXX_EN_DPLL_LOCKED 0x7 65#define OMAP4XXX_EN_DPLL_LOCKED 0x7
66 66
67extern struct ti_clk_ll_ops omap_clk_ll_ops;
68
67extern u16 cpu_mask; 69extern u16 cpu_mask;
68 70
69extern const struct clkops clkops_omap2_dflt_wait; 71extern const struct clkops clkops_omap2_dflt_wait;
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 1fe3e6b833d2..de75cbcdc9d1 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -23,6 +23,7 @@
23#define MAX_MODULE_READY_TIME 2000 23#define MAX_MODULE_READY_TIME 2000
24 24
25# ifndef __ASSEMBLER__ 25# ifndef __ASSEMBLER__
26#include <linux/clk/ti.h>
26extern void __iomem *cm_base; 27extern void __iomem *cm_base;
27extern void __iomem *cm2_base; 28extern void __iomem *cm2_base;
28extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2); 29extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2);
@@ -50,7 +51,7 @@ extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2);
50 * @module_disable: ptr to the SoC CM-specific module_disable impl 51 * @module_disable: ptr to the SoC CM-specific module_disable impl
51 */ 52 */
52struct cm_ll_data { 53struct cm_ll_data {
53 int (*split_idlest_reg)(void __iomem *idlest_reg, s16 *prcm_inst, 54 int (*split_idlest_reg)(struct clk_omap_reg *idlest_reg, s16 *prcm_inst,
54 u8 *idlest_reg_id); 55 u8 *idlest_reg_id);
55 int (*wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg, 56 int (*wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg,
56 u8 idlest_shift); 57 u8 idlest_shift);
@@ -60,7 +61,7 @@ struct cm_ll_data {
60 void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs); 61 void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs);
61}; 62};
62 63
63extern int cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst, 64extern int cm_split_idlest_reg(struct clk_omap_reg *idlest_reg, s16 *prcm_inst,
64 u8 *idlest_reg_id); 65 u8 *idlest_reg_id);
65int omap_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_reg, 66int omap_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_reg,
66 u8 idlest_shift); 67 u8 idlest_shift);
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index 3e5fd3587eb1..cd90b4c6a06b 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -204,7 +204,7 @@ void omap2xxx_cm_apll96_disable(void)
204 * XXX This function is only needed until absolute register addresses are 204 * XXX This function is only needed until absolute register addresses are
205 * removed from the OMAP struct clk records. 205 * removed from the OMAP struct clk records.
206 */ 206 */
207static int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg, 207static int omap2xxx_cm_split_idlest_reg(struct clk_omap_reg *idlest_reg,
208 s16 *prcm_inst, 208 s16 *prcm_inst,
209 u8 *idlest_reg_id) 209 u8 *idlest_reg_id)
210{ 210{
@@ -212,10 +212,7 @@ static int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
212 u8 idlest_offs; 212 u8 idlest_offs;
213 int i; 213 int i;
214 214
215 if (idlest_reg < cm_base || idlest_reg > (cm_base + 0x0fff)) 215 idlest_offs = idlest_reg->offset & 0xff;
216 return -EINVAL;
217
218 idlest_offs = (unsigned long)idlest_reg & 0xff;
219 for (i = 0; i < ARRAY_SIZE(omap2xxx_cm_idlest_offs); i++) { 216 for (i = 0; i < ARRAY_SIZE(omap2xxx_cm_idlest_offs); i++) {
220 if (idlest_offs == omap2xxx_cm_idlest_offs[i]) { 217 if (idlest_offs == omap2xxx_cm_idlest_offs[i]) {
221 *idlest_reg_id = i + 1; 218 *idlest_reg_id = i + 1;
@@ -226,7 +223,7 @@ static int omap2xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
226 if (i == ARRAY_SIZE(omap2xxx_cm_idlest_offs)) 223 if (i == ARRAY_SIZE(omap2xxx_cm_idlest_offs))
227 return -EINVAL; 224 return -EINVAL;
228 225
229 offs = idlest_reg - cm_base; 226 offs = idlest_reg->offset;
230 offs &= 0xff00; 227 offs &= 0xff00;
231 *prcm_inst = offs; 228 *prcm_inst = offs;
232 229
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index d91ae8206d1e..55b046a719dc 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -118,7 +118,7 @@ static int omap3xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id,
118 * XXX This function is only needed until absolute register addresses are 118 * XXX This function is only needed until absolute register addresses are
119 * removed from the OMAP struct clk records. 119 * removed from the OMAP struct clk records.
120 */ 120 */
121static int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg, 121static int omap3xxx_cm_split_idlest_reg(struct clk_omap_reg *idlest_reg,
122 s16 *prcm_inst, 122 s16 *prcm_inst,
123 u8 *idlest_reg_id) 123 u8 *idlest_reg_id)
124{ 124{
@@ -126,11 +126,7 @@ static int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
126 u8 idlest_offs; 126 u8 idlest_offs;
127 int i; 127 int i;
128 128
129 if (idlest_reg < (cm_base + OMAP3430_IVA2_MOD) || 129 idlest_offs = idlest_reg->offset & 0xff;
130 idlest_reg > (cm_base + 0x1ffff))
131 return -EINVAL;
132
133 idlest_offs = (unsigned long)idlest_reg & 0xff;
134 for (i = 0; i < ARRAY_SIZE(omap3xxx_cm_idlest_offs); i++) { 130 for (i = 0; i < ARRAY_SIZE(omap3xxx_cm_idlest_offs); i++) {
135 if (idlest_offs == omap3xxx_cm_idlest_offs[i]) { 131 if (idlest_offs == omap3xxx_cm_idlest_offs[i]) {
136 *idlest_reg_id = i + 1; 132 *idlest_reg_id = i + 1;
@@ -141,7 +137,7 @@ static int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg,
141 if (i == ARRAY_SIZE(omap3xxx_cm_idlest_offs)) 137 if (i == ARRAY_SIZE(omap3xxx_cm_idlest_offs))
142 return -EINVAL; 138 return -EINVAL;
143 139
144 offs = idlest_reg - cm_base; 140 offs = idlest_reg->offset;
145 offs &= 0xff00; 141 offs &= 0xff00;
146 *prcm_inst = offs; 142 *prcm_inst = offs;
147 143
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 23e8bcec34e3..bbe41f4c9dc8 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -65,7 +65,7 @@ void __init omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2)
65 * or 0 upon success. XXX This function is only needed until absolute 65 * or 0 upon success. XXX This function is only needed until absolute
66 * register addresses are removed from the OMAP struct clk records. 66 * register addresses are removed from the OMAP struct clk records.
67 */ 67 */
68int cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst, 68int cm_split_idlest_reg(struct clk_omap_reg *idlest_reg, s16 *prcm_inst,
69 u8 *idlest_reg_id) 69 u8 *idlest_reg_id)
70{ 70{
71 if (!cm_ll_data->split_idlest_reg) { 71 if (!cm_ll_data->split_idlest_reg) {
diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c
index e04634c46395..2d61893da024 100644
--- a/drivers/clk/bcm/clk-iproc-pll.c
+++ b/drivers/clk/bcm/clk-iproc-pll.c
@@ -277,7 +277,7 @@ static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index,
277 if (rate >= VCO_LOW && rate < VCO_HIGH) { 277 if (rate >= VCO_LOW && rate < VCO_HIGH) {
278 ki = 4; 278 ki = 4;
279 kp_index = KP_BAND_MID; 279 kp_index = KP_BAND_MID;
280 } else if (rate >= VCO_HIGH && rate && rate < VCO_HIGH_HIGH) { 280 } else if (rate >= VCO_HIGH && rate < VCO_HIGH_HIGH) {
281 ki = 3; 281 ki = 3;
282 kp_index = KP_BAND_HIGH; 282 kp_index = KP_BAND_HIGH;
283 } else if (rate >= VCO_HIGH_HIGH && rate < VCO_MAX) { 283 } else if (rate >= VCO_HIGH_HIGH && rate < VCO_MAX) {
diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c
index 3fca0526d940..4df38c5ff96c 100644
--- a/drivers/clk/clk-cs2000-cp.c
+++ b/drivers/clk/clk-cs2000-cp.c
@@ -36,15 +36,27 @@
36 36
37/* DEVICE_CTRL */ 37/* DEVICE_CTRL */
38#define PLL_UNLOCK (1 << 7) 38#define PLL_UNLOCK (1 << 7)
39#define AUXOUTDIS (1 << 1)
40#define CLKOUTDIS (1 << 0)
39 41
40/* DEVICE_CFG1 */ 42/* DEVICE_CFG1 */
41#define RSEL(x) (((x) & 0x3) << 3) 43#define RSEL(x) (((x) & 0x3) << 3)
42#define RSEL_MASK RSEL(0x3) 44#define RSEL_MASK RSEL(0x3)
43#define ENDEV1 (0x1) 45#define ENDEV1 (0x1)
44 46
47/* DEVICE_CFG2 */
48#define AUTORMOD (1 << 3)
49#define LOCKCLK(x) (((x) & 0x3) << 1)
50#define LOCKCLK_MASK LOCKCLK(0x3)
51#define FRACNSRC (1 << 0)
52
45/* GLOBAL_CFG */ 53/* GLOBAL_CFG */
46#define ENDEV2 (0x1) 54#define ENDEV2 (0x1)
47 55
56/* FUNC_CFG1 */
57#define REFCLKDIV(x) (((x) & 0x3) << 3)
58#define REFCLKDIV_MASK REFCLKDIV(0x3)
59
48#define CH_SIZE_ERR(ch) ((ch < 0) || (ch >= CH_MAX)) 60#define CH_SIZE_ERR(ch) ((ch < 0) || (ch >= CH_MAX))
49#define hw_to_priv(_hw) container_of(_hw, struct cs2000_priv, hw) 61#define hw_to_priv(_hw) container_of(_hw, struct cs2000_priv, hw)
50#define priv_to_client(priv) (priv->client) 62#define priv_to_client(priv) (priv->client)
@@ -127,7 +139,9 @@ static int cs2000_clk_in_bound_rate(struct cs2000_priv *priv,
127 else 139 else
128 return -EINVAL; 140 return -EINVAL;
129 141
130 return cs2000_bset(priv, FUNC_CFG1, 0x3 << 3, val << 3); 142 return cs2000_bset(priv, FUNC_CFG1,
143 REFCLKDIV_MASK,
144 REFCLKDIV(val));
131} 145}
132 146
133static int cs2000_wait_pll_lock(struct cs2000_priv *priv) 147static int cs2000_wait_pll_lock(struct cs2000_priv *priv)
@@ -153,7 +167,10 @@ static int cs2000_wait_pll_lock(struct cs2000_priv *priv)
153static int cs2000_clk_out_enable(struct cs2000_priv *priv, bool enable) 167static int cs2000_clk_out_enable(struct cs2000_priv *priv, bool enable)
154{ 168{
155 /* enable both AUX_OUT, CLK_OUT */ 169 /* enable both AUX_OUT, CLK_OUT */
156 return cs2000_write(priv, DEVICE_CTRL, enable ? 0 : 0x3); 170 return cs2000_bset(priv, DEVICE_CTRL,
171 (AUXOUTDIS | CLKOUTDIS),
172 enable ? 0 :
173 (AUXOUTDIS | CLKOUTDIS));
157} 174}
158 175
159static u32 cs2000_rate_to_ratio(u32 rate_in, u32 rate_out) 176static u32 cs2000_rate_to_ratio(u32 rate_in, u32 rate_out)
@@ -243,7 +260,9 @@ static int cs2000_ratio_select(struct cs2000_priv *priv, int ch)
243 if (ret < 0) 260 if (ret < 0)
244 return ret; 261 return ret;
245 262
246 ret = cs2000_write(priv, DEVICE_CFG2, 0x0); 263 ret = cs2000_bset(priv, DEVICE_CFG2,
264 (AUTORMOD | LOCKCLK_MASK | FRACNSRC),
265 0);
247 if (ret < 0) 266 if (ret < 0)
248 return ret; 267 return ret;
249 268
@@ -351,8 +370,7 @@ static const struct clk_ops cs2000_ops = {
351 370
352static int cs2000_clk_get(struct cs2000_priv *priv) 371static int cs2000_clk_get(struct cs2000_priv *priv)
353{ 372{
354 struct i2c_client *client = priv_to_client(priv); 373 struct device *dev = priv_to_dev(priv);
355 struct device *dev = &client->dev;
356 struct clk *clk_in, *ref_clk; 374 struct clk *clk_in, *ref_clk;
357 375
358 clk_in = devm_clk_get(dev, "clk_in"); 376 clk_in = devm_clk_get(dev, "clk_in");
@@ -420,8 +438,7 @@ static int cs2000_clk_register(struct cs2000_priv *priv)
420 438
421static int cs2000_version_print(struct cs2000_priv *priv) 439static int cs2000_version_print(struct cs2000_priv *priv)
422{ 440{
423 struct i2c_client *client = priv_to_client(priv); 441 struct device *dev = priv_to_dev(priv);
424 struct device *dev = &client->dev;
425 s32 val; 442 s32 val;
426 const char *revision; 443 const char *revision;
427 444
@@ -452,7 +469,7 @@ static int cs2000_version_print(struct cs2000_priv *priv)
452static int cs2000_remove(struct i2c_client *client) 469static int cs2000_remove(struct i2c_client *client)
453{ 470{
454 struct cs2000_priv *priv = i2c_get_clientdata(client); 471 struct cs2000_priv *priv = i2c_get_clientdata(client);
455 struct device *dev = &client->dev; 472 struct device *dev = priv_to_dev(priv);
456 struct device_node *np = dev->of_node; 473 struct device_node *np = dev->of_node;
457 474
458 of_clk_del_provider(np); 475 of_clk_del_provider(np);
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index ab609a76706f..68e2a4e499f1 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -429,6 +429,13 @@ static const struct clk_div_table pll_divp_table[] = {
429 { 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 }, { 0 } 429 { 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 }, { 0 }
430}; 430};
431 431
432static const struct clk_div_table pll_divq_table[] = {
433 { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 },
434 { 8, 8 }, { 9, 9 }, { 10, 10 }, { 11, 11 }, { 12, 12 }, { 13, 13 },
435 { 14, 14 }, { 15, 15 },
436 { 0 }
437};
438
432static const struct clk_div_table pll_divr_table[] = { 439static const struct clk_div_table pll_divr_table[] = {
433 { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, { 0 } 440 { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, { 0 }
434}; 441};
@@ -496,9 +503,9 @@ struct stm32f4_div_data {
496 503
497#define MAX_PLL_DIV 3 504#define MAX_PLL_DIV 3
498static const struct stm32f4_div_data div_data[MAX_PLL_DIV] = { 505static const struct stm32f4_div_data div_data[MAX_PLL_DIV] = {
499 { 16, 2, 0, pll_divp_table }, 506 { 16, 2, 0, pll_divp_table },
500 { 24, 4, CLK_DIVIDER_ONE_BASED, NULL }, 507 { 24, 4, 0, pll_divq_table },
501 { 28, 3, 0, pll_divr_table }, 508 { 28, 3, 0, pll_divr_table },
502}; 509};
503 510
504struct stm32f4_pll_data { 511struct stm32f4_pll_data {
@@ -524,19 +531,26 @@ static int stm32f4_pll_is_enabled(struct clk_hw *hw)
524 return clk_gate_ops.is_enabled(hw); 531 return clk_gate_ops.is_enabled(hw);
525} 532}
526 533
534#define PLL_TIMEOUT 10000
535
527static int stm32f4_pll_enable(struct clk_hw *hw) 536static int stm32f4_pll_enable(struct clk_hw *hw)
528{ 537{
529 struct clk_gate *gate = to_clk_gate(hw); 538 struct clk_gate *gate = to_clk_gate(hw);
530 struct stm32f4_pll *pll = to_stm32f4_pll(gate); 539 struct stm32f4_pll *pll = to_stm32f4_pll(gate);
531 int ret = 0; 540 int bit_status;
532 unsigned long reg; 541 unsigned int timeout = PLL_TIMEOUT;
533 542
534 ret = clk_gate_ops.enable(hw); 543 if (clk_gate_ops.is_enabled(hw))
544 return 0;
535 545
536 ret = readl_relaxed_poll_timeout_atomic(base + STM32F4_RCC_CR, reg, 546 clk_gate_ops.enable(hw);
537 reg & (1 << pll->bit_rdy_idx), 0, 10000);
538 547
539 return ret; 548 do {
549 bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx));
550
551 } while (bit_status && --timeout);
552
553 return bit_status;
540} 554}
541 555
542static void stm32f4_pll_disable(struct clk_hw *hw) 556static void stm32f4_pll_disable(struct clk_hw *hw)
@@ -827,24 +841,32 @@ struct stm32_rgate {
827 u8 bit_rdy_idx; 841 u8 bit_rdy_idx;
828}; 842};
829 843
830#define RTC_TIMEOUT 1000000 844#define RGATE_TIMEOUT 50000
831 845
832static int rgclk_enable(struct clk_hw *hw) 846static int rgclk_enable(struct clk_hw *hw)
833{ 847{
834 struct clk_gate *gate = to_clk_gate(hw); 848 struct clk_gate *gate = to_clk_gate(hw);
835 struct stm32_rgate *rgate = to_rgclk(gate); 849 struct stm32_rgate *rgate = to_rgclk(gate);
836 u32 reg; 850 int bit_status;
837 int ret; 851 unsigned int timeout = RGATE_TIMEOUT;
852
853 if (clk_gate_ops.is_enabled(hw))
854 return 0;
838 855
839 disable_power_domain_write_protection(); 856 disable_power_domain_write_protection();
840 857
841 clk_gate_ops.enable(hw); 858 clk_gate_ops.enable(hw);
842 859
843 ret = readl_relaxed_poll_timeout_atomic(gate->reg, reg, 860 do {
844 reg & rgate->bit_rdy_idx, 1000, RTC_TIMEOUT); 861 bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy_idx));
862 if (bit_status)
863 udelay(100);
864
865 } while (bit_status && --timeout);
845 866
846 enable_power_domain_write_protection(); 867 enable_power_domain_write_protection();
847 return ret; 868
869 return bit_status;
848} 870}
849 871
850static void rgclk_disable(struct clk_hw *hw) 872static void rgclk_disable(struct clk_hw *hw)
@@ -1526,7 +1548,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
1526 } 1548 }
1527 1549
1528 clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0, 1550 clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0,
1529 base + STM32F4_RCC_CSR, 0, 2, 0, &stm32f4_clk_lock); 1551 base + STM32F4_RCC_CSR, 0, 1, 0, &stm32f4_clk_lock);
1530 1552
1531 if (IS_ERR(clks[CLK_LSI])) { 1553 if (IS_ERR(clks[CLK_LSI])) {
1532 pr_err("Unable to register lsi clock\n"); 1554 pr_err("Unable to register lsi clock\n");
@@ -1534,7 +1556,7 @@ static void __init stm32f4_rcc_init(struct device_node *np)
1534 } 1556 }
1535 1557
1536 clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0, 1558 clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0,
1537 base + STM32F4_RCC_BDCR, 0, 2, 0, &stm32f4_clk_lock); 1559 base + STM32F4_RCC_BDCR, 0, 1, 0, &stm32f4_clk_lock);
1538 1560
1539 if (IS_ERR(clks[CLK_LSE])) { 1561 if (IS_ERR(clks[CLK_LSE])) {
1540 pr_err("Unable to register lse clock\n"); 1562 pr_err("Unable to register lse clock\n");
diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
index 56741f3cf0a3..ea7d552a2f2b 100644
--- a/drivers/clk/clk-versaclock5.c
+++ b/drivers/clk/clk-versaclock5.c
@@ -113,10 +113,29 @@
113#define VC5_MUX_IN_XIN BIT(0) 113#define VC5_MUX_IN_XIN BIT(0)
114#define VC5_MUX_IN_CLKIN BIT(1) 114#define VC5_MUX_IN_CLKIN BIT(1)
115 115
116/* Maximum number of clk_out supported by this driver */
117#define VC5_MAX_CLK_OUT_NUM 5
118
119/* Maximum number of FODs supported by this driver */
120#define VC5_MAX_FOD_NUM 4
121
122/* flags to describe chip features */
123/* chip has built-in oscilator */
124#define VC5_HAS_INTERNAL_XTAL BIT(0)
125
116/* Supported IDT VC5 models. */ 126/* Supported IDT VC5 models. */
117enum vc5_model { 127enum vc5_model {
118 IDT_VC5_5P49V5923, 128 IDT_VC5_5P49V5923,
119 IDT_VC5_5P49V5933, 129 IDT_VC5_5P49V5933,
130 IDT_VC5_5P49V5935,
131};
132
133/* Structure to describe features of a particular VC5 model */
134struct vc5_chip_info {
135 const enum vc5_model model;
136 const unsigned int clk_fod_cnt;
137 const unsigned int clk_out_cnt;
138 const u32 flags;
120}; 139};
121 140
122struct vc5_driver_data; 141struct vc5_driver_data;
@@ -132,15 +151,15 @@ struct vc5_hw_data {
132struct vc5_driver_data { 151struct vc5_driver_data {
133 struct i2c_client *client; 152 struct i2c_client *client;
134 struct regmap *regmap; 153 struct regmap *regmap;
135 enum vc5_model model; 154 const struct vc5_chip_info *chip_info;
136 155
137 struct clk *pin_xin; 156 struct clk *pin_xin;
138 struct clk *pin_clkin; 157 struct clk *pin_clkin;
139 unsigned char clk_mux_ins; 158 unsigned char clk_mux_ins;
140 struct clk_hw clk_mux; 159 struct clk_hw clk_mux;
141 struct vc5_hw_data clk_pll; 160 struct vc5_hw_data clk_pll;
142 struct vc5_hw_data clk_fod[2]; 161 struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM];
143 struct vc5_hw_data clk_out[3]; 162 struct vc5_hw_data clk_out[VC5_MAX_CLK_OUT_NUM];
144}; 163};
145 164
146static const char * const vc5_mux_names[] = { 165static const char * const vc5_mux_names[] = {
@@ -563,7 +582,7 @@ static struct clk_hw *vc5_of_clk_get(struct of_phandle_args *clkspec,
563 struct vc5_driver_data *vc5 = data; 582 struct vc5_driver_data *vc5 = data;
564 unsigned int idx = clkspec->args[0]; 583 unsigned int idx = clkspec->args[0];
565 584
566 if (idx > 2) 585 if (idx >= vc5->chip_info->clk_out_cnt)
567 return ERR_PTR(-EINVAL); 586 return ERR_PTR(-EINVAL);
568 587
569 return &vc5->clk_out[idx].hw; 588 return &vc5->clk_out[idx].hw;
@@ -576,6 +595,7 @@ static int vc5_map_index_to_output(const enum vc5_model model,
576 case IDT_VC5_5P49V5933: 595 case IDT_VC5_5P49V5933:
577 return (n == 0) ? 0 : 3; 596 return (n == 0) ? 0 : 3;
578 case IDT_VC5_5P49V5923: 597 case IDT_VC5_5P49V5923:
598 case IDT_VC5_5P49V5935:
579 default: 599 default:
580 return n; 600 return n;
581 } 601 }
@@ -586,12 +606,10 @@ static const struct of_device_id clk_vc5_of_match[];
586static int vc5_probe(struct i2c_client *client, 606static int vc5_probe(struct i2c_client *client,
587 const struct i2c_device_id *id) 607 const struct i2c_device_id *id)
588{ 608{
589 const struct of_device_id *of_id =
590 of_match_device(clk_vc5_of_match, &client->dev);
591 struct vc5_driver_data *vc5; 609 struct vc5_driver_data *vc5;
592 struct clk_init_data init; 610 struct clk_init_data init;
593 const char *parent_names[2]; 611 const char *parent_names[2];
594 unsigned int n, idx; 612 unsigned int n, idx = 0;
595 int ret; 613 int ret;
596 614
597 vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL); 615 vc5 = devm_kzalloc(&client->dev, sizeof(*vc5), GFP_KERNEL);
@@ -600,7 +618,7 @@ static int vc5_probe(struct i2c_client *client,
600 618
601 i2c_set_clientdata(client, vc5); 619 i2c_set_clientdata(client, vc5);
602 vc5->client = client; 620 vc5->client = client;
603 vc5->model = (enum vc5_model)of_id->data; 621 vc5->chip_info = of_device_get_match_data(&client->dev);
604 622
605 vc5->pin_xin = devm_clk_get(&client->dev, "xin"); 623 vc5->pin_xin = devm_clk_get(&client->dev, "xin");
606 if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER) 624 if (PTR_ERR(vc5->pin_xin) == -EPROBE_DEFER)
@@ -622,8 +640,7 @@ static int vc5_probe(struct i2c_client *client,
622 if (!IS_ERR(vc5->pin_xin)) { 640 if (!IS_ERR(vc5->pin_xin)) {
623 vc5->clk_mux_ins |= VC5_MUX_IN_XIN; 641 vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
624 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin); 642 parent_names[init.num_parents++] = __clk_get_name(vc5->pin_xin);
625 } else if (vc5->model == IDT_VC5_5P49V5933) { 643 } else if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) {
626 /* IDT VC5 5P49V5933 has built-in oscilator. */
627 vc5->pin_xin = clk_register_fixed_rate(&client->dev, 644 vc5->pin_xin = clk_register_fixed_rate(&client->dev,
628 "internal-xtal", NULL, 645 "internal-xtal", NULL,
629 0, 25000000); 646 0, 25000000);
@@ -672,8 +689,8 @@ static int vc5_probe(struct i2c_client *client,
672 } 689 }
673 690
674 /* Register FODs */ 691 /* Register FODs */
675 for (n = 0; n < 2; n++) { 692 for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) {
676 idx = vc5_map_index_to_output(vc5->model, n); 693 idx = vc5_map_index_to_output(vc5->chip_info->model, n);
677 memset(&init, 0, sizeof(init)); 694 memset(&init, 0, sizeof(init));
678 init.name = vc5_fod_names[idx]; 695 init.name = vc5_fod_names[idx];
679 init.ops = &vc5_fod_ops; 696 init.ops = &vc5_fod_ops;
@@ -709,8 +726,8 @@ static int vc5_probe(struct i2c_client *client,
709 } 726 }
710 727
711 /* Register FOD-connected OUTx outputs */ 728 /* Register FOD-connected OUTx outputs */
712 for (n = 1; n < 3; n++) { 729 for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) {
713 idx = vc5_map_index_to_output(vc5->model, n - 1); 730 idx = vc5_map_index_to_output(vc5->chip_info->model, n - 1);
714 parent_names[0] = vc5_fod_names[idx]; 731 parent_names[0] = vc5_fod_names[idx];
715 if (n == 1) 732 if (n == 1)
716 parent_names[1] = vc5_mux_names[0]; 733 parent_names[1] = vc5_mux_names[0];
@@ -744,7 +761,7 @@ static int vc5_probe(struct i2c_client *client,
744 return 0; 761 return 0;
745 762
746err_clk: 763err_clk:
747 if (vc5->model == IDT_VC5_5P49V5933) 764 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
748 clk_unregister_fixed_rate(vc5->pin_xin); 765 clk_unregister_fixed_rate(vc5->pin_xin);
749 return ret; 766 return ret;
750} 767}
@@ -755,22 +772,45 @@ static int vc5_remove(struct i2c_client *client)
755 772
756 of_clk_del_provider(client->dev.of_node); 773 of_clk_del_provider(client->dev.of_node);
757 774
758 if (vc5->model == IDT_VC5_5P49V5933) 775 if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)
759 clk_unregister_fixed_rate(vc5->pin_xin); 776 clk_unregister_fixed_rate(vc5->pin_xin);
760 777
761 return 0; 778 return 0;
762} 779}
763 780
781static const struct vc5_chip_info idt_5p49v5923_info = {
782 .model = IDT_VC5_5P49V5923,
783 .clk_fod_cnt = 2,
784 .clk_out_cnt = 3,
785 .flags = 0,
786};
787
788static const struct vc5_chip_info idt_5p49v5933_info = {
789 .model = IDT_VC5_5P49V5933,
790 .clk_fod_cnt = 2,
791 .clk_out_cnt = 3,
792 .flags = VC5_HAS_INTERNAL_XTAL,
793};
794
795static const struct vc5_chip_info idt_5p49v5935_info = {
796 .model = IDT_VC5_5P49V5935,
797 .clk_fod_cnt = 4,
798 .clk_out_cnt = 5,
799 .flags = VC5_HAS_INTERNAL_XTAL,
800};
801
764static const struct i2c_device_id vc5_id[] = { 802static const struct i2c_device_id vc5_id[] = {
765 { "5p49v5923", .driver_data = IDT_VC5_5P49V5923 }, 803 { "5p49v5923", .driver_data = IDT_VC5_5P49V5923 },
766 { "5p49v5933", .driver_data = IDT_VC5_5P49V5933 }, 804 { "5p49v5933", .driver_data = IDT_VC5_5P49V5933 },
805 { "5p49v5935", .driver_data = IDT_VC5_5P49V5935 },
767 { } 806 { }
768}; 807};
769MODULE_DEVICE_TABLE(i2c, vc5_id); 808MODULE_DEVICE_TABLE(i2c, vc5_id);
770 809
771static const struct of_device_id clk_vc5_of_match[] = { 810static const struct of_device_id clk_vc5_of_match[] = {
772 { .compatible = "idt,5p49v5923", .data = (void *)IDT_VC5_5P49V5923 }, 811 { .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info },
773 { .compatible = "idt,5p49v5933", .data = (void *)IDT_VC5_5P49V5933 }, 812 { .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },
813 { .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
774 { }, 814 { },
775}; 815};
776MODULE_DEVICE_TABLE(of, clk_vc5_of_match); 816MODULE_DEVICE_TABLE(of, clk_vc5_of_match);
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 0fb39fe217d1..cddddbe46d9d 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -966,6 +966,8 @@ static int __clk_notify(struct clk_core *core, unsigned long msg,
966 cnd.clk = cn->clk; 966 cnd.clk = cn->clk;
967 ret = srcu_notifier_call_chain(&cn->notifier_head, msg, 967 ret = srcu_notifier_call_chain(&cn->notifier_head, msg,
968 &cnd); 968 &cnd);
969 if (ret & NOTIFY_STOP_MASK)
970 return ret;
969 } 971 }
970 } 972 }
971 973
@@ -2126,6 +2128,31 @@ static const struct file_operations clk_dump_fops = {
2126 .release = single_release, 2128 .release = single_release,
2127}; 2129};
2128 2130
2131static int possible_parents_dump(struct seq_file *s, void *data)
2132{
2133 struct clk_core *core = s->private;
2134 int i;
2135
2136 for (i = 0; i < core->num_parents - 1; i++)
2137 seq_printf(s, "%s ", core->parent_names[i]);
2138
2139 seq_printf(s, "%s\n", core->parent_names[i]);
2140
2141 return 0;
2142}
2143
2144static int possible_parents_open(struct inode *inode, struct file *file)
2145{
2146 return single_open(file, possible_parents_dump, inode->i_private);
2147}
2148
2149static const struct file_operations possible_parents_fops = {
2150 .open = possible_parents_open,
2151 .read = seq_read,
2152 .llseek = seq_lseek,
2153 .release = single_release,
2154};
2155
2129static int clk_debug_create_one(struct clk_core *core, struct dentry *pdentry) 2156static int clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
2130{ 2157{
2131 struct dentry *d; 2158 struct dentry *d;
@@ -2177,6 +2204,13 @@ static int clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
2177 if (!d) 2204 if (!d)
2178 goto err_out; 2205 goto err_out;
2179 2206
2207 if (core->num_parents > 1) {
2208 d = debugfs_create_file("clk_possible_parents", S_IRUGO,
2209 core->dentry, core, &possible_parents_fops);
2210 if (!d)
2211 goto err_out;
2212 }
2213
2180 if (core->ops->debug_init) { 2214 if (core->ops->debug_init) {
2181 ret = core->ops->debug_init(core->hw, core->dentry); 2215 ret = core->ops->debug_init(core->hw, core->dentry);
2182 if (ret) 2216 if (ret)
@@ -2502,7 +2536,7 @@ struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
2502 2536
2503 clk->core = hw->core; 2537 clk->core = hw->core;
2504 clk->dev_id = dev_id; 2538 clk->dev_id = dev_id;
2505 clk->con_id = con_id; 2539 clk->con_id = kstrdup_const(con_id, GFP_KERNEL);
2506 clk->max_rate = ULONG_MAX; 2540 clk->max_rate = ULONG_MAX;
2507 2541
2508 clk_prepare_lock(); 2542 clk_prepare_lock();
@@ -2518,6 +2552,7 @@ void __clk_free_clk(struct clk *clk)
2518 hlist_del(&clk->clks_node); 2552 hlist_del(&clk->clks_node);
2519 clk_prepare_unlock(); 2553 clk_prepare_unlock();
2520 2554
2555 kfree_const(clk->con_id);
2521 kfree(clk); 2556 kfree(clk);
2522} 2557}
2523 2558
diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c
index c0e8e1f196aa..2ae151ce623a 100644
--- a/drivers/clk/hisilicon/clk-hi6220.c
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -134,6 +134,7 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = {
134 { HI6220_UART4_PCLK, "uart4_pclk", "uart4_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 8, 0, }, 134 { HI6220_UART4_PCLK, "uart4_pclk", "uart4_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 8, 0, },
135 { HI6220_SPI_CLK, "spi_clk", "clk_150m", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 9, 0, }, 135 { HI6220_SPI_CLK, "spi_clk", "clk_150m", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 9, 0, },
136 { HI6220_TSENSOR_CLK, "tsensor_clk", "clk_bus", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 12, 0, }, 136 { HI6220_TSENSOR_CLK, "tsensor_clk", "clk_bus", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 12, 0, },
137 { HI6220_DAPB_CLK, "dapb_clk", "cs_dapb", CLK_SET_RATE_PARENT|CLK_IS_CRITICAL, 0x230, 18, 0, },
137 { HI6220_MMU_CLK, "mmu_clk", "ddrc_axi1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x240, 11, 0, }, 138 { HI6220_MMU_CLK, "mmu_clk", "ddrc_axi1", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x240, 11, 0, },
138 { HI6220_HIFI_SEL, "hifi_sel", "hifi_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 0, 0, }, 139 { HI6220_HIFI_SEL, "hifi_sel", "hifi_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 0, 0, },
139 { HI6220_MMC0_SYSPLL, "mmc0_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 1, 0, }, 140 { HI6220_MMC0_SYSPLL, "mmc0_syspll", "syspll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 1, 0, },
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index 75c35fb12b60..b4e0dff3c8c2 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -73,7 +73,7 @@ static struct clk *clks[IMX6UL_CLK_END];
73static struct clk_onecell_data clk_data; 73static struct clk_onecell_data clk_data;
74 74
75static int const clks_init_on[] __initconst = { 75static int const clks_init_on[] __initconst = {
76 IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2, IMX6UL_CLK_AIPSTZ3, 76 IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2,
77 IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM, 77 IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM,
78 IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG, 78 IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG,
79}; 79};
@@ -341,9 +341,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
341 clks[IMX6UL_CLK_GPT2_SERIAL] = imx_clk_gate2("gpt2_serial", "perclk", base + 0x68, 26); 341 clks[IMX6UL_CLK_GPT2_SERIAL] = imx_clk_gate2("gpt2_serial", "perclk", base + 0x68, 26);
342 clks[IMX6UL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28); 342 clks[IMX6UL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28);
343 clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28); 343 clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28);
344 if (clk_on_imx6ul()) 344 if (clk_on_imx6ull())
345 clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30);
346 else if (clk_on_imx6ull())
347 clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x80, 18); 345 clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x80, 18);
348 346
349 /* CCGR1 */ 347 /* CCGR1 */
@@ -360,7 +358,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
360 clks[IMX6UL_CLK_GPT1_BUS] = imx_clk_gate2("gpt1_bus", "perclk", base + 0x6c, 20); 358 clks[IMX6UL_CLK_GPT1_BUS] = imx_clk_gate2("gpt1_bus", "perclk", base + 0x6c, 20);
361 clks[IMX6UL_CLK_GPT1_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22); 359 clks[IMX6UL_CLK_GPT1_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22);
362 clks[IMX6UL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24); 360 clks[IMX6UL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24);
363 clks[IMX6UL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serail", "uart_podf", base + 0x6c, 24); 361 clks[IMX6UL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serial", "uart_podf", base + 0x6c, 24);
364 362
365 /* CCGR2 */ 363 /* CCGR2 */
366 if (clk_on_imx6ull()) { 364 if (clk_on_imx6ull()) {
@@ -482,6 +480,9 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node)
482 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) 480 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
483 clk_prepare_enable(clks[clks_init_on[i]]); 481 clk_prepare_enable(clks[clks_init_on[i]]);
484 482
483 if (clk_on_imx6ull())
484 clk_prepare_enable(clks[IMX6UL_CLK_AIPSTZ3]);
485
485 if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { 486 if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
486 clk_prepare_enable(clks[IMX6UL_CLK_USBPHY1_GATE]); 487 clk_prepare_enable(clks[IMX6UL_CLK_USBPHY1_GATE]);
487 clk_prepare_enable(clks[IMX6UL_CLK_USBPHY2_GATE]); 488 clk_prepare_enable(clks[IMX6UL_CLK_USBPHY2_GATE]);
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index ae1d31be906e..562055129ed8 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -386,7 +386,7 @@ static int const clks_init_on[] __initconst = {
386 IMX7D_PLL_SYS_MAIN_480M_CLK, IMX7D_NAND_USDHC_BUS_ROOT_CLK, 386 IMX7D_PLL_SYS_MAIN_480M_CLK, IMX7D_NAND_USDHC_BUS_ROOT_CLK,
387 IMX7D_DRAM_PHYM_ROOT_CLK, IMX7D_DRAM_ROOT_CLK, 387 IMX7D_DRAM_PHYM_ROOT_CLK, IMX7D_DRAM_ROOT_CLK,
388 IMX7D_DRAM_PHYM_ALT_ROOT_CLK, IMX7D_DRAM_ALT_ROOT_CLK, 388 IMX7D_DRAM_PHYM_ALT_ROOT_CLK, IMX7D_DRAM_ALT_ROOT_CLK,
389 IMX7D_AHB_CHANNEL_ROOT_CLK, 389 IMX7D_AHB_CHANNEL_ROOT_CLK, IMX7D_IPG_ROOT_CLK,
390}; 390};
391 391
392static struct clk_onecell_data clk_data; 392static struct clk_onecell_data clk_data;
@@ -725,7 +725,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
725 clks[IMX7D_DISP_AXI_ROOT_DIV] = imx_clk_divider2("disp_axi_post_div", "disp_axi_pre_div", base + 0x8880, 0, 6); 725 clks[IMX7D_DISP_AXI_ROOT_DIV] = imx_clk_divider2("disp_axi_post_div", "disp_axi_pre_div", base + 0x8880, 0, 6);
726 clks[IMX7D_ENET_AXI_ROOT_DIV] = imx_clk_divider2("enet_axi_post_div", "enet_axi_pre_div", base + 0x8900, 0, 6); 726 clks[IMX7D_ENET_AXI_ROOT_DIV] = imx_clk_divider2("enet_axi_post_div", "enet_axi_pre_div", base + 0x8900, 0, 6);
727 clks[IMX7D_NAND_USDHC_BUS_ROOT_DIV] = imx_clk_divider2("nand_usdhc_post_div", "nand_usdhc_pre_div", base + 0x8980, 0, 6); 727 clks[IMX7D_NAND_USDHC_BUS_ROOT_DIV] = imx_clk_divider2("nand_usdhc_post_div", "nand_usdhc_pre_div", base + 0x8980, 0, 6);
728 clks[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_divider2("ahb_post_div", "ahb_pre_div", base + 0x9000, 0, 6); 728 clks[IMX7D_AHB_CHANNEL_ROOT_DIV] = imx_clk_divider2("ahb_root_clk", "ahb_pre_div", base + 0x9000, 0, 6);
729 clks[IMX7D_IPG_ROOT_CLK] = imx_clk_divider2("ipg_root_clk", "ahb_root_clk", base + 0x9080, 0, 2);
729 clks[IMX7D_DRAM_ROOT_DIV] = imx_clk_divider2("dram_post_div", "dram_cg", base + 0x9880, 0, 3); 730 clks[IMX7D_DRAM_ROOT_DIV] = imx_clk_divider2("dram_post_div", "dram_cg", base + 0x9880, 0, 3);
730 clks[IMX7D_DRAM_PHYM_ALT_ROOT_DIV] = imx_clk_divider2("dram_phym_alt_post_div", "dram_phym_alt_pre_div", base + 0xa000, 0, 3); 731 clks[IMX7D_DRAM_PHYM_ALT_ROOT_DIV] = imx_clk_divider2("dram_phym_alt_post_div", "dram_phym_alt_pre_div", base + 0xa000, 0, 3);
731 clks[IMX7D_DRAM_ALT_ROOT_DIV] = imx_clk_divider2("dram_alt_post_div", "dram_alt_pre_div", base + 0xa080, 0, 3); 732 clks[IMX7D_DRAM_ALT_ROOT_DIV] = imx_clk_divider2("dram_alt_post_div", "dram_alt_pre_div", base + 0xa080, 0, 3);
@@ -796,9 +797,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
796 clks[IMX7D_DISP_AXI_ROOT_CLK] = imx_clk_gate4("disp_axi_root_clk", "disp_axi_post_div", base + 0x4050, 0); 797 clks[IMX7D_DISP_AXI_ROOT_CLK] = imx_clk_gate4("disp_axi_root_clk", "disp_axi_post_div", base + 0x4050, 0);
797 clks[IMX7D_ENET_AXI_ROOT_CLK] = imx_clk_gate4("enet_axi_root_clk", "enet_axi_post_div", base + 0x4060, 0); 798 clks[IMX7D_ENET_AXI_ROOT_CLK] = imx_clk_gate4("enet_axi_root_clk", "enet_axi_post_div", base + 0x4060, 0);
798 clks[IMX7D_OCRAM_CLK] = imx_clk_gate4("ocram_clk", "axi_post_div", base + 0x4110, 0); 799 clks[IMX7D_OCRAM_CLK] = imx_clk_gate4("ocram_clk", "axi_post_div", base + 0x4110, 0);
799 clks[IMX7D_OCRAM_S_CLK] = imx_clk_gate4("ocram_s_clk", "ahb_post_div", base + 0x4120, 0); 800 clks[IMX7D_OCRAM_S_CLK] = imx_clk_gate4("ocram_s_clk", "ahb_root_clk", base + 0x4120, 0);
800 clks[IMX7D_NAND_USDHC_BUS_ROOT_CLK] = imx_clk_gate4("nand_usdhc_root_clk", "nand_usdhc_post_div", base + 0x4130, 0); 801 clks[IMX7D_NAND_USDHC_BUS_ROOT_CLK] = imx_clk_gate4("nand_usdhc_root_clk", "nand_usdhc_post_div", base + 0x4130, 0);
801 clks[IMX7D_AHB_CHANNEL_ROOT_CLK] = imx_clk_gate4("ahb_root_clk", "ahb_post_div", base + 0x4200, 0);
802 clks[IMX7D_DRAM_ROOT_CLK] = imx_clk_gate4("dram_root_clk", "dram_post_div", base + 0x4130, 0); 802 clks[IMX7D_DRAM_ROOT_CLK] = imx_clk_gate4("dram_root_clk", "dram_post_div", base + 0x4130, 0);
803 clks[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_gate4("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0); 803 clks[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_gate4("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0);
804 clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate4("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0); 804 clks[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_gate4("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0);
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 349583405b7c..83b6d9d65aa1 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -2,6 +2,6 @@
2# Makefile for Meson specific clk 2# Makefile for Meson specific clk
3# 3#
4 4
5obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o 5obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o
6obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o 6obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
7obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o 7obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
diff --git a/drivers/clk/meson/clk-audio-divider.c b/drivers/clk/meson/clk-audio-divider.c
new file mode 100644
index 000000000000..6c07db06642d
--- /dev/null
+++ b/drivers/clk/meson/clk-audio-divider.c
@@ -0,0 +1,144 @@
1/*
2 * Copyright (c) 2017 AmLogic, Inc.
3 * Author: Jerome Brunet <jbrunet@baylibre.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18/*
19 * i2s master clock divider: The algorithm of the generic clk-divider used with
20 * a very precise clock parent such as the mpll tends to select a low divider
21 * factor. This gives poor results with this particular divider, especially with
22 * high frequencies (> 100 MHz)
23 *
24 * This driver try to select the maximum possible divider with the rate the
25 * upstream clock can provide.
26 */
27
28#include <linux/clk-provider.h>
29#include "clkc.h"
30
31#define to_meson_clk_audio_divider(_hw) container_of(_hw, \
32 struct meson_clk_audio_divider, hw)
33
34static int _div_round(unsigned long parent_rate, unsigned long rate,
35 unsigned long flags)
36{
37 if (flags & CLK_DIVIDER_ROUND_CLOSEST)
38 return DIV_ROUND_CLOSEST_ULL((u64)parent_rate, rate);
39
40 return DIV_ROUND_UP_ULL((u64)parent_rate, rate);
41}
42
43static int _get_val(unsigned long parent_rate, unsigned long rate)
44{
45 return DIV_ROUND_UP_ULL((u64)parent_rate, rate) - 1;
46}
47
48static int _valid_divider(struct clk_hw *hw, int divider)
49{
50 struct meson_clk_audio_divider *adiv =
51 to_meson_clk_audio_divider(hw);
52 int max_divider;
53 u8 width;
54
55 width = adiv->div.width;
56 max_divider = 1 << width;
57
58 return clamp(divider, 1, max_divider);
59}
60
61static unsigned long audio_divider_recalc_rate(struct clk_hw *hw,
62 unsigned long parent_rate)
63{
64 struct meson_clk_audio_divider *adiv =
65 to_meson_clk_audio_divider(hw);
66 struct parm *p;
67 unsigned long reg, divider;
68
69 p = &adiv->div;
70 reg = readl(adiv->base + p->reg_off);
71 divider = PARM_GET(p->width, p->shift, reg) + 1;
72
73 return DIV_ROUND_UP_ULL((u64)parent_rate, divider);
74}
75
76static long audio_divider_round_rate(struct clk_hw *hw,
77 unsigned long rate,
78 unsigned long *parent_rate)
79{
80 struct meson_clk_audio_divider *adiv =
81 to_meson_clk_audio_divider(hw);
82 unsigned long max_prate;
83 int divider;
84
85 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
86 divider = _div_round(*parent_rate, rate, adiv->flags);
87 divider = _valid_divider(hw, divider);
88 return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
89 }
90
91 /* Get the maximum parent rate */
92 max_prate = clk_hw_round_rate(clk_hw_get_parent(hw), ULONG_MAX);
93
94 /* Get the corresponding rounded down divider */
95 divider = max_prate / rate;
96 divider = _valid_divider(hw, divider);
97
98 /* Get actual rate of the parent */
99 *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
100 divider * rate);
101
102 return DIV_ROUND_UP_ULL((u64)*parent_rate, divider);
103}
104
105static int audio_divider_set_rate(struct clk_hw *hw,
106 unsigned long rate,
107 unsigned long parent_rate)
108{
109 struct meson_clk_audio_divider *adiv =
110 to_meson_clk_audio_divider(hw);
111 struct parm *p;
112 unsigned long reg, flags = 0;
113 int val;
114
115 val = _get_val(parent_rate, rate);
116
117 if (adiv->lock)
118 spin_lock_irqsave(adiv->lock, flags);
119 else
120 __acquire(adiv->lock);
121
122 p = &adiv->div;
123 reg = readl(adiv->base + p->reg_off);
124 reg = PARM_SET(p->width, p->shift, reg, val);
125 writel(reg, adiv->base + p->reg_off);
126
127 if (adiv->lock)
128 spin_unlock_irqrestore(adiv->lock, flags);
129 else
130 __release(adiv->lock);
131
132 return 0;
133}
134
135const struct clk_ops meson_clk_audio_divider_ro_ops = {
136 .recalc_rate = audio_divider_recalc_rate,
137 .round_rate = audio_divider_round_rate,
138};
139
140const struct clk_ops meson_clk_audio_divider_ops = {
141 .recalc_rate = audio_divider_recalc_rate,
142 .round_rate = audio_divider_round_rate,
143 .set_rate = audio_divider_set_rate,
144};
diff --git a/drivers/clk/meson/clk-mpll.c b/drivers/clk/meson/clk-mpll.c
index 03af79005ddb..39eab69fe51a 100644
--- a/drivers/clk/meson/clk-mpll.c
+++ b/drivers/clk/meson/clk-mpll.c
@@ -64,17 +64,51 @@
64#include <linux/clk-provider.h> 64#include <linux/clk-provider.h>
65#include "clkc.h" 65#include "clkc.h"
66 66
67#define SDM_MAX 16384 67#define SDM_DEN 16384
68#define N2_MIN 4
69#define N2_MAX 511
68 70
69#define to_meson_clk_mpll(_hw) container_of(_hw, struct meson_clk_mpll, hw) 71#define to_meson_clk_mpll(_hw) container_of(_hw, struct meson_clk_mpll, hw)
70 72
73static long rate_from_params(unsigned long parent_rate,
74 unsigned long sdm,
75 unsigned long n2)
76{
77 unsigned long divisor = (SDM_DEN * n2) + sdm;
78
79 if (n2 < N2_MIN)
80 return -EINVAL;
81
82 return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
83}
84
85static void params_from_rate(unsigned long requested_rate,
86 unsigned long parent_rate,
87 unsigned long *sdm,
88 unsigned long *n2)
89{
90 uint64_t div = parent_rate;
91 unsigned long rem = do_div(div, requested_rate);
92
93 if (div < N2_MIN) {
94 *n2 = N2_MIN;
95 *sdm = 0;
96 } else if (div > N2_MAX) {
97 *n2 = N2_MAX;
98 *sdm = SDM_DEN - 1;
99 } else {
100 *n2 = div;
101 *sdm = DIV_ROUND_UP(rem * SDM_DEN, requested_rate);
102 }
103}
104
71static unsigned long mpll_recalc_rate(struct clk_hw *hw, 105static unsigned long mpll_recalc_rate(struct clk_hw *hw,
72 unsigned long parent_rate) 106 unsigned long parent_rate)
73{ 107{
74 struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw); 108 struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw);
75 struct parm *p; 109 struct parm *p;
76 unsigned long rate = 0;
77 unsigned long reg, sdm, n2; 110 unsigned long reg, sdm, n2;
111 long rate;
78 112
79 p = &mpll->sdm; 113 p = &mpll->sdm;
80 reg = readl(mpll->base + p->reg_off); 114 reg = readl(mpll->base + p->reg_off);
@@ -84,11 +118,123 @@ static unsigned long mpll_recalc_rate(struct clk_hw *hw,
84 reg = readl(mpll->base + p->reg_off); 118 reg = readl(mpll->base + p->reg_off);
85 n2 = PARM_GET(p->width, p->shift, reg); 119 n2 = PARM_GET(p->width, p->shift, reg);
86 120
87 rate = (parent_rate * SDM_MAX) / ((SDM_MAX * n2) + sdm); 121 rate = rate_from_params(parent_rate, sdm, n2);
122 if (rate < 0)
123 return 0;
88 124
89 return rate; 125 return rate;
90} 126}
91 127
128static long mpll_round_rate(struct clk_hw *hw,
129 unsigned long rate,
130 unsigned long *parent_rate)
131{
132 unsigned long sdm, n2;
133
134 params_from_rate(rate, *parent_rate, &sdm, &n2);
135 return rate_from_params(*parent_rate, sdm, n2);
136}
137
138static int mpll_set_rate(struct clk_hw *hw,
139 unsigned long rate,
140 unsigned long parent_rate)
141{
142 struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw);
143 struct parm *p;
144 unsigned long reg, sdm, n2;
145 unsigned long flags = 0;
146
147 params_from_rate(rate, parent_rate, &sdm, &n2);
148
149 if (mpll->lock)
150 spin_lock_irqsave(mpll->lock, flags);
151 else
152 __acquire(mpll->lock);
153
154 p = &mpll->sdm;
155 reg = readl(mpll->base + p->reg_off);
156 reg = PARM_SET(p->width, p->shift, reg, sdm);
157 writel(reg, mpll->base + p->reg_off);
158
159 p = &mpll->sdm_en;
160 reg = readl(mpll->base + p->reg_off);
161 reg = PARM_SET(p->width, p->shift, reg, 1);
162 writel(reg, mpll->base + p->reg_off);
163
164 p = &mpll->n2;
165 reg = readl(mpll->base + p->reg_off);
166 reg = PARM_SET(p->width, p->shift, reg, n2);
167 writel(reg, mpll->base + p->reg_off);
168
169 if (mpll->lock)
170 spin_unlock_irqrestore(mpll->lock, flags);
171 else
172 __release(mpll->lock);
173
174 return 0;
175}
176
177static void mpll_enable_core(struct clk_hw *hw, int enable)
178{
179 struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw);
180 struct parm *p;
181 unsigned long reg;
182 unsigned long flags = 0;
183
184 if (mpll->lock)
185 spin_lock_irqsave(mpll->lock, flags);
186 else
187 __acquire(mpll->lock);
188
189 p = &mpll->en;
190 reg = readl(mpll->base + p->reg_off);
191 reg = PARM_SET(p->width, p->shift, reg, enable ? 1 : 0);
192 writel(reg, mpll->base + p->reg_off);
193
194 if (mpll->lock)
195 spin_unlock_irqrestore(mpll->lock, flags);
196 else
197 __release(mpll->lock);
198}
199
200
201static int mpll_enable(struct clk_hw *hw)
202{
203 mpll_enable_core(hw, 1);
204
205 return 0;
206}
207
208static void mpll_disable(struct clk_hw *hw)
209{
210 mpll_enable_core(hw, 0);
211}
212
213static int mpll_is_enabled(struct clk_hw *hw)
214{
215 struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw);
216 struct parm *p;
217 unsigned long reg;
218 int en;
219
220 p = &mpll->en;
221 reg = readl(mpll->base + p->reg_off);
222 en = PARM_GET(p->width, p->shift, reg);
223
224 return en;
225}
226
92const struct clk_ops meson_clk_mpll_ro_ops = { 227const struct clk_ops meson_clk_mpll_ro_ops = {
93 .recalc_rate = mpll_recalc_rate, 228 .recalc_rate = mpll_recalc_rate,
229 .round_rate = mpll_round_rate,
230 .is_enabled = mpll_is_enabled,
231};
232
233const struct clk_ops meson_clk_mpll_ops = {
234 .recalc_rate = mpll_recalc_rate,
235 .round_rate = mpll_round_rate,
236 .set_rate = mpll_set_rate,
237 .enable = mpll_enable,
238 .disable = mpll_disable,
239 .is_enabled = mpll_is_enabled,
94}; 240};
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 4adc1e89212c..01341553f50b 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -116,6 +116,30 @@ static const struct pll_rate_table *meson_clk_get_pll_settings(struct meson_clk_
116 return NULL; 116 return NULL;
117} 117}
118 118
119/* Specific wait loop for GXL/GXM GP0 PLL */
120static int meson_clk_pll_wait_lock_reset(struct meson_clk_pll *pll,
121 struct parm *p_n)
122{
123 int delay = 100;
124 u32 reg;
125
126 while (delay > 0) {
127 reg = readl(pll->base + p_n->reg_off);
128 writel(reg | MESON_PLL_RESET, pll->base + p_n->reg_off);
129 udelay(10);
130 writel(reg & ~MESON_PLL_RESET, pll->base + p_n->reg_off);
131
132 /* This delay comes from AMLogic tree clk-gp0-gxl driver */
133 mdelay(1);
134
135 reg = readl(pll->base + p_n->reg_off);
136 if (reg & MESON_PLL_LOCK)
137 return 0;
138 delay--;
139 }
140 return -ETIMEDOUT;
141}
142
119static int meson_clk_pll_wait_lock(struct meson_clk_pll *pll, 143static int meson_clk_pll_wait_lock(struct meson_clk_pll *pll,
120 struct parm *p_n) 144 struct parm *p_n)
121{ 145{
@@ -132,6 +156,15 @@ static int meson_clk_pll_wait_lock(struct meson_clk_pll *pll,
132 return -ETIMEDOUT; 156 return -ETIMEDOUT;
133} 157}
134 158
159static void meson_clk_pll_init_params(struct meson_clk_pll *pll)
160{
161 int i;
162
163 for (i = 0 ; i < pll->params.params_count ; ++i)
164 writel(pll->params.params_table[i].value,
165 pll->base + pll->params.params_table[i].reg_off);
166}
167
135static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, 168static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
136 unsigned long parent_rate) 169 unsigned long parent_rate)
137{ 170{
@@ -151,10 +184,16 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
151 if (!rate_set) 184 if (!rate_set)
152 return -EINVAL; 185 return -EINVAL;
153 186
187 /* Initialize the PLL in a clean state if specified */
188 if (pll->params.params_count)
189 meson_clk_pll_init_params(pll);
190
154 /* PLL reset */ 191 /* PLL reset */
155 p = &pll->n; 192 p = &pll->n;
156 reg = readl(pll->base + p->reg_off); 193 reg = readl(pll->base + p->reg_off);
157 writel(reg | MESON_PLL_RESET, pll->base + p->reg_off); 194 /* If no_init_reset is provided, avoid resetting at this point */
195 if (!pll->params.no_init_reset)
196 writel(reg | MESON_PLL_RESET, pll->base + p->reg_off);
158 197
159 reg = PARM_SET(p->width, p->shift, reg, rate_set->n); 198 reg = PARM_SET(p->width, p->shift, reg, rate_set->n);
160 writel(reg, pll->base + p->reg_off); 199 writel(reg, pll->base + p->reg_off);
@@ -184,7 +223,17 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
184 } 223 }
185 224
186 p = &pll->n; 225 p = &pll->n;
187 ret = meson_clk_pll_wait_lock(pll, p); 226 /* If clear_reset_for_lock is provided, remove the reset bit here */
227 if (pll->params.clear_reset_for_lock) {
228 reg = readl(pll->base + p->reg_off);
229 writel(reg & ~MESON_PLL_RESET, pll->base + p->reg_off);
230 }
231
232 /* If reset_lock_loop, use a special loop including resetting */
233 if (pll->params.reset_lock_loop)
234 ret = meson_clk_pll_wait_lock_reset(pll, p);
235 else
236 ret = meson_clk_pll_wait_lock(pll, p);
188 if (ret) { 237 if (ret) {
189 pr_warn("%s: pll did not lock, trying to restore old rate %lu\n", 238 pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
190 __func__, old_rate); 239 __func__, old_rate);
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 9bb70e7a7d6a..d6feafe8bd6c 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -25,7 +25,7 @@
25#define PARM_GET(width, shift, reg) \ 25#define PARM_GET(width, shift, reg) \
26 (((reg) & SETPMASK(width, shift)) >> (shift)) 26 (((reg) & SETPMASK(width, shift)) >> (shift))
27#define PARM_SET(width, shift, reg, val) \ 27#define PARM_SET(width, shift, reg, val) \
28 (((reg) & CLRPMASK(width, shift)) | (val << (shift))) 28 (((reg) & CLRPMASK(width, shift)) | ((val) << (shift)))
29 29
30#define MESON_PARM_APPLICABLE(p) (!!((p)->width)) 30#define MESON_PARM_APPLICABLE(p) (!!((p)->width))
31 31
@@ -62,6 +62,28 @@ struct pll_rate_table {
62 .frac = (_frac), \ 62 .frac = (_frac), \
63 } \ 63 } \
64 64
65struct pll_params_table {
66 unsigned int reg_off;
67 unsigned int value;
68};
69
70#define PLL_PARAM(_reg, _val) \
71 { \
72 .reg_off = (_reg), \
73 .value = (_val), \
74 }
75
76struct pll_setup_params {
77 struct pll_params_table *params_table;
78 unsigned int params_count;
79 /* Workaround for GP0, do not reset before configuring */
80 bool no_init_reset;
81 /* Workaround for GP0, unreset right before checking for lock */
82 bool clear_reset_for_lock;
83 /* Workaround for GXL GP0, reset in the lock checking loop */
84 bool reset_lock_loop;
85};
86
65struct meson_clk_pll { 87struct meson_clk_pll {
66 struct clk_hw hw; 88 struct clk_hw hw;
67 void __iomem *base; 89 void __iomem *base;
@@ -70,6 +92,7 @@ struct meson_clk_pll {
70 struct parm frac; 92 struct parm frac;
71 struct parm od; 93 struct parm od;
72 struct parm od2; 94 struct parm od2;
95 const struct pll_setup_params params;
73 const struct pll_rate_table *rate_table; 96 const struct pll_rate_table *rate_table;
74 unsigned int rate_count; 97 unsigned int rate_count;
75 spinlock_t *lock; 98 spinlock_t *lock;
@@ -92,8 +115,17 @@ struct meson_clk_mpll {
92 struct clk_hw hw; 115 struct clk_hw hw;
93 void __iomem *base; 116 void __iomem *base;
94 struct parm sdm; 117 struct parm sdm;
118 struct parm sdm_en;
95 struct parm n2; 119 struct parm n2;
96 /* FIXME ssen gate control? */ 120 struct parm en;
121 spinlock_t *lock;
122};
123
124struct meson_clk_audio_divider {
125 struct clk_hw hw;
126 void __iomem *base;
127 struct parm div;
128 u8 flags;
97 spinlock_t *lock; 129 spinlock_t *lock;
98}; 130};
99 131
@@ -116,5 +148,8 @@ extern const struct clk_ops meson_clk_pll_ro_ops;
116extern const struct clk_ops meson_clk_pll_ops; 148extern const struct clk_ops meson_clk_pll_ops;
117extern const struct clk_ops meson_clk_cpu_ops; 149extern const struct clk_ops meson_clk_cpu_ops;
118extern const struct clk_ops meson_clk_mpll_ro_ops; 150extern const struct clk_ops meson_clk_mpll_ro_ops;
151extern const struct clk_ops meson_clk_mpll_ops;
152extern const struct clk_ops meson_clk_audio_divider_ro_ops;
153extern const struct clk_ops meson_clk_audio_divider_ops;
119 154
120#endif /* __CLKC_H */ 155#endif /* __CLKC_H */
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 1c1ec137a3cc..ad5f027af1a2 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -20,6 +20,7 @@
20#include <linux/clk.h> 20#include <linux/clk.h>
21#include <linux/clk-provider.h> 21#include <linux/clk-provider.h>
22#include <linux/of_address.h> 22#include <linux/of_address.h>
23#include <linux/of_device.h>
23#include <linux/platform_device.h> 24#include <linux/platform_device.h>
24#include <linux/init.h> 25#include <linux/init.h>
25 26
@@ -120,7 +121,7 @@ static const struct pll_rate_table sys_pll_rate_table[] = {
120 { /* sentinel */ }, 121 { /* sentinel */ },
121}; 122};
122 123
123static const struct pll_rate_table gp0_pll_rate_table[] = { 124static const struct pll_rate_table gxbb_gp0_pll_rate_table[] = {
124 PLL_RATE(96000000, 32, 1, 3), 125 PLL_RATE(96000000, 32, 1, 3),
125 PLL_RATE(99000000, 33, 1, 3), 126 PLL_RATE(99000000, 33, 1, 3),
126 PLL_RATE(102000000, 34, 1, 3), 127 PLL_RATE(102000000, 34, 1, 3),
@@ -248,6 +249,35 @@ static const struct pll_rate_table gp0_pll_rate_table[] = {
248 { /* sentinel */ }, 249 { /* sentinel */ },
249}; 250};
250 251
252static const struct pll_rate_table gxl_gp0_pll_rate_table[] = {
253 PLL_RATE(504000000, 42, 1, 1),
254 PLL_RATE(516000000, 43, 1, 1),
255 PLL_RATE(528000000, 44, 1, 1),
256 PLL_RATE(540000000, 45, 1, 1),
257 PLL_RATE(552000000, 46, 1, 1),
258 PLL_RATE(564000000, 47, 1, 1),
259 PLL_RATE(576000000, 48, 1, 1),
260 PLL_RATE(588000000, 49, 1, 1),
261 PLL_RATE(600000000, 50, 1, 1),
262 PLL_RATE(612000000, 51, 1, 1),
263 PLL_RATE(624000000, 52, 1, 1),
264 PLL_RATE(636000000, 53, 1, 1),
265 PLL_RATE(648000000, 54, 1, 1),
266 PLL_RATE(660000000, 55, 1, 1),
267 PLL_RATE(672000000, 56, 1, 1),
268 PLL_RATE(684000000, 57, 1, 1),
269 PLL_RATE(696000000, 58, 1, 1),
270 PLL_RATE(708000000, 59, 1, 1),
271 PLL_RATE(720000000, 60, 1, 1),
272 PLL_RATE(732000000, 61, 1, 1),
273 PLL_RATE(744000000, 62, 1, 1),
274 PLL_RATE(756000000, 63, 1, 1),
275 PLL_RATE(768000000, 64, 1, 1),
276 PLL_RATE(780000000, 65, 1, 1),
277 PLL_RATE(792000000, 66, 1, 1),
278 { /* sentinel */ },
279};
280
251static const struct clk_div_table cpu_div_table[] = { 281static const struct clk_div_table cpu_div_table[] = {
252 { .val = 1, .div = 1 }, 282 { .val = 1, .div = 1 },
253 { .val = 2, .div = 2 }, 283 { .val = 2, .div = 2 },
@@ -352,6 +382,13 @@ static struct meson_clk_pll gxbb_sys_pll = {
352 }, 382 },
353}; 383};
354 384
385struct pll_params_table gxbb_gp0_params_table[] = {
386 PLL_PARAM(HHI_GP0_PLL_CNTL, 0x6a000228),
387 PLL_PARAM(HHI_GP0_PLL_CNTL2, 0x69c80000),
388 PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a5590c4),
389 PLL_PARAM(HHI_GP0_PLL_CNTL4, 0x0000500d),
390};
391
355static struct meson_clk_pll gxbb_gp0_pll = { 392static struct meson_clk_pll gxbb_gp0_pll = {
356 .m = { 393 .m = {
357 .reg_off = HHI_GP0_PLL_CNTL, 394 .reg_off = HHI_GP0_PLL_CNTL,
@@ -368,8 +405,57 @@ static struct meson_clk_pll gxbb_gp0_pll = {
368 .shift = 16, 405 .shift = 16,
369 .width = 2, 406 .width = 2,
370 }, 407 },
371 .rate_table = gp0_pll_rate_table, 408 .params = {
372 .rate_count = ARRAY_SIZE(gp0_pll_rate_table), 409 .params_table = gxbb_gp0_params_table,
410 .params_count = ARRAY_SIZE(gxbb_gp0_params_table),
411 .no_init_reset = true,
412 .clear_reset_for_lock = true,
413 },
414 .rate_table = gxbb_gp0_pll_rate_table,
415 .rate_count = ARRAY_SIZE(gxbb_gp0_pll_rate_table),
416 .lock = &clk_lock,
417 .hw.init = &(struct clk_init_data){
418 .name = "gp0_pll",
419 .ops = &meson_clk_pll_ops,
420 .parent_names = (const char *[]){ "xtal" },
421 .num_parents = 1,
422 .flags = CLK_GET_RATE_NOCACHE,
423 },
424};
425
426struct pll_params_table gxl_gp0_params_table[] = {
427 PLL_PARAM(HHI_GP0_PLL_CNTL, 0x40010250),
428 PLL_PARAM(HHI_GP0_PLL_CNTL1, 0xc084a000),
429 PLL_PARAM(HHI_GP0_PLL_CNTL2, 0xb75020be),
430 PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a59a288),
431 PLL_PARAM(HHI_GP0_PLL_CNTL4, 0xc000004d),
432 PLL_PARAM(HHI_GP0_PLL_CNTL5, 0x00078000),
433};
434
435static struct meson_clk_pll gxl_gp0_pll = {
436 .m = {
437 .reg_off = HHI_GP0_PLL_CNTL,
438 .shift = 0,
439 .width = 9,
440 },
441 .n = {
442 .reg_off = HHI_GP0_PLL_CNTL,
443 .shift = 9,
444 .width = 5,
445 },
446 .od = {
447 .reg_off = HHI_GP0_PLL_CNTL,
448 .shift = 16,
449 .width = 2,
450 },
451 .params = {
452 .params_table = gxl_gp0_params_table,
453 .params_count = ARRAY_SIZE(gxl_gp0_params_table),
454 .no_init_reset = true,
455 .reset_lock_loop = true,
456 },
457 .rate_table = gxl_gp0_pll_rate_table,
458 .rate_count = ARRAY_SIZE(gxl_gp0_pll_rate_table),
373 .lock = &clk_lock, 459 .lock = &clk_lock,
374 .hw.init = &(struct clk_init_data){ 460 .hw.init = &(struct clk_init_data){
375 .name = "gp0_pll", 461 .name = "gp0_pll",
@@ -441,15 +527,25 @@ static struct meson_clk_mpll gxbb_mpll0 = {
441 .shift = 0, 527 .shift = 0,
442 .width = 14, 528 .width = 14,
443 }, 529 },
530 .sdm_en = {
531 .reg_off = HHI_MPLL_CNTL7,
532 .shift = 15,
533 .width = 1,
534 },
444 .n2 = { 535 .n2 = {
445 .reg_off = HHI_MPLL_CNTL7, 536 .reg_off = HHI_MPLL_CNTL7,
446 .shift = 16, 537 .shift = 16,
447 .width = 9, 538 .width = 9,
448 }, 539 },
540 .en = {
541 .reg_off = HHI_MPLL_CNTL7,
542 .shift = 14,
543 .width = 1,
544 },
449 .lock = &clk_lock, 545 .lock = &clk_lock,
450 .hw.init = &(struct clk_init_data){ 546 .hw.init = &(struct clk_init_data){
451 .name = "mpll0", 547 .name = "mpll0",
452 .ops = &meson_clk_mpll_ro_ops, 548 .ops = &meson_clk_mpll_ops,
453 .parent_names = (const char *[]){ "fixed_pll" }, 549 .parent_names = (const char *[]){ "fixed_pll" },
454 .num_parents = 1, 550 .num_parents = 1,
455 }, 551 },
@@ -461,15 +557,25 @@ static struct meson_clk_mpll gxbb_mpll1 = {
461 .shift = 0, 557 .shift = 0,
462 .width = 14, 558 .width = 14,
463 }, 559 },
560 .sdm_en = {
561 .reg_off = HHI_MPLL_CNTL8,
562 .shift = 15,
563 .width = 1,
564 },
464 .n2 = { 565 .n2 = {
465 .reg_off = HHI_MPLL_CNTL8, 566 .reg_off = HHI_MPLL_CNTL8,
466 .shift = 16, 567 .shift = 16,
467 .width = 9, 568 .width = 9,
468 }, 569 },
570 .en = {
571 .reg_off = HHI_MPLL_CNTL8,
572 .shift = 14,
573 .width = 1,
574 },
469 .lock = &clk_lock, 575 .lock = &clk_lock,
470 .hw.init = &(struct clk_init_data){ 576 .hw.init = &(struct clk_init_data){
471 .name = "mpll1", 577 .name = "mpll1",
472 .ops = &meson_clk_mpll_ro_ops, 578 .ops = &meson_clk_mpll_ops,
473 .parent_names = (const char *[]){ "fixed_pll" }, 579 .parent_names = (const char *[]){ "fixed_pll" },
474 .num_parents = 1, 580 .num_parents = 1,
475 }, 581 },
@@ -481,15 +587,25 @@ static struct meson_clk_mpll gxbb_mpll2 = {
481 .shift = 0, 587 .shift = 0,
482 .width = 14, 588 .width = 14,
483 }, 589 },
590 .sdm_en = {
591 .reg_off = HHI_MPLL_CNTL9,
592 .shift = 15,
593 .width = 1,
594 },
484 .n2 = { 595 .n2 = {
485 .reg_off = HHI_MPLL_CNTL9, 596 .reg_off = HHI_MPLL_CNTL9,
486 .shift = 16, 597 .shift = 16,
487 .width = 9, 598 .width = 9,
488 }, 599 },
600 .en = {
601 .reg_off = HHI_MPLL_CNTL9,
602 .shift = 14,
603 .width = 1,
604 },
489 .lock = &clk_lock, 605 .lock = &clk_lock,
490 .hw.init = &(struct clk_init_data){ 606 .hw.init = &(struct clk_init_data){
491 .name = "mpll2", 607 .name = "mpll2",
492 .ops = &meson_clk_mpll_ro_ops, 608 .ops = &meson_clk_mpll_ops,
493 .parent_names = (const char *[]){ "fixed_pll" }, 609 .parent_names = (const char *[]){ "fixed_pll" },
494 .num_parents = 1, 610 .num_parents = 1,
495 }, 611 },
@@ -604,6 +720,237 @@ static struct clk_gate gxbb_sar_adc_clk = {
604 }, 720 },
605}; 721};
606 722
723/*
724 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
725 * muxed by a glitch-free switch.
726 */
727
728static u32 mux_table_mali_0_1[] = {0, 1, 2, 3, 4, 5, 6, 7};
729static const char *gxbb_mali_0_1_parent_names[] = {
730 "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
731 "fclk_div4", "fclk_div3", "fclk_div5"
732};
733
734static struct clk_mux gxbb_mali_0_sel = {
735 .reg = (void *)HHI_MALI_CLK_CNTL,
736 .mask = 0x7,
737 .shift = 9,
738 .table = mux_table_mali_0_1,
739 .lock = &clk_lock,
740 .hw.init = &(struct clk_init_data){
741 .name = "mali_0_sel",
742 .ops = &clk_mux_ops,
743 /*
744 * bits 10:9 selects from 8 possible parents:
745 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
746 * fclk_div4, fclk_div3, fclk_div5
747 */
748 .parent_names = gxbb_mali_0_1_parent_names,
749 .num_parents = 8,
750 .flags = CLK_SET_RATE_NO_REPARENT,
751 },
752};
753
754static struct clk_divider gxbb_mali_0_div = {
755 .reg = (void *)HHI_MALI_CLK_CNTL,
756 .shift = 0,
757 .width = 7,
758 .lock = &clk_lock,
759 .hw.init = &(struct clk_init_data){
760 .name = "mali_0_div",
761 .ops = &clk_divider_ops,
762 .parent_names = (const char *[]){ "mali_0_sel" },
763 .num_parents = 1,
764 .flags = CLK_SET_RATE_NO_REPARENT,
765 },
766};
767
768static struct clk_gate gxbb_mali_0 = {
769 .reg = (void *)HHI_MALI_CLK_CNTL,
770 .bit_idx = 8,
771 .lock = &clk_lock,
772 .hw.init = &(struct clk_init_data){
773 .name = "mali_0",
774 .ops = &clk_gate_ops,
775 .parent_names = (const char *[]){ "mali_0_div" },
776 .num_parents = 1,
777 .flags = CLK_SET_RATE_PARENT,
778 },
779};
780
781static struct clk_mux gxbb_mali_1_sel = {
782 .reg = (void *)HHI_MALI_CLK_CNTL,
783 .mask = 0x7,
784 .shift = 25,
785 .table = mux_table_mali_0_1,
786 .lock = &clk_lock,
787 .hw.init = &(struct clk_init_data){
788 .name = "mali_1_sel",
789 .ops = &clk_mux_ops,
790 /*
791 * bits 10:9 selects from 8 possible parents:
792 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
793 * fclk_div4, fclk_div3, fclk_div5
794 */
795 .parent_names = gxbb_mali_0_1_parent_names,
796 .num_parents = 8,
797 .flags = CLK_SET_RATE_NO_REPARENT,
798 },
799};
800
801static struct clk_divider gxbb_mali_1_div = {
802 .reg = (void *)HHI_MALI_CLK_CNTL,
803 .shift = 16,
804 .width = 7,
805 .lock = &clk_lock,
806 .hw.init = &(struct clk_init_data){
807 .name = "mali_1_div",
808 .ops = &clk_divider_ops,
809 .parent_names = (const char *[]){ "mali_1_sel" },
810 .num_parents = 1,
811 .flags = CLK_SET_RATE_NO_REPARENT,
812 },
813};
814
815static struct clk_gate gxbb_mali_1 = {
816 .reg = (void *)HHI_MALI_CLK_CNTL,
817 .bit_idx = 24,
818 .lock = &clk_lock,
819 .hw.init = &(struct clk_init_data){
820 .name = "mali_1",
821 .ops = &clk_gate_ops,
822 .parent_names = (const char *[]){ "mali_1_div" },
823 .num_parents = 1,
824 .flags = CLK_SET_RATE_PARENT,
825 },
826};
827
828static u32 mux_table_mali[] = {0, 1};
829static const char *gxbb_mali_parent_names[] = {
830 "mali_0", "mali_1"
831};
832
833static struct clk_mux gxbb_mali = {
834 .reg = (void *)HHI_MALI_CLK_CNTL,
835 .mask = 1,
836 .shift = 31,
837 .table = mux_table_mali,
838 .lock = &clk_lock,
839 .hw.init = &(struct clk_init_data){
840 .name = "mali",
841 .ops = &clk_mux_ops,
842 .parent_names = gxbb_mali_parent_names,
843 .num_parents = 2,
844 .flags = CLK_SET_RATE_NO_REPARENT,
845 },
846};
847
848static struct clk_mux gxbb_cts_amclk_sel = {
849 .reg = (void *) HHI_AUD_CLK_CNTL,
850 .mask = 0x3,
851 .shift = 9,
852 /* Default parent unknown (register reset value: 0) */
853 .table = (u32[]){ 1, 2, 3 },
854 .lock = &clk_lock,
855 .hw.init = &(struct clk_init_data){
856 .name = "cts_amclk_sel",
857 .ops = &clk_mux_ops,
858 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
859 .num_parents = 3,
860 .flags = CLK_SET_RATE_PARENT,
861 },
862};
863
864static struct meson_clk_audio_divider gxbb_cts_amclk_div = {
865 .div = {
866 .reg_off = HHI_AUD_CLK_CNTL,
867 .shift = 0,
868 .width = 8,
869 },
870 .lock = &clk_lock,
871 .hw.init = &(struct clk_init_data){
872 .name = "cts_amclk_div",
873 .ops = &meson_clk_audio_divider_ops,
874 .parent_names = (const char *[]){ "cts_amclk_sel" },
875 .num_parents = 1,
876 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
877 },
878};
879
880static struct clk_gate gxbb_cts_amclk = {
881 .reg = (void *) HHI_AUD_CLK_CNTL,
882 .bit_idx = 8,
883 .lock = &clk_lock,
884 .hw.init = &(struct clk_init_data){
885 .name = "cts_amclk",
886 .ops = &clk_gate_ops,
887 .parent_names = (const char *[]){ "cts_amclk_div" },
888 .num_parents = 1,
889 .flags = CLK_SET_RATE_PARENT,
890 },
891};
892
893static struct clk_mux gxbb_cts_mclk_i958_sel = {
894 .reg = (void *)HHI_AUD_CLK_CNTL2,
895 .mask = 0x3,
896 .shift = 25,
897 /* Default parent unknown (register reset value: 0) */
898 .table = (u32[]){ 1, 2, 3 },
899 .lock = &clk_lock,
900 .hw.init = &(struct clk_init_data){
901 .name = "cts_mclk_i958_sel",
902 .ops = &clk_mux_ops,
903 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
904 .num_parents = 3,
905 .flags = CLK_SET_RATE_PARENT,
906 },
907};
908
909static struct clk_divider gxbb_cts_mclk_i958_div = {
910 .reg = (void *)HHI_AUD_CLK_CNTL2,
911 .shift = 16,
912 .width = 8,
913 .lock = &clk_lock,
914 .hw.init = &(struct clk_init_data){
915 .name = "cts_mclk_i958_div",
916 .ops = &clk_divider_ops,
917 .parent_names = (const char *[]){ "cts_mclk_i958_sel" },
918 .num_parents = 1,
919 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
920 },
921};
922
923static struct clk_gate gxbb_cts_mclk_i958 = {
924 .reg = (void *)HHI_AUD_CLK_CNTL2,
925 .bit_idx = 24,
926 .lock = &clk_lock,
927 .hw.init = &(struct clk_init_data){
928 .name = "cts_mclk_i958",
929 .ops = &clk_gate_ops,
930 .parent_names = (const char *[]){ "cts_mclk_i958_div" },
931 .num_parents = 1,
932 .flags = CLK_SET_RATE_PARENT,
933 },
934};
935
936static struct clk_mux gxbb_cts_i958 = {
937 .reg = (void *)HHI_AUD_CLK_CNTL2,
938 .mask = 0x1,
939 .shift = 27,
940 .lock = &clk_lock,
941 .hw.init = &(struct clk_init_data){
942 .name = "cts_i958",
943 .ops = &clk_mux_ops,
944 .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" },
945 .num_parents = 2,
946 /*
947 *The parent is specific to origin of the audio data. Let the
948 * consumer choose the appropriate parent
949 */
950 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
951 },
952};
953
607/* Everything Else (EE) domain gates */ 954/* Everything Else (EE) domain gates */
608static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0); 955static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
609static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1); 956static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -797,6 +1144,140 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
797 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw, 1144 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
798 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw, 1145 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
799 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw, 1146 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
1147 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
1148 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
1149 [CLKID_MALI_0] = &gxbb_mali_0.hw,
1150 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
1151 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
1152 [CLKID_MALI_1] = &gxbb_mali_1.hw,
1153 [CLKID_MALI] = &gxbb_mali.hw,
1154 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
1155 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
1156 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
1157 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
1158 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
1159 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
1160 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
1161 },
1162 .num = NR_CLKS,
1163};
1164
1165static struct clk_hw_onecell_data gxl_hw_onecell_data = {
1166 .hws = {
1167 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
1168 [CLKID_CPUCLK] = &gxbb_cpu_clk.hw,
1169 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
1170 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
1171 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
1172 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
1173 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
1174 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
1175 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
1176 [CLKID_GP0_PLL] = &gxl_gp0_pll.hw,
1177 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
1178 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
1179 [CLKID_CLK81] = &gxbb_clk81.hw,
1180 [CLKID_MPLL0] = &gxbb_mpll0.hw,
1181 [CLKID_MPLL1] = &gxbb_mpll1.hw,
1182 [CLKID_MPLL2] = &gxbb_mpll2.hw,
1183 [CLKID_DDR] = &gxbb_ddr.hw,
1184 [CLKID_DOS] = &gxbb_dos.hw,
1185 [CLKID_ISA] = &gxbb_isa.hw,
1186 [CLKID_PL301] = &gxbb_pl301.hw,
1187 [CLKID_PERIPHS] = &gxbb_periphs.hw,
1188 [CLKID_SPICC] = &gxbb_spicc.hw,
1189 [CLKID_I2C] = &gxbb_i2c.hw,
1190 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
1191 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
1192 [CLKID_RNG0] = &gxbb_rng0.hw,
1193 [CLKID_UART0] = &gxbb_uart0.hw,
1194 [CLKID_SDHC] = &gxbb_sdhc.hw,
1195 [CLKID_STREAM] = &gxbb_stream.hw,
1196 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
1197 [CLKID_SDIO] = &gxbb_sdio.hw,
1198 [CLKID_ABUF] = &gxbb_abuf.hw,
1199 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
1200 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
1201 [CLKID_SPI] = &gxbb_spi.hw,
1202 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
1203 [CLKID_ETH] = &gxbb_eth.hw,
1204 [CLKID_DEMUX] = &gxbb_demux.hw,
1205 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
1206 [CLKID_IEC958] = &gxbb_iec958.hw,
1207 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
1208 [CLKID_AMCLK] = &gxbb_amclk.hw,
1209 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
1210 [CLKID_MIXER] = &gxbb_mixer.hw,
1211 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
1212 [CLKID_ADC] = &gxbb_adc.hw,
1213 [CLKID_BLKMV] = &gxbb_blkmv.hw,
1214 [CLKID_AIU] = &gxbb_aiu.hw,
1215 [CLKID_UART1] = &gxbb_uart1.hw,
1216 [CLKID_G2D] = &gxbb_g2d.hw,
1217 [CLKID_USB0] = &gxbb_usb0.hw,
1218 [CLKID_USB1] = &gxbb_usb1.hw,
1219 [CLKID_RESET] = &gxbb_reset.hw,
1220 [CLKID_NAND] = &gxbb_nand.hw,
1221 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
1222 [CLKID_USB] = &gxbb_usb.hw,
1223 [CLKID_VDIN1] = &gxbb_vdin1.hw,
1224 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
1225 [CLKID_EFUSE] = &gxbb_efuse.hw,
1226 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
1227 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
1228 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
1229 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
1230 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
1231 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
1232 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
1233 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
1234 [CLKID_DVIN] = &gxbb_dvin.hw,
1235 [CLKID_UART2] = &gxbb_uart2.hw,
1236 [CLKID_SANA] = &gxbb_sana.hw,
1237 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
1238 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
1239 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
1240 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
1241 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
1242 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
1243 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
1244 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
1245 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
1246 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
1247 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
1248 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
1249 [CLKID_ENC480P] = &gxbb_enc480p.hw,
1250 [CLKID_RNG1] = &gxbb_rng1.hw,
1251 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
1252 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
1253 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
1254 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
1255 [CLKID_EDP] = &gxbb_edp.hw,
1256 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
1257 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
1258 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
1259 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
1260 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
1261 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
1262 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
1263 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
1264 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
1265 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
1266 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
1267 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
1268 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
1269 [CLKID_MALI_0] = &gxbb_mali_0.hw,
1270 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
1271 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
1272 [CLKID_MALI_1] = &gxbb_mali_1.hw,
1273 [CLKID_MALI] = &gxbb_mali.hw,
1274 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
1275 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
1276 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
1277 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
1278 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
1279 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
1280 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
800 }, 1281 },
801 .num = NR_CLKS, 1282 .num = NR_CLKS,
802}; 1283};
@@ -810,13 +1291,20 @@ static struct meson_clk_pll *const gxbb_clk_plls[] = {
810 &gxbb_gp0_pll, 1291 &gxbb_gp0_pll,
811}; 1292};
812 1293
1294static struct meson_clk_pll *const gxl_clk_plls[] = {
1295 &gxbb_fixed_pll,
1296 &gxbb_hdmi_pll,
1297 &gxbb_sys_pll,
1298 &gxl_gp0_pll,
1299};
1300
813static struct meson_clk_mpll *const gxbb_clk_mplls[] = { 1301static struct meson_clk_mpll *const gxbb_clk_mplls[] = {
814 &gxbb_mpll0, 1302 &gxbb_mpll0,
815 &gxbb_mpll1, 1303 &gxbb_mpll1,
816 &gxbb_mpll2, 1304 &gxbb_mpll2,
817}; 1305};
818 1306
819static struct clk_gate *gxbb_clk_gates[] = { 1307static struct clk_gate *const gxbb_clk_gates[] = {
820 &gxbb_clk81, 1308 &gxbb_clk81,
821 &gxbb_ddr, 1309 &gxbb_ddr,
822 &gxbb_dos, 1310 &gxbb_dos,
@@ -900,16 +1388,105 @@ static struct clk_gate *gxbb_clk_gates[] = {
900 &gxbb_emmc_b, 1388 &gxbb_emmc_b,
901 &gxbb_emmc_c, 1389 &gxbb_emmc_c,
902 &gxbb_sar_adc_clk, 1390 &gxbb_sar_adc_clk,
1391 &gxbb_mali_0,
1392 &gxbb_mali_1,
1393 &gxbb_cts_amclk,
1394 &gxbb_cts_mclk_i958,
1395};
1396
1397static struct clk_mux *const gxbb_clk_muxes[] = {
1398 &gxbb_mpeg_clk_sel,
1399 &gxbb_sar_adc_clk_sel,
1400 &gxbb_mali_0_sel,
1401 &gxbb_mali_1_sel,
1402 &gxbb_mali,
1403 &gxbb_cts_amclk_sel,
1404 &gxbb_cts_mclk_i958_sel,
1405 &gxbb_cts_i958,
1406};
1407
1408static struct clk_divider *const gxbb_clk_dividers[] = {
1409 &gxbb_mpeg_clk_div,
1410 &gxbb_sar_adc_clk_div,
1411 &gxbb_mali_0_div,
1412 &gxbb_mali_1_div,
1413 &gxbb_cts_mclk_i958_div,
1414};
1415
1416static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
1417 &gxbb_cts_amclk_div,
1418};
1419
1420struct clkc_data {
1421 struct clk_gate *const *clk_gates;
1422 unsigned int clk_gates_count;
1423 struct meson_clk_mpll *const *clk_mplls;
1424 unsigned int clk_mplls_count;
1425 struct meson_clk_pll *const *clk_plls;
1426 unsigned int clk_plls_count;
1427 struct clk_mux *const *clk_muxes;
1428 unsigned int clk_muxes_count;
1429 struct clk_divider *const *clk_dividers;
1430 unsigned int clk_dividers_count;
1431 struct meson_clk_audio_divider *const *clk_audio_dividers;
1432 unsigned int clk_audio_dividers_count;
1433 struct meson_clk_cpu *cpu_clk;
1434 struct clk_hw_onecell_data *hw_onecell_data;
1435};
1436
1437static const struct clkc_data gxbb_clkc_data = {
1438 .clk_gates = gxbb_clk_gates,
1439 .clk_gates_count = ARRAY_SIZE(gxbb_clk_gates),
1440 .clk_mplls = gxbb_clk_mplls,
1441 .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls),
1442 .clk_plls = gxbb_clk_plls,
1443 .clk_plls_count = ARRAY_SIZE(gxbb_clk_plls),
1444 .clk_muxes = gxbb_clk_muxes,
1445 .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes),
1446 .clk_dividers = gxbb_clk_dividers,
1447 .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
1448 .clk_audio_dividers = gxbb_audio_dividers,
1449 .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
1450 .cpu_clk = &gxbb_cpu_clk,
1451 .hw_onecell_data = &gxbb_hw_onecell_data,
1452};
1453
1454static const struct clkc_data gxl_clkc_data = {
1455 .clk_gates = gxbb_clk_gates,
1456 .clk_gates_count = ARRAY_SIZE(gxbb_clk_gates),
1457 .clk_mplls = gxbb_clk_mplls,
1458 .clk_mplls_count = ARRAY_SIZE(gxbb_clk_mplls),
1459 .clk_plls = gxl_clk_plls,
1460 .clk_plls_count = ARRAY_SIZE(gxl_clk_plls),
1461 .clk_muxes = gxbb_clk_muxes,
1462 .clk_muxes_count = ARRAY_SIZE(gxbb_clk_muxes),
1463 .clk_dividers = gxbb_clk_dividers,
1464 .clk_dividers_count = ARRAY_SIZE(gxbb_clk_dividers),
1465 .clk_audio_dividers = gxbb_audio_dividers,
1466 .clk_audio_dividers_count = ARRAY_SIZE(gxbb_audio_dividers),
1467 .cpu_clk = &gxbb_cpu_clk,
1468 .hw_onecell_data = &gxl_hw_onecell_data,
1469};
1470
1471static const struct of_device_id clkc_match_table[] = {
1472 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
1473 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
1474 {},
903}; 1475};
904 1476
905static int gxbb_clkc_probe(struct platform_device *pdev) 1477static int gxbb_clkc_probe(struct platform_device *pdev)
906{ 1478{
1479 const struct clkc_data *clkc_data;
907 void __iomem *clk_base; 1480 void __iomem *clk_base;
908 int ret, clkid, i; 1481 int ret, clkid, i;
909 struct clk_hw *parent_hw; 1482 struct clk_hw *parent_hw;
910 struct clk *parent_clk; 1483 struct clk *parent_clk;
911 struct device *dev = &pdev->dev; 1484 struct device *dev = &pdev->dev;
912 1485
1486 clkc_data = of_device_get_match_data(&pdev->dev);
1487 if (!clkc_data)
1488 return -EINVAL;
1489
913 /* Generic clocks and PLLs */ 1490 /* Generic clocks and PLLs */
914 clk_base = of_iomap(dev->of_node, 0); 1491 clk_base = of_iomap(dev->of_node, 0);
915 if (!clk_base) { 1492 if (!clk_base) {
@@ -918,34 +1495,45 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
918 } 1495 }
919 1496
920 /* Populate base address for PLLs */ 1497 /* Populate base address for PLLs */
921 for (i = 0; i < ARRAY_SIZE(gxbb_clk_plls); i++) 1498 for (i = 0; i < clkc_data->clk_plls_count; i++)
922 gxbb_clk_plls[i]->base = clk_base; 1499 clkc_data->clk_plls[i]->base = clk_base;
923 1500
924 /* Populate base address for MPLLs */ 1501 /* Populate base address for MPLLs */
925 for (i = 0; i < ARRAY_SIZE(gxbb_clk_mplls); i++) 1502 for (i = 0; i < clkc_data->clk_mplls_count; i++)
926 gxbb_clk_mplls[i]->base = clk_base; 1503 clkc_data->clk_mplls[i]->base = clk_base;
927 1504
928 /* Populate the base address for CPU clk */ 1505 /* Populate the base address for CPU clk */
929 gxbb_cpu_clk.base = clk_base; 1506 clkc_data->cpu_clk->base = clk_base;
1507
1508 /* Populate base address for gates */
1509 for (i = 0; i < clkc_data->clk_gates_count; i++)
1510 clkc_data->clk_gates[i]->reg = clk_base +
1511 (u64)clkc_data->clk_gates[i]->reg;
930 1512
931 /* Populate the base address for the MPEG clks */ 1513 /* Populate base address for muxes */
932 gxbb_mpeg_clk_sel.reg = clk_base + (u64)gxbb_mpeg_clk_sel.reg; 1514 for (i = 0; i < clkc_data->clk_muxes_count; i++)
933 gxbb_mpeg_clk_div.reg = clk_base + (u64)gxbb_mpeg_clk_div.reg; 1515 clkc_data->clk_muxes[i]->reg = clk_base +
1516 (u64)clkc_data->clk_muxes[i]->reg;
934 1517
935 /* Populate the base address for the SAR ADC clks */ 1518 /* Populate base address for dividers */
936 gxbb_sar_adc_clk_sel.reg = clk_base + (u64)gxbb_sar_adc_clk_sel.reg; 1519 for (i = 0; i < clkc_data->clk_dividers_count; i++)
937 gxbb_sar_adc_clk_div.reg = clk_base + (u64)gxbb_sar_adc_clk_div.reg; 1520 clkc_data->clk_dividers[i]->reg = clk_base +
1521 (u64)clkc_data->clk_dividers[i]->reg;
938 1522
939 /* Populate base address for gates */ 1523 /* Populate base address for the audio dividers */
940 for (i = 0; i < ARRAY_SIZE(gxbb_clk_gates); i++) 1524 for (i = 0; i < clkc_data->clk_audio_dividers_count; i++)
941 gxbb_clk_gates[i]->reg = clk_base + 1525 clkc_data->clk_audio_dividers[i]->base = clk_base;
942 (u64)gxbb_clk_gates[i]->reg;
943 1526
944 /* 1527 /*
945 * register all clks 1528 * register all clks
946 */ 1529 */
947 for (clkid = 0; clkid < NR_CLKS; clkid++) { 1530 for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) {
948 ret = devm_clk_hw_register(dev, gxbb_hw_onecell_data.hws[clkid]); 1531 /* array might be sparse */
1532 if (!clkc_data->hw_onecell_data->hws[clkid])
1533 continue;
1534
1535 ret = devm_clk_hw_register(dev,
1536 clkc_data->hw_onecell_data->hws[clkid]);
949 if (ret) 1537 if (ret)
950 goto iounmap; 1538 goto iounmap;
951 } 1539 }
@@ -964,9 +1552,9 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
964 * a new clk_hw, and this hack will no longer work. Releasing the ccr 1552 * a new clk_hw, and this hack will no longer work. Releasing the ccr
965 * feature before that time solves the problem :-) 1553 * feature before that time solves the problem :-)
966 */ 1554 */
967 parent_hw = clk_hw_get_parent(&gxbb_cpu_clk.hw); 1555 parent_hw = clk_hw_get_parent(&clkc_data->cpu_clk->hw);
968 parent_clk = parent_hw->clk; 1556 parent_clk = parent_hw->clk;
969 ret = clk_notifier_register(parent_clk, &gxbb_cpu_clk.clk_nb); 1557 ret = clk_notifier_register(parent_clk, &clkc_data->cpu_clk->clk_nb);
970 if (ret) { 1558 if (ret) {
971 pr_err("%s: failed to register clock notifier for cpu_clk\n", 1559 pr_err("%s: failed to register clock notifier for cpu_clk\n",
972 __func__); 1560 __func__);
@@ -974,23 +1562,18 @@ static int gxbb_clkc_probe(struct platform_device *pdev)
974 } 1562 }
975 1563
976 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, 1564 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
977 &gxbb_hw_onecell_data); 1565 clkc_data->hw_onecell_data);
978 1566
979iounmap: 1567iounmap:
980 iounmap(clk_base); 1568 iounmap(clk_base);
981 return ret; 1569 return ret;
982} 1570}
983 1571
984static const struct of_device_id gxbb_clkc_match_table[] = {
985 { .compatible = "amlogic,gxbb-clkc" },
986 { }
987};
988
989static struct platform_driver gxbb_driver = { 1572static struct platform_driver gxbb_driver = {
990 .probe = gxbb_clkc_probe, 1573 .probe = gxbb_clkc_probe,
991 .driver = { 1574 .driver = {
992 .name = "gxbb-clkc", 1575 .name = "gxbb-clkc",
993 .of_match_table = gxbb_clkc_match_table, 1576 .of_match_table = clkc_match_table,
994 }, 1577 },
995}; 1578};
996 1579
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 8ee2022ce5d5..1d8d13f5e813 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -71,6 +71,8 @@
71#define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */ 71#define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
72#define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */ 72#define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
73#define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */ 73#define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */
74#define HHI_GP0_PLL_CNTL5 0x50 /* 0x14 offset in data sheet */
75#define HHI_GP0_PLL_CNTL1 0x58 /* 0x16 offset in data sheet */
74 76
75#define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */ 77#define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */
76#define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */ 78#define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */
@@ -177,7 +179,7 @@
177/* CLKID_FCLK_DIV4 */ 179/* CLKID_FCLK_DIV4 */
178#define CLKID_FCLK_DIV5 7 180#define CLKID_FCLK_DIV5 7
179#define CLKID_FCLK_DIV7 8 181#define CLKID_FCLK_DIV7 8
180#define CLKID_GP0_PLL 9 182/* CLKID_GP0_PLL */
181#define CLKID_MPEG_SEL 10 183#define CLKID_MPEG_SEL 10
182#define CLKID_MPEG_DIV 11 184#define CLKID_MPEG_DIV 11
183/* CLKID_CLK81 */ 185/* CLKID_CLK81 */
@@ -206,16 +208,16 @@
206#define CLKID_I2S_SPDIF 35 208#define CLKID_I2S_SPDIF 35
207/* CLKID_ETH */ 209/* CLKID_ETH */
208#define CLKID_DEMUX 37 210#define CLKID_DEMUX 37
209#define CLKID_AIU_GLUE 38 211/* CLKID_AIU_GLUE */
210#define CLKID_IEC958 39 212#define CLKID_IEC958 39
211#define CLKID_I2S_OUT 40 213/* CLKID_I2S_OUT */
212#define CLKID_AMCLK 41 214#define CLKID_AMCLK 41
213#define CLKID_AIFIFO2 42 215#define CLKID_AIFIFO2 42
214#define CLKID_MIXER 43 216#define CLKID_MIXER 43
215#define CLKID_MIXER_IFACE 44 217/* CLKID_MIXER_IFACE */
216#define CLKID_ADC 45 218#define CLKID_ADC 45
217#define CLKID_BLKMV 46 219#define CLKID_BLKMV 46
218#define CLKID_AIU 47 220/* CLKID_AIU */
219#define CLKID_UART1 48 221#define CLKID_UART1 48
220#define CLKID_G2D 49 222#define CLKID_G2D 49
221/* CLKID_USB0 */ 223/* CLKID_USB0 */
@@ -248,7 +250,7 @@
248/* CLKID_GCLK_VENCI_INT0 */ 250/* CLKID_GCLK_VENCI_INT0 */
249#define CLKID_GCLK_VENCI_INT 78 251#define CLKID_GCLK_VENCI_INT 78
250#define CLKID_DAC_CLK 79 252#define CLKID_DAC_CLK 79
251#define CLKID_AOCLK_GATE 80 253/* CLKID_AOCLK_GATE */
252#define CLKID_IEC958_GATE 81 254#define CLKID_IEC958_GATE 81
253#define CLKID_ENC480P 82 255#define CLKID_ENC480P 82
254#define CLKID_RNG1 83 256#define CLKID_RNG1 83
@@ -268,8 +270,22 @@
268/* CLKID_SAR_ADC_CLK */ 270/* CLKID_SAR_ADC_CLK */
269/* CLKID_SAR_ADC_SEL */ 271/* CLKID_SAR_ADC_SEL */
270#define CLKID_SAR_ADC_DIV 99 272#define CLKID_SAR_ADC_DIV 99
273/* CLKID_MALI_0_SEL */
274#define CLKID_MALI_0_DIV 101
275/* CLKID_MALI_0 */
276/* CLKID_MALI_1_SEL */
277#define CLKID_MALI_1_DIV 104
278/* CLKID_MALI_1 */
279/* CLKID_MALI */
280#define CLKID_CTS_AMCLK 107
281#define CLKID_CTS_AMCLK_SEL 108
282#define CLKID_CTS_AMCLK_DIV 109
283#define CLKID_CTS_MCLK_I958 110
284#define CLKID_CTS_MCLK_I958_SEL 111
285#define CLKID_CTS_MCLK_I958_DIV 112
286#define CLKID_CTS_I958 113
271 287
272#define NR_CLKS 100 288#define NR_CLKS 114
273 289
274/* include the CLKIDs that have been made part of the stable DT binding */ 290/* include the CLKIDs that have been made part of the stable DT binding */
275#include <dt-bindings/clock/gxbb-clkc.h> 291#include <dt-bindings/clock/gxbb-clkc.h>
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 888494d4fb8a..e9985503165c 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -245,6 +245,96 @@ static struct clk_fixed_factor meson8b_fclk_div7 = {
245 }, 245 },
246}; 246};
247 247
248static struct meson_clk_mpll meson8b_mpll0 = {
249 .sdm = {
250 .reg_off = HHI_MPLL_CNTL7,
251 .shift = 0,
252 .width = 14,
253 },
254 .sdm_en = {
255 .reg_off = HHI_MPLL_CNTL7,
256 .shift = 15,
257 .width = 1,
258 },
259 .n2 = {
260 .reg_off = HHI_MPLL_CNTL7,
261 .shift = 16,
262 .width = 9,
263 },
264 .en = {
265 .reg_off = HHI_MPLL_CNTL7,
266 .shift = 14,
267 .width = 1,
268 },
269 .lock = &clk_lock,
270 .hw.init = &(struct clk_init_data){
271 .name = "mpll0",
272 .ops = &meson_clk_mpll_ops,
273 .parent_names = (const char *[]){ "fixed_pll" },
274 .num_parents = 1,
275 },
276};
277
278static struct meson_clk_mpll meson8b_mpll1 = {
279 .sdm = {
280 .reg_off = HHI_MPLL_CNTL8,
281 .shift = 0,
282 .width = 14,
283 },
284 .sdm_en = {
285 .reg_off = HHI_MPLL_CNTL8,
286 .shift = 15,
287 .width = 1,
288 },
289 .n2 = {
290 .reg_off = HHI_MPLL_CNTL8,
291 .shift = 16,
292 .width = 9,
293 },
294 .en = {
295 .reg_off = HHI_MPLL_CNTL8,
296 .shift = 14,
297 .width = 1,
298 },
299 .lock = &clk_lock,
300 .hw.init = &(struct clk_init_data){
301 .name = "mpll1",
302 .ops = &meson_clk_mpll_ops,
303 .parent_names = (const char *[]){ "fixed_pll" },
304 .num_parents = 1,
305 },
306};
307
308static struct meson_clk_mpll meson8b_mpll2 = {
309 .sdm = {
310 .reg_off = HHI_MPLL_CNTL9,
311 .shift = 0,
312 .width = 14,
313 },
314 .sdm_en = {
315 .reg_off = HHI_MPLL_CNTL9,
316 .shift = 15,
317 .width = 1,
318 },
319 .n2 = {
320 .reg_off = HHI_MPLL_CNTL9,
321 .shift = 16,
322 .width = 9,
323 },
324 .en = {
325 .reg_off = HHI_MPLL_CNTL9,
326 .shift = 14,
327 .width = 1,
328 },
329 .lock = &clk_lock,
330 .hw.init = &(struct clk_init_data){
331 .name = "mpll2",
332 .ops = &meson_clk_mpll_ops,
333 .parent_names = (const char *[]){ "fixed_pll" },
334 .num_parents = 1,
335 },
336};
337
248/* 338/*
249 * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL 339 * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL
250 * post-dividers and should be modeled with their respective PLLs via the 340 * post-dividers and should be modeled with their respective PLLs via the
@@ -491,6 +581,9 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
491 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw, 581 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
492 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw, 582 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
493 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw, 583 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
584 [CLKID_MPLL0] = &meson8b_mpll0.hw,
585 [CLKID_MPLL1] = &meson8b_mpll1.hw,
586 [CLKID_MPLL2] = &meson8b_mpll2.hw,
494 }, 587 },
495 .num = CLK_NR_CLKS, 588 .num = CLK_NR_CLKS,
496}; 589};
@@ -501,7 +594,13 @@ static struct meson_clk_pll *const meson8b_clk_plls[] = {
501 &meson8b_sys_pll, 594 &meson8b_sys_pll,
502}; 595};
503 596
504static struct clk_gate *meson8b_clk_gates[] = { 597static struct meson_clk_mpll *const meson8b_clk_mplls[] = {
598 &meson8b_mpll0,
599 &meson8b_mpll1,
600 &meson8b_mpll2,
601};
602
603static struct clk_gate *const meson8b_clk_gates[] = {
505 &meson8b_clk81, 604 &meson8b_clk81,
506 &meson8b_ddr, 605 &meson8b_ddr,
507 &meson8b_dos, 606 &meson8b_dos,
@@ -582,6 +681,14 @@ static struct clk_gate *meson8b_clk_gates[] = {
582 &meson8b_ao_iface, 681 &meson8b_ao_iface,
583}; 682};
584 683
684static struct clk_mux *const meson8b_clk_muxes[] = {
685 &meson8b_mpeg_clk_sel,
686};
687
688static struct clk_divider *const meson8b_clk_dividers[] = {
689 &meson8b_mpeg_clk_div,
690};
691
585static int meson8b_clkc_probe(struct platform_device *pdev) 692static int meson8b_clkc_probe(struct platform_device *pdev)
586{ 693{
587 void __iomem *clk_base; 694 void __iomem *clk_base;
@@ -601,18 +708,28 @@ static int meson8b_clkc_probe(struct platform_device *pdev)
601 for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++) 708 for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++)
602 meson8b_clk_plls[i]->base = clk_base; 709 meson8b_clk_plls[i]->base = clk_base;
603 710
711 /* Populate base address for MPLLs */
712 for (i = 0; i < ARRAY_SIZE(meson8b_clk_mplls); i++)
713 meson8b_clk_mplls[i]->base = clk_base;
714
604 /* Populate the base address for CPU clk */ 715 /* Populate the base address for CPU clk */
605 meson8b_cpu_clk.base = clk_base; 716 meson8b_cpu_clk.base = clk_base;
606 717
607 /* Populate the base address for the MPEG clks */
608 meson8b_mpeg_clk_sel.reg = clk_base + (u32)meson8b_mpeg_clk_sel.reg;
609 meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg;
610
611 /* Populate base address for gates */ 718 /* Populate base address for gates */
612 for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++) 719 for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++)
613 meson8b_clk_gates[i]->reg = clk_base + 720 meson8b_clk_gates[i]->reg = clk_base +
614 (u32)meson8b_clk_gates[i]->reg; 721 (u32)meson8b_clk_gates[i]->reg;
615 722
723 /* Populate base address for muxes */
724 for (i = 0; i < ARRAY_SIZE(meson8b_clk_muxes); i++)
725 meson8b_clk_muxes[i]->reg = clk_base +
726 (u32)meson8b_clk_muxes[i]->reg;
727
728 /* Populate base address for dividers */
729 for (i = 0; i < ARRAY_SIZE(meson8b_clk_dividers); i++)
730 meson8b_clk_dividers[i]->reg = clk_base +
731 (u32)meson8b_clk_dividers[i]->reg;
732
616 /* 733 /*
617 * register all clks 734 * register all clks
618 * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1 735 * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index 010e9582888d..3881defc8644 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -42,6 +42,21 @@
42#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ 42#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
43 43
44/* 44/*
45 * MPLL register offeset taken from the S905 datasheet. Vendor kernel source
46 * confirm these are the same for the S805.
47 */
48#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
49#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */
50#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */
51#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */
52#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */
53#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */
54#define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */
55#define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */
56#define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */
57#define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */
58
59/*
45 * CLKID index values 60 * CLKID index values
46 * 61 *
47 * These indices are entirely contrived and do not map onto the hardware. 62 * These indices are entirely contrived and do not map onto the hardware.
@@ -142,8 +157,11 @@
142#define CLKID_AO_AHB_SRAM 90 157#define CLKID_AO_AHB_SRAM 90
143#define CLKID_AO_AHB_BUS 91 158#define CLKID_AO_AHB_BUS 91
144#define CLKID_AO_IFACE 92 159#define CLKID_AO_IFACE 92
160#define CLKID_MPLL0 93
161#define CLKID_MPLL1 94
162#define CLKID_MPLL2 95
145 163
146#define CLK_NR_CLKS 93 164#define CLK_NR_CLKS 96
147 165
148/* include the CLKIDs that have been made part of the stable DT binding */ 166/* include the CLKIDs that have been made part of the stable DT binding */
149#include <dt-bindings/clock/meson8b-clkc.h> 167#include <dt-bindings/clock/meson8b-clkc.h>
diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
index 9b97246287a7..20d8fea32a99 100644
--- a/drivers/clk/qcom/mmcc-msm8996.c
+++ b/drivers/clk/qcom/mmcc-msm8996.c
@@ -2986,7 +2986,7 @@ static struct gdsc vfe1_gdsc = {
2986 .cxcs = (unsigned int []){ 0x36ac }, 2986 .cxcs = (unsigned int []){ 0x36ac },
2987 .cxc_count = 1, 2987 .cxc_count = 1,
2988 .pd = { 2988 .pd = {
2989 .name = "vfe0", 2989 .name = "vfe1",
2990 }, 2990 },
2991 .parent = &camss_gdsc.pd, 2991 .parent = &camss_gdsc.pd,
2992 .pwrsts = PWRSTS_OFF_ON, 2992 .pwrsts = PWRSTS_OFF_ON,
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index bfffdb00df97..eaa98b488f01 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -16,6 +16,7 @@
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/soc/renesas/rcar-rst.h> 18#include <linux/soc/renesas/rcar-rst.h>
19#include <linux/sys_soc.h>
19 20
20#include <dt-bindings/clock/r8a7795-cpg-mssr.h> 21#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
21 22
@@ -24,7 +25,7 @@
24 25
25enum clk_ids { 26enum clk_ids {
26 /* Core Clock Outputs exported to DT */ 27 /* Core Clock Outputs exported to DT */
27 LAST_DT_CORE_CLK = R8A7795_CLK_OSC, 28 LAST_DT_CORE_CLK = R8A7795_CLK_S0D12,
28 29
29 /* External Input Clocks */ 30 /* External Input Clocks */
30 CLK_EXTAL, 31 CLK_EXTAL,
@@ -51,10 +52,10 @@ enum clk_ids {
51 MOD_CLK_BASE 52 MOD_CLK_BASE
52}; 53};
53 54
54static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { 55static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
55 /* External Clock Inputs */ 56 /* External Clock Inputs */
56 DEF_INPUT("extal", CLK_EXTAL), 57 DEF_INPUT("extal", CLK_EXTAL),
57 DEF_INPUT("extalr", CLK_EXTALR), 58 DEF_INPUT("extalr", CLK_EXTALR),
58 59
59 /* Internal Core Clocks */ 60 /* Internal Core Clocks */
60 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 61 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
@@ -78,7 +79,12 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
78 DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), 79 DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
79 DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1), 80 DEF_FIXED("zx", R8A7795_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
80 DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1), 81 DEF_FIXED("s0d1", R8A7795_CLK_S0D1, CLK_S0, 1, 1),
82 DEF_FIXED("s0d2", R8A7795_CLK_S0D2, CLK_S0, 2, 1),
83 DEF_FIXED("s0d3", R8A7795_CLK_S0D3, CLK_S0, 3, 1),
81 DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1), 84 DEF_FIXED("s0d4", R8A7795_CLK_S0D4, CLK_S0, 4, 1),
85 DEF_FIXED("s0d6", R8A7795_CLK_S0D6, CLK_S0, 6, 1),
86 DEF_FIXED("s0d8", R8A7795_CLK_S0D8, CLK_S0, 8, 1),
87 DEF_FIXED("s0d12", R8A7795_CLK_S0D12, CLK_S0, 12, 1),
82 DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1), 88 DEF_FIXED("s1d1", R8A7795_CLK_S1D1, CLK_S1, 1, 1),
83 DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1), 89 DEF_FIXED("s1d2", R8A7795_CLK_S1D2, CLK_S1, 2, 1),
84 DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1), 90 DEF_FIXED("s1d4", R8A7795_CLK_S1D4, CLK_S1, 4, 1),
@@ -89,29 +95,29 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
89 DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1), 95 DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
90 DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1), 96 DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
91 97
92 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x0074), 98 DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074),
93 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x0078), 99 DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078),
94 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x0268), 100 DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
95 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x026c), 101 DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
96 102
97 DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1), 103 DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
98 DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1), 104 DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
99 105
100 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
101 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
102 DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244), 106 DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
103 DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), 107 DEF_DIV6P1("csi0", R8A7795_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
108 DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
109 DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
104 110
105 DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), 111 DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
106 DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), 112 DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
107 113
108 DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), 114 DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
109}; 115};
110 116
111static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = { 117static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
112 DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), 118 DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */
113 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S2D1), 119 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
114 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S2D1), 120 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
115 DEF_MOD("scif5", 202, R8A7795_CLK_S3D4), 121 DEF_MOD("scif5", 202, R8A7795_CLK_S3D4),
116 DEF_MOD("scif4", 203, R8A7795_CLK_S3D4), 122 DEF_MOD("scif4", 203, R8A7795_CLK_S3D4),
117 DEF_MOD("scif3", 204, R8A7795_CLK_S3D4), 123 DEF_MOD("scif3", 204, R8A7795_CLK_S3D4),
@@ -121,9 +127,9 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
121 DEF_MOD("msiof2", 209, R8A7795_CLK_MSO), 127 DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
122 DEF_MOD("msiof1", 210, R8A7795_CLK_MSO), 128 DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
123 DEF_MOD("msiof0", 211, R8A7795_CLK_MSO), 129 DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
124 DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1), 130 DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3),
125 DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1), 131 DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3),
126 DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S3D1), 132 DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
127 DEF_MOD("cmt3", 300, R8A7795_CLK_R), 133 DEF_MOD("cmt3", 300, R8A7795_CLK_R),
128 DEF_MOD("cmt2", 301, R8A7795_CLK_R), 134 DEF_MOD("cmt2", 301, R8A7795_CLK_R),
129 DEF_MOD("cmt1", 302, R8A7795_CLK_R), 135 DEF_MOD("cmt1", 302, R8A7795_CLK_R),
@@ -135,15 +141,15 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
135 DEF_MOD("sdif0", 314, R8A7795_CLK_SD0), 141 DEF_MOD("sdif0", 314, R8A7795_CLK_SD0),
136 DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1), 142 DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
137 DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1), 143 DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
138 DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), 144 DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */
139 DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1), 145 DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
140 DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1), 146 DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
141 DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1), 147 DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
142 DEF_MOD("rwdt0", 402, R8A7795_CLK_R), 148 DEF_MOD("rwdt", 402, R8A7795_CLK_R),
143 DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), 149 DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
144 DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), 150 DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
145 DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4), 151 DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3),
146 DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4), 152 DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3),
147 DEF_MOD("drif7", 508, R8A7795_CLK_S3D2), 153 DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
148 DEF_MOD("drif6", 509, R8A7795_CLK_S3D2), 154 DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
149 DEF_MOD("drif5", 510, R8A7795_CLK_S3D2), 155 DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
@@ -159,35 +165,35 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
159 DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1), 165 DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
160 DEF_MOD("thermal", 522, R8A7795_CLK_CP), 166 DEF_MOD("thermal", 522, R8A7795_CLK_CP),
161 DEF_MOD("pwm", 523, R8A7795_CLK_S3D4), 167 DEF_MOD("pwm", 523, R8A7795_CLK_S3D4),
162 DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), 168 DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1), /* ES1.x */
163 DEF_MOD("fcpvd2", 601, R8A7795_CLK_S2D1), 169 DEF_MOD("fcpvd2", 601, R8A7795_CLK_S0D2),
164 DEF_MOD("fcpvd1", 602, R8A7795_CLK_S2D1), 170 DEF_MOD("fcpvd1", 602, R8A7795_CLK_S0D2),
165 DEF_MOD("fcpvd0", 603, R8A7795_CLK_S2D1), 171 DEF_MOD("fcpvd0", 603, R8A7795_CLK_S0D2),
166 DEF_MOD("fcpvb1", 606, R8A7795_CLK_S2D1), 172 DEF_MOD("fcpvb1", 606, R8A7795_CLK_S0D1),
167 DEF_MOD("fcpvb0", 607, R8A7795_CLK_S2D1), 173 DEF_MOD("fcpvb0", 607, R8A7795_CLK_S0D1),
168 DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), 174 DEF_MOD("fcpvi2", 609, R8A7795_CLK_S2D1), /* ES1.x */
169 DEF_MOD("fcpvi1", 610, R8A7795_CLK_S2D1), 175 DEF_MOD("fcpvi1", 610, R8A7795_CLK_S0D1),
170 DEF_MOD("fcpvi0", 611, R8A7795_CLK_S2D1), 176 DEF_MOD("fcpvi0", 611, R8A7795_CLK_S0D1),
171 DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), 177 DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */
172 DEF_MOD("fcpf1", 614, R8A7795_CLK_S2D1), 178 DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1),
173 DEF_MOD("fcpf0", 615, R8A7795_CLK_S2D1), 179 DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1),
174 DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), 180 DEF_MOD("fcpci1", 616, R8A7795_CLK_S2D1), /* ES1.x */
175 DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), 181 DEF_MOD("fcpci0", 617, R8A7795_CLK_S2D1), /* ES1.x */
176 DEF_MOD("fcpcs", 619, R8A7795_CLK_S2D1), 182 DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1),
177 DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), 183 DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */
178 DEF_MOD("vspd2", 621, R8A7795_CLK_S2D1), 184 DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2),
179 DEF_MOD("vspd1", 622, R8A7795_CLK_S2D1), 185 DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2),
180 DEF_MOD("vspd0", 623, R8A7795_CLK_S2D1), 186 DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2),
181 DEF_MOD("vspbc", 624, R8A7795_CLK_S2D1), 187 DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1),
182 DEF_MOD("vspbd", 626, R8A7795_CLK_S2D1), 188 DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1),
183 DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), 189 DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
184 DEF_MOD("vspi1", 630, R8A7795_CLK_S2D1), 190 DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
185 DEF_MOD("vspi0", 631, R8A7795_CLK_S2D1), 191 DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
186 DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4), 192 DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
187 DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4), 193 DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
188 DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4), 194 DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
189 DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4), 195 DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
190 DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), 196 DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
191 DEF_MOD("csi20", 714, R8A7795_CLK_CSI0), 197 DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
192 DEF_MOD("csi41", 715, R8A7795_CLK_CSI0), 198 DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
193 DEF_MOD("csi40", 716, R8A7795_CLK_CSI0), 199 DEF_MOD("csi40", 716, R8A7795_CLK_CSI0),
@@ -198,16 +204,20 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
198 DEF_MOD("lvds", 727, R8A7795_CLK_S0D4), 204 DEF_MOD("lvds", 727, R8A7795_CLK_S0D4),
199 DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI), 205 DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI),
200 DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI), 206 DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI),
201 DEF_MOD("vin7", 804, R8A7795_CLK_S2D1), 207 DEF_MOD("vin7", 804, R8A7795_CLK_S0D2),
202 DEF_MOD("vin6", 805, R8A7795_CLK_S2D1), 208 DEF_MOD("vin6", 805, R8A7795_CLK_S0D2),
203 DEF_MOD("vin5", 806, R8A7795_CLK_S2D1), 209 DEF_MOD("vin5", 806, R8A7795_CLK_S0D2),
204 DEF_MOD("vin4", 807, R8A7795_CLK_S2D1), 210 DEF_MOD("vin4", 807, R8A7795_CLK_S0D2),
205 DEF_MOD("vin3", 808, R8A7795_CLK_S2D1), 211 DEF_MOD("vin3", 808, R8A7795_CLK_S0D2),
206 DEF_MOD("vin2", 809, R8A7795_CLK_S2D1), 212 DEF_MOD("vin2", 809, R8A7795_CLK_S0D2),
207 DEF_MOD("vin1", 810, R8A7795_CLK_S2D1), 213 DEF_MOD("vin1", 810, R8A7795_CLK_S0D2),
208 DEF_MOD("vin0", 811, R8A7795_CLK_S2D1), 214 DEF_MOD("vin0", 811, R8A7795_CLK_S0D2),
209 DEF_MOD("etheravb", 812, R8A7795_CLK_S3D2), 215 DEF_MOD("etheravb", 812, R8A7795_CLK_S0D6),
210 DEF_MOD("sata0", 815, R8A7795_CLK_S3D2), 216 DEF_MOD("sata0", 815, R8A7795_CLK_S3D2),
217 DEF_MOD("imr3", 820, R8A7795_CLK_S0D2),
218 DEF_MOD("imr2", 821, R8A7795_CLK_S0D2),
219 DEF_MOD("imr1", 822, R8A7795_CLK_S0D2),
220 DEF_MOD("imr0", 823, R8A7795_CLK_S0D2),
211 DEF_MOD("gpio7", 905, R8A7795_CLK_CP), 221 DEF_MOD("gpio7", 905, R8A7795_CLK_CP),
212 DEF_MOD("gpio6", 906, R8A7795_CLK_CP), 222 DEF_MOD("gpio6", 906, R8A7795_CLK_CP),
213 DEF_MOD("gpio5", 907, R8A7795_CLK_CP), 223 DEF_MOD("gpio5", 907, R8A7795_CLK_CP),
@@ -310,6 +320,82 @@ static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = {
310 { 2, 192, 192, }, 320 { 2, 192, 192, },
311}; 321};
312 322
323static const struct soc_device_attribute r8a7795es1[] __initconst = {
324 { .soc_id = "r8a7795", .revision = "ES1.*" },
325 { /* sentinel */ }
326};
327
328
329 /*
330 * Fixups for R-Car H3 ES1.x
331 */
332
333static const unsigned int r8a7795es1_mod_nullify[] __initconst = {
334 MOD_CLK_ID(326), /* USB-DMAC3-0 */
335 MOD_CLK_ID(329), /* USB-DMAC3-1 */
336 MOD_CLK_ID(700), /* EHCI/OHCI3 */
337 MOD_CLK_ID(705), /* HS-USB-IF3 */
338
339};
340
341static const struct mssr_mod_reparent r8a7795es1_mod_reparent[] __initconst = {
342 { MOD_CLK_ID(118), R8A7795_CLK_S2D1 }, /* FDP1-1 */
343 { MOD_CLK_ID(119), R8A7795_CLK_S2D1 }, /* FDP1-0 */
344 { MOD_CLK_ID(217), R8A7795_CLK_S3D1 }, /* SYS-DMAC2 */
345 { MOD_CLK_ID(218), R8A7795_CLK_S3D1 }, /* SYS-DMAC1 */
346 { MOD_CLK_ID(219), R8A7795_CLK_S3D1 }, /* SYS-DMAC0 */
347 { MOD_CLK_ID(501), R8A7795_CLK_S3D1 }, /* AUDMAC1 */
348 { MOD_CLK_ID(502), R8A7795_CLK_S3D1 }, /* AUDMAC0 */
349 { MOD_CLK_ID(601), R8A7795_CLK_S2D1 }, /* FCPVD2 */
350 { MOD_CLK_ID(602), R8A7795_CLK_S2D1 }, /* FCPVD1 */
351 { MOD_CLK_ID(603), R8A7795_CLK_S2D1 }, /* FCPVD0 */
352 { MOD_CLK_ID(606), R8A7795_CLK_S2D1 }, /* FCPVB1 */
353 { MOD_CLK_ID(607), R8A7795_CLK_S2D1 }, /* FCPVB0 */
354 { MOD_CLK_ID(610), R8A7795_CLK_S2D1 }, /* FCPVI1 */
355 { MOD_CLK_ID(611), R8A7795_CLK_S2D1 }, /* FCPVI0 */
356 { MOD_CLK_ID(614), R8A7795_CLK_S2D1 }, /* FCPF1 */
357 { MOD_CLK_ID(615), R8A7795_CLK_S2D1 }, /* FCPF0 */
358 { MOD_CLK_ID(619), R8A7795_CLK_S2D1 }, /* FCPCS */
359 { MOD_CLK_ID(621), R8A7795_CLK_S2D1 }, /* VSPD2 */
360 { MOD_CLK_ID(622), R8A7795_CLK_S2D1 }, /* VSPD1 */
361 { MOD_CLK_ID(623), R8A7795_CLK_S2D1 }, /* VSPD0 */
362 { MOD_CLK_ID(624), R8A7795_CLK_S2D1 }, /* VSPBC */
363 { MOD_CLK_ID(626), R8A7795_CLK_S2D1 }, /* VSPBD */
364 { MOD_CLK_ID(630), R8A7795_CLK_S2D1 }, /* VSPI1 */
365 { MOD_CLK_ID(631), R8A7795_CLK_S2D1 }, /* VSPI0 */
366 { MOD_CLK_ID(804), R8A7795_CLK_S2D1 }, /* VIN7 */
367 { MOD_CLK_ID(805), R8A7795_CLK_S2D1 }, /* VIN6 */
368 { MOD_CLK_ID(806), R8A7795_CLK_S2D1 }, /* VIN5 */
369 { MOD_CLK_ID(807), R8A7795_CLK_S2D1 }, /* VIN4 */
370 { MOD_CLK_ID(808), R8A7795_CLK_S2D1 }, /* VIN3 */
371 { MOD_CLK_ID(809), R8A7795_CLK_S2D1 }, /* VIN2 */
372 { MOD_CLK_ID(810), R8A7795_CLK_S2D1 }, /* VIN1 */
373 { MOD_CLK_ID(811), R8A7795_CLK_S2D1 }, /* VIN0 */
374 { MOD_CLK_ID(812), R8A7795_CLK_S3D2 }, /* EAVB-IF */
375 { MOD_CLK_ID(820), R8A7795_CLK_S2D1 }, /* IMR3 */
376 { MOD_CLK_ID(821), R8A7795_CLK_S2D1 }, /* IMR2 */
377 { MOD_CLK_ID(822), R8A7795_CLK_S2D1 }, /* IMR1 */
378 { MOD_CLK_ID(823), R8A7795_CLK_S2D1 }, /* IMR0 */
379};
380
381
382 /*
383 * Fixups for R-Car H3 ES2.x
384 */
385
386static const unsigned int r8a7795es2_mod_nullify[] __initconst = {
387 MOD_CLK_ID(117), /* FDP1-2 */
388 MOD_CLK_ID(327), /* USB3-IF1 */
389 MOD_CLK_ID(600), /* FCPVD3 */
390 MOD_CLK_ID(609), /* FCPVI2 */
391 MOD_CLK_ID(613), /* FCPF2 */
392 MOD_CLK_ID(616), /* FCPCI1 */
393 MOD_CLK_ID(617), /* FCPCI0 */
394 MOD_CLK_ID(620), /* VSPD3 */
395 MOD_CLK_ID(629), /* VSPI2 */
396 MOD_CLK_ID(713), /* CSI21 */
397};
398
313static int __init r8a7795_cpg_mssr_init(struct device *dev) 399static int __init r8a7795_cpg_mssr_init(struct device *dev)
314{ 400{
315 const struct rcar_gen3_cpg_pll_config *cpg_pll_config; 401 const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
@@ -326,7 +412,26 @@ static int __init r8a7795_cpg_mssr_init(struct device *dev)
326 return -EINVAL; 412 return -EINVAL;
327 } 413 }
328 414
329 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR); 415 if (soc_device_match(r8a7795es1)) {
416 cpg_core_nullify_range(r8a7795_core_clks,
417 ARRAY_SIZE(r8a7795_core_clks),
418 R8A7795_CLK_S0D2, R8A7795_CLK_S0D12);
419 mssr_mod_nullify(r8a7795_mod_clks,
420 ARRAY_SIZE(r8a7795_mod_clks),
421 r8a7795es1_mod_nullify,
422 ARRAY_SIZE(r8a7795es1_mod_nullify));
423 mssr_mod_reparent(r8a7795_mod_clks,
424 ARRAY_SIZE(r8a7795_mod_clks),
425 r8a7795es1_mod_reparent,
426 ARRAY_SIZE(r8a7795es1_mod_reparent));
427 } else {
428 mssr_mod_nullify(r8a7795_mod_clks,
429 ARRAY_SIZE(r8a7795_mod_clks),
430 r8a7795es2_mod_nullify,
431 ARRAY_SIZE(r8a7795es2_mod_nullify));
432 }
433
434 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
330} 435}
331 436
332const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = { 437const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = {
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 11e084a56b0d..9d114b31b073 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -54,8 +54,8 @@ enum clk_ids {
54 54
55static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { 55static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
56 /* External Clock Inputs */ 56 /* External Clock Inputs */
57 DEF_INPUT("extal", CLK_EXTAL), 57 DEF_INPUT("extal", CLK_EXTAL),
58 DEF_INPUT("extalr", CLK_EXTALR), 58 DEF_INPUT("extalr", CLK_EXTALR),
59 59
60 /* Internal Core Clocks */ 60 /* Internal Core Clocks */
61 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), 61 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
@@ -95,10 +95,10 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
95 DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1), 95 DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1),
96 DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1), 96 DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1),
97 97
98 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x0074), 98 DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074),
99 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x0078), 99 DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078),
100 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x0268), 100 DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
101 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x026c), 101 DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
102 102
103 DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1), 103 DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
104 DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1), 104 DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
@@ -135,7 +135,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
135 DEF_MOD("sdif2", 312, R8A7796_CLK_SD2), 135 DEF_MOD("sdif2", 312, R8A7796_CLK_SD2),
136 DEF_MOD("sdif1", 313, R8A7796_CLK_SD1), 136 DEF_MOD("sdif1", 313, R8A7796_CLK_SD1),
137 DEF_MOD("sdif0", 314, R8A7796_CLK_SD0), 137 DEF_MOD("sdif0", 314, R8A7796_CLK_SD0),
138 DEF_MOD("rwdt0", 402, R8A7796_CLK_R), 138 DEF_MOD("rwdt", 402, R8A7796_CLK_R),
139 DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1), 139 DEF_MOD("intc-ap", 408, R8A7796_CLK_S3D1),
140 DEF_MOD("drif7", 508, R8A7796_CLK_S3D2), 140 DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
141 DEF_MOD("drif6", 509, R8A7796_CLK_S3D2), 141 DEF_MOD("drif6", 509, R8A7796_CLK_S3D2),
@@ -179,6 +179,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {
179 DEF_MOD("vin1", 810, R8A7796_CLK_S0D2), 179 DEF_MOD("vin1", 810, R8A7796_CLK_S0D2),
180 DEF_MOD("vin0", 811, R8A7796_CLK_S0D2), 180 DEF_MOD("vin0", 811, R8A7796_CLK_S0D2),
181 DEF_MOD("etheravb", 812, R8A7796_CLK_S0D6), 181 DEF_MOD("etheravb", 812, R8A7796_CLK_S0D6),
182 DEF_MOD("imr1", 822, R8A7796_CLK_S0D2),
183 DEF_MOD("imr0", 823, R8A7796_CLK_S0D2),
182 DEF_MOD("gpio7", 905, R8A7796_CLK_S3D4), 184 DEF_MOD("gpio7", 905, R8A7796_CLK_S3D4),
183 DEF_MOD("gpio6", 906, R8A7796_CLK_S3D4), 185 DEF_MOD("gpio6", 906, R8A7796_CLK_S3D4),
184 DEF_MOD("gpio5", 907, R8A7796_CLK_S3D4), 186 DEF_MOD("gpio5", 907, R8A7796_CLK_S3D4),
@@ -271,7 +273,7 @@ static int __init r8a7796_cpg_mssr_init(struct device *dev)
271 return -EINVAL; 273 return -EINVAL;
272 } 274 }
273 275
274 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR); 276 return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
275} 277}
276 278
277const struct cpg_mssr_info r8a7796_cpg_mssr_info __initconst = { 279const struct cpg_mssr_info r8a7796_cpg_mssr_info __initconst = {
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 742f6dc7c156..3dee900522b7 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -20,6 +20,7 @@
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/slab.h> 22#include <linux/slab.h>
23#include <linux/sys_soc.h>
23 24
24#include "renesas-cpg-mssr.h" 25#include "renesas-cpg-mssr.h"
25#include "rcar-gen3-cpg.h" 26#include "rcar-gen3-cpg.h"
@@ -247,6 +248,27 @@ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core,
247 248
248static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata; 249static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
249static unsigned int cpg_clk_extalr __initdata; 250static unsigned int cpg_clk_extalr __initdata;
251static u32 cpg_mode __initdata;
252static u32 cpg_quirks __initdata;
253
254#define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */
255#define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */
256
257static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
258 {
259 .soc_id = "r8a7795", .revision = "ES1.0",
260 .data = (void *)(PLL_ERRATA | RCKCR_CKSEL),
261 },
262 {
263 .soc_id = "r8a7795", .revision = "ES1.*",
264 .data = (void *)RCKCR_CKSEL,
265 },
266 {
267 .soc_id = "r8a7796", .revision = "ES1.0",
268 .data = (void *)RCKCR_CKSEL,
269 },
270 { /* sentinel */ }
271};
250 272
251struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, 273struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
252 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 274 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
@@ -275,6 +297,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
275 */ 297 */
276 value = readl(base + CPG_PLL0CR); 298 value = readl(base + CPG_PLL0CR);
277 mult = (((value >> 24) & 0x7f) + 1) * 2; 299 mult = (((value >> 24) & 0x7f) + 1) * 2;
300 if (cpg_quirks & PLL_ERRATA)
301 mult *= 2;
278 break; 302 break;
279 303
280 case CLK_TYPE_GEN3_PLL1: 304 case CLK_TYPE_GEN3_PLL1:
@@ -290,6 +314,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
290 */ 314 */
291 value = readl(base + CPG_PLL2CR); 315 value = readl(base + CPG_PLL2CR);
292 mult = (((value >> 24) & 0x7f) + 1) * 2; 316 mult = (((value >> 24) & 0x7f) + 1) * 2;
317 if (cpg_quirks & PLL_ERRATA)
318 mult *= 2;
293 break; 319 break;
294 320
295 case CLK_TYPE_GEN3_PLL3: 321 case CLK_TYPE_GEN3_PLL3:
@@ -305,24 +331,33 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
305 */ 331 */
306 value = readl(base + CPG_PLL4CR); 332 value = readl(base + CPG_PLL4CR);
307 mult = (((value >> 24) & 0x7f) + 1) * 2; 333 mult = (((value >> 24) & 0x7f) + 1) * 2;
334 if (cpg_quirks & PLL_ERRATA)
335 mult *= 2;
308 break; 336 break;
309 337
310 case CLK_TYPE_GEN3_SD: 338 case CLK_TYPE_GEN3_SD:
311 return cpg_sd_clk_register(core, base, __clk_get_name(parent)); 339 return cpg_sd_clk_register(core, base, __clk_get_name(parent));
312 340
313 case CLK_TYPE_GEN3_R: 341 case CLK_TYPE_GEN3_R:
314 /* 342 if (cpg_quirks & RCKCR_CKSEL) {
315 * RINT is default. 343 /*
316 * Only if EXTALR is populated, we switch to it. 344 * RINT is default.
317 */ 345 * Only if EXTALR is populated, we switch to it.
318 value = readl(base + CPG_RCKCR) & 0x3f; 346 */
319 347 value = readl(base + CPG_RCKCR) & 0x3f;
320 if (clk_get_rate(clks[cpg_clk_extalr])) { 348
321 parent = clks[cpg_clk_extalr]; 349 if (clk_get_rate(clks[cpg_clk_extalr])) {
322 value |= BIT(15); 350 parent = clks[cpg_clk_extalr];
351 value |= BIT(15);
352 }
353
354 writel(value, base + CPG_RCKCR);
355 break;
323 } 356 }
324 357
325 writel(value, base + CPG_RCKCR); 358 /* Select parent clock of RCLK by MD28 */
359 if (cpg_mode & BIT(28))
360 parent = clks[cpg_clk_extalr];
326 break; 361 break;
327 362
328 default: 363 default:
@@ -334,9 +369,16 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
334} 369}
335 370
336int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, 371int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
337 unsigned int clk_extalr) 372 unsigned int clk_extalr, u32 mode)
338{ 373{
374 const struct soc_device_attribute *attr;
375
339 cpg_pll_config = config; 376 cpg_pll_config = config;
340 cpg_clk_extalr = clk_extalr; 377 cpg_clk_extalr = clk_extalr;
378 cpg_mode = mode;
379 attr = soc_device_match(cpg_quirks_match);
380 if (attr)
381 cpg_quirks = (uintptr_t)attr->data;
382 pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
341 return 0; 383 return 0;
342} 384}
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index f788f481dd42..073be54b5d03 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -37,6 +37,6 @@ struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
37 const struct cpg_core_clk *core, const struct cpg_mssr_info *info, 37 const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
38 struct clk **clks, void __iomem *base); 38 struct clk **clks, void __iomem *base);
39int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, 39int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
40 unsigned int clk_extalr); 40 unsigned int clk_extalr, u32 mode);
41 41
42#endif 42#endif
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index eadcbd43ff88..99eeec6f24ec 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -265,6 +265,11 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
265 WARN_DEBUG(id >= priv->num_core_clks); 265 WARN_DEBUG(id >= priv->num_core_clks);
266 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); 266 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
267 267
268 if (!core->name) {
269 /* Skip NULLified clock */
270 return;
271 }
272
268 switch (core->type) { 273 switch (core->type) {
269 case CLK_TYPE_IN: 274 case CLK_TYPE_IN:
270 clk = of_clk_get_by_name(priv->dev->of_node, core->name); 275 clk = of_clk_get_by_name(priv->dev->of_node, core->name);
@@ -335,6 +340,11 @@ static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
335 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks); 340 WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
336 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT); 341 WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
337 342
343 if (!mod->name) {
344 /* Skip NULLified clock */
345 return;
346 }
347
338 parent = priv->clks[mod->parent]; 348 parent = priv->clks[mod->parent];
339 if (IS_ERR(parent)) { 349 if (IS_ERR(parent)) {
340 clk = parent; 350 clk = parent;
@@ -734,5 +744,45 @@ static int __init cpg_mssr_init(void)
734 744
735subsys_initcall(cpg_mssr_init); 745subsys_initcall(cpg_mssr_init);
736 746
747void __init cpg_core_nullify_range(struct cpg_core_clk *core_clks,
748 unsigned int num_core_clks,
749 unsigned int first_clk,
750 unsigned int last_clk)
751{
752 unsigned int i;
753
754 for (i = 0; i < num_core_clks; i++)
755 if (core_clks[i].id >= first_clk &&
756 core_clks[i].id <= last_clk)
757 core_clks[i].name = NULL;
758}
759
760void __init mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
761 unsigned int num_mod_clks,
762 const unsigned int *clks, unsigned int n)
763{
764 unsigned int i, j;
765
766 for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
767 if (mod_clks[i].id == clks[j]) {
768 mod_clks[i].name = NULL;
769 j++;
770 }
771}
772
773void __init mssr_mod_reparent(struct mssr_mod_clk *mod_clks,
774 unsigned int num_mod_clks,
775 const struct mssr_mod_reparent *clks,
776 unsigned int n)
777{
778 unsigned int i, j;
779
780 for (i = 0, j = 0; i < num_mod_clks && j < n; i++)
781 if (mod_clks[i].id == clks[j].clk) {
782 mod_clks[i].parent = clks[j].parent;
783 j++;
784 }
785}
786
737MODULE_DESCRIPTION("Renesas CPG/MSSR Driver"); 787MODULE_DESCRIPTION("Renesas CPG/MSSR Driver");
738MODULE_LICENSE("GPL v2"); 788MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index 4bb7a80c6469..148f4f0aa2a4 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -134,4 +134,26 @@ extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
134extern const struct cpg_mssr_info r8a7745_cpg_mssr_info; 134extern const struct cpg_mssr_info r8a7745_cpg_mssr_info;
135extern const struct cpg_mssr_info r8a7795_cpg_mssr_info; 135extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
136extern const struct cpg_mssr_info r8a7796_cpg_mssr_info; 136extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
137
138
139 /*
140 * Helpers for fixing up clock tables depending on SoC revision
141 */
142
143struct mssr_mod_reparent {
144 unsigned int clk, parent;
145};
146
147
148extern void cpg_core_nullify_range(struct cpg_core_clk *core_clks,
149 unsigned int num_core_clks,
150 unsigned int first_clk,
151 unsigned int last_clk);
152extern void mssr_mod_nullify(struct mssr_mod_clk *mod_clks,
153 unsigned int num_mod_clks,
154 const unsigned int *clks, unsigned int n);
155extern void mssr_mod_reparent(struct mssr_mod_clk *mod_clks,
156 unsigned int num_mod_clks,
157 const struct mssr_mod_reparent *clks,
158 unsigned int n);
137#endif 159#endif
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 141971488f40..26b220c988b2 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -12,7 +12,7 @@ obj-y += clk-muxgrf.o
12obj-y += clk-ddr.o 12obj-y += clk-ddr.o
13obj-$(CONFIG_RESET_CONTROLLER) += softrst.o 13obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
14 14
15obj-y += clk-rk1108.o 15obj-y += clk-rv1108.o
16obj-y += clk-rk3036.o 16obj-y += clk-rk3036.o
17obj-y += clk-rk3188.o 17obj-y += clk-rk3188.o
18obj-y += clk-rk3228.o 18obj-y += clk-rk3228.o
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index eec51893a7e6..dd0433d4753e 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -269,6 +269,7 @@ static int rockchip_rk3036_pll_enable(struct clk_hw *hw)
269 269
270 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0), 270 writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
271 pll->reg_base + RK3036_PLLCON(1)); 271 pll->reg_base + RK3036_PLLCON(1));
272 rockchip_pll_wait_lock(pll);
272 273
273 return 0; 274 return 0;
274} 275}
@@ -501,6 +502,7 @@ static int rockchip_rk3066_pll_enable(struct clk_hw *hw)
501 502
502 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0), 503 writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0),
503 pll->reg_base + RK3066_PLLCON(3)); 504 pll->reg_base + RK3066_PLLCON(3));
505 rockchip_pll_wait_lock(pll);
504 506
505 return 0; 507 return 0;
506} 508}
@@ -746,6 +748,7 @@ static int rockchip_rk3399_pll_enable(struct clk_hw *hw)
746 748
747 writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0), 749 writel(HIWORD_UPDATE(0, RK3399_PLLCON3_PWRDOWN, 0),
748 pll->reg_base + RK3399_PLLCON(3)); 750 pll->reg_base + RK3399_PLLCON(3));
751 rockchip_rk3399_pll_wait_lock(pll);
749 752
750 return 0; 753 return 0;
751} 754}
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 924f560dcf80..00d4150e33c3 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -127,7 +127,7 @@ PNAME(mux_ddrphy_p) = { "dpll_ddr", "gpll_ddr" };
127PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" }; 127PNAME(mux_pll_src_3plls_p) = { "apll", "dpll", "gpll" };
128PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" }; 128PNAME(mux_timer_p) = { "xin24m", "pclk_peri_src" };
129 129
130PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll" "usb480m" }; 130PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" };
131 131
132PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" }; 132PNAME(mux_mmc_src_p) = { "apll", "dpll", "gpll", "xin24m" };
133PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" }; 133PNAME(mux_i2s_pre_p) = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
@@ -450,6 +450,13 @@ static void __init rk3036_clk_init(struct device_node *np)
450 return; 450 return;
451 } 451 }
452 452
453 /*
454 * Make uart_pll_clk a child of the gpll, as all other sources are
455 * not that usable / stable.
456 */
457 writel_relaxed(HIWORD_UPDATE(0x2, 0x3, 10),
458 reg_base + RK2928_CLKSEL_CON(13));
459
453 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS); 460 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
454 if (IS_ERR(ctx)) { 461 if (IS_ERR(ctx)) {
455 pr_err("%s: rockchip clk init failed\n", __func__); 462 pr_err("%s: rockchip clk init failed\n", __func__);
diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
index 1e384e143504..b04f29774ee7 100644
--- a/drivers/clk/rockchip/clk-rk3328.c
+++ b/drivers/clk/rockchip/clk-rk3328.c
@@ -20,6 +20,7 @@
20#include <dt-bindings/clock/rk3328-cru.h> 20#include <dt-bindings/clock/rk3328-cru.h>
21#include "clk.h" 21#include "clk.h"
22 22
23#define RK3328_GRF_SOC_CON4 0x410
23#define RK3328_GRF_SOC_STATUS0 0x480 24#define RK3328_GRF_SOC_STATUS0 0x480
24#define RK3328_GRF_MAC_CON1 0x904 25#define RK3328_GRF_MAC_CON1 0x904
25#define RK3328_GRF_MAC_CON2 0x908 26#define RK3328_GRF_MAC_CON2 0x908
@@ -214,6 +215,8 @@ PNAME(mux_mac2io_src_p) = { "clk_mac2io_src",
214 "gmac_clkin" }; 215 "gmac_clkin" };
215PNAME(mux_mac2phy_src_p) = { "clk_mac2phy_src", 216PNAME(mux_mac2phy_src_p) = { "clk_mac2phy_src",
216 "phy_50m_out" }; 217 "phy_50m_out" };
218PNAME(mux_mac2io_ext_p) = { "clk_mac2io",
219 "gmac_clkin" };
217 220
218static struct rockchip_pll_clock rk3328_pll_clks[] __initdata = { 221static struct rockchip_pll_clock rk3328_pll_clks[] __initdata = {
219 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 222 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
@@ -680,6 +683,10 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
680 COMPOSITE(SCLK_MAC2IO_OUT, "clk_mac2io_out", mux_2plls_p, 0, 683 COMPOSITE(SCLK_MAC2IO_OUT, "clk_mac2io_out", mux_2plls_p, 0,
681 RK3328_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 5, DFLAGS, 684 RK3328_CLKSEL_CON(27), 15, 1, MFLAGS, 8, 5, DFLAGS,
682 RK3328_CLKGATE_CON(3), 5, GFLAGS), 685 RK3328_CLKGATE_CON(3), 5, GFLAGS),
686 MUXGRF(SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_p, CLK_SET_RATE_NO_REPARENT,
687 RK3328_GRF_MAC_CON1, 10, 1, MFLAGS),
688 MUXGRF(SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_p, CLK_SET_RATE_NO_REPARENT,
689 RK3328_GRF_SOC_CON4, 14, 1, MFLAGS),
683 690
684 COMPOSITE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", mux_2plls_p, 0, 691 COMPOSITE(SCLK_MAC2PHY_SRC, "clk_mac2phy_src", mux_2plls_p, 0,
685 RK3328_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 5, DFLAGS, 692 RK3328_CLKSEL_CON(26), 7, 1, MFLAGS, 0, 5, DFLAGS,
@@ -691,6 +698,8 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
691 COMPOSITE_NOMUX(SCLK_MAC2PHY_OUT, "clk_mac2phy_out", "clk_mac2phy", 0, 698 COMPOSITE_NOMUX(SCLK_MAC2PHY_OUT, "clk_mac2phy_out", "clk_mac2phy", 0,
692 RK3328_CLKSEL_CON(26), 8, 2, DFLAGS, 699 RK3328_CLKSEL_CON(26), 8, 2, DFLAGS,
693 RK3328_CLKGATE_CON(9), 2, GFLAGS), 700 RK3328_CLKGATE_CON(9), 2, GFLAGS),
701 MUXGRF(SCLK_MAC2PHY, "clk_mac2phy", mux_mac2phy_src_p, CLK_SET_RATE_NO_REPARENT,
702 RK3328_GRF_MAC_CON2, 10, 1, MFLAGS),
694 703
695 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 704 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
696 705
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 6cb474c593e7..024762d3214d 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -835,18 +835,18 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
835 GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 0, GFLAGS), 835 GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 0, GFLAGS),
836 836
837 /* timer gates */ 837 /* timer gates */
838 GATE(0, "sclk_timer15", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 11, GFLAGS), 838 GATE(SCLK_TIMER15, "sclk_timer15", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 11, GFLAGS),
839 GATE(0, "sclk_timer14", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 10, GFLAGS), 839 GATE(SCLK_TIMER14, "sclk_timer14", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 10, GFLAGS),
840 GATE(0, "sclk_timer13", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 9, GFLAGS), 840 GATE(SCLK_TIMER13, "sclk_timer13", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 9, GFLAGS),
841 GATE(0, "sclk_timer12", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 8, GFLAGS), 841 GATE(SCLK_TIMER12, "sclk_timer12", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 8, GFLAGS),
842 GATE(0, "sclk_timer11", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 7, GFLAGS), 842 GATE(SCLK_TIMER11, "sclk_timer11", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 7, GFLAGS),
843 GATE(0, "sclk_timer10", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 6, GFLAGS), 843 GATE(SCLK_TIMER10, "sclk_timer10", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 6, GFLAGS),
844 GATE(0, "sclk_timer05", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 5, GFLAGS), 844 GATE(SCLK_TIMER05, "sclk_timer05", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 5, GFLAGS),
845 GATE(0, "sclk_timer04", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 4, GFLAGS), 845 GATE(SCLK_TIMER04, "sclk_timer04", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 4, GFLAGS),
846 GATE(0, "sclk_timer03", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 3, GFLAGS), 846 GATE(SCLK_TIMER03, "sclk_timer03", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 3, GFLAGS),
847 GATE(0, "sclk_timer02", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 2, GFLAGS), 847 GATE(SCLK_TIMER02, "sclk_timer02", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 2, GFLAGS),
848 GATE(0, "sclk_timer01", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 1, GFLAGS), 848 GATE(SCLK_TIMER01, "sclk_timer01", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 1, GFLAGS),
849 GATE(0, "sclk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 0, GFLAGS), 849 GATE(SCLK_TIMER00, "sclk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 0, GFLAGS),
850}; 850};
851 851
852static const char *const rk3368_critical_clocks[] __initconst = { 852static const char *const rk3368_critical_clocks[] __initconst = {
@@ -858,6 +858,9 @@ static const char *const rk3368_critical_clocks[] __initconst = {
858 */ 858 */
859 "pclk_pwm1", 859 "pclk_pwm1",
860 "pclk_pd_pmu", 860 "pclk_pd_pmu",
861 "pclk_pd_alive",
862 "pclk_peri",
863 "hclk_peri",
861}; 864};
862 865
863static void __init rk3368_clk_init(struct device_node *np) 866static void __init rk3368_clk_init(struct device_node *np)
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 73121b144634..fa3cbef08776 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -1477,10 +1477,10 @@ static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
1477 GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS), 1477 GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS),
1478 GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS), 1478 GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS),
1479 1479
1480 GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS), 1480 GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS),
1481 GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS), 1481 GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS),
1482 GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS), 1482 GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS),
1483 GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS), 1483 GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS),
1484 GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS), 1484 GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS),
1485}; 1485};
1486 1486
diff --git a/drivers/clk/rockchip/clk-rk1108.c b/drivers/clk/rockchip/clk-rv1108.c
index 92750d798e5d..7c05ab366348 100644
--- a/drivers/clk/rockchip/clk-rk1108.c
+++ b/drivers/clk/rockchip/clk-rv1108.c
@@ -18,16 +18,16 @@
18#include <linux/of.h> 18#include <linux/of.h>
19#include <linux/of_address.h> 19#include <linux/of_address.h>
20#include <linux/syscore_ops.h> 20#include <linux/syscore_ops.h>
21#include <dt-bindings/clock/rk1108-cru.h> 21#include <dt-bindings/clock/rv1108-cru.h>
22#include "clk.h" 22#include "clk.h"
23 23
24#define RK1108_GRF_SOC_STATUS0 0x480 24#define RV1108_GRF_SOC_STATUS0 0x480
25 25
26enum rk1108_plls { 26enum rv1108_plls {
27 apll, dpll, gpll, 27 apll, dpll, gpll,
28}; 28};
29 29
30static struct rockchip_pll_rate_table rk1108_pll_rates[] = { 30static struct rockchip_pll_rate_table rv1108_pll_rates[] = {
31 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ 31 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
32 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 32 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
33 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 33 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
@@ -74,32 +74,32 @@ static struct rockchip_pll_rate_table rk1108_pll_rates[] = {
74 { /* sentinel */ }, 74 { /* sentinel */ },
75}; 75};
76 76
77#define RK1108_DIV_CORE_MASK 0xf 77#define RV1108_DIV_CORE_MASK 0xf
78#define RK1108_DIV_CORE_SHIFT 4 78#define RV1108_DIV_CORE_SHIFT 4
79 79
80#define RK1108_CLKSEL0(_core_peri_div) \ 80#define RV1108_CLKSEL0(_core_peri_div) \
81 { \ 81 { \
82 .reg = RK1108_CLKSEL_CON(1), \ 82 .reg = RV1108_CLKSEL_CON(1), \
83 .val = HIWORD_UPDATE(_core_peri_div, RK1108_DIV_CORE_MASK,\ 83 .val = HIWORD_UPDATE(_core_peri_div, RV1108_DIV_CORE_MASK,\
84 RK1108_DIV_CORE_SHIFT) \ 84 RV1108_DIV_CORE_SHIFT) \
85 } 85 }
86 86
87#define RK1108_CPUCLK_RATE(_prate, _core_peri_div) \ 87#define RV1108_CPUCLK_RATE(_prate, _core_peri_div) \
88 { \ 88 { \
89 .prate = _prate, \ 89 .prate = _prate, \
90 .divs = { \ 90 .divs = { \
91 RK1108_CLKSEL0(_core_peri_div), \ 91 RV1108_CLKSEL0(_core_peri_div), \
92 }, \ 92 }, \
93 } 93 }
94 94
95static struct rockchip_cpuclk_rate_table rk1108_cpuclk_rates[] __initdata = { 95static struct rockchip_cpuclk_rate_table rv1108_cpuclk_rates[] __initdata = {
96 RK1108_CPUCLK_RATE(816000000, 4), 96 RV1108_CPUCLK_RATE(816000000, 4),
97 RK1108_CPUCLK_RATE(600000000, 4), 97 RV1108_CPUCLK_RATE(600000000, 4),
98 RK1108_CPUCLK_RATE(312000000, 4), 98 RV1108_CPUCLK_RATE(312000000, 4),
99}; 99};
100 100
101static const struct rockchip_cpuclk_reg_data rk1108_cpuclk_data = { 101static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = {
102 .core_reg = RK1108_CLKSEL_CON(0), 102 .core_reg = RV1108_CLKSEL_CON(0),
103 .div_core_shift = 0, 103 .div_core_shift = 0,
104 .div_core_mask = 0x1f, 104 .div_core_mask = 0x1f,
105 .mux_core_alt = 1, 105 .mux_core_alt = 1,
@@ -131,13 +131,13 @@ PNAME(mux_i2s_out_p) = { "i2s0_pre", "xin12m" };
131PNAME(mux_i2s1_p) = { "i2s1_src", "i2s1_frac", "xin12m" }; 131PNAME(mux_i2s1_p) = { "i2s1_src", "i2s1_frac", "xin12m" };
132PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" }; 132PNAME(mux_i2s2_p) = { "i2s2_src", "i2s2_frac", "xin12m" };
133 133
134static struct rockchip_pll_clock rk1108_pll_clks[] __initdata = { 134static struct rockchip_pll_clock rv1108_pll_clks[] __initdata = {
135 [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RK1108_PLL_CON(0), 135 [apll] = PLL(pll_rk3399, PLL_APLL, "apll", mux_pll_p, 0, RV1108_PLL_CON(0),
136 RK1108_PLL_CON(3), 8, 31, 0, rk1108_pll_rates), 136 RV1108_PLL_CON(3), 8, 31, 0, rv1108_pll_rates),
137 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK1108_PLL_CON(8), 137 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RV1108_PLL_CON(8),
138 RK1108_PLL_CON(11), 8, 31, 0, NULL), 138 RV1108_PLL_CON(11), 8, 31, 0, NULL),
139 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK1108_PLL_CON(16), 139 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16),
140 RK1108_PLL_CON(19), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk1108_pll_rates), 140 RV1108_PLL_CON(19), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rv1108_pll_rates),
141}; 141};
142 142
143#define MFLAGS CLK_MUX_HIWORD_MASK 143#define MFLAGS CLK_MUX_HIWORD_MASK
@@ -145,56 +145,56 @@ static struct rockchip_pll_clock rk1108_pll_clks[] __initdata = {
145#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) 145#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
146#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK 146#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
147 147
148static struct rockchip_clk_branch rk1108_uart0_fracmux __initdata = 148static struct rockchip_clk_branch rv1108_uart0_fracmux __initdata =
149 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT, 149 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
150 RK1108_CLKSEL_CON(13), 8, 2, MFLAGS); 150 RV1108_CLKSEL_CON(13), 8, 2, MFLAGS);
151 151
152static struct rockchip_clk_branch rk1108_uart1_fracmux __initdata = 152static struct rockchip_clk_branch rv1108_uart1_fracmux __initdata =
153 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT, 153 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
154 RK1108_CLKSEL_CON(14), 8, 2, MFLAGS); 154 RV1108_CLKSEL_CON(14), 8, 2, MFLAGS);
155 155
156static struct rockchip_clk_branch rk1108_uart2_fracmux __initdata = 156static struct rockchip_clk_branch rv1108_uart2_fracmux __initdata =
157 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT, 157 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
158 RK1108_CLKSEL_CON(15), 8, 2, MFLAGS); 158 RV1108_CLKSEL_CON(15), 8, 2, MFLAGS);
159 159
160static struct rockchip_clk_branch rk1108_i2s0_fracmux __initdata = 160static struct rockchip_clk_branch rv1108_i2s0_fracmux __initdata =
161 MUX(0, "i2s0_pre", mux_i2s0_pre_p, CLK_SET_RATE_PARENT, 161 MUX(0, "i2s0_pre", mux_i2s0_pre_p, CLK_SET_RATE_PARENT,
162 RK1108_CLKSEL_CON(5), 12, 2, MFLAGS); 162 RV1108_CLKSEL_CON(5), 12, 2, MFLAGS);
163 163
164static struct rockchip_clk_branch rk1108_i2s1_fracmux __initdata = 164static struct rockchip_clk_branch rv1108_i2s1_fracmux __initdata =
165 MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT, 165 MUX(0, "i2s1_pre", mux_i2s1_p, CLK_SET_RATE_PARENT,
166 RK1108_CLKSEL_CON(6), 12, 2, MFLAGS); 166 RV1108_CLKSEL_CON(6), 12, 2, MFLAGS);
167 167
168static struct rockchip_clk_branch rk1108_i2s2_fracmux __initdata = 168static struct rockchip_clk_branch rv1108_i2s2_fracmux __initdata =
169 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT, 169 MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
170 RK1108_CLKSEL_CON(7), 12, 2, MFLAGS); 170 RV1108_CLKSEL_CON(7), 12, 2, MFLAGS);
171 171
172static struct rockchip_clk_branch rk1108_clk_branches[] __initdata = { 172static struct rockchip_clk_branch rv1108_clk_branches[] __initdata = {
173 MUX(0, "hdmi_phy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT, 173 MUX(0, "hdmi_phy", mux_hdmiphy_phy_p, CLK_SET_RATE_PARENT,
174 RK1108_MISC_CON, 13, 2, MFLAGS), 174 RV1108_MISC_CON, 13, 2, MFLAGS),
175 MUX(0, "usb480m", mux_usb480m_pre_p, CLK_SET_RATE_PARENT, 175 MUX(0, "usb480m", mux_usb480m_pre_p, CLK_SET_RATE_PARENT,
176 RK1108_MISC_CON, 15, 2, MFLAGS), 176 RV1108_MISC_CON, 15, 2, MFLAGS),
177 /* 177 /*
178 * Clock-Architecture Diagram 2 178 * Clock-Architecture Diagram 2
179 */ 179 */
180 180
181 /* PD_CORE */ 181 /* PD_CORE */
182 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED, 182 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
183 RK1108_CLKGATE_CON(0), 1, GFLAGS), 183 RV1108_CLKGATE_CON(0), 1, GFLAGS),
184 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED, 184 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
185 RK1108_CLKGATE_CON(0), 0, GFLAGS), 185 RV1108_CLKGATE_CON(0), 0, GFLAGS),
186 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED, 186 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
187 RK1108_CLKGATE_CON(0), 2, GFLAGS), 187 RV1108_CLKGATE_CON(0), 2, GFLAGS),
188 COMPOSITE_NOMUX(0, "pclken_dbg", "armclk", CLK_IGNORE_UNUSED, 188 COMPOSITE_NOMUX(0, "pclken_dbg", "armclk", CLK_IGNORE_UNUSED,
189 RK1108_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY, 189 RV1108_CLKSEL_CON(1), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
190 RK1108_CLKGATE_CON(0), 5, GFLAGS), 190 RV1108_CLKGATE_CON(0), 5, GFLAGS),
191 COMPOSITE_NOMUX(ACLK_ENMCORE, "aclkenm_core", "armclk", CLK_IGNORE_UNUSED, 191 COMPOSITE_NOMUX(ACLK_ENMCORE, "aclkenm_core", "armclk", CLK_IGNORE_UNUSED,
192 RK1108_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY, 192 RV1108_CLKSEL_CON(1), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
193 RK1108_CLKGATE_CON(0), 4, GFLAGS), 193 RV1108_CLKGATE_CON(0), 4, GFLAGS),
194 GATE(ACLK_CORE, "aclk_core", "aclkenm_core", CLK_IGNORE_UNUSED, 194 GATE(ACLK_CORE, "aclk_core", "aclkenm_core", CLK_IGNORE_UNUSED,
195 RK1108_CLKGATE_CON(11), 0, GFLAGS), 195 RV1108_CLKGATE_CON(11), 0, GFLAGS),
196 GATE(0, "pclk_dbg", "pclken_dbg", CLK_IGNORE_UNUSED, 196 GATE(0, "pclk_dbg", "pclken_dbg", CLK_IGNORE_UNUSED,
197 RK1108_CLKGATE_CON(11), 1, GFLAGS), 197 RV1108_CLKGATE_CON(11), 1, GFLAGS),
198 198
199 /* PD_RKVENC */ 199 /* PD_RKVENC */
200 200
@@ -202,58 +202,58 @@ static struct rockchip_clk_branch rk1108_clk_branches[] __initdata = {
202 202
203 /* PD_PMU_wrapper */ 203 /* PD_PMU_wrapper */
204 COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IGNORE_UNUSED, 204 COMPOSITE_NOMUX(0, "pmu_24m_ena", "gpll", CLK_IGNORE_UNUSED,
205 RK1108_CLKSEL_CON(38), 0, 5, DFLAGS, 205 RV1108_CLKSEL_CON(38), 0, 5, DFLAGS,
206 RK1108_CLKGATE_CON(8), 12, GFLAGS), 206 RV1108_CLKGATE_CON(8), 12, GFLAGS),
207 GATE(0, "pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED, 207 GATE(0, "pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
208 RK1108_CLKGATE_CON(10), 0, GFLAGS), 208 RV1108_CLKGATE_CON(10), 0, GFLAGS),
209 GATE(0, "intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED, 209 GATE(0, "intmem1", "pmu_24m_ena", CLK_IGNORE_UNUSED,
210 RK1108_CLKGATE_CON(10), 1, GFLAGS), 210 RV1108_CLKGATE_CON(10), 1, GFLAGS),
211 GATE(0, "gpio0_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED, 211 GATE(0, "gpio0_pmu", "pmu_24m_ena", CLK_IGNORE_UNUSED,
212 RK1108_CLKGATE_CON(10), 2, GFLAGS), 212 RV1108_CLKGATE_CON(10), 2, GFLAGS),
213 GATE(0, "pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED, 213 GATE(0, "pmugrf", "pmu_24m_ena", CLK_IGNORE_UNUSED,
214 RK1108_CLKGATE_CON(10), 3, GFLAGS), 214 RV1108_CLKGATE_CON(10), 3, GFLAGS),
215 GATE(0, "pmu_noc", "pmu_24m_ena", CLK_IGNORE_UNUSED, 215 GATE(0, "pmu_noc", "pmu_24m_ena", CLK_IGNORE_UNUSED,
216 RK1108_CLKGATE_CON(10), 4, GFLAGS), 216 RV1108_CLKGATE_CON(10), 4, GFLAGS),
217 GATE(0, "i2c0_pmu_pclk", "pmu_24m_ena", CLK_IGNORE_UNUSED, 217 GATE(0, "i2c0_pmu_pclk", "pmu_24m_ena", CLK_IGNORE_UNUSED,
218 RK1108_CLKGATE_CON(10), 5, GFLAGS), 218 RV1108_CLKGATE_CON(10), 5, GFLAGS),
219 GATE(0, "pwm0_pmu_pclk", "pmu_24m_ena", CLK_IGNORE_UNUSED, 219 GATE(0, "pwm0_pmu_pclk", "pmu_24m_ena", CLK_IGNORE_UNUSED,
220 RK1108_CLKGATE_CON(10), 6, GFLAGS), 220 RV1108_CLKGATE_CON(10), 6, GFLAGS),
221 COMPOSITE(0, "pwm0_pmu_clk", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 221 COMPOSITE(0, "pwm0_pmu_clk", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
222 RK1108_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 7, DFLAGS, 222 RV1108_CLKSEL_CON(12), 7, 1, MFLAGS, 0, 7, DFLAGS,
223 RK1108_CLKGATE_CON(8), 15, GFLAGS), 223 RV1108_CLKGATE_CON(8), 15, GFLAGS),
224 COMPOSITE(0, "i2c0_pmu_clk", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 224 COMPOSITE(0, "i2c0_pmu_clk", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
225 RK1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS, 225 RV1108_CLKSEL_CON(19), 7, 1, MFLAGS, 0, 7, DFLAGS,
226 RK1108_CLKGATE_CON(8), 14, GFLAGS), 226 RV1108_CLKGATE_CON(8), 14, GFLAGS),
227 GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, 227 GATE(0, "pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED,
228 RK1108_CLKGATE_CON(8), 13, GFLAGS), 228 RV1108_CLKGATE_CON(8), 13, GFLAGS),
229 229
230 /* 230 /*
231 * Clock-Architecture Diagram 4 231 * Clock-Architecture Diagram 4
232 */ 232 */
233 COMPOSITE(0, "aclk_vio0_2wrap_occ", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED, 233 COMPOSITE(0, "aclk_vio0_2wrap_occ", mux_pll_src_4plls_p, CLK_IGNORE_UNUSED,
234 RK1108_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS, 234 RV1108_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
235 RK1108_CLKGATE_CON(6), 0, GFLAGS), 235 RV1108_CLKGATE_CON(6), 0, GFLAGS),
236 GATE(0, "aclk_vio0_pre", "aclk_vio0_2wrap_occ", CLK_IGNORE_UNUSED, 236 GATE(0, "aclk_vio0_pre", "aclk_vio0_2wrap_occ", CLK_IGNORE_UNUSED,
237 RK1108_CLKGATE_CON(17), 0, GFLAGS), 237 RV1108_CLKGATE_CON(17), 0, GFLAGS),
238 COMPOSITE_NOMUX(0, "hclk_vio_pre", "aclk_vio0_pre", 0, 238 COMPOSITE_NOMUX(0, "hclk_vio_pre", "aclk_vio0_pre", 0,
239 RK1108_CLKSEL_CON(29), 0, 5, DFLAGS, 239 RV1108_CLKSEL_CON(29), 0, 5, DFLAGS,
240 RK1108_CLKGATE_CON(7), 2, GFLAGS), 240 RV1108_CLKGATE_CON(7), 2, GFLAGS),
241 COMPOSITE_NOMUX(0, "pclk_vio_pre", "aclk_vio0_pre", 0, 241 COMPOSITE_NOMUX(0, "pclk_vio_pre", "aclk_vio0_pre", 0,
242 RK1108_CLKSEL_CON(29), 8, 5, DFLAGS, 242 RV1108_CLKSEL_CON(29), 8, 5, DFLAGS,
243 RK1108_CLKGATE_CON(7), 3, GFLAGS), 243 RV1108_CLKGATE_CON(7), 3, GFLAGS),
244 244
245 INVERTER(0, "pclk_vip", "ext_vip", 245 INVERTER(0, "pclk_vip", "ext_vip",
246 RK1108_CLKSEL_CON(31), 8, IFLAGS), 246 RV1108_CLKSEL_CON(31), 8, IFLAGS),
247 GATE(0, "pclk_isp_pre", "pclk_vip", CLK_IGNORE_UNUSED, 247 GATE(0, "pclk_isp_pre", "pclk_vip", CLK_IGNORE_UNUSED,
248 RK1108_CLKGATE_CON(7), 6, GFLAGS), 248 RV1108_CLKGATE_CON(7), 6, GFLAGS),
249 GATE(0, "pclk_isp", "pclk_isp_pre", CLK_IGNORE_UNUSED, 249 GATE(0, "pclk_isp", "pclk_isp_pre", CLK_IGNORE_UNUSED,
250 RK1108_CLKGATE_CON(18), 10, GFLAGS), 250 RV1108_CLKGATE_CON(18), 10, GFLAGS),
251 GATE(0, "dclk_hdmiphy_src_gpll", "gpll", CLK_IGNORE_UNUSED, 251 GATE(0, "dclk_hdmiphy_src_gpll", "gpll", CLK_IGNORE_UNUSED,
252 RK1108_CLKGATE_CON(6), 5, GFLAGS), 252 RV1108_CLKGATE_CON(6), 5, GFLAGS),
253 GATE(0, "dclk_hdmiphy_src_dpll", "dpll", CLK_IGNORE_UNUSED, 253 GATE(0, "dclk_hdmiphy_src_dpll", "dpll", CLK_IGNORE_UNUSED,
254 RK1108_CLKGATE_CON(6), 4, GFLAGS), 254 RV1108_CLKGATE_CON(6), 4, GFLAGS),
255 COMPOSITE_NOGATE(0, "dclk_hdmiphy", mux_dclk_hdmiphy_pre_p, 0, 255 COMPOSITE_NOGATE(0, "dclk_hdmiphy", mux_dclk_hdmiphy_pre_p, 0,
256 RK1108_CLKSEL_CON(32), 6, 2, MFLAGS, 8, 6, DFLAGS), 256 RV1108_CLKSEL_CON(32), 6, 2, MFLAGS, 8, 6, DFLAGS),
257 257
258 /* 258 /*
259 * Clock-Architecture Diagram 5 259 * Clock-Architecture Diagram 5
@@ -262,153 +262,153 @@ static struct rockchip_clk_branch rk1108_clk_branches[] __initdata = {
262 FACTOR(0, "xin12m", "xin24m", 0, 1, 2), 262 FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
263 263
264 COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0, 264 COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
265 RK1108_CLKSEL_CON(5), 8, 1, MFLAGS, 0, 7, DFLAGS, 265 RV1108_CLKSEL_CON(5), 8, 1, MFLAGS, 0, 7, DFLAGS,
266 RK1108_CLKGATE_CON(2), 0, GFLAGS), 266 RV1108_CLKGATE_CON(2), 0, GFLAGS),
267 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, 267 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
268 RK1108_CLKSEL_CON(8), 0, 268 RV1108_CLKSEL_CON(8), 0,
269 RK1108_CLKGATE_CON(2), 1, GFLAGS, 269 RV1108_CLKGATE_CON(2), 1, GFLAGS,
270 &rk1108_i2s0_fracmux), 270 &rv1108_i2s0_fracmux),
271 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT, 271 GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
272 RK1108_CLKGATE_CON(2), 2, GFLAGS), 272 RV1108_CLKGATE_CON(2), 2, GFLAGS),
273 COMPOSITE_NODIV(0, "i2s_out", mux_i2s_out_p, 0, 273 COMPOSITE_NODIV(0, "i2s_out", mux_i2s_out_p, 0,
274 RK1108_CLKSEL_CON(5), 15, 1, MFLAGS, 274 RV1108_CLKSEL_CON(5), 15, 1, MFLAGS,
275 RK1108_CLKGATE_CON(2), 3, GFLAGS), 275 RV1108_CLKGATE_CON(2), 3, GFLAGS),
276 276
277 COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0, 277 COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0,
278 RK1108_CLKSEL_CON(6), 8, 1, MFLAGS, 0, 7, DFLAGS, 278 RV1108_CLKSEL_CON(6), 8, 1, MFLAGS, 0, 7, DFLAGS,
279 RK1108_CLKGATE_CON(2), 4, GFLAGS), 279 RV1108_CLKGATE_CON(2), 4, GFLAGS),
280 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT, 280 COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
281 RK2928_CLKSEL_CON(9), 0, 281 RK2928_CLKSEL_CON(9), 0,
282 RK2928_CLKGATE_CON(2), 5, GFLAGS, 282 RK2928_CLKGATE_CON(2), 5, GFLAGS,
283 &rk1108_i2s1_fracmux), 283 &rv1108_i2s1_fracmux),
284 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT, 284 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
285 RK1108_CLKGATE_CON(2), 6, GFLAGS), 285 RV1108_CLKGATE_CON(2), 6, GFLAGS),
286 286
287 COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0, 287 COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0,
288 RK1108_CLKSEL_CON(7), 8, 1, MFLAGS, 0, 7, DFLAGS, 288 RV1108_CLKSEL_CON(7), 8, 1, MFLAGS, 0, 7, DFLAGS,
289 RK1108_CLKGATE_CON(3), 8, GFLAGS), 289 RV1108_CLKGATE_CON(3), 8, GFLAGS),
290 COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT, 290 COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
291 RK1108_CLKSEL_CON(10), 0, 291 RV1108_CLKSEL_CON(10), 0,
292 RK1108_CLKGATE_CON(2), 9, GFLAGS, 292 RV1108_CLKGATE_CON(2), 9, GFLAGS,
293 &rk1108_i2s2_fracmux), 293 &rv1108_i2s2_fracmux),
294 GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT, 294 GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
295 RK1108_CLKGATE_CON(2), 10, GFLAGS), 295 RV1108_CLKGATE_CON(2), 10, GFLAGS),
296 296
297 /* PD_BUS */ 297 /* PD_BUS */
298 GATE(0, "aclk_bus_src_gpll", "gpll", CLK_IGNORE_UNUSED, 298 GATE(0, "aclk_bus_src_gpll", "gpll", CLK_IGNORE_UNUSED,
299 RK1108_CLKGATE_CON(1), 0, GFLAGS), 299 RV1108_CLKGATE_CON(1), 0, GFLAGS),
300 GATE(0, "aclk_bus_src_apll", "apll", CLK_IGNORE_UNUSED, 300 GATE(0, "aclk_bus_src_apll", "apll", CLK_IGNORE_UNUSED,
301 RK1108_CLKGATE_CON(1), 1, GFLAGS), 301 RV1108_CLKGATE_CON(1), 1, GFLAGS),
302 GATE(0, "aclk_bus_src_dpll", "dpll", CLK_IGNORE_UNUSED, 302 GATE(0, "aclk_bus_src_dpll", "dpll", CLK_IGNORE_UNUSED,
303 RK1108_CLKGATE_CON(1), 2, GFLAGS), 303 RV1108_CLKGATE_CON(1), 2, GFLAGS),
304 COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, 0, 304 COMPOSITE_NOGATE(ACLK_PRE, "aclk_bus_pre", mux_aclk_bus_src_p, 0,
305 RK1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS), 305 RV1108_CLKSEL_CON(2), 8, 2, MFLAGS, 0, 5, DFLAGS),
306 COMPOSITE_NOMUX(0, "hclk_bus_pre", "aclk_bus_2wrap_occ", 0, 306 COMPOSITE_NOMUX(0, "hclk_bus_pre", "aclk_bus_2wrap_occ", 0,
307 RK1108_CLKSEL_CON(3), 0, 5, DFLAGS, 307 RV1108_CLKSEL_CON(3), 0, 5, DFLAGS,
308 RK1108_CLKGATE_CON(1), 4, GFLAGS), 308 RV1108_CLKGATE_CON(1), 4, GFLAGS),
309 COMPOSITE_NOMUX(0, "pclken_bus", "aclk_bus_2wrap_occ", 0, 309 COMPOSITE_NOMUX(0, "pclken_bus", "aclk_bus_2wrap_occ", 0,
310 RK1108_CLKSEL_CON(3), 8, 5, DFLAGS, 310 RV1108_CLKSEL_CON(3), 8, 5, DFLAGS,
311 RK1108_CLKGATE_CON(1), 5, GFLAGS), 311 RV1108_CLKGATE_CON(1), 5, GFLAGS),
312 GATE(0, "pclk_bus_pre", "pclken_bus", CLK_IGNORE_UNUSED, 312 GATE(0, "pclk_bus_pre", "pclken_bus", CLK_IGNORE_UNUSED,
313 RK1108_CLKGATE_CON(1), 6, GFLAGS), 313 RV1108_CLKGATE_CON(1), 6, GFLAGS),
314 GATE(0, "pclk_top_pre", "pclken_bus", CLK_IGNORE_UNUSED, 314 GATE(0, "pclk_top_pre", "pclken_bus", CLK_IGNORE_UNUSED,
315 RK1108_CLKGATE_CON(1), 7, GFLAGS), 315 RV1108_CLKGATE_CON(1), 7, GFLAGS),
316 GATE(0, "pclk_ddr_pre", "pclken_bus", CLK_IGNORE_UNUSED, 316 GATE(0, "pclk_ddr_pre", "pclken_bus", CLK_IGNORE_UNUSED,
317 RK1108_CLKGATE_CON(1), 8, GFLAGS), 317 RV1108_CLKGATE_CON(1), 8, GFLAGS),
318 GATE(0, "clk_timer0", "mux_pll_p", CLK_IGNORE_UNUSED, 318 GATE(0, "clk_timer0", "mux_pll_p", CLK_IGNORE_UNUSED,
319 RK1108_CLKGATE_CON(1), 9, GFLAGS), 319 RV1108_CLKGATE_CON(1), 9, GFLAGS),
320 GATE(0, "clk_timer1", "mux_pll_p", CLK_IGNORE_UNUSED, 320 GATE(0, "clk_timer1", "mux_pll_p", CLK_IGNORE_UNUSED,
321 RK1108_CLKGATE_CON(1), 10, GFLAGS), 321 RV1108_CLKGATE_CON(1), 10, GFLAGS),
322 GATE(0, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED, 322 GATE(0, "pclk_timer", "pclk_bus_pre", CLK_IGNORE_UNUSED,
323 RK1108_CLKGATE_CON(13), 4, GFLAGS), 323 RV1108_CLKGATE_CON(13), 4, GFLAGS),
324 324
325 COMPOSITE(0, "uart0_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 325 COMPOSITE(0, "uart0_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
326 RK1108_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS, 326 RV1108_CLKSEL_CON(13), 12, 2, MFLAGS, 0, 7, DFLAGS,
327 RK1108_CLKGATE_CON(3), 1, GFLAGS), 327 RV1108_CLKGATE_CON(3), 1, GFLAGS),
328 COMPOSITE(0, "uart1_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 328 COMPOSITE(0, "uart1_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
329 RK1108_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS, 329 RV1108_CLKSEL_CON(14), 12, 2, MFLAGS, 0, 7, DFLAGS,
330 RK1108_CLKGATE_CON(3), 3, GFLAGS), 330 RV1108_CLKGATE_CON(3), 3, GFLAGS),
331 COMPOSITE(0, "uart21_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED, 331 COMPOSITE(0, "uart21_src", mux_pll_src_dpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
332 RK1108_CLKSEL_CON(15), 12, 2, MFLAGS, 0, 7, DFLAGS, 332 RV1108_CLKSEL_CON(15), 12, 2, MFLAGS, 0, 7, DFLAGS,
333 RK1108_CLKGATE_CON(3), 5, GFLAGS), 333 RV1108_CLKGATE_CON(3), 5, GFLAGS),
334 334
335 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT, 335 COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
336 RK1108_CLKSEL_CON(16), 0, 336 RV1108_CLKSEL_CON(16), 0,
337 RK1108_CLKGATE_CON(3), 2, GFLAGS, 337 RV1108_CLKGATE_CON(3), 2, GFLAGS,
338 &rk1108_uart0_fracmux), 338 &rv1108_uart0_fracmux),
339 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT, 339 COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
340 RK1108_CLKSEL_CON(17), 0, 340 RV1108_CLKSEL_CON(17), 0,
341 RK1108_CLKGATE_CON(3), 4, GFLAGS, 341 RV1108_CLKGATE_CON(3), 4, GFLAGS,
342 &rk1108_uart1_fracmux), 342 &rv1108_uart1_fracmux),
343 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT, 343 COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
344 RK1108_CLKSEL_CON(18), 0, 344 RV1108_CLKSEL_CON(18), 0,
345 RK1108_CLKGATE_CON(3), 6, GFLAGS, 345 RV1108_CLKGATE_CON(3), 6, GFLAGS,
346 &rk1108_uart2_fracmux), 346 &rv1108_uart2_fracmux),
347 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", CLK_IGNORE_UNUSED, 347 GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_pre", CLK_IGNORE_UNUSED,
348 RK1108_CLKGATE_CON(13), 10, GFLAGS), 348 RV1108_CLKGATE_CON(13), 10, GFLAGS),
349 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", CLK_IGNORE_UNUSED, 349 GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_pre", CLK_IGNORE_UNUSED,
350 RK1108_CLKGATE_CON(13), 11, GFLAGS), 350 RV1108_CLKGATE_CON(13), 11, GFLAGS),
351 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", CLK_IGNORE_UNUSED, 351 GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_pre", CLK_IGNORE_UNUSED,
352 RK1108_CLKGATE_CON(13), 12, GFLAGS), 352 RV1108_CLKGATE_CON(13), 12, GFLAGS),
353 353
354 COMPOSITE(0, "clk_i2c1", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 354 COMPOSITE(0, "clk_i2c1", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
355 RK1108_CLKSEL_CON(19), 15, 2, MFLAGS, 8, 7, DFLAGS, 355 RV1108_CLKSEL_CON(19), 15, 2, MFLAGS, 8, 7, DFLAGS,
356 RK1108_CLKGATE_CON(3), 7, GFLAGS), 356 RV1108_CLKGATE_CON(3), 7, GFLAGS),
357 COMPOSITE(0, "clk_i2c2", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 357 COMPOSITE(0, "clk_i2c2", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
358 RK1108_CLKSEL_CON(20), 7, 2, MFLAGS, 0, 7, DFLAGS, 358 RV1108_CLKSEL_CON(20), 7, 2, MFLAGS, 0, 7, DFLAGS,
359 RK1108_CLKGATE_CON(3), 8, GFLAGS), 359 RV1108_CLKGATE_CON(3), 8, GFLAGS),
360 COMPOSITE(0, "clk_i2c3", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 360 COMPOSITE(0, "clk_i2c3", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
361 RK1108_CLKSEL_CON(20), 15, 2, MFLAGS, 8, 7, DFLAGS, 361 RV1108_CLKSEL_CON(20), 15, 2, MFLAGS, 8, 7, DFLAGS,
362 RK1108_CLKGATE_CON(3), 9, GFLAGS), 362 RV1108_CLKGATE_CON(3), 9, GFLAGS),
363 GATE(0, "pclk_i2c1", "pclk_bus_pre", CLK_IGNORE_UNUSED, 363 GATE(0, "pclk_i2c1", "pclk_bus_pre", CLK_IGNORE_UNUSED,
364 RK1108_CLKGATE_CON(13), 0, GFLAGS), 364 RV1108_CLKGATE_CON(13), 0, GFLAGS),
365 GATE(0, "pclk_i2c2", "pclk_bus_pre", CLK_IGNORE_UNUSED, 365 GATE(0, "pclk_i2c2", "pclk_bus_pre", CLK_IGNORE_UNUSED,
366 RK1108_CLKGATE_CON(13), 1, GFLAGS), 366 RV1108_CLKGATE_CON(13), 1, GFLAGS),
367 GATE(0, "pclk_i2c3", "pclk_bus_pre", CLK_IGNORE_UNUSED, 367 GATE(0, "pclk_i2c3", "pclk_bus_pre", CLK_IGNORE_UNUSED,
368 RK1108_CLKGATE_CON(13), 2, GFLAGS), 368 RV1108_CLKGATE_CON(13), 2, GFLAGS),
369 COMPOSITE(0, "clk_pwm1", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED, 369 COMPOSITE(0, "clk_pwm1", mux_pll_src_2plls_p, CLK_IGNORE_UNUSED,
370 RK1108_CLKSEL_CON(12), 15, 2, MFLAGS, 8, 7, DFLAGS, 370 RV1108_CLKSEL_CON(12), 15, 2, MFLAGS, 8, 7, DFLAGS,
371 RK1108_CLKGATE_CON(3), 10, GFLAGS), 371 RV1108_CLKGATE_CON(3), 10, GFLAGS),
372 GATE(0, "pclk_pwm1", "pclk_bus_pre", CLK_IGNORE_UNUSED, 372 GATE(0, "pclk_pwm1", "pclk_bus_pre", CLK_IGNORE_UNUSED,
373 RK1108_CLKGATE_CON(13), 6, GFLAGS), 373 RV1108_CLKGATE_CON(13), 6, GFLAGS),
374 GATE(0, "pclk_wdt", "pclk_bus_pre", CLK_IGNORE_UNUSED, 374 GATE(0, "pclk_wdt", "pclk_bus_pre", CLK_IGNORE_UNUSED,
375 RK1108_CLKGATE_CON(13), 3, GFLAGS), 375 RV1108_CLKGATE_CON(13), 3, GFLAGS),
376 GATE(0, "pclk_gpio1", "pclk_bus_pre", CLK_IGNORE_UNUSED, 376 GATE(0, "pclk_gpio1", "pclk_bus_pre", CLK_IGNORE_UNUSED,
377 RK1108_CLKGATE_CON(13), 7, GFLAGS), 377 RV1108_CLKGATE_CON(13), 7, GFLAGS),
378 GATE(0, "pclk_gpio2", "pclk_bus_pre", CLK_IGNORE_UNUSED, 378 GATE(0, "pclk_gpio2", "pclk_bus_pre", CLK_IGNORE_UNUSED,
379 RK1108_CLKGATE_CON(13), 8, GFLAGS), 379 RV1108_CLKGATE_CON(13), 8, GFLAGS),
380 GATE(0, "pclk_gpio3", "pclk_bus_pre", CLK_IGNORE_UNUSED, 380 GATE(0, "pclk_gpio3", "pclk_bus_pre", CLK_IGNORE_UNUSED,
381 RK1108_CLKGATE_CON(13), 9, GFLAGS), 381 RV1108_CLKGATE_CON(13), 9, GFLAGS),
382 382
383 GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED, 383 GATE(0, "pclk_grf", "pclk_bus_pre", CLK_IGNORE_UNUSED,
384 RK1108_CLKGATE_CON(14), 0, GFLAGS), 384 RV1108_CLKGATE_CON(14), 0, GFLAGS),
385 385
386 GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre", 0, 386 GATE(ACLK_DMAC, "aclk_dmac", "aclk_bus_pre", 0,
387 RK1108_CLKGATE_CON(12), 2, GFLAGS), 387 RV1108_CLKGATE_CON(12), 2, GFLAGS),
388 GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED, 388 GATE(0, "hclk_rom", "hclk_bus_pre", CLK_IGNORE_UNUSED,
389 RK1108_CLKGATE_CON(12), 3, GFLAGS), 389 RV1108_CLKGATE_CON(12), 3, GFLAGS),
390 GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED, 390 GATE(0, "aclk_intmem", "aclk_bus_pre", CLK_IGNORE_UNUSED,
391 RK1108_CLKGATE_CON(12), 1, GFLAGS), 391 RV1108_CLKGATE_CON(12), 1, GFLAGS),
392 392
393 /* PD_DDR */ 393 /* PD_DDR */
394 GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED, 394 GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
395 RK1108_CLKGATE_CON(0), 8, GFLAGS), 395 RV1108_CLKGATE_CON(0), 8, GFLAGS),
396 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED, 396 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
397 RK1108_CLKGATE_CON(0), 9, GFLAGS), 397 RV1108_CLKGATE_CON(0), 9, GFLAGS),
398 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED, 398 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
399 RK1108_CLKGATE_CON(0), 10, GFLAGS), 399 RV1108_CLKGATE_CON(0), 10, GFLAGS),
400 COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED, 400 COMPOSITE(0, "ddrphy4x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
401 RK1108_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 3, 401 RV1108_CLKSEL_CON(4), 8, 2, MFLAGS, 0, 3,
402 DFLAGS | CLK_DIVIDER_POWER_OF_TWO, 402 DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
403 RK1108_CLKGATE_CON(10), 9, GFLAGS), 403 RV1108_CLKGATE_CON(10), 9, GFLAGS),
404 GATE(0, "ddrupctl", "ddrphy_pre", CLK_IGNORE_UNUSED, 404 GATE(0, "ddrupctl", "ddrphy_pre", CLK_IGNORE_UNUSED,
405 RK1108_CLKGATE_CON(12), 4, GFLAGS), 405 RV1108_CLKGATE_CON(12), 4, GFLAGS),
406 GATE(0, "ddrc", "ddrphy", CLK_IGNORE_UNUSED, 406 GATE(0, "ddrc", "ddrphy", CLK_IGNORE_UNUSED,
407 RK1108_CLKGATE_CON(12), 5, GFLAGS), 407 RV1108_CLKGATE_CON(12), 5, GFLAGS),
408 GATE(0, "ddrmon", "ddrphy_pre", CLK_IGNORE_UNUSED, 408 GATE(0, "ddrmon", "ddrphy_pre", CLK_IGNORE_UNUSED,
409 RK1108_CLKGATE_CON(12), 6, GFLAGS), 409 RV1108_CLKGATE_CON(12), 6, GFLAGS),
410 GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED, 410 GATE(0, "timer_clk", "xin24m", CLK_IGNORE_UNUSED,
411 RK1108_CLKGATE_CON(0), 11, GFLAGS), 411 RV1108_CLKGATE_CON(0), 11, GFLAGS),
412 412
413 /* 413 /*
414 * Clock-Architecture Diagram 6 414 * Clock-Architecture Diagram 6
@@ -416,73 +416,73 @@ static struct rockchip_clk_branch rk1108_clk_branches[] __initdata = {
416 416
417 /* PD_PERI */ 417 /* PD_PERI */
418 COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", 0, 418 COMPOSITE_NOMUX(0, "pclk_periph_pre", "gpll", 0,
419 RK1108_CLKSEL_CON(23), 10, 5, DFLAGS, 419 RV1108_CLKSEL_CON(23), 10, 5, DFLAGS,
420 RK1108_CLKGATE_CON(4), 5, GFLAGS), 420 RV1108_CLKGATE_CON(4), 5, GFLAGS),
421 GATE(0, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED, 421 GATE(0, "pclk_periph", "pclk_periph_pre", CLK_IGNORE_UNUSED,
422 RK1108_CLKGATE_CON(15), 13, GFLAGS), 422 RV1108_CLKGATE_CON(15), 13, GFLAGS),
423 COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", 0, 423 COMPOSITE_NOMUX(0, "hclk_periph_pre", "gpll", 0,
424 RK1108_CLKSEL_CON(23), 5, 5, DFLAGS, 424 RV1108_CLKSEL_CON(23), 5, 5, DFLAGS,
425 RK1108_CLKGATE_CON(4), 4, GFLAGS), 425 RV1108_CLKGATE_CON(4), 4, GFLAGS),
426 GATE(0, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED, 426 GATE(0, "hclk_periph", "hclk_periph_pre", CLK_IGNORE_UNUSED,
427 RK1108_CLKGATE_CON(15), 12, GFLAGS), 427 RV1108_CLKGATE_CON(15), 12, GFLAGS),
428 428
429 GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IGNORE_UNUSED, 429 GATE(0, "aclk_peri_src_dpll", "dpll", CLK_IGNORE_UNUSED,
430 RK1108_CLKGATE_CON(4), 1, GFLAGS), 430 RV1108_CLKGATE_CON(4), 1, GFLAGS),
431 GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IGNORE_UNUSED, 431 GATE(0, "aclk_peri_src_gpll", "gpll", CLK_IGNORE_UNUSED,
432 RK1108_CLKGATE_CON(4), 2, GFLAGS), 432 RV1108_CLKGATE_CON(4), 2, GFLAGS),
433 COMPOSITE(0, "aclk_periph", mux_aclk_peri_src_p, CLK_IGNORE_UNUSED, 433 COMPOSITE(0, "aclk_periph", mux_aclk_peri_src_p, CLK_IGNORE_UNUSED,
434 RK1108_CLKSEL_CON(23), 15, 2, MFLAGS, 0, 5, DFLAGS, 434 RV1108_CLKSEL_CON(23), 15, 2, MFLAGS, 0, 5, DFLAGS,
435 RK1108_CLKGATE_CON(15), 11, GFLAGS), 435 RV1108_CLKGATE_CON(15), 11, GFLAGS),
436 436
437 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, 437 COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,
438 RK1108_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 8, DFLAGS, 438 RV1108_CLKSEL_CON(25), 8, 2, MFLAGS, 0, 8, DFLAGS,
439 RK1108_CLKGATE_CON(5), 0, GFLAGS), 439 RV1108_CLKGATE_CON(5), 0, GFLAGS),
440 440
441 COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0, 441 COMPOSITE_NODIV(0, "sclk_sdio_src", mux_mmc_src_p, 0,
442 RK1108_CLKSEL_CON(25), 10, 2, MFLAGS, 442 RV1108_CLKSEL_CON(25), 10, 2, MFLAGS,
443 RK1108_CLKGATE_CON(5), 2, GFLAGS), 443 RV1108_CLKGATE_CON(5), 2, GFLAGS),
444 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0, 444 DIV(SCLK_SDIO, "sclk_sdio", "sclk_sdio_src", 0,
445 RK1108_CLKSEL_CON(26), 0, 8, DFLAGS), 445 RV1108_CLKSEL_CON(26), 0, 8, DFLAGS),
446 446
447 COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0, 447 COMPOSITE_NODIV(0, "sclk_emmc_src", mux_mmc_src_p, 0,
448 RK1108_CLKSEL_CON(25), 12, 2, MFLAGS, 448 RV1108_CLKSEL_CON(25), 12, 2, MFLAGS,
449 RK1108_CLKGATE_CON(5), 1, GFLAGS), 449 RV1108_CLKGATE_CON(5), 1, GFLAGS),
450 DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0, 450 DIV(SCLK_EMMC, "sclk_emmc", "sclk_emmc_src", 0,
451 RK2928_CLKSEL_CON(26), 8, 8, DFLAGS), 451 RK2928_CLKSEL_CON(26), 8, 8, DFLAGS),
452 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_periph", 0, RK1108_CLKGATE_CON(15), 0, GFLAGS), 452 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 0, GFLAGS),
453 GATE(HCLK_SDIO, "hclk_sdio", "hclk_periph", 0, RK1108_CLKGATE_CON(15), 1, GFLAGS), 453 GATE(HCLK_SDIO, "hclk_sdio", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 1, GFLAGS),
454 GATE(HCLK_EMMC, "hclk_emmc", "hclk_periph", 0, RK1108_CLKGATE_CON(15), 2, GFLAGS), 454 GATE(HCLK_EMMC, "hclk_emmc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 2, GFLAGS),
455 455
456 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0, 456 COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
457 RK1108_CLKSEL_CON(27), 14, 2, MFLAGS, 8, 5, DFLAGS, 457 RV1108_CLKSEL_CON(27), 14, 2, MFLAGS, 8, 5, DFLAGS,
458 RK1108_CLKGATE_CON(5), 3, GFLAGS), 458 RV1108_CLKGATE_CON(5), 3, GFLAGS),
459 GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RK1108_CLKGATE_CON(15), 3, GFLAGS), 459 GATE(HCLK_NANDC, "hclk_nandc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 3, GFLAGS),
460 460
461 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_2plls_p, 0, 461 COMPOSITE(SCLK_SFC, "sclk_sfc", mux_pll_src_2plls_p, 0,
462 RK1108_CLKSEL_CON(27), 7, 2, MFLAGS, 0, 7, DFLAGS, 462 RV1108_CLKSEL_CON(27), 7, 2, MFLAGS, 0, 7, DFLAGS,
463 RK1108_CLKGATE_CON(5), 4, GFLAGS), 463 RV1108_CLKGATE_CON(5), 4, GFLAGS),
464 GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RK1108_CLKGATE_CON(15), 10, GFLAGS), 464 GATE(HCLK_SFC, "hclk_sfc", "hclk_periph", 0, RV1108_CLKGATE_CON(15), 10, GFLAGS),
465 465
466 COMPOSITE(0, "sclk_macphy_pre", mux_pll_src_apll_gpll_p, 0, 466 COMPOSITE(0, "sclk_macphy_pre", mux_pll_src_apll_gpll_p, 0,
467 RK1108_CLKSEL_CON(24), 12, 2, MFLAGS, 0, 5, DFLAGS, 467 RV1108_CLKSEL_CON(24), 12, 2, MFLAGS, 0, 5, DFLAGS,
468 RK1108_CLKGATE_CON(4), 10, GFLAGS), 468 RV1108_CLKGATE_CON(4), 10, GFLAGS),
469 MUX(0, "sclk_macphy", mux_sclk_macphy_p, CLK_SET_RATE_PARENT, 469 MUX(0, "sclk_macphy", mux_sclk_macphy_p, CLK_SET_RATE_PARENT,
470 RK1108_CLKSEL_CON(24), 8, 2, MFLAGS), 470 RV1108_CLKSEL_CON(24), 8, 2, MFLAGS),
471 GATE(0, "sclk_macphy_rx", "sclk_macphy", 0, RK1108_CLKGATE_CON(4), 8, GFLAGS), 471 GATE(0, "sclk_macphy_rx", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 8, GFLAGS),
472 GATE(0, "sclk_mac_ref", "sclk_macphy", 0, RK1108_CLKGATE_CON(4), 6, GFLAGS), 472 GATE(0, "sclk_mac_ref", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 6, GFLAGS),
473 GATE(0, "sclk_mac_refout", "sclk_macphy", 0, RK1108_CLKGATE_CON(4), 7, GFLAGS), 473 GATE(0, "sclk_mac_refout", "sclk_macphy", 0, RV1108_CLKGATE_CON(4), 7, GFLAGS),
474 474
475 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RK1108_SDMMC_CON0, 1), 475 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "sclk_sdmmc", RV1108_SDMMC_CON0, 1),
476 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK1108_SDMMC_CON1, 1), 476 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RV1108_SDMMC_CON1, 1),
477 477
478 MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RK1108_SDIO_CON0, 1), 478 MMC(SCLK_SDIO_DRV, "sdio_drv", "sclk_sdio", RV1108_SDIO_CON0, 1),
479 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RK1108_SDIO_CON1, 1), 479 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "sclk_sdio", RV1108_SDIO_CON1, 1),
480 480
481 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RK1108_EMMC_CON0, 1), 481 MMC(SCLK_EMMC_DRV, "emmc_drv", "sclk_emmc", RV1108_EMMC_CON0, 1),
482 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RK1108_EMMC_CON1, 1), 482 MMC(SCLK_EMMC_SAMPLE, "emmc_sample", "sclk_emmc", RV1108_EMMC_CON1, 1),
483}; 483};
484 484
485static const char *const rk1108_critical_clocks[] __initconst = { 485static const char *const rv1108_critical_clocks[] __initconst = {
486 "aclk_core", 486 "aclk_core",
487 "aclk_bus_src_gpll", 487 "aclk_bus_src_gpll",
488 "aclk_periph", 488 "aclk_periph",
@@ -490,7 +490,7 @@ static const char *const rk1108_critical_clocks[] __initconst = {
490 "pclk_periph", 490 "pclk_periph",
491}; 491};
492 492
493static void __init rk1108_clk_init(struct device_node *np) 493static void __init rv1108_clk_init(struct device_node *np)
494{ 494{
495 struct rockchip_clk_provider *ctx; 495 struct rockchip_clk_provider *ctx;
496 void __iomem *reg_base; 496 void __iomem *reg_base;
@@ -508,24 +508,24 @@ static void __init rk1108_clk_init(struct device_node *np)
508 return; 508 return;
509 } 509 }
510 510
511 rockchip_clk_register_plls(ctx, rk1108_pll_clks, 511 rockchip_clk_register_plls(ctx, rv1108_pll_clks,
512 ARRAY_SIZE(rk1108_pll_clks), 512 ARRAY_SIZE(rv1108_pll_clks),
513 RK1108_GRF_SOC_STATUS0); 513 RV1108_GRF_SOC_STATUS0);
514 rockchip_clk_register_branches(ctx, rk1108_clk_branches, 514 rockchip_clk_register_branches(ctx, rv1108_clk_branches,
515 ARRAY_SIZE(rk1108_clk_branches)); 515 ARRAY_SIZE(rv1108_clk_branches));
516 rockchip_clk_protect_critical(rk1108_critical_clocks, 516 rockchip_clk_protect_critical(rv1108_critical_clocks,
517 ARRAY_SIZE(rk1108_critical_clocks)); 517 ARRAY_SIZE(rv1108_critical_clocks));
518 518
519 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk", 519 rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
520 mux_armclk_p, ARRAY_SIZE(mux_armclk_p), 520 mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
521 &rk1108_cpuclk_data, rk1108_cpuclk_rates, 521 &rv1108_cpuclk_data, rv1108_cpuclk_rates,
522 ARRAY_SIZE(rk1108_cpuclk_rates)); 522 ARRAY_SIZE(rv1108_cpuclk_rates));
523 523
524 rockchip_register_softrst(np, 13, reg_base + RK1108_SOFTRST_CON(0), 524 rockchip_register_softrst(np, 13, reg_base + RV1108_SOFTRST_CON(0),
525 ROCKCHIP_SOFTRST_HIWORD_MASK); 525 ROCKCHIP_SOFTRST_HIWORD_MASK);
526 526
527 rockchip_register_restart_notifier(ctx, RK1108_GLB_SRST_FST, NULL); 527 rockchip_register_restart_notifier(ctx, RV1108_GLB_SRST_FST, NULL);
528 528
529 rockchip_clk_of_add_provider(np, ctx); 529 rockchip_clk_of_add_provider(np, ctx);
530} 530}
531CLK_OF_DECLARE(rk1108_cru, "rockchip,rk1108-cru", rk1108_clk_init); 531CLK_OF_DECLARE(rv1108_cru, "rockchip,rv1108-cru", rv1108_clk_init);
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index 7c15473ea72b..ef601dded32c 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -34,20 +34,20 @@ struct clk;
34#define HIWORD_UPDATE(val, mask, shift) \ 34#define HIWORD_UPDATE(val, mask, shift) \
35 ((val) << (shift) | (mask) << ((shift) + 16)) 35 ((val) << (shift) | (mask) << ((shift) + 16))
36 36
37/* register positions shared by RK1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */ 37/* register positions shared by RV1108, RK2928, RK3036, RK3066, RK3188 and RK3228 */
38#define RK1108_PLL_CON(x) ((x) * 0x4) 38#define RV1108_PLL_CON(x) ((x) * 0x4)
39#define RK1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60) 39#define RV1108_CLKSEL_CON(x) ((x) * 0x4 + 0x60)
40#define RK1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120) 40#define RV1108_CLKGATE_CON(x) ((x) * 0x4 + 0x120)
41#define RK1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180) 41#define RV1108_SOFTRST_CON(x) ((x) * 0x4 + 0x180)
42#define RK1108_GLB_SRST_FST 0x1c0 42#define RV1108_GLB_SRST_FST 0x1c0
43#define RK1108_GLB_SRST_SND 0x1c4 43#define RV1108_GLB_SRST_SND 0x1c4
44#define RK1108_MISC_CON 0x1cc 44#define RV1108_MISC_CON 0x1cc
45#define RK1108_SDMMC_CON0 0x1d8 45#define RV1108_SDMMC_CON0 0x1d8
46#define RK1108_SDMMC_CON1 0x1dc 46#define RV1108_SDMMC_CON1 0x1dc
47#define RK1108_SDIO_CON0 0x1e0 47#define RV1108_SDIO_CON0 0x1e0
48#define RK1108_SDIO_CON1 0x1e4 48#define RV1108_SDIO_CON1 0x1e4
49#define RK1108_EMMC_CON0 0x1e8 49#define RV1108_EMMC_CON0 0x1e8
50#define RK1108_EMMC_CON1 0x1ec 50#define RV1108_EMMC_CON1 0x1ec
51 51
52#define RK2928_PLL_CON(x) ((x) * 0x4) 52#define RK2928_PLL_CON(x) ((x) * 0x4)
53#define RK2928_MODE_CON 0x40 53#define RK2928_MODE_CON 0x40
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 695bbf9ef428..64088e599404 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -1,6 +1,7 @@
1config SUNXI_CCU 1config SUNXI_CCU
2 bool "Clock support for Allwinner SoCs" 2 bool "Clock support for Allwinner SoCs"
3 depends on ARCH_SUNXI || COMPILE_TEST 3 depends on ARCH_SUNXI || COMPILE_TEST
4 select RESET_CONTROLLER
4 default ARCH_SUNXI 5 default ARCH_SUNXI
5 6
6if SUNXI_CCU 7if SUNXI_CCU
@@ -63,6 +64,7 @@ config SUN50I_A64_CCU
63 select SUNXI_CCU_MP 64 select SUNXI_CCU_MP
64 select SUNXI_CCU_PHASE 65 select SUNXI_CCU_PHASE
65 default ARM64 && ARCH_SUNXI 66 default ARM64 && ARCH_SUNXI
67 depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
66 68
67config SUN5I_CCU 69config SUN5I_CCU
68 bool "Support for the Allwinner sun5i family CCM" 70 bool "Support for the Allwinner sun5i family CCM"
@@ -74,16 +76,19 @@ config SUN5I_CCU
74 select SUNXI_CCU_MP 76 select SUNXI_CCU_MP
75 select SUNXI_CCU_PHASE 77 select SUNXI_CCU_PHASE
76 default MACH_SUN5I 78 default MACH_SUN5I
79 depends on MACH_SUN5I || COMPILE_TEST
77 80
78config SUN6I_A31_CCU 81config SUN6I_A31_CCU
79 bool "Support for the Allwinner A31/A31s CCU" 82 bool "Support for the Allwinner A31/A31s CCU"
80 select SUNXI_CCU_DIV 83 select SUNXI_CCU_DIV
81 select SUNXI_CCU_NK 84 select SUNXI_CCU_NK
82 select SUNXI_CCU_NKM 85 select SUNXI_CCU_NKM
86 select SUNXI_CCU_NKMP
83 select SUNXI_CCU_NM 87 select SUNXI_CCU_NM
84 select SUNXI_CCU_MP 88 select SUNXI_CCU_MP
85 select SUNXI_CCU_PHASE 89 select SUNXI_CCU_PHASE
86 default MACH_SUN6I 90 default MACH_SUN6I
91 depends on MACH_SUN6I || COMPILE_TEST
87 92
88config SUN8I_A23_CCU 93config SUN8I_A23_CCU
89 bool "Support for the Allwinner A23 CCU" 94 bool "Support for the Allwinner A23 CCU"
@@ -96,6 +101,7 @@ config SUN8I_A23_CCU
96 select SUNXI_CCU_MP 101 select SUNXI_CCU_MP
97 select SUNXI_CCU_PHASE 102 select SUNXI_CCU_PHASE
98 default MACH_SUN8I 103 default MACH_SUN8I
104 depends on MACH_SUN8I || COMPILE_TEST
99 105
100config SUN8I_A33_CCU 106config SUN8I_A33_CCU
101 bool "Support for the Allwinner A33 CCU" 107 bool "Support for the Allwinner A33 CCU"
@@ -108,6 +114,7 @@ config SUN8I_A33_CCU
108 select SUNXI_CCU_MP 114 select SUNXI_CCU_MP
109 select SUNXI_CCU_PHASE 115 select SUNXI_CCU_PHASE
110 default MACH_SUN8I 116 default MACH_SUN8I
117 depends on MACH_SUN8I || COMPILE_TEST
111 118
112config SUN8I_H3_CCU 119config SUN8I_H3_CCU
113 bool "Support for the Allwinner H3 CCU" 120 bool "Support for the Allwinner H3 CCU"
@@ -118,7 +125,8 @@ config SUN8I_H3_CCU
118 select SUNXI_CCU_NM 125 select SUNXI_CCU_NM
119 select SUNXI_CCU_MP 126 select SUNXI_CCU_MP
120 select SUNXI_CCU_PHASE 127 select SUNXI_CCU_PHASE
121 default MACH_SUN8I 128 default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
129 depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
122 130
123config SUN8I_V3S_CCU 131config SUN8I_V3S_CCU
124 bool "Support for the Allwinner V3s CCU" 132 bool "Support for the Allwinner V3s CCU"
@@ -130,15 +138,24 @@ config SUN8I_V3S_CCU
130 select SUNXI_CCU_MP 138 select SUNXI_CCU_MP
131 select SUNXI_CCU_PHASE 139 select SUNXI_CCU_PHASE
132 default MACH_SUN8I 140 default MACH_SUN8I
141 depends on MACH_SUN8I || COMPILE_TEST
133 142
134config SUN9I_A80_CCU 143config SUN9I_A80_CCU
135 bool "Support for the Allwinner A80 CCU" 144 bool "Support for the Allwinner A80 CCU"
136 select SUNXI_CCU_DIV 145 select SUNXI_CCU_DIV
146 select SUNXI_CCU_MULT
137 select SUNXI_CCU_GATE 147 select SUNXI_CCU_GATE
138 select SUNXI_CCU_NKMP 148 select SUNXI_CCU_NKMP
139 select SUNXI_CCU_NM 149 select SUNXI_CCU_NM
140 select SUNXI_CCU_MP 150 select SUNXI_CCU_MP
141 select SUNXI_CCU_PHASE 151 select SUNXI_CCU_PHASE
142 default MACH_SUN9I 152 default MACH_SUN9I
153 depends on MACH_SUN9I || COMPILE_TEST
154
155config SUN8I_R_CCU
156 bool "Support for Allwinner SoCs' PRCM CCUs"
157 select SUNXI_CCU_DIV
158 select SUNXI_CCU_GATE
159 default MACH_SUN8I || (ARCH_SUNXI && ARM64)
143 160
144endif 161endif
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 6feaac0c5600..0ec02fe14c50 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o
25obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o 25obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o
26obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o 26obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
27obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o 27obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o
28obj-$(CONFIG_SUN8I_R_CCU) += ccu-sun8i-r.o
28obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o 29obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o
29obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o 30obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o
30obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o 31obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index e3c084cc6da5..f54114c607df 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -566,7 +566,7 @@ static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
566 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); 566 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
567 567
568/* Fixed Factor clocks */ 568/* Fixed Factor clocks */
569static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 1, 2, 0); 569static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);
570 570
571/* We hardcode the divider to 4 for now */ 571/* We hardcode the divider to 4 for now */
572static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", 572static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
diff --git a/drivers/clk/sunxi-ng/ccu-sun5i.c b/drivers/clk/sunxi-ng/ccu-sun5i.c
index 06edaa523479..5c476f966a72 100644
--- a/drivers/clk/sunxi-ng/ccu-sun5i.c
+++ b/drivers/clk/sunxi-ng/ccu-sun5i.c
@@ -469,7 +469,7 @@ static const char * const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
469static const u8 csi_table[] = { 0, 1, 2, 5, 6 }; 469static const u8 csi_table[] = { 0, 1, 2, 5, 6 };
470static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi", 470static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi",
471 csi_parents, csi_table, 471 csi_parents, csi_table,
472 0x134, 0, 5, 24, 2, BIT(31), 0); 472 0x134, 0, 5, 24, 3, BIT(31), 0);
473 473
474static SUNXI_CCU_GATE(ve_clk, "ve", "pll-ve", 474static SUNXI_CCU_GATE(ve_clk, "ve", "pll-ve",
475 0x13c, BIT(31), CLK_SET_RATE_PARENT); 475 0x13c, BIT(31), CLK_SET_RATE_PARENT);
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
index 4c9a920ff4ab..89e68d29bf45 100644
--- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
@@ -608,7 +608,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", lcd_ch1_parents,
608 0x150, 0, 4, 24, 2, BIT(31), 608 0x150, 0, 4, 24, 2, BIT(31),
609 CLK_SET_RATE_PARENT); 609 CLK_SET_RATE_PARENT);
610 610
611static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(31), 0); 611static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(30), 0);
612 612
613static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0); 613static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
614 614
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
index a7b3c08ed0e2..8d38e6510e29 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
@@ -159,13 +159,17 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
159 BIT(28), /* lock */ 159 BIT(28), /* lock */
160 CLK_SET_RATE_UNGATE); 160 CLK_SET_RATE_UNGATE);
161 161
162/* TODO: Fix N */ 162static struct ccu_mult pll_ddr1_clk = {
163static SUNXI_CCU_N_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", 163 .enable = BIT(31),
164 "osc24M", 0x04c, 164 .lock = BIT(28),
165 8, 6, /* N */ 165 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 6, 0, 12, 0),
166 BIT(31), /* gate */ 166 .common = {
167 BIT(28), /* lock */ 167 .reg = 0x04c,
168 CLK_SET_RATE_UNGATE); 168 .hw.init = CLK_HW_INIT("pll-ddr1", "osc24M",
169 &ccu_mult_ops,
170 CLK_SET_RATE_UNGATE),
171 },
172};
169 173
170static const char * const cpux_parents[] = { "osc32k", "osc24M", 174static const char * const cpux_parents[] = { "osc32k", "osc24M",
171 "pll-cpux" , "pll-cpux" }; 175 "pll-cpux" , "pll-cpux" };
@@ -752,6 +756,13 @@ static const struct sunxi_ccu_desc sun8i_a33_ccu_desc = {
752 .num_resets = ARRAY_SIZE(sun8i_a33_ccu_resets), 756 .num_resets = ARRAY_SIZE(sun8i_a33_ccu_resets),
753}; 757};
754 758
759static struct ccu_pll_nb sun8i_a33_pll_cpu_nb = {
760 .common = &pll_cpux_clk.common,
761 /* copy from pll_cpux_clk */
762 .enable = BIT(31),
763 .lock = BIT(28),
764};
765
755static struct ccu_mux_nb sun8i_a33_cpu_nb = { 766static struct ccu_mux_nb sun8i_a33_cpu_nb = {
756 .common = &cpux_clk.common, 767 .common = &cpux_clk.common,
757 .cm = &cpux_clk.mux, 768 .cm = &cpux_clk.mux,
@@ -783,6 +794,10 @@ static void __init sun8i_a33_ccu_setup(struct device_node *node)
783 794
784 sunxi_ccu_probe(node, reg, &sun8i_a33_ccu_desc); 795 sunxi_ccu_probe(node, reg, &sun8i_a33_ccu_desc);
785 796
797 /* Gate then ungate PLL CPU after any rate changes */
798 ccu_pll_notifier_register(&sun8i_a33_pll_cpu_nb);
799
800 /* Reparent CPU during PLL CPU rate changes */
786 ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk, 801 ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
787 &sun8i_a33_cpu_nb); 802 &sun8i_a33_cpu_nb);
788} 803}
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index a26c8a19fe93..4cbc1b701b7c 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -300,8 +300,10 @@ static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
300 0x06c, BIT(18), 0); 300 0x06c, BIT(18), 0);
301static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 301static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
302 0x06c, BIT(19), 0); 302 0x06c, BIT(19), 0);
303static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2", 303static SUNXI_CCU_GATE(bus_scr0_clk, "bus-scr0", "apb2",
304 0x06c, BIT(20), 0); 304 0x06c, BIT(20), 0);
305static SUNXI_CCU_GATE(bus_scr1_clk, "bus-scr1", "apb2",
306 0x06c, BIT(21), 0);
305 307
306static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy", "ahb1", 308static SUNXI_CCU_GATE(bus_ephy_clk, "bus-ephy", "ahb1",
307 0x070, BIT(0), 0); 309 0x070, BIT(0), 0);
@@ -546,7 +548,7 @@ static struct ccu_common *sun8i_h3_ccu_clks[] = {
546 &bus_uart1_clk.common, 548 &bus_uart1_clk.common,
547 &bus_uart2_clk.common, 549 &bus_uart2_clk.common,
548 &bus_uart3_clk.common, 550 &bus_uart3_clk.common,
549 &bus_scr_clk.common, 551 &bus_scr0_clk.common,
550 &bus_ephy_clk.common, 552 &bus_ephy_clk.common,
551 &bus_dbg_clk.common, 553 &bus_dbg_clk.common,
552 &ths_clk.common, 554 &ths_clk.common,
@@ -597,6 +599,114 @@ static struct ccu_common *sun8i_h3_ccu_clks[] = {
597 &gpu_clk.common, 599 &gpu_clk.common,
598}; 600};
599 601
602static struct ccu_common *sun50i_h5_ccu_clks[] = {
603 &pll_cpux_clk.common,
604 &pll_audio_base_clk.common,
605 &pll_video_clk.common,
606 &pll_ve_clk.common,
607 &pll_ddr_clk.common,
608 &pll_periph0_clk.common,
609 &pll_gpu_clk.common,
610 &pll_periph1_clk.common,
611 &pll_de_clk.common,
612 &cpux_clk.common,
613 &axi_clk.common,
614 &ahb1_clk.common,
615 &apb1_clk.common,
616 &apb2_clk.common,
617 &ahb2_clk.common,
618 &bus_ce_clk.common,
619 &bus_dma_clk.common,
620 &bus_mmc0_clk.common,
621 &bus_mmc1_clk.common,
622 &bus_mmc2_clk.common,
623 &bus_nand_clk.common,
624 &bus_dram_clk.common,
625 &bus_emac_clk.common,
626 &bus_ts_clk.common,
627 &bus_hstimer_clk.common,
628 &bus_spi0_clk.common,
629 &bus_spi1_clk.common,
630 &bus_otg_clk.common,
631 &bus_ehci0_clk.common,
632 &bus_ehci1_clk.common,
633 &bus_ehci2_clk.common,
634 &bus_ehci3_clk.common,
635 &bus_ohci0_clk.common,
636 &bus_ohci1_clk.common,
637 &bus_ohci2_clk.common,
638 &bus_ohci3_clk.common,
639 &bus_ve_clk.common,
640 &bus_tcon0_clk.common,
641 &bus_tcon1_clk.common,
642 &bus_deinterlace_clk.common,
643 &bus_csi_clk.common,
644 &bus_tve_clk.common,
645 &bus_hdmi_clk.common,
646 &bus_de_clk.common,
647 &bus_gpu_clk.common,
648 &bus_msgbox_clk.common,
649 &bus_spinlock_clk.common,
650 &bus_codec_clk.common,
651 &bus_spdif_clk.common,
652 &bus_pio_clk.common,
653 &bus_ths_clk.common,
654 &bus_i2s0_clk.common,
655 &bus_i2s1_clk.common,
656 &bus_i2s2_clk.common,
657 &bus_i2c0_clk.common,
658 &bus_i2c1_clk.common,
659 &bus_i2c2_clk.common,
660 &bus_uart0_clk.common,
661 &bus_uart1_clk.common,
662 &bus_uart2_clk.common,
663 &bus_uart3_clk.common,
664 &bus_scr0_clk.common,
665 &bus_scr1_clk.common,
666 &bus_ephy_clk.common,
667 &bus_dbg_clk.common,
668 &ths_clk.common,
669 &nand_clk.common,
670 &mmc0_clk.common,
671 &mmc1_clk.common,
672 &mmc2_clk.common,
673 &ts_clk.common,
674 &ce_clk.common,
675 &spi0_clk.common,
676 &spi1_clk.common,
677 &i2s0_clk.common,
678 &i2s1_clk.common,
679 &i2s2_clk.common,
680 &spdif_clk.common,
681 &usb_phy0_clk.common,
682 &usb_phy1_clk.common,
683 &usb_phy2_clk.common,
684 &usb_phy3_clk.common,
685 &usb_ohci0_clk.common,
686 &usb_ohci1_clk.common,
687 &usb_ohci2_clk.common,
688 &usb_ohci3_clk.common,
689 &dram_clk.common,
690 &dram_ve_clk.common,
691 &dram_csi_clk.common,
692 &dram_deinterlace_clk.common,
693 &dram_ts_clk.common,
694 &de_clk.common,
695 &tcon_clk.common,
696 &tve_clk.common,
697 &deinterlace_clk.common,
698 &csi_misc_clk.common,
699 &csi_sclk_clk.common,
700 &csi_mclk_clk.common,
701 &ve_clk.common,
702 &ac_dig_clk.common,
703 &avs_clk.common,
704 &hdmi_clk.common,
705 &hdmi_ddc_clk.common,
706 &mbus_clk.common,
707 &gpu_clk.common,
708};
709
600/* We hardcode the divider to 4 for now */ 710/* We hardcode the divider to 4 for now */
601static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", 711static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
602 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); 712 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
@@ -677,7 +787,7 @@ static struct clk_hw_onecell_data sun8i_h3_hw_clks = {
677 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, 787 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
678 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, 788 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
679 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, 789 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
680 [CLK_BUS_SCR] = &bus_scr_clk.common.hw, 790 [CLK_BUS_SCR0] = &bus_scr0_clk.common.hw,
681 [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw, 791 [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
682 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, 792 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
683 [CLK_THS] = &ths_clk.common.hw, 793 [CLK_THS] = &ths_clk.common.hw,
@@ -727,7 +837,123 @@ static struct clk_hw_onecell_data sun8i_h3_hw_clks = {
727 [CLK_MBUS] = &mbus_clk.common.hw, 837 [CLK_MBUS] = &mbus_clk.common.hw,
728 [CLK_GPU] = &gpu_clk.common.hw, 838 [CLK_GPU] = &gpu_clk.common.hw,
729 }, 839 },
730 .num = CLK_NUMBER, 840 .num = CLK_NUMBER_H3,
841};
842
843static struct clk_hw_onecell_data sun50i_h5_hw_clks = {
844 .hws = {
845 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
846 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
847 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
848 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
849 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
850 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
851 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
852 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
853 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
854 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
855 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
856 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
857 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
858 [CLK_PLL_DE] = &pll_de_clk.common.hw,
859 [CLK_CPUX] = &cpux_clk.common.hw,
860 [CLK_AXI] = &axi_clk.common.hw,
861 [CLK_AHB1] = &ahb1_clk.common.hw,
862 [CLK_APB1] = &apb1_clk.common.hw,
863 [CLK_APB2] = &apb2_clk.common.hw,
864 [CLK_AHB2] = &ahb2_clk.common.hw,
865 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
866 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
867 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
868 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
869 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
870 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
871 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
872 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
873 [CLK_BUS_TS] = &bus_ts_clk.common.hw,
874 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
875 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
876 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
877 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
878 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
879 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw,
880 [CLK_BUS_EHCI2] = &bus_ehci2_clk.common.hw,
881 [CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw,
882 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
883 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw,
884 [CLK_BUS_OHCI2] = &bus_ohci2_clk.common.hw,
885 [CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw,
886 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
887 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw,
888 [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw,
889 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
890 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
891 [CLK_BUS_TVE] = &bus_tve_clk.common.hw,
892 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
893 [CLK_BUS_DE] = &bus_de_clk.common.hw,
894 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
895 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
896 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
897 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
898 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
899 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
900 [CLK_BUS_THS] = &bus_ths_clk.common.hw,
901 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
902 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
903 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
904 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
905 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
906 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
907 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
908 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
909 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
910 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
911 [CLK_BUS_SCR0] = &bus_scr0_clk.common.hw,
912 [CLK_BUS_SCR1] = &bus_scr1_clk.common.hw,
913 [CLK_BUS_EPHY] = &bus_ephy_clk.common.hw,
914 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
915 [CLK_THS] = &ths_clk.common.hw,
916 [CLK_NAND] = &nand_clk.common.hw,
917 [CLK_MMC0] = &mmc0_clk.common.hw,
918 [CLK_MMC1] = &mmc1_clk.common.hw,
919 [CLK_MMC2] = &mmc2_clk.common.hw,
920 [CLK_TS] = &ts_clk.common.hw,
921 [CLK_CE] = &ce_clk.common.hw,
922 [CLK_SPI0] = &spi0_clk.common.hw,
923 [CLK_SPI1] = &spi1_clk.common.hw,
924 [CLK_I2S0] = &i2s0_clk.common.hw,
925 [CLK_I2S1] = &i2s1_clk.common.hw,
926 [CLK_I2S2] = &i2s2_clk.common.hw,
927 [CLK_SPDIF] = &spdif_clk.common.hw,
928 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
929 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
930 [CLK_USB_PHY2] = &usb_phy2_clk.common.hw,
931 [CLK_USB_PHY3] = &usb_phy3_clk.common.hw,
932 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
933 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw,
934 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw,
935 [CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw,
936 [CLK_DRAM] = &dram_clk.common.hw,
937 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
938 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
939 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw,
940 [CLK_DRAM_TS] = &dram_ts_clk.common.hw,
941 [CLK_DE] = &de_clk.common.hw,
942 [CLK_TCON0] = &tcon_clk.common.hw,
943 [CLK_TVE] = &tve_clk.common.hw,
944 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
945 [CLK_CSI_MISC] = &csi_misc_clk.common.hw,
946 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
947 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
948 [CLK_VE] = &ve_clk.common.hw,
949 [CLK_AC_DIG] = &ac_dig_clk.common.hw,
950 [CLK_AVS] = &avs_clk.common.hw,
951 [CLK_HDMI] = &hdmi_clk.common.hw,
952 [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw,
953 [CLK_MBUS] = &mbus_clk.common.hw,
954 [CLK_GPU] = &gpu_clk.common.hw,
955 },
956 .num = CLK_NUMBER_H5,
731}; 957};
732 958
733static struct ccu_reset_map sun8i_h3_ccu_resets[] = { 959static struct ccu_reset_map sun8i_h3_ccu_resets[] = {
@@ -790,7 +1016,71 @@ static struct ccu_reset_map sun8i_h3_ccu_resets[] = {
790 [RST_BUS_UART1] = { 0x2d8, BIT(17) }, 1016 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
791 [RST_BUS_UART2] = { 0x2d8, BIT(18) }, 1017 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
792 [RST_BUS_UART3] = { 0x2d8, BIT(19) }, 1018 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
793 [RST_BUS_SCR] = { 0x2d8, BIT(20) }, 1019 [RST_BUS_SCR0] = { 0x2d8, BIT(20) },
1020};
1021
1022static struct ccu_reset_map sun50i_h5_ccu_resets[] = {
1023 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
1024 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
1025 [RST_USB_PHY2] = { 0x0cc, BIT(2) },
1026 [RST_USB_PHY3] = { 0x0cc, BIT(3) },
1027
1028 [RST_MBUS] = { 0x0fc, BIT(31) },
1029
1030 [RST_BUS_CE] = { 0x2c0, BIT(5) },
1031 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
1032 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
1033 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
1034 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
1035 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
1036 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
1037 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
1038 [RST_BUS_TS] = { 0x2c0, BIT(18) },
1039 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
1040 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
1041 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
1042 [RST_BUS_OTG] = { 0x2c0, BIT(23) },
1043 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) },
1044 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) },
1045 [RST_BUS_EHCI2] = { 0x2c0, BIT(26) },
1046 [RST_BUS_EHCI3] = { 0x2c0, BIT(27) },
1047 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) },
1048 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) },
1049 [RST_BUS_OHCI2] = { 0x2c0, BIT(30) },
1050 [RST_BUS_OHCI3] = { 0x2c0, BIT(31) },
1051
1052 [RST_BUS_VE] = { 0x2c4, BIT(0) },
1053 [RST_BUS_TCON0] = { 0x2c4, BIT(3) },
1054 [RST_BUS_TCON1] = { 0x2c4, BIT(4) },
1055 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
1056 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
1057 [RST_BUS_TVE] = { 0x2c4, BIT(9) },
1058 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
1059 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
1060 [RST_BUS_DE] = { 0x2c4, BIT(12) },
1061 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
1062 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
1063 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
1064 [RST_BUS_DBG] = { 0x2c4, BIT(31) },
1065
1066 [RST_BUS_EPHY] = { 0x2c8, BIT(2) },
1067
1068 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
1069 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
1070 [RST_BUS_THS] = { 0x2d0, BIT(8) },
1071 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
1072 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
1073 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
1074
1075 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
1076 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
1077 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
1078 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
1079 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
1080 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
1081 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
1082 [RST_BUS_SCR0] = { 0x2d8, BIT(20) },
1083 [RST_BUS_SCR1] = { 0x2d8, BIT(20) },
794}; 1084};
795 1085
796static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = { 1086static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
@@ -803,6 +1093,16 @@ static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
803 .num_resets = ARRAY_SIZE(sun8i_h3_ccu_resets), 1093 .num_resets = ARRAY_SIZE(sun8i_h3_ccu_resets),
804}; 1094};
805 1095
1096static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
1097 .ccu_clks = sun50i_h5_ccu_clks,
1098 .num_ccu_clks = ARRAY_SIZE(sun50i_h5_ccu_clks),
1099
1100 .hw_clks = &sun50i_h5_hw_clks,
1101
1102 .resets = sun50i_h5_ccu_resets,
1103 .num_resets = ARRAY_SIZE(sun50i_h5_ccu_resets),
1104};
1105
806static struct ccu_mux_nb sun8i_h3_cpu_nb = { 1106static struct ccu_mux_nb sun8i_h3_cpu_nb = {
807 .common = &cpux_clk.common, 1107 .common = &cpux_clk.common,
808 .cm = &cpux_clk.mux, 1108 .cm = &cpux_clk.mux,
@@ -810,7 +1110,8 @@ static struct ccu_mux_nb sun8i_h3_cpu_nb = {
810 .bypass_index = 1, /* index of 24 MHz oscillator */ 1110 .bypass_index = 1, /* index of 24 MHz oscillator */
811}; 1111};
812 1112
813static void __init sun8i_h3_ccu_setup(struct device_node *node) 1113static void __init sunxi_h3_h5_ccu_init(struct device_node *node,
1114 const struct sunxi_ccu_desc *desc)
814{ 1115{
815 void __iomem *reg; 1116 void __iomem *reg;
816 u32 val; 1117 u32 val;
@@ -827,10 +1128,22 @@ static void __init sun8i_h3_ccu_setup(struct device_node *node)
827 val &= ~GENMASK(19, 16); 1128 val &= ~GENMASK(19, 16);
828 writel(val | (3 << 16), reg + SUN8I_H3_PLL_AUDIO_REG); 1129 writel(val | (3 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
829 1130
830 sunxi_ccu_probe(node, reg, &sun8i_h3_ccu_desc); 1131 sunxi_ccu_probe(node, reg, desc);
831 1132
832 ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk, 1133 ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
833 &sun8i_h3_cpu_nb); 1134 &sun8i_h3_cpu_nb);
834} 1135}
1136
1137static void __init sun8i_h3_ccu_setup(struct device_node *node)
1138{
1139 sunxi_h3_h5_ccu_init(node, &sun8i_h3_ccu_desc);
1140}
835CLK_OF_DECLARE(sun8i_h3_ccu, "allwinner,sun8i-h3-ccu", 1141CLK_OF_DECLARE(sun8i_h3_ccu, "allwinner,sun8i-h3-ccu",
836 sun8i_h3_ccu_setup); 1142 sun8i_h3_ccu_setup);
1143
1144static void __init sun50i_h5_ccu_setup(struct device_node *node)
1145{
1146 sunxi_h3_h5_ccu_init(node, &sun50i_h5_ccu_desc);
1147}
1148CLK_OF_DECLARE(sun50i_h5_ccu, "allwinner,sun50i-h5-ccu",
1149 sun50i_h5_ccu_setup);
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
index 78be712c7487..85973d1e8165 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.h
@@ -57,6 +57,7 @@
57 57
58/* And the GPU module clock is exported */ 58/* And the GPU module clock is exported */
59 59
60#define CLK_NUMBER (CLK_GPU + 1) 60#define CLK_NUMBER_H3 (CLK_GPU + 1)
61#define CLK_NUMBER_H5 (CLK_BUS_SCR1 + 1)
61 62
62#endif /* _CCU_SUN8I_H3_H_ */ 63#endif /* _CCU_SUN8I_H3_H_ */
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
new file mode 100644
index 000000000000..0d027d53dbdf
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
@@ -0,0 +1,213 @@
1/*
2 * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/clk-provider.h>
15#include <linux/of_address.h>
16#include <linux/platform_device.h>
17
18#include "ccu_common.h"
19#include "ccu_reset.h"
20
21#include "ccu_div.h"
22#include "ccu_gate.h"
23#include "ccu_mp.h"
24#include "ccu_nm.h"
25
26#include "ccu-sun8i-r.h"
27
28static const char * const ar100_parents[] = { "osc32k", "osc24M",
29 "pll-periph0", "iosc" };
30
31static struct ccu_div ar100_clk = {
32 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
33
34 .mux = {
35 .shift = 16,
36 .width = 2,
37
38 .variable_prediv = {
39 .index = 2,
40 .shift = 8,
41 .width = 5,
42 },
43 },
44
45 .common = {
46 .reg = 0x00,
47 .features = CCU_FEATURE_VARIABLE_PREDIV,
48 .hw.init = CLK_HW_INIT_PARENTS("ar100",
49 ar100_parents,
50 &ccu_div_ops,
51 0),
52 },
53};
54
55static CLK_FIXED_FACTOR(ahb0_clk, "ahb0", "ar100", 1, 1, 0);
56
57static struct ccu_div apb0_clk = {
58 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
59
60 .common = {
61 .reg = 0x0c,
62 .hw.init = CLK_HW_INIT("apb0",
63 "ahb0",
64 &ccu_div_ops,
65 0),
66 },
67};
68
69static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0",
70 0x28, BIT(0), 0);
71static SUNXI_CCU_GATE(apb0_ir_clk, "apb0-ir", "apb0",
72 0x28, BIT(1), 0);
73static SUNXI_CCU_GATE(apb0_timer_clk, "apb0-timer", "apb0",
74 0x28, BIT(2), 0);
75static SUNXI_CCU_GATE(apb0_rsb_clk, "apb0-rsb", "apb0",
76 0x28, BIT(3), 0);
77static SUNXI_CCU_GATE(apb0_uart_clk, "apb0-uart", "apb0",
78 0x28, BIT(4), 0);
79static SUNXI_CCU_GATE(apb0_i2c_clk, "apb0-i2c", "apb0",
80 0x28, BIT(6), 0);
81static SUNXI_CCU_GATE(apb0_twd_clk, "apb0-twd", "apb0",
82 0x28, BIT(7), 0);
83
84static const char * const r_mod0_default_parents[] = { "osc32K", "osc24M" };
85static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
86 r_mod0_default_parents, 0x54,
87 0, 4, /* M */
88 16, 2, /* P */
89 24, 2, /* mux */
90 BIT(31), /* gate */
91 0);
92
93static struct ccu_common *sun8i_h3_r_ccu_clks[] = {
94 &ar100_clk.common,
95 &apb0_clk.common,
96 &apb0_pio_clk.common,
97 &apb0_ir_clk.common,
98 &apb0_timer_clk.common,
99 &apb0_uart_clk.common,
100 &apb0_i2c_clk.common,
101 &apb0_twd_clk.common,
102 &ir_clk.common,
103};
104
105static struct ccu_common *sun50i_a64_r_ccu_clks[] = {
106 &ar100_clk.common,
107 &apb0_clk.common,
108 &apb0_pio_clk.common,
109 &apb0_ir_clk.common,
110 &apb0_timer_clk.common,
111 &apb0_rsb_clk.common,
112 &apb0_uart_clk.common,
113 &apb0_i2c_clk.common,
114 &apb0_twd_clk.common,
115 &ir_clk.common,
116};
117
118static struct clk_hw_onecell_data sun8i_h3_r_hw_clks = {
119 .hws = {
120 [CLK_AR100] = &ar100_clk.common.hw,
121 [CLK_AHB0] = &ahb0_clk.hw,
122 [CLK_APB0] = &apb0_clk.common.hw,
123 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
124 [CLK_APB0_IR] = &apb0_ir_clk.common.hw,
125 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw,
126 [CLK_APB0_UART] = &apb0_uart_clk.common.hw,
127 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw,
128 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw,
129 [CLK_IR] = &ir_clk.common.hw,
130 },
131 .num = CLK_NUMBER,
132};
133
134static struct clk_hw_onecell_data sun50i_a64_r_hw_clks = {
135 .hws = {
136 [CLK_AR100] = &ar100_clk.common.hw,
137 [CLK_AHB0] = &ahb0_clk.hw,
138 [CLK_APB0] = &apb0_clk.common.hw,
139 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw,
140 [CLK_APB0_IR] = &apb0_ir_clk.common.hw,
141 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw,
142 [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw,
143 [CLK_APB0_UART] = &apb0_uart_clk.common.hw,
144 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw,
145 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw,
146 [CLK_IR] = &ir_clk.common.hw,
147 },
148 .num = CLK_NUMBER,
149};
150
151static struct ccu_reset_map sun8i_h3_r_ccu_resets[] = {
152 [RST_APB0_IR] = { 0xb0, BIT(1) },
153 [RST_APB0_TIMER] = { 0xb0, BIT(2) },
154 [RST_APB0_UART] = { 0xb0, BIT(4) },
155 [RST_APB0_I2C] = { 0xb0, BIT(6) },
156};
157
158static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = {
159 [RST_APB0_IR] = { 0xb0, BIT(1) },
160 [RST_APB0_TIMER] = { 0xb0, BIT(2) },
161 [RST_APB0_RSB] = { 0xb0, BIT(3) },
162 [RST_APB0_UART] = { 0xb0, BIT(4) },
163 [RST_APB0_I2C] = { 0xb0, BIT(6) },
164};
165
166static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = {
167 .ccu_clks = sun8i_h3_r_ccu_clks,
168 .num_ccu_clks = ARRAY_SIZE(sun8i_h3_r_ccu_clks),
169
170 .hw_clks = &sun8i_h3_r_hw_clks,
171
172 .resets = sun8i_h3_r_ccu_resets,
173 .num_resets = ARRAY_SIZE(sun8i_h3_r_ccu_resets),
174};
175
176static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = {
177 .ccu_clks = sun50i_a64_r_ccu_clks,
178 .num_ccu_clks = ARRAY_SIZE(sun50i_a64_r_ccu_clks),
179
180 .hw_clks = &sun50i_a64_r_hw_clks,
181
182 .resets = sun50i_a64_r_ccu_resets,
183 .num_resets = ARRAY_SIZE(sun50i_a64_r_ccu_resets),
184};
185
186static void __init sunxi_r_ccu_init(struct device_node *node,
187 const struct sunxi_ccu_desc *desc)
188{
189 void __iomem *reg;
190
191 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
192 if (IS_ERR(reg)) {
193 pr_err("%s: Could not map the clock registers\n",
194 of_node_full_name(node));
195 return;
196 }
197
198 sunxi_ccu_probe(node, reg, desc);
199}
200
201static void __init sun8i_h3_r_ccu_setup(struct device_node *node)
202{
203 sunxi_r_ccu_init(node, &sun8i_h3_r_ccu_desc);
204}
205CLK_OF_DECLARE(sun8i_h3_r_ccu, "allwinner,sun8i-h3-r-ccu",
206 sun8i_h3_r_ccu_setup);
207
208static void __init sun50i_a64_r_ccu_setup(struct device_node *node)
209{
210 sunxi_r_ccu_init(node, &sun50i_a64_r_ccu_desc);
211}
212CLK_OF_DECLARE(sun50i_a64_r_ccu, "allwinner,sun50i-a64-r-ccu",
213 sun50i_a64_r_ccu_setup);
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.h b/drivers/clk/sunxi-ng/ccu-sun8i-r.h
new file mode 100644
index 000000000000..eaa431fd1d8f
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.h
@@ -0,0 +1,27 @@
1/*
2 * Copyright 2016 Icenowy <icenowy@aosc.xyz>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef _CCU_SUN8I_R_H
16#define _CCU_SUN8I_R_H_
17
18#include <dt-bindings/clock/sun8i-r-ccu.h>
19#include <dt-bindings/reset/sun8i-r-ccu.h>
20
21/* AHB/APB bus clocks are not exported */
22#define CLK_AHB0 1
23#define CLK_APB0 2
24
25#define CLK_NUMBER (CLK_APB0_TWD + 1)
26
27#endif /* _CCU_SUN8I_R_H */
diff --git a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
index e13e313ce4f5..51f6d495de5b 100644
--- a/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
+++ b/drivers/clk/sunxi-ng/ccu-sun9i-a80.c
@@ -29,41 +29,41 @@
29 29
30#define CCU_SUN9I_LOCK_REG 0x09c 30#define CCU_SUN9I_LOCK_REG 0x09c
31 31
32static struct clk_div_table pll_cpux_p_div_table[] = {
33 { .val = 0, .div = 1 },
34 { .val = 1, .div = 4 },
35 { /* Sentinel */ },
36};
37
38/* 32/*
39 * The CPU PLLs are actually NP clocks, but P is /1 or /4, so here we 33 * The CPU PLLs are actually NP clocks, with P being /1 or /4. However
40 * use the NM clocks with a divider table for M. 34 * P should only be used for output frequencies lower than 228 MHz.
35 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
36 *
37 * For now we can just model it as a multiplier clock, and force P to /1.
41 */ 38 */
42static struct ccu_nm pll_c0cpux_clk = { 39#define SUN9I_A80_PLL_C0CPUX_REG 0x000
40#define SUN9I_A80_PLL_C1CPUX_REG 0x004
41
42static struct ccu_mult pll_c0cpux_clk = {
43 .enable = BIT(31), 43 .enable = BIT(31),
44 .lock = BIT(0), 44 .lock = BIT(0),
45 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 45 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
46 .m = _SUNXI_CCU_DIV_TABLE(16, 1, pll_cpux_p_div_table),
47 .common = { 46 .common = {
48 .reg = 0x000, 47 .reg = SUN9I_A80_PLL_C0CPUX_REG,
49 .lock_reg = CCU_SUN9I_LOCK_REG, 48 .lock_reg = CCU_SUN9I_LOCK_REG,
50 .features = CCU_FEATURE_LOCK_REG, 49 .features = CCU_FEATURE_LOCK_REG,
51 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M", 50 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
52 &ccu_nm_ops, CLK_SET_RATE_UNGATE), 51 &ccu_mult_ops,
52 CLK_SET_RATE_UNGATE),
53 }, 53 },
54}; 54};
55 55
56static struct ccu_nm pll_c1cpux_clk = { 56static struct ccu_mult pll_c1cpux_clk = {
57 .enable = BIT(31), 57 .enable = BIT(31),
58 .lock = BIT(1), 58 .lock = BIT(1),
59 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 59 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
60 .m = _SUNXI_CCU_DIV_TABLE(16, 1, pll_cpux_p_div_table),
61 .common = { 60 .common = {
62 .reg = 0x004, 61 .reg = SUN9I_A80_PLL_C1CPUX_REG,
63 .lock_reg = CCU_SUN9I_LOCK_REG, 62 .lock_reg = CCU_SUN9I_LOCK_REG,
64 .features = CCU_FEATURE_LOCK_REG, 63 .features = CCU_FEATURE_LOCK_REG,
65 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M", 64 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
66 &ccu_nm_ops, CLK_SET_RATE_UNGATE), 65 &ccu_mult_ops,
66 CLK_SET_RATE_UNGATE),
67 }, 67 },
68}; 68};
69 69
@@ -1189,6 +1189,36 @@ static const struct sunxi_ccu_desc sun9i_a80_ccu_desc = {
1189 .num_resets = ARRAY_SIZE(sun9i_a80_ccu_resets), 1189 .num_resets = ARRAY_SIZE(sun9i_a80_ccu_resets),
1190}; 1190};
1191 1191
1192#define SUN9I_A80_PLL_P_SHIFT 16
1193#define SUN9I_A80_PLL_N_SHIFT 8
1194#define SUN9I_A80_PLL_N_WIDTH 8
1195
1196static void sun9i_a80_cpu_pll_fixup(void __iomem *reg)
1197{
1198 u32 val = readl(reg);
1199
1200 /* bail out if P divider is not used */
1201 if (!(val & BIT(SUN9I_A80_PLL_P_SHIFT)))
1202 return;
1203
1204 /*
1205 * If P is used, output should be less than 288 MHz. When we
1206 * set P to 1, we should also decrease the multiplier so the
1207 * output doesn't go out of range, but not too much such that
1208 * the multiplier stays above 12, the minimal operation value.
1209 *
1210 * To keep it simple, set the multiplier to 17, the reset value.
1211 */
1212 val &= ~GENMASK(SUN9I_A80_PLL_N_SHIFT + SUN9I_A80_PLL_N_WIDTH - 1,
1213 SUN9I_A80_PLL_N_SHIFT);
1214 val |= 17 << SUN9I_A80_PLL_N_SHIFT;
1215
1216 /* And clear P */
1217 val &= ~BIT(SUN9I_A80_PLL_P_SHIFT);
1218
1219 writel(val, reg);
1220}
1221
1192static int sun9i_a80_ccu_probe(struct platform_device *pdev) 1222static int sun9i_a80_ccu_probe(struct platform_device *pdev)
1193{ 1223{
1194 struct resource *res; 1224 struct resource *res;
@@ -1205,6 +1235,10 @@ static int sun9i_a80_ccu_probe(struct platform_device *pdev)
1205 val &= (BIT(16) & BIT(18)); 1235 val &= (BIT(16) & BIT(18));
1206 writel(val, reg + SUN9I_A80_PLL_AUDIO_REG); 1236 writel(val, reg + SUN9I_A80_PLL_AUDIO_REG);
1207 1237
1238 /* Enforce P = 1 for both CPU cluster PLLs */
1239 sun9i_a80_cpu_pll_fixup(reg + SUN9I_A80_PLL_C0CPUX_REG);
1240 sun9i_a80_cpu_pll_fixup(reg + SUN9I_A80_PLL_C1CPUX_REG);
1241
1208 return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun9i_a80_ccu_desc); 1242 return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun9i_a80_ccu_desc);
1209} 1243}
1210 1244
diff --git a/drivers/clk/sunxi-ng/ccu_common.c b/drivers/clk/sunxi-ng/ccu_common.c
index 8a47bafd7890..40aac316128f 100644
--- a/drivers/clk/sunxi-ng/ccu_common.c
+++ b/drivers/clk/sunxi-ng/ccu_common.c
@@ -14,11 +14,13 @@
14 * GNU General Public License for more details. 14 * GNU General Public License for more details.
15 */ 15 */
16 16
17#include <linux/clk.h>
17#include <linux/clk-provider.h> 18#include <linux/clk-provider.h>
18#include <linux/iopoll.h> 19#include <linux/iopoll.h>
19#include <linux/slab.h> 20#include <linux/slab.h>
20 21
21#include "ccu_common.h" 22#include "ccu_common.h"
23#include "ccu_gate.h"
22#include "ccu_reset.h" 24#include "ccu_reset.h"
23 25
24static DEFINE_SPINLOCK(ccu_lock); 26static DEFINE_SPINLOCK(ccu_lock);
@@ -39,6 +41,53 @@ void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock)
39 WARN_ON(readl_relaxed_poll_timeout(addr, reg, reg & lock, 100, 70000)); 41 WARN_ON(readl_relaxed_poll_timeout(addr, reg, reg & lock, 100, 70000));
40} 42}
41 43
44/*
45 * This clock notifier is called when the frequency of a PLL clock is
46 * changed. In common PLL designs, changes to the dividers take effect
47 * almost immediately, while changes to the multipliers (implemented
48 * as dividers in the feedback loop) take a few cycles to work into
49 * the feedback loop for the PLL to stablize.
50 *
51 * Sometimes when the PLL clock rate is changed, the decrease in the
52 * divider is too much for the decrease in the multiplier to catch up.
53 * The PLL clock rate will spike, and in some cases, might lock up
54 * completely.
55 *
56 * This notifier callback will gate and then ungate the clock,
57 * effectively resetting it, so it proceeds to work. Care must be
58 * taken to reparent consumers to other temporary clocks during the
59 * rate change, and that this notifier callback must be the first
60 * to be registered.
61 */
62static int ccu_pll_notifier_cb(struct notifier_block *nb,
63 unsigned long event, void *data)
64{
65 struct ccu_pll_nb *pll = to_ccu_pll_nb(nb);
66 int ret = 0;
67
68 if (event != POST_RATE_CHANGE)
69 goto out;
70
71 ccu_gate_helper_disable(pll->common, pll->enable);
72
73 ret = ccu_gate_helper_enable(pll->common, pll->enable);
74 if (ret)
75 goto out;
76
77 ccu_helper_wait_for_lock(pll->common, pll->lock);
78
79out:
80 return notifier_from_errno(ret);
81}
82
83int ccu_pll_notifier_register(struct ccu_pll_nb *pll_nb)
84{
85 pll_nb->clk_nb.notifier_call = ccu_pll_notifier_cb;
86
87 return clk_notifier_register(pll_nb->common->hw.clk,
88 &pll_nb->clk_nb);
89}
90
42int sunxi_ccu_probe(struct device_node *node, void __iomem *reg, 91int sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
43 const struct sunxi_ccu_desc *desc) 92 const struct sunxi_ccu_desc *desc)
44{ 93{
@@ -63,8 +112,8 @@ int sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
63 112
64 ret = clk_hw_register(NULL, hw); 113 ret = clk_hw_register(NULL, hw);
65 if (ret) { 114 if (ret) {
66 pr_err("Couldn't register clock %s\n", 115 pr_err("Couldn't register clock %d - %s\n",
67 clk_hw_get_name(hw)); 116 i, clk_hw_get_name(hw));
68 goto err_clk_unreg; 117 goto err_clk_unreg;
69 } 118 }
70 } 119 }
diff --git a/drivers/clk/sunxi-ng/ccu_common.h b/drivers/clk/sunxi-ng/ccu_common.h
index 73d81dc58fc5..d6fdd7a789aa 100644
--- a/drivers/clk/sunxi-ng/ccu_common.h
+++ b/drivers/clk/sunxi-ng/ccu_common.h
@@ -83,6 +83,18 @@ struct sunxi_ccu_desc {
83 83
84void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock); 84void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock);
85 85
86struct ccu_pll_nb {
87 struct notifier_block clk_nb;
88 struct ccu_common *common;
89
90 u32 enable;
91 u32 lock;
92};
93
94#define to_ccu_pll_nb(_nb) container_of(_nb, struct ccu_pll_nb, clk_nb)
95
96int ccu_pll_notifier_register(struct ccu_pll_nb *pll_nb);
97
86int sunxi_ccu_probe(struct device_node *node, void __iomem *reg, 98int sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
87 const struct sunxi_ccu_desc *desc); 99 const struct sunxi_ccu_desc *desc);
88 100
diff --git a/drivers/clk/sunxi-ng/ccu_gate.c b/drivers/clk/sunxi-ng/ccu_gate.c
index 8a81f9d4a89f..cd069d5da215 100644
--- a/drivers/clk/sunxi-ng/ccu_gate.c
+++ b/drivers/clk/sunxi-ng/ccu_gate.c
@@ -75,8 +75,55 @@ static int ccu_gate_is_enabled(struct clk_hw *hw)
75 return ccu_gate_helper_is_enabled(&cg->common, cg->enable); 75 return ccu_gate_helper_is_enabled(&cg->common, cg->enable);
76} 76}
77 77
78static unsigned long ccu_gate_recalc_rate(struct clk_hw *hw,
79 unsigned long parent_rate)
80{
81 struct ccu_gate *cg = hw_to_ccu_gate(hw);
82 unsigned long rate = parent_rate;
83
84 if (cg->common.features & CCU_FEATURE_ALL_PREDIV)
85 rate /= cg->common.prediv;
86
87 return rate;
88}
89
90static long ccu_gate_round_rate(struct clk_hw *hw, unsigned long rate,
91 unsigned long *prate)
92{
93 struct ccu_gate *cg = hw_to_ccu_gate(hw);
94 int div = 1;
95
96 if (cg->common.features & CCU_FEATURE_ALL_PREDIV)
97 div = cg->common.prediv;
98
99 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
100 unsigned long best_parent = rate;
101
102 if (cg->common.features & CCU_FEATURE_ALL_PREDIV)
103 best_parent *= div;
104 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
105 }
106
107 return *prate / div;
108}
109
110static int ccu_gate_set_rate(struct clk_hw *hw, unsigned long rate,
111 unsigned long parent_rate)
112{
113 /*
114 * We must report success but we can do so unconditionally because
115 * clk_factor_round_rate returns values that ensure this call is a
116 * nop.
117 */
118
119 return 0;
120}
121
78const struct clk_ops ccu_gate_ops = { 122const struct clk_ops ccu_gate_ops = {
79 .disable = ccu_gate_disable, 123 .disable = ccu_gate_disable,
80 .enable = ccu_gate_enable, 124 .enable = ccu_gate_enable,
81 .is_enabled = ccu_gate_is_enabled, 125 .is_enabled = ccu_gate_is_enabled,
126 .round_rate = ccu_gate_round_rate,
127 .set_rate = ccu_gate_set_rate,
128 .recalc_rate = ccu_gate_recalc_rate,
82}; 129};
diff --git a/drivers/clk/sunxi-ng/ccu_mp.c b/drivers/clk/sunxi-ng/ccu_mp.c
index 22c2ca7a2a22..b583f186a804 100644
--- a/drivers/clk/sunxi-ng/ccu_mp.c
+++ b/drivers/clk/sunxi-ng/ccu_mp.c
@@ -85,6 +85,10 @@ static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
85 unsigned int m, p; 85 unsigned int m, p;
86 u32 reg; 86 u32 reg;
87 87
88 /* Adjust parent_rate according to pre-dividers */
89 ccu_mux_helper_adjust_parent_for_prediv(&cmp->common, &cmp->mux,
90 -1, &parent_rate);
91
88 reg = readl(cmp->common.base + cmp->common.reg); 92 reg = readl(cmp->common.base + cmp->common.reg);
89 93
90 m = reg >> cmp->m.shift; 94 m = reg >> cmp->m.shift;
@@ -117,6 +121,10 @@ static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
117 unsigned int m, p; 121 unsigned int m, p;
118 u32 reg; 122 u32 reg;
119 123
124 /* Adjust parent_rate according to pre-dividers */
125 ccu_mux_helper_adjust_parent_for_prediv(&cmp->common, &cmp->mux,
126 -1, &parent_rate);
127
120 max_m = cmp->m.max ?: 1 << cmp->m.width; 128 max_m = cmp->m.max ?: 1 << cmp->m.width;
121 max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1); 129 max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
122 130
diff --git a/drivers/clk/sunxi-ng/ccu_mult.c b/drivers/clk/sunxi-ng/ccu_mult.c
index 8724c01171b1..671141359895 100644
--- a/drivers/clk/sunxi-ng/ccu_mult.c
+++ b/drivers/clk/sunxi-ng/ccu_mult.c
@@ -137,6 +137,8 @@ static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate,
137 137
138 spin_unlock_irqrestore(cm->common.lock, flags); 138 spin_unlock_irqrestore(cm->common.lock, flags);
139 139
140 ccu_helper_wait_for_lock(&cm->common, cm->lock);
141
140 return 0; 142 return 0;
141} 143}
142 144
diff --git a/drivers/clk/sunxi-ng/ccu_mult.h b/drivers/clk/sunxi-ng/ccu_mult.h
index 524acddfcb2e..f9c37b987d72 100644
--- a/drivers/clk/sunxi-ng/ccu_mult.h
+++ b/drivers/clk/sunxi-ng/ccu_mult.h
@@ -33,6 +33,7 @@ struct ccu_mult_internal {
33 33
34struct ccu_mult { 34struct ccu_mult {
35 u32 enable; 35 u32 enable;
36 u32 lock;
36 37
37 struct ccu_frac_internal frac; 38 struct ccu_frac_internal frac;
38 struct ccu_mult_internal mult; 39 struct ccu_mult_internal mult;
@@ -45,6 +46,7 @@ struct ccu_mult {
45 _flags) \ 46 _flags) \
46 struct ccu_mult _struct = { \ 47 struct ccu_mult _struct = { \
47 .enable = _gate, \ 48 .enable = _gate, \
49 .lock = _lock, \
48 .mult = _SUNXI_CCU_MULT(_mshift, _mwidth), \ 50 .mult = _SUNXI_CCU_MULT(_mshift, _mwidth), \
49 .common = { \ 51 .common = { \
50 .reg = _reg, \ 52 .reg = _reg, \
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
index a2b40a000157..488055ed944f 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.c
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
@@ -107,7 +107,7 @@ static unsigned long ccu_nkmp_recalc_rate(struct clk_hw *hw,
107 p = reg >> nkmp->p.shift; 107 p = reg >> nkmp->p.shift;
108 p &= (1 << nkmp->p.width) - 1; 108 p &= (1 << nkmp->p.width) - 1;
109 109
110 return parent_rate * n * k >> p / m; 110 return (parent_rate * n * k >> p) / m;
111} 111}
112 112
113static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate, 113static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h
index 5738635c5274..689f344377a7 100644
--- a/drivers/clk/tegra/clk-id.h
+++ b/drivers/clk/tegra/clk-id.h
@@ -307,6 +307,23 @@ enum clk_id {
307 tegra_clk_xusb_ssp_src, 307 tegra_clk_xusb_ssp_src,
308 tegra_clk_sclk_mux, 308 tegra_clk_sclk_mux,
309 tegra_clk_sor_safe, 309 tegra_clk_sor_safe,
310 tegra_clk_cec,
311 tegra_clk_ispa,
312 tegra_clk_dmic1,
313 tegra_clk_dmic2,
314 tegra_clk_dmic3,
315 tegra_clk_dmic1_sync_clk,
316 tegra_clk_dmic2_sync_clk,
317 tegra_clk_dmic3_sync_clk,
318 tegra_clk_dmic1_sync_clk_mux,
319 tegra_clk_dmic2_sync_clk_mux,
320 tegra_clk_dmic3_sync_clk_mux,
321 tegra_clk_iqc1,
322 tegra_clk_iqc2,
323 tegra_clk_pll_a_out_adsp,
324 tegra_clk_pll_a_out0_out_adsp,
325 tegra_clk_adsp,
326 tegra_clk_adsp_neon,
310 tegra_clk_max, 327 tegra_clk_max,
311}; 328};
312 329
diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
index 88127828befe..303ef32ee3f1 100644
--- a/drivers/clk/tegra/clk-periph-gate.c
+++ b/drivers/clk/tegra/clk-periph-gate.c
@@ -159,6 +159,9 @@ struct clk *tegra_clk_register_periph_gate(const char *name,
159 gate->enable_refcnt = enable_refcnt; 159 gate->enable_refcnt = enable_refcnt;
160 gate->regs = pregs; 160 gate->regs = pregs;
161 161
162 if (read_enb(gate) & periph_clk_to_bit(gate))
163 enable_refcnt[clk_num]++;
164
162 /* Data in .init is copied by clk_register(), so stack variable OK */ 165 /* Data in .init is copied by clk_register(), so stack variable OK */
163 gate->hw.init = &init; 166 gate->hw.init = &init;
164 167
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index a17ca6d7f649..cf80831de79d 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -138,7 +138,7 @@ static const struct clk_ops tegra_clk_periph_no_gate_ops = {
138}; 138};
139 139
140static struct clk *_tegra_clk_register_periph(const char *name, 140static struct clk *_tegra_clk_register_periph(const char *name,
141 const char **parent_names, int num_parents, 141 const char * const *parent_names, int num_parents,
142 struct tegra_clk_periph *periph, 142 struct tegra_clk_periph *periph,
143 void __iomem *clk_base, u32 offset, 143 void __iomem *clk_base, u32 offset,
144 unsigned long flags) 144 unsigned long flags)
@@ -186,7 +186,7 @@ static struct clk *_tegra_clk_register_periph(const char *name,
186} 186}
187 187
188struct clk *tegra_clk_register_periph(const char *name, 188struct clk *tegra_clk_register_periph(const char *name,
189 const char **parent_names, int num_parents, 189 const char * const *parent_names, int num_parents,
190 struct tegra_clk_periph *periph, void __iomem *clk_base, 190 struct tegra_clk_periph *periph, void __iomem *clk_base,
191 u32 offset, unsigned long flags) 191 u32 offset, unsigned long flags)
192{ 192{
@@ -195,7 +195,7 @@ struct clk *tegra_clk_register_periph(const char *name,
195} 195}
196 196
197struct clk *tegra_clk_register_periph_nodiv(const char *name, 197struct clk *tegra_clk_register_periph_nodiv(const char *name,
198 const char **parent_names, int num_parents, 198 const char * const *parent_names, int num_parents,
199 struct tegra_clk_periph *periph, void __iomem *clk_base, 199 struct tegra_clk_periph *periph, void __iomem *clk_base,
200 u32 offset) 200 u32 offset)
201{ 201{
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index b3855360d6bc..159a854779e6 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -2517,152 +2517,6 @@ static int clk_plle_tegra210_is_enabled(struct clk_hw *hw)
2517 return val & PLLE_BASE_ENABLE ? 1 : 0; 2517 return val & PLLE_BASE_ENABLE ? 1 : 0;
2518} 2518}
2519 2519
2520static int clk_pllu_tegra210_enable(struct clk_hw *hw)
2521{
2522 struct tegra_clk_pll *pll = to_clk_pll(hw);
2523 struct clk_hw *pll_ref = clk_hw_get_parent(hw);
2524 struct clk_hw *osc = clk_hw_get_parent(pll_ref);
2525 const struct utmi_clk_param *params = NULL;
2526 unsigned long flags = 0, input_rate;
2527 unsigned int i;
2528 int ret = 0;
2529 u32 value;
2530
2531 if (!osc) {
2532 pr_err("%s: failed to get OSC clock\n", __func__);
2533 return -EINVAL;
2534 }
2535
2536 input_rate = clk_hw_get_rate(osc);
2537
2538 if (pll->lock)
2539 spin_lock_irqsave(pll->lock, flags);
2540
2541 _clk_pll_enable(hw);
2542
2543 ret = clk_pll_wait_for_lock(pll);
2544 if (ret < 0)
2545 goto out;
2546
2547 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
2548 if (input_rate == utmi_parameters[i].osc_frequency) {
2549 params = &utmi_parameters[i];
2550 break;
2551 }
2552 }
2553
2554 if (!params) {
2555 pr_err("%s: unexpected input rate %lu Hz\n", __func__,
2556 input_rate);
2557 ret = -EINVAL;
2558 goto out;
2559 }
2560
2561 value = pll_readl_base(pll);
2562 value &= ~PLLU_BASE_OVERRIDE;
2563 pll_writel_base(value, pll);
2564
2565 /* Put PLLU under HW control */
2566 value = readl_relaxed(pll->clk_base + PLLU_HW_PWRDN_CFG0);
2567 value |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE |
2568 PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT |
2569 PLLU_HW_PWRDN_CFG0_USE_LOCKDET;
2570 value &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL |
2571 PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL);
2572 writel_relaxed(value, pll->clk_base + PLLU_HW_PWRDN_CFG0);
2573
2574 value = readl_relaxed(pll->clk_base + XUSB_PLL_CFG0);
2575 value &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY;
2576 writel_relaxed(value, pll->clk_base + XUSB_PLL_CFG0);
2577
2578 udelay(1);
2579
2580 value = readl_relaxed(pll->clk_base + PLLU_HW_PWRDN_CFG0);
2581 value |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE;
2582 writel_relaxed(value, pll->clk_base + PLLU_HW_PWRDN_CFG0);
2583
2584 udelay(1);
2585
2586 /* Disable PLLU clock branch to UTMIPLL since it uses OSC */
2587 value = pll_readl_base(pll);
2588 value &= ~PLLU_BASE_CLKENABLE_USB;
2589 pll_writel_base(value, pll);
2590
2591 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2592 if (value & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE) {
2593 pr_debug("UTMIPLL already enabled\n");
2594 goto out;
2595 }
2596
2597 value &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2598 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2599
2600 /* Program UTMIP PLL stable and active counts */
2601 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
2602 value &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
2603 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count);
2604 value &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
2605 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count);
2606 value |= UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN;
2607 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
2608
2609 /* Program UTMIP PLL delay and oscillator frequency counts */
2610 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
2611 value &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
2612 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count);
2613 value &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
2614 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count);
2615 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
2616
2617 /* Remove power downs from UTMIP PLL control bits */
2618 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
2619 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2620 value |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2621 writel(value, pll->clk_base + UTMIP_PLL_CFG1);
2622
2623 udelay(1);
2624
2625 /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */
2626 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);
2627 value |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
2628 value |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
2629 value |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
2630 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
2631 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
2632 value &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
2633 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2);
2634
2635 /* Setup HW control of UTMIPLL */
2636 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);
2637 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2638 value &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2639 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1);
2640
2641 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2642 value |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
2643 value &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
2644 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2645
2646 udelay(1);
2647
2648 value = readl_relaxed(pll->clk_base + XUSB_PLL_CFG0);
2649 value &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;
2650 writel_relaxed(value, pll->clk_base + XUSB_PLL_CFG0);
2651
2652 udelay(1);
2653
2654 /* Enable HW control of UTMIPLL */
2655 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2656 value |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
2657 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0);
2658
2659out:
2660 if (pll->lock)
2661 spin_unlock_irqrestore(pll->lock, flags);
2662
2663 return ret;
2664}
2665
2666static const struct clk_ops tegra_clk_plle_tegra210_ops = { 2520static const struct clk_ops tegra_clk_plle_tegra210_ops = {
2667 .is_enabled = clk_plle_tegra210_is_enabled, 2521 .is_enabled = clk_plle_tegra210_is_enabled,
2668 .enable = clk_plle_tegra210_enable, 2522 .enable = clk_plle_tegra210_enable,
@@ -2670,13 +2524,6 @@ static const struct clk_ops tegra_clk_plle_tegra210_ops = {
2670 .recalc_rate = clk_pll_recalc_rate, 2524 .recalc_rate = clk_pll_recalc_rate,
2671}; 2525};
2672 2526
2673static const struct clk_ops tegra_clk_pllu_tegra210_ops = {
2674 .is_enabled = clk_pll_is_enabled,
2675 .enable = clk_pllu_tegra210_enable,
2676 .disable = clk_pll_disable,
2677 .recalc_rate = clk_pllre_recalc_rate,
2678};
2679
2680struct clk *tegra_clk_register_plle_tegra210(const char *name, 2527struct clk *tegra_clk_register_plle_tegra210(const char *name,
2681 const char *parent_name, 2528 const char *parent_name,
2682 void __iomem *clk_base, unsigned long flags, 2529 void __iomem *clk_base, unsigned long flags,
@@ -2918,25 +2765,4 @@ struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
2918 return clk; 2765 return clk;
2919} 2766}
2920 2767
2921struct clk *tegra_clk_register_pllu_tegra210(const char *name,
2922 const char *parent_name, void __iomem *clk_base,
2923 unsigned long flags, struct tegra_clk_pll_params *pll_params,
2924 spinlock_t *lock)
2925{
2926 struct tegra_clk_pll *pll;
2927 struct clk *clk;
2928
2929 pll_params->flags |= TEGRA_PLLU;
2930
2931 pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);
2932 if (IS_ERR(pll))
2933 return ERR_CAST(pll);
2934
2935 clk = _tegra_clk_register_pll(pll, name, parent_name, flags,
2936 &tegra_clk_pllu_tegra210_ops);
2937 if (IS_ERR(clk))
2938 kfree(pll);
2939
2940 return clk;
2941}
2942#endif 2768#endif
diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
index 131d1b5085e2..84267cfc4433 100644
--- a/drivers/clk/tegra/clk-super.c
+++ b/drivers/clk/tegra/clk-super.c
@@ -121,9 +121,50 @@ out:
121 return err; 121 return err;
122} 122}
123 123
124const struct clk_ops tegra_clk_super_mux_ops = {
125 .get_parent = clk_super_get_parent,
126 .set_parent = clk_super_set_parent,
127};
128
129static long clk_super_round_rate(struct clk_hw *hw, unsigned long rate,
130 unsigned long *parent_rate)
131{
132 struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
133 struct clk_hw *div_hw = &super->frac_div.hw;
134
135 __clk_hw_set_clk(div_hw, hw);
136
137 return super->div_ops->round_rate(div_hw, rate, parent_rate);
138}
139
140static unsigned long clk_super_recalc_rate(struct clk_hw *hw,
141 unsigned long parent_rate)
142{
143 struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
144 struct clk_hw *div_hw = &super->frac_div.hw;
145
146 __clk_hw_set_clk(div_hw, hw);
147
148 return super->div_ops->recalc_rate(div_hw, parent_rate);
149}
150
151static int clk_super_set_rate(struct clk_hw *hw, unsigned long rate,
152 unsigned long parent_rate)
153{
154 struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
155 struct clk_hw *div_hw = &super->frac_div.hw;
156
157 __clk_hw_set_clk(div_hw, hw);
158
159 return super->div_ops->set_rate(div_hw, rate, parent_rate);
160}
161
124const struct clk_ops tegra_clk_super_ops = { 162const struct clk_ops tegra_clk_super_ops = {
125 .get_parent = clk_super_get_parent, 163 .get_parent = clk_super_get_parent,
126 .set_parent = clk_super_set_parent, 164 .set_parent = clk_super_set_parent,
165 .set_rate = clk_super_set_rate,
166 .round_rate = clk_super_round_rate,
167 .recalc_rate = clk_super_recalc_rate,
127}; 168};
128 169
129struct clk *tegra_clk_register_super_mux(const char *name, 170struct clk *tegra_clk_register_super_mux(const char *name,
@@ -136,13 +177,11 @@ struct clk *tegra_clk_register_super_mux(const char *name,
136 struct clk_init_data init; 177 struct clk_init_data init;
137 178
138 super = kzalloc(sizeof(*super), GFP_KERNEL); 179 super = kzalloc(sizeof(*super), GFP_KERNEL);
139 if (!super) { 180 if (!super)
140 pr_err("%s: could not allocate super clk\n", __func__);
141 return ERR_PTR(-ENOMEM); 181 return ERR_PTR(-ENOMEM);
142 }
143 182
144 init.name = name; 183 init.name = name;
145 init.ops = &tegra_clk_super_ops; 184 init.ops = &tegra_clk_super_mux_ops;
146 init.flags = flags; 185 init.flags = flags;
147 init.parent_names = parent_names; 186 init.parent_names = parent_names;
148 init.num_parents = num_parents; 187 init.num_parents = num_parents;
@@ -163,3 +202,43 @@ struct clk *tegra_clk_register_super_mux(const char *name,
163 202
164 return clk; 203 return clk;
165} 204}
205
206struct clk *tegra_clk_register_super_clk(const char *name,
207 const char * const *parent_names, u8 num_parents,
208 unsigned long flags, void __iomem *reg, u8 clk_super_flags,
209 spinlock_t *lock)
210{
211 struct tegra_clk_super_mux *super;
212 struct clk *clk;
213 struct clk_init_data init;
214
215 super = kzalloc(sizeof(*super), GFP_KERNEL);
216 if (!super)
217 return ERR_PTR(-ENOMEM);
218
219 init.name = name;
220 init.ops = &tegra_clk_super_ops;
221 init.flags = flags;
222 init.parent_names = parent_names;
223 init.num_parents = num_parents;
224
225 super->reg = reg;
226 super->lock = lock;
227 super->width = 4;
228 super->flags = clk_super_flags;
229 super->frac_div.reg = reg + 4;
230 super->frac_div.shift = 16;
231 super->frac_div.width = 8;
232 super->frac_div.frac_width = 1;
233 super->frac_div.lock = lock;
234 super->div_ops = &tegra_clk_frac_div_ops;
235
236 /* Data in .init is copied by clk_register(), so stack variable OK */
237 super->hw.init = &init;
238
239 clk = clk_register(NULL, &super->hw);
240 if (IS_ERR(clk))
241 kfree(super);
242
243 return clk;
244}
diff --git a/drivers/clk/tegra/clk-tegra-audio.c b/drivers/clk/tegra/clk-tegra-audio.c
index e2bfa9b368f6..b37cae7af26d 100644
--- a/drivers/clk/tegra/clk-tegra-audio.c
+++ b/drivers/clk/tegra/clk-tegra-audio.c
@@ -31,6 +31,9 @@
31#define AUDIO_SYNC_CLK_I2S3 0x4ac 31#define AUDIO_SYNC_CLK_I2S3 0x4ac
32#define AUDIO_SYNC_CLK_I2S4 0x4b0 32#define AUDIO_SYNC_CLK_I2S4 0x4b0
33#define AUDIO_SYNC_CLK_SPDIF 0x4b4 33#define AUDIO_SYNC_CLK_SPDIF 0x4b4
34#define AUDIO_SYNC_CLK_DMIC1 0x560
35#define AUDIO_SYNC_CLK_DMIC2 0x564
36#define AUDIO_SYNC_CLK_DMIC3 0x6b8
34 37
35#define AUDIO_SYNC_DOUBLER 0x49c 38#define AUDIO_SYNC_DOUBLER 0x49c
36 39
@@ -91,8 +94,14 @@ struct tegra_audio2x_clk_initdata {
91 94
92static DEFINE_SPINLOCK(clk_doubler_lock); 95static DEFINE_SPINLOCK(clk_doubler_lock);
93 96
94static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync", 97static const char * const mux_audio_sync_clk[] = { "spdif_in_sync",
95 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync", 98 "i2s0_sync", "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync",
99 "pll_a_out0", "vimclk_sync",
100};
101
102static const char * const mux_dmic_sync_clk[] = { "unused", "i2s0_sync",
103 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "pll_a_out0",
104 "vimclk_sync",
96}; 105};
97 106
98static struct tegra_sync_source_initdata sync_source_clks[] __initdata = { 107static struct tegra_sync_source_initdata sync_source_clks[] __initdata = {
@@ -114,6 +123,12 @@ static struct tegra_audio_clk_initdata audio_clks[] = {
114 AUDIO(spdif, AUDIO_SYNC_CLK_SPDIF), 123 AUDIO(spdif, AUDIO_SYNC_CLK_SPDIF),
115}; 124};
116 125
126static struct tegra_audio_clk_initdata dmic_clks[] = {
127 AUDIO(dmic1_sync_clk, AUDIO_SYNC_CLK_DMIC1),
128 AUDIO(dmic2_sync_clk, AUDIO_SYNC_CLK_DMIC2),
129 AUDIO(dmic3_sync_clk, AUDIO_SYNC_CLK_DMIC3),
130};
131
117static struct tegra_audio2x_clk_initdata audio2x_clks[] = { 132static struct tegra_audio2x_clk_initdata audio2x_clks[] = {
118 AUDIO2X(audio0, 113, 24), 133 AUDIO2X(audio0, 113, 24),
119 AUDIO2X(audio1, 114, 25), 134 AUDIO2X(audio1, 114, 25),
@@ -123,6 +138,41 @@ static struct tegra_audio2x_clk_initdata audio2x_clks[] = {
123 AUDIO2X(spdif, 118, 29), 138 AUDIO2X(spdif, 118, 29),
124}; 139};
125 140
141static void __init tegra_audio_sync_clk_init(void __iomem *clk_base,
142 struct tegra_clk *tegra_clks,
143 struct tegra_audio_clk_initdata *sync,
144 int num_sync_clks,
145 const char * const *mux_names,
146 int num_mux_inputs)
147{
148 struct clk *clk;
149 struct clk **dt_clk;
150 struct tegra_audio_clk_initdata *data;
151 int i;
152
153 for (i = 0, data = sync; i < num_sync_clks; i++, data++) {
154 dt_clk = tegra_lookup_dt_id(data->mux_clk_id, tegra_clks);
155 if (!dt_clk)
156 continue;
157
158 clk = clk_register_mux(NULL, data->mux_name, mux_names,
159 num_mux_inputs,
160 CLK_SET_RATE_NO_REPARENT,
161 clk_base + data->offset, 0, 3, 0,
162 NULL);
163 *dt_clk = clk;
164
165 dt_clk = tegra_lookup_dt_id(data->gate_clk_id, tegra_clks);
166 if (!dt_clk)
167 continue;
168
169 clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
170 0, clk_base + data->offset, 4,
171 CLK_GATE_SET_TO_DISABLE, NULL);
172 *dt_clk = clk;
173 }
174}
175
126void __init tegra_audio_clk_init(void __iomem *clk_base, 176void __init tegra_audio_clk_init(void __iomem *clk_base,
127 void __iomem *pmc_base, struct tegra_clk *tegra_clks, 177 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
128 struct tegra_audio_clk_info *audio_info, 178 struct tegra_audio_clk_info *audio_info,
@@ -176,30 +226,17 @@ void __init tegra_audio_clk_init(void __iomem *clk_base,
176 *dt_clk = clk; 226 *dt_clk = clk;
177 } 227 }
178 228
179 for (i = 0; i < ARRAY_SIZE(audio_clks); i++) { 229 tegra_audio_sync_clk_init(clk_base, tegra_clks, audio_clks,
180 struct tegra_audio_clk_initdata *data; 230 ARRAY_SIZE(audio_clks), mux_audio_sync_clk,
231 ARRAY_SIZE(mux_audio_sync_clk));
181 232
182 data = &audio_clks[i]; 233 /* make sure the DMIC sync clocks have a valid parent */
183 dt_clk = tegra_lookup_dt_id(data->mux_clk_id, tegra_clks); 234 for (i = 0; i < ARRAY_SIZE(dmic_clks); i++)
235 writel_relaxed(1, clk_base + dmic_clks[i].offset);
184 236
185 if (!dt_clk) 237 tegra_audio_sync_clk_init(clk_base, tegra_clks, dmic_clks,
186 continue; 238 ARRAY_SIZE(dmic_clks), mux_dmic_sync_clk,
187 clk = clk_register_mux(NULL, data->mux_name, mux_audio_sync_clk, 239 ARRAY_SIZE(mux_dmic_sync_clk));
188 ARRAY_SIZE(mux_audio_sync_clk),
189 CLK_SET_RATE_NO_REPARENT,
190 clk_base + data->offset, 0, 3, 0,
191 NULL);
192 *dt_clk = clk;
193
194 dt_clk = tegra_lookup_dt_id(data->gate_clk_id, tegra_clks);
195 if (!dt_clk)
196 continue;
197
198 clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
199 0, clk_base + data->offset, 4,
200 CLK_GATE_SET_TO_DISABLE, NULL);
201 *dt_clk = clk;
202 }
203 240
204 for (i = 0; i < ARRAY_SIZE(audio2x_clks); i++) { 241 for (i = 0; i < ARRAY_SIZE(audio2x_clks); i++) {
205 struct tegra_audio2x_clk_initdata *data; 242 struct tegra_audio2x_clk_initdata *data;
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 4ce4e7fb1124..294bfe40a4f5 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -138,6 +138,9 @@
138#define CLK_SOURCE_TSECB 0x6d8 138#define CLK_SOURCE_TSECB 0x6d8
139#define CLK_SOURCE_MAUD 0x6d4 139#define CLK_SOURCE_MAUD 0x6d4
140#define CLK_SOURCE_USB2_HSIC_TRK 0x6cc 140#define CLK_SOURCE_USB2_HSIC_TRK 0x6cc
141#define CLK_SOURCE_DMIC1 0x64c
142#define CLK_SOURCE_DMIC2 0x650
143#define CLK_SOURCE_DMIC3 0x6bc
141 144
142#define MASK(x) (BIT(x) - 1) 145#define MASK(x) (BIT(x) - 1)
143 146
@@ -168,6 +171,12 @@
168 0, TEGRA_PERIPH_NO_GATE, _clk_id,\ 171 0, TEGRA_PERIPH_NO_GATE, _clk_id,\
169 _parents##_idx, 0, _lock) 172 _parents##_idx, 0, _lock)
170 173
174#define MUX8_NOGATE(_name, _parents, _offset, _clk_id) \
175 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset, \
176 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\
177 0, TEGRA_PERIPH_NO_GATE, _clk_id,\
178 _parents##_idx, 0, NULL)
179
171#define INT(_name, _parents, _offset, \ 180#define INT(_name, _parents, _offset, \
172 _clk_num, _gate_flags, _clk_id) \ 181 _clk_num, _gate_flags, _clk_id) \
173 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\ 182 TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
@@ -619,6 +628,21 @@ static const char *mux_clkm_plldp_sor0lvds[] = {
619}; 628};
620#define mux_clkm_plldp_sor0lvds_idx NULL 629#define mux_clkm_plldp_sor0lvds_idx NULL
621 630
631static const char * const mux_dmic1[] = {
632 "pll_a_out0", "dmic1_sync_clk", "pll_p", "clk_m"
633};
634#define mux_dmic1_idx NULL
635
636static const char * const mux_dmic2[] = {
637 "pll_a_out0", "dmic2_sync_clk", "pll_p", "clk_m"
638};
639#define mux_dmic2_idx NULL
640
641static const char * const mux_dmic3[] = {
642 "pll_a_out0", "dmic3_sync_clk", "pll_p", "clk_m"
643};
644#define mux_dmic3_idx NULL
645
622static struct tegra_periph_init_data periph_clks[] = { 646static struct tegra_periph_init_data periph_clks[] = {
623 AUDIO("d_audio", CLK_SOURCE_D_AUDIO, 106, TEGRA_PERIPH_ON_APB, tegra_clk_d_audio), 647 AUDIO("d_audio", CLK_SOURCE_D_AUDIO, 106, TEGRA_PERIPH_ON_APB, tegra_clk_d_audio),
624 AUDIO("dam0", CLK_SOURCE_DAM0, 108, TEGRA_PERIPH_ON_APB, tegra_clk_dam0), 648 AUDIO("dam0", CLK_SOURCE_DAM0, 108, TEGRA_PERIPH_ON_APB, tegra_clk_dam0),
@@ -739,7 +763,7 @@ static struct tegra_periph_init_data periph_clks[] = {
739 MUX8("soc_therm", mux_clkm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm_8), 763 MUX8("soc_therm", mux_clkm_pllc_pllp_plla, CLK_SOURCE_SOC_THERM, 78, TEGRA_PERIPH_ON_APB, tegra_clk_soc_therm_8),
740 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8), 764 MUX8("vi_sensor", mux_pllm_pllc2_c_c3_pllp_plla, CLK_SOURCE_VI_SENSOR, 164, TEGRA_PERIPH_NO_RESET, tegra_clk_vi_sensor_8),
741 MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8), 765 MUX8("isp", mux_pllm_pllc_pllp_plla_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_8),
742 MUX8("isp", mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4, CLK_SOURCE_ISP, 23, TEGRA_PERIPH_ON_APB, tegra_clk_isp_9), 766 MUX8_NOGATE("isp", mux_pllc_pllp_plla1_pllc2_c3_clkm_pllc4, CLK_SOURCE_ISP, tegra_clk_isp_9),
743 MUX8("entropy", mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy), 767 MUX8("entropy", mux_pllp_clkm1, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy),
744 MUX8("entropy", mux_pllp_clkm_clk32_plle, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy_8), 768 MUX8("entropy", mux_pllp_clkm_clk32_plle, CLK_SOURCE_ENTROPY, 149, 0, tegra_clk_entropy_8),
745 MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio), 769 MUX8("hdmi_audio", mux_pllp3_pllc_clkm, CLK_SOURCE_HDMI_AUDIO, 176, TEGRA_PERIPH_NO_RESET, tegra_clk_hdmi_audio),
@@ -788,6 +812,9 @@ static struct tegra_periph_init_data periph_clks[] = {
788 MUX("uartape", mux_pllp_pllc_clkm, CLK_SOURCE_UARTAPE, 212, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_uartape), 812 MUX("uartape", mux_pllp_pllc_clkm, CLK_SOURCE_UARTAPE, 212, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_uartape),
789 MUX8("tsecb", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_TSECB, 206, 0, tegra_clk_tsecb), 813 MUX8("tsecb", mux_pllp_pllc2_c_c3_clkm, CLK_SOURCE_TSECB, 206, 0, tegra_clk_tsecb),
790 MUX8("maud", mux_pllp_pllp_out3_clkm_clk32k_plla, CLK_SOURCE_MAUD, 202, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_maud), 814 MUX8("maud", mux_pllp_pllp_out3_clkm_clk32k_plla, CLK_SOURCE_MAUD, 202, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_maud),
815 MUX8("dmic1", mux_dmic1, CLK_SOURCE_DMIC1, 161, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic1),
816 MUX8("dmic2", mux_dmic2, CLK_SOURCE_DMIC2, 162, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic2),
817 MUX8("dmic3", mux_dmic3, CLK_SOURCE_DMIC3, 197, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_dmic3),
791}; 818};
792 819
793static struct tegra_periph_init_data gate_clks[] = { 820static struct tegra_periph_init_data gate_clks[] = {
@@ -809,7 +836,7 @@ static struct tegra_periph_init_data gate_clks[] = {
809 GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0), 836 GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0),
810 GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0), 837 GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0),
811 GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0), 838 GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0),
812 GATE("afi", "clk_m", 72, 0, tegra_clk_afi, 0), 839 GATE("afi", "mselect", 72, 0, tegra_clk_afi, 0),
813 GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0), 840 GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0),
814 GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0), 841 GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0),
815 GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0), 842 GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0),
@@ -819,7 +846,8 @@ static struct tegra_periph_init_data gate_clks[] = {
819 GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0), 846 GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
820 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED), 847 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IGNORE_UNUSED),
821 GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0), 848 GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
822 GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb, 0), 849 GATE("ispa", "isp", 23, 0, tegra_clk_ispa, 0),
850 GATE("ispb", "isp", 3, 0, tegra_clk_ispb, 0),
823 GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0), 851 GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0),
824 GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0), 852 GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
825 GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0), 853 GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),
@@ -830,6 +858,13 @@ static struct tegra_periph_init_data gate_clks[] = {
830 GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0), 858 GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0),
831 GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0), 859 GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0),
832 GATE("apb2ape", "clk_m", 107, 0, tegra_clk_apb2ape, 0), 860 GATE("apb2ape", "clk_m", 107, 0, tegra_clk_apb2ape, 0),
861 GATE("cec", "pclk", 136, 0, tegra_clk_cec, 0),
862 GATE("iqc1", "clk_m", 221, 0, tegra_clk_iqc1, 0),
863 GATE("iqc2", "clk_m", 220, 0, tegra_clk_iqc1, 0),
864 GATE("pll_a_out_adsp", "pll_a", 188, 0, tegra_clk_pll_a_out_adsp, 0),
865 GATE("pll_a_out0_out_adsp", "pll_a", 188, 0, tegra_clk_pll_a_out0_out_adsp, 0),
866 GATE("adsp", "aclk", 199, 0, tegra_clk_adsp, 0),
867 GATE("adsp_neon", "aclk", 218, 0, tegra_clk_adsp_neon, 0),
833}; 868};
834 869
835static struct tegra_periph_init_data div_clks[] = { 870static struct tegra_periph_init_data div_clks[] = {
diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c
index 91377abfefa1..a35579a3f884 100644
--- a/drivers/clk/tegra/clk-tegra-pmc.c
+++ b/drivers/clk/tegra/clk-tegra-pmc.c
@@ -95,7 +95,8 @@ void __init tegra_pmc_clk_init(void __iomem *pmc_base,
95 continue; 95 continue;
96 96
97 clk = clk_register_mux(NULL, data->mux_name, data->parents, 97 clk = clk_register_mux(NULL, data->mux_name, data->parents,
98 data->num_parents, CLK_SET_RATE_NO_REPARENT, 98 data->num_parents,
99 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,
99 pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift, 100 pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift,
100 3, 0, &clk_out_lock); 101 3, 0, &clk_out_lock);
101 *dt_clk = clk; 102 *dt_clk = clk;
@@ -106,7 +107,8 @@ void __init tegra_pmc_clk_init(void __iomem *pmc_base,
106 continue; 107 continue;
107 108
108 clk = clk_register_gate(NULL, data->gate_name, data->mux_name, 109 clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
109 0, pmc_base + PMC_CLK_OUT_CNTRL, 110 CLK_SET_RATE_PARENT,
111 pmc_base + PMC_CLK_OUT_CNTRL,
110 data->gate_shift, 0, &clk_out_lock); 112 data->gate_shift, 0, &clk_out_lock);
111 *dt_clk = clk; 113 *dt_clk = clk;
112 clk_register_clkdev(clk, data->dev_name, data->gate_name); 114 clk_register_clkdev(clk, data->dev_name, data->gate_name);
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 933b5dd698b8..fd1a99c05c2d 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -819,6 +819,7 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
819 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true }, 819 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true },
820 [tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true }, 820 [tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
821 [tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true }, 821 [tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
822 [tegra_clk_cec] = { .dt_id = TEGRA114_CLK_CEC, .present = true },
822}; 823};
823 824
824static struct tegra_devclk devclks[] __initdata = { 825static struct tegra_devclk devclks[] __initdata = {
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index a112d3d2bff1..e81ea5b11577 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -928,6 +928,7 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
928 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true }, 928 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_1_MUX, .present = true },
929 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true }, 929 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_2_MUX, .present = true },
930 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true }, 930 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA124_CLK_CLK_OUT_3_MUX, .present = true },
931 [tegra_clk_cec] = { .dt_id = TEGRA124_CLK_CEC, .present = true },
931}; 932};
932 933
933static struct tegra_devclk devclks[] __initdata = { 934static struct tegra_devclk devclks[] __initdata = {
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 2896d2e783ce..1024e853ea65 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -24,6 +24,8 @@
24#include <linux/export.h> 24#include <linux/export.h>
25#include <linux/clk/tegra.h> 25#include <linux/clk/tegra.h>
26#include <dt-bindings/clock/tegra210-car.h> 26#include <dt-bindings/clock/tegra210-car.h>
27#include <dt-bindings/reset/tegra210-car.h>
28#include <linux/iopoll.h>
27 29
28#include "clk.h" 30#include "clk.h"
29#include "clk-id.h" 31#include "clk-id.h"
@@ -155,9 +157,35 @@
155#define PMC_PLLM_WB0_OVERRIDE 0x1dc 157#define PMC_PLLM_WB0_OVERRIDE 0x1dc
156#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 158#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0
157 159
160#define UTMIP_PLL_CFG2 0x488
161#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)
162#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
163#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
164#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
165#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
166#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP BIT(3)
167#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
168#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERUP BIT(5)
169#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN BIT(24)
170#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP BIT(25)
171
172#define UTMIP_PLL_CFG1 0x484
173#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
174#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
175#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP BIT(17)
176#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
177#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP BIT(15)
178#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
179#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
180
158#define SATA_PLL_CFG0 0x490 181#define SATA_PLL_CFG0 0x490
159#define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0) 182#define SATA_PLL_CFG0_PADPLL_RESET_SWCTL BIT(0)
160#define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2) 183#define SATA_PLL_CFG0_PADPLL_USE_LOCKDET BIT(2)
184#define SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL BIT(4)
185#define SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE BIT(5)
186#define SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE BIT(6)
187#define SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE BIT(7)
188
161#define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13) 189#define SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ BIT(13)
162#define SATA_PLL_CFG0_SEQ_ENABLE BIT(24) 190#define SATA_PLL_CFG0_SEQ_ENABLE BIT(24)
163 191
@@ -196,6 +224,12 @@
196#define CLK_M_DIVISOR_SHIFT 2 224#define CLK_M_DIVISOR_SHIFT 2
197#define CLK_M_DIVISOR_MASK 0x3 225#define CLK_M_DIVISOR_MASK 0x3
198 226
227#define RST_DFLL_DVCO 0x2f4
228#define DVFS_DFLL_RESET_SHIFT 0
229
230#define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8
231#define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac
232
199/* 233/*
200 * SDM fractional divisor is 16-bit 2's complement signed number within 234 * SDM fractional divisor is 16-bit 2's complement signed number within
201 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned 235 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
@@ -454,6 +488,26 @@ void tegra210_sata_pll_hw_sequence_start(void)
454} 488}
455EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start); 489EXPORT_SYMBOL_GPL(tegra210_sata_pll_hw_sequence_start);
456 490
491void tegra210_set_sata_pll_seq_sw(bool state)
492{
493 u32 val;
494
495 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
496 if (state) {
497 val |= SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL;
498 val |= SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE;
499 val |= SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE;
500 val |= SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE;
501 } else {
502 val &= ~SATA_PLL_CFG0_SATA_SEQ_IN_SWCTL;
503 val &= ~SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE;
504 val &= ~SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE;
505 val &= ~SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE;
506 }
507 writel_relaxed(val, clk_base + SATA_PLL_CFG0);
508}
509EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw);
510
457static inline void _pll_misc_chk_default(void __iomem *base, 511static inline void _pll_misc_chk_default(void __iomem *base,
458 struct tegra_clk_pll_params *params, 512 struct tegra_clk_pll_params *params,
459 u8 misc_num, u32 default_val, u32 mask) 513 u8 misc_num, u32 default_val, u32 mask)
@@ -501,12 +555,12 @@ static void tegra210_pllcx_set_defaults(const char *name,
501{ 555{
502 pllcx->params->defaults_set = true; 556 pllcx->params->defaults_set = true;
503 557
504 if (readl_relaxed(clk_base + pllcx->params->base_reg) & 558 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) {
505 PLL_ENABLE) {
506 /* PLL is ON: only check if defaults already set */ 559 /* PLL is ON: only check if defaults already set */
507 pllcx_check_defaults(pllcx->params); 560 pllcx_check_defaults(pllcx->params);
508 pr_warn("%s already enabled. Postponing set full defaults\n", 561 if (!pllcx->params->defaults_set)
509 name); 562 pr_warn("%s already enabled. Postponing set full defaults\n",
563 name);
510 return; 564 return;
511 } 565 }
512 566
@@ -608,7 +662,6 @@ static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
608 662
609 if (readl_relaxed(clk_base + plld->params->base_reg) & 663 if (readl_relaxed(clk_base + plld->params->base_reg) &
610 PLL_ENABLE) { 664 PLL_ENABLE) {
611 pr_warn("PLL_D already enabled. Postponing set full defaults\n");
612 665
613 /* 666 /*
614 * PLL is ON: check if defaults already set, then set those 667 * PLL is ON: check if defaults already set, then set those
@@ -625,6 +678,9 @@ static void tegra210_plld_set_defaults(struct tegra_clk_pll *plld)
625 _pll_misc_chk_default(clk_base, plld->params, 0, val, 678 _pll_misc_chk_default(clk_base, plld->params, 0, val,
626 ~mask & PLLD_MISC0_WRITE_MASK); 679 ~mask & PLLD_MISC0_WRITE_MASK);
627 680
681 if (!plld->params->defaults_set)
682 pr_warn("PLL_D already enabled. Postponing set full defaults\n");
683
628 /* Enable lock detect */ 684 /* Enable lock detect */
629 mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE; 685 mask = PLLD_MISC0_LOCK_ENABLE | PLLD_MISC0_LOCK_OVERRIDE;
630 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]); 686 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
@@ -896,7 +952,6 @@ static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
896 val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT; 952 val |= step_b << PLLX_MISC2_DYNRAMP_STEPB_SHIFT;
897 953
898 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) { 954 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {
899 pr_warn("PLL_X already enabled. Postponing set full defaults\n");
900 955
901 /* 956 /*
902 * PLL is ON: check if defaults already set, then set those 957 * PLL is ON: check if defaults already set, then set those
@@ -904,6 +959,8 @@ static void tegra210_pllx_set_defaults(struct tegra_clk_pll *pllx)
904 */ 959 */
905 pllx_check_defaults(pllx); 960 pllx_check_defaults(pllx);
906 961
962 if (!pllx->params->defaults_set)
963 pr_warn("PLL_X already enabled. Postponing set full defaults\n");
907 /* Configure dyn ramp, disable lock override */ 964 /* Configure dyn ramp, disable lock override */
908 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]); 965 writel_relaxed(val, clk_base + pllx->params->ext_misc_reg[2]);
909 966
@@ -948,7 +1005,6 @@ static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
948 pllmb->params->defaults_set = true; 1005 pllmb->params->defaults_set = true;
949 1006
950 if (val & PLL_ENABLE) { 1007 if (val & PLL_ENABLE) {
951 pr_warn("PLL_MB already enabled. Postponing set full defaults\n");
952 1008
953 /* 1009 /*
954 * PLL is ON: check if defaults already set, then set those 1010 * PLL is ON: check if defaults already set, then set those
@@ -959,6 +1015,8 @@ static void tegra210_pllmb_set_defaults(struct tegra_clk_pll *pllmb)
959 _pll_misc_chk_default(clk_base, pllmb->params, 0, val, 1015 _pll_misc_chk_default(clk_base, pllmb->params, 0, val,
960 ~mask & PLLMB_MISC1_WRITE_MASK); 1016 ~mask & PLLMB_MISC1_WRITE_MASK);
961 1017
1018 if (!pllmb->params->defaults_set)
1019 pr_warn("PLL_MB already enabled. Postponing set full defaults\n");
962 /* Enable lock detect */ 1020 /* Enable lock detect */
963 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]); 1021 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);
964 val &= ~mask; 1022 val &= ~mask;
@@ -1008,13 +1066,14 @@ static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp)
1008 pllp->params->defaults_set = true; 1066 pllp->params->defaults_set = true;
1009 1067
1010 if (val & PLL_ENABLE) { 1068 if (val & PLL_ENABLE) {
1011 pr_warn("PLL_P already enabled. Postponing set full defaults\n");
1012 1069
1013 /* 1070 /*
1014 * PLL is ON: check if defaults already set, then set those 1071 * PLL is ON: check if defaults already set, then set those
1015 * that can be updated in flight. 1072 * that can be updated in flight.
1016 */ 1073 */
1017 pllp_check_defaults(pllp, true); 1074 pllp_check_defaults(pllp, true);
1075 if (!pllp->params->defaults_set)
1076 pr_warn("PLL_P already enabled. Postponing set full defaults\n");
1018 1077
1019 /* Enable lock detect */ 1078 /* Enable lock detect */
1020 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]); 1079 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]);
@@ -1046,47 +1105,49 @@ static void tegra210_pllp_set_defaults(struct tegra_clk_pll *pllp)
1046 * Both VCO and post-divider output rates are fixed at 480MHz and 240MHz, 1105 * Both VCO and post-divider output rates are fixed at 480MHz and 240MHz,
1047 * respectively. 1106 * respectively.
1048 */ 1107 */
1049static void pllu_check_defaults(struct tegra_clk_pll *pll, bool hw_control) 1108static void pllu_check_defaults(struct tegra_clk_pll_params *params,
1109 bool hw_control)
1050{ 1110{
1051 u32 val, mask; 1111 u32 val, mask;
1052 1112
1053 /* Ignore lock enable (will be set) and IDDQ if under h/w control */ 1113 /* Ignore lock enable (will be set) and IDDQ if under h/w control */
1054 val = PLLU_MISC0_DEFAULT_VALUE & (~PLLU_MISC0_IDDQ); 1114 val = PLLU_MISC0_DEFAULT_VALUE & (~PLLU_MISC0_IDDQ);
1055 mask = PLLU_MISC0_LOCK_ENABLE | (hw_control ? PLLU_MISC0_IDDQ : 0); 1115 mask = PLLU_MISC0_LOCK_ENABLE | (hw_control ? PLLU_MISC0_IDDQ : 0);
1056 _pll_misc_chk_default(clk_base, pll->params, 0, val, 1116 _pll_misc_chk_default(clk_base, params, 0, val,
1057 ~mask & PLLU_MISC0_WRITE_MASK); 1117 ~mask & PLLU_MISC0_WRITE_MASK);
1058 1118
1059 val = PLLU_MISC1_DEFAULT_VALUE; 1119 val = PLLU_MISC1_DEFAULT_VALUE;
1060 mask = PLLU_MISC1_LOCK_OVERRIDE; 1120 mask = PLLU_MISC1_LOCK_OVERRIDE;
1061 _pll_misc_chk_default(clk_base, pll->params, 1, val, 1121 _pll_misc_chk_default(clk_base, params, 1, val,
1062 ~mask & PLLU_MISC1_WRITE_MASK); 1122 ~mask & PLLU_MISC1_WRITE_MASK);
1063} 1123}
1064 1124
1065static void tegra210_pllu_set_defaults(struct tegra_clk_pll *pllu) 1125static void tegra210_pllu_set_defaults(struct tegra_clk_pll_params *pllu)
1066{ 1126{
1067 u32 val = readl_relaxed(clk_base + pllu->params->base_reg); 1127 u32 val = readl_relaxed(clk_base + pllu->base_reg);
1068 1128
1069 pllu->params->defaults_set = true; 1129 pllu->defaults_set = true;
1070 1130
1071 if (val & PLL_ENABLE) { 1131 if (val & PLL_ENABLE) {
1072 pr_warn("PLL_U already enabled. Postponing set full defaults\n");
1073 1132
1074 /* 1133 /*
1075 * PLL is ON: check if defaults already set, then set those 1134 * PLL is ON: check if defaults already set, then set those
1076 * that can be updated in flight. 1135 * that can be updated in flight.
1077 */ 1136 */
1078 pllu_check_defaults(pllu, false); 1137 pllu_check_defaults(pllu, false);
1138 if (!pllu->defaults_set)
1139 pr_warn("PLL_U already enabled. Postponing set full defaults\n");
1079 1140
1080 /* Enable lock detect */ 1141 /* Enable lock detect */
1081 val = readl_relaxed(clk_base + pllu->params->ext_misc_reg[0]); 1142 val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]);
1082 val &= ~PLLU_MISC0_LOCK_ENABLE; 1143 val &= ~PLLU_MISC0_LOCK_ENABLE;
1083 val |= PLLU_MISC0_DEFAULT_VALUE & PLLU_MISC0_LOCK_ENABLE; 1144 val |= PLLU_MISC0_DEFAULT_VALUE & PLLU_MISC0_LOCK_ENABLE;
1084 writel_relaxed(val, clk_base + pllu->params->ext_misc_reg[0]); 1145 writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]);
1085 1146
1086 val = readl_relaxed(clk_base + pllu->params->ext_misc_reg[1]); 1147 val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]);
1087 val &= ~PLLU_MISC1_LOCK_OVERRIDE; 1148 val &= ~PLLU_MISC1_LOCK_OVERRIDE;
1088 val |= PLLU_MISC1_DEFAULT_VALUE & PLLU_MISC1_LOCK_OVERRIDE; 1149 val |= PLLU_MISC1_DEFAULT_VALUE & PLLU_MISC1_LOCK_OVERRIDE;
1089 writel_relaxed(val, clk_base + pllu->params->ext_misc_reg[1]); 1150 writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]);
1090 udelay(1); 1151 udelay(1);
1091 1152
1092 return; 1153 return;
@@ -1094,9 +1155,9 @@ static void tegra210_pllu_set_defaults(struct tegra_clk_pll *pllu)
1094 1155
1095 /* set IDDQ, enable lock detect */ 1156 /* set IDDQ, enable lock detect */
1096 writel_relaxed(PLLU_MISC0_DEFAULT_VALUE, 1157 writel_relaxed(PLLU_MISC0_DEFAULT_VALUE,
1097 clk_base + pllu->params->ext_misc_reg[0]); 1158 clk_base + pllu->ext_misc_reg[0]);
1098 writel_relaxed(PLLU_MISC1_DEFAULT_VALUE, 1159 writel_relaxed(PLLU_MISC1_DEFAULT_VALUE,
1099 clk_base + pllu->params->ext_misc_reg[1]); 1160 clk_base + pllu->ext_misc_reg[1]);
1100 udelay(1); 1161 udelay(1);
1101} 1162}
1102 1163
@@ -1216,6 +1277,7 @@ static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw,
1216 cfg->n = p_rate / cf; 1277 cfg->n = p_rate / cf;
1217 1278
1218 cfg->sdm_data = 0; 1279 cfg->sdm_data = 0;
1280 cfg->output_rate = input_rate;
1219 if (params->sdm_ctrl_reg) { 1281 if (params->sdm_ctrl_reg) {
1220 unsigned long rem = p_rate - cf * cfg->n; 1282 unsigned long rem = p_rate - cf * cfg->n;
1221 /* If ssc is enabled SDM enabled as well, even for integer n */ 1283 /* If ssc is enabled SDM enabled as well, even for integer n */
@@ -1226,10 +1288,15 @@ static int tegra210_pll_fixed_mdiv_cfg(struct clk_hw *hw,
1226 s -= PLL_SDM_COEFF / 2; 1288 s -= PLL_SDM_COEFF / 2;
1227 cfg->sdm_data = sdin_din_to_data(s); 1289 cfg->sdm_data = sdin_din_to_data(s);
1228 } 1290 }
1291 cfg->output_rate *= cfg->n * PLL_SDM_COEFF + PLL_SDM_COEFF/2 +
1292 sdin_data_to_din(cfg->sdm_data);
1293 cfg->output_rate /= p * cfg->m * PLL_SDM_COEFF;
1294 } else {
1295 cfg->output_rate *= cfg->n;
1296 cfg->output_rate /= p * cfg->m;
1229 } 1297 }
1230 1298
1231 cfg->input_rate = input_rate; 1299 cfg->input_rate = input_rate;
1232 cfg->output_rate = rate;
1233 1300
1234 return 0; 1301 return 0;
1235} 1302}
@@ -1772,7 +1839,7 @@ static struct tegra_clk_pll_params pll_a1_params = {
1772 .misc_reg = PLLA1_MISC0, 1839 .misc_reg = PLLA1_MISC0,
1773 .lock_mask = PLLCX_BASE_LOCK, 1840 .lock_mask = PLLCX_BASE_LOCK,
1774 .lock_delay = 300, 1841 .lock_delay = 300,
1775 .iddq_reg = PLLA1_MISC0, 1842 .iddq_reg = PLLA1_MISC1,
1776 .iddq_bit_idx = PLLCX_IDDQ_BIT, 1843 .iddq_bit_idx = PLLCX_IDDQ_BIT,
1777 .reset_reg = PLLA1_MISC0, 1844 .reset_reg = PLLA1_MISC0,
1778 .reset_bit_idx = PLLCX_RESET_BIT, 1845 .reset_bit_idx = PLLCX_RESET_BIT,
@@ -1987,9 +2054,9 @@ static struct div_nmp pllu_nmp = {
1987}; 2054};
1988 2055
1989static struct tegra_clk_pll_freq_table pll_u_freq_table[] = { 2056static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
1990 { 12000000, 480000000, 40, 1, 1, 0 }, 2057 { 12000000, 480000000, 40, 1, 0, 0 },
1991 { 13000000, 480000000, 36, 1, 1, 0 }, /* actual: 468.0 MHz */ 2058 { 13000000, 480000000, 36, 1, 0, 0 }, /* actual: 468.0 MHz */
1992 { 38400000, 480000000, 25, 2, 1, 0 }, 2059 { 38400000, 480000000, 25, 2, 0, 0 },
1993 { 0, 0, 0, 0, 0, 0 }, 2060 { 0, 0, 0, 0, 0, 0 },
1994}; 2061};
1995 2062
@@ -2013,8 +2080,47 @@ static struct tegra_clk_pll_params pll_u_vco_params = {
2013 .div_nmp = &pllu_nmp, 2080 .div_nmp = &pllu_nmp,
2014 .freq_table = pll_u_freq_table, 2081 .freq_table = pll_u_freq_table,
2015 .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT, 2082 .flags = TEGRA_PLLU | TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
2016 .set_defaults = tegra210_pllu_set_defaults, 2083};
2017 .calc_rate = tegra210_pll_fixed_mdiv_cfg, 2084
2085struct utmi_clk_param {
2086 /* Oscillator Frequency in KHz */
2087 u32 osc_frequency;
2088 /* UTMIP PLL Enable Delay Count */
2089 u8 enable_delay_count;
2090 /* UTMIP PLL Stable count */
2091 u16 stable_count;
2092 /* UTMIP PLL Active delay count */
2093 u8 active_delay_count;
2094 /* UTMIP PLL Xtal frequency count */
2095 u16 xtal_freq_count;
2096};
2097
2098static const struct utmi_clk_param utmi_parameters[] = {
2099 {
2100 .osc_frequency = 38400000, .enable_delay_count = 0x0,
2101 .stable_count = 0x0, .active_delay_count = 0x6,
2102 .xtal_freq_count = 0x80
2103 }, {
2104 .osc_frequency = 13000000, .enable_delay_count = 0x02,
2105 .stable_count = 0x33, .active_delay_count = 0x05,
2106 .xtal_freq_count = 0x7f
2107 }, {
2108 .osc_frequency = 19200000, .enable_delay_count = 0x03,
2109 .stable_count = 0x4b, .active_delay_count = 0x06,
2110 .xtal_freq_count = 0xbb
2111 }, {
2112 .osc_frequency = 12000000, .enable_delay_count = 0x02,
2113 .stable_count = 0x2f, .active_delay_count = 0x08,
2114 .xtal_freq_count = 0x76
2115 }, {
2116 .osc_frequency = 26000000, .enable_delay_count = 0x04,
2117 .stable_count = 0x66, .active_delay_count = 0x09,
2118 .xtal_freq_count = 0xfe
2119 }, {
2120 .osc_frequency = 16800000, .enable_delay_count = 0x03,
2121 .stable_count = 0x41, .active_delay_count = 0x0a,
2122 .xtal_freq_count = 0xa4
2123 },
2018}; 2124};
2019 2125
2020static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { 2126static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
@@ -2115,7 +2221,6 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
2115 [tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true }, 2221 [tegra_clk_pll_c2] = { .dt_id = TEGRA210_CLK_PLL_C2, .present = true },
2116 [tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true }, 2222 [tegra_clk_pll_c3] = { .dt_id = TEGRA210_CLK_PLL_C3, .present = true },
2117 [tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true }, 2223 [tegra_clk_pll_m] = { .dt_id = TEGRA210_CLK_PLL_M, .present = true },
2118 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA210_CLK_PLL_M_OUT1, .present = true },
2119 [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true }, 2224 [tegra_clk_pll_p] = { .dt_id = TEGRA210_CLK_PLL_P, .present = true },
2120 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true }, 2225 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA210_CLK_PLL_P_OUT1, .present = true },
2121 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true }, 2226 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA210_CLK_PLL_P_OUT3, .present = true },
@@ -2209,6 +2314,25 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = {
2209 [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true }, 2314 [tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true },
2210 [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true }, 2315 [tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true },
2211 [tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true }, 2316 [tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true },
2317 [tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true },
2318 [tegra_clk_ispa] = { .dt_id = TEGRA210_CLK_ISPA, .present = true },
2319 [tegra_clk_cec] = { .dt_id = TEGRA210_CLK_CEC, .present = true },
2320 [tegra_clk_dmic1] = { .dt_id = TEGRA210_CLK_DMIC1, .present = true },
2321 [tegra_clk_dmic2] = { .dt_id = TEGRA210_CLK_DMIC2, .present = true },
2322 [tegra_clk_dmic3] = { .dt_id = TEGRA210_CLK_DMIC3, .present = true },
2323 [tegra_clk_dmic1_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK, .present = true },
2324 [tegra_clk_dmic2_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK, .present = true },
2325 [tegra_clk_dmic3_sync_clk] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK, .present = true },
2326 [tegra_clk_dmic1_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC1_SYNC_CLK_MUX, .present = true },
2327 [tegra_clk_dmic2_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC2_SYNC_CLK_MUX, .present = true },
2328 [tegra_clk_dmic3_sync_clk_mux] = { .dt_id = TEGRA210_CLK_DMIC3_SYNC_CLK_MUX, .present = true },
2329 [tegra_clk_dp2] = { .dt_id = TEGRA210_CLK_DP2, .present = true },
2330 [tegra_clk_iqc1] = { .dt_id = TEGRA210_CLK_IQC1, .present = true },
2331 [tegra_clk_iqc2] = { .dt_id = TEGRA210_CLK_IQC2, .present = true },
2332 [tegra_clk_pll_a_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT_ADSP, .present = true },
2333 [tegra_clk_pll_a_out0_out_adsp] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP, .present = true },
2334 [tegra_clk_adsp] = { .dt_id = TEGRA210_CLK_ADSP, .present = true },
2335 [tegra_clk_adsp_neon] = { .dt_id = TEGRA210_CLK_ADSP_NEON, .present = true },
2212}; 2336};
2213 2337
2214static struct tegra_devclk devclks[] __initdata = { 2338static struct tegra_devclk devclks[] __initdata = {
@@ -2227,7 +2351,6 @@ static struct tegra_devclk devclks[] __initdata = {
2227 { .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 }, 2351 { .con_id = "pll_p_out3", .dt_id = TEGRA210_CLK_PLL_P_OUT3 },
2228 { .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 }, 2352 { .con_id = "pll_p_out4", .dt_id = TEGRA210_CLK_PLL_P_OUT4 },
2229 { .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M }, 2353 { .con_id = "pll_m", .dt_id = TEGRA210_CLK_PLL_M },
2230 { .con_id = "pll_m_out1", .dt_id = TEGRA210_CLK_PLL_M_OUT1 },
2231 { .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X }, 2354 { .con_id = "pll_x", .dt_id = TEGRA210_CLK_PLL_X },
2232 { .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 }, 2355 { .con_id = "pll_x_out0", .dt_id = TEGRA210_CLK_PLL_X_OUT0 },
2233 { .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U }, 2356 { .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U },
@@ -2286,6 +2409,221 @@ static struct tegra_audio_clk_info tegra210_audio_plls[] = {
2286 2409
2287static struct clk **clks; 2410static struct clk **clks;
2288 2411
2412static const char * const aclk_parents[] = {
2413 "pll_a1", "pll_c", "pll_p", "pll_a_out0", "pll_c2", "pll_c3",
2414 "clk_m"
2415};
2416
2417void tegra210_put_utmipll_in_iddq(void)
2418{
2419 u32 reg;
2420
2421 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2422
2423 if (reg & UTMIPLL_HW_PWRDN_CFG0_UTMIPLL_LOCK) {
2424 pr_err("trying to assert IDDQ while UTMIPLL is locked\n");
2425 return;
2426 }
2427
2428 reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2429 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2430}
2431EXPORT_SYMBOL_GPL(tegra210_put_utmipll_in_iddq);
2432
2433void tegra210_put_utmipll_out_iddq(void)
2434{
2435 u32 reg;
2436
2437 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2438 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2439 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2440}
2441EXPORT_SYMBOL_GPL(tegra210_put_utmipll_out_iddq);
2442
2443static void tegra210_utmi_param_configure(void)
2444{
2445 u32 reg;
2446 int i;
2447
2448 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
2449 if (osc_freq == utmi_parameters[i].osc_frequency)
2450 break;
2451 }
2452
2453 if (i >= ARRAY_SIZE(utmi_parameters)) {
2454 pr_err("%s: Unexpected oscillator freq %lu\n", __func__,
2455 osc_freq);
2456 return;
2457 }
2458
2459 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2460 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;
2461 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2462
2463 udelay(10);
2464
2465 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2466
2467 /* Program UTMIP PLL stable and active counts */
2468 /* [FIXME] arclk_rst.h says WRONG! This should be 1ms -> 0x50 Check! */
2469 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
2470 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);
2471
2472 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
2473
2474 reg |=
2475 UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(utmi_parameters[i].active_delay_count);
2476 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2477
2478 /* Program UTMIP PLL delay and oscillator frequency counts */
2479 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2480 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
2481
2482 reg |=
2483 UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(utmi_parameters[i].enable_delay_count);
2484
2485 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
2486 reg |=
2487 UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(utmi_parameters[i].xtal_freq_count);
2488
2489 reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
2490 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2491
2492 /* Remove power downs from UTMIP PLL control bits */
2493 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2494 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2495 reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2496 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2497 udelay(1);
2498
2499 /* Enable samplers for SNPS, XUSB_HOST, XUSB_DEV */
2500 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2501 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP;
2502 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP;
2503 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP;
2504 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
2505 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
2506 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN;
2507 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
2508
2509 /* Setup HW control of UTMIPLL */
2510 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2511 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
2512 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;
2513 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
2514
2515 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2516 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;
2517 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;
2518 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2519
2520 udelay(1);
2521
2522 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2523 reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY;
2524 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2525
2526 udelay(1);
2527
2528 /* Enable HW control UTMIPLL */
2529 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2530 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;
2531 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0);
2532}
2533
2534static int tegra210_enable_pllu(void)
2535{
2536 struct tegra_clk_pll_freq_table *fentry;
2537 struct tegra_clk_pll pllu;
2538 u32 reg;
2539
2540 for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) {
2541 if (fentry->input_rate == pll_ref_freq)
2542 break;
2543 }
2544
2545 if (!fentry->input_rate) {
2546 pr_err("Unknown PLL_U reference frequency %lu\n", pll_ref_freq);
2547 return -EINVAL;
2548 }
2549
2550 /* clear IDDQ bit */
2551 pllu.params = &pll_u_vco_params;
2552 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);
2553 reg &= ~BIT(pllu.params->iddq_bit_idx);
2554 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]);
2555
2556 reg = readl_relaxed(clk_base + PLLU_BASE);
2557 reg &= ~GENMASK(20, 0);
2558 reg |= fentry->m;
2559 reg |= fentry->n << 8;
2560 reg |= fentry->p << 16;
2561 writel(reg, clk_base + PLLU_BASE);
2562 reg |= PLL_ENABLE;
2563 writel(reg, clk_base + PLLU_BASE);
2564
2565 readl_relaxed_poll_timeout(clk_base + PLLU_BASE, reg,
2566 reg & PLL_BASE_LOCK, 2, 1000);
2567 if (!(reg & PLL_BASE_LOCK)) {
2568 pr_err("Timed out waiting for PLL_U to lock\n");
2569 return -ETIMEDOUT;
2570 }
2571
2572 return 0;
2573}
2574
2575static int tegra210_init_pllu(void)
2576{
2577 u32 reg;
2578 int err;
2579
2580 tegra210_pllu_set_defaults(&pll_u_vco_params);
2581 /* skip initialization when pllu is in hw controlled mode */
2582 reg = readl_relaxed(clk_base + PLLU_BASE);
2583 if (reg & PLLU_BASE_OVERRIDE) {
2584 if (!(reg & PLL_ENABLE)) {
2585 err = tegra210_enable_pllu();
2586 if (err < 0) {
2587 WARN_ON(1);
2588 return err;
2589 }
2590 }
2591 /* enable hw controlled mode */
2592 reg = readl_relaxed(clk_base + PLLU_BASE);
2593 reg &= ~PLLU_BASE_OVERRIDE;
2594 writel(reg, clk_base + PLLU_BASE);
2595
2596 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2597 reg |= PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE |
2598 PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT |
2599 PLLU_HW_PWRDN_CFG0_USE_LOCKDET;
2600 reg &= ~(PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL |
2601 PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL);
2602 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2603
2604 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2605 reg &= ~XUSB_PLL_CFG0_PLLU_LOCK_DLY_MASK;
2606 writel_relaxed(reg, clk_base + XUSB_PLL_CFG0);
2607 udelay(1);
2608
2609 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2610 reg |= PLLU_HW_PWRDN_CFG0_SEQ_ENABLE;
2611 writel_relaxed(reg, clk_base + PLLU_HW_PWRDN_CFG0);
2612 udelay(1);
2613
2614 reg = readl_relaxed(clk_base + PLLU_BASE);
2615 reg &= ~PLLU_BASE_CLKENABLE_USB;
2616 writel_relaxed(reg, clk_base + PLLU_BASE);
2617 }
2618
2619 /* enable UTMIPLL hw control if not yet done by the bootloader */
2620 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2621 if (!(reg & UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE))
2622 tegra210_utmi_param_configure();
2623
2624 return 0;
2625}
2626
2289static __init void tegra210_periph_clk_init(void __iomem *clk_base, 2627static __init void tegra210_periph_clk_init(void __iomem *clk_base,
2290 void __iomem *pmc_base) 2628 void __iomem *pmc_base)
2291{ 2629{
@@ -2347,6 +2685,11 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
2347 clk_register_clkdev(clk, "cml1", NULL); 2685 clk_register_clkdev(clk, "cml1", NULL);
2348 clks[TEGRA210_CLK_CML1] = clk; 2686 clks[TEGRA210_CLK_CML1] = clk;
2349 2687
2688 clk = tegra_clk_register_super_clk("aclk", aclk_parents,
2689 ARRAY_SIZE(aclk_parents), 0, clk_base + 0x6e0,
2690 0, NULL);
2691 clks[TEGRA210_CLK_ACLK] = clk;
2692
2350 tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params); 2693 tegra_periph_clk_init(clk_base, pmc_base, tegra210_clks, &pll_p_params);
2351} 2694}
2352 2695
@@ -2402,9 +2745,6 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
2402 clk_register_clkdev(clk, "pll_mb", NULL); 2745 clk_register_clkdev(clk, "pll_mb", NULL);
2403 clks[TEGRA210_CLK_PLL_MB] = clk; 2746 clks[TEGRA210_CLK_PLL_MB] = clk;
2404 2747
2405 clk_register_clkdev(clk, "pll_m_out1", NULL);
2406 clks[TEGRA210_CLK_PLL_M_OUT1] = clk;
2407
2408 /* PLLM_UD */ 2748 /* PLLM_UD */
2409 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m", 2749 clk = clk_register_fixed_factor(NULL, "pll_m_ud", "pll_m",
2410 CLK_SET_RATE_PARENT, 1, 1); 2750 CLK_SET_RATE_PARENT, 1, 1);
@@ -2412,11 +2752,12 @@ static void __init tegra210_pll_init(void __iomem *clk_base,
2412 clks[TEGRA210_CLK_PLL_M_UD] = clk; 2752 clks[TEGRA210_CLK_PLL_M_UD] = clk;
2413 2753
2414 /* PLLU_VCO */ 2754 /* PLLU_VCO */
2415 clk = tegra_clk_register_pllu_tegra210("pll_u_vco", "pll_ref", 2755 if (!tegra210_init_pllu()) {
2416 clk_base, 0, &pll_u_vco_params, 2756 clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0,
2417 &pll_u_lock); 2757 480*1000*1000);
2418 clk_register_clkdev(clk, "pll_u_vco", NULL); 2758 clk_register_clkdev(clk, "pll_u_vco", NULL);
2419 clks[TEGRA210_CLK_PLL_U] = clk; 2759 clks[TEGRA210_CLK_PLL_U] = clk;
2760 }
2420 2761
2421 /* PLLU_OUT */ 2762 /* PLLU_OUT */
2422 clk = clk_register_divider_table(NULL, "pll_u_out", "pll_u_vco", 0, 2763 clk = clk_register_divider_table(NULL, "pll_u_out", "pll_u_vco", 0,
@@ -2651,6 +2992,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
2651 { TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1 }, 2992 { TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1 },
2652 { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 }, 2993 { TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
2653 { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 }, 2994 { TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
2995 /* TODO find a way to enable this on-demand */
2996 { TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 },
2654 { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 }, 2997 { TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
2655 { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 }, 2998 { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
2656 { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 }, 2999 { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
@@ -2661,6 +3004,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
2661 { TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 }, 3004 { TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 },
2662 { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 }, 3005 { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 },
2663 { TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 }, 3006 { TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 },
3007 { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },
3008 { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },
2664 /* This MUST be the last entry. */ 3009 /* This MUST be the last entry. */
2665 { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 }, 3010 { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
2666}; 3011};
@@ -2679,6 +3024,81 @@ static void __init tegra210_clock_apply_init_table(void)
2679} 3024}
2680 3025
2681/** 3026/**
3027 * tegra210_car_barrier - wait for pending writes to the CAR to complete
3028 *
3029 * Wait for any outstanding writes to the CAR MMIO space from this CPU
3030 * to complete before continuing execution. No return value.
3031 */
3032static void tegra210_car_barrier(void)
3033{
3034 readl_relaxed(clk_base + RST_DFLL_DVCO);
3035}
3036
3037/**
3038 * tegra210_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
3039 *
3040 * Assert the reset line of the DFLL's DVCO. No return value.
3041 */
3042static void tegra210_clock_assert_dfll_dvco_reset(void)
3043{
3044 u32 v;
3045
3046 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
3047 v |= (1 << DVFS_DFLL_RESET_SHIFT);
3048 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
3049 tegra210_car_barrier();
3050}
3051
3052/**
3053 * tegra210_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
3054 *
3055 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
3056 * operate. No return value.
3057 */
3058static void tegra210_clock_deassert_dfll_dvco_reset(void)
3059{
3060 u32 v;
3061
3062 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
3063 v &= ~(1 << DVFS_DFLL_RESET_SHIFT);
3064 writel_relaxed(v, clk_base + RST_DFLL_DVCO);
3065 tegra210_car_barrier();
3066}
3067
3068static int tegra210_reset_assert(unsigned long id)
3069{
3070 if (id == TEGRA210_RST_DFLL_DVCO)
3071 tegra210_clock_assert_dfll_dvco_reset();
3072 else if (id == TEGRA210_RST_ADSP)
3073 writel(GENMASK(26, 21) | BIT(7),
3074 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_SET);
3075 else
3076 return -EINVAL;
3077
3078 return 0;
3079}
3080
3081static int tegra210_reset_deassert(unsigned long id)
3082{
3083 if (id == TEGRA210_RST_DFLL_DVCO)
3084 tegra210_clock_deassert_dfll_dvco_reset();
3085 else if (id == TEGRA210_RST_ADSP) {
3086 writel(BIT(21), clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
3087 /*
3088 * Considering adsp cpu clock (min: 12.5MHZ, max: 1GHz)
3089 * a delay of 5us ensures that it's at least
3090 * 6 * adsp_cpu_cycle_period long.
3091 */
3092 udelay(5);
3093 writel(GENMASK(26, 22) | BIT(7),
3094 clk_base + CLK_RST_CONTROLLER_RST_DEV_Y_CLR);
3095 } else
3096 return -EINVAL;
3097
3098 return 0;
3099}
3100
3101/**
2682 * tegra210_clock_init - Tegra210-specific clock initialization 3102 * tegra210_clock_init - Tegra210-specific clock initialization
2683 * @np: struct device_node * of the DT node for the SoC CAR IP block 3103 * @np: struct device_node * of the DT node for the SoC CAR IP block
2684 * 3104 *
@@ -2742,6 +3162,9 @@ static void __init tegra210_clock_init(struct device_node *np)
2742 3162
2743 tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks, 3163 tegra_super_clk_gen5_init(clk_base, pmc_base, tegra210_clks,
2744 &pll_x_params); 3164 &pll_x_params);
3165 tegra_init_special_resets(2, tegra210_reset_assert,
3166 tegra210_reset_deassert);
3167
2745 tegra_add_of_provider(np); 3168 tegra_add_of_provider(np);
2746 tegra_register_devclks(devclks, ARRAY_SIZE(devclks)); 3169 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
2747 3170
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 8e2db5ead8da..a2d163f759b4 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -817,6 +817,7 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
817 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true }, 817 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },
818 [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true }, 818 [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
819 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true }, 819 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
820 [tegra_clk_cec] = { .dt_id = TEGRA30_CLK_CEC, .present = true },
820}; 821};
821 822
822static const char *pll_e_parents[] = { "pll_ref", "pll_p" }; 823static const char *pll_e_parents[] = { "pll_ref", "pll_p" };
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index b2cdd9a235f4..ba923f0d5953 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -17,6 +17,7 @@
17#include <linux/clkdev.h> 17#include <linux/clkdev.h>
18#include <linux/clk.h> 18#include <linux/clk.h>
19#include <linux/clk-provider.h> 19#include <linux/clk-provider.h>
20#include <linux/delay.h>
20#include <linux/of.h> 21#include <linux/of.h>
21#include <linux/clk/tegra.h> 22#include <linux/clk/tegra.h>
22#include <linux/reset-controller.h> 23#include <linux/reset-controller.h>
@@ -182,6 +183,20 @@ static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev,
182 return -EINVAL; 183 return -EINVAL;
183} 184}
184 185
186static int tegra_clk_rst_reset(struct reset_controller_dev *rcdev,
187 unsigned long id)
188{
189 int err;
190
191 err = tegra_clk_rst_assert(rcdev, id);
192 if (err)
193 return err;
194
195 udelay(1);
196
197 return tegra_clk_rst_deassert(rcdev, id);
198}
199
185const struct tegra_clk_periph_regs *get_reg_bank(int clkid) 200const struct tegra_clk_periph_regs *get_reg_bank(int clkid)
186{ 201{
187 int reg_bank = clkid / 32; 202 int reg_bank = clkid / 32;
@@ -274,6 +289,7 @@ void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
274static const struct reset_control_ops rst_ops = { 289static const struct reset_control_ops rst_ops = {
275 .assert = tegra_clk_rst_assert, 290 .assert = tegra_clk_rst_assert,
276 .deassert = tegra_clk_rst_deassert, 291 .deassert = tegra_clk_rst_deassert,
292 .reset = tegra_clk_rst_reset,
277}; 293};
278 294
279static struct reset_controller_dev rst_ctlr = { 295static struct reset_controller_dev rst_ctlr = {
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 6ba82ecffd4d..945b07093afa 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -116,7 +116,7 @@ struct tegra_clk_pll_freq_table {
116 unsigned long input_rate; 116 unsigned long input_rate;
117 unsigned long output_rate; 117 unsigned long output_rate;
118 u32 n; 118 u32 n;
119 u16 m; 119 u32 m;
120 u8 p; 120 u8 p;
121 u8 cpcon; 121 u8 cpcon;
122 u16 sdm_data; 122 u16 sdm_data;
@@ -586,11 +586,11 @@ struct tegra_clk_periph {
586 586
587extern const struct clk_ops tegra_clk_periph_ops; 587extern const struct clk_ops tegra_clk_periph_ops;
588struct clk *tegra_clk_register_periph(const char *name, 588struct clk *tegra_clk_register_periph(const char *name,
589 const char **parent_names, int num_parents, 589 const char * const *parent_names, int num_parents,
590 struct tegra_clk_periph *periph, void __iomem *clk_base, 590 struct tegra_clk_periph *periph, void __iomem *clk_base,
591 u32 offset, unsigned long flags); 591 u32 offset, unsigned long flags);
592struct clk *tegra_clk_register_periph_nodiv(const char *name, 592struct clk *tegra_clk_register_periph_nodiv(const char *name,
593 const char **parent_names, int num_parents, 593 const char * const *parent_names, int num_parents,
594 struct tegra_clk_periph *periph, void __iomem *clk_base, 594 struct tegra_clk_periph *periph, void __iomem *clk_base,
595 u32 offset); 595 u32 offset);
596 596
@@ -626,7 +626,7 @@ struct tegra_periph_init_data {
626 const char *name; 626 const char *name;
627 int clk_id; 627 int clk_id;
628 union { 628 union {
629 const char **parent_names; 629 const char *const *parent_names;
630 const char *parent_name; 630 const char *parent_name;
631 } p; 631 } p;
632 int num_parents; 632 int num_parents;
@@ -686,6 +686,8 @@ struct tegra_periph_init_data {
686struct tegra_clk_super_mux { 686struct tegra_clk_super_mux {
687 struct clk_hw hw; 687 struct clk_hw hw;
688 void __iomem *reg; 688 void __iomem *reg;
689 struct tegra_clk_frac_div frac_div;
690 const struct clk_ops *div_ops;
689 u8 width; 691 u8 width;
690 u8 flags; 692 u8 flags;
691 u8 div2_index; 693 u8 div2_index;
@@ -702,7 +704,10 @@ struct clk *tegra_clk_register_super_mux(const char *name,
702 const char **parent_names, u8 num_parents, 704 const char **parent_names, u8 num_parents,
703 unsigned long flags, void __iomem *reg, u8 clk_super_flags, 705 unsigned long flags, void __iomem *reg, u8 clk_super_flags,
704 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock); 706 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock);
705 707struct clk *tegra_clk_register_super_clk(const char *name,
708 const char * const *parent_names, u8 num_parents,
709 unsigned long flags, void __iomem *reg, u8 clk_super_flags,
710 spinlock_t *lock);
706/** 711/**
707 * struct clk_init_table - clock initialization table 712 * struct clk_init_table - clock initialization table
708 * @clk_id: clock id as mentioned in device tree bindings 713 * @clk_id: clock id as mentioned in device tree bindings
diff --git a/drivers/clk/ti/apll.c b/drivers/clk/ti/apll.c
index 6411e132faa2..06f486b3488c 100644
--- a/drivers/clk/ti/apll.c
+++ b/drivers/clk/ti/apll.c
@@ -55,20 +55,20 @@ static int dra7_apll_enable(struct clk_hw *hw)
55 state <<= __ffs(ad->idlest_mask); 55 state <<= __ffs(ad->idlest_mask);
56 56
57 /* Check is already locked */ 57 /* Check is already locked */
58 v = ti_clk_ll_ops->clk_readl(ad->idlest_reg); 58 v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
59 59
60 if ((v & ad->idlest_mask) == state) 60 if ((v & ad->idlest_mask) == state)
61 return r; 61 return r;
62 62
63 v = ti_clk_ll_ops->clk_readl(ad->control_reg); 63 v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
64 v &= ~ad->enable_mask; 64 v &= ~ad->enable_mask;
65 v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask); 65 v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);
66 ti_clk_ll_ops->clk_writel(v, ad->control_reg); 66 ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
67 67
68 state <<= __ffs(ad->idlest_mask); 68 state <<= __ffs(ad->idlest_mask);
69 69
70 while (1) { 70 while (1) {
71 v = ti_clk_ll_ops->clk_readl(ad->idlest_reg); 71 v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
72 if ((v & ad->idlest_mask) == state) 72 if ((v & ad->idlest_mask) == state)
73 break; 73 break;
74 if (i > MAX_APLL_WAIT_TRIES) 74 if (i > MAX_APLL_WAIT_TRIES)
@@ -99,10 +99,10 @@ static void dra7_apll_disable(struct clk_hw *hw)
99 99
100 state <<= __ffs(ad->idlest_mask); 100 state <<= __ffs(ad->idlest_mask);
101 101
102 v = ti_clk_ll_ops->clk_readl(ad->control_reg); 102 v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
103 v &= ~ad->enable_mask; 103 v &= ~ad->enable_mask;
104 v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask); 104 v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);
105 ti_clk_ll_ops->clk_writel(v, ad->control_reg); 105 ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
106} 106}
107 107
108static int dra7_apll_is_enabled(struct clk_hw *hw) 108static int dra7_apll_is_enabled(struct clk_hw *hw)
@@ -113,7 +113,7 @@ static int dra7_apll_is_enabled(struct clk_hw *hw)
113 113
114 ad = clk->dpll_data; 114 ad = clk->dpll_data;
115 115
116 v = ti_clk_ll_ops->clk_readl(ad->control_reg); 116 v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
117 v &= ad->enable_mask; 117 v &= ad->enable_mask;
118 118
119 v >>= __ffs(ad->enable_mask); 119 v >>= __ffs(ad->enable_mask);
@@ -164,7 +164,7 @@ static void __init omap_clk_register_apll(struct clk_hw *hw,
164 164
165 ad->clk_bypass = __clk_get_hw(clk); 165 ad->clk_bypass = __clk_get_hw(clk);
166 166
167 clk = clk_register(NULL, &clk_hw->hw); 167 clk = ti_clk_register(NULL, &clk_hw->hw, node->name);
168 if (!IS_ERR(clk)) { 168 if (!IS_ERR(clk)) {
169 of_clk_add_provider(node, of_clk_src_simple_get, clk); 169 of_clk_add_provider(node, of_clk_src_simple_get, clk);
170 kfree(clk_hw->hw.init->parent_names); 170 kfree(clk_hw->hw.init->parent_names);
@@ -185,6 +185,7 @@ static void __init of_dra7_apll_setup(struct device_node *node)
185 struct clk_hw_omap *clk_hw = NULL; 185 struct clk_hw_omap *clk_hw = NULL;
186 struct clk_init_data *init = NULL; 186 struct clk_init_data *init = NULL;
187 const char **parent_names = NULL; 187 const char **parent_names = NULL;
188 int ret;
188 189
189 ad = kzalloc(sizeof(*ad), GFP_KERNEL); 190 ad = kzalloc(sizeof(*ad), GFP_KERNEL);
190 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 191 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
@@ -194,7 +195,6 @@ static void __init of_dra7_apll_setup(struct device_node *node)
194 195
195 clk_hw->dpll_data = ad; 196 clk_hw->dpll_data = ad;
196 clk_hw->hw.init = init; 197 clk_hw->hw.init = init;
197 clk_hw->flags = MEMMAP_ADDRESSING;
198 198
199 init->name = node->name; 199 init->name = node->name;
200 init->ops = &apll_ck_ops; 200 init->ops = &apll_ck_ops;
@@ -213,10 +213,10 @@ static void __init of_dra7_apll_setup(struct device_node *node)
213 213
214 init->parent_names = parent_names; 214 init->parent_names = parent_names;
215 215
216 ad->control_reg = ti_clk_get_reg_addr(node, 0); 216 ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg);
217 ad->idlest_reg = ti_clk_get_reg_addr(node, 1); 217 ret |= ti_clk_get_reg_addr(node, 1, &ad->idlest_reg);
218 218
219 if (IS_ERR(ad->control_reg) || IS_ERR(ad->idlest_reg)) 219 if (ret)
220 goto cleanup; 220 goto cleanup;
221 221
222 ad->idlest_mask = 0x1; 222 ad->idlest_mask = 0x1;
@@ -242,7 +242,7 @@ static int omap2_apll_is_enabled(struct clk_hw *hw)
242 struct dpll_data *ad = clk->dpll_data; 242 struct dpll_data *ad = clk->dpll_data;
243 u32 v; 243 u32 v;
244 244
245 v = ti_clk_ll_ops->clk_readl(ad->control_reg); 245 v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
246 v &= ad->enable_mask; 246 v &= ad->enable_mask;
247 247
248 v >>= __ffs(ad->enable_mask); 248 v >>= __ffs(ad->enable_mask);
@@ -268,13 +268,13 @@ static int omap2_apll_enable(struct clk_hw *hw)
268 u32 v; 268 u32 v;
269 int i = 0; 269 int i = 0;
270 270
271 v = ti_clk_ll_ops->clk_readl(ad->control_reg); 271 v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
272 v &= ~ad->enable_mask; 272 v &= ~ad->enable_mask;
273 v |= OMAP2_EN_APLL_LOCKED << __ffs(ad->enable_mask); 273 v |= OMAP2_EN_APLL_LOCKED << __ffs(ad->enable_mask);
274 ti_clk_ll_ops->clk_writel(v, ad->control_reg); 274 ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
275 275
276 while (1) { 276 while (1) {
277 v = ti_clk_ll_ops->clk_readl(ad->idlest_reg); 277 v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);
278 if (v & ad->idlest_mask) 278 if (v & ad->idlest_mask)
279 break; 279 break;
280 if (i > MAX_APLL_WAIT_TRIES) 280 if (i > MAX_APLL_WAIT_TRIES)
@@ -298,10 +298,10 @@ static void omap2_apll_disable(struct clk_hw *hw)
298 struct dpll_data *ad = clk->dpll_data; 298 struct dpll_data *ad = clk->dpll_data;
299 u32 v; 299 u32 v;
300 300
301 v = ti_clk_ll_ops->clk_readl(ad->control_reg); 301 v = ti_clk_ll_ops->clk_readl(&ad->control_reg);
302 v &= ~ad->enable_mask; 302 v &= ~ad->enable_mask;
303 v |= OMAP2_EN_APLL_STOPPED << __ffs(ad->enable_mask); 303 v |= OMAP2_EN_APLL_STOPPED << __ffs(ad->enable_mask);
304 ti_clk_ll_ops->clk_writel(v, ad->control_reg); 304 ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
305} 305}
306 306
307static struct clk_ops omap2_apll_ops = { 307static struct clk_ops omap2_apll_ops = {
@@ -316,10 +316,10 @@ static void omap2_apll_set_autoidle(struct clk_hw_omap *clk, u32 val)
316 struct dpll_data *ad = clk->dpll_data; 316 struct dpll_data *ad = clk->dpll_data;
317 u32 v; 317 u32 v;
318 318
319 v = ti_clk_ll_ops->clk_readl(ad->autoidle_reg); 319 v = ti_clk_ll_ops->clk_readl(&ad->autoidle_reg);
320 v &= ~ad->autoidle_mask; 320 v &= ~ad->autoidle_mask;
321 v |= val << __ffs(ad->autoidle_mask); 321 v |= val << __ffs(ad->autoidle_mask);
322 ti_clk_ll_ops->clk_writel(v, ad->control_reg); 322 ti_clk_ll_ops->clk_writel(v, &ad->control_reg);
323} 323}
324 324
325#define OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP 0x3 325#define OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP 0x3
@@ -348,6 +348,7 @@ static void __init of_omap2_apll_setup(struct device_node *node)
348 struct clk *clk; 348 struct clk *clk;
349 const char *parent_name; 349 const char *parent_name;
350 u32 val; 350 u32 val;
351 int ret;
351 352
352 ad = kzalloc(sizeof(*ad), GFP_KERNEL); 353 ad = kzalloc(sizeof(*ad), GFP_KERNEL);
353 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 354 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
@@ -393,12 +394,11 @@ static void __init of_omap2_apll_setup(struct device_node *node)
393 394
394 ad->idlest_mask = 1 << val; 395 ad->idlest_mask = 1 << val;
395 396
396 ad->control_reg = ti_clk_get_reg_addr(node, 0); 397 ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg);
397 ad->autoidle_reg = ti_clk_get_reg_addr(node, 1); 398 ret |= ti_clk_get_reg_addr(node, 1, &ad->autoidle_reg);
398 ad->idlest_reg = ti_clk_get_reg_addr(node, 2); 399 ret |= ti_clk_get_reg_addr(node, 2, &ad->idlest_reg);
399 400
400 if (IS_ERR(ad->control_reg) || IS_ERR(ad->autoidle_reg) || 401 if (ret)
401 IS_ERR(ad->idlest_reg))
402 goto cleanup; 402 goto cleanup;
403 403
404 clk = clk_register(NULL, &clk_hw->hw); 404 clk = clk_register(NULL, &clk_hw->hw);
diff --git a/drivers/clk/ti/autoidle.c b/drivers/clk/ti/autoidle.c
index 345af43465f0..7bb9afbe4058 100644
--- a/drivers/clk/ti/autoidle.c
+++ b/drivers/clk/ti/autoidle.c
@@ -25,7 +25,7 @@
25#include "clock.h" 25#include "clock.h"
26 26
27struct clk_ti_autoidle { 27struct clk_ti_autoidle {
28 void __iomem *reg; 28 struct clk_omap_reg reg;
29 u8 shift; 29 u8 shift;
30 u8 flags; 30 u8 flags;
31 const char *name; 31 const char *name;
@@ -73,28 +73,28 @@ static void _allow_autoidle(struct clk_ti_autoidle *clk)
73{ 73{
74 u32 val; 74 u32 val;
75 75
76 val = ti_clk_ll_ops->clk_readl(clk->reg); 76 val = ti_clk_ll_ops->clk_readl(&clk->reg);
77 77
78 if (clk->flags & AUTOIDLE_LOW) 78 if (clk->flags & AUTOIDLE_LOW)
79 val &= ~(1 << clk->shift); 79 val &= ~(1 << clk->shift);
80 else 80 else
81 val |= (1 << clk->shift); 81 val |= (1 << clk->shift);
82 82
83 ti_clk_ll_ops->clk_writel(val, clk->reg); 83 ti_clk_ll_ops->clk_writel(val, &clk->reg);
84} 84}
85 85
86static void _deny_autoidle(struct clk_ti_autoidle *clk) 86static void _deny_autoidle(struct clk_ti_autoidle *clk)
87{ 87{
88 u32 val; 88 u32 val;
89 89
90 val = ti_clk_ll_ops->clk_readl(clk->reg); 90 val = ti_clk_ll_ops->clk_readl(&clk->reg);
91 91
92 if (clk->flags & AUTOIDLE_LOW) 92 if (clk->flags & AUTOIDLE_LOW)
93 val |= (1 << clk->shift); 93 val |= (1 << clk->shift);
94 else 94 else
95 val &= ~(1 << clk->shift); 95 val &= ~(1 << clk->shift);
96 96
97 ti_clk_ll_ops->clk_writel(val, clk->reg); 97 ti_clk_ll_ops->clk_writel(val, &clk->reg);
98} 98}
99 99
100/** 100/**
@@ -140,6 +140,7 @@ int __init of_ti_clk_autoidle_setup(struct device_node *node)
140{ 140{
141 u32 shift; 141 u32 shift;
142 struct clk_ti_autoidle *clk; 142 struct clk_ti_autoidle *clk;
143 int ret;
143 144
144 /* Check if this clock has autoidle support or not */ 145 /* Check if this clock has autoidle support or not */
145 if (of_property_read_u32(node, "ti,autoidle-shift", &shift)) 146 if (of_property_read_u32(node, "ti,autoidle-shift", &shift))
@@ -152,11 +153,10 @@ int __init of_ti_clk_autoidle_setup(struct device_node *node)
152 153
153 clk->shift = shift; 154 clk->shift = shift;
154 clk->name = node->name; 155 clk->name = node->name;
155 clk->reg = ti_clk_get_reg_addr(node, 0); 156 ret = ti_clk_get_reg_addr(node, 0, &clk->reg);
156 157 if (ret) {
157 if (IS_ERR(clk->reg)) {
158 kfree(clk); 158 kfree(clk);
159 return -EINVAL; 159 return ret;
160 } 160 }
161 161
162 if (of_property_read_bool(node, "ti,invert-autoidle-bit")) 162 if (of_property_read_bool(node, "ti,invert-autoidle-bit"))
diff --git a/drivers/clk/ti/clk-3xxx.c b/drivers/clk/ti/clk-3xxx.c
index 11d8aa3ec186..b1251cae98b8 100644
--- a/drivers/clk/ti/clk-3xxx.c
+++ b/drivers/clk/ti/clk-3xxx.c
@@ -52,14 +52,13 @@
52 * @idlest_reg and @idlest_bit. No return value. 52 * @idlest_reg and @idlest_bit. No return value.
53 */ 53 */
54static void omap3430es2_clk_ssi_find_idlest(struct clk_hw_omap *clk, 54static void omap3430es2_clk_ssi_find_idlest(struct clk_hw_omap *clk,
55 void __iomem **idlest_reg, 55 struct clk_omap_reg *idlest_reg,
56 u8 *idlest_bit, 56 u8 *idlest_bit,
57 u8 *idlest_val) 57 u8 *idlest_val)
58{ 58{
59 u32 r; 59 memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
60 60 idlest_reg->offset &= ~0xf0;
61 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); 61 idlest_reg->offset |= 0x20;
62 *idlest_reg = (__force void __iomem *)r;
63 *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT; 62 *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
64 *idlest_val = OMAP34XX_CM_IDLEST_VAL; 63 *idlest_val = OMAP34XX_CM_IDLEST_VAL;
65} 64}
@@ -85,15 +84,15 @@ const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait = {
85 * default find_idlest code assumes that they are at the same 84 * default find_idlest code assumes that they are at the same
86 * position.) No return value. 85 * position.) No return value.
87 */ 86 */
88static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk_hw_omap *clk, 87static void
89 void __iomem **idlest_reg, 88omap3430es2_clk_dss_usbhost_find_idlest(struct clk_hw_omap *clk,
90 u8 *idlest_bit, 89 struct clk_omap_reg *idlest_reg,
91 u8 *idlest_val) 90 u8 *idlest_bit, u8 *idlest_val)
92{ 91{
93 u32 r; 92 memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
94 93
95 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); 94 idlest_reg->offset &= ~0xf0;
96 *idlest_reg = (__force void __iomem *)r; 95 idlest_reg->offset |= 0x20;
97 /* USBHOST_IDLE has same shift */ 96 /* USBHOST_IDLE has same shift */
98 *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT; 97 *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
99 *idlest_val = OMAP34XX_CM_IDLEST_VAL; 98 *idlest_val = OMAP34XX_CM_IDLEST_VAL;
@@ -122,15 +121,15 @@ const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait = {
122 * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via 121 * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via
123 * @idlest_reg and @idlest_bit. No return value. 122 * @idlest_reg and @idlest_bit. No return value.
124 */ 123 */
125static void omap3430es2_clk_hsotgusb_find_idlest(struct clk_hw_omap *clk, 124static void
126 void __iomem **idlest_reg, 125omap3430es2_clk_hsotgusb_find_idlest(struct clk_hw_omap *clk,
127 u8 *idlest_bit, 126 struct clk_omap_reg *idlest_reg,
128 u8 *idlest_val) 127 u8 *idlest_bit,
128 u8 *idlest_val)
129{ 129{
130 u32 r; 130 memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
131 131 idlest_reg->offset &= ~0xf0;
132 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); 132 idlest_reg->offset |= 0x20;
133 *idlest_reg = (__force void __iomem *)r;
134 *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT; 133 *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
135 *idlest_val = OMAP34XX_CM_IDLEST_VAL; 134 *idlest_val = OMAP34XX_CM_IDLEST_VAL;
136} 135}
@@ -154,11 +153,11 @@ const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait = {
154 * bit. A value of 1 indicates that clock is enabled. 153 * bit. A value of 1 indicates that clock is enabled.
155 */ 154 */
156static void am35xx_clk_find_idlest(struct clk_hw_omap *clk, 155static void am35xx_clk_find_idlest(struct clk_hw_omap *clk,
157 void __iomem **idlest_reg, 156 struct clk_omap_reg *idlest_reg,
158 u8 *idlest_bit, 157 u8 *idlest_bit,
159 u8 *idlest_val) 158 u8 *idlest_val)
160{ 159{
161 *idlest_reg = (__force void __iomem *)(clk->enable_reg); 160 memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
162 *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET; 161 *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET;
163 *idlest_val = AM35XX_IPSS_CLK_IDLEST_VAL; 162 *idlest_val = AM35XX_IPSS_CLK_IDLEST_VAL;
164} 163}
@@ -178,10 +177,10 @@ static void am35xx_clk_find_idlest(struct clk_hw_omap *clk,
178 * avoid this issue, and remove the casts. No return value. 177 * avoid this issue, and remove the casts. No return value.
179 */ 178 */
180static void am35xx_clk_find_companion(struct clk_hw_omap *clk, 179static void am35xx_clk_find_companion(struct clk_hw_omap *clk,
181 void __iomem **other_reg, 180 struct clk_omap_reg *other_reg,
182 u8 *other_bit) 181 u8 *other_bit)
183{ 182{
184 *other_reg = (__force void __iomem *)(clk->enable_reg); 183 memcpy(other_reg, &clk->enable_reg, sizeof(*other_reg));
185 if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) 184 if (clk->enable_bit & AM35XX_IPSS_ICK_MASK)
186 *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET; 185 *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET;
187 else 186 else
@@ -205,14 +204,14 @@ const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait = {
205 * and @idlest_bit. No return value. 204 * and @idlest_bit. No return value.
206 */ 205 */
207static void am35xx_clk_ipss_find_idlest(struct clk_hw_omap *clk, 206static void am35xx_clk_ipss_find_idlest(struct clk_hw_omap *clk,
208 void __iomem **idlest_reg, 207 struct clk_omap_reg *idlest_reg,
209 u8 *idlest_bit, 208 u8 *idlest_bit,
210 u8 *idlest_val) 209 u8 *idlest_val)
211{ 210{
212 u32 r; 211 memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
213 212
214 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); 213 idlest_reg->offset &= ~0xf0;
215 *idlest_reg = (__force void __iomem *)r; 214 idlest_reg->offset |= 0x20;
216 *idlest_bit = AM35XX_ST_IPSS_SHIFT; 215 *idlest_bit = AM35XX_ST_IPSS_SHIFT;
217 *idlest_val = OMAP34XX_CM_IDLEST_VAL; 216 *idlest_val = OMAP34XX_CM_IDLEST_VAL;
218} 217}
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
index 7a8b51b35f9f..1c8bb83003bf 100644
--- a/drivers/clk/ti/clk-44xx.c
+++ b/drivers/clk/ti/clk-44xx.c
@@ -34,196 +34,13 @@
34#define OMAP4_DPLL_USB_DEFFREQ 960000000 34#define OMAP4_DPLL_USB_DEFFREQ 960000000
35 35
36static struct ti_dt_clk omap44xx_clks[] = { 36static struct ti_dt_clk omap44xx_clks[] = {
37 DT_CLK(NULL, "extalt_clkin_ck", "extalt_clkin_ck"),
38 DT_CLK(NULL, "pad_clks_src_ck", "pad_clks_src_ck"),
39 DT_CLK(NULL, "pad_clks_ck", "pad_clks_ck"),
40 DT_CLK(NULL, "pad_slimbus_core_clks_ck", "pad_slimbus_core_clks_ck"),
41 DT_CLK(NULL, "secure_32k_clk_src_ck", "secure_32k_clk_src_ck"),
42 DT_CLK(NULL, "slimbus_src_clk", "slimbus_src_clk"),
43 DT_CLK(NULL, "slimbus_clk", "slimbus_clk"),
44 DT_CLK(NULL, "sys_32k_ck", "sys_32k_ck"),
45 DT_CLK(NULL, "virt_12000000_ck", "virt_12000000_ck"),
46 DT_CLK(NULL, "virt_13000000_ck", "virt_13000000_ck"),
47 DT_CLK(NULL, "virt_16800000_ck", "virt_16800000_ck"),
48 DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"),
49 DT_CLK(NULL, "virt_26000000_ck", "virt_26000000_ck"),
50 DT_CLK(NULL, "virt_27000000_ck", "virt_27000000_ck"),
51 DT_CLK(NULL, "virt_38400000_ck", "virt_38400000_ck"),
52 DT_CLK(NULL, "sys_clkin_ck", "sys_clkin_ck"),
53 DT_CLK(NULL, "tie_low_clock_ck", "tie_low_clock_ck"),
54 DT_CLK(NULL, "utmi_phy_clkout_ck", "utmi_phy_clkout_ck"),
55 DT_CLK(NULL, "xclk60mhsp1_ck", "xclk60mhsp1_ck"),
56 DT_CLK(NULL, "xclk60mhsp2_ck", "xclk60mhsp2_ck"),
57 DT_CLK(NULL, "xclk60motg_ck", "xclk60motg_ck"),
58 DT_CLK(NULL, "abe_dpll_bypass_clk_mux_ck", "abe_dpll_bypass_clk_mux_ck"),
59 DT_CLK(NULL, "abe_dpll_refclk_mux_ck", "abe_dpll_refclk_mux_ck"),
60 DT_CLK(NULL, "dpll_abe_ck", "dpll_abe_ck"),
61 DT_CLK(NULL, "dpll_abe_x2_ck", "dpll_abe_x2_ck"),
62 DT_CLK(NULL, "dpll_abe_m2x2_ck", "dpll_abe_m2x2_ck"),
63 DT_CLK(NULL, "abe_24m_fclk", "abe_24m_fclk"),
64 DT_CLK(NULL, "abe_clk", "abe_clk"),
65 DT_CLK(NULL, "aess_fclk", "aess_fclk"),
66 DT_CLK(NULL, "dpll_abe_m3x2_ck", "dpll_abe_m3x2_ck"),
67 DT_CLK(NULL, "core_hsd_byp_clk_mux_ck", "core_hsd_byp_clk_mux_ck"),
68 DT_CLK(NULL, "dpll_core_ck", "dpll_core_ck"),
69 DT_CLK(NULL, "dpll_core_x2_ck", "dpll_core_x2_ck"),
70 DT_CLK(NULL, "dpll_core_m6x2_ck", "dpll_core_m6x2_ck"),
71 DT_CLK(NULL, "dbgclk_mux_ck", "dbgclk_mux_ck"),
72 DT_CLK(NULL, "dpll_core_m2_ck", "dpll_core_m2_ck"),
73 DT_CLK(NULL, "ddrphy_ck", "ddrphy_ck"),
74 DT_CLK(NULL, "dpll_core_m5x2_ck", "dpll_core_m5x2_ck"),
75 DT_CLK(NULL, "div_core_ck", "div_core_ck"),
76 DT_CLK(NULL, "div_iva_hs_clk", "div_iva_hs_clk"),
77 DT_CLK(NULL, "div_mpu_hs_clk", "div_mpu_hs_clk"),
78 DT_CLK(NULL, "dpll_core_m4x2_ck", "dpll_core_m4x2_ck"),
79 DT_CLK(NULL, "dll_clk_div_ck", "dll_clk_div_ck"),
80 DT_CLK(NULL, "dpll_abe_m2_ck", "dpll_abe_m2_ck"),
81 DT_CLK(NULL, "dpll_core_m3x2_ck", "dpll_core_m3x2_ck"),
82 DT_CLK(NULL, "dpll_core_m7x2_ck", "dpll_core_m7x2_ck"),
83 DT_CLK(NULL, "iva_hsd_byp_clk_mux_ck", "iva_hsd_byp_clk_mux_ck"),
84 DT_CLK(NULL, "dpll_iva_ck", "dpll_iva_ck"),
85 DT_CLK(NULL, "dpll_iva_x2_ck", "dpll_iva_x2_ck"),
86 DT_CLK(NULL, "dpll_iva_m4x2_ck", "dpll_iva_m4x2_ck"),
87 DT_CLK(NULL, "dpll_iva_m5x2_ck", "dpll_iva_m5x2_ck"),
88 DT_CLK(NULL, "dpll_mpu_ck", "dpll_mpu_ck"),
89 DT_CLK(NULL, "dpll_mpu_m2_ck", "dpll_mpu_m2_ck"),
90 DT_CLK(NULL, "per_hs_clk_div_ck", "per_hs_clk_div_ck"),
91 DT_CLK(NULL, "per_hsd_byp_clk_mux_ck", "per_hsd_byp_clk_mux_ck"),
92 DT_CLK(NULL, "dpll_per_ck", "dpll_per_ck"),
93 DT_CLK(NULL, "dpll_per_m2_ck", "dpll_per_m2_ck"),
94 DT_CLK(NULL, "dpll_per_x2_ck", "dpll_per_x2_ck"),
95 DT_CLK(NULL, "dpll_per_m2x2_ck", "dpll_per_m2x2_ck"),
96 DT_CLK(NULL, "dpll_per_m3x2_ck", "dpll_per_m3x2_ck"),
97 DT_CLK(NULL, "dpll_per_m4x2_ck", "dpll_per_m4x2_ck"),
98 DT_CLK(NULL, "dpll_per_m5x2_ck", "dpll_per_m5x2_ck"),
99 DT_CLK(NULL, "dpll_per_m6x2_ck", "dpll_per_m6x2_ck"),
100 DT_CLK(NULL, "dpll_per_m7x2_ck", "dpll_per_m7x2_ck"),
101 DT_CLK(NULL, "usb_hs_clk_div_ck", "usb_hs_clk_div_ck"),
102 DT_CLK(NULL, "dpll_usb_ck", "dpll_usb_ck"),
103 DT_CLK(NULL, "dpll_usb_clkdcoldo_ck", "dpll_usb_clkdcoldo_ck"),
104 DT_CLK(NULL, "dpll_usb_m2_ck", "dpll_usb_m2_ck"),
105 DT_CLK(NULL, "ducati_clk_mux_ck", "ducati_clk_mux_ck"),
106 DT_CLK(NULL, "func_12m_fclk", "func_12m_fclk"),
107 DT_CLK(NULL, "func_24m_clk", "func_24m_clk"),
108 DT_CLK(NULL, "func_24mc_fclk", "func_24mc_fclk"),
109 DT_CLK(NULL, "func_48m_fclk", "func_48m_fclk"),
110 DT_CLK(NULL, "func_48mc_fclk", "func_48mc_fclk"),
111 DT_CLK(NULL, "func_64m_fclk", "func_64m_fclk"),
112 DT_CLK(NULL, "func_96m_fclk", "func_96m_fclk"),
113 DT_CLK(NULL, "init_60m_fclk", "init_60m_fclk"),
114 DT_CLK(NULL, "l3_div_ck", "l3_div_ck"),
115 DT_CLK(NULL, "l4_div_ck", "l4_div_ck"),
116 DT_CLK(NULL, "lp_clk_div_ck", "lp_clk_div_ck"),
117 DT_CLK(NULL, "l4_wkup_clk_mux_ck", "l4_wkup_clk_mux_ck"),
118 DT_CLK("smp_twd", NULL, "mpu_periphclk"), 37 DT_CLK("smp_twd", NULL, "mpu_periphclk"),
119 DT_CLK(NULL, "ocp_abe_iclk", "ocp_abe_iclk"),
120 DT_CLK(NULL, "per_abe_24m_fclk", "per_abe_24m_fclk"),
121 DT_CLK(NULL, "per_abe_nc_fclk", "per_abe_nc_fclk"),
122 DT_CLK(NULL, "syc_clk_div_ck", "syc_clk_div_ck"),
123 DT_CLK(NULL, "aes1_fck", "aes1_fck"),
124 DT_CLK(NULL, "aes2_fck", "aes2_fck"),
125 DT_CLK(NULL, "dmic_sync_mux_ck", "dmic_sync_mux_ck"),
126 DT_CLK(NULL, "func_dmic_abe_gfclk", "func_dmic_abe_gfclk"),
127 DT_CLK(NULL, "dss_sys_clk", "dss_sys_clk"),
128 DT_CLK(NULL, "dss_tv_clk", "dss_tv_clk"),
129 DT_CLK(NULL, "dss_dss_clk", "dss_dss_clk"),
130 DT_CLK(NULL, "dss_48mhz_clk", "dss_48mhz_clk"),
131 DT_CLK(NULL, "dss_fck", "dss_fck"),
132 DT_CLK("omapdss_dss", "ick", "dss_fck"), 38 DT_CLK("omapdss_dss", "ick", "dss_fck"),
133 DT_CLK(NULL, "fdif_fck", "fdif_fck"),
134 DT_CLK(NULL, "gpio1_dbclk", "gpio1_dbclk"),
135 DT_CLK(NULL, "gpio2_dbclk", "gpio2_dbclk"),
136 DT_CLK(NULL, "gpio3_dbclk", "gpio3_dbclk"),
137 DT_CLK(NULL, "gpio4_dbclk", "gpio4_dbclk"),
138 DT_CLK(NULL, "gpio5_dbclk", "gpio5_dbclk"),
139 DT_CLK(NULL, "gpio6_dbclk", "gpio6_dbclk"),
140 DT_CLK(NULL, "sgx_clk_mux", "sgx_clk_mux"),
141 DT_CLK(NULL, "hsi_fck", "hsi_fck"),
142 DT_CLK(NULL, "iss_ctrlclk", "iss_ctrlclk"),
143 DT_CLK(NULL, "mcasp_sync_mux_ck", "mcasp_sync_mux_ck"),
144 DT_CLK(NULL, "func_mcasp_abe_gfclk", "func_mcasp_abe_gfclk"),
145 DT_CLK(NULL, "mcbsp1_sync_mux_ck", "mcbsp1_sync_mux_ck"),
146 DT_CLK(NULL, "func_mcbsp1_gfclk", "func_mcbsp1_gfclk"),
147 DT_CLK(NULL, "mcbsp2_sync_mux_ck", "mcbsp2_sync_mux_ck"),
148 DT_CLK(NULL, "func_mcbsp2_gfclk", "func_mcbsp2_gfclk"),
149 DT_CLK(NULL, "mcbsp3_sync_mux_ck", "mcbsp3_sync_mux_ck"),
150 DT_CLK(NULL, "func_mcbsp3_gfclk", "func_mcbsp3_gfclk"),
151 DT_CLK(NULL, "mcbsp4_sync_mux_ck", "mcbsp4_sync_mux_ck"),
152 DT_CLK(NULL, "per_mcbsp4_gfclk", "per_mcbsp4_gfclk"),
153 DT_CLK(NULL, "hsmmc1_fclk", "hsmmc1_fclk"),
154 DT_CLK(NULL, "hsmmc2_fclk", "hsmmc2_fclk"),
155 DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "ocp2scp_usb_phy_phy_48m"),
156 DT_CLK(NULL, "sha2md5_fck", "sha2md5_fck"),
157 DT_CLK(NULL, "slimbus1_fclk_1", "slimbus1_fclk_1"),
158 DT_CLK(NULL, "slimbus1_fclk_0", "slimbus1_fclk_0"),
159 DT_CLK(NULL, "slimbus1_fclk_2", "slimbus1_fclk_2"),
160 DT_CLK(NULL, "slimbus1_slimbus_clk", "slimbus1_slimbus_clk"),
161 DT_CLK(NULL, "slimbus2_fclk_1", "slimbus2_fclk_1"),
162 DT_CLK(NULL, "slimbus2_fclk_0", "slimbus2_fclk_0"),
163 DT_CLK(NULL, "slimbus2_slimbus_clk", "slimbus2_slimbus_clk"),
164 DT_CLK(NULL, "smartreflex_core_fck", "smartreflex_core_fck"),
165 DT_CLK(NULL, "smartreflex_iva_fck", "smartreflex_iva_fck"),
166 DT_CLK(NULL, "smartreflex_mpu_fck", "smartreflex_mpu_fck"),
167 DT_CLK(NULL, "dmt1_clk_mux", "dmt1_clk_mux"),
168 DT_CLK(NULL, "cm2_dm10_mux", "cm2_dm10_mux"),
169 DT_CLK(NULL, "cm2_dm11_mux", "cm2_dm11_mux"),
170 DT_CLK(NULL, "cm2_dm2_mux", "cm2_dm2_mux"),
171 DT_CLK(NULL, "cm2_dm3_mux", "cm2_dm3_mux"),
172 DT_CLK(NULL, "cm2_dm4_mux", "cm2_dm4_mux"),
173 DT_CLK(NULL, "timer5_sync_mux", "timer5_sync_mux"),
174 DT_CLK(NULL, "timer6_sync_mux", "timer6_sync_mux"),
175 DT_CLK(NULL, "timer7_sync_mux", "timer7_sync_mux"),
176 DT_CLK(NULL, "timer8_sync_mux", "timer8_sync_mux"),
177 DT_CLK(NULL, "cm2_dm9_mux", "cm2_dm9_mux"),
178 DT_CLK(NULL, "usb_host_fs_fck", "usb_host_fs_fck"),
179 DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"), 39 DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
180 DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
181 DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "usb_host_hs_utmi_p1_clk"),
182 DT_CLK(NULL, "utmi_p2_gfclk", "utmi_p2_gfclk"),
183 DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "usb_host_hs_utmi_p2_clk"),
184 DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "usb_host_hs_utmi_p3_clk"),
185 DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "usb_host_hs_hsic480m_p1_clk"),
186 DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "usb_host_hs_hsic60m_p1_clk"),
187 DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "usb_host_hs_hsic60m_p2_clk"),
188 DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "usb_host_hs_hsic480m_p2_clk"),
189 DT_CLK(NULL, "usb_host_hs_func48mclk", "usb_host_hs_func48mclk"),
190 DT_CLK(NULL, "usb_host_hs_fck", "usb_host_hs_fck"),
191 DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"), 40 DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
192 DT_CLK(NULL, "otg_60m_gfclk", "otg_60m_gfclk"),
193 DT_CLK(NULL, "usb_otg_hs_xclk", "usb_otg_hs_xclk"),
194 DT_CLK(NULL, "usb_otg_hs_ick", "usb_otg_hs_ick"),
195 DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"), 41 DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"),
196 DT_CLK(NULL, "usb_phy_cm_clk32k", "usb_phy_cm_clk32k"),
197 DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "usb_tll_hs_usb_ch2_clk"),
198 DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "usb_tll_hs_usb_ch0_clk"),
199 DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "usb_tll_hs_usb_ch1_clk"),
200 DT_CLK(NULL, "usb_tll_hs_ick", "usb_tll_hs_ick"),
201 DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"), 42 DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
202 DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"), 43 DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
203 DT_CLK(NULL, "usim_ck", "usim_ck"),
204 DT_CLK(NULL, "usim_fclk", "usim_fclk"),
205 DT_CLK(NULL, "pmd_stm_clock_mux_ck", "pmd_stm_clock_mux_ck"),
206 DT_CLK(NULL, "pmd_trace_clk_mux_ck", "pmd_trace_clk_mux_ck"),
207 DT_CLK(NULL, "stm_clk_div_ck", "stm_clk_div_ck"),
208 DT_CLK(NULL, "trace_clk_div_ck", "trace_clk_div_ck"),
209 DT_CLK(NULL, "auxclk0_src_ck", "auxclk0_src_ck"),
210 DT_CLK(NULL, "auxclk0_ck", "auxclk0_ck"),
211 DT_CLK(NULL, "auxclkreq0_ck", "auxclkreq0_ck"),
212 DT_CLK(NULL, "auxclk1_src_ck", "auxclk1_src_ck"),
213 DT_CLK(NULL, "auxclk1_ck", "auxclk1_ck"),
214 DT_CLK(NULL, "auxclkreq1_ck", "auxclkreq1_ck"),
215 DT_CLK(NULL, "auxclk2_src_ck", "auxclk2_src_ck"),
216 DT_CLK(NULL, "auxclk2_ck", "auxclk2_ck"),
217 DT_CLK(NULL, "auxclkreq2_ck", "auxclkreq2_ck"),
218 DT_CLK(NULL, "auxclk3_src_ck", "auxclk3_src_ck"),
219 DT_CLK(NULL, "auxclk3_ck", "auxclk3_ck"),
220 DT_CLK(NULL, "auxclkreq3_ck", "auxclkreq3_ck"),
221 DT_CLK(NULL, "auxclk4_src_ck", "auxclk4_src_ck"),
222 DT_CLK(NULL, "auxclk4_ck", "auxclk4_ck"),
223 DT_CLK(NULL, "auxclkreq4_ck", "auxclkreq4_ck"),
224 DT_CLK(NULL, "auxclk5_src_ck", "auxclk5_src_ck"),
225 DT_CLK(NULL, "auxclk5_ck", "auxclk5_ck"),
226 DT_CLK(NULL, "auxclkreq5_ck", "auxclkreq5_ck"),
227 DT_CLK("omap_i2c.1", "ick", "dummy_ck"), 44 DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
228 DT_CLK("omap_i2c.2", "ick", "dummy_ck"), 45 DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
229 DT_CLK("omap_i2c.3", "ick", "dummy_ck"), 46 DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
@@ -263,9 +80,6 @@ static struct ti_dt_clk omap44xx_clks[] = {
263 DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"), 80 DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"),
264 DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"), 81 DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"),
265 DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"), 82 DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"),
266 DT_CLK(NULL, "bandgap_fclk", "bandgap_fclk"),
267 DT_CLK(NULL, "div_ts_ck", "div_ts_ck"),
268 DT_CLK(NULL, "bandgap_ts_fclk", "bandgap_ts_fclk"),
269 { .node_name = NULL }, 83 { .node_name = NULL },
270}; 84};
271 85
@@ -278,6 +92,8 @@ int __init omap4xxx_dt_clk_init(void)
278 92
279 omap2_clk_disable_autoidle_all(); 93 omap2_clk_disable_autoidle_all();
280 94
95 ti_clk_add_aliases();
96
281 /* 97 /*
282 * Lock USB DPLL on OMAP4 devices so that the L3INIT power 98 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
283 * domain can transition to retention state when not in use. 99 * domain can transition to retention state when not in use.
diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c
index 45d05339d583..13eb04f72389 100644
--- a/drivers/clk/ti/clk-dra7-atl.c
+++ b/drivers/clk/ti/clk-dra7-atl.c
@@ -24,6 +24,9 @@
24#include <linux/of_address.h> 24#include <linux/of_address.h>
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <linux/pm_runtime.h> 26#include <linux/pm_runtime.h>
27#include <linux/clk/ti.h>
28
29#include "clock.h"
27 30
28#define DRA7_ATL_INSTANCES 4 31#define DRA7_ATL_INSTANCES 4
29 32
@@ -171,6 +174,7 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node)
171 struct clk_init_data init = { NULL }; 174 struct clk_init_data init = { NULL };
172 const char **parent_names = NULL; 175 const char **parent_names = NULL;
173 struct clk *clk; 176 struct clk *clk;
177 int ret;
174 178
175 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); 179 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
176 if (!clk_hw) { 180 if (!clk_hw) {
@@ -200,9 +204,14 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node)
200 204
201 init.parent_names = parent_names; 205 init.parent_names = parent_names;
202 206
203 clk = clk_register(NULL, &clk_hw->hw); 207 clk = ti_clk_register(NULL, &clk_hw->hw, node->name);
204 208
205 if (!IS_ERR(clk)) { 209 if (!IS_ERR(clk)) {
210 ret = ti_clk_add_alias(NULL, clk, node->name);
211 if (ret) {
212 clk_unregister(clk);
213 goto cleanup;
214 }
206 of_clk_add_provider(node, of_clk_src_simple_get, clk); 215 of_clk_add_provider(node, of_clk_src_simple_get, clk);
207 kfree(parent_names); 216 kfree(parent_names);
208 return; 217 return;
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index 5fcf247759ac..ddbad7e8d7c9 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -24,6 +24,7 @@
24#include <linux/list.h> 24#include <linux/list.h>
25#include <linux/regmap.h> 25#include <linux/regmap.h>
26#include <linux/bootmem.h> 26#include <linux/bootmem.h>
27#include <linux/device.h>
27 28
28#include "clock.h" 29#include "clock.h"
29 30
@@ -42,27 +43,29 @@ struct clk_iomap {
42 43
43static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS]; 44static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS];
44 45
45static void clk_memmap_writel(u32 val, void __iomem *reg) 46static void clk_memmap_writel(u32 val, const struct clk_omap_reg *reg)
46{ 47{
47 struct clk_omap_reg *r = (struct clk_omap_reg *)&reg; 48 struct clk_iomap *io = clk_memmaps[reg->index];
48 struct clk_iomap *io = clk_memmaps[r->index];
49 49
50 if (io->regmap) 50 if (reg->ptr)
51 regmap_write(io->regmap, r->offset, val); 51 writel_relaxed(val, reg->ptr);
52 else if (io->regmap)
53 regmap_write(io->regmap, reg->offset, val);
52 else 54 else
53 writel_relaxed(val, io->mem + r->offset); 55 writel_relaxed(val, io->mem + reg->offset);
54} 56}
55 57
56static u32 clk_memmap_readl(void __iomem *reg) 58static u32 clk_memmap_readl(const struct clk_omap_reg *reg)
57{ 59{
58 u32 val; 60 u32 val;
59 struct clk_omap_reg *r = (struct clk_omap_reg *)&reg; 61 struct clk_iomap *io = clk_memmaps[reg->index];
60 struct clk_iomap *io = clk_memmaps[r->index];
61 62
62 if (io->regmap) 63 if (reg->ptr)
63 regmap_read(io->regmap, r->offset, &val); 64 val = readl_relaxed(reg->ptr);
65 else if (io->regmap)
66 regmap_read(io->regmap, reg->offset, &val);
64 else 67 else
65 val = readl_relaxed(io->mem + r->offset); 68 val = readl_relaxed(io->mem + reg->offset);
66 69
67 return val; 70 return val;
68} 71}
@@ -161,20 +164,18 @@ int __init ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
161 * ti_clk_get_reg_addr - get register address for a clock register 164 * ti_clk_get_reg_addr - get register address for a clock register
162 * @node: device node for the clock 165 * @node: device node for the clock
163 * @index: register index from the clock node 166 * @index: register index from the clock node
167 * @reg: pointer to target register struct
164 * 168 *
165 * Builds clock register address from device tree information. This 169 * Builds clock register address from device tree information, and returns
166 * is a struct of type clk_omap_reg. Returns a pointer to the register 170 * the data via the provided output pointer @reg. Returns 0 on success,
167 * address, or a pointer error value in failure. 171 * negative error value on failure.
168 */ 172 */
169void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index) 173int ti_clk_get_reg_addr(struct device_node *node, int index,
174 struct clk_omap_reg *reg)
170{ 175{
171 struct clk_omap_reg *reg;
172 u32 val; 176 u32 val;
173 u32 tmp;
174 int i; 177 int i;
175 178
176 reg = (struct clk_omap_reg *)&tmp;
177
178 for (i = 0; i < CLK_MAX_MEMMAPS; i++) { 179 for (i = 0; i < CLK_MAX_MEMMAPS; i++) {
179 if (clocks_node_ptr[i] == node->parent) 180 if (clocks_node_ptr[i] == node->parent)
180 break; 181 break;
@@ -182,19 +183,20 @@ void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index)
182 183
183 if (i == CLK_MAX_MEMMAPS) { 184 if (i == CLK_MAX_MEMMAPS) {
184 pr_err("clk-provider not found for %s!\n", node->name); 185 pr_err("clk-provider not found for %s!\n", node->name);
185 return IOMEM_ERR_PTR(-ENOENT); 186 return -ENOENT;
186 } 187 }
187 188
188 reg->index = i; 189 reg->index = i;
189 190
190 if (of_property_read_u32_index(node, "reg", index, &val)) { 191 if (of_property_read_u32_index(node, "reg", index, &val)) {
191 pr_err("%s must have reg[%d]!\n", node->name, index); 192 pr_err("%s must have reg[%d]!\n", node->name, index);
192 return IOMEM_ERR_PTR(-EINVAL); 193 return -EINVAL;
193 } 194 }
194 195
195 reg->offset = val; 196 reg->offset = val;
197 reg->ptr = NULL;
196 198
197 return (__force void __iomem *)tmp; 199 return 0;
198} 200}
199 201
200/** 202/**
@@ -297,6 +299,7 @@ struct clk __init *ti_clk_register_clk(struct ti_clk *setup)
297 struct ti_clk_fixed *fixed; 299 struct ti_clk_fixed *fixed;
298 struct ti_clk_fixed_factor *fixed_factor; 300 struct ti_clk_fixed_factor *fixed_factor;
299 struct clk_hw *clk_hw; 301 struct clk_hw *clk_hw;
302 int ret;
300 303
301 if (setup->clk) 304 if (setup->clk)
302 return setup->clk; 305 return setup->clk;
@@ -307,6 +310,13 @@ struct clk __init *ti_clk_register_clk(struct ti_clk *setup)
307 310
308 clk = clk_register_fixed_rate(NULL, setup->name, NULL, 0, 311 clk = clk_register_fixed_rate(NULL, setup->name, NULL, 0,
309 fixed->frequency); 312 fixed->frequency);
313 if (!IS_ERR(clk)) {
314 ret = ti_clk_add_alias(NULL, clk, setup->name);
315 if (ret) {
316 clk_unregister(clk);
317 clk = ERR_PTR(ret);
318 }
319 }
310 break; 320 break;
311 case TI_CLK_MUX: 321 case TI_CLK_MUX:
312 clk = ti_clk_register_mux(setup); 322 clk = ti_clk_register_mux(setup);
@@ -324,6 +334,13 @@ struct clk __init *ti_clk_register_clk(struct ti_clk *setup)
324 fixed_factor->parent, 334 fixed_factor->parent,
325 0, fixed_factor->mult, 335 0, fixed_factor->mult,
326 fixed_factor->div); 336 fixed_factor->div);
337 if (!IS_ERR(clk)) {
338 ret = ti_clk_add_alias(NULL, clk, setup->name);
339 if (ret) {
340 clk_unregister(clk);
341 clk = ERR_PTR(ret);
342 }
343 }
327 break; 344 break;
328 case TI_CLK_GATE: 345 case TI_CLK_GATE:
329 clk = ti_clk_register_gate(setup); 346 clk = ti_clk_register_gate(setup);
@@ -354,6 +371,12 @@ struct clk __init *ti_clk_register_clk(struct ti_clk *setup)
354 return clk; 371 return clk;
355} 372}
356 373
374static const struct of_device_id simple_clk_match_table[] __initconst = {
375 { .compatible = "fixed-clock" },
376 { .compatible = "fixed-factor-clock" },
377 { }
378};
379
357int __init ti_clk_register_legacy_clks(struct ti_clk_alias *clks) 380int __init ti_clk_register_legacy_clks(struct ti_clk_alias *clks)
358{ 381{
359 struct clk *clk; 382 struct clk *clk;
@@ -371,9 +394,6 @@ int __init ti_clk_register_legacy_clks(struct ti_clk_alias *clks)
371 clks->clk->name, PTR_ERR(clk)); 394 clks->clk->name, PTR_ERR(clk));
372 return PTR_ERR(clk); 395 return PTR_ERR(clk);
373 } 396 }
374 } else {
375 clks->lk.clk = clk;
376 clkdev_add(&clks->lk);
377 } 397 }
378 clks++; 398 clks++;
379 } 399 }
@@ -396,8 +416,6 @@ int __init ti_clk_register_legacy_clks(struct ti_clk_alias *clks)
396 } 416 }
397 } else { 417 } else {
398 retry = true; 418 retry = true;
399 retry_clk->lk.clk = clk;
400 clkdev_add(&retry_clk->lk);
401 list_del(&retry_clk->link); 419 list_del(&retry_clk->link);
402 } 420 }
403 } 421 }
@@ -408,6 +426,26 @@ int __init ti_clk_register_legacy_clks(struct ti_clk_alias *clks)
408#endif 426#endif
409 427
410/** 428/**
429 * ti_clk_add_aliases - setup clock aliases
430 *
431 * Sets up any missing clock aliases. No return value.
432 */
433void __init ti_clk_add_aliases(void)
434{
435 struct device_node *np;
436 struct clk *clk;
437
438 for_each_matching_node(np, simple_clk_match_table) {
439 struct of_phandle_args clkspec;
440
441 clkspec.np = np;
442 clk = of_clk_get_from_provider(&clkspec);
443
444 ti_clk_add_alias(NULL, clk, np->name);
445 }
446}
447
448/**
411 * ti_clk_setup_features - setup clock features flags 449 * ti_clk_setup_features - setup clock features flags
412 * @features: features definition to use 450 * @features: features definition to use
413 * 451 *
@@ -453,3 +491,66 @@ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks)
453 clk_prepare_enable(init_clk); 491 clk_prepare_enable(init_clk);
454 } 492 }
455} 493}
494
495/**
496 * ti_clk_add_alias - add a clock alias for a TI clock
497 * @dev: device alias for this clock
498 * @clk: clock handle to create alias for
499 * @con: connection ID for this clock
500 *
501 * Creates a clock alias for a TI clock. Allocates the clock lookup entry
502 * and assigns the data to it. Returns 0 if successful, negative error
503 * value otherwise.
504 */
505int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con)
506{
507 struct clk_lookup *cl;
508
509 if (!clk)
510 return 0;
511
512 if (IS_ERR(clk))
513 return PTR_ERR(clk);
514
515 cl = kzalloc(sizeof(*cl), GFP_KERNEL);
516 if (!cl)
517 return -ENOMEM;
518
519 if (dev)
520 cl->dev_id = dev_name(dev);
521 cl->con_id = con;
522 cl->clk = clk;
523
524 clkdev_add(cl);
525
526 return 0;
527}
528
529/**
530 * ti_clk_register - register a TI clock to the common clock framework
531 * @dev: device for this clock
532 * @hw: hardware clock handle
533 * @con: connection ID for this clock
534 *
535 * Registers a TI clock to the common clock framework, and adds a clock
536 * alias for it. Returns a handle to the registered clock if successful,
537 * ERR_PTR value in failure.
538 */
539struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
540 const char *con)
541{
542 struct clk *clk;
543 int ret;
544
545 clk = clk_register(dev, hw);
546 if (IS_ERR(clk))
547 return clk;
548
549 ret = ti_clk_add_alias(dev, clk, con);
550 if (ret) {
551 clk_unregister(clk);
552 return ERR_PTR(ret);
553 }
554
555 return clk;
556}
diff --git a/drivers/clk/ti/clkt_dflt.c b/drivers/clk/ti/clkt_dflt.c
index c6ae563801d7..91751dd26b16 100644
--- a/drivers/clk/ti/clkt_dflt.c
+++ b/drivers/clk/ti/clkt_dflt.c
@@ -55,7 +55,8 @@
55 * elapsed. XXX Deprecated - should be moved into drivers for the 55 * elapsed. XXX Deprecated - should be moved into drivers for the
56 * individual IP block that the IDLEST register exists in. 56 * individual IP block that the IDLEST register exists in.
57 */ 57 */
58static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, 58static int _wait_idlest_generic(struct clk_hw_omap *clk,
59 struct clk_omap_reg *reg,
59 u32 mask, u8 idlest, const char *name) 60 u32 mask, u8 idlest, const char *name)
60{ 61{
61 int i = 0, ena = 0; 62 int i = 0, ena = 0;
@@ -91,7 +92,7 @@ static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg,
91 */ 92 */
92static void _omap2_module_wait_ready(struct clk_hw_omap *clk) 93static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
93{ 94{
94 void __iomem *companion_reg, *idlest_reg; 95 struct clk_omap_reg companion_reg, idlest_reg;
95 u8 other_bit, idlest_bit, idlest_val, idlest_reg_id; 96 u8 other_bit, idlest_bit, idlest_val, idlest_reg_id;
96 s16 prcm_mod; 97 s16 prcm_mod;
97 int r; 98 int r;
@@ -99,17 +100,17 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
99 /* Not all modules have multiple clocks that their IDLEST depends on */ 100 /* Not all modules have multiple clocks that their IDLEST depends on */
100 if (clk->ops->find_companion) { 101 if (clk->ops->find_companion) {
101 clk->ops->find_companion(clk, &companion_reg, &other_bit); 102 clk->ops->find_companion(clk, &companion_reg, &other_bit);
102 if (!(ti_clk_ll_ops->clk_readl(companion_reg) & 103 if (!(ti_clk_ll_ops->clk_readl(&companion_reg) &
103 (1 << other_bit))) 104 (1 << other_bit)))
104 return; 105 return;
105 } 106 }
106 107
107 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); 108 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
108 r = ti_clk_ll_ops->cm_split_idlest_reg(idlest_reg, &prcm_mod, 109 r = ti_clk_ll_ops->cm_split_idlest_reg(&idlest_reg, &prcm_mod,
109 &idlest_reg_id); 110 &idlest_reg_id);
110 if (r) { 111 if (r) {
111 /* IDLEST register not in the CM module */ 112 /* IDLEST register not in the CM module */
112 _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit), 113 _wait_idlest_generic(clk, &idlest_reg, (1 << idlest_bit),
113 idlest_val, clk_hw_get_name(&clk->hw)); 114 idlest_val, clk_hw_get_name(&clk->hw));
114 } else { 115 } else {
115 ti_clk_ll_ops->cm_wait_module_ready(0, prcm_mod, idlest_reg_id, 116 ti_clk_ll_ops->cm_wait_module_ready(0, prcm_mod, idlest_reg_id,
@@ -139,17 +140,17 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
139 * avoid this issue, and remove the casts. No return value. 140 * avoid this issue, and remove the casts. No return value.
140 */ 141 */
141void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, 142void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
142 void __iomem **other_reg, u8 *other_bit) 143 struct clk_omap_reg *other_reg,
144 u8 *other_bit)
143{ 145{
144 u32 r; 146 memcpy(other_reg, &clk->enable_reg, sizeof(*other_reg));
145 147
146 /* 148 /*
147 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes 149 * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes
148 * it's just a matter of XORing the bits. 150 * it's just a matter of XORing the bits.
149 */ 151 */
150 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); 152 other_reg->offset ^= (CM_FCLKEN ^ CM_ICLKEN);
151 153
152 *other_reg = (__force void __iomem *)r;
153 *other_bit = clk->enable_bit; 154 *other_bit = clk->enable_bit;
154} 155}
155 156
@@ -168,13 +169,14 @@ void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
168 * CM_IDLEST2). This is not true for all modules. No return value. 169 * CM_IDLEST2). This is not true for all modules. No return value.
169 */ 170 */
170void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, 171void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
171 void __iomem **idlest_reg, u8 *idlest_bit, 172 struct clk_omap_reg *idlest_reg, u8 *idlest_bit,
172 u8 *idlest_val) 173 u8 *idlest_val)
173{ 174{
174 u32 r; 175 memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
176
177 idlest_reg->offset &= ~0xf0;
178 idlest_reg->offset |= 0x20;
175 179
176 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
177 *idlest_reg = (__force void __iomem *)r;
178 *idlest_bit = clk->enable_bit; 180 *idlest_bit = clk->enable_bit;
179 181
180 /* 182 /*
@@ -222,31 +224,19 @@ int omap2_dflt_clk_enable(struct clk_hw *hw)
222 } 224 }
223 } 225 }
224 226
225 if (IS_ERR(clk->enable_reg)) {
226 pr_err("%s: %s missing enable_reg\n", __func__,
227 clk_hw_get_name(hw));
228 ret = -EINVAL;
229 goto err;
230 }
231
232 /* FIXME should not have INVERT_ENABLE bit here */ 227 /* FIXME should not have INVERT_ENABLE bit here */
233 v = ti_clk_ll_ops->clk_readl(clk->enable_reg); 228 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
234 if (clk->flags & INVERT_ENABLE) 229 if (clk->flags & INVERT_ENABLE)
235 v &= ~(1 << clk->enable_bit); 230 v &= ~(1 << clk->enable_bit);
236 else 231 else
237 v |= (1 << clk->enable_bit); 232 v |= (1 << clk->enable_bit);
238 ti_clk_ll_ops->clk_writel(v, clk->enable_reg); 233 ti_clk_ll_ops->clk_writel(v, &clk->enable_reg);
239 v = ti_clk_ll_ops->clk_readl(clk->enable_reg); /* OCP barrier */ 234 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); /* OCP barrier */
240 235
241 if (clk->ops && clk->ops->find_idlest) 236 if (clk->ops && clk->ops->find_idlest)
242 _omap2_module_wait_ready(clk); 237 _omap2_module_wait_ready(clk);
243 238
244 return 0; 239 return 0;
245
246err:
247 if (clkdm_control && clk->clkdm)
248 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
249 return ret;
250} 240}
251 241
252/** 242/**
@@ -264,22 +254,13 @@ void omap2_dflt_clk_disable(struct clk_hw *hw)
264 u32 v; 254 u32 v;
265 255
266 clk = to_clk_hw_omap(hw); 256 clk = to_clk_hw_omap(hw);
267 if (IS_ERR(clk->enable_reg)) {
268 /*
269 * 'independent' here refers to a clock which is not
270 * controlled by its parent.
271 */
272 pr_err("%s: independent clock %s has no enable_reg\n",
273 __func__, clk_hw_get_name(hw));
274 return;
275 }
276 257
277 v = ti_clk_ll_ops->clk_readl(clk->enable_reg); 258 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
278 if (clk->flags & INVERT_ENABLE) 259 if (clk->flags & INVERT_ENABLE)
279 v |= (1 << clk->enable_bit); 260 v |= (1 << clk->enable_bit);
280 else 261 else
281 v &= ~(1 << clk->enable_bit); 262 v &= ~(1 << clk->enable_bit);
282 ti_clk_ll_ops->clk_writel(v, clk->enable_reg); 263 ti_clk_ll_ops->clk_writel(v, &clk->enable_reg);
283 /* No OCP barrier needed here since it is a disable operation */ 264 /* No OCP barrier needed here since it is a disable operation */
284 265
285 if (!(ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) && 266 if (!(ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) &&
@@ -300,7 +281,7 @@ int omap2_dflt_clk_is_enabled(struct clk_hw *hw)
300 struct clk_hw_omap *clk = to_clk_hw_omap(hw); 281 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
301 u32 v; 282 u32 v;
302 283
303 v = ti_clk_ll_ops->clk_readl(clk->enable_reg); 284 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg);
304 285
305 if (clk->flags & INVERT_ENABLE) 286 if (clk->flags & INVERT_ENABLE)
306 v ^= BIT(clk->enable_bit); 287 v ^= BIT(clk->enable_bit);
diff --git a/drivers/clk/ti/clkt_dpll.c b/drivers/clk/ti/clkt_dpll.c
index b919fdfe8256..ce98da2c10be 100644
--- a/drivers/clk/ti/clkt_dpll.c
+++ b/drivers/clk/ti/clkt_dpll.c
@@ -213,7 +213,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw)
213 if (!dd) 213 if (!dd)
214 return -EINVAL; 214 return -EINVAL;
215 215
216 v = ti_clk_ll_ops->clk_readl(dd->control_reg); 216 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
217 v &= dd->enable_mask; 217 v &= dd->enable_mask;
218 v >>= __ffs(dd->enable_mask); 218 v >>= __ffs(dd->enable_mask);
219 219
@@ -249,14 +249,14 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
249 return 0; 249 return 0;
250 250
251 /* Return bypass rate if DPLL is bypassed */ 251 /* Return bypass rate if DPLL is bypassed */
252 v = ti_clk_ll_ops->clk_readl(dd->control_reg); 252 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
253 v &= dd->enable_mask; 253 v &= dd->enable_mask;
254 v >>= __ffs(dd->enable_mask); 254 v >>= __ffs(dd->enable_mask);
255 255
256 if (_omap2_dpll_is_in_bypass(v)) 256 if (_omap2_dpll_is_in_bypass(v))
257 return clk_hw_get_rate(dd->clk_bypass); 257 return clk_hw_get_rate(dd->clk_bypass);
258 258
259 v = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg); 259 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
260 dpll_mult = v & dd->mult_mask; 260 dpll_mult = v & dd->mult_mask;
261 dpll_mult >>= __ffs(dd->mult_mask); 261 dpll_mult >>= __ffs(dd->mult_mask);
262 dpll_div = v & dd->div1_mask; 262 dpll_div = v & dd->div1_mask;
diff --git a/drivers/clk/ti/clkt_iclk.c b/drivers/clk/ti/clkt_iclk.c
index 38c36908cf88..60b583d7db33 100644
--- a/drivers/clk/ti/clkt_iclk.c
+++ b/drivers/clk/ti/clkt_iclk.c
@@ -31,28 +31,29 @@
31void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk) 31void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk)
32{ 32{
33 u32 v; 33 u32 v;
34 void __iomem *r; 34 struct clk_omap_reg r;
35 35
36 r = (__force void __iomem *) 36 memcpy(&r, &clk->enable_reg, sizeof(r));
37 ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); 37 r.offset ^= (CM_AUTOIDLE ^ CM_ICLKEN);
38 38
39 v = ti_clk_ll_ops->clk_readl(r); 39 v = ti_clk_ll_ops->clk_readl(&r);
40 v |= (1 << clk->enable_bit); 40 v |= (1 << clk->enable_bit);
41 ti_clk_ll_ops->clk_writel(v, r); 41 ti_clk_ll_ops->clk_writel(v, &r);
42} 42}
43 43
44/* XXX */ 44/* XXX */
45void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk) 45void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk)
46{ 46{
47 u32 v; 47 u32 v;
48 void __iomem *r; 48 struct clk_omap_reg r;
49 49
50 r = (__force void __iomem *) 50 memcpy(&r, &clk->enable_reg, sizeof(r));
51 ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
52 51
53 v = ti_clk_ll_ops->clk_readl(r); 52 r.offset ^= (CM_AUTOIDLE ^ CM_ICLKEN);
53
54 v = ti_clk_ll_ops->clk_readl(&r);
54 v &= ~(1 << clk->enable_bit); 55 v &= ~(1 << clk->enable_bit);
55 ti_clk_ll_ops->clk_writel(v, r); 56 ti_clk_ll_ops->clk_writel(v, &r);
56} 57}
57 58
58/** 59/**
@@ -68,14 +69,12 @@ void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk)
68 * modules. No return value. 69 * modules. No return value.
69 */ 70 */
70static void omap2430_clk_i2chs_find_idlest(struct clk_hw_omap *clk, 71static void omap2430_clk_i2chs_find_idlest(struct clk_hw_omap *clk,
71 void __iomem **idlest_reg, 72 struct clk_omap_reg *idlest_reg,
72 u8 *idlest_bit, 73 u8 *idlest_bit,
73 u8 *idlest_val) 74 u8 *idlest_val)
74{ 75{
75 u32 r; 76 memcpy(idlest_reg, &clk->enable_reg, sizeof(*idlest_reg));
76 77 idlest_reg->offset ^= (OMAP24XX_CM_FCLKEN2 ^ CM_IDLEST);
77 r = ((__force u32)clk->enable_reg ^ (OMAP24XX_CM_FCLKEN2 ^ CM_IDLEST));
78 *idlest_reg = (__force void __iomem *)r;
79 *idlest_bit = clk->enable_bit; 78 *idlest_bit = clk->enable_bit;
80 *idlest_val = OMAP24XX_CM_IDLEST_VAL; 79 *idlest_val = OMAP24XX_CM_IDLEST_VAL;
81} 80}
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index 13c37f48d9d6..3f7b26540be8 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -16,6 +16,28 @@
16#ifndef __DRIVERS_CLK_TI_CLOCK__ 16#ifndef __DRIVERS_CLK_TI_CLOCK__
17#define __DRIVERS_CLK_TI_CLOCK__ 17#define __DRIVERS_CLK_TI_CLOCK__
18 18
19struct clk_omap_divider {
20 struct clk_hw hw;
21 struct clk_omap_reg reg;
22 u8 shift;
23 u8 width;
24 u8 flags;
25 const struct clk_div_table *table;
26};
27
28#define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw)
29
30struct clk_omap_mux {
31 struct clk_hw hw;
32 struct clk_omap_reg reg;
33 u32 *table;
34 u32 mask;
35 u8 shift;
36 u8 flags;
37};
38
39#define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw)
40
19enum { 41enum {
20 TI_CLK_FIXED, 42 TI_CLK_FIXED,
21 TI_CLK_MUX, 43 TI_CLK_MUX,
@@ -86,7 +108,7 @@ struct ti_clk_mux {
86 int num_parents; 108 int num_parents;
87 u16 reg; 109 u16 reg;
88 u8 module; 110 u8 module;
89 const char **parents; 111 const char * const *parents;
90 u16 flags; 112 u16 flags;
91}; 113};
92 114
@@ -189,16 +211,25 @@ struct clk *ti_clk_register_mux(struct ti_clk *setup);
189struct clk *ti_clk_register_divider(struct ti_clk *setup); 211struct clk *ti_clk_register_divider(struct ti_clk *setup);
190struct clk *ti_clk_register_composite(struct ti_clk *setup); 212struct clk *ti_clk_register_composite(struct ti_clk *setup);
191struct clk *ti_clk_register_dpll(struct ti_clk *setup); 213struct clk *ti_clk_register_dpll(struct ti_clk *setup);
214struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
215 const char *con);
216int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con);
217void ti_clk_add_aliases(void);
192 218
193struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup); 219struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup);
194struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup); 220struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup);
195struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup); 221struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
196 222
223int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
224 u8 flags, u8 *width,
225 const struct clk_div_table **table);
226
197void ti_clk_patch_legacy_clks(struct ti_clk **patch); 227void ti_clk_patch_legacy_clks(struct ti_clk **patch);
198struct clk *ti_clk_register_clk(struct ti_clk *setup); 228struct clk *ti_clk_register_clk(struct ti_clk *setup);
199int ti_clk_register_legacy_clks(struct ti_clk_alias *clks); 229int ti_clk_register_legacy_clks(struct ti_clk_alias *clks);
200 230
201void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index); 231int ti_clk_get_reg_addr(struct device_node *node, int index,
232 struct clk_omap_reg *reg);
202void ti_dt_clocks_register(struct ti_dt_clk *oclks); 233void ti_dt_clocks_register(struct ti_dt_clk *oclks);
203int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw, 234int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
204 ti_of_clk_init_cb_t func); 235 ti_of_clk_init_cb_t func);
@@ -223,7 +254,9 @@ extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
223 254
224extern const struct clk_ops ti_clk_divider_ops; 255extern const struct clk_ops ti_clk_divider_ops;
225extern const struct clk_ops ti_clk_mux_ops; 256extern const struct clk_ops ti_clk_mux_ops;
257extern const struct clk_ops omap_gate_clk_ops;
226 258
259void omap2_init_clk_clkdm(struct clk_hw *hw);
227int omap2_clkops_enable_clkdm(struct clk_hw *hw); 260int omap2_clkops_enable_clkdm(struct clk_hw *hw);
228void omap2_clkops_disable_clkdm(struct clk_hw *hw); 261void omap2_clkops_disable_clkdm(struct clk_hw *hw);
229 262
@@ -231,10 +264,10 @@ int omap2_dflt_clk_enable(struct clk_hw *hw);
231void omap2_dflt_clk_disable(struct clk_hw *hw); 264void omap2_dflt_clk_disable(struct clk_hw *hw);
232int omap2_dflt_clk_is_enabled(struct clk_hw *hw); 265int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
233void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, 266void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
234 void __iomem **other_reg, 267 struct clk_omap_reg *other_reg,
235 u8 *other_bit); 268 u8 *other_bit);
236void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, 269void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
237 void __iomem **idlest_reg, 270 struct clk_omap_reg *idlest_reg,
238 u8 *idlest_bit, u8 *idlest_val); 271 u8 *idlest_bit, u8 *idlest_val);
239 272
240void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk); 273void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c
index 6cf9dd189a92..fbedc6a9fed0 100644
--- a/drivers/clk/ti/clockdomain.c
+++ b/drivers/clk/ti/clockdomain.c
@@ -52,10 +52,6 @@ int omap2_clkops_enable_clkdm(struct clk_hw *hw)
52 return -EINVAL; 52 return -EINVAL;
53 } 53 }
54 54
55 if (unlikely(clk->enable_reg))
56 pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__,
57 clk_hw_get_name(hw));
58
59 if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) { 55 if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) {
60 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", 56 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
61 __func__, clk_hw_get_name(hw)); 57 __func__, clk_hw_get_name(hw));
@@ -90,10 +86,6 @@ void omap2_clkops_disable_clkdm(struct clk_hw *hw)
90 return; 86 return;
91 } 87 }
92 88
93 if (unlikely(clk->enable_reg))
94 pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__,
95 clk_hw_get_name(hw));
96
97 if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) { 89 if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) {
98 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n", 90 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
99 __func__, clk_hw_get_name(hw)); 91 __func__, clk_hw_get_name(hw));
@@ -103,6 +95,36 @@ void omap2_clkops_disable_clkdm(struct clk_hw *hw)
103 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); 95 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
104} 96}
105 97
98/**
99 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
100 * @clk: OMAP clock struct ptr to use
101 *
102 * Convert a clockdomain name stored in a struct clk 'clk' into a
103 * clockdomain pointer, and save it into the struct clk. Intended to be
104 * called during clk_register(). No return value.
105 */
106void omap2_init_clk_clkdm(struct clk_hw *hw)
107{
108 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
109 struct clockdomain *clkdm;
110 const char *clk_name;
111
112 if (!clk->clkdm_name)
113 return;
114
115 clk_name = __clk_get_name(hw->clk);
116
117 clkdm = ti_clk_ll_ops->clkdm_lookup(clk->clkdm_name);
118 if (clkdm) {
119 pr_debug("clock: associated clk %s to clkdm %s\n",
120 clk_name, clk->clkdm_name);
121 clk->clkdm = clkdm;
122 } else {
123 pr_debug("clock: could not associate clk %s to clkdm %s\n",
124 clk_name, clk->clkdm_name);
125 }
126}
127
106static void __init of_ti_clockdomain_setup(struct device_node *node) 128static void __init of_ti_clockdomain_setup(struct device_node *node)
107{ 129{
108 struct clk *clk; 130 struct clk *clk;
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
index 1cf70f452e1e..beea89463ca2 100644
--- a/drivers/clk/ti/composite.c
+++ b/drivers/clk/ti/composite.c
@@ -124,8 +124,9 @@ struct clk *ti_clk_register_composite(struct ti_clk *setup)
124 struct clk_hw *mux; 124 struct clk_hw *mux;
125 struct clk_hw *div; 125 struct clk_hw *div;
126 int num_parents = 1; 126 int num_parents = 1;
127 const char **parent_names = NULL; 127 const char * const *parent_names = NULL;
128 struct clk *clk; 128 struct clk *clk;
129 int ret;
129 130
130 comp = setup->data; 131 comp = setup->data;
131 132
@@ -150,6 +151,12 @@ struct clk *ti_clk_register_composite(struct ti_clk *setup)
150 &ti_composite_divider_ops, gate, 151 &ti_composite_divider_ops, gate,
151 &ti_composite_gate_ops, 0); 152 &ti_composite_gate_ops, 0);
152 153
154 ret = ti_clk_add_alias(NULL, clk, setup->name);
155 if (ret) {
156 clk_unregister(clk);
157 return ERR_PTR(ret);
158 }
159
153 return clk; 160 return clk;
154} 161}
155#endif 162#endif
@@ -163,6 +170,7 @@ static void __init _register_composite(struct clk_hw *hw,
163 int num_parents = 0; 170 int num_parents = 0;
164 const char **parent_names = NULL; 171 const char **parent_names = NULL;
165 int i; 172 int i;
173 int ret;
166 174
167 /* Check for presence of each component clock */ 175 /* Check for presence of each component clock */
168 for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) { 176 for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) {
@@ -217,8 +225,14 @@ static void __init _register_composite(struct clk_hw *hw,
217 _get_hw(cclk, CLK_COMPONENT_TYPE_GATE), 225 _get_hw(cclk, CLK_COMPONENT_TYPE_GATE),
218 &ti_composite_gate_ops, 0); 226 &ti_composite_gate_ops, 0);
219 227
220 if (!IS_ERR(clk)) 228 if (!IS_ERR(clk)) {
229 ret = ti_clk_add_alias(NULL, clk, node->name);
230 if (ret) {
231 clk_unregister(clk);
232 goto cleanup;
233 }
221 of_clk_add_provider(node, of_clk_src_simple_get, clk); 234 of_clk_add_provider(node, of_clk_src_simple_get, clk);
235 }
222 236
223cleanup: 237cleanup:
224 /* Free component clock list entries */ 238 /* Free component clock list entries */
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
index 6bb87784a0d6..d6dcb283b72b 100644
--- a/drivers/clk/ti/divider.c
+++ b/drivers/clk/ti/divider.c
@@ -39,7 +39,7 @@ static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
39 return maxdiv; 39 return maxdiv;
40} 40}
41 41
42static unsigned int _get_maxdiv(struct clk_divider *divider) 42static unsigned int _get_maxdiv(struct clk_omap_divider *divider)
43{ 43{
44 if (divider->flags & CLK_DIVIDER_ONE_BASED) 44 if (divider->flags & CLK_DIVIDER_ONE_BASED)
45 return div_mask(divider); 45 return div_mask(divider);
@@ -61,7 +61,7 @@ static unsigned int _get_table_div(const struct clk_div_table *table,
61 return 0; 61 return 0;
62} 62}
63 63
64static unsigned int _get_div(struct clk_divider *divider, unsigned int val) 64static unsigned int _get_div(struct clk_omap_divider *divider, unsigned int val)
65{ 65{
66 if (divider->flags & CLK_DIVIDER_ONE_BASED) 66 if (divider->flags & CLK_DIVIDER_ONE_BASED)
67 return val; 67 return val;
@@ -83,7 +83,7 @@ static unsigned int _get_table_val(const struct clk_div_table *table,
83 return 0; 83 return 0;
84} 84}
85 85
86static unsigned int _get_val(struct clk_divider *divider, u8 div) 86static unsigned int _get_val(struct clk_omap_divider *divider, u8 div)
87{ 87{
88 if (divider->flags & CLK_DIVIDER_ONE_BASED) 88 if (divider->flags & CLK_DIVIDER_ONE_BASED)
89 return div; 89 return div;
@@ -97,10 +97,10 @@ static unsigned int _get_val(struct clk_divider *divider, u8 div)
97static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw, 97static unsigned long ti_clk_divider_recalc_rate(struct clk_hw *hw,
98 unsigned long parent_rate) 98 unsigned long parent_rate)
99{ 99{
100 struct clk_divider *divider = to_clk_divider(hw); 100 struct clk_omap_divider *divider = to_clk_omap_divider(hw);
101 unsigned int div, val; 101 unsigned int div, val;
102 102
103 val = ti_clk_ll_ops->clk_readl(divider->reg) >> divider->shift; 103 val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift;
104 val &= div_mask(divider); 104 val &= div_mask(divider);
105 105
106 div = _get_div(divider, val); 106 div = _get_div(divider, val);
@@ -131,7 +131,7 @@ static bool _is_valid_table_div(const struct clk_div_table *table,
131 return false; 131 return false;
132} 132}
133 133
134static bool _is_valid_div(struct clk_divider *divider, unsigned int div) 134static bool _is_valid_div(struct clk_omap_divider *divider, unsigned int div)
135{ 135{
136 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) 136 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
137 return is_power_of_2(div); 137 return is_power_of_2(div);
@@ -172,7 +172,7 @@ static int _div_round(const struct clk_div_table *table,
172static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate, 172static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
173 unsigned long *best_parent_rate) 173 unsigned long *best_parent_rate)
174{ 174{
175 struct clk_divider *divider = to_clk_divider(hw); 175 struct clk_omap_divider *divider = to_clk_omap_divider(hw);
176 int i, bestdiv = 0; 176 int i, bestdiv = 0;
177 unsigned long parent_rate, best = 0, now, maxdiv; 177 unsigned long parent_rate, best = 0, now, maxdiv;
178 unsigned long parent_rate_saved = *best_parent_rate; 178 unsigned long parent_rate_saved = *best_parent_rate;
@@ -239,14 +239,14 @@ static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
239static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, 239static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
240 unsigned long parent_rate) 240 unsigned long parent_rate)
241{ 241{
242 struct clk_divider *divider; 242 struct clk_omap_divider *divider;
243 unsigned int div, value; 243 unsigned int div, value;
244 u32 val; 244 u32 val;
245 245
246 if (!hw || !rate) 246 if (!hw || !rate)
247 return -EINVAL; 247 return -EINVAL;
248 248
249 divider = to_clk_divider(hw); 249 divider = to_clk_omap_divider(hw);
250 250
251 div = DIV_ROUND_UP(parent_rate, rate); 251 div = DIV_ROUND_UP(parent_rate, rate);
252 value = _get_val(divider, div); 252 value = _get_val(divider, div);
@@ -257,11 +257,11 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
257 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { 257 if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
258 val = div_mask(divider) << (divider->shift + 16); 258 val = div_mask(divider) << (divider->shift + 16);
259 } else { 259 } else {
260 val = ti_clk_ll_ops->clk_readl(divider->reg); 260 val = ti_clk_ll_ops->clk_readl(&divider->reg);
261 val &= ~(div_mask(divider) << divider->shift); 261 val &= ~(div_mask(divider) << divider->shift);
262 } 262 }
263 val |= value << divider->shift; 263 val |= value << divider->shift;
264 ti_clk_ll_ops->clk_writel(val, divider->reg); 264 ti_clk_ll_ops->clk_writel(val, &divider->reg);
265 265
266 return 0; 266 return 0;
267} 267}
@@ -274,11 +274,12 @@ const struct clk_ops ti_clk_divider_ops = {
274 274
275static struct clk *_register_divider(struct device *dev, const char *name, 275static struct clk *_register_divider(struct device *dev, const char *name,
276 const char *parent_name, 276 const char *parent_name,
277 unsigned long flags, void __iomem *reg, 277 unsigned long flags,
278 struct clk_omap_reg *reg,
278 u8 shift, u8 width, u8 clk_divider_flags, 279 u8 shift, u8 width, u8 clk_divider_flags,
279 const struct clk_div_table *table) 280 const struct clk_div_table *table)
280{ 281{
281 struct clk_divider *div; 282 struct clk_omap_divider *div;
282 struct clk *clk; 283 struct clk *clk;
283 struct clk_init_data init; 284 struct clk_init_data init;
284 285
@@ -303,7 +304,7 @@ static struct clk *_register_divider(struct device *dev, const char *name,
303 init.num_parents = (parent_name ? 1 : 0); 304 init.num_parents = (parent_name ? 1 : 0);
304 305
305 /* struct clk_divider assignments */ 306 /* struct clk_divider assignments */
306 div->reg = reg; 307 memcpy(&div->reg, reg, sizeof(*reg));
307 div->shift = shift; 308 div->shift = shift;
308 div->width = width; 309 div->width = width;
309 div->flags = clk_divider_flags; 310 div->flags = clk_divider_flags;
@@ -311,7 +312,7 @@ static struct clk *_register_divider(struct device *dev, const char *name,
311 div->table = table; 312 div->table = table;
312 313
313 /* register the clock */ 314 /* register the clock */
314 clk = clk_register(dev, &div->hw); 315 clk = ti_clk_register(dev, &div->hw, name);
315 316
316 if (IS_ERR(clk)) 317 if (IS_ERR(clk))
317 kfree(div); 318 kfree(div);
@@ -319,20 +320,17 @@ static struct clk *_register_divider(struct device *dev, const char *name,
319 return clk; 320 return clk;
320} 321}
321 322
322static struct clk_div_table * 323int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
323_get_div_table_from_setup(struct ti_clk_divider *setup, u8 *width) 324 u8 flags, u8 *width,
325 const struct clk_div_table **table)
324{ 326{
325 int valid_div = 0; 327 int valid_div = 0;
326 struct clk_div_table *table;
327 int i;
328 int div;
329 u32 val; 328 u32 val;
330 u8 flags; 329 int div;
331 330 int i;
332 if (!setup->num_dividers) { 331 struct clk_div_table *tmp;
333 /* Clk divider table not provided, determine min/max divs */
334 flags = setup->flags;
335 332
333 if (!div_table) {
336 if (flags & CLKF_INDEX_STARTS_AT_ONE) 334 if (flags & CLKF_INDEX_STARTS_AT_ONE)
337 val = 1; 335 val = 1;
338 else 336 else
@@ -340,7 +338,7 @@ _get_div_table_from_setup(struct ti_clk_divider *setup, u8 *width)
340 338
341 div = 1; 339 div = 1;
342 340
343 while (div < setup->max_div) { 341 while (div < max_div) {
344 if (flags & CLKF_INDEX_POWER_OF_TWO) 342 if (flags & CLKF_INDEX_POWER_OF_TWO)
345 div <<= 1; 343 div <<= 1;
346 else 344 else
@@ -349,37 +347,59 @@ _get_div_table_from_setup(struct ti_clk_divider *setup, u8 *width)
349 } 347 }
350 348
351 *width = fls(val); 349 *width = fls(val);
350 *table = NULL;
352 351
353 return NULL; 352 return 0;
354 } 353 }
355 354
356 for (i = 0; i < setup->num_dividers; i++) 355 i = 0;
357 if (setup->dividers[i]) 356
357 while (!num_dividers || i < num_dividers) {
358 if (div_table[i] == -1)
359 break;
360 if (div_table[i])
358 valid_div++; 361 valid_div++;
362 i++;
363 }
359 364
360 table = kzalloc(sizeof(*table) * (valid_div + 1), GFP_KERNEL); 365 num_dividers = i;
361 if (!table) 366
362 return ERR_PTR(-ENOMEM); 367 tmp = kzalloc(sizeof(*tmp) * (valid_div + 1), GFP_KERNEL);
368 if (!tmp)
369 return -ENOMEM;
363 370
364 valid_div = 0; 371 valid_div = 0;
365 *width = 0; 372 *width = 0;
366 373
367 for (i = 0; i < setup->num_dividers; i++) 374 for (i = 0; i < num_dividers; i++)
368 if (setup->dividers[i]) { 375 if (div_table[i] > 0) {
369 table[valid_div].div = setup->dividers[i]; 376 tmp[valid_div].div = div_table[i];
370 table[valid_div].val = i; 377 tmp[valid_div].val = i;
371 valid_div++; 378 valid_div++;
372 *width = i; 379 *width = i;
373 } 380 }
374 381
375 *width = fls(*width); 382 *width = fls(*width);
383 *table = tmp;
384
385 return 0;
386}
387
388static const struct clk_div_table *
389_get_div_table_from_setup(struct ti_clk_divider *setup, u8 *width)
390{
391 const struct clk_div_table *table = NULL;
392
393 ti_clk_parse_divider_data(setup->dividers, setup->num_dividers,
394 setup->max_div, setup->flags, width,
395 &table);
376 396
377 return table; 397 return table;
378} 398}
379 399
380struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup) 400struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup)
381{ 401{
382 struct clk_divider *div; 402 struct clk_omap_divider *div;
383 struct clk_omap_reg *reg; 403 struct clk_omap_reg *reg;
384 404
385 if (!setup) 405 if (!setup)
@@ -414,7 +434,7 @@ struct clk *ti_clk_register_divider(struct ti_clk *setup)
414 u8 width; 434 u8 width;
415 u32 flags = 0; 435 u32 flags = 0;
416 u8 div_flags = 0; 436 u8 div_flags = 0;
417 struct clk_div_table *table; 437 const struct clk_div_table *table;
418 struct clk *clk; 438 struct clk *clk;
419 439
420 div = setup->data; 440 div = setup->data;
@@ -542,14 +562,15 @@ static int _get_divider_width(struct device_node *node,
542} 562}
543 563
544static int __init ti_clk_divider_populate(struct device_node *node, 564static int __init ti_clk_divider_populate(struct device_node *node,
545 void __iomem **reg, const struct clk_div_table **table, 565 struct clk_omap_reg *reg, const struct clk_div_table **table,
546 u32 *flags, u8 *div_flags, u8 *width, u8 *shift) 566 u32 *flags, u8 *div_flags, u8 *width, u8 *shift)
547{ 567{
548 u32 val; 568 u32 val;
569 int ret;
549 570
550 *reg = ti_clk_get_reg_addr(node, 0); 571 ret = ti_clk_get_reg_addr(node, 0, reg);
551 if (IS_ERR(*reg)) 572 if (ret)
552 return PTR_ERR(*reg); 573 return ret;
553 574
554 if (!of_property_read_u32(node, "ti,bit-shift", &val)) 575 if (!of_property_read_u32(node, "ti,bit-shift", &val))
555 *shift = val; 576 *shift = val;
@@ -588,7 +609,7 @@ static void __init of_ti_divider_clk_setup(struct device_node *node)
588{ 609{
589 struct clk *clk; 610 struct clk *clk;
590 const char *parent_name; 611 const char *parent_name;
591 void __iomem *reg; 612 struct clk_omap_reg reg;
592 u8 clk_divider_flags = 0; 613 u8 clk_divider_flags = 0;
593 u8 width = 0; 614 u8 width = 0;
594 u8 shift = 0; 615 u8 shift = 0;
@@ -601,7 +622,7 @@ static void __init of_ti_divider_clk_setup(struct device_node *node)
601 &clk_divider_flags, &width, &shift)) 622 &clk_divider_flags, &width, &shift))
602 goto cleanup; 623 goto cleanup;
603 624
604 clk = _register_divider(NULL, node->name, parent_name, flags, reg, 625 clk = _register_divider(NULL, node->name, parent_name, flags, &reg,
605 shift, width, clk_divider_flags, table); 626 shift, width, clk_divider_flags, table);
606 627
607 if (!IS_ERR(clk)) { 628 if (!IS_ERR(clk)) {
@@ -617,7 +638,7 @@ CLK_OF_DECLARE(divider_clk, "ti,divider-clock", of_ti_divider_clk_setup);
617 638
618static void __init of_ti_composite_divider_clk_setup(struct device_node *node) 639static void __init of_ti_composite_divider_clk_setup(struct device_node *node)
619{ 640{
620 struct clk_divider *div; 641 struct clk_omap_divider *div;
621 u32 val; 642 u32 val;
622 643
623 div = kzalloc(sizeof(*div), GFP_KERNEL); 644 div = kzalloc(sizeof(*div), GFP_KERNEL);
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c
index 4b9a419d8e14..96d84888c6c5 100644
--- a/drivers/clk/ti/dpll.c
+++ b/drivers/clk/ti/dpll.c
@@ -185,7 +185,7 @@ static void __init _register_dpll(struct clk_hw *hw,
185 dd->clk_bypass = __clk_get_hw(clk); 185 dd->clk_bypass = __clk_get_hw(clk);
186 186
187 /* register the clock */ 187 /* register the clock */
188 clk = clk_register(NULL, &clk_hw->hw); 188 clk = ti_clk_register(NULL, &clk_hw->hw, node->name);
189 189
190 if (!IS_ERR(clk)) { 190 if (!IS_ERR(clk)) {
191 omap2_init_clk_hw_omap_clocks(&clk_hw->hw); 191 omap2_init_clk_hw_omap_clocks(&clk_hw->hw);
@@ -203,17 +203,10 @@ cleanup:
203} 203}
204 204
205#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS) 205#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_ATAGS)
206static void __iomem *_get_reg(u8 module, u16 offset) 206void _get_reg(u8 module, u16 offset, struct clk_omap_reg *reg)
207{ 207{
208 u32 reg; 208 reg->index = module;
209 struct clk_omap_reg *reg_setup; 209 reg->offset = offset;
210
211 reg_setup = (struct clk_omap_reg *)&reg;
212
213 reg_setup->index = module;
214 reg_setup->offset = offset;
215
216 return (void __iomem *)reg;
217} 210}
218 211
219struct clk *ti_clk_register_dpll(struct ti_clk *setup) 212struct clk *ti_clk_register_dpll(struct ti_clk *setup)
@@ -248,7 +241,6 @@ struct clk *ti_clk_register_dpll(struct ti_clk *setup)
248 clk_hw->dpll_data = dd; 241 clk_hw->dpll_data = dd;
249 clk_hw->ops = &clkhwops_omap3_dpll; 242 clk_hw->ops = &clkhwops_omap3_dpll;
250 clk_hw->hw.init = &init; 243 clk_hw->hw.init = &init;
251 clk_hw->flags = MEMMAP_ADDRESSING;
252 244
253 init.name = setup->name; 245 init.name = setup->name;
254 init.ops = ops; 246 init.ops = ops;
@@ -256,10 +248,10 @@ struct clk *ti_clk_register_dpll(struct ti_clk *setup)
256 init.num_parents = dpll->num_parents; 248 init.num_parents = dpll->num_parents;
257 init.parent_names = dpll->parents; 249 init.parent_names = dpll->parents;
258 250
259 dd->control_reg = _get_reg(dpll->module, dpll->control_reg); 251 _get_reg(dpll->module, dpll->control_reg, &dd->control_reg);
260 dd->idlest_reg = _get_reg(dpll->module, dpll->idlest_reg); 252 _get_reg(dpll->module, dpll->idlest_reg, &dd->idlest_reg);
261 dd->mult_div1_reg = _get_reg(dpll->module, dpll->mult_div1_reg); 253 _get_reg(dpll->module, dpll->mult_div1_reg, &dd->mult_div1_reg);
262 dd->autoidle_reg = _get_reg(dpll->module, dpll->autoidle_reg); 254 _get_reg(dpll->module, dpll->autoidle_reg, &dd->autoidle_reg);
263 255
264 dd->modes = dpll->modes; 256 dd->modes = dpll->modes;
265 dd->div1_mask = dpll->div1_mask; 257 dd->div1_mask = dpll->div1_mask;
@@ -288,7 +280,7 @@ struct clk *ti_clk_register_dpll(struct ti_clk *setup)
288 if (dpll->flags & CLKF_J_TYPE) 280 if (dpll->flags & CLKF_J_TYPE)
289 dd->flags |= DPLL_J_TYPE; 281 dd->flags |= DPLL_J_TYPE;
290 282
291 clk = clk_register(NULL, &clk_hw->hw); 283 clk = ti_clk_register(NULL, &clk_hw->hw, setup->name);
292 284
293 if (!IS_ERR(clk)) 285 if (!IS_ERR(clk))
294 return clk; 286 return clk;
@@ -320,6 +312,7 @@ static void _register_dpll_x2(struct device_node *node,
320 struct clk_hw_omap *clk_hw; 312 struct clk_hw_omap *clk_hw;
321 const char *name = node->name; 313 const char *name = node->name;
322 const char *parent_name; 314 const char *parent_name;
315 int ret;
323 316
324 parent_name = of_clk_get_parent_name(node, 0); 317 parent_name = of_clk_get_parent_name(node, 0);
325 if (!parent_name) { 318 if (!parent_name) {
@@ -339,8 +332,19 @@ static void _register_dpll_x2(struct device_node *node,
339 init.parent_names = &parent_name; 332 init.parent_names = &parent_name;
340 init.num_parents = 1; 333 init.num_parents = 1;
341 334
335 if (hw_ops == &clkhwops_omap4_dpllmx) {
336 /* Check if register defined, if not, drop hw-ops */
337 ret = of_property_count_elems_of_size(node, "reg", 1);
338 if (ret <= 0) {
339 hw_ops = NULL;
340 } else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) {
341 kfree(clk_hw);
342 return;
343 }
344 }
345
342 /* register the clock */ 346 /* register the clock */
343 clk = clk_register(NULL, &clk_hw->hw); 347 clk = ti_clk_register(NULL, &clk_hw->hw, name);
344 348
345 if (IS_ERR(clk)) { 349 if (IS_ERR(clk)) {
346 kfree(clk_hw); 350 kfree(clk_hw);
@@ -380,7 +384,6 @@ static void __init of_ti_dpll_setup(struct device_node *node,
380 clk_hw->dpll_data = dd; 384 clk_hw->dpll_data = dd;
381 clk_hw->ops = &clkhwops_omap3_dpll; 385 clk_hw->ops = &clkhwops_omap3_dpll;
382 clk_hw->hw.init = init; 386 clk_hw->hw.init = init;
383 clk_hw->flags = MEMMAP_ADDRESSING;
384 387
385 init->name = node->name; 388 init->name = node->name;
386 init->ops = ops; 389 init->ops = ops;
@@ -399,7 +402,8 @@ static void __init of_ti_dpll_setup(struct device_node *node,
399 402
400 init->parent_names = parent_names; 403 init->parent_names = parent_names;
401 404
402 dd->control_reg = ti_clk_get_reg_addr(node, 0); 405 if (ti_clk_get_reg_addr(node, 0, &dd->control_reg))
406 goto cleanup;
403 407
404 /* 408 /*
405 * Special case for OMAP2 DPLL, register order is different due to 409 * Special case for OMAP2 DPLL, register order is different due to
@@ -407,25 +411,22 @@ static void __init of_ti_dpll_setup(struct device_node *node,
407 * missing idlest_mask. 411 * missing idlest_mask.
408 */ 412 */
409 if (!dd->idlest_mask) { 413 if (!dd->idlest_mask) {
410 dd->mult_div1_reg = ti_clk_get_reg_addr(node, 1); 414 if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg))
415 goto cleanup;
411#ifdef CONFIG_ARCH_OMAP2 416#ifdef CONFIG_ARCH_OMAP2
412 clk_hw->ops = &clkhwops_omap2xxx_dpll; 417 clk_hw->ops = &clkhwops_omap2xxx_dpll;
413 omap2xxx_clkt_dpllcore_init(&clk_hw->hw); 418 omap2xxx_clkt_dpllcore_init(&clk_hw->hw);
414#endif 419#endif
415 } else { 420 } else {
416 dd->idlest_reg = ti_clk_get_reg_addr(node, 1); 421 if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg))
417 if (IS_ERR(dd->idlest_reg))
418 goto cleanup; 422 goto cleanup;
419 423
420 dd->mult_div1_reg = ti_clk_get_reg_addr(node, 2); 424 if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg))
425 goto cleanup;
421 } 426 }
422 427
423 if (IS_ERR(dd->control_reg) || IS_ERR(dd->mult_div1_reg))
424 goto cleanup;
425
426 if (dd->autoidle_mask) { 428 if (dd->autoidle_mask) {
427 dd->autoidle_reg = ti_clk_get_reg_addr(node, 3); 429 if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg))
428 if (IS_ERR(dd->autoidle_reg))
429 goto cleanup; 430 goto cleanup;
430 } 431 }
431 432
diff --git a/drivers/clk/ti/dpll3xxx.c b/drivers/clk/ti/dpll3xxx.c
index 4cdd28a25584..4534de2ef455 100644
--- a/drivers/clk/ti/dpll3xxx.c
+++ b/drivers/clk/ti/dpll3xxx.c
@@ -54,10 +54,10 @@ static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
54 54
55 dd = clk->dpll_data; 55 dd = clk->dpll_data;
56 56
57 v = ti_clk_ll_ops->clk_readl(dd->control_reg); 57 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
58 v &= ~dd->enable_mask; 58 v &= ~dd->enable_mask;
59 v |= clken_bits << __ffs(dd->enable_mask); 59 v |= clken_bits << __ffs(dd->enable_mask);
60 ti_clk_ll_ops->clk_writel(v, dd->control_reg); 60 ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
61} 61}
62 62
63/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ 63/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
@@ -73,7 +73,7 @@ static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
73 73
74 state <<= __ffs(dd->idlest_mask); 74 state <<= __ffs(dd->idlest_mask);
75 75
76 while (((ti_clk_ll_ops->clk_readl(dd->idlest_reg) & dd->idlest_mask) 76 while (((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask)
77 != state) && i < MAX_DPLL_WAIT_TRIES) { 77 != state) && i < MAX_DPLL_WAIT_TRIES) {
78 i++; 78 i++;
79 udelay(1); 79 udelay(1);
@@ -151,7 +151,7 @@ static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
151 state <<= __ffs(dd->idlest_mask); 151 state <<= __ffs(dd->idlest_mask);
152 152
153 /* Check if already locked */ 153 /* Check if already locked */
154 if ((ti_clk_ll_ops->clk_readl(dd->idlest_reg) & dd->idlest_mask) == 154 if ((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) ==
155 state) 155 state)
156 goto done; 156 goto done;
157 157
@@ -317,14 +317,14 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
317 * only since freqsel field is no longer present on other devices. 317 * only since freqsel field is no longer present on other devices.
318 */ 318 */
319 if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) { 319 if (ti_clk_get_features()->flags & TI_CLK_DPLL_HAS_FREQSEL) {
320 v = ti_clk_ll_ops->clk_readl(dd->control_reg); 320 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
321 v &= ~dd->freqsel_mask; 321 v &= ~dd->freqsel_mask;
322 v |= freqsel << __ffs(dd->freqsel_mask); 322 v |= freqsel << __ffs(dd->freqsel_mask);
323 ti_clk_ll_ops->clk_writel(v, dd->control_reg); 323 ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
324 } 324 }
325 325
326 /* Set DPLL multiplier, divider */ 326 /* Set DPLL multiplier, divider */
327 v = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg); 327 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
328 328
329 /* Handle Duty Cycle Correction */ 329 /* Handle Duty Cycle Correction */
330 if (dd->dcc_mask) { 330 if (dd->dcc_mask) {
@@ -370,11 +370,11 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
370 } 370 }
371 } 371 }
372 372
373 ti_clk_ll_ops->clk_writel(v, dd->mult_div1_reg); 373 ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
374 374
375 /* Set 4X multiplier and low-power mode */ 375 /* Set 4X multiplier and low-power mode */
376 if (dd->m4xen_mask || dd->lpmode_mask) { 376 if (dd->m4xen_mask || dd->lpmode_mask) {
377 v = ti_clk_ll_ops->clk_readl(dd->control_reg); 377 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
378 378
379 if (dd->m4xen_mask) { 379 if (dd->m4xen_mask) {
380 if (dd->last_rounded_m4xen) 380 if (dd->last_rounded_m4xen)
@@ -390,7 +390,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
390 v &= ~dd->lpmode_mask; 390 v &= ~dd->lpmode_mask;
391 } 391 }
392 392
393 ti_clk_ll_ops->clk_writel(v, dd->control_reg); 393 ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
394 } 394 }
395 395
396 /* We let the clock framework set the other output dividers later */ 396 /* We let the clock framework set the other output dividers later */
@@ -652,10 +652,10 @@ static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
652 652
653 dd = clk->dpll_data; 653 dd = clk->dpll_data;
654 654
655 if (!dd->autoidle_reg) 655 if (!dd->autoidle_mask)
656 return -EINVAL; 656 return -EINVAL;
657 657
658 v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg); 658 v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
659 v &= dd->autoidle_mask; 659 v &= dd->autoidle_mask;
660 v >>= __ffs(dd->autoidle_mask); 660 v >>= __ffs(dd->autoidle_mask);
661 661
@@ -681,7 +681,7 @@ static void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
681 681
682 dd = clk->dpll_data; 682 dd = clk->dpll_data;
683 683
684 if (!dd->autoidle_reg) 684 if (!dd->autoidle_mask)
685 return; 685 return;
686 686
687 /* 687 /*
@@ -689,10 +689,10 @@ static void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
689 * by writing 0x5 instead of 0x1. Add some mechanism to 689 * by writing 0x5 instead of 0x1. Add some mechanism to
690 * optionally enter this mode. 690 * optionally enter this mode.
691 */ 691 */
692 v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg); 692 v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
693 v &= ~dd->autoidle_mask; 693 v &= ~dd->autoidle_mask;
694 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); 694 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
695 ti_clk_ll_ops->clk_writel(v, dd->autoidle_reg); 695 ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);
696} 696}
697 697
698/** 698/**
@@ -711,13 +711,13 @@ static void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
711 711
712 dd = clk->dpll_data; 712 dd = clk->dpll_data;
713 713
714 if (!dd->autoidle_reg) 714 if (!dd->autoidle_mask)
715 return; 715 return;
716 716
717 v = ti_clk_ll_ops->clk_readl(dd->autoidle_reg); 717 v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
718 v &= ~dd->autoidle_mask; 718 v &= ~dd->autoidle_mask;
719 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); 719 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
720 ti_clk_ll_ops->clk_writel(v, dd->autoidle_reg); 720 ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);
721} 721}
722 722
723/* Clock control for DPLL outputs */ 723/* Clock control for DPLL outputs */
@@ -773,7 +773,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
773 773
774 WARN_ON(!dd->enable_mask); 774 WARN_ON(!dd->enable_mask);
775 775
776 v = ti_clk_ll_ops->clk_readl(dd->control_reg) & dd->enable_mask; 776 v = ti_clk_ll_ops->clk_readl(&dd->control_reg) & dd->enable_mask;
777 v >>= __ffs(dd->enable_mask); 777 v >>= __ffs(dd->enable_mask);
778 if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) 778 if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
779 rate = parent_rate; 779 rate = parent_rate;
diff --git a/drivers/clk/ti/dpll44xx.c b/drivers/clk/ti/dpll44xx.c
index 82c05b55a7be..d7a3f7ec8d77 100644
--- a/drivers/clk/ti/dpll44xx.c
+++ b/drivers/clk/ti/dpll44xx.c
@@ -42,17 +42,17 @@ static void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
42 u32 v; 42 u32 v;
43 u32 mask; 43 u32 mask;
44 44
45 if (!clk || !clk->clksel_reg) 45 if (!clk)
46 return; 46 return;
47 47
48 mask = clk->flags & CLOCK_CLKOUTX2 ? 48 mask = clk->flags & CLOCK_CLKOUTX2 ?
49 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : 49 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
50 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; 50 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
51 51
52 v = ti_clk_ll_ops->clk_readl(clk->clksel_reg); 52 v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg);
53 /* Clear the bit to allow gatectrl */ 53 /* Clear the bit to allow gatectrl */
54 v &= ~mask; 54 v &= ~mask;
55 ti_clk_ll_ops->clk_writel(v, clk->clksel_reg); 55 ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg);
56} 56}
57 57
58static void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) 58static void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
@@ -60,17 +60,17 @@ static void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
60 u32 v; 60 u32 v;
61 u32 mask; 61 u32 mask;
62 62
63 if (!clk || !clk->clksel_reg) 63 if (!clk)
64 return; 64 return;
65 65
66 mask = clk->flags & CLOCK_CLKOUTX2 ? 66 mask = clk->flags & CLOCK_CLKOUTX2 ?
67 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : 67 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
68 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; 68 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
69 69
70 v = ti_clk_ll_ops->clk_readl(clk->clksel_reg); 70 v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg);
71 /* Set the bit to deny gatectrl */ 71 /* Set the bit to deny gatectrl */
72 v |= mask; 72 v |= mask;
73 ti_clk_ll_ops->clk_writel(v, clk->clksel_reg); 73 ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg);
74} 74}
75 75
76const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = { 76const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
@@ -128,7 +128,7 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
128 rate = omap2_get_dpll_rate(clk); 128 rate = omap2_get_dpll_rate(clk);
129 129
130 /* regm4xen adds a multiplier of 4 to DPLL calculations */ 130 /* regm4xen adds a multiplier of 4 to DPLL calculations */
131 v = ti_clk_ll_ops->clk_readl(dd->control_reg); 131 v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
132 if (v & OMAP4430_DPLL_REGM4XEN_MASK) 132 if (v & OMAP4430_DPLL_REGM4XEN_MASK)
133 rate *= OMAP4430_REGM4XEN_MULT; 133 rate *= OMAP4430_REGM4XEN_MULT;
134 134
diff --git a/drivers/clk/ti/fixed-factor.c b/drivers/clk/ti/fixed-factor.c
index 3cd406768909..0174a51a4ba6 100644
--- a/drivers/clk/ti/fixed-factor.c
+++ b/drivers/clk/ti/fixed-factor.c
@@ -62,6 +62,7 @@ static void __init of_ti_fixed_factor_clk_setup(struct device_node *node)
62 if (!IS_ERR(clk)) { 62 if (!IS_ERR(clk)) {
63 of_clk_add_provider(node, of_clk_src_simple_get, clk); 63 of_clk_add_provider(node, of_clk_src_simple_get, clk);
64 of_ti_clk_autoidle_setup(node); 64 of_ti_clk_autoidle_setup(node);
65 ti_clk_add_alias(NULL, clk, clk_name);
65 } 66 }
66} 67}
67CLK_OF_DECLARE(ti_fixed_factor_clk, "ti,fixed-factor-clock", 68CLK_OF_DECLARE(ti_fixed_factor_clk, "ti,fixed-factor-clock",
diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c
index bc05f276f32b..7151ec3a1b07 100644
--- a/drivers/clk/ti/gate.c
+++ b/drivers/clk/ti/gate.c
@@ -35,7 +35,7 @@ static const struct clk_ops omap_gate_clkdm_clk_ops = {
35 .disable = &omap2_clkops_disable_clkdm, 35 .disable = &omap2_clkops_disable_clkdm,
36}; 36};
37 37
38static const struct clk_ops omap_gate_clk_ops = { 38const struct clk_ops omap_gate_clk_ops = {
39 .init = &omap2_init_clk_clkdm, 39 .init = &omap2_init_clk_clkdm,
40 .enable = &omap2_dflt_clk_enable, 40 .enable = &omap2_dflt_clk_enable,
41 .disable = &omap2_dflt_clk_disable, 41 .disable = &omap2_dflt_clk_disable,
@@ -62,7 +62,7 @@ static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
62 */ 62 */
63static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *hw) 63static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *hw)
64{ 64{
65 struct clk_divider *parent; 65 struct clk_omap_divider *parent;
66 struct clk_hw *parent_hw; 66 struct clk_hw *parent_hw;
67 u32 dummy_v, orig_v; 67 u32 dummy_v, orig_v;
68 int ret; 68 int ret;
@@ -72,19 +72,19 @@ static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *hw)
72 72
73 /* Parent is the x2 node, get parent of parent for the m2 div */ 73 /* Parent is the x2 node, get parent of parent for the m2 div */
74 parent_hw = clk_hw_get_parent(clk_hw_get_parent(hw)); 74 parent_hw = clk_hw_get_parent(clk_hw_get_parent(hw));
75 parent = to_clk_divider(parent_hw); 75 parent = to_clk_omap_divider(parent_hw);
76 76
77 /* Restore the dividers */ 77 /* Restore the dividers */
78 if (!ret) { 78 if (!ret) {
79 orig_v = ti_clk_ll_ops->clk_readl(parent->reg); 79 orig_v = ti_clk_ll_ops->clk_readl(&parent->reg);
80 dummy_v = orig_v; 80 dummy_v = orig_v;
81 81
82 /* Write any other value different from the Read value */ 82 /* Write any other value different from the Read value */
83 dummy_v ^= (1 << parent->shift); 83 dummy_v ^= (1 << parent->shift);
84 ti_clk_ll_ops->clk_writel(dummy_v, parent->reg); 84 ti_clk_ll_ops->clk_writel(dummy_v, &parent->reg);
85 85
86 /* Write the original divider */ 86 /* Write the original divider */
87 ti_clk_ll_ops->clk_writel(orig_v, parent->reg); 87 ti_clk_ll_ops->clk_writel(orig_v, &parent->reg);
88 } 88 }
89 89
90 return ret; 90 return ret;
@@ -92,7 +92,7 @@ static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *hw)
92 92
93static struct clk *_register_gate(struct device *dev, const char *name, 93static struct clk *_register_gate(struct device *dev, const char *name,
94 const char *parent_name, unsigned long flags, 94 const char *parent_name, unsigned long flags,
95 void __iomem *reg, u8 bit_idx, 95 struct clk_omap_reg *reg, u8 bit_idx,
96 u8 clk_gate_flags, const struct clk_ops *ops, 96 u8 clk_gate_flags, const struct clk_ops *ops,
97 const struct clk_hw_omap_ops *hw_ops) 97 const struct clk_hw_omap_ops *hw_ops)
98{ 98{
@@ -109,18 +109,18 @@ static struct clk *_register_gate(struct device *dev, const char *name,
109 init.name = name; 109 init.name = name;
110 init.ops = ops; 110 init.ops = ops;
111 111
112 clk_hw->enable_reg = reg; 112 memcpy(&clk_hw->enable_reg, reg, sizeof(*reg));
113 clk_hw->enable_bit = bit_idx; 113 clk_hw->enable_bit = bit_idx;
114 clk_hw->ops = hw_ops; 114 clk_hw->ops = hw_ops;
115 115
116 clk_hw->flags = MEMMAP_ADDRESSING | clk_gate_flags; 116 clk_hw->flags = clk_gate_flags;
117 117
118 init.parent_names = &parent_name; 118 init.parent_names = &parent_name;
119 init.num_parents = 1; 119 init.num_parents = 1;
120 120
121 init.flags = flags; 121 init.flags = flags;
122 122
123 clk = clk_register(NULL, &clk_hw->hw); 123 clk = ti_clk_register(NULL, &clk_hw->hw, name);
124 124
125 if (IS_ERR(clk)) 125 if (IS_ERR(clk))
126 kfree(clk_hw); 126 kfree(clk_hw);
@@ -133,8 +133,7 @@ struct clk *ti_clk_register_gate(struct ti_clk *setup)
133{ 133{
134 const struct clk_ops *ops = &omap_gate_clk_ops; 134 const struct clk_ops *ops = &omap_gate_clk_ops;
135 const struct clk_hw_omap_ops *hw_ops = NULL; 135 const struct clk_hw_omap_ops *hw_ops = NULL;
136 u32 reg; 136 struct clk_omap_reg reg;
137 struct clk_omap_reg *reg_setup;
138 u32 flags = 0; 137 u32 flags = 0;
139 u8 clk_gate_flags = 0; 138 u8 clk_gate_flags = 0;
140 struct ti_clk_gate *gate; 139 struct ti_clk_gate *gate;
@@ -144,8 +143,6 @@ struct clk *ti_clk_register_gate(struct ti_clk *setup)
144 if (gate->flags & CLKF_INTERFACE) 143 if (gate->flags & CLKF_INTERFACE)
145 return ti_clk_register_interface(setup); 144 return ti_clk_register_interface(setup);
146 145
147 reg_setup = (struct clk_omap_reg *)&reg;
148
149 if (gate->flags & CLKF_SET_RATE_PARENT) 146 if (gate->flags & CLKF_SET_RATE_PARENT)
150 flags |= CLK_SET_RATE_PARENT; 147 flags |= CLK_SET_RATE_PARENT;
151 148
@@ -169,11 +166,12 @@ struct clk *ti_clk_register_gate(struct ti_clk *setup)
169 if (gate->flags & CLKF_AM35XX) 166 if (gate->flags & CLKF_AM35XX)
170 hw_ops = &clkhwops_am35xx_ipss_module_wait; 167 hw_ops = &clkhwops_am35xx_ipss_module_wait;
171 168
172 reg_setup->index = gate->module; 169 reg.index = gate->module;
173 reg_setup->offset = gate->reg; 170 reg.offset = gate->reg;
171 reg.ptr = NULL;
174 172
175 return _register_gate(NULL, setup->name, gate->parent, flags, 173 return _register_gate(NULL, setup->name, gate->parent, flags,
176 (void __iomem *)reg, gate->bit_shift, 174 &reg, gate->bit_shift,
177 clk_gate_flags, ops, hw_ops); 175 clk_gate_flags, ops, hw_ops);
178} 176}
179 177
@@ -203,7 +201,6 @@ struct clk_hw *ti_clk_build_component_gate(struct ti_clk_gate *setup)
203 ops = &clkhwops_iclk_wait; 201 ops = &clkhwops_iclk_wait;
204 202
205 gate->ops = ops; 203 gate->ops = ops;
206 gate->flags = MEMMAP_ADDRESSING;
207 204
208 return &gate->hw; 205 return &gate->hw;
209} 206}
@@ -215,15 +212,14 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node,
215{ 212{
216 struct clk *clk; 213 struct clk *clk;
217 const char *parent_name; 214 const char *parent_name;
218 void __iomem *reg = NULL; 215 struct clk_omap_reg reg;
219 u8 enable_bit = 0; 216 u8 enable_bit = 0;
220 u32 val; 217 u32 val;
221 u32 flags = 0; 218 u32 flags = 0;
222 u8 clk_gate_flags = 0; 219 u8 clk_gate_flags = 0;
223 220
224 if (ops != &omap_gate_clkdm_clk_ops) { 221 if (ops != &omap_gate_clkdm_clk_ops) {
225 reg = ti_clk_get_reg_addr(node, 0); 222 if (ti_clk_get_reg_addr(node, 0, &reg))
226 if (IS_ERR(reg))
227 return; 223 return;
228 224
229 if (!of_property_read_u32(node, "ti,bit-shift", &val)) 225 if (!of_property_read_u32(node, "ti,bit-shift", &val))
@@ -243,7 +239,7 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node,
243 if (of_property_read_bool(node, "ti,set-bit-to-disable")) 239 if (of_property_read_bool(node, "ti,set-bit-to-disable"))
244 clk_gate_flags |= INVERT_ENABLE; 240 clk_gate_flags |= INVERT_ENABLE;
245 241
246 clk = _register_gate(NULL, node->name, parent_name, flags, reg, 242 clk = _register_gate(NULL, node->name, parent_name, flags, &reg,
247 enable_bit, clk_gate_flags, ops, hw_ops); 243 enable_bit, clk_gate_flags, ops, hw_ops);
248 244
249 if (!IS_ERR(clk)) 245 if (!IS_ERR(clk))
@@ -261,15 +257,13 @@ _of_ti_composite_gate_clk_setup(struct device_node *node,
261 if (!gate) 257 if (!gate)
262 return; 258 return;
263 259
264 gate->enable_reg = ti_clk_get_reg_addr(node, 0); 260 if (ti_clk_get_reg_addr(node, 0, &gate->enable_reg))
265 if (IS_ERR(gate->enable_reg))
266 goto cleanup; 261 goto cleanup;
267 262
268 of_property_read_u32(node, "ti,bit-shift", &val); 263 of_property_read_u32(node, "ti,bit-shift", &val);
269 264
270 gate->enable_bit = val; 265 gate->enable_bit = val;
271 gate->ops = hw_ops; 266 gate->ops = hw_ops;
272 gate->flags = MEMMAP_ADDRESSING;
273 267
274 if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE)) 268 if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE))
275 return; 269 return;
diff --git a/drivers/clk/ti/interface.c b/drivers/clk/ti/interface.c
index e505e6f8228d..62cf50c1e1e3 100644
--- a/drivers/clk/ti/interface.c
+++ b/drivers/clk/ti/interface.c
@@ -34,7 +34,7 @@ static const struct clk_ops ti_interface_clk_ops = {
34 34
35static struct clk *_register_interface(struct device *dev, const char *name, 35static struct clk *_register_interface(struct device *dev, const char *name,
36 const char *parent_name, 36 const char *parent_name,
37 void __iomem *reg, u8 bit_idx, 37 struct clk_omap_reg *reg, u8 bit_idx,
38 const struct clk_hw_omap_ops *ops) 38 const struct clk_hw_omap_ops *ops)
39{ 39{
40 struct clk_init_data init = { NULL }; 40 struct clk_init_data init = { NULL };
@@ -47,8 +47,7 @@ static struct clk *_register_interface(struct device *dev, const char *name,
47 47
48 clk_hw->hw.init = &init; 48 clk_hw->hw.init = &init;
49 clk_hw->ops = ops; 49 clk_hw->ops = ops;
50 clk_hw->flags = MEMMAP_ADDRESSING; 50 memcpy(&clk_hw->enable_reg, reg, sizeof(*reg));
51 clk_hw->enable_reg = reg;
52 clk_hw->enable_bit = bit_idx; 51 clk_hw->enable_bit = bit_idx;
53 52
54 init.name = name; 53 init.name = name;
@@ -58,7 +57,7 @@ static struct clk *_register_interface(struct device *dev, const char *name,
58 init.num_parents = 1; 57 init.num_parents = 1;
59 init.parent_names = &parent_name; 58 init.parent_names = &parent_name;
60 59
61 clk = clk_register(NULL, &clk_hw->hw); 60 clk = ti_clk_register(NULL, &clk_hw->hw, name);
62 61
63 if (IS_ERR(clk)) 62 if (IS_ERR(clk))
64 kfree(clk_hw); 63 kfree(clk_hw);
@@ -72,14 +71,13 @@ static struct clk *_register_interface(struct device *dev, const char *name,
72struct clk *ti_clk_register_interface(struct ti_clk *setup) 71struct clk *ti_clk_register_interface(struct ti_clk *setup)
73{ 72{
74 const struct clk_hw_omap_ops *ops = &clkhwops_iclk_wait; 73 const struct clk_hw_omap_ops *ops = &clkhwops_iclk_wait;
75 u32 reg; 74 struct clk_omap_reg reg;
76 struct clk_omap_reg *reg_setup;
77 struct ti_clk_gate *gate; 75 struct ti_clk_gate *gate;
78 76
79 gate = setup->data; 77 gate = setup->data;
80 reg_setup = (struct clk_omap_reg *)&reg; 78 reg.index = gate->module;
81 reg_setup->index = gate->module; 79 reg.offset = gate->reg;
82 reg_setup->offset = gate->reg; 80 reg.ptr = NULL;
83 81
84 if (gate->flags & CLKF_NO_WAIT) 82 if (gate->flags & CLKF_NO_WAIT)
85 ops = &clkhwops_iclk; 83 ops = &clkhwops_iclk;
@@ -97,7 +95,7 @@ struct clk *ti_clk_register_interface(struct ti_clk *setup)
97 ops = &clkhwops_am35xx_ipss_wait; 95 ops = &clkhwops_am35xx_ipss_wait;
98 96
99 return _register_interface(NULL, setup->name, gate->parent, 97 return _register_interface(NULL, setup->name, gate->parent,
100 (void __iomem *)reg, gate->bit_shift, ops); 98 &reg, gate->bit_shift, ops);
101} 99}
102#endif 100#endif
103 101
@@ -106,12 +104,11 @@ static void __init _of_ti_interface_clk_setup(struct device_node *node,
106{ 104{
107 struct clk *clk; 105 struct clk *clk;
108 const char *parent_name; 106 const char *parent_name;
109 void __iomem *reg; 107 struct clk_omap_reg reg;
110 u8 enable_bit = 0; 108 u8 enable_bit = 0;
111 u32 val; 109 u32 val;
112 110
113 reg = ti_clk_get_reg_addr(node, 0); 111 if (ti_clk_get_reg_addr(node, 0, &reg))
114 if (IS_ERR(reg))
115 return; 112 return;
116 113
117 if (!of_property_read_u32(node, "ti,bit-shift", &val)) 114 if (!of_property_read_u32(node, "ti,bit-shift", &val))
@@ -123,7 +120,7 @@ static void __init _of_ti_interface_clk_setup(struct device_node *node,
123 return; 120 return;
124 } 121 }
125 122
126 clk = _register_interface(NULL, node->name, parent_name, reg, 123 clk = _register_interface(NULL, node->name, parent_name, &reg,
127 enable_bit, ops); 124 enable_bit, ops);
128 125
129 if (!IS_ERR(clk)) 126 if (!IS_ERR(clk))
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
index 44777ab6fdeb..18c267b38461 100644
--- a/drivers/clk/ti/mux.c
+++ b/drivers/clk/ti/mux.c
@@ -28,7 +28,7 @@
28 28
29static u8 ti_clk_mux_get_parent(struct clk_hw *hw) 29static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
30{ 30{
31 struct clk_mux *mux = to_clk_mux(hw); 31 struct clk_omap_mux *mux = to_clk_omap_mux(hw);
32 int num_parents = clk_hw_get_num_parents(hw); 32 int num_parents = clk_hw_get_num_parents(hw);
33 u32 val; 33 u32 val;
34 34
@@ -39,7 +39,7 @@ static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
39 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so 39 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
40 * val = 0x4 really means "bit 2, index starts at bit 0" 40 * val = 0x4 really means "bit 2, index starts at bit 0"
41 */ 41 */
42 val = ti_clk_ll_ops->clk_readl(mux->reg) >> mux->shift; 42 val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift;
43 val &= mux->mask; 43 val &= mux->mask;
44 44
45 if (mux->table) { 45 if (mux->table) {
@@ -65,7 +65,7 @@ static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
65 65
66static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) 66static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
67{ 67{
68 struct clk_mux *mux = to_clk_mux(hw); 68 struct clk_omap_mux *mux = to_clk_omap_mux(hw);
69 u32 val; 69 u32 val;
70 70
71 if (mux->table) { 71 if (mux->table) {
@@ -81,11 +81,11 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
81 if (mux->flags & CLK_MUX_HIWORD_MASK) { 81 if (mux->flags & CLK_MUX_HIWORD_MASK) {
82 val = mux->mask << (mux->shift + 16); 82 val = mux->mask << (mux->shift + 16);
83 } else { 83 } else {
84 val = ti_clk_ll_ops->clk_readl(mux->reg); 84 val = ti_clk_ll_ops->clk_readl(&mux->reg);
85 val &= ~(mux->mask << mux->shift); 85 val &= ~(mux->mask << mux->shift);
86 } 86 }
87 val |= index << mux->shift; 87 val |= index << mux->shift;
88 ti_clk_ll_ops->clk_writel(val, mux->reg); 88 ti_clk_ll_ops->clk_writel(val, &mux->reg);
89 89
90 return 0; 90 return 0;
91} 91}
@@ -97,12 +97,12 @@ const struct clk_ops ti_clk_mux_ops = {
97}; 97};
98 98
99static struct clk *_register_mux(struct device *dev, const char *name, 99static struct clk *_register_mux(struct device *dev, const char *name,
100 const char **parent_names, u8 num_parents, 100 const char * const *parent_names,
101 unsigned long flags, void __iomem *reg, 101 u8 num_parents, unsigned long flags,
102 u8 shift, u32 mask, u8 clk_mux_flags, 102 struct clk_omap_reg *reg, u8 shift, u32 mask,
103 u32 *table) 103 u8 clk_mux_flags, u32 *table)
104{ 104{
105 struct clk_mux *mux; 105 struct clk_omap_mux *mux;
106 struct clk *clk; 106 struct clk *clk;
107 struct clk_init_data init; 107 struct clk_init_data init;
108 108
@@ -120,14 +120,14 @@ static struct clk *_register_mux(struct device *dev, const char *name,
120 init.num_parents = num_parents; 120 init.num_parents = num_parents;
121 121
122 /* struct clk_mux assignments */ 122 /* struct clk_mux assignments */
123 mux->reg = reg; 123 memcpy(&mux->reg, reg, sizeof(*reg));
124 mux->shift = shift; 124 mux->shift = shift;
125 mux->mask = mask; 125 mux->mask = mask;
126 mux->flags = clk_mux_flags; 126 mux->flags = clk_mux_flags;
127 mux->table = table; 127 mux->table = table;
128 mux->hw.init = &init; 128 mux->hw.init = &init;
129 129
130 clk = clk_register(dev, &mux->hw); 130 clk = ti_clk_register(dev, &mux->hw, name);
131 131
132 if (IS_ERR(clk)) 132 if (IS_ERR(clk))
133 kfree(mux); 133 kfree(mux);
@@ -140,12 +140,9 @@ struct clk *ti_clk_register_mux(struct ti_clk *setup)
140 struct ti_clk_mux *mux; 140 struct ti_clk_mux *mux;
141 u32 flags; 141 u32 flags;
142 u8 mux_flags = 0; 142 u8 mux_flags = 0;
143 struct clk_omap_reg *reg_setup; 143 struct clk_omap_reg reg;
144 u32 reg;
145 u32 mask; 144 u32 mask;
146 145
147 reg_setup = (struct clk_omap_reg *)&reg;
148
149 mux = setup->data; 146 mux = setup->data;
150 flags = CLK_SET_RATE_NO_REPARENT; 147 flags = CLK_SET_RATE_NO_REPARENT;
151 148
@@ -154,8 +151,9 @@ struct clk *ti_clk_register_mux(struct ti_clk *setup)
154 mask--; 151 mask--;
155 152
156 mask = (1 << fls(mask)) - 1; 153 mask = (1 << fls(mask)) - 1;
157 reg_setup->index = mux->module; 154 reg.index = mux->module;
158 reg_setup->offset = mux->reg; 155 reg.offset = mux->reg;
156 reg.ptr = NULL;
159 157
160 if (mux->flags & CLKF_INDEX_STARTS_AT_ONE) 158 if (mux->flags & CLKF_INDEX_STARTS_AT_ONE)
161 mux_flags |= CLK_MUX_INDEX_ONE; 159 mux_flags |= CLK_MUX_INDEX_ONE;
@@ -164,7 +162,7 @@ struct clk *ti_clk_register_mux(struct ti_clk *setup)
164 flags |= CLK_SET_RATE_PARENT; 162 flags |= CLK_SET_RATE_PARENT;
165 163
166 return _register_mux(NULL, setup->name, mux->parents, mux->num_parents, 164 return _register_mux(NULL, setup->name, mux->parents, mux->num_parents,
167 flags, (void __iomem *)reg, mux->bit_shift, mask, 165 flags, &reg, mux->bit_shift, mask,
168 mux_flags, NULL); 166 mux_flags, NULL);
169} 167}
170 168
@@ -177,7 +175,7 @@ struct clk *ti_clk_register_mux(struct ti_clk *setup)
177static void of_mux_clk_setup(struct device_node *node) 175static void of_mux_clk_setup(struct device_node *node)
178{ 176{
179 struct clk *clk; 177 struct clk *clk;
180 void __iomem *reg; 178 struct clk_omap_reg reg;
181 unsigned int num_parents; 179 unsigned int num_parents;
182 const char **parent_names; 180 const char **parent_names;
183 u8 clk_mux_flags = 0; 181 u8 clk_mux_flags = 0;
@@ -196,9 +194,7 @@ static void of_mux_clk_setup(struct device_node *node)
196 194
197 of_clk_parent_fill(node, parent_names, num_parents); 195 of_clk_parent_fill(node, parent_names, num_parents);
198 196
199 reg = ti_clk_get_reg_addr(node, 0); 197 if (ti_clk_get_reg_addr(node, 0, &reg))
200
201 if (IS_ERR(reg))
202 goto cleanup; 198 goto cleanup;
203 199
204 of_property_read_u32(node, "ti,bit-shift", &shift); 200 of_property_read_u32(node, "ti,bit-shift", &shift);
@@ -217,7 +213,7 @@ static void of_mux_clk_setup(struct device_node *node)
217 mask = (1 << fls(mask)) - 1; 213 mask = (1 << fls(mask)) - 1;
218 214
219 clk = _register_mux(NULL, node->name, parent_names, num_parents, 215 clk = _register_mux(NULL, node->name, parent_names, num_parents,
220 flags, reg, shift, mask, clk_mux_flags, NULL); 216 flags, &reg, shift, mask, clk_mux_flags, NULL);
221 217
222 if (!IS_ERR(clk)) 218 if (!IS_ERR(clk))
223 of_clk_add_provider(node, of_clk_src_simple_get, clk); 219 of_clk_add_provider(node, of_clk_src_simple_get, clk);
@@ -229,8 +225,7 @@ CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
229 225
230struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup) 226struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup)
231{ 227{
232 struct clk_mux *mux; 228 struct clk_omap_mux *mux;
233 struct clk_omap_reg *reg;
234 int num_parents; 229 int num_parents;
235 230
236 if (!setup) 231 if (!setup)
@@ -240,12 +235,10 @@ struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup)
240 if (!mux) 235 if (!mux)
241 return ERR_PTR(-ENOMEM); 236 return ERR_PTR(-ENOMEM);
242 237
243 reg = (struct clk_omap_reg *)&mux->reg;
244
245 mux->shift = setup->bit_shift; 238 mux->shift = setup->bit_shift;
246 239
247 reg->index = setup->module; 240 mux->reg.index = setup->module;
248 reg->offset = setup->reg; 241 mux->reg.offset = setup->reg;
249 242
250 if (setup->flags & CLKF_INDEX_STARTS_AT_ONE) 243 if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
251 mux->flags |= CLK_MUX_INDEX_ONE; 244 mux->flags |= CLK_MUX_INDEX_ONE;
@@ -260,7 +253,7 @@ struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup)
260 253
261static void __init of_ti_composite_mux_clk_setup(struct device_node *node) 254static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
262{ 255{
263 struct clk_mux *mux; 256 struct clk_omap_mux *mux;
264 unsigned int num_parents; 257 unsigned int num_parents;
265 u32 val; 258 u32 val;
266 259
@@ -268,9 +261,7 @@ static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
268 if (!mux) 261 if (!mux)
269 return; 262 return;
270 263
271 mux->reg = ti_clk_get_reg_addr(node, 0); 264 if (ti_clk_get_reg_addr(node, 0, &mux->reg))
272
273 if (IS_ERR(mux->reg))
274 goto cleanup; 265 goto cleanup;
275 266
276 if (!of_property_read_u32(node, "ti,bit-shift", &val)) 267 if (!of_property_read_u32(node, "ti,bit-shift", &val))
diff --git a/drivers/clk/zte/clk-zx296718.c b/drivers/clk/zte/clk-zx296718.c
index 2f7c668643fe..a10962988ba8 100644
--- a/drivers/clk/zte/clk-zx296718.c
+++ b/drivers/clk/zte/clk-zx296718.c
@@ -94,13 +94,36 @@
94 94
95static DEFINE_SPINLOCK(clk_lock); 95static DEFINE_SPINLOCK(clk_lock);
96 96
97static struct zx_pll_config pll_cpu_table[] = { 97static const struct zx_pll_config pll_cpu_table[] = {
98 PLL_RATE(1312000000, 0x00103621, 0x04aaaaaa), 98 PLL_RATE(1312000000, 0x00103621, 0x04aaaaaa),
99 PLL_RATE(1407000000, 0x00103a21, 0x04aaaaaa), 99 PLL_RATE(1407000000, 0x00103a21, 0x04aaaaaa),
100 PLL_RATE(1503000000, 0x00103e21, 0x04aaaaaa), 100 PLL_RATE(1503000000, 0x00103e21, 0x04aaaaaa),
101 PLL_RATE(1600000000, 0x00104221, 0x04aaaaaa), 101 PLL_RATE(1600000000, 0x00104221, 0x04aaaaaa),
102}; 102};
103 103
104static const struct zx_pll_config pll_vga_table[] = {
105 PLL_RATE(36000000, 0x00102464, 0x04000000), /* 800x600@56 */
106 PLL_RATE(40000000, 0x00102864, 0x04000000), /* 800x600@60 */
107 PLL_RATE(49500000, 0x00103164, 0x04800000), /* 800x600@75 */
108 PLL_RATE(50000000, 0x00103264, 0x04000000), /* 800x600@72 */
109 PLL_RATE(56250000, 0x00103864, 0x04400000), /* 800x600@85 */
110 PLL_RATE(65000000, 0x00104164, 0x04000000), /* 1024x768@60 */
111 PLL_RATE(74375000, 0x00104a64, 0x04600000), /* 1280x720@60 */
112 PLL_RATE(75000000, 0x00104b64, 0x04800000), /* 1024x768@70 */
113 PLL_RATE(78750000, 0x00104e64, 0x04c00000), /* 1024x768@75 */
114 PLL_RATE(85500000, 0x00105564, 0x04800000), /* 1360x768@60 */
115 PLL_RATE(106500000, 0x00106a64, 0x04800000), /* 1440x900@60 */
116 PLL_RATE(108000000, 0x00106c64, 0x04000000), /* 1280x1024@60 */
117 PLL_RATE(110000000, 0x00106e64, 0x04000000), /* 1024x768@85 */
118 PLL_RATE(135000000, 0x00105a44, 0x04000000), /* 1280x1024@75 */
119 PLL_RATE(136750000, 0x00104462, 0x04600000), /* 1440x900@75 */
120 PLL_RATE(148500000, 0x00104a62, 0x04400000), /* 1920x1080@60 */
121 PLL_RATE(157000000, 0x00104e62, 0x04800000), /* 1440x900@85 */
122 PLL_RATE(157500000, 0x00104e62, 0x04c00000), /* 1280x1024@85 */
123 PLL_RATE(162000000, 0x00105162, 0x04000000), /* 1600x1200@60 */
124 PLL_RATE(193250000, 0x00106062, 0x04a00000), /* 1920x1200@60 */
125};
126
104PNAME(osc) = { 127PNAME(osc) = {
105 "osc24m", 128 "osc24m",
106 "osc32k", 129 "osc32k",
@@ -369,6 +392,7 @@ PNAME(wdt_ares_p) = {
369 392
370static struct clk_zx_pll zx296718_pll_clk[] = { 393static struct clk_zx_pll zx296718_pll_clk[] = {
371 ZX296718_PLL("pll_cpu", "osc24m", PLL_CPU_REG, pll_cpu_table), 394 ZX296718_PLL("pll_cpu", "osc24m", PLL_CPU_REG, pll_cpu_table),
395 ZX296718_PLL("pll_vga", "osc24m", PLL_VGA_REG, pll_vga_table),
372}; 396};
373 397
374static struct zx_clk_fixed_factor top_ffactor_clk[] = { 398static struct zx_clk_fixed_factor top_ffactor_clk[] = {
@@ -409,7 +433,7 @@ static struct zx_clk_fixed_factor top_ffactor_clk[] = {
409 FFACTOR(0, "clk54m", "pll_mm1", 1, 24, 0), 433 FFACTOR(0, "clk54m", "pll_mm1", 1, 24, 0),
410 /* vga */ 434 /* vga */
411 FFACTOR(0, "pll_vga_1800m", "pll_vga", 1, 1, 0), 435 FFACTOR(0, "pll_vga_1800m", "pll_vga", 1, 1, 0),
412 FFACTOR(0, "clk_vga", "pll_vga", 1, 2, 0), 436 FFACTOR(0, "clk_vga", "pll_vga", 1, 1, CLK_SET_RATE_PARENT),
413 /* pll ddr */ 437 /* pll ddr */
414 FFACTOR(0, "clk466m", "pll_ddr", 1, 2, 0), 438 FFACTOR(0, "clk466m", "pll_ddr", 1, 2, 0),
415 439
@@ -458,8 +482,8 @@ static struct zx_clk_mux top_mux_clk[] = {
458 MUX(0, "sappu_a_mux", sappu_aclk_p, TOP_CLK_MUX5, 4, 2), 482 MUX(0, "sappu_a_mux", sappu_aclk_p, TOP_CLK_MUX5, 4, 2),
459 MUX(0, "sappu_w_mux", sappu_wclk_p, TOP_CLK_MUX5, 8, 3), 483 MUX(0, "sappu_w_mux", sappu_wclk_p, TOP_CLK_MUX5, 8, 3),
460 MUX(0, "vou_a_mux", vou_aclk_p, TOP_CLK_MUX7, 0, 3), 484 MUX(0, "vou_a_mux", vou_aclk_p, TOP_CLK_MUX7, 0, 3),
461 MUX(0, "vou_main_w_mux", vou_main_wclk_p, TOP_CLK_MUX7, 4, 3), 485 MUX_F(0, "vou_main_w_mux", vou_main_wclk_p, TOP_CLK_MUX7, 4, 3, CLK_SET_RATE_PARENT, 0),
462 MUX(0, "vou_aux_w_mux", vou_aux_wclk_p, TOP_CLK_MUX7, 8, 3), 486 MUX_F(0, "vou_aux_w_mux", vou_aux_wclk_p, TOP_CLK_MUX7, 8, 3, CLK_SET_RATE_PARENT, 0),
463 MUX(0, "vou_ppu_w_mux", vou_ppu_wclk_p, TOP_CLK_MUX7, 12, 3), 487 MUX(0, "vou_ppu_w_mux", vou_ppu_wclk_p, TOP_CLK_MUX7, 12, 3),
464 MUX(0, "vga_i2c_mux", vga_i2c_wclk_p, TOP_CLK_MUX7, 16, 1), 488 MUX(0, "vga_i2c_mux", vga_i2c_wclk_p, TOP_CLK_MUX7, 16, 1),
465 MUX(0, "viu_m0_a_mux", viu_m0_aclk_p, TOP_CLK_MUX6, 0, 3), 489 MUX(0, "viu_m0_a_mux", viu_m0_aclk_p, TOP_CLK_MUX6, 0, 3),
diff --git a/drivers/clk/zte/clk.c b/drivers/clk/zte/clk.c
index 878d879b23ff..b82031766ffa 100644
--- a/drivers/clk/zte/clk.c
+++ b/drivers/clk/zte/clk.c
@@ -52,7 +52,10 @@ static int hw_to_idx(struct clk_zx_pll *zx_pll)
52 52
53 /* For matching the value in lookup table */ 53 /* For matching the value in lookup table */
54 hw_cfg0 &= ~BIT(zx_pll->lock_bit); 54 hw_cfg0 &= ~BIT(zx_pll->lock_bit);
55 hw_cfg0 |= BIT(zx_pll->pd_bit); 55
56 /* Check availability of pd_bit */
57 if (zx_pll->pd_bit < 32)
58 hw_cfg0 |= BIT(zx_pll->pd_bit);
56 59
57 for (i = 0; i < zx_pll->count; i++) { 60 for (i = 0; i < zx_pll->count; i++) {
58 if (hw_cfg0 == config[i].cfg0 && hw_cfg1 == config[i].cfg1) 61 if (hw_cfg0 == config[i].cfg0 && hw_cfg1 == config[i].cfg1)
@@ -108,6 +111,10 @@ static int zx_pll_enable(struct clk_hw *hw)
108 struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw); 111 struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
109 u32 reg; 112 u32 reg;
110 113
114 /* If pd_bit is not available, simply return success. */
115 if (zx_pll->pd_bit > 31)
116 return 0;
117
111 reg = readl_relaxed(zx_pll->reg_base); 118 reg = readl_relaxed(zx_pll->reg_base);
112 writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base); 119 writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base);
113 120
@@ -120,6 +127,9 @@ static void zx_pll_disable(struct clk_hw *hw)
120 struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw); 127 struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
121 u32 reg; 128 u32 reg;
122 129
130 if (zx_pll->pd_bit > 31)
131 return;
132
123 reg = readl_relaxed(zx_pll->reg_base); 133 reg = readl_relaxed(zx_pll->reg_base);
124 writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base); 134 writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base);
125} 135}
diff --git a/drivers/clk/zte/clk.h b/drivers/clk/zte/clk.h
index 84a55a3e2bd4..4df0f121b56d 100644
--- a/drivers/clk/zte/clk.h
+++ b/drivers/clk/zte/clk.h
@@ -66,8 +66,12 @@ struct clk_zx_pll {
66 CLK_GET_RATE_NOCACHE), \ 66 CLK_GET_RATE_NOCACHE), \
67} 67}
68 68
69/*
70 * The pd_bit is not available on ZX296718, so let's pass something
71 * bigger than 31, e.g. 0xff, to indicate that.
72 */
69#define ZX296718_PLL(_name, _parent, _reg, _table) \ 73#define ZX296718_PLL(_name, _parent, _reg, _table) \
70ZX_PLL(_name, _parent, _reg, _table, 0, 30) 74ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)
71 75
72struct zx_clk_gate { 76struct zx_clk_gate {
73 struct clk_gate gate; 77 struct clk_gate gate;
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 692846c7941b..cce6cb5418f1 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -10,12 +10,17 @@
10#define CLKID_FCLK_DIV2 4 10#define CLKID_FCLK_DIV2 4
11#define CLKID_FCLK_DIV3 5 11#define CLKID_FCLK_DIV3 5
12#define CLKID_FCLK_DIV4 6 12#define CLKID_FCLK_DIV4 6
13#define CLKID_GP0_PLL 9
13#define CLKID_CLK81 12 14#define CLKID_CLK81 12
14#define CLKID_MPLL2 15 15#define CLKID_MPLL2 15
15#define CLKID_SPI 34 16#define CLKID_SPI 34
16#define CLKID_I2C 22 17#define CLKID_I2C 22
17#define CLKID_SAR_ADC 23 18#define CLKID_SAR_ADC 23
18#define CLKID_ETH 36 19#define CLKID_ETH 36
20#define CLKID_AIU_GLUE 38
21#define CLKID_I2S_OUT 40
22#define CLKID_MIXER_IFACE 44
23#define CLKID_AIU 47
19#define CLKID_USB0 50 24#define CLKID_USB0 50
20#define CLKID_USB1 51 25#define CLKID_USB1 51
21#define CLKID_USB 55 26#define CLKID_USB 55
@@ -24,11 +29,17 @@
24#define CLKID_USB0_DDR_BRIDGE 65 29#define CLKID_USB0_DDR_BRIDGE 65
25#define CLKID_SANA 69 30#define CLKID_SANA 69
26#define CLKID_GCLK_VENCI_INT0 77 31#define CLKID_GCLK_VENCI_INT0 77
32#define CLKID_AOCLK_GATE 80
27#define CLKID_AO_I2C 93 33#define CLKID_AO_I2C 93
28#define CLKID_SD_EMMC_A 94 34#define CLKID_SD_EMMC_A 94
29#define CLKID_SD_EMMC_B 95 35#define CLKID_SD_EMMC_B 95
30#define CLKID_SD_EMMC_C 96 36#define CLKID_SD_EMMC_C 96
31#define CLKID_SAR_ADC_CLK 97 37#define CLKID_SAR_ADC_CLK 97
32#define CLKID_SAR_ADC_SEL 98 38#define CLKID_SAR_ADC_SEL 98
39#define CLKID_MALI_0_SEL 100
40#define CLKID_MALI_0 102
41#define CLKID_MALI_1_SEL 103
42#define CLKID_MALI_1 105
43#define CLKID_MALI 106
33 44
34#endif /* __GXBB_CLKC_H */ 45#endif /* __GXBB_CLKC_H */
diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h
index 6b03c84f4278..b8ba665aab7b 100644
--- a/include/dt-bindings/clock/hi6220-clock.h
+++ b/include/dt-bindings/clock/hi6220-clock.h
@@ -124,7 +124,10 @@
124#define HI6220_CS_DAPB 57 124#define HI6220_CS_DAPB 57
125#define HI6220_CS_ATB_DIV 58 125#define HI6220_CS_ATB_DIV 58
126 126
127#define HI6220_SYS_NR_CLKS 59 127/* gate clock */
128#define HI6220_DAPB_CLK 59
129
130#define HI6220_SYS_NR_CLKS 60
128 131
129/* clk in Hi6220 media controller */ 132/* clk in Hi6220 media controller */
130/* gate clocks */ 133/* gate clocks */
diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
index e864aae0a256..f047eaf261f3 100644
--- a/include/dt-bindings/clock/r8a7795-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h
@@ -60,4 +60,11 @@
60#define R8A7795_CLK_R 45 60#define R8A7795_CLK_R 45
61#define R8A7795_CLK_OSC 46 61#define R8A7795_CLK_OSC 46
62 62
63/* r8a7795 ES2.0 CPG Core Clocks */
64#define R8A7795_CLK_S0D2 47
65#define R8A7795_CLK_S0D3 48
66#define R8A7795_CLK_S0D6 49
67#define R8A7795_CLK_S0D8 50
68#define R8A7795_CLK_S0D12 51
69
63#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */ 70#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h
index ee702c8e4c09..d2b26a4b43eb 100644
--- a/include/dt-bindings/clock/rk3328-cru.h
+++ b/include/dt-bindings/clock/rk3328-cru.h
@@ -97,6 +97,7 @@
97#define SCLK_MAC2IO_SRC 99 97#define SCLK_MAC2IO_SRC 99
98#define SCLK_MAC2IO 100 98#define SCLK_MAC2IO 100
99#define SCLK_MAC2PHY 101 99#define SCLK_MAC2PHY 101
100#define SCLK_MAC2IO_EXT 102
100 101
101/* dclk gates */ 102/* dclk gates */
102#define DCLK_LCDC 120 103#define DCLK_LCDC 120
diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
index 9c5dd9ba2f6c..aeb83e581a11 100644
--- a/include/dt-bindings/clock/rk3368-cru.h
+++ b/include/dt-bindings/clock/rk3368-cru.h
@@ -44,13 +44,12 @@
44#define SCLK_I2S_8CH 82 44#define SCLK_I2S_8CH 82
45#define SCLK_SPDIF_8CH 83 45#define SCLK_SPDIF_8CH 83
46#define SCLK_I2S_2CH 84 46#define SCLK_I2S_2CH 84
47#define SCLK_TIMER0 85 47#define SCLK_TIMER00 85
48#define SCLK_TIMER1 86 48#define SCLK_TIMER01 86
49#define SCLK_TIMER2 87 49#define SCLK_TIMER02 87
50#define SCLK_TIMER3 88 50#define SCLK_TIMER03 88
51#define SCLK_TIMER4 89 51#define SCLK_TIMER04 89
52#define SCLK_TIMER5 90 52#define SCLK_TIMER05 90
53#define SCLK_TIMER6 91
54#define SCLK_OTGPHY0 93 53#define SCLK_OTGPHY0 93
55#define SCLK_OTG_ADP 96 54#define SCLK_OTG_ADP 96
56#define SCLK_HSICPHY480M 97 55#define SCLK_HSICPHY480M 97
@@ -82,6 +81,12 @@
82#define SCLK_SFC 126 81#define SCLK_SFC 126
83#define SCLK_MAC 127 82#define SCLK_MAC 127
84#define SCLK_MACREF_OUT 128 83#define SCLK_MACREF_OUT 128
84#define SCLK_TIMER10 133
85#define SCLK_TIMER11 134
86#define SCLK_TIMER12 135
87#define SCLK_TIMER13 136
88#define SCLK_TIMER14 137
89#define SCLK_TIMER15 138
85 90
86#define DCLK_VOP 190 91#define DCLK_VOP 190
87#define MCLK_CRYPTO 191 92#define MCLK_CRYPTO 191
diff --git a/include/dt-bindings/clock/rk1108-cru.h b/include/dt-bindings/clock/rv1108-cru.h
index 9350a5527a36..ae26f8105914 100644
--- a/include/dt-bindings/clock/rk1108-cru.h
+++ b/include/dt-bindings/clock/rv1108-cru.h
@@ -13,8 +13,8 @@
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15 15
16#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H 16#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
17#define _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H 17#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
18 18
19/* pll id */ 19/* pll id */
20#define PLL_APLL 0 20#define PLL_APLL 0
@@ -266,4 +266,4 @@
266#define ARST_DSP_EDP_PERF 184 266#define ARST_DSP_EDP_PERF 184
267#define ARST_DSP_EPP_PERF 185 267#define ARST_DSP_EPP_PERF 185
268 268
269#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RK1108_H */ 269#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */
diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h
index efb7ba2bd515..c2afc41d6964 100644
--- a/include/dt-bindings/clock/sun8i-h3-ccu.h
+++ b/include/dt-bindings/clock/sun8i-h3-ccu.h
@@ -91,7 +91,7 @@
91#define CLK_BUS_UART1 63 91#define CLK_BUS_UART1 63
92#define CLK_BUS_UART2 64 92#define CLK_BUS_UART2 64
93#define CLK_BUS_UART3 65 93#define CLK_BUS_UART3 65
94#define CLK_BUS_SCR 66 94#define CLK_BUS_SCR0 66
95#define CLK_BUS_EPHY 67 95#define CLK_BUS_EPHY 67
96#define CLK_BUS_DBG 68 96#define CLK_BUS_DBG 68
97 97
@@ -142,4 +142,7 @@
142 142
143#define CLK_GPU 114 143#define CLK_GPU 114
144 144
145/* New clocks imported in H5 */
146#define CLK_BUS_SCR1 115
147
145#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */ 148#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */
diff --git a/include/dt-bindings/clock/sun8i-r-ccu.h b/include/dt-bindings/clock/sun8i-r-ccu.h
new file mode 100644
index 000000000000..779d20aa0d05
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-r-ccu.h
@@ -0,0 +1,59 @@
1/*
2 * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_
44#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_
45
46#define CLK_AR100 0
47
48#define CLK_APB0_PIO 3
49#define CLK_APB0_IR 4
50#define CLK_APB0_TIMER 5
51#define CLK_APB0_RSB 6
52#define CLK_APB0_UART 7
53/* 8 is reserved for CLK_APB0_W1 on A31 */
54#define CLK_APB0_I2C 9
55#define CLK_APB0_TWD 10
56
57#define CLK_IR 11
58
59#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
index 534c03f8ad72..ed5ca218c857 100644
--- a/include/dt-bindings/clock/tegra114-car.h
+++ b/include/dt-bindings/clock/tegra114-car.h
@@ -156,7 +156,7 @@
156/* 133 */ 156/* 133 */
157/* 134 */ 157/* 134 */
158/* 135 */ 158/* 135 */
159/* 136 */ 159#define TEGRA114_CLK_CEC 136
160/* 137 */ 160/* 137 */
161/* 138 */ 161/* 138 */
162/* 139 */ 162/* 139 */
diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h
index a2156090563f..9352c7e2ce0b 100644
--- a/include/dt-bindings/clock/tegra124-car-common.h
+++ b/include/dt-bindings/clock/tegra124-car-common.h
@@ -156,7 +156,7 @@
156/* 133 */ 156/* 133 */
157/* 134 */ 157/* 134 */
158/* 135 */ 158/* 135 */
159/* 136 */ 159#define TEGRA124_CLK_CEC 136
160/* 137 */ 160/* 137 */
161/* 138 */ 161/* 138 */
162/* 139 */ 162/* 139 */
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index 35288b20f2c9..46689cd3750b 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -39,7 +39,7 @@
39/* 20 (register bit affects vi and vi_sensor) */ 39/* 20 (register bit affects vi and vi_sensor) */
40/* 21 */ 40/* 21 */
41#define TEGRA210_CLK_USBD 22 41#define TEGRA210_CLK_USBD 22
42#define TEGRA210_CLK_ISP 23 42#define TEGRA210_CLK_ISPA 23
43/* 24 */ 43/* 24 */
44/* 25 */ 44/* 25 */
45#define TEGRA210_CLK_DISP2 26 45#define TEGRA210_CLK_DISP2 26
@@ -156,7 +156,7 @@
156/* 133 */ 156/* 133 */
157/* 134 */ 157/* 134 */
158/* 135 */ 158/* 135 */
159/* 136 */ 159#define TEGRA210_CLK_CEC 136
160/* 137 */ 160/* 137 */
161/* 138 */ 161/* 138 */
162/* 139 */ 162/* 139 */
@@ -173,7 +173,7 @@
173#define TEGRA210_CLK_ENTROPY 149 173#define TEGRA210_CLK_ENTROPY 149
174/* 150 */ 174/* 150 */
175/* 151 */ 175/* 151 */
176/* 152 */ 176#define TEGRA210_CLK_DP2 152
177/* 153 */ 177/* 153 */
178/* 154 */ 178/* 154 */
179/* 155 (bit affects dfll_ref and dfll_soc) */ 179/* 155 (bit affects dfll_ref and dfll_soc) */
@@ -210,7 +210,7 @@
210#define TEGRA210_CLK_DBGAPB 185 210#define TEGRA210_CLK_DBGAPB 185
211/* 186 */ 211/* 186 */
212#define TEGRA210_CLK_PLL_P_OUT_ADSP 187 212#define TEGRA210_CLK_PLL_P_OUT_ADSP 187
213/* 188 */ 213/* 188 ((bit affects pll_a_out_adsp and pll_a_out0_out_adsp)*/
214#define TEGRA210_CLK_PLL_G_REF 189 214#define TEGRA210_CLK_PLL_G_REF 189
215/* 190 */ 215/* 190 */
216/* 191 */ 216/* 191 */
@@ -222,7 +222,7 @@
222/* 196 */ 222/* 196 */
223#define TEGRA210_CLK_DMIC3 197 223#define TEGRA210_CLK_DMIC3 197
224#define TEGRA210_CLK_APE 198 224#define TEGRA210_CLK_APE 198
225/* 199 */ 225#define TEGRA210_CLK_ADSP 199
226/* 200 */ 226/* 200 */
227/* 201 */ 227/* 201 */
228#define TEGRA210_CLK_MAUD 202 228#define TEGRA210_CLK_MAUD 202
@@ -241,10 +241,10 @@
241/* 215 */ 241/* 215 */
242/* 216 */ 242/* 216 */
243/* 217 */ 243/* 217 */
244/* 218 */ 244#define TEGRA210_CLK_ADSP_NEON 218
245#define TEGRA210_CLK_NVENC 219 245#define TEGRA210_CLK_NVENC 219
246/* 220 */ 246#define TEGRA210_CLK_IQC2 220
247/* 221 */ 247#define TEGRA210_CLK_IQC1 221
248#define TEGRA210_CLK_SOR_SAFE 222 248#define TEGRA210_CLK_SOR_SAFE 222
249#define TEGRA210_CLK_PLL_P_OUT_CPU 223 249#define TEGRA210_CLK_PLL_P_OUT_CPU 223
250 250
@@ -349,9 +349,9 @@
349#define TEGRA210_CLK_PLL_RE_OUT1 319 349#define TEGRA210_CLK_PLL_RE_OUT1 319
350/* 320 */ 350/* 320 */
351/* 321 */ 351/* 321 */
352/* 322 */ 352#define TEGRA210_CLK_ISP 322
353/* 323 */ 353#define TEGRA210_CLK_PLL_A_OUT_ADSP 323
354/* 324 */ 354#define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324
355/* 325 */ 355/* 325 */
356/* 326 */ 356/* 326 */
357/* 327 */ 357/* 327 */
@@ -396,6 +396,15 @@
396#define TEGRA210_CLK_PLL_C_UD 364 396#define TEGRA210_CLK_PLL_C_UD 364
397#define TEGRA210_CLK_SCLK_MUX 365 397#define TEGRA210_CLK_SCLK_MUX 365
398 398
399#define TEGRA210_CLK_CLK_MAX 366 399#define TEGRA210_CLK_ACLK 370
400
401#define TEGRA210_CLK_DMIC1_SYNC_CLK 388
402#define TEGRA210_CLK_DMIC1_SYNC_CLK_MUX 389
403#define TEGRA210_CLK_DMIC2_SYNC_CLK 390
404#define TEGRA210_CLK_DMIC2_SYNC_CLK_MUX 391
405#define TEGRA210_CLK_DMIC3_SYNC_CLK 392
406#define TEGRA210_CLK_DMIC3_SYNC_CLK_MUX 393
407
408#define TEGRA210_CLK_CLK_MAX 394
400 409
401#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */ 410#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */
diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h
index 889e49ba0aa3..7213354b9652 100644
--- a/include/dt-bindings/clock/tegra30-car.h
+++ b/include/dt-bindings/clock/tegra30-car.h
@@ -156,7 +156,7 @@
156/* 133 */ 156/* 133 */
157/* 134 */ 157/* 134 */
158/* 135 */ 158/* 135 */
159/* 136 */ 159#define TEGRA30_CLK_CEC 136
160/* 137 */ 160/* 137 */
161/* 138 */ 161/* 138 */
162/* 139 */ 162/* 139 */
diff --git a/include/dt-bindings/reset/sun8i-h3-ccu.h b/include/dt-bindings/reset/sun8i-h3-ccu.h
index 6b7af80c26ec..484c2a22919d 100644
--- a/include/dt-bindings/reset/sun8i-h3-ccu.h
+++ b/include/dt-bindings/reset/sun8i-h3-ccu.h
@@ -98,6 +98,9 @@
98#define RST_BUS_UART1 50 98#define RST_BUS_UART1 50
99#define RST_BUS_UART2 51 99#define RST_BUS_UART2 51
100#define RST_BUS_UART3 52 100#define RST_BUS_UART3 52
101#define RST_BUS_SCR 53 101#define RST_BUS_SCR0 53
102
103/* New resets imported in H5 */
104#define RST_BUS_SCR1 54
102 105
103#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ 106#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */
diff --git a/include/dt-bindings/reset/sun8i-r-ccu.h b/include/dt-bindings/reset/sun8i-r-ccu.h
new file mode 100644
index 000000000000..4ba64f3d6fc9
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-r-ccu.h
@@ -0,0 +1,53 @@
1/*
2 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#ifndef _DT_BINDINGS_RST_SUN8I_R_CCU_H_
44#define _DT_BINDINGS_RST_SUN8I_R_CCU_H_
45
46#define RST_APB0_IR 0
47#define RST_APB0_TIMER 1
48#define RST_APB0_RSB 2
49#define RST_APB0_UART 3
50/* 4 is reserved for RST_APB0_W1 on A31 */
51#define RST_APB0_I2C 5
52
53#endif /* _DT_BINDINGS_RST_SUN8I_R_CCU_H_ */
diff --git a/include/dt-bindings/reset/tegra210-car.h b/include/dt-bindings/reset/tegra210-car.h
new file mode 100644
index 000000000000..296ec6e3f8c0
--- /dev/null
+++ b/include/dt-bindings/reset/tegra210-car.h
@@ -0,0 +1,13 @@
1/*
2 * This header provides Tegra210-specific constants for binding
3 * nvidia,tegra210-car.
4 */
5
6#ifndef _DT_BINDINGS_RESET_TEGRA210_CAR_H
7#define _DT_BINDINGS_RESET_TEGRA210_CAR_H
8
9#define TEGRA210_RESET(x) (7 * 32 + (x))
10#define TEGRA210_RST_DFLL_DVCO TEGRA210_RESET(0)
11#define TEGRA210_RST_ADSP TEGRA210_RESET(1)
12
13#endif /* _DT_BINDINGS_RESET_TEGRA210_CAR_H */
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 7007a5f48080..d23c9cf26993 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -125,5 +125,8 @@ extern void tegra210_xusb_pll_hw_control_enable(void);
125extern void tegra210_xusb_pll_hw_sequence_start(void); 125extern void tegra210_xusb_pll_hw_sequence_start(void);
126extern void tegra210_sata_pll_hw_control_enable(void); 126extern void tegra210_sata_pll_hw_control_enable(void);
127extern void tegra210_sata_pll_hw_sequence_start(void); 127extern void tegra210_sata_pll_hw_sequence_start(void);
128extern void tegra210_set_sata_pll_seq_sw(bool state);
129extern void tegra210_put_utmipll_in_iddq(void);
130extern void tegra210_put_utmipll_out_iddq(void);
128 131
129#endif /* __LINUX_CLK_TEGRA_H_ */ 132#endif /* __LINUX_CLK_TEGRA_H_ */
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 6110fe09ed18..d18da839b810 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -19,6 +19,18 @@
19#include <linux/clkdev.h> 19#include <linux/clkdev.h>
20 20
21/** 21/**
22 * struct clk_omap_reg - OMAP register declaration
23 * @offset: offset from the master IP module base address
24 * @index: index of the master IP module
25 */
26struct clk_omap_reg {
27 void __iomem *ptr;
28 u16 offset;
29 u8 index;
30 u8 flags;
31};
32
33/**
22 * struct dpll_data - DPLL registers and integration data 34 * struct dpll_data - DPLL registers and integration data
23 * @mult_div1_reg: register containing the DPLL M and N bitfields 35 * @mult_div1_reg: register containing the DPLL M and N bitfields
24 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg 36 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
@@ -67,12 +79,12 @@
67 * can be placed into read-only space. 79 * can be placed into read-only space.
68 */ 80 */
69struct dpll_data { 81struct dpll_data {
70 void __iomem *mult_div1_reg; 82 struct clk_omap_reg mult_div1_reg;
71 u32 mult_mask; 83 u32 mult_mask;
72 u32 div1_mask; 84 u32 div1_mask;
73 struct clk_hw *clk_bypass; 85 struct clk_hw *clk_bypass;
74 struct clk_hw *clk_ref; 86 struct clk_hw *clk_ref;
75 void __iomem *control_reg; 87 struct clk_omap_reg control_reg;
76 u32 enable_mask; 88 u32 enable_mask;
77 unsigned long last_rounded_rate; 89 unsigned long last_rounded_rate;
78 u16 last_rounded_m; 90 u16 last_rounded_m;
@@ -84,8 +96,8 @@ struct dpll_data {
84 u16 max_divider; 96 u16 max_divider;
85 unsigned long max_rate; 97 unsigned long max_rate;
86 u8 modes; 98 u8 modes;
87 void __iomem *autoidle_reg; 99 struct clk_omap_reg autoidle_reg;
88 void __iomem *idlest_reg; 100 struct clk_omap_reg idlest_reg;
89 u32 autoidle_mask; 101 u32 autoidle_mask;
90 u32 freqsel_mask; 102 u32 freqsel_mask;
91 u32 idlest_mask; 103 u32 idlest_mask;
@@ -113,10 +125,10 @@ struct clk_hw_omap;
113 */ 125 */
114struct clk_hw_omap_ops { 126struct clk_hw_omap_ops {
115 void (*find_idlest)(struct clk_hw_omap *oclk, 127 void (*find_idlest)(struct clk_hw_omap *oclk,
116 void __iomem **idlest_reg, 128 struct clk_omap_reg *idlest_reg,
117 u8 *idlest_bit, u8 *idlest_val); 129 u8 *idlest_bit, u8 *idlest_val);
118 void (*find_companion)(struct clk_hw_omap *oclk, 130 void (*find_companion)(struct clk_hw_omap *oclk,
119 void __iomem **other_reg, 131 struct clk_omap_reg *other_reg,
120 u8 *other_bit); 132 u8 *other_bit);
121 void (*allow_idle)(struct clk_hw_omap *oclk); 133 void (*allow_idle)(struct clk_hw_omap *oclk);
122 void (*deny_idle)(struct clk_hw_omap *oclk); 134 void (*deny_idle)(struct clk_hw_omap *oclk);
@@ -129,8 +141,6 @@ struct clk_hw_omap_ops {
129 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) 141 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
130 * @flags: see "struct clk.flags possibilities" above 142 * @flags: see "struct clk.flags possibilities" above
131 * @clksel_reg: for clksel clks, register va containing src/divisor select 143 * @clksel_reg: for clksel clks, register va containing src/divisor select
132 * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
133 * @clksel: for clksel clks, pointer to struct clksel for this clock
134 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock 144 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
135 * @clkdm_name: clockdomain name that this clock is contained in 145 * @clkdm_name: clockdomain name that this clock is contained in
136 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime 146 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
@@ -141,12 +151,10 @@ struct clk_hw_omap {
141 struct list_head node; 151 struct list_head node;
142 unsigned long fixed_rate; 152 unsigned long fixed_rate;
143 u8 fixed_div; 153 u8 fixed_div;
144 void __iomem *enable_reg; 154 struct clk_omap_reg enable_reg;
145 u8 enable_bit; 155 u8 enable_bit;
146 u8 flags; 156 u8 flags;
147 void __iomem *clksel_reg; 157 struct clk_omap_reg clksel_reg;
148 u32 clksel_mask;
149 const struct clksel *clksel;
150 struct dpll_data *dpll_data; 158 struct dpll_data *dpll_data;
151 const char *clkdm_name; 159 const char *clkdm_name;
152 struct clockdomain *clkdm; 160 struct clockdomain *clkdm;
@@ -172,7 +180,6 @@ struct clk_hw_omap {
172 * should be used. This is a temporary solution - a better approach 180 * should be used. This is a temporary solution - a better approach
173 * would be to associate clock type-specific data with the clock, 181 * would be to associate clock type-specific data with the clock,
174 * similar to the struct dpll_data approach. 182 * similar to the struct dpll_data approach.
175 * MEMMAP_ADDRESSING: Use memmap addressing to access clock registers.
176 */ 183 */
177#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ 184#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
178#define CLOCK_IDLE_CONTROL (1 << 1) 185#define CLOCK_IDLE_CONTROL (1 << 1)
@@ -180,7 +187,6 @@ struct clk_hw_omap {
180#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ 187#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
181#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ 188#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
182#define CLOCK_CLKOUTX2 (1 << 5) 189#define CLOCK_CLKOUTX2 (1 << 5)
183#define MEMMAP_ADDRESSING (1 << 6)
184 190
185/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ 191/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
186#define DPLL_LOW_POWER_STOP 0x1 192#define DPLL_LOW_POWER_STOP 0x1
@@ -202,21 +208,12 @@ enum {
202}; 208};
203 209
204/** 210/**
205 * struct clk_omap_reg - OMAP register declaration
206 * @offset: offset from the master IP module base address
207 * @index: index of the master IP module
208 */
209struct clk_omap_reg {
210 u16 offset;
211 u16 index;
212};
213
214/**
215 * struct ti_clk_ll_ops - low-level ops for clocks 211 * struct ti_clk_ll_ops - low-level ops for clocks
216 * @clk_readl: pointer to register read function 212 * @clk_readl: pointer to register read function
217 * @clk_writel: pointer to register write function 213 * @clk_writel: pointer to register write function
218 * @clkdm_clk_enable: pointer to clockdomain enable function 214 * @clkdm_clk_enable: pointer to clockdomain enable function
219 * @clkdm_clk_disable: pointer to clockdomain disable function 215 * @clkdm_clk_disable: pointer to clockdomain disable function
216 * @clkdm_lookup: pointer to clockdomain lookup function
220 * @cm_wait_module_ready: pointer to CM module wait ready function 217 * @cm_wait_module_ready: pointer to CM module wait ready function
221 * @cm_split_idlest_reg: pointer to CM module function to split idlest reg 218 * @cm_split_idlest_reg: pointer to CM module function to split idlest reg
222 * 219 *
@@ -227,20 +224,20 @@ struct clk_omap_reg {
227 * operations not provided directly by clock drivers. 224 * operations not provided directly by clock drivers.
228 */ 225 */
229struct ti_clk_ll_ops { 226struct ti_clk_ll_ops {
230 u32 (*clk_readl)(void __iomem *reg); 227 u32 (*clk_readl)(const struct clk_omap_reg *reg);
231 void (*clk_writel)(u32 val, void __iomem *reg); 228 void (*clk_writel)(u32 val, const struct clk_omap_reg *reg);
232 int (*clkdm_clk_enable)(struct clockdomain *clkdm, struct clk *clk); 229 int (*clkdm_clk_enable)(struct clockdomain *clkdm, struct clk *clk);
233 int (*clkdm_clk_disable)(struct clockdomain *clkdm, 230 int (*clkdm_clk_disable)(struct clockdomain *clkdm,
234 struct clk *clk); 231 struct clk *clk);
232 struct clockdomain * (*clkdm_lookup)(const char *name);
235 int (*cm_wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg, 233 int (*cm_wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg,
236 u8 idlest_shift); 234 u8 idlest_shift);
237 int (*cm_split_idlest_reg)(void __iomem *idlest_reg, s16 *prcm_inst, 235 int (*cm_split_idlest_reg)(struct clk_omap_reg *idlest_reg,
238 u8 *idlest_reg_id); 236 s16 *prcm_inst, u8 *idlest_reg_id);
239}; 237};
240 238
241#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw) 239#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
242 240
243void omap2_init_clk_clkdm(struct clk_hw *clk);
244int omap2_clk_disable_autoidle_all(void); 241int omap2_clk_disable_autoidle_all(void);
245int omap2_clk_enable_autoidle_all(void); 242int omap2_clk_enable_autoidle_all(void);
246int omap2_clk_allow_idle(struct clk *clk); 243int omap2_clk_allow_idle(struct clk *clk);
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-29 10:37:50 -0400