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-rw-r--r--drivers/edac/fsl_ddr_edac.c166
-rw-r--r--drivers/edac/fsl_ddr_edac.h43
-rw-r--r--drivers/edac/mpc85xx_edac.c4
3 files changed, 105 insertions, 108 deletions
diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c
index ca7636fbc799..26758337e23e 100644
--- a/drivers/edac/fsl_ddr_edac.c
+++ b/drivers/edac/fsl_ddr_edac.c
@@ -42,74 +42,74 @@ static u32 orig_ddr_err_sbe;
42 42
43#define to_mci(k) container_of(k, struct mem_ctl_info, dev) 43#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
44 44
45static ssize_t mpc85xx_mc_inject_data_hi_show(struct device *dev, 45static ssize_t fsl_mc_inject_data_hi_show(struct device *dev,
46 struct device_attribute *mattr, 46 struct device_attribute *mattr,
47 char *data) 47 char *data)
48{ 48{
49 struct mem_ctl_info *mci = to_mci(dev); 49 struct mem_ctl_info *mci = to_mci(dev);
50 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 50 struct fsl_mc_pdata *pdata = mci->pvt_info;
51 return sprintf(data, "0x%08x", 51 return sprintf(data, "0x%08x",
52 in_be32(pdata->mc_vbase + 52 in_be32(pdata->mc_vbase +
53 MPC85XX_MC_DATA_ERR_INJECT_HI)); 53 FSL_MC_DATA_ERR_INJECT_HI));
54} 54}
55 55
56static ssize_t mpc85xx_mc_inject_data_lo_show(struct device *dev, 56static ssize_t fsl_mc_inject_data_lo_show(struct device *dev,
57 struct device_attribute *mattr, 57 struct device_attribute *mattr,
58 char *data) 58 char *data)
59{ 59{
60 struct mem_ctl_info *mci = to_mci(dev); 60 struct mem_ctl_info *mci = to_mci(dev);
61 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 61 struct fsl_mc_pdata *pdata = mci->pvt_info;
62 return sprintf(data, "0x%08x", 62 return sprintf(data, "0x%08x",
63 in_be32(pdata->mc_vbase + 63 in_be32(pdata->mc_vbase +
64 MPC85XX_MC_DATA_ERR_INJECT_LO)); 64 FSL_MC_DATA_ERR_INJECT_LO));
65} 65}
66 66
67static ssize_t mpc85xx_mc_inject_ctrl_show(struct device *dev, 67static ssize_t fsl_mc_inject_ctrl_show(struct device *dev,
68 struct device_attribute *mattr, 68 struct device_attribute *mattr,
69 char *data) 69 char *data)
70{ 70{
71 struct mem_ctl_info *mci = to_mci(dev); 71 struct mem_ctl_info *mci = to_mci(dev);
72 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 72 struct fsl_mc_pdata *pdata = mci->pvt_info;
73 return sprintf(data, "0x%08x", 73 return sprintf(data, "0x%08x",
74 in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT)); 74 in_be32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT));
75} 75}
76 76
77static ssize_t mpc85xx_mc_inject_data_hi_store(struct device *dev, 77static ssize_t fsl_mc_inject_data_hi_store(struct device *dev,
78 struct device_attribute *mattr, 78 struct device_attribute *mattr,
79 const char *data, size_t count) 79 const char *data, size_t count)
80{ 80{
81 struct mem_ctl_info *mci = to_mci(dev); 81 struct mem_ctl_info *mci = to_mci(dev);
82 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 82 struct fsl_mc_pdata *pdata = mci->pvt_info;
83 if (isdigit(*data)) { 83 if (isdigit(*data)) {
84 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI, 84 out_be32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI,
85 simple_strtoul(data, NULL, 0)); 85 simple_strtoul(data, NULL, 0));
86 return count; 86 return count;
87 } 87 }
88 return 0; 88 return 0;
89} 89}
90 90
91static ssize_t mpc85xx_mc_inject_data_lo_store(struct device *dev, 91static ssize_t fsl_mc_inject_data_lo_store(struct device *dev,
92 struct device_attribute *mattr, 92 struct device_attribute *mattr,
93 const char *data, size_t count) 93 const char *data, size_t count)
94{ 94{
95 struct mem_ctl_info *mci = to_mci(dev); 95 struct mem_ctl_info *mci = to_mci(dev);
96 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 96 struct fsl_mc_pdata *pdata = mci->pvt_info;
97 if (isdigit(*data)) { 97 if (isdigit(*data)) {
98 out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO, 98 out_be32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO,
99 simple_strtoul(data, NULL, 0)); 99 simple_strtoul(data, NULL, 0));
100 return count; 100 return count;
101 } 101 }
102 return 0; 102 return 0;
103} 103}
104 104
105static ssize_t mpc85xx_mc_inject_ctrl_store(struct device *dev, 105static ssize_t fsl_mc_inject_ctrl_store(struct device *dev,
106 struct device_attribute *mattr, 106 struct device_attribute *mattr,
107 const char *data, size_t count) 107 const char *data, size_t count)
108{ 108{
109 struct mem_ctl_info *mci = to_mci(dev); 109 struct mem_ctl_info *mci = to_mci(dev);
110 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 110 struct fsl_mc_pdata *pdata = mci->pvt_info;
111 if (isdigit(*data)) { 111 if (isdigit(*data)) {
112 out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT, 112 out_be32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT,
113 simple_strtoul(data, NULL, 0)); 113 simple_strtoul(data, NULL, 0));
114 return count; 114 return count;
115 } 115 }
@@ -117,20 +117,20 @@ static ssize_t mpc85xx_mc_inject_ctrl_store(struct device *dev,
117} 117}
118 118
119DEVICE_ATTR(inject_data_hi, S_IRUGO | S_IWUSR, 119DEVICE_ATTR(inject_data_hi, S_IRUGO | S_IWUSR,
120 mpc85xx_mc_inject_data_hi_show, mpc85xx_mc_inject_data_hi_store); 120 fsl_mc_inject_data_hi_show, fsl_mc_inject_data_hi_store);
121DEVICE_ATTR(inject_data_lo, S_IRUGO | S_IWUSR, 121DEVICE_ATTR(inject_data_lo, S_IRUGO | S_IWUSR,
122 mpc85xx_mc_inject_data_lo_show, mpc85xx_mc_inject_data_lo_store); 122 fsl_mc_inject_data_lo_show, fsl_mc_inject_data_lo_store);
123DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR, 123DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR,
124 mpc85xx_mc_inject_ctrl_show, mpc85xx_mc_inject_ctrl_store); 124 fsl_mc_inject_ctrl_show, fsl_mc_inject_ctrl_store);
125 125
126static struct attribute *mpc85xx_dev_attrs[] = { 126static struct attribute *fsl_ddr_dev_attrs[] = {
127 &dev_attr_inject_data_hi.attr, 127 &dev_attr_inject_data_hi.attr,
128 &dev_attr_inject_data_lo.attr, 128 &dev_attr_inject_data_lo.attr,
129 &dev_attr_inject_ctrl.attr, 129 &dev_attr_inject_ctrl.attr,
130 NULL 130 NULL
131}; 131};
132 132
133ATTRIBUTE_GROUPS(mpc85xx_dev); 133ATTRIBUTE_GROUPS(fsl_ddr_dev);
134 134
135/**************************** MC Err device ***************************/ 135/**************************** MC Err device ***************************/
136 136
@@ -241,9 +241,9 @@ static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc,
241 241
242#define make64(high, low) (((u64)(high) << 32) | (low)) 242#define make64(high, low) (((u64)(high) << 32) | (low))
243 243
244static void mpc85xx_mc_check(struct mem_ctl_info *mci) 244static void fsl_mc_check(struct mem_ctl_info *mci)
245{ 245{
246 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 246 struct fsl_mc_pdata *pdata = mci->pvt_info;
247 struct csrow_info *csrow; 247 struct csrow_info *csrow;
248 u32 bus_width; 248 u32 bus_width;
249 u32 err_detect; 249 u32 err_detect;
@@ -256,23 +256,23 @@ static void mpc85xx_mc_check(struct mem_ctl_info *mci)
256 int bad_data_bit; 256 int bad_data_bit;
257 int bad_ecc_bit; 257 int bad_ecc_bit;
258 258
259 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); 259 err_detect = in_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
260 if (!err_detect) 260 if (!err_detect)
261 return; 261 return;
262 262
263 mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n", 263 fsl_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
264 err_detect); 264 err_detect);
265 265
266 /* no more processing if not ECC bit errors */ 266 /* no more processing if not ECC bit errors */
267 if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) { 267 if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
268 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); 268 out_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
269 return; 269 return;
270 } 270 }
271 271
272 syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC); 272 syndrome = in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_ECC);
273 273
274 /* Mask off appropriate bits of syndrome based on bus width */ 274 /* Mask off appropriate bits of syndrome based on bus width */
275 bus_width = (in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG) & 275 bus_width = (in_be32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) &
276 DSC_DBW_MASK) ? 32 : 64; 276 DSC_DBW_MASK) ? 32 : 64;
277 if (bus_width == 64) 277 if (bus_width == 64)
278 syndrome &= 0xff; 278 syndrome &= 0xff;
@@ -280,8 +280,8 @@ static void mpc85xx_mc_check(struct mem_ctl_info *mci)
280 syndrome &= 0xffff; 280 syndrome &= 0xffff;
281 281
282 err_addr = make64( 282 err_addr = make64(
283 in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_EXT_ADDRESS), 283 in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_EXT_ADDRESS),
284 in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS)); 284 in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_ADDRESS));
285 pfn = err_addr >> PAGE_SHIFT; 285 pfn = err_addr >> PAGE_SHIFT;
286 286
287 for (row_index = 0; row_index < mci->nr_csrows; row_index++) { 287 for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
@@ -290,8 +290,8 @@ static void mpc85xx_mc_check(struct mem_ctl_info *mci)
290 break; 290 break;
291 } 291 }
292 292
293 cap_high = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_HI); 293 cap_high = in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_HI);
294 cap_low = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_LO); 294 cap_low = in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_LO);
295 295
296 /* 296 /*
297 * Analyze single-bit errors on 64-bit wide buses 297 * Analyze single-bit errors on 64-bit wide buses
@@ -302,28 +302,28 @@ static void mpc85xx_mc_check(struct mem_ctl_info *mci)
302 &bad_data_bit, &bad_ecc_bit); 302 &bad_data_bit, &bad_ecc_bit);
303 303
304 if (bad_data_bit != -1) 304 if (bad_data_bit != -1)
305 mpc85xx_mc_printk(mci, KERN_ERR, 305 fsl_mc_printk(mci, KERN_ERR,
306 "Faulty Data bit: %d\n", bad_data_bit); 306 "Faulty Data bit: %d\n", bad_data_bit);
307 if (bad_ecc_bit != -1) 307 if (bad_ecc_bit != -1)
308 mpc85xx_mc_printk(mci, KERN_ERR, 308 fsl_mc_printk(mci, KERN_ERR,
309 "Faulty ECC bit: %d\n", bad_ecc_bit); 309 "Faulty ECC bit: %d\n", bad_ecc_bit);
310 310
311 mpc85xx_mc_printk(mci, KERN_ERR, 311 fsl_mc_printk(mci, KERN_ERR,
312 "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n", 312 "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
313 cap_high ^ (1 << (bad_data_bit - 32)), 313 cap_high ^ (1 << (bad_data_bit - 32)),
314 cap_low ^ (1 << bad_data_bit), 314 cap_low ^ (1 << bad_data_bit),
315 syndrome ^ (1 << bad_ecc_bit)); 315 syndrome ^ (1 << bad_ecc_bit));
316 } 316 }
317 317
318 mpc85xx_mc_printk(mci, KERN_ERR, 318 fsl_mc_printk(mci, KERN_ERR,
319 "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n", 319 "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
320 cap_high, cap_low, syndrome); 320 cap_high, cap_low, syndrome);
321 mpc85xx_mc_printk(mci, KERN_ERR, "Err addr: %#8.8llx\n", err_addr); 321 fsl_mc_printk(mci, KERN_ERR, "Err addr: %#8.8llx\n", err_addr);
322 mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn); 322 fsl_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
323 323
324 /* we are out of range */ 324 /* we are out of range */
325 if (row_index == mci->nr_csrows) 325 if (row_index == mci->nr_csrows)
326 mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n"); 326 fsl_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
327 327
328 if (err_detect & DDR_EDE_SBE) 328 if (err_detect & DDR_EDE_SBE)
329 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 329 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
@@ -337,27 +337,27 @@ static void mpc85xx_mc_check(struct mem_ctl_info *mci)
337 row_index, 0, -1, 337 row_index, 0, -1,
338 mci->ctl_name, ""); 338 mci->ctl_name, "");
339 339
340 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect); 340 out_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
341} 341}
342 342
343static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id) 343static irqreturn_t fsl_mc_isr(int irq, void *dev_id)
344{ 344{
345 struct mem_ctl_info *mci = dev_id; 345 struct mem_ctl_info *mci = dev_id;
346 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 346 struct fsl_mc_pdata *pdata = mci->pvt_info;
347 u32 err_detect; 347 u32 err_detect;
348 348
349 err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT); 349 err_detect = in_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
350 if (!err_detect) 350 if (!err_detect)
351 return IRQ_NONE; 351 return IRQ_NONE;
352 352
353 mpc85xx_mc_check(mci); 353 fsl_mc_check(mci);
354 354
355 return IRQ_HANDLED; 355 return IRQ_HANDLED;
356} 356}
357 357
358static void mpc85xx_init_csrows(struct mem_ctl_info *mci) 358static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
359{ 359{
360 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 360 struct fsl_mc_pdata *pdata = mci->pvt_info;
361 struct csrow_info *csrow; 361 struct csrow_info *csrow;
362 struct dimm_info *dimm; 362 struct dimm_info *dimm;
363 u32 sdram_ctl; 363 u32 sdram_ctl;
@@ -366,7 +366,7 @@ static void mpc85xx_init_csrows(struct mem_ctl_info *mci)
366 u32 cs_bnds; 366 u32 cs_bnds;
367 int index; 367 int index;
368 368
369 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); 369 sdram_ctl = in_be32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
370 370
371 sdtype = sdram_ctl & DSC_SDTYPE_MASK; 371 sdtype = sdram_ctl & DSC_SDTYPE_MASK;
372 if (sdram_ctl & DSC_RD_EN) { 372 if (sdram_ctl & DSC_RD_EN) {
@@ -408,8 +408,8 @@ static void mpc85xx_init_csrows(struct mem_ctl_info *mci)
408 csrow = mci->csrows[index]; 408 csrow = mci->csrows[index];
409 dimm = csrow->channels[0]->dimm; 409 dimm = csrow->channels[0]->dimm;
410 410
411 cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 + 411 cs_bnds = in_be32(pdata->mc_vbase + FSL_MC_CS_BNDS_0 +
412 (index * MPC85XX_MC_CS_BNDS_OFS)); 412 (index * FSL_MC_CS_BNDS_OFS));
413 413
414 start = (cs_bnds & 0xffff0000) >> 16; 414 start = (cs_bnds & 0xffff0000) >> 16;
415 end = (cs_bnds & 0x0000ffff); 415 end = (cs_bnds & 0x0000ffff);
@@ -434,16 +434,16 @@ static void mpc85xx_init_csrows(struct mem_ctl_info *mci)
434 } 434 }
435} 435}
436 436
437int mpc85xx_mc_err_probe(struct platform_device *op) 437int fsl_mc_err_probe(struct platform_device *op)
438{ 438{
439 struct mem_ctl_info *mci; 439 struct mem_ctl_info *mci;
440 struct edac_mc_layer layers[2]; 440 struct edac_mc_layer layers[2];
441 struct mpc85xx_mc_pdata *pdata; 441 struct fsl_mc_pdata *pdata;
442 struct resource r; 442 struct resource r;
443 u32 sdram_ctl; 443 u32 sdram_ctl;
444 int res; 444 int res;
445 445
446 if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL)) 446 if (!devres_open_group(&op->dev, fsl_mc_err_probe, GFP_KERNEL))
447 return -ENOMEM; 447 return -ENOMEM;
448 448
449 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 449 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
@@ -455,12 +455,12 @@ int mpc85xx_mc_err_probe(struct platform_device *op)
455 mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers, 455 mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers,
456 sizeof(*pdata)); 456 sizeof(*pdata));
457 if (!mci) { 457 if (!mci) {
458 devres_release_group(&op->dev, mpc85xx_mc_err_probe); 458 devres_release_group(&op->dev, fsl_mc_err_probe);
459 return -ENOMEM; 459 return -ENOMEM;
460 } 460 }
461 461
462 pdata = mci->pvt_info; 462 pdata = mci->pvt_info;
463 pdata->name = "mpc85xx_mc_err"; 463 pdata->name = "fsl_mc_err";
464 pdata->irq = NO_IRQ; 464 pdata->irq = NO_IRQ;
465 mci->pdev = &op->dev; 465 mci->pdev = &op->dev;
466 pdata->edac_idx = edac_mc_idx++; 466 pdata->edac_idx = edac_mc_idx++;
@@ -490,7 +490,7 @@ int mpc85xx_mc_err_probe(struct platform_device *op)
490 goto err; 490 goto err;
491 } 491 }
492 492
493 sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG); 493 sdram_ctl = in_be32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
494 if (!(sdram_ctl & DSC_ECC_EN)) { 494 if (!(sdram_ctl & DSC_ECC_EN)) {
495 /* no ECC */ 495 /* no ECC */
496 pr_warn("%s: No ECC DIMMs discovered\n", __func__); 496 pr_warn("%s: No ECC DIMMs discovered\n", __func__);
@@ -506,46 +506,46 @@ int mpc85xx_mc_err_probe(struct platform_device *op)
506 mci->mod_name = EDAC_MOD_STR; 506 mci->mod_name = EDAC_MOD_STR;
507 507
508 if (edac_op_state == EDAC_OPSTATE_POLL) 508 if (edac_op_state == EDAC_OPSTATE_POLL)
509 mci->edac_check = mpc85xx_mc_check; 509 mci->edac_check = fsl_mc_check;
510 510
511 mci->ctl_page_to_phys = NULL; 511 mci->ctl_page_to_phys = NULL;
512 512
513 mci->scrub_mode = SCRUB_SW_SRC; 513 mci->scrub_mode = SCRUB_SW_SRC;
514 514
515 mpc85xx_init_csrows(mci); 515 fsl_ddr_init_csrows(mci);
516 516
517 /* store the original error disable bits */ 517 /* store the original error disable bits */
518 orig_ddr_err_disable = 518 orig_ddr_err_disable =
519 in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE); 519 in_be32(pdata->mc_vbase + FSL_MC_ERR_DISABLE);
520 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0); 520 out_be32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, 0);
521 521
522 /* clear all error bits */ 522 /* clear all error bits */
523 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0); 523 out_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT, ~0);
524 524
525 if (edac_mc_add_mc_with_groups(mci, mpc85xx_dev_groups)) { 525 if (edac_mc_add_mc_with_groups(mci, fsl_ddr_dev_groups)) {
526 edac_dbg(3, "failed edac_mc_add_mc()\n"); 526 edac_dbg(3, "failed edac_mc_add_mc()\n");
527 goto err; 527 goto err;
528 } 528 }
529 529
530 if (edac_op_state == EDAC_OPSTATE_INT) { 530 if (edac_op_state == EDAC_OPSTATE_INT) {
531 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 531 out_be32(pdata->mc_vbase + FSL_MC_ERR_INT_EN,
532 DDR_EIE_MBEE | DDR_EIE_SBEE); 532 DDR_EIE_MBEE | DDR_EIE_SBEE);
533 533
534 /* store the original error management threshold */ 534 /* store the original error management threshold */
535 orig_ddr_err_sbe = in_be32(pdata->mc_vbase + 535 orig_ddr_err_sbe = in_be32(pdata->mc_vbase +
536 MPC85XX_MC_ERR_SBE) & 0xff0000; 536 FSL_MC_ERR_SBE) & 0xff0000;
537 537
538 /* set threshold to 1 error per interrupt */ 538 /* set threshold to 1 error per interrupt */
539 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000); 539 out_be32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000);
540 540
541 /* register interrupts */ 541 /* register interrupts */
542 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); 542 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
543 res = devm_request_irq(&op->dev, pdata->irq, 543 res = devm_request_irq(&op->dev, pdata->irq,
544 mpc85xx_mc_isr, 544 fsl_mc_isr,
545 IRQF_SHARED, 545 IRQF_SHARED,
546 "[EDAC] MC err", mci); 546 "[EDAC] MC err", mci);
547 if (res < 0) { 547 if (res < 0) {
548 pr_err("%s: Unable to request irq %d for MPC85xx DRAM ERR\n", 548 pr_err("%s: Unable to request irq %d for FSL DDR DRAM ERR\n",
549 __func__, pdata->irq); 549 __func__, pdata->irq);
550 irq_dispose_mapping(pdata->irq); 550 irq_dispose_mapping(pdata->irq);
551 res = -ENODEV; 551 res = -ENODEV;
@@ -556,7 +556,7 @@ int mpc85xx_mc_err_probe(struct platform_device *op)
556 pdata->irq); 556 pdata->irq);
557 } 557 }
558 558
559 devres_remove_group(&op->dev, mpc85xx_mc_err_probe); 559 devres_remove_group(&op->dev, fsl_mc_err_probe);
560 edac_dbg(3, "success\n"); 560 edac_dbg(3, "success\n");
561 pr_info(EDAC_MOD_STR " MC err registered\n"); 561 pr_info(EDAC_MOD_STR " MC err registered\n");
562 562
@@ -565,26 +565,26 @@ int mpc85xx_mc_err_probe(struct platform_device *op)
565err2: 565err2:
566 edac_mc_del_mc(&op->dev); 566 edac_mc_del_mc(&op->dev);
567err: 567err:
568 devres_release_group(&op->dev, mpc85xx_mc_err_probe); 568 devres_release_group(&op->dev, fsl_mc_err_probe);
569 edac_mc_free(mci); 569 edac_mc_free(mci);
570 return res; 570 return res;
571} 571}
572 572
573int mpc85xx_mc_err_remove(struct platform_device *op) 573int fsl_mc_err_remove(struct platform_device *op)
574{ 574{
575 struct mem_ctl_info *mci = dev_get_drvdata(&op->dev); 575 struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
576 struct mpc85xx_mc_pdata *pdata = mci->pvt_info; 576 struct fsl_mc_pdata *pdata = mci->pvt_info;
577 577
578 edac_dbg(0, "\n"); 578 edac_dbg(0, "\n");
579 579
580 if (edac_op_state == EDAC_OPSTATE_INT) { 580 if (edac_op_state == EDAC_OPSTATE_INT) {
581 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0); 581 out_be32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, 0);
582 irq_dispose_mapping(pdata->irq); 582 irq_dispose_mapping(pdata->irq);
583 } 583 }
584 584
585 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 585 out_be32(pdata->mc_vbase + FSL_MC_ERR_DISABLE,
586 orig_ddr_err_disable); 586 orig_ddr_err_disable);
587 out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe); 587 out_be32(pdata->mc_vbase + FSL_MC_ERR_SBE, orig_ddr_err_sbe);
588 588
589 edac_mc_del_mc(&op->dev); 589 edac_mc_del_mc(&op->dev);
590 edac_mc_free(mci); 590 edac_mc_free(mci);
diff --git a/drivers/edac/fsl_ddr_edac.h b/drivers/edac/fsl_ddr_edac.h
index 2f2c2b1890b9..1eccc62b5d93 100644
--- a/drivers/edac/fsl_ddr_edac.h
+++ b/drivers/edac/fsl_ddr_edac.h
@@ -16,7 +16,7 @@
16#ifndef _FSL_DDR_EDAC_H_ 16#ifndef _FSL_DDR_EDAC_H_
17#define _FSL_DDR_EDAC_H_ 17#define _FSL_DDR_EDAC_H_
18 18
19#define mpc85xx_mc_printk(mci, level, fmt, arg...) \ 19#define fsl_mc_printk(mci, level, fmt, arg...) \
20 edac_mc_chipset_printk(mci, level, "FSL_DDR", fmt, ##arg) 20 edac_mc_chipset_printk(mci, level, "FSL_DDR", fmt, ##arg)
21 21
22/* 22/*
@@ -24,26 +24,23 @@
24 */ 24 */
25 25
26/* DDR_SDRAM_CFG */ 26/* DDR_SDRAM_CFG */
27#define MPC85XX_MC_DDR_SDRAM_CFG 0x0110 27#define FSL_MC_DDR_SDRAM_CFG 0x0110
28#define MPC85XX_MC_CS_BNDS_0 0x0000 28#define FSL_MC_CS_BNDS_0 0x0000
29#define MPC85XX_MC_CS_BNDS_1 0x0008 29#define FSL_MC_CS_BNDS_OFS 0x0008
30#define MPC85XX_MC_CS_BNDS_2 0x0010
31#define MPC85XX_MC_CS_BNDS_3 0x0018
32#define MPC85XX_MC_CS_BNDS_OFS 0x0008
33 30
34#define MPC85XX_MC_DATA_ERR_INJECT_HI 0x0e00 31#define FSL_MC_DATA_ERR_INJECT_HI 0x0e00
35#define MPC85XX_MC_DATA_ERR_INJECT_LO 0x0e04 32#define FSL_MC_DATA_ERR_INJECT_LO 0x0e04
36#define MPC85XX_MC_ECC_ERR_INJECT 0x0e08 33#define FSL_MC_ECC_ERR_INJECT 0x0e08
37#define MPC85XX_MC_CAPTURE_DATA_HI 0x0e20 34#define FSL_MC_CAPTURE_DATA_HI 0x0e20
38#define MPC85XX_MC_CAPTURE_DATA_LO 0x0e24 35#define FSL_MC_CAPTURE_DATA_LO 0x0e24
39#define MPC85XX_MC_CAPTURE_ECC 0x0e28 36#define FSL_MC_CAPTURE_ECC 0x0e28
40#define MPC85XX_MC_ERR_DETECT 0x0e40 37#define FSL_MC_ERR_DETECT 0x0e40
41#define MPC85XX_MC_ERR_DISABLE 0x0e44 38#define FSL_MC_ERR_DISABLE 0x0e44
42#define MPC85XX_MC_ERR_INT_EN 0x0e48 39#define FSL_MC_ERR_INT_EN 0x0e48
43#define MPC85XX_MC_CAPTURE_ATRIBUTES 0x0e4c 40#define FSL_MC_CAPTURE_ATRIBUTES 0x0e4c
44#define MPC85XX_MC_CAPTURE_ADDRESS 0x0e50 41#define FSL_MC_CAPTURE_ADDRESS 0x0e50
45#define MPC85XX_MC_CAPTURE_EXT_ADDRESS 0x0e54 42#define FSL_MC_CAPTURE_EXT_ADDRESS 0x0e54
46#define MPC85XX_MC_ERR_SBE 0x0e58 43#define FSL_MC_ERR_SBE 0x0e58
47 44
48#define DSC_MEM_EN 0x80000000 45#define DSC_MEM_EN 0x80000000
49#define DSC_ECC_EN 0x20000000 46#define DSC_ECC_EN 0x20000000
@@ -75,12 +72,12 @@
75#define DDR_EDI_SBED 0x4 /* single-bit ECC error disable */ 72#define DDR_EDI_SBED 0x4 /* single-bit ECC error disable */
76#define DDR_EDI_MBED 0x8 /* multi-bit ECC error disable */ 73#define DDR_EDI_MBED 0x8 /* multi-bit ECC error disable */
77 74
78struct mpc85xx_mc_pdata { 75struct fsl_mc_pdata {
79 char *name; 76 char *name;
80 int edac_idx; 77 int edac_idx;
81 void __iomem *mc_vbase; 78 void __iomem *mc_vbase;
82 int irq; 79 int irq;
83}; 80};
84int mpc85xx_mc_err_probe(struct platform_device *op); 81int fsl_mc_err_probe(struct platform_device *op);
85int mpc85xx_mc_err_remove(struct platform_device *op); 82int fsl_mc_err_remove(struct platform_device *op);
86#endif 83#endif
diff --git a/drivers/edac/mpc85xx_edac.c b/drivers/edac/mpc85xx_edac.c
index c548a80f1823..0a4020923684 100644
--- a/drivers/edac/mpc85xx_edac.c
+++ b/drivers/edac/mpc85xx_edac.c
@@ -656,8 +656,8 @@ static const struct of_device_id mpc85xx_mc_err_of_match[] = {
656MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match); 656MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match);
657 657
658static struct platform_driver mpc85xx_mc_err_driver = { 658static struct platform_driver mpc85xx_mc_err_driver = {
659 .probe = mpc85xx_mc_err_probe, 659 .probe = fsl_mc_err_probe,
660 .remove = mpc85xx_mc_err_remove, 660 .remove = fsl_mc_err_remove,
661 .driver = { 661 .driver = {
662 .name = "mpc85xx_mc_err", 662 .name = "mpc85xx_mc_err",
663 .of_match_table = mpc85xx_mc_err_of_match, 663 .of_match_table = mpc85xx_mc_err_of_match,
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 02:43:47 -0500