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-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/clk-aspeed.c78
-rw-r--r--drivers/clk/clk-aspeed.h82
-rw-r--r--drivers/clk/clk-ast2600.c704
-rw-r--r--drivers/clk/clk-composite.c1
-rw-r--r--drivers/clk/clk-qoriq.c2
-rw-r--r--drivers/clk/clk-si5341.c1
-rw-r--r--drivers/clk/clk.c58
-rw-r--r--drivers/clk/st/clkgen-fsyn.c1
-rw-r--r--drivers/clk/st/clkgen-pll.c13
-rw-r--r--include/dt-bindings/clock/ast2600-clock.h113
-rw-r--r--include/linux/clk.h17
12 files changed, 964 insertions, 107 deletions
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0cad76021297..0138fb14e6f8 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o
30obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o 30obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
31obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o 31obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
32obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o 32obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o
33obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o
33obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o 34obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
34obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o 35obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
35obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o 36obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o
diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
index 42b4df6ba249..abf06fb6453e 100644
--- a/drivers/clk/clk-aspeed.c
+++ b/drivers/clk/clk-aspeed.c
@@ -1,19 +1,19 @@
1// SPDX-License-Identifier: GPL-2.0+ 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright IBM Corp
2 3
3#define pr_fmt(fmt) "clk-aspeed: " fmt 4#define pr_fmt(fmt) "clk-aspeed: " fmt
4 5
5#include <linux/clk-provider.h>
6#include <linux/mfd/syscon.h> 6#include <linux/mfd/syscon.h>
7#include <linux/of_address.h> 7#include <linux/of_address.h>
8#include <linux/of_device.h> 8#include <linux/of_device.h>
9#include <linux/platform_device.h> 9#include <linux/platform_device.h>
10#include <linux/regmap.h> 10#include <linux/regmap.h>
11#include <linux/reset-controller.h>
12#include <linux/slab.h> 11#include <linux/slab.h>
13#include <linux/spinlock.h>
14 12
15#include <dt-bindings/clock/aspeed-clock.h> 13#include <dt-bindings/clock/aspeed-clock.h>
16 14
15#include "clk-aspeed.h"
16
17#define ASPEED_NUM_CLKS 36 17#define ASPEED_NUM_CLKS 36
18 18
19#define ASPEED_RESET2_OFFSET 32 19#define ASPEED_RESET2_OFFSET 32
@@ -42,48 +42,6 @@ static struct clk_hw_onecell_data *aspeed_clk_data;
42 42
43static void __iomem *scu_base; 43static void __iomem *scu_base;
44 44
45/**
46 * struct aspeed_gate_data - Aspeed gated clocks
47 * @clock_idx: bit used to gate this clock in the clock register
48 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
49 * reset is required when enabling the clock
50 * @name: the clock name
51 * @parent_name: the name of the parent clock
52 * @flags: standard clock framework flags
53 */
54struct aspeed_gate_data {
55 u8 clock_idx;
56 s8 reset_idx;
57 const char *name;
58 const char *parent_name;
59 unsigned long flags;
60};
61
62/**
63 * struct aspeed_clk_gate - Aspeed specific clk_gate structure
64 * @hw: handle between common and hardware-specific interfaces
65 * @reg: register controlling gate
66 * @clock_idx: bit used to gate this clock in the clock register
67 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
68 * reset is required when enabling the clock
69 * @flags: hardware-specific flags
70 * @lock: register lock
71 *
72 * Some of the clocks in the Aspeed SoC must be put in reset before enabling.
73 * This modified version of clk_gate allows an optional reset bit to be
74 * specified.
75 */
76struct aspeed_clk_gate {
77 struct clk_hw hw;
78 struct regmap *map;
79 u8 clock_idx;
80 s8 reset_idx;
81 u8 flags;
82 spinlock_t *lock;
83};
84
85#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
86
87/* TODO: ask Aspeed about the actual parent data */ 45/* TODO: ask Aspeed about the actual parent data */
88static const struct aspeed_gate_data aspeed_gates[] = { 46static const struct aspeed_gate_data aspeed_gates[] = {
89 /* clk rst name parent flags */ 47 /* clk rst name parent flags */
@@ -208,13 +166,6 @@ static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val)
208 mult, div); 166 mult, div);
209} 167}
210 168
211struct aspeed_clk_soc_data {
212 const struct clk_div_table *div_table;
213 const struct clk_div_table *eclk_div_table;
214 const struct clk_div_table *mac_div_table;
215 struct clk_hw *(*calc_pll)(const char *name, u32 val);
216};
217
218static const struct aspeed_clk_soc_data ast2500_data = { 169static const struct aspeed_clk_soc_data ast2500_data = {
219 .div_table = ast2500_div_table, 170 .div_table = ast2500_div_table,
220 .eclk_div_table = ast2500_eclk_div_table, 171 .eclk_div_table = ast2500_eclk_div_table,
@@ -315,18 +266,6 @@ static const struct clk_ops aspeed_clk_gate_ops = {
315 .is_enabled = aspeed_clk_is_enabled, 266 .is_enabled = aspeed_clk_is_enabled,
316}; 267};
317 268
318/**
319 * struct aspeed_reset - Aspeed reset controller
320 * @map: regmap to access the containing system controller
321 * @rcdev: reset controller device
322 */
323struct aspeed_reset {
324 struct regmap *map;
325 struct reset_controller_dev rcdev;
326};
327
328#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
329
330static const u8 aspeed_resets[] = { 269static const u8 aspeed_resets[] = {
331 /* SCU04 resets */ 270 /* SCU04 resets */
332 [ASPEED_RESET_XDMA] = 25, 271 [ASPEED_RESET_XDMA] = 25,
@@ -500,9 +439,14 @@ static int aspeed_clk_probe(struct platform_device *pdev)
500 return PTR_ERR(hw); 439 return PTR_ERR(hw);
501 aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw; 440 aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw;
502 441
503 /* SD/SDIO clock divider (TODO: There's a gate too) */ 442 /* SD/SDIO clock divider and gate */
504 hw = clk_hw_register_divider_table(dev, "sdio", "hpll", 0, 443 hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
505 scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, 444 scu_base + ASPEED_CLK_SELECTION, 15, 0,
445 &aspeed_clk_lock);
446 if (IS_ERR(hw))
447 return PTR_ERR(hw);
448 hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
449 0, scu_base + ASPEED_CLK_SELECTION, 12, 3, 0,
506 soc_data->div_table, 450 soc_data->div_table,
507 &aspeed_clk_lock); 451 &aspeed_clk_lock);
508 if (IS_ERR(hw)) 452 if (IS_ERR(hw))
diff --git a/drivers/clk/clk-aspeed.h b/drivers/clk/clk-aspeed.h
new file mode 100644
index 000000000000..5296b15b1c88
--- /dev/null
+++ b/drivers/clk/clk-aspeed.h
@@ -0,0 +1,82 @@
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Structures used by ASPEED clock drivers
4 *
5 * Copyright 2019 IBM Corp.
6 */
7
8#include <linux/clk-provider.h>
9#include <linux/kernel.h>
10#include <linux/reset-controller.h>
11#include <linux/spinlock.h>
12
13struct clk_div_table;
14struct regmap;
15
16/**
17 * struct aspeed_gate_data - Aspeed gated clocks
18 * @clock_idx: bit used to gate this clock in the clock register
19 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
20 * reset is required when enabling the clock
21 * @name: the clock name
22 * @parent_name: the name of the parent clock
23 * @flags: standard clock framework flags
24 */
25struct aspeed_gate_data {
26 u8 clock_idx;
27 s8 reset_idx;
28 const char *name;
29 const char *parent_name;
30 unsigned long flags;
31};
32
33/**
34 * struct aspeed_clk_gate - Aspeed specific clk_gate structure
35 * @hw: handle between common and hardware-specific interfaces
36 * @reg: register controlling gate
37 * @clock_idx: bit used to gate this clock in the clock register
38 * @reset_idx: bit used to reset this IP in the reset register. -1 if no
39 * reset is required when enabling the clock
40 * @flags: hardware-specific flags
41 * @lock: register lock
42 *
43 * Some of the clocks in the Aspeed SoC must be put in reset before enabling.
44 * This modified version of clk_gate allows an optional reset bit to be
45 * specified.
46 */
47struct aspeed_clk_gate {
48 struct clk_hw hw;
49 struct regmap *map;
50 u8 clock_idx;
51 s8 reset_idx;
52 u8 flags;
53 spinlock_t *lock;
54};
55
56#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
57
58/**
59 * struct aspeed_reset - Aspeed reset controller
60 * @map: regmap to access the containing system controller
61 * @rcdev: reset controller device
62 */
63struct aspeed_reset {
64 struct regmap *map;
65 struct reset_controller_dev rcdev;
66};
67
68#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
69
70/**
71 * struct aspeed_clk_soc_data - Aspeed SoC specific divisor information
72 * @div_table: Common divider lookup table
73 * @eclk_div_table: Divider lookup table for ECLK
74 * @mac_div_table: Divider lookup table for MAC (Ethernet) clocks
75 * @calc_pll: Callback to maculate common PLL settings
76 */
77struct aspeed_clk_soc_data {
78 const struct clk_div_table *div_table;
79 const struct clk_div_table *eclk_div_table;
80 const struct clk_div_table *mac_div_table;
81 struct clk_hw *(*calc_pll)(const char *name, u32 val);
82};
diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c
new file mode 100644
index 000000000000..1c1bb39bb04e
--- /dev/null
+++ b/drivers/clk/clk-ast2600.c
@@ -0,0 +1,704 @@
1// SPDX-License-Identifier: GPL-2.0-or-later
2// Copyright IBM Corp
3// Copyright ASPEED Technology
4
5#define pr_fmt(fmt) "clk-ast2600: " fmt
6
7#include <linux/mfd/syscon.h>
8#include <linux/of_address.h>
9#include <linux/of_device.h>
10#include <linux/platform_device.h>
11#include <linux/regmap.h>
12#include <linux/slab.h>
13
14#include <dt-bindings/clock/ast2600-clock.h>
15
16#include "clk-aspeed.h"
17
18#define ASPEED_G6_NUM_CLKS 67
19
20#define ASPEED_G6_SILICON_REV 0x004
21
22#define ASPEED_G6_RESET_CTRL 0x040
23#define ASPEED_G6_RESET_CTRL2 0x050
24
25#define ASPEED_G6_CLK_STOP_CTRL 0x080
26#define ASPEED_G6_CLK_STOP_CTRL2 0x090
27
28#define ASPEED_G6_MISC_CTRL 0x0C0
29#define UART_DIV13_EN BIT(12)
30
31#define ASPEED_G6_CLK_SELECTION1 0x300
32#define ASPEED_G6_CLK_SELECTION2 0x304
33#define ASPEED_G6_CLK_SELECTION4 0x310
34
35#define ASPEED_HPLL_PARAM 0x200
36#define ASPEED_APLL_PARAM 0x210
37#define ASPEED_MPLL_PARAM 0x220
38#define ASPEED_EPLL_PARAM 0x240
39#define ASPEED_DPLL_PARAM 0x260
40
41#define ASPEED_G6_STRAP1 0x500
42
43/* Globally visible clocks */
44static DEFINE_SPINLOCK(aspeed_g6_clk_lock);
45
46/* Keeps track of all clocks */
47static struct clk_hw_onecell_data *aspeed_g6_clk_data;
48
49static void __iomem *scu_g6_base;
50
51/*
52 * Clocks marked with CLK_IS_CRITICAL:
53 *
54 * ref0 and ref1 are essential for the SoC to operate
55 * mpll is required if SDRAM is used
56 */
57static const struct aspeed_gate_data aspeed_g6_gates[] = {
58 /* clk rst name parent flags */
59 [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
60 [ASPEED_CLK_GATE_ECLK] = { 1, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */
61 [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
62 /* vclk parent - dclk/d1clk/hclk/mclk */
63 [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
64 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
65 /* From dpll */
66 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
67 [ASPEED_CLK_GATE_REF0CLK] = { 6, -1, "ref0clk-gate", "clkin", CLK_IS_CRITICAL },
68 [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
69 /* Reserved 8 */
70 [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
71 /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */
72 [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", "d1clk", 0 }, /* GFX CRT */
73 /* Reserved 11/12 */
74 [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
75 [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
76 [ASPEED_CLK_GATE_UART5CLK] = { 15, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
77 /* Reserved 16/19 */
78 [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac12", 0 }, /* MAC1 */
79 [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac12", 0 }, /* MAC2 */
80 /* Reserved 22/23 */
81 [ASPEED_CLK_GATE_RSACLK] = { 24, 4, "rsaclk-gate", NULL, 0 }, /* HAC */
82 [ASPEED_CLK_GATE_RVASCLK] = { 25, 9, "rvasclk-gate", NULL, 0 }, /* RVAS */
83 /* Reserved 26 */
84 [ASPEED_CLK_GATE_EMMCCLK] = { 27, 16, "emmcclk-gate", NULL, 0 }, /* For card clk */
85 /* Reserved 28/29/30 */
86 [ASPEED_CLK_GATE_LCLK] = { 32, 32, "lclk-gate", NULL, 0 }, /* LPC */
87 [ASPEED_CLK_GATE_ESPICLK] = { 33, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
88 [ASPEED_CLK_GATE_REF1CLK] = { 34, -1, "ref1clk-gate", "clkin", CLK_IS_CRITICAL },
89 /* Reserved 35 */
90 [ASPEED_CLK_GATE_SDCLK] = { 36, 56, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
91 [ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
92 /* Reserved 38 RSA: no longer used */
93 /* Reserved 39 */
94 [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", NULL, 0 }, /* I3C0 */
95 [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", NULL, 0 }, /* I3C1 */
96 [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", NULL, 0 }, /* I3C2 */
97 [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", NULL, 0 }, /* I3C3 */
98 [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", NULL, 0 }, /* I3C4 */
99 [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", NULL, 0 }, /* I3C5 */
100 [ASPEED_CLK_GATE_I3C6CLK] = { 46, 46, "i3c6clk-gate", NULL, 0 }, /* I3C6 */
101 [ASPEED_CLK_GATE_I3C7CLK] = { 47, 47, "i3c7clk-gate", NULL, 0 }, /* I3C7 */
102 [ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
103 [ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
104 [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
105 [ASPEED_CLK_GATE_UART4CLK] = { 51, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
106 [ASPEED_CLK_GATE_MAC3CLK] = { 52, 52, "mac3clk-gate", "mac34", 0 }, /* MAC3 */
107 [ASPEED_CLK_GATE_MAC4CLK] = { 53, 53, "mac4clk-gate", "mac34", 0 }, /* MAC4 */
108 [ASPEED_CLK_GATE_UART6CLK] = { 54, -1, "uart6clk-gate", "uartx", 0 }, /* UART6 */
109 [ASPEED_CLK_GATE_UART7CLK] = { 55, -1, "uart7clk-gate", "uartx", 0 }, /* UART7 */
110 [ASPEED_CLK_GATE_UART8CLK] = { 56, -1, "uart8clk-gate", "uartx", 0 }, /* UART8 */
111 [ASPEED_CLK_GATE_UART9CLK] = { 57, -1, "uart9clk-gate", "uartx", 0 }, /* UART9 */
112 [ASPEED_CLK_GATE_UART10CLK] = { 58, -1, "uart10clk-gate", "uartx", 0 }, /* UART10 */
113 [ASPEED_CLK_GATE_UART11CLK] = { 59, -1, "uart11clk-gate", "uartx", 0 }, /* UART11 */
114 [ASPEED_CLK_GATE_UART12CLK] = { 60, -1, "uart12clk-gate", "uartx", 0 }, /* UART12 */
115 [ASPEED_CLK_GATE_UART13CLK] = { 61, -1, "uart13clk-gate", "uartx", 0 }, /* UART13 */
116 [ASPEED_CLK_GATE_FSICLK] = { 62, 59, "fsiclk-gate", NULL, 0 }, /* FSI */
117};
118
119static const char * const eclk_parent_names[] = { "mpll", "hpll", "dpll" };
120
121static const struct clk_div_table ast2600_eclk_div_table[] = {
122 { 0x0, 2 },
123 { 0x1, 2 },
124 { 0x2, 3 },
125 { 0x3, 4 },
126 { 0x4, 5 },
127 { 0x5, 6 },
128 { 0x6, 7 },
129 { 0x7, 8 },
130 { 0 }
131};
132
133static const struct clk_div_table ast2600_mac_div_table[] = {
134 { 0x0, 4 },
135 { 0x1, 4 },
136 { 0x2, 6 },
137 { 0x3, 8 },
138 { 0x4, 10 },
139 { 0x5, 12 },
140 { 0x6, 14 },
141 { 0x7, 16 },
142 { 0 }
143};
144
145static const struct clk_div_table ast2600_div_table[] = {
146 { 0x0, 4 },
147 { 0x1, 8 },
148 { 0x2, 12 },
149 { 0x3, 16 },
150 { 0x4, 20 },
151 { 0x5, 24 },
152 { 0x6, 28 },
153 { 0x7, 32 },
154 { 0 }
155};
156
157/* For hpll/dpll/epll/mpll */
158static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
159{
160 unsigned int mult, div;
161
162 if (val & BIT(24)) {
163 /* Pass through mode */
164 mult = div = 1;
165 } else {
166 /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
167 u32 m = val & 0x1fff;
168 u32 n = (val >> 13) & 0x3f;
169 u32 p = (val >> 19) & 0xf;
170 mult = (m + 1) / (n + 1);
171 div = (p + 1);
172 }
173 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
174 mult, div);
175};
176
177static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)
178{
179 unsigned int mult, div;
180
181 if (val & BIT(20)) {
182 /* Pass through mode */
183 mult = div = 1;
184 } else {
185 /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
186 u32 m = (val >> 5) & 0x3f;
187 u32 od = (val >> 4) & 0x1;
188 u32 n = val & 0xf;
189
190 mult = (2 - od) * (m + 2);
191 div = n + 1;
192 }
193 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
194 mult, div);
195};
196
197static u32 get_bit(u8 idx)
198{
199 return BIT(idx % 32);
200}
201
202static u32 get_reset_reg(struct aspeed_clk_gate *gate)
203{
204 if (gate->reset_idx < 32)
205 return ASPEED_G6_RESET_CTRL;
206
207 return ASPEED_G6_RESET_CTRL2;
208}
209
210static u32 get_clock_reg(struct aspeed_clk_gate *gate)
211{
212 if (gate->clock_idx < 32)
213 return ASPEED_G6_CLK_STOP_CTRL;
214
215 return ASPEED_G6_CLK_STOP_CTRL2;
216}
217
218static int aspeed_g6_clk_is_enabled(struct clk_hw *hw)
219{
220 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
221 u32 clk = get_bit(gate->clock_idx);
222 u32 rst = get_bit(gate->reset_idx);
223 u32 reg;
224 u32 enval;
225
226 /*
227 * If the IP is in reset, treat the clock as not enabled,
228 * this happens with some clocks such as the USB one when
229 * coming from cold reset. Without this, aspeed_clk_enable()
230 * will fail to lift the reset.
231 */
232 if (gate->reset_idx >= 0) {
233 regmap_read(gate->map, get_reset_reg(gate), &reg);
234
235 if (reg & rst)
236 return 0;
237 }
238
239 regmap_read(gate->map, get_clock_reg(gate), &reg);
240
241 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
242
243 return ((reg & clk) == enval) ? 1 : 0;
244}
245
246static int aspeed_g6_clk_enable(struct clk_hw *hw)
247{
248 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
249 unsigned long flags;
250 u32 clk = get_bit(gate->clock_idx);
251 u32 rst = get_bit(gate->reset_idx);
252
253 spin_lock_irqsave(gate->lock, flags);
254
255 if (aspeed_g6_clk_is_enabled(hw)) {
256 spin_unlock_irqrestore(gate->lock, flags);
257 return 0;
258 }
259
260 if (gate->reset_idx >= 0) {
261 /* Put IP in reset */
262 regmap_write(gate->map, get_reset_reg(gate), rst);
263 /* Delay 100us */
264 udelay(100);
265 }
266
267 /* Enable clock */
268 if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
269 regmap_write(gate->map, get_clock_reg(gate), clk);
270 } else {
271 /* Use set to clear register */
272 regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk);
273 }
274
275 if (gate->reset_idx >= 0) {
276 /* A delay of 10ms is specified by the ASPEED docs */
277 mdelay(10);
278 /* Take IP out of reset */
279 regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst);
280 }
281
282 spin_unlock_irqrestore(gate->lock, flags);
283
284 return 0;
285}
286
287static void aspeed_g6_clk_disable(struct clk_hw *hw)
288{
289 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
290 unsigned long flags;
291 u32 clk = get_bit(gate->clock_idx);
292
293 spin_lock_irqsave(gate->lock, flags);
294
295 if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
296 regmap_write(gate->map, get_clock_reg(gate), clk);
297 } else {
298 /* Use set to clear register */
299 regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk);
300 }
301
302 spin_unlock_irqrestore(gate->lock, flags);
303}
304
305static const struct clk_ops aspeed_g6_clk_gate_ops = {
306 .enable = aspeed_g6_clk_enable,
307 .disable = aspeed_g6_clk_disable,
308 .is_enabled = aspeed_g6_clk_is_enabled,
309};
310
311static int aspeed_g6_reset_deassert(struct reset_controller_dev *rcdev,
312 unsigned long id)
313{
314 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
315 u32 rst = get_bit(id);
316 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
317
318 /* Use set to clear register */
319 return regmap_write(ar->map, reg + 0x04, rst);
320}
321
322static int aspeed_g6_reset_assert(struct reset_controller_dev *rcdev,
323 unsigned long id)
324{
325 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
326 u32 rst = get_bit(id);
327 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
328
329 return regmap_write(ar->map, reg, rst);
330}
331
332static int aspeed_g6_reset_status(struct reset_controller_dev *rcdev,
333 unsigned long id)
334{
335 struct aspeed_reset *ar = to_aspeed_reset(rcdev);
336 int ret;
337 u32 val;
338 u32 rst = get_bit(id);
339 u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
340
341 ret = regmap_read(ar->map, reg, &val);
342 if (ret)
343 return ret;
344
345 return !!(val & rst);
346}
347
348static const struct reset_control_ops aspeed_g6_reset_ops = {
349 .assert = aspeed_g6_reset_assert,
350 .deassert = aspeed_g6_reset_deassert,
351 .status = aspeed_g6_reset_status,
352};
353
354static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev,
355 const char *name, const char *parent_name, unsigned long flags,
356 struct regmap *map, u8 clock_idx, u8 reset_idx,
357 u8 clk_gate_flags, spinlock_t *lock)
358{
359 struct aspeed_clk_gate *gate;
360 struct clk_init_data init;
361 struct clk_hw *hw;
362 int ret;
363
364 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
365 if (!gate)
366 return ERR_PTR(-ENOMEM);
367
368 init.name = name;
369 init.ops = &aspeed_g6_clk_gate_ops;
370 init.flags = flags;
371 init.parent_names = parent_name ? &parent_name : NULL;
372 init.num_parents = parent_name ? 1 : 0;
373
374 gate->map = map;
375 gate->clock_idx = clock_idx;
376 gate->reset_idx = reset_idx;
377 gate->flags = clk_gate_flags;
378 gate->lock = lock;
379 gate->hw.init = &init;
380
381 hw = &gate->hw;
382 ret = clk_hw_register(dev, hw);
383 if (ret) {
384 kfree(gate);
385 hw = ERR_PTR(ret);
386 }
387
388 return hw;
389}
390
391static const char * const vclk_parent_names[] = {
392 "dpll",
393 "d1pll",
394 "hclk",
395 "mclk",
396};
397
398static const char * const d1clk_parent_names[] = {
399 "dpll",
400 "epll",
401 "usb-phy-40m",
402 "gpioc6_clkin",
403 "dp_phy_pll",
404};
405
406static int aspeed_g6_clk_probe(struct platform_device *pdev)
407{
408 struct device *dev = &pdev->dev;
409 struct aspeed_reset *ar;
410 struct regmap *map;
411 struct clk_hw *hw;
412 u32 val, rate;
413 int i, ret;
414
415 map = syscon_node_to_regmap(dev->of_node);
416 if (IS_ERR(map)) {
417 dev_err(dev, "no syscon regmap\n");
418 return PTR_ERR(map);
419 }
420
421 ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
422 if (!ar)
423 return -ENOMEM;
424
425 ar->map = map;
426
427 ar->rcdev.owner = THIS_MODULE;
428 ar->rcdev.nr_resets = 64;
429 ar->rcdev.ops = &aspeed_g6_reset_ops;
430 ar->rcdev.of_node = dev->of_node;
431
432 ret = devm_reset_controller_register(dev, &ar->rcdev);
433 if (ret) {
434 dev_err(dev, "could not register reset controller\n");
435 return ret;
436 }
437
438 /* UART clock div13 setting */
439 regmap_read(map, ASPEED_G6_MISC_CTRL, &val);
440 if (val & UART_DIV13_EN)
441 rate = 24000000 / 13;
442 else
443 rate = 24000000;
444 hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
445 if (IS_ERR(hw))
446 return PTR_ERR(hw);
447 aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw;
448
449 /* UART6~13 clock div13 setting */
450 regmap_read(map, 0x80, &val);
451 if (val & BIT(31))
452 rate = 24000000 / 13;
453 else
454 rate = 24000000;
455 hw = clk_hw_register_fixed_rate(dev, "uartx", NULL, 0, rate);
456 if (IS_ERR(hw))
457 return PTR_ERR(hw);
458 aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw;
459
460 /* EMMC ext clock divider */
461 hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "hpll", 0,
462 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 15, 0,
463 &aspeed_g6_clk_lock);
464 if (IS_ERR(hw))
465 return PTR_ERR(hw);
466 hw = clk_hw_register_divider_table(dev, "emmc_extclk", "emmc_extclk_gate", 0,
467 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 12, 3, 0,
468 ast2600_div_table,
469 &aspeed_g6_clk_lock);
470 if (IS_ERR(hw))
471 return PTR_ERR(hw);
472 aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw;
473
474 /* SD/SDIO clock divider and gate */
475 hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
476 scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0,
477 &aspeed_g6_clk_lock);
478 if (IS_ERR(hw))
479 return PTR_ERR(hw);
480 hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
481 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0,
482 ast2600_div_table,
483 &aspeed_g6_clk_lock);
484 if (IS_ERR(hw))
485 return PTR_ERR(hw);
486 aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw;
487
488 /* MAC1/2 AHB bus clock divider */
489 hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0,
490 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0,
491 ast2600_mac_div_table,
492 &aspeed_g6_clk_lock);
493 if (IS_ERR(hw))
494 return PTR_ERR(hw);
495 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw;
496
497 /* MAC3/4 AHB bus clock divider */
498 hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0,
499 scu_g6_base + 0x310, 24, 3, 0,
500 ast2600_mac_div_table,
501 &aspeed_g6_clk_lock);
502 if (IS_ERR(hw))
503 return PTR_ERR(hw);
504 aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw;
505
506 /* LPC Host (LHCLK) clock divider */
507 hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
508 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
509 ast2600_div_table,
510 &aspeed_g6_clk_lock);
511 if (IS_ERR(hw))
512 return PTR_ERR(hw);
513 aspeed_g6_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
514
515 /* gfx d1clk : use dp clk */
516 regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10));
517 /* SoC Display clock selection */
518 hw = clk_hw_register_mux(dev, "d1clk", d1clk_parent_names,
519 ARRAY_SIZE(d1clk_parent_names), 0,
520 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 8, 3, 0,
521 &aspeed_g6_clk_lock);
522 if (IS_ERR(hw))
523 return PTR_ERR(hw);
524 aspeed_g6_clk_data->hws[ASPEED_CLK_D1CLK] = hw;
525
526 /* d1 clk div 0x308[17:15] x [14:12] - 8,7,6,5,4,3,2,1 */
527 regmap_write(map, 0x308, 0x12000); /* 3x3 = 9 */
528
529 /* P-Bus (BCLK) clock divider */
530 hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
531 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
532 ast2600_div_table,
533 &aspeed_g6_clk_lock);
534 if (IS_ERR(hw))
535 return PTR_ERR(hw);
536 aspeed_g6_clk_data->hws[ASPEED_CLK_BCLK] = hw;
537
538 /* Video Capture clock selection */
539 hw = clk_hw_register_mux(dev, "vclk", vclk_parent_names,
540 ARRAY_SIZE(vclk_parent_names), 0,
541 scu_g6_base + ASPEED_G6_CLK_SELECTION2, 12, 3, 0,
542 &aspeed_g6_clk_lock);
543 if (IS_ERR(hw))
544 return PTR_ERR(hw);
545 aspeed_g6_clk_data->hws[ASPEED_CLK_VCLK] = hw;
546
547 /* Video Engine clock divider */
548 hw = clk_hw_register_divider_table(dev, "eclk", NULL, 0,
549 scu_g6_base + ASPEED_G6_CLK_SELECTION1, 28, 3, 0,
550 ast2600_eclk_div_table,
551 &aspeed_g6_clk_lock);
552 if (IS_ERR(hw))
553 return PTR_ERR(hw);
554 aspeed_g6_clk_data->hws[ASPEED_CLK_ECLK] = hw;
555
556 for (i = 0; i < ARRAY_SIZE(aspeed_g6_gates); i++) {
557 const struct aspeed_gate_data *gd = &aspeed_g6_gates[i];
558 u32 gate_flags;
559
560 /*
561 * Special case: the USB port 1 clock (bit 14) is always
562 * working the opposite way from the other ones.
563 */
564 gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
565 hw = aspeed_g6_clk_hw_register_gate(dev,
566 gd->name,
567 gd->parent_name,
568 gd->flags,
569 map,
570 gd->clock_idx,
571 gd->reset_idx,
572 gate_flags,
573 &aspeed_g6_clk_lock);
574 if (IS_ERR(hw))
575 return PTR_ERR(hw);
576 aspeed_g6_clk_data->hws[i] = hw;
577 }
578
579 return 0;
580};
581
582static const struct of_device_id aspeed_g6_clk_dt_ids[] = {
583 { .compatible = "aspeed,ast2600-scu" },
584 { }
585};
586
587static struct platform_driver aspeed_g6_clk_driver = {
588 .probe = aspeed_g6_clk_probe,
589 .driver = {
590 .name = "ast2600-clk",
591 .of_match_table = aspeed_g6_clk_dt_ids,
592 .suppress_bind_attrs = true,
593 },
594};
595builtin_platform_driver(aspeed_g6_clk_driver);
596
597static const u32 ast2600_a0_axi_ahb_div_table[] = {
598 2, 2, 3, 5,
599};
600
601static const u32 ast2600_a1_axi_ahb_div_table[] = {
602 4, 6, 2, 4,
603};
604
605static void __init aspeed_g6_cc(struct regmap *map)
606{
607 struct clk_hw *hw;
608 u32 val, div, chip_id, axi_div, ahb_div;
609
610 clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
611
612 /*
613 * High-speed PLL clock derived from the crystal. This the CPU clock,
614 * and we assume that it is enabled
615 */
616 regmap_read(map, ASPEED_HPLL_PARAM, &val);
617 aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val);
618
619 regmap_read(map, ASPEED_MPLL_PARAM, &val);
620 aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val);
621
622 regmap_read(map, ASPEED_DPLL_PARAM, &val);
623 aspeed_g6_clk_data->hws[ASPEED_CLK_DPLL] = ast2600_calc_pll("dpll", val);
624
625 regmap_read(map, ASPEED_EPLL_PARAM, &val);
626 aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val);
627
628 regmap_read(map, ASPEED_APLL_PARAM, &val);
629 aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val);
630
631 /* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/
632 regmap_read(map, ASPEED_G6_STRAP1, &val);
633 if (val & BIT(16))
634 axi_div = 1;
635 else
636 axi_div = 2;
637
638 regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);
639 if (chip_id & BIT(16))
640 ahb_div = ast2600_a1_axi_ahb_div_table[(val >> 11) & 0x3];
641 else
642 ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3];
643
644 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div);
645 aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw;
646
647 regmap_read(map, ASPEED_G6_CLK_SELECTION1, &val);
648 val = (val >> 23) & 0x7;
649 div = 4 * (val + 1);
650 hw = clk_hw_register_fixed_factor(NULL, "apb1", "hpll", 0, 1, div);
651 aspeed_g6_clk_data->hws[ASPEED_CLK_APB1] = hw;
652
653 regmap_read(map, ASPEED_G6_CLK_SELECTION4, &val);
654 val = (val >> 9) & 0x7;
655 div = 2 * (val + 1);
656 hw = clk_hw_register_fixed_factor(NULL, "apb2", "ahb", 0, 1, div);
657 aspeed_g6_clk_data->hws[ASPEED_CLK_APB2] = hw;
658
659 /* USB 2.0 port1 phy 40MHz clock */
660 hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000);
661 aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw;
662};
663
664static void __init aspeed_g6_cc_init(struct device_node *np)
665{
666 struct regmap *map;
667 int ret;
668 int i;
669
670 scu_g6_base = of_iomap(np, 0);
671 if (!scu_g6_base)
672 return;
673
674 aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws,
675 ASPEED_G6_NUM_CLKS), GFP_KERNEL);
676 if (!aspeed_g6_clk_data)
677 return;
678
679 /*
680 * This way all clocks fetched before the platform device probes,
681 * except those we assign here for early use, will be deferred.
682 */
683 for (i = 0; i < ASPEED_G6_NUM_CLKS; i++)
684 aspeed_g6_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
685
686 /*
687 * We check that the regmap works on this very first access,
688 * but as this is an MMIO-backed regmap, subsequent regmap
689 * access is not going to fail and we skip error checks from
690 * this point.
691 */
692 map = syscon_node_to_regmap(np);
693 if (IS_ERR(map)) {
694 pr_err("no syscon regmap\n");
695 return;
696 }
697
698 aspeed_g6_cc(map);
699 aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
700 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);
701 if (ret)
702 pr_err("failed to add DT provider: %d\n", ret);
703};
704CLK_OF_DECLARE_DRIVER(aspeed_cc_g6, "aspeed,ast2600-scu", aspeed_g6_cc_init);
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index b06038b8f658..4f13a681ddfc 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -3,7 +3,6 @@
3 * Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved. 3 * Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved.
4 */ 4 */
5 5
6#include <linux/clk.h>
7#include <linux/clk-provider.h> 6#include <linux/clk-provider.h>
8#include <linux/err.h> 7#include <linux/err.h>
9#include <linux/slab.h> 8#include <linux/slab.h>
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 07f3b252f3e0..bed140f7375f 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -686,7 +686,7 @@ static const struct clockgen_chipinfo chipinfo[] = {
686 .guts_compat = "fsl,qoriq-device-config-1.0", 686 .guts_compat = "fsl,qoriq-device-config-1.0",
687 .init_periph = p5020_init_periph, 687 .init_periph = p5020_init_periph,
688 .cmux_groups = { 688 .cmux_groups = {
689 &p2041_cmux_grp1, &p2041_cmux_grp2 689 &p5020_cmux_grp1, &p5020_cmux_grp2
690 }, 690 },
691 .cmux_to_group = { 691 .cmux_to_group = {
692 0, 1, -1 692 0, 1, -1
diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c
index 72424eb7e5f8..6e780c2a9e6b 100644
--- a/drivers/clk/clk-si5341.c
+++ b/drivers/clk/clk-si5341.c
@@ -547,7 +547,6 @@ static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
547 bool is_integer; 547 bool is_integer;
548 548
549 n_num = synth->data->freq_vco; 549 n_num = synth->data->freq_vco;
550 n_den = rate;
551 550
552 /* see if there's an integer solution */ 551 /* see if there's an integer solution */
553 r = do_div(n_num, rate); 552 r = do_div(n_num, rate);
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index c0990703ce54..7783c25fb407 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -593,6 +593,8 @@ static void clk_core_get_boundaries(struct clk_core *core,
593{ 593{
594 struct clk *clk_user; 594 struct clk *clk_user;
595 595
596 lockdep_assert_held(&prepare_lock);
597
596 *min_rate = core->min_rate; 598 *min_rate = core->min_rate;
597 *max_rate = core->max_rate; 599 *max_rate = core->max_rate;
598 600
@@ -2847,9 +2849,6 @@ static struct hlist_head *orphan_list[] = {
2847static void clk_summary_show_one(struct seq_file *s, struct clk_core *c, 2849static void clk_summary_show_one(struct seq_file *s, struct clk_core *c,
2848 int level) 2850 int level)
2849{ 2851{
2850 if (!c)
2851 return;
2852
2853 seq_printf(s, "%*s%-*s %7d %8d %8d %11lu %10lu %5d %6d\n", 2852 seq_printf(s, "%*s%-*s %7d %8d %8d %11lu %10lu %5d %6d\n",
2854 level * 3 + 1, "", 2853 level * 3 + 1, "",
2855 30 - level * 3, c->name, 2854 30 - level * 3, c->name,
@@ -2864,9 +2863,6 @@ static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
2864{ 2863{
2865 struct clk_core *child; 2864 struct clk_core *child;
2866 2865
2867 if (!c)
2868 return;
2869
2870 clk_summary_show_one(s, c, level); 2866 clk_summary_show_one(s, c, level);
2871 2867
2872 hlist_for_each_entry(child, &c->children, child_node) 2868 hlist_for_each_entry(child, &c->children, child_node)
@@ -2896,8 +2892,9 @@ DEFINE_SHOW_ATTRIBUTE(clk_summary);
2896 2892
2897static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level) 2893static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
2898{ 2894{
2899 if (!c) 2895 unsigned long min_rate, max_rate;
2900 return; 2896
2897 clk_core_get_boundaries(c, &min_rate, &max_rate);
2901 2898
2902 /* This should be JSON format, i.e. elements separated with a comma */ 2899 /* This should be JSON format, i.e. elements separated with a comma */
2903 seq_printf(s, "\"%s\": { ", c->name); 2900 seq_printf(s, "\"%s\": { ", c->name);
@@ -2905,6 +2902,8 @@ static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level)
2905 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count); 2902 seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
2906 seq_printf(s, "\"protect_count\": %d,", c->protect_count); 2903 seq_printf(s, "\"protect_count\": %d,", c->protect_count);
2907 seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c)); 2904 seq_printf(s, "\"rate\": %lu,", clk_core_get_rate(c));
2905 seq_printf(s, "\"min_rate\": %lu,", min_rate);
2906 seq_printf(s, "\"max_rate\": %lu,", max_rate);
2908 seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c)); 2907 seq_printf(s, "\"accuracy\": %lu,", clk_core_get_accuracy(c));
2909 seq_printf(s, "\"phase\": %d,", clk_core_get_phase(c)); 2908 seq_printf(s, "\"phase\": %d,", clk_core_get_phase(c));
2910 seq_printf(s, "\"duty_cycle\": %u", 2909 seq_printf(s, "\"duty_cycle\": %u",
@@ -2915,9 +2914,6 @@ static void clk_dump_subtree(struct seq_file *s, struct clk_core *c, int level)
2915{ 2914{
2916 struct clk_core *child; 2915 struct clk_core *child;
2917 2916
2918 if (!c)
2919 return;
2920
2921 clk_dump_one(s, c, level); 2917 clk_dump_one(s, c, level);
2922 2918
2923 hlist_for_each_entry(child, &c->children, child_node) { 2919 hlist_for_each_entry(child, &c->children, child_node) {
@@ -3013,15 +3009,15 @@ static void possible_parent_show(struct seq_file *s, struct clk_core *core,
3013 */ 3009 */
3014 parent = clk_core_get_parent_by_index(core, i); 3010 parent = clk_core_get_parent_by_index(core, i);
3015 if (parent) 3011 if (parent)
3016 seq_printf(s, "%s", parent->name); 3012 seq_puts(s, parent->name);
3017 else if (core->parents[i].name) 3013 else if (core->parents[i].name)
3018 seq_printf(s, "%s", core->parents[i].name); 3014 seq_puts(s, core->parents[i].name);
3019 else if (core->parents[i].fw_name) 3015 else if (core->parents[i].fw_name)
3020 seq_printf(s, "<%s>(fw)", core->parents[i].fw_name); 3016 seq_printf(s, "<%s>(fw)", core->parents[i].fw_name);
3021 else if (core->parents[i].index >= 0) 3017 else if (core->parents[i].index >= 0)
3022 seq_printf(s, "%s", 3018 seq_puts(s,
3023 of_clk_get_parent_name(core->of_node, 3019 of_clk_get_parent_name(core->of_node,
3024 core->parents[i].index)); 3020 core->parents[i].index));
3025 else 3021 else
3026 seq_puts(s, "(missing)"); 3022 seq_puts(s, "(missing)");
3027 3023
@@ -3064,6 +3060,34 @@ static int clk_duty_cycle_show(struct seq_file *s, void *data)
3064} 3060}
3065DEFINE_SHOW_ATTRIBUTE(clk_duty_cycle); 3061DEFINE_SHOW_ATTRIBUTE(clk_duty_cycle);
3066 3062
3063static int clk_min_rate_show(struct seq_file *s, void *data)
3064{
3065 struct clk_core *core = s->private;
3066 unsigned long min_rate, max_rate;
3067
3068 clk_prepare_lock();
3069 clk_core_get_boundaries(core, &min_rate, &max_rate);
3070 clk_prepare_unlock();
3071 seq_printf(s, "%lu\n", min_rate);
3072
3073 return 0;
3074}
3075DEFINE_SHOW_ATTRIBUTE(clk_min_rate);
3076
3077static int clk_max_rate_show(struct seq_file *s, void *data)
3078{
3079 struct clk_core *core = s->private;
3080 unsigned long min_rate, max_rate;
3081
3082 clk_prepare_lock();
3083 clk_core_get_boundaries(core, &min_rate, &max_rate);
3084 clk_prepare_unlock();
3085 seq_printf(s, "%lu\n", max_rate);
3086
3087 return 0;
3088}
3089DEFINE_SHOW_ATTRIBUTE(clk_max_rate);
3090
3067static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry) 3091static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
3068{ 3092{
3069 struct dentry *root; 3093 struct dentry *root;
@@ -3075,6 +3099,8 @@ static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
3075 core->dentry = root; 3099 core->dentry = root;
3076 3100
3077 debugfs_create_ulong("clk_rate", 0444, root, &core->rate); 3101 debugfs_create_ulong("clk_rate", 0444, root, &core->rate);
3102 debugfs_create_file("clk_min_rate", 0444, root, core, &clk_min_rate_fops);
3103 debugfs_create_file("clk_max_rate", 0444, root, core, &clk_max_rate_fops);
3078 debugfs_create_ulong("clk_accuracy", 0444, root, &core->accuracy); 3104 debugfs_create_ulong("clk_accuracy", 0444, root, &core->accuracy);
3079 debugfs_create_u32("clk_phase", 0444, root, &core->phase); 3105 debugfs_create_u32("clk_phase", 0444, root, &core->phase);
3080 debugfs_create_file("clk_flags", 0444, root, core, &clk_flags_fops); 3106 debugfs_create_file("clk_flags", 0444, root, core, &clk_flags_fops);
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index ca1ccdb8a3b1..a156bd0c6af7 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -67,7 +67,6 @@ struct clkgen_quadfs_data {
67}; 67};
68 68
69static const struct clk_ops st_quadfs_pll_c32_ops; 69static const struct clk_ops st_quadfs_pll_c32_ops;
70static const struct clk_ops st_quadfs_fs660c32_ops;
71 70
72static int clk_fs660c32_dig_get_params(unsigned long input, 71static int clk_fs660c32_dig_get_params(unsigned long input,
73 unsigned long output, struct stm_fs *fs); 72 unsigned long output, struct stm_fs *fs);
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index d8a688bd45ec..c3952f2c42ba 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -61,19 +61,6 @@ static const struct clk_ops stm_pll3200c32_ops;
61static const struct clk_ops stm_pll3200c32_a9_ops; 61static const struct clk_ops stm_pll3200c32_a9_ops;
62static const struct clk_ops stm_pll4600c28_ops; 62static const struct clk_ops stm_pll4600c28_ops;
63 63
64static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
65 /* 407 A0 */
66 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
67 .pdn_ctrl = CLKGEN_FIELD(0x2a0, 0x1, 8),
68 .locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
69 .ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
70 .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
71 .num_odfs = 1,
72 .odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
73 .odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
74 .ops = &stm_pll3200c32_ops,
75};
76
77static const struct clkgen_pll_data st_pll3200c32_cx_0 = { 64static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
78 /* 407 C0 PLL0 */ 65 /* 407 C0 PLL0 */
79 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8), 66 .pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
new file mode 100644
index 000000000000..38074a5f7296
--- /dev/null
+++ b/include/dt-bindings/clock/ast2600-clock.h
@@ -0,0 +1,113 @@
1/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */
2#ifndef DT_BINDINGS_AST2600_CLOCK_H
3#define DT_BINDINGS_AST2600_CLOCK_H
4
5#define ASPEED_CLK_GATE_ECLK 0
6#define ASPEED_CLK_GATE_GCLK 1
7
8#define ASPEED_CLK_GATE_MCLK 2
9
10#define ASPEED_CLK_GATE_VCLK 3
11#define ASPEED_CLK_GATE_BCLK 4
12#define ASPEED_CLK_GATE_DCLK 5
13
14#define ASPEED_CLK_GATE_LCLK 6
15#define ASPEED_CLK_GATE_LHCCLK 7
16
17#define ASPEED_CLK_GATE_D1CLK 8
18#define ASPEED_CLK_GATE_YCLK 9
19
20#define ASPEED_CLK_GATE_REF0CLK 10
21#define ASPEED_CLK_GATE_REF1CLK 11
22
23#define ASPEED_CLK_GATE_ESPICLK 12
24
25#define ASPEED_CLK_GATE_USBUHCICLK 13
26#define ASPEED_CLK_GATE_USBPORT1CLK 14
27#define ASPEED_CLK_GATE_USBPORT2CLK 15
28
29#define ASPEED_CLK_GATE_RSACLK 16
30#define ASPEED_CLK_GATE_RVASCLK 17
31
32#define ASPEED_CLK_GATE_MAC1CLK 18
33#define ASPEED_CLK_GATE_MAC2CLK 19
34#define ASPEED_CLK_GATE_MAC3CLK 20
35#define ASPEED_CLK_GATE_MAC4CLK 21
36
37#define ASPEED_CLK_GATE_UART1CLK 22
38#define ASPEED_CLK_GATE_UART2CLK 23
39#define ASPEED_CLK_GATE_UART3CLK 24
40#define ASPEED_CLK_GATE_UART4CLK 25
41#define ASPEED_CLK_GATE_UART5CLK 26
42#define ASPEED_CLK_GATE_UART6CLK 27
43#define ASPEED_CLK_GATE_UART7CLK 28
44#define ASPEED_CLK_GATE_UART8CLK 29
45#define ASPEED_CLK_GATE_UART9CLK 30
46#define ASPEED_CLK_GATE_UART10CLK 31
47#define ASPEED_CLK_GATE_UART11CLK 32
48#define ASPEED_CLK_GATE_UART12CLK 33
49#define ASPEED_CLK_GATE_UART13CLK 34
50
51#define ASPEED_CLK_GATE_SDCLK 35
52#define ASPEED_CLK_GATE_EMMCCLK 36
53
54#define ASPEED_CLK_GATE_I3C0CLK 37
55#define ASPEED_CLK_GATE_I3C1CLK 38
56#define ASPEED_CLK_GATE_I3C2CLK 39
57#define ASPEED_CLK_GATE_I3C3CLK 40
58#define ASPEED_CLK_GATE_I3C4CLK 41
59#define ASPEED_CLK_GATE_I3C5CLK 42
60#define ASPEED_CLK_GATE_I3C6CLK 43
61#define ASPEED_CLK_GATE_I3C7CLK 44
62
63#define ASPEED_CLK_GATE_FSICLK 45
64
65#define ASPEED_CLK_HPLL 46
66#define ASPEED_CLK_MPLL 47
67#define ASPEED_CLK_DPLL 48
68#define ASPEED_CLK_EPLL 49
69#define ASPEED_CLK_APLL 50
70#define ASPEED_CLK_AHB 51
71#define ASPEED_CLK_APB1 52
72#define ASPEED_CLK_APB2 53
73#define ASPEED_CLK_BCLK 54
74#define ASPEED_CLK_D1CLK 55
75#define ASPEED_CLK_VCLK 56
76#define ASPEED_CLK_LHCLK 57
77#define ASPEED_CLK_UART 58
78#define ASPEED_CLK_UARTX 59
79#define ASPEED_CLK_SDIO 60
80#define ASPEED_CLK_EMMC 61
81#define ASPEED_CLK_ECLK 62
82#define ASPEED_CLK_ECLK_MUX 63
83#define ASPEED_CLK_MAC12 64
84#define ASPEED_CLK_MAC34 65
85#define ASPEED_CLK_USBPHY_40M 66
86
87/* Only list resets here that are not part of a gate */
88#define ASPEED_RESET_ADC 55
89#define ASPEED_RESET_JTAG_MASTER2 54
90#define ASPEED_RESET_I3C_DMA 39
91#define ASPEED_RESET_PWM 37
92#define ASPEED_RESET_PECI 36
93#define ASPEED_RESET_MII 35
94#define ASPEED_RESET_I2C 34
95#define ASPEED_RESET_H2X 31
96#define ASPEED_RESET_GP_MCU 30
97#define ASPEED_RESET_DP_MCU 29
98#define ASPEED_RESET_DP 28
99#define ASPEED_RESET_RC_XDMA 27
100#define ASPEED_RESET_GRAPHICS 26
101#define ASPEED_RESET_DEV_XDMA 25
102#define ASPEED_RESET_DEV_MCTP 24
103#define ASPEED_RESET_RC_MCTP 23
104#define ASPEED_RESET_JTAG_MASTER 22
105#define ASPEED_RESET_PCIE_DEV_O 21
106#define ASPEED_RESET_PCIE_DEV_OEN 20
107#define ASPEED_RESET_PCIE_RC_O 19
108#define ASPEED_RESET_PCIE_RC_OEN 18
109#define ASPEED_RESET_PCI_DP 5
110#define ASPEED_RESET_AHB 1
111#define ASPEED_RESET_SDRAM 0
112
113#endif
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 3c096c7a51dc..7a795fd6d141 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -239,7 +239,8 @@ static inline int clk_prepare(struct clk *clk)
239 return 0; 239 return 0;
240} 240}
241 241
242static inline int __must_check clk_bulk_prepare(int num_clks, struct clk_bulk_data *clks) 242static inline int __must_check
243clk_bulk_prepare(int num_clks, const struct clk_bulk_data *clks)
243{ 244{
244 might_sleep(); 245 might_sleep();
245 return 0; 246 return 0;
@@ -263,7 +264,8 @@ static inline void clk_unprepare(struct clk *clk)
263{ 264{
264 might_sleep(); 265 might_sleep();
265} 266}
266static inline void clk_bulk_unprepare(int num_clks, struct clk_bulk_data *clks) 267static inline void clk_bulk_unprepare(int num_clks,
268 const struct clk_bulk_data *clks)
267{ 269{
268 might_sleep(); 270 might_sleep();
269} 271}
@@ -819,7 +821,8 @@ static inline int clk_enable(struct clk *clk)
819 return 0; 821 return 0;
820} 822}
821 823
822static inline int __must_check clk_bulk_enable(int num_clks, struct clk_bulk_data *clks) 824static inline int __must_check clk_bulk_enable(int num_clks,
825 const struct clk_bulk_data *clks)
823{ 826{
824 return 0; 827 return 0;
825} 828}
@@ -828,7 +831,7 @@ static inline void clk_disable(struct clk *clk) {}
828 831
829 832
830static inline void clk_bulk_disable(int num_clks, 833static inline void clk_bulk_disable(int num_clks,
831 struct clk_bulk_data *clks) {} 834 const struct clk_bulk_data *clks) {}
832 835
833static inline unsigned long clk_get_rate(struct clk *clk) 836static inline unsigned long clk_get_rate(struct clk *clk)
834{ 837{
@@ -917,8 +920,8 @@ static inline void clk_disable_unprepare(struct clk *clk)
917 clk_unprepare(clk); 920 clk_unprepare(clk);
918} 921}
919 922
920static inline int __must_check clk_bulk_prepare_enable(int num_clks, 923static inline int __must_check
921 struct clk_bulk_data *clks) 924clk_bulk_prepare_enable(int num_clks, const struct clk_bulk_data *clks)
922{ 925{
923 int ret; 926 int ret;
924 927
@@ -933,7 +936,7 @@ static inline int __must_check clk_bulk_prepare_enable(int num_clks,
933} 936}
934 937
935static inline void clk_bulk_disable_unprepare(int num_clks, 938static inline void clk_bulk_disable_unprepare(int num_clks,
936 struct clk_bulk_data *clks) 939 const struct clk_bulk_data *clks)
937{ 940{
938 clk_bulk_disable(num_clks, clks); 941 clk_bulk_disable(num_clks, clks);
939 clk_bulk_unprepare(num_clks, clks); 942 clk_bulk_unprepare(num_clks, clks);
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 07:32:24 -0400