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-rw-r--r--Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt10
-rw-r--r--Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt4
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt4
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt (renamed from Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt)59
-rw-r--r--Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt2
-rw-r--r--Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt6
-rw-r--r--Documentation/driver-api/pinctl.rst6
-rw-r--r--Documentation/gpio/gpio-legacy.txt10
-rw-r--r--Documentation/translations/zh_CN/gpio.txt6
-rw-r--r--MAINTAINERS1
-rw-r--r--arch/blackfin/Kconfig7
-rw-r--r--arch/blackfin/Kconfig.debug1
-rw-r--r--arch/blackfin/include/asm/gpio.h20
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c3
-rw-r--r--arch/blackfin/kernel/debug-mmrs.c2
-rw-r--r--arch/blackfin/mach-common/ints-priority.c2
-rw-r--r--arch/blackfin/mach-common/pm.c2
-rw-r--r--drivers/gpio/Kconfig9
-rw-r--r--drivers/gpio/gpio-aspeed.c4
-rw-r--r--drivers/gpio/gpio-em.c4
-rw-r--r--drivers/gpio/gpio-pxa.c14
-rw-r--r--drivers/gpio/gpio-rcar.c4
-rw-r--r--drivers/gpio/gpio-tegra.c4
-rw-r--r--drivers/gpio/gpio-tz1090.c4
-rw-r--r--drivers/gpio/gpiolib.c4
-rw-r--r--drivers/pinctrl/Kconfig32
-rw-r--r--drivers/pinctrl/bcm/pinctrl-iproc-gpio.c4
-rw-r--r--drivers/pinctrl/bcm/pinctrl-nsp-gpio.c21
-rw-r--r--drivers/pinctrl/core.c12
-rw-r--r--drivers/pinctrl/core.h2
-rw-r--r--drivers/pinctrl/intel/Kconfig11
-rw-r--r--drivers/pinctrl/intel/Makefile1
-rw-r--r--drivers/pinctrl/intel/pinctrl-cedarfork.c375
-rw-r--r--drivers/pinctrl/intel/pinctrl-cherryview.c2
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.c20
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.h3
-rw-r--r--drivers/pinctrl/meson/Kconfig41
-rw-r--r--drivers/pinctrl/meson/Makefile9
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson-gxbb.c892
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson-gxl.c852
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson.c200
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson.h47
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson8-pmx.c108
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson8-pmx.h48
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson8.c992
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson8b.c808
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-37xx.c64
-rw-r--r--drivers/pinctrl/pinconf-generic.c2
-rw-r--r--drivers/pinctrl/pinctrl-amd.c4
-rw-r--r--drivers/pinctrl/pinctrl-gemini.c333
-rw-r--r--drivers/pinctrl/pinctrl-ingenic.c2
-rw-r--r--drivers/pinctrl/pinctrl-max77620.c21
-rw-r--r--drivers/pinctrl/pinctrl-mcp23s08.c20
-rw-r--r--drivers/pinctrl/pinctrl-rockchip.c43
-rw-r--r--drivers/pinctrl/pinctrl-rza1.c134
-rw-r--r--drivers/pinctrl/pinctrl-single.c4
-rw-r--r--drivers/pinctrl/pinctrl-sx150x.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-spmi-gpio.c6
-rw-r--r--drivers/pinctrl/samsung/Kconfig2
-rw-r--r--drivers/pinctrl/sh-pfc/core.c131
-rw-r--r--drivers/pinctrl/sh-pfc/core.h11
-rw-r--r--drivers/pinctrl/sh-pfc/gpio.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7778.c403
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7794.c1
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c542
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7795.c1904
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7796.c573
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a77995.c394
-rw-r--r--drivers/pinctrl/sh-pfc/pinctrl.c12
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h24
-rw-r--r--drivers/pinctrl/sirf/pinctrl-atlas7.c4
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.c4
-rw-r--r--drivers/pinctrl/spear/pinctrl-plgpio.c6
-rw-r--r--drivers/pinctrl/stm32/pinctrl-stm32.c4
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun5i.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c3
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c3
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c1
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.c13
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sunxi.h1
-rw-r--r--drivers/pinctrl/ti/pinctrl-ti-iodelay.c4
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-core.c14
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c4
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c4
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c4
-rw-r--r--include/dt-bindings/gpio/meson-gxbb-gpio.h2
-rw-r--r--include/dt-bindings/gpio/meson-gxl-gpio.h2
-rw-r--r--include/linux/pinctrl/consumer.h8
-rw-r--r--include/linux/pinctrl/pinconf-generic.h5
96 files changed, 6241 insertions, 3161 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
index 61466c58faae..d857b67fab72 100644
--- a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
@@ -9,8 +9,14 @@ The pin controller node must be a subnode of the system controller node.
9Required properties: 9Required properties:
10- compatible: "cortina,gemini-pinctrl" 10- compatible: "cortina,gemini-pinctrl"
11 11
12Subnodes of the pin controller contain pin control multiplexing set-up. 12Subnodes of the pin controller contain pin control multiplexing set-up
13Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes. 13and pin configuration of individual pins.
14
15Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes
16and generic pin config nodes.
17
18Supported configurations:
19- skew-delay is supported on the Ethernet pins
14 20
15Example: 21Example:
16 22
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
index f64060908d5a..c7c088d2dd50 100644
--- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
@@ -97,8 +97,8 @@ group spi_quad
97 - pins 15-16 97 - pins 15-16
98 - functions spi, gpio 98 - functions spi, gpio
99 99
100group uart_2 100group uart2
101 - pins 9-10 101 - pins 9-10 and 18-19
102 - functions uart, gpio 102 - functions uart, gpio
103 103
104Available groups and functions for the South bridge: 104Available groups and functions for the South bridge:
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
index 4483cc31e531..ad9bbbba36e9 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
@@ -271,6 +271,10 @@ output-high - set the pin to output mode with high level
271sleep-hardware-state - indicate this is sleep related state which will be programmed 271sleep-hardware-state - indicate this is sleep related state which will be programmed
272 into the registers for the sleep state. 272 into the registers for the sleep state.
273slew-rate - set the slew rate 273slew-rate - set the slew rate
274skew-delay - this affects the expected clock skew on input pins
275 and the delay before latching a value to an output
276 pin. Typically indicates how many double-inverters are
277 used to delay the signal.
274 278
275For example: 279For example:
276 280
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt
index c934106b10aa..9c451c20dda4 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-mcp23s08.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt
@@ -13,6 +13,7 @@ Required properties:
13 - "microchip,mcp23s18" for 16 GPIO SPI version 13 - "microchip,mcp23s18" for 16 GPIO SPI version
14 - "microchip,mcp23008" for 8 GPIO I2C version or 14 - "microchip,mcp23008" for 8 GPIO I2C version or
15 - "microchip,mcp23017" for 16 GPIO I2C version of the chip 15 - "microchip,mcp23017" for 16 GPIO I2C version of the chip
16 - "microchip,mcp23018" for 16 GPIO I2C version
16 NOTE: Do not use the old mcp prefix any more. It is deprecated and will be 17 NOTE: Do not use the old mcp prefix any more. It is deprecated and will be
17 removed. 18 removed.
18- #gpio-cells : Should be two. 19- #gpio-cells : Should be two.
@@ -81,3 +82,61 @@ gpiom1: gpio@0 {
81 reg = <0>; 82 reg = <0>;
82 spi-max-frequency = <1000000>; 83 spi-max-frequency = <1000000>;
83}; 84};
85
86Pull-up configuration
87=====================
88
89If pins are used as output, they can also be configured with pull-ups. This is
90done with pinctrl.
91
92Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
93for details of the common pinctrl bindings used by client devices,
94including the meaning of the phrase "pin configuration node".
95
96Optional Pinmux properties:
97--------------------------
98Following properties are required if default setting of pins are required
99at boot.
100- pinctrl-names: A pinctrl state named per <pinctrl-binding.txt>.
101- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
102 <pinctrl-binding.txt>.
103
104The pin configurations are defined as child of the pinctrl states node. Each
105sub-node have following properties:
106
107Required properties:
108------------------
109- pins: List of pins. Valid values of pins properties are:
110 gpio0 ... gpio7 for the devices with 8 GPIO pins and
111 gpio0 ... gpio15 for the devices with 16 GPIO pins.
112
113Optional properties:
114-------------------
115The following optional property is defined in the pinmux DT binding document
116<pinctrl-bindings.txt>. Absence of this property will leave the configuration
117in its default state.
118 bias-pull-up
119
120Example with pinctrl to pull-up output pins:
121gpio21: gpio@21 {
122 compatible = "microchip,mcp23017";
123 gpio-controller;
124 #gpio-cells = <0x2>;
125 reg = <0x21>;
126 interrupt-parent = <&socgpio>;
127 interrupts = <0x17 0x8>;
128 interrupt-names = "mcp23017@21 irq";
129 interrupt-controller;
130 #interrupt-cells = <0x2>;
131 microchip,irq-mirror;
132 pinctrl-names = "default";
133 pinctrl-0 = <&i2cgpio0irq &gpio21pullups>;
134
135 gpio21pullups: pinmux {
136 pins = "gpio0", "gpio1", "gpio2", "gpio3",
137 "gpio4", "gpio5", "gpio6", "gpio7",
138 "gpio8", "gpio9", "gpio10", "gpio11",
139 "gpio12", "gpio13", "gpio14", "gpio15";
140 bias-pull-up;
141 };
142};
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
index 5b12c57e7f02..5c25fcb29fb5 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
@@ -15,6 +15,7 @@ PMIC's from Qualcomm.
15 "qcom,pm8921-gpio" 15 "qcom,pm8921-gpio"
16 "qcom,pm8941-gpio" 16 "qcom,pm8941-gpio"
17 "qcom,pm8994-gpio" 17 "qcom,pm8994-gpio"
18 "qcom,pmi8994-gpio"
18 "qcom,pma8084-gpio" 19 "qcom,pma8084-gpio"
19 "qcom,pmi8994-gpio" 20 "qcom,pmi8994-gpio"
20 21
@@ -85,6 +86,7 @@ to specify in a pin configuration subnode:
85 gpio1-gpio44 for pm8921 86 gpio1-gpio44 for pm8921
86 gpio1-gpio36 for pm8941 87 gpio1-gpio36 for pm8941
87 gpio1-gpio22 for pm8994 88 gpio1-gpio22 for pm8994
89 gpio1-gpio10 for pmi8994
88 gpio1-gpio22 for pma8084 90 gpio1-gpio22 for pma8084
89 gpio1-gpio10 for pmi8994 91 gpio1-gpio10 for pmi8994
90 92
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt
index 43e21474528a..fd3696eb36bf 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt
@@ -12,8 +12,10 @@ Pin controller node
12------------------- 12-------------------
13 13
14Required properties: 14Required properties:
15 - compatible 15 - compatible: should be:
16 this shall be "renesas,r7s72100-ports". 16 - "renesas,r7s72100-ports": for RZ/A1H
17 - "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M
18 - "renesas,r7s72102-ports": for RZ/A1L
17 19
18 - reg 20 - reg
19 address base and length of the memory area where the pin controller 21 address base and length of the memory area where the pin controller
diff --git a/Documentation/driver-api/pinctl.rst b/Documentation/driver-api/pinctl.rst
index 48f15b4f9d3e..6cb68d67fa75 100644
--- a/Documentation/driver-api/pinctl.rst
+++ b/Documentation/driver-api/pinctl.rst
@@ -757,8 +757,8 @@ that your datasheet calls "GPIO mode", but actually is just an electrical
757configuration for a certain device. See the section below named 757configuration for a certain device. See the section below named
758"GPIO mode pitfalls" for more details on this scenario. 758"GPIO mode pitfalls" for more details on this scenario.
759 759
760The public pinmux API contains two functions named pinctrl_request_gpio() 760The public pinmux API contains two functions named pinctrl_gpio_request()
761and pinctrl_free_gpio(). These two functions shall *ONLY* be called from 761and pinctrl_gpio_free(). These two functions shall *ONLY* be called from
762gpiolib-based drivers as part of their gpio_request() and 762gpiolib-based drivers as part of their gpio_request() and
763gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output] 763gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output]
764shall only be called from within respective gpio_direction_[input|output] 764shall only be called from within respective gpio_direction_[input|output]
@@ -790,7 +790,7 @@ gpiolib driver and the affected GPIO range, pin offset and desired direction
790will be passed along to this function. 790will be passed along to this function.
791 791
792Alternatively to using these special functions, it is fully allowed to use 792Alternatively to using these special functions, it is fully allowed to use
793named functions for each GPIO pin, the pinctrl_request_gpio() will attempt to 793named functions for each GPIO pin, the pinctrl_gpio_request() will attempt to
794obtain the function "gpioN" where "N" is the global GPIO pin number if no 794obtain the function "gpioN" where "N" is the global GPIO pin number if no
795special GPIO-handler is registered. 795special GPIO-handler is registered.
796 796
diff --git a/Documentation/gpio/gpio-legacy.txt b/Documentation/gpio/gpio-legacy.txt
index 5eacc147ea87..8356d0e78f67 100644
--- a/Documentation/gpio/gpio-legacy.txt
+++ b/Documentation/gpio/gpio-legacy.txt
@@ -273,8 +273,8 @@ easily, gating off unused clocks.
273 273
274For GPIOs that use pins known to the pinctrl subsystem, that subsystem should 274For GPIOs that use pins known to the pinctrl subsystem, that subsystem should
275be informed of their use; a gpiolib driver's .request() operation may call 275be informed of their use; a gpiolib driver's .request() operation may call
276pinctrl_request_gpio(), and a gpiolib driver's .free() operation may call 276pinctrl_gpio_request(), and a gpiolib driver's .free() operation may call
277pinctrl_free_gpio(). The pinctrl subsystem allows a pinctrl_request_gpio() 277pinctrl_gpio_free(). The pinctrl subsystem allows a pinctrl_gpio_request()
278to succeed concurrently with a pin or pingroup being "owned" by a device for 278to succeed concurrently with a pin or pingroup being "owned" by a device for
279pin multiplexing. 279pin multiplexing.
280 280
@@ -448,8 +448,8 @@ together with an optional gpio feature. We have already covered the
448case where e.g. a GPIO controller need to reserve a pin or set the 448case where e.g. a GPIO controller need to reserve a pin or set the
449direction of a pin by calling any of: 449direction of a pin by calling any of:
450 450
451pinctrl_request_gpio() 451pinctrl_gpio_request()
452pinctrl_free_gpio() 452pinctrl_gpio_free()
453pinctrl_gpio_direction_input() 453pinctrl_gpio_direction_input()
454pinctrl_gpio_direction_output() 454pinctrl_gpio_direction_output()
455 455
@@ -466,7 +466,7 @@ gpio (under gpiolib) is still maintained by gpio drivers. It may happen
466that different pin ranges in a SoC is managed by different gpio drivers. 466that different pin ranges in a SoC is managed by different gpio drivers.
467 467
468This makes it logical to let gpio drivers announce their pin ranges to 468This makes it logical to let gpio drivers announce their pin ranges to
469the pin ctrl subsystem before it will call 'pinctrl_request_gpio' in order 469the pin ctrl subsystem before it will call 'pinctrl_gpio_request' in order
470to request the corresponding pin to be prepared by the pinctrl subsystem 470to request the corresponding pin to be prepared by the pinctrl subsystem
471before any gpio usage. 471before any gpio usage.
472 472
diff --git a/Documentation/translations/zh_CN/gpio.txt b/Documentation/translations/zh_CN/gpio.txt
index bce972521065..4f8bf30a41dc 100644
--- a/Documentation/translations/zh_CN/gpio.txt
+++ b/Documentation/translations/zh_CN/gpio.txt
@@ -257,9 +257,9 @@ GPIO 值的命令需要等待其信息排到队首才发送命令，再获得其
257简单地关闭未使用时钟)。 257简单地关闭未使用时钟)。
258 258
259对于 GPIO 使用 pinctrl 子系统已知的引脚，子系统应该被告知其使用情况； 259对于 GPIO 使用 pinctrl 子系统已知的引脚，子系统应该被告知其使用情况；
260一个 gpiolib 驱动的 .request()操作应调用 pinctrl_request_gpio()， 260一个 gpiolib 驱动的 .request()操作应调用 pinctrl_gpio_request()，
261而 gpiolib 驱动的 .free()操作应调用 pinctrl_free_gpio()。pinctrl 261而 gpiolib 驱动的 .free()操作应调用 pinctrl_gpio_free()。pinctrl
262子系统允许 pinctrl_request_gpio()在某个引脚或引脚组以复用形式“属于” 262子系统允许 pinctrl_gpio_request()在某个引脚或引脚组以复用形式“属于”
263一个设备时都成功返回。 263一个设备时都成功返回。
264 264
265任何须将 GPIO 信号导向适当引脚的引脚复用硬件的编程应该发生在 GPIO 265任何须将 GPIO 信号导向适当引脚的引脚复用硬件的编程应该发生在 GPIO
diff --git a/MAINTAINERS b/MAINTAINERS
index fa9c49c594a1..c8dfe6cdc4dd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10713,6 +10713,7 @@ PIN CONTROLLER - RENESAS
10713M: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10713M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
10714M: Geert Uytterhoeven <geert+renesas@glider.be> 10714M: Geert Uytterhoeven <geert+renesas@glider.be>
10715L: linux-renesas-soc@vger.kernel.org 10715L: linux-renesas-soc@vger.kernel.org
10716T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc
10716S: Maintained 10717S: Maintained
10717F: drivers/pinctrl/sh-pfc/ 10718F: drivers/pinctrl/sh-pfc/
10718 10719
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index af5369422032..d9c2866ba618 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -321,11 +321,14 @@ config BF53x
321 321
322config GPIO_ADI 322config GPIO_ADI
323 def_bool y 323 def_bool y
324 depends on !PINCTRL
324 depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561) 325 depends on (BF51x || BF52x || BF53x || BF538 || BF539 || BF561)
325 326
326config PINCTRL 327config PINCTRL_BLACKFIN_ADI2
327 def_bool y 328 def_bool y
328 depends on BF54x || BF60x 329 depends on (BF54x || BF60x)
330 select PINCTRL
331 select PINCTRL_ADI2
329 332
330config MEM_MT48LC64M4A2FB_7E 333config MEM_MT48LC64M4A2FB_7E
331 bool 334 bool
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug
index 4ddd1b73ee3e..c8d957274cc2 100644
--- a/arch/blackfin/Kconfig.debug
+++ b/arch/blackfin/Kconfig.debug
@@ -18,6 +18,7 @@ config DEBUG_VERBOSE
18 18
19config DEBUG_MMRS 19config DEBUG_MMRS
20 tristate "Generate Blackfin MMR tree" 20 tristate "Generate Blackfin MMR tree"
21 depends on !PINCTRL
21 select DEBUG_FS 22 select DEBUG_FS
22 help 23 help
23 Create a tree of Blackfin MMRs via the debugfs tree. If 24 Create a tree of Blackfin MMRs via the debugfs tree. If
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 99d338ca2ea4..a2579321c7f1 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -183,6 +183,26 @@ static inline int irq_to_gpio(unsigned irq)
183{ 183{
184 return irq - GPIO_IRQ_BASE; 184 return irq - GPIO_IRQ_BASE;
185} 185}
186
187#else /* CONFIG_PINCTRL */
188
189/*
190 * CONFIG_PM is not working with pin control and should probably
191 * avoid being selected when pin control is active, but so far,
192 * these stubs are here to make allyesconfig and allmodconfig
193 * compile properly. These functions are normally backed by the
194 * CONFIG_ADI_GPIO custom GPIO implementation.
195 */
196
197static inline int bfin_pm_standby_setup(void)
198{
199 return 0;
200}
201
202static inline void bfin_pm_standby_restore(void)
203{
204}
205
186#endif /* CONFIG_PINCTRL */ 206#endif /* CONFIG_PINCTRL */
187 207
188#include <asm/irq.h> 208#include <asm/irq.h>
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index c5d31287de01..63da80bbadf6 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -15,6 +15,9 @@
15/* FIXME: consumer API required for gpio_set_value() etc, get rid of this */ 15/* FIXME: consumer API required for gpio_set_value() etc, get rid of this */
16#include <linux/gpio.h> 16#include <linux/gpio.h>
17#include <linux/irq.h> 17#include <linux/irq.h>
18#include <asm/gpio.h>
19#include <asm/irq_handler.h>
20#include <asm/portmux.h>
18 21
19#if ANOMALY_05000311 || ANOMALY_05000323 22#if ANOMALY_05000311 || ANOMALY_05000323
20enum { 23enum {
diff --git a/arch/blackfin/kernel/debug-mmrs.c b/arch/blackfin/kernel/debug-mmrs.c
index f31ace221392..194773ce109e 100644
--- a/arch/blackfin/kernel/debug-mmrs.c
+++ b/arch/blackfin/kernel/debug-mmrs.c
@@ -10,7 +10,6 @@
10#include <linux/fs.h> 10#include <linux/fs.h>
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/gpio.h>
14 13
15#include <asm/blackfin.h> 14#include <asm/blackfin.h>
16#include <asm/gptimers.h> 15#include <asm/gptimers.h>
@@ -20,6 +19,7 @@
20#include <asm/bfin_serial.h> 19#include <asm/bfin_serial.h>
21#include <asm/bfin5xx_spi.h> 20#include <asm/bfin5xx_spi.h>
22#include <asm/bfin_twi.h> 21#include <asm/bfin_twi.h>
22#include <asm/gpio.h>
23 23
24/* Common code defines PORT_MUX on us, so redirect the MMR back locally */ 24/* Common code defines PORT_MUX on us, so redirect the MMR back locally */
25#ifdef BFIN_PORT_MUX 25#ifdef BFIN_PORT_MUX
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 13e94bf9d8ba..e81a5b7dabdc 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -18,7 +18,6 @@
18#include <linux/sched.h> 18#include <linux/sched.h>
19#include <linux/sched/debug.h> 19#include <linux/sched/debug.h>
20#include <linux/syscore_ops.h> 20#include <linux/syscore_ops.h>
21#include <linux/gpio.h>
22#include <asm/delay.h> 21#include <asm/delay.h>
23#ifdef CONFIG_IPIPE 22#ifdef CONFIG_IPIPE
24#include <linux/ipipe.h> 23#include <linux/ipipe.h>
@@ -28,6 +27,7 @@
28#include <asm/irq_handler.h> 27#include <asm/irq_handler.h>
29#include <asm/dpmc.h> 28#include <asm/dpmc.h>
30#include <asm/traps.h> 29#include <asm/traps.h>
30#include <asm/gpio.h>
31 31
32/* 32/*
33 * NOTES: 33 * NOTES:
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index 5ece38a5b758..f57b5fe5355e 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -15,12 +15,12 @@
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/irq.h> 16#include <linux/irq.h>
17#include <linux/delay.h> 17#include <linux/delay.h>
18#include <linux/gpio.h>
19 18
20#include <asm/cplb.h> 19#include <asm/cplb.h>
21#include <asm/dma.h> 20#include <asm/dma.h>
22#include <asm/dpmc.h> 21#include <asm/dpmc.h>
23#include <asm/pm.h> 22#include <asm/pm.h>
23#include <asm/gpio.h>
24 24
25#ifdef CONFIG_BF60x 25#ifdef CONFIG_BF60x
26struct bfin_cpu_pm_fns *bfin_cpu_pm; 26struct bfin_cpu_pm_fns *bfin_cpu_pm;
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 29fc15423299..d6a8e851ad13 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -834,15 +834,6 @@ config GPIO_PCF857X
834 This driver provides an in-kernel interface to those GPIOs using 834 This driver provides an in-kernel interface to those GPIOs using
835 platform-neutral GPIO calls. 835 platform-neutral GPIO calls.
836 836
837config GPIO_SX150X
838 bool "Semtech SX150x I2C GPIO expander (deprecated)"
839 depends on PINCTRL && I2C=y
840 select PINCTRL_SX150X
841 default n
842 help
843 Say yes here to provide support for Semtech SX150x-series I2C
844 GPIO expanders. The GPIO driver was replaced by a Pinctrl version.
845
846config GPIO_TPIC2810 837config GPIO_TPIC2810
847 tristate "TPIC2810 8-Bit I2C GPO expander" 838 tristate "TPIC2810 8-Bit I2C GPO expander"
848 help 839 help
diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c
index 8781817d9003..6b3ca6601af2 100644
--- a/drivers/gpio/gpio-aspeed.c
+++ b/drivers/gpio/gpio-aspeed.c
@@ -539,12 +539,12 @@ static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset)
539 if (!have_gpio(gpiochip_get_data(chip), offset)) 539 if (!have_gpio(gpiochip_get_data(chip), offset))
540 return -ENODEV; 540 return -ENODEV;
541 541
542 return pinctrl_request_gpio(chip->base + offset); 542 return pinctrl_gpio_request(chip->base + offset);
543} 543}
544 544
545static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset) 545static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset)
546{ 546{
547 pinctrl_free_gpio(chip->base + offset); 547 pinctrl_gpio_free(chip->base + offset);
548} 548}
549 549
550static inline void __iomem *bank_debounce_reg(struct aspeed_gpio *gpio, 550static inline void __iomem *bank_debounce_reg(struct aspeed_gpio *gpio,
diff --git a/drivers/gpio/gpio-em.c b/drivers/gpio/gpio-em.c
index 8d32ccc980d9..b86e09e1b13b 100644
--- a/drivers/gpio/gpio-em.c
+++ b/drivers/gpio/gpio-em.c
@@ -239,12 +239,12 @@ static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
239 239
240static int em_gio_request(struct gpio_chip *chip, unsigned offset) 240static int em_gio_request(struct gpio_chip *chip, unsigned offset)
241{ 241{
242 return pinctrl_request_gpio(chip->base + offset); 242 return pinctrl_gpio_request(chip->base + offset);
243} 243}
244 244
245static void em_gio_free(struct gpio_chip *chip, unsigned offset) 245static void em_gio_free(struct gpio_chip *chip, unsigned offset)
246{ 246{
247 pinctrl_free_gpio(chip->base + offset); 247 pinctrl_gpio_free(chip->base + offset);
248 248
249 /* Set the GPIO as an input to ensure that the next GPIO request won't 249 /* Set the GPIO as an input to ensure that the next GPIO request won't
250 * drive the GPIO pin as an output. 250 * drive the GPIO pin as an output.
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 6029899789f3..f480fb896963 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -330,16 +330,6 @@ static int pxa_gpio_of_xlate(struct gpio_chip *gc,
330} 330}
331#endif 331#endif
332 332
333static int pxa_gpio_request(struct gpio_chip *chip, unsigned int offset)
334{
335 return pinctrl_request_gpio(chip->base + offset);
336}
337
338static void pxa_gpio_free(struct gpio_chip *chip, unsigned int offset)
339{
340 pinctrl_free_gpio(chip->base + offset);
341}
342
343static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio, 333static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio,
344 struct device_node *np, void __iomem *regbase) 334 struct device_node *np, void __iomem *regbase)
345{ 335{
@@ -358,8 +348,8 @@ static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio,
358 pchip->chip.set = pxa_gpio_set; 348 pchip->chip.set = pxa_gpio_set;
359 pchip->chip.to_irq = pxa_gpio_to_irq; 349 pchip->chip.to_irq = pxa_gpio_to_irq;
360 pchip->chip.ngpio = ngpio; 350 pchip->chip.ngpio = ngpio;
361 pchip->chip.request = pxa_gpio_request; 351 pchip->chip.request = gpiochip_generic_request;
362 pchip->chip.free = pxa_gpio_free; 352 pchip->chip.free = gpiochip_generic_free;
363#ifdef CONFIG_OF_GPIO 353#ifdef CONFIG_OF_GPIO
364 pchip->chip.of_node = np; 354 pchip->chip.of_node = np;
365 pchip->chip.of_xlate = pxa_gpio_of_xlate; 355 pchip->chip.of_xlate = pxa_gpio_of_xlate;
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index 0ea998a3e357..e76de57dd617 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -250,7 +250,7 @@ static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
250 if (error < 0) 250 if (error < 0)
251 return error; 251 return error;
252 252
253 error = pinctrl_request_gpio(chip->base + offset); 253 error = pinctrl_gpio_request(chip->base + offset);
254 if (error) 254 if (error)
255 pm_runtime_put(&p->pdev->dev); 255 pm_runtime_put(&p->pdev->dev);
256 256
@@ -261,7 +261,7 @@ static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
261{ 261{
262 struct gpio_rcar_priv *p = gpiochip_get_data(chip); 262 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
263 263
264 pinctrl_free_gpio(chip->base + offset); 264 pinctrl_gpio_free(chip->base + offset);
265 265
266 /* 266 /*
267 * Set the GPIO as an input to ensure that the next GPIO request won't 267 * Set the GPIO as an input to ensure that the next GPIO request won't
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index fbaf974277df..8db47f671708 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -141,14 +141,14 @@ static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
141 141
142static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset) 142static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset)
143{ 143{
144 return pinctrl_request_gpio(offset); 144 return pinctrl_gpio_request(offset);
145} 145}
146 146
147static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset) 147static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
148{ 148{
149 struct tegra_gpio_info *tgi = gpiochip_get_data(chip); 149 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
150 150
151 pinctrl_free_gpio(offset); 151 pinctrl_gpio_free(offset);
152 tegra_gpio_disable(tgi, offset); 152 tegra_gpio_disable(tgi, offset);
153} 153}
154 154
diff --git a/drivers/gpio/gpio-tz1090.c b/drivers/gpio/gpio-tz1090.c
index 22c5be65051f..0bb9bb583889 100644
--- a/drivers/gpio/gpio-tz1090.c
+++ b/drivers/gpio/gpio-tz1090.c
@@ -232,7 +232,7 @@ static int tz1090_gpio_request(struct gpio_chip *chip, unsigned int offset)
232 struct tz1090_gpio_bank *bank = gpiochip_get_data(chip); 232 struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
233 int ret; 233 int ret;
234 234
235 ret = pinctrl_request_gpio(chip->base + offset); 235 ret = pinctrl_gpio_request(chip->base + offset);
236 if (ret) 236 if (ret)
237 return ret; 237 return ret;
238 238
@@ -246,7 +246,7 @@ static void tz1090_gpio_free(struct gpio_chip *chip, unsigned int offset)
246{ 246{
247 struct tz1090_gpio_bank *bank = gpiochip_get_data(chip); 247 struct tz1090_gpio_bank *bank = gpiochip_get_data(chip);
248 248
249 pinctrl_free_gpio(chip->base + offset); 249 pinctrl_gpio_free(chip->base + offset);
250 250
251 tz1090_gpio_clear_bit(bank, REG_GPIO_BIT_EN, offset); 251 tz1090_gpio_clear_bit(bank, REG_GPIO_BIT_EN, offset);
252} 252}
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 641a5eb552cb..aad84a6306c4 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1962,7 +1962,7 @@ static inline void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip)
1962 */ 1962 */
1963int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset) 1963int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset)
1964{ 1964{
1965 return pinctrl_request_gpio(chip->gpiodev->base + offset); 1965 return pinctrl_gpio_request(chip->gpiodev->base + offset);
1966} 1966}
1967EXPORT_SYMBOL_GPL(gpiochip_generic_request); 1967EXPORT_SYMBOL_GPL(gpiochip_generic_request);
1968 1968
@@ -1973,7 +1973,7 @@ EXPORT_SYMBOL_GPL(gpiochip_generic_request);
1973 */ 1973 */
1974void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset) 1974void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset)
1975{ 1975{
1976 pinctrl_free_gpio(chip->gpiodev->base + offset); 1976 pinctrl_gpio_free(chip->gpiodev->base + offset);
1977} 1977}
1978EXPORT_SYMBOL_GPL(gpiochip_generic_free); 1978EXPORT_SYMBOL_GPL(gpiochip_generic_free);
1979 1979
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 82cd8b08d71f..4571cc098b76 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -2,11 +2,10 @@
2# PINCTRL infrastructure and drivers 2# PINCTRL infrastructure and drivers
3# 3#
4 4
5config PINCTRL 5menuconfig PINCTRL
6 bool 6 bool "Pin controllers"
7 7
8menu "Pin controllers" 8if PINCTRL
9 depends on PINCTRL
10 9
11config GENERIC_PINCTRL_GROUPS 10config GENERIC_PINCTRL_GROUPS
12 bool 11 bool
@@ -33,7 +32,8 @@ config DEBUG_PINCTRL
33 32
34config PINCTRL_ADI2 33config PINCTRL_ADI2
35 bool "ADI pin controller driver" 34 bool "ADI pin controller driver"
36 depends on BLACKFIN 35 depends on (BF54x || BF60x)
36 depends on !GPIO_ADI
37 select PINMUX 37 select PINMUX
38 select IRQ_DOMAIN 38 select IRQ_DOMAIN
39 help 39 help
@@ -98,7 +98,8 @@ config PINCTRL_AT91PIO4
98 98
99config PINCTRL_AMD 99config PINCTRL_AMD
100 tristate "AMD GPIO pin control" 100 tristate "AMD GPIO pin control"
101 depends on GPIOLIB 101 depends on HAS_IOMEM
102 select GPIOLIB
102 select GPIOLIB_IRQCHIP 103 select GPIOLIB_IRQCHIP
103 select PINMUX 104 select PINMUX
104 select PINCONF 105 select PINCONF
@@ -152,12 +153,14 @@ config PINCTRL_GEMINI
152 depends on ARCH_GEMINI 153 depends on ARCH_GEMINI
153 default ARCH_GEMINI 154 default ARCH_GEMINI
154 select PINMUX 155 select PINMUX
156 select GENERIC_PINCONF
155 select MFD_SYSCON 157 select MFD_SYSCON
156 158
157config PINCTRL_MCP23S08 159config PINCTRL_MCP23S08
158 tristate "Microchip MCP23xxx I/O expander" 160 tristate "Microchip MCP23xxx I/O expander"
159 depends on SPI_MASTER || I2C 161 depends on SPI_MASTER || I2C
160 depends on I2C || I2C=n 162 depends on I2C || I2C=n
163 select GPIOLIB
161 select GPIOLIB_IRQCHIP 164 select GPIOLIB_IRQCHIP
162 select REGMAP_I2C if I2C 165 select REGMAP_I2C if I2C
163 select REGMAP_SPI if SPI_MASTER 166 select REGMAP_SPI if SPI_MASTER
@@ -168,16 +171,6 @@ config PINCTRL_MCP23S08
168 This provides a GPIO interface supporting inputs and outputs. 171 This provides a GPIO interface supporting inputs and outputs.
169 The I2C versions of the chips can be used as interrupt-controller. 172 The I2C versions of the chips can be used as interrupt-controller.
170 173
171config PINCTRL_MESON
172 bool
173 depends on OF
174 select PINMUX
175 select PINCONF
176 select GENERIC_PINCONF
177 select GPIOLIB
178 select OF_GPIO
179 select REGMAP_MMIO
180
181config PINCTRL_OXNAS 174config PINCTRL_OXNAS
182 bool 175 bool
183 depends on OF 176 depends on OF
@@ -210,6 +203,7 @@ config PINCTRL_RZA1
210config PINCTRL_SINGLE 203config PINCTRL_SINGLE
211 tristate "One-register-per-pin type device tree based pinctrl driver" 204 tristate "One-register-per-pin type device tree based pinctrl driver"
212 depends on OF 205 depends on OF
206 depends on HAS_IOMEM
213 select GENERIC_PINCTRL_GROUPS 207 select GENERIC_PINCTRL_GROUPS
214 select GENERIC_PINMUX_FUNCTIONS 208 select GENERIC_PINMUX_FUNCTIONS
215 select GENERIC_PINCONF 209 select GENERIC_PINCONF
@@ -226,10 +220,11 @@ config PINCTRL_SIRF
226 220
227config PINCTRL_SX150X 221config PINCTRL_SX150X
228 bool "Semtech SX150x I2C GPIO expander pinctrl driver" 222 bool "Semtech SX150x I2C GPIO expander pinctrl driver"
229 depends on GPIOLIB && I2C=y 223 depends on I2C=y
230 select PINMUX 224 select PINMUX
231 select PINCONF 225 select PINCONF
232 select GENERIC_PINCONF 226 select GENERIC_PINCONF
227 select GPIOLIB
233 select GPIOLIB_IRQCHIP 228 select GPIOLIB_IRQCHIP
234 select REGMAP 229 select REGMAP
235 help 230 help
@@ -369,6 +364,7 @@ source "drivers/pinctrl/uniphier/Kconfig"
369source "drivers/pinctrl/vt8500/Kconfig" 364source "drivers/pinctrl/vt8500/Kconfig"
370source "drivers/pinctrl/mediatek/Kconfig" 365source "drivers/pinctrl/mediatek/Kconfig"
371source "drivers/pinctrl/zte/Kconfig" 366source "drivers/pinctrl/zte/Kconfig"
367source "drivers/pinctrl/meson/Kconfig"
372 368
373config PINCTRL_XWAY 369config PINCTRL_XWAY
374 bool 370 bool
@@ -380,4 +376,4 @@ config PINCTRL_TB10X
380 depends on OF && ARC_PLAT_TB10X 376 depends on OF && ARC_PLAT_TB10X
381 select GPIOLIB 377 select GPIOLIB
382 378
383endmenu 379endif
diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
index b93f62dc8733..b70058caee50 100644
--- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
+++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
@@ -311,7 +311,7 @@ static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset)
311 if (!chip->pinmux_is_supported) 311 if (!chip->pinmux_is_supported)
312 return 0; 312 return 0;
313 313
314 return pinctrl_request_gpio(gpio); 314 return pinctrl_gpio_request(gpio);
315} 315}
316 316
317static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset) 317static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset)
@@ -322,7 +322,7 @@ static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset)
322 if (!chip->pinmux_is_supported) 322 if (!chip->pinmux_is_supported)
323 return; 323 return;
324 324
325 pinctrl_free_gpio(gpio); 325 pinctrl_gpio_free(gpio);
326} 326}
327 327
328static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) 328static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
index 1cfe45fd391f..e67ae52023ad 100644
--- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
+++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
@@ -275,23 +275,6 @@ static struct irq_chip nsp_gpio_irq_chip = {
275 .irq_set_type = nsp_gpio_irq_set_type, 275 .irq_set_type = nsp_gpio_irq_set_type,
276}; 276};
277 277
278/*
279 * Request the nsp IOMUX pinmux controller to mux individual pins to GPIO
280 */
281static int nsp_gpio_request(struct gpio_chip *gc, unsigned offset)
282{
283 unsigned gpio = gc->base + offset;
284
285 return pinctrl_request_gpio(gpio);
286}
287
288static void nsp_gpio_free(struct gpio_chip *gc, unsigned offset)
289{
290 unsigned gpio = gc->base + offset;
291
292 pinctrl_free_gpio(gpio);
293}
294
295static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) 278static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
296{ 279{
297 struct nsp_gpio *chip = gpiochip_get_data(gc); 280 struct nsp_gpio *chip = gpiochip_get_data(gc);
@@ -670,8 +653,8 @@ static int nsp_gpio_probe(struct platform_device *pdev)
670 gc->label = dev_name(dev); 653 gc->label = dev_name(dev);
671 gc->parent = dev; 654 gc->parent = dev;
672 gc->of_node = dev->of_node; 655 gc->of_node = dev->of_node;
673 gc->request = nsp_gpio_request; 656 gc->request = gpiochip_generic_request;
674 gc->free = nsp_gpio_free; 657 gc->free = gpiochip_generic_free;
675 gc->direction_input = nsp_gpio_direction_input; 658 gc->direction_input = nsp_gpio_direction_input;
676 gc->direction_output = nsp_gpio_direction_output; 659 gc->direction_output = nsp_gpio_direction_output;
677 gc->set = nsp_gpio_set; 660 gc->set = nsp_gpio_set;
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 56fbe4c3e800..4c8d5b23e4d0 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -733,14 +733,14 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
733} 733}
734 734
735/** 735/**
736 * pinctrl_request_gpio() - request a single pin to be used as GPIO 736 * pinctrl_gpio_request() - request a single pin to be used as GPIO
737 * @gpio: the GPIO pin number from the GPIO subsystem number space 737 * @gpio: the GPIO pin number from the GPIO subsystem number space
738 * 738 *
739 * This function should *ONLY* be used from gpiolib-based GPIO drivers, 739 * This function should *ONLY* be used from gpiolib-based GPIO drivers,
740 * as part of their gpio_request() semantics, platforms and individual drivers 740 * as part of their gpio_request() semantics, platforms and individual drivers
741 * shall *NOT* request GPIO pins to be muxed in. 741 * shall *NOT* request GPIO pins to be muxed in.
742 */ 742 */
743int pinctrl_request_gpio(unsigned gpio) 743int pinctrl_gpio_request(unsigned gpio)
744{ 744{
745 struct pinctrl_dev *pctldev; 745 struct pinctrl_dev *pctldev;
746 struct pinctrl_gpio_range *range; 746 struct pinctrl_gpio_range *range;
@@ -765,17 +765,17 @@ int pinctrl_request_gpio(unsigned gpio)
765 765
766 return ret; 766 return ret;
767} 767}
768EXPORT_SYMBOL_GPL(pinctrl_request_gpio); 768EXPORT_SYMBOL_GPL(pinctrl_gpio_request);
769 769
770/** 770/**
771 * pinctrl_free_gpio() - free control on a single pin, currently used as GPIO 771 * pinctrl_gpio_free() - free control on a single pin, currently used as GPIO
772 * @gpio: the GPIO pin number from the GPIO subsystem number space 772 * @gpio: the GPIO pin number from the GPIO subsystem number space
773 * 773 *
774 * This function should *ONLY* be used from gpiolib-based GPIO drivers, 774 * This function should *ONLY* be used from gpiolib-based GPIO drivers,
775 * as part of their gpio_free() semantics, platforms and individual drivers 775 * as part of their gpio_free() semantics, platforms and individual drivers
776 * shall *NOT* request GPIO pins to be muxed out. 776 * shall *NOT* request GPIO pins to be muxed out.
777 */ 777 */
778void pinctrl_free_gpio(unsigned gpio) 778void pinctrl_gpio_free(unsigned gpio)
779{ 779{
780 struct pinctrl_dev *pctldev; 780 struct pinctrl_dev *pctldev;
781 struct pinctrl_gpio_range *range; 781 struct pinctrl_gpio_range *range;
@@ -795,7 +795,7 @@ void pinctrl_free_gpio(unsigned gpio)
795 795
796 mutex_unlock(&pctldev->mutex); 796 mutex_unlock(&pctldev->mutex);
797} 797}
798EXPORT_SYMBOL_GPL(pinctrl_free_gpio); 798EXPORT_SYMBOL_GPL(pinctrl_gpio_free);
799 799
800static int pinctrl_gpio_direction(unsigned gpio, bool input) 800static int pinctrl_gpio_direction(unsigned gpio, bool input)
801{ 801{
diff --git a/drivers/pinctrl/core.h b/drivers/pinctrl/core.h
index 7880c3adc450..8cf2eba17c8c 100644
--- a/drivers/pinctrl/core.h
+++ b/drivers/pinctrl/core.h
@@ -154,7 +154,7 @@ struct pinctrl_setting {
154 * or pin, and each of these will increment the @usecount. 154 * or pin, and each of these will increment the @usecount.
155 * @mux_owner: The name of device that called pinctrl_get(). 155 * @mux_owner: The name of device that called pinctrl_get().
156 * @mux_setting: The most recent selected mux setting for this pin, if any. 156 * @mux_setting: The most recent selected mux setting for this pin, if any.
157 * @gpio_owner: If pinctrl_request_gpio() was called for this pin, this is 157 * @gpio_owner: If pinctrl_gpio_request() was called for this pin, this is
158 * the name of the GPIO that "owns" this pin. 158 * the name of the GPIO that "owns" this pin.
159 */ 159 */
160struct pin_desc { 160struct pin_desc {
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index f30720a752f3..4aea1b8504f7 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -5,7 +5,8 @@ if (X86 || COMPILE_TEST)
5 5
6config PINCTRL_BAYTRAIL 6config PINCTRL_BAYTRAIL
7 bool "Intel Baytrail GPIO pin control" 7 bool "Intel Baytrail GPIO pin control"
8 depends on GPIOLIB && ACPI 8 depends on ACPI
9 select GPIOLIB
9 select GPIOLIB_IRQCHIP 10 select GPIOLIB_IRQCHIP
10 select PINMUX 11 select PINMUX
11 select PINCONF 12 select PINCONF
@@ -65,6 +66,14 @@ config PINCTRL_CANNONLAKE
65 This pinctrl driver provides an interface that allows configuring 66 This pinctrl driver provides an interface that allows configuring
66 of Intel Cannon Lake PCH pins and using them as GPIOs. 67 of Intel Cannon Lake PCH pins and using them as GPIOs.
67 68
69config PINCTRL_CEDARFORK
70 tristate "Intel Cedar Fork pinctrl and GPIO driver"
71 depends on ACPI
72 select PINCTRL_INTEL
73 help
74 This pinctrl driver provides an interface that allows configuring
75 of Intel Cedar Fork PCH pins and using them as GPIOs.
76
68config PINCTRL_DENVERTON 77config PINCTRL_DENVERTON
69 tristate "Intel Denverton pinctrl and GPIO driver" 78 tristate "Intel Denverton pinctrl and GPIO driver"
70 depends on ACPI 79 depends on ACPI
diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile
index 624d367caa09..fadfe3ea2b04 100644
--- a/drivers/pinctrl/intel/Makefile
+++ b/drivers/pinctrl/intel/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o
7obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o 7obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o
8obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o 8obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o
9obj-$(CONFIG_PINCTRL_CANNONLAKE) += pinctrl-cannonlake.o 9obj-$(CONFIG_PINCTRL_CANNONLAKE) += pinctrl-cannonlake.o
10obj-$(CONFIG_PINCTRL_CEDARFORK) += pinctrl-cedarfork.o
10obj-$(CONFIG_PINCTRL_DENVERTON) += pinctrl-denverton.o 11obj-$(CONFIG_PINCTRL_DENVERTON) += pinctrl-denverton.o
11obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o 12obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o
12obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o 13obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o
diff --git a/drivers/pinctrl/intel/pinctrl-cedarfork.c b/drivers/pinctrl/intel/pinctrl-cedarfork.c
new file mode 100644
index 000000000000..59216b0533d9
--- /dev/null
+++ b/drivers/pinctrl/intel/pinctrl-cedarfork.c
@@ -0,0 +1,375 @@
1/*
2 * Intel Cedar Fork PCH pinctrl/GPIO driver
3 *
4 * Copyright (C) 2017, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/acpi.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/pm.h>
16#include <linux/pinctrl/pinctrl.h>
17
18#include "pinctrl-intel.h"
19
20#define CDF_PAD_OWN 0x020
21#define CDF_PADCFGLOCK 0x0c0
22#define CDF_HOSTSW_OWN 0x120
23#define CDF_GPI_IS 0x200
24#define CDF_GPI_IE 0x230
25
26#define CDF_GPP(r, s, e) \
27 { \
28 .reg_num = (r), \
29 .base = (s), \
30 .size = ((e) - (s) + 1), \
31 }
32
33#define CDF_COMMUNITY(b, s, e, g) \
34 { \
35 .barno = (b), \
36 .padown_offset = CDF_PAD_OWN, \
37 .padcfglock_offset = CDF_PADCFGLOCK, \
38 .hostown_offset = CDF_HOSTSW_OWN, \
39 .is_offset = CDF_GPI_IS, \
40 .ie_offset = CDF_GPI_IE, \
41 .pin_base = (s), \
42 .npins = ((e) - (s) + 1), \
43 .gpps = (g), \
44 .ngpps = ARRAY_SIZE(g), \
45 }
46
47/* Cedar Fork PCH */
48static const struct pinctrl_pin_desc cdf_pins[] = {
49 /* WEST2 */
50 PINCTRL_PIN(0, "GBE_SDP_TIMESYNC0_S2N"),
51 PINCTRL_PIN(1, "GBE_SDP_TIMESYNC1_S2N"),
52 PINCTRL_PIN(2, "GBE_SDP_TIMESYNC2_S2N"),
53 PINCTRL_PIN(3, "GBE_SDP_TIMESYNC3_S2N"),
54 PINCTRL_PIN(4, "GBE0_I2C_CLK"),
55 PINCTRL_PIN(5, "GBE0_I2C_DATA"),
56 PINCTRL_PIN(6, "GBE1_I2C_CLK"),
57 PINCTRL_PIN(7, "GBE1_I2C_DATA"),
58 PINCTRL_PIN(8, "GBE2_I2C_CLK"),
59 PINCTRL_PIN(9, "GBE2_I2C_DATA"),
60 PINCTRL_PIN(10, "GBE3_I2C_CLK"),
61 PINCTRL_PIN(11, "GBE3_I2C_DATA"),
62 PINCTRL_PIN(12, "GBE0_LED0"),
63 PINCTRL_PIN(13, "GBE0_LED1"),
64 PINCTRL_PIN(14, "GBE0_LED2"),
65 PINCTRL_PIN(15, "GBE1_LED0"),
66 PINCTRL_PIN(16, "GBE1_LED1"),
67 PINCTRL_PIN(17, "GBE1_LED2"),
68 PINCTRL_PIN(18, "GBE2_LED0"),
69 PINCTRL_PIN(19, "GBE2_LED1"),
70 PINCTRL_PIN(20, "GBE2_LED2"),
71 PINCTRL_PIN(21, "GBE3_LED0"),
72 PINCTRL_PIN(22, "GBE3_LED1"),
73 PINCTRL_PIN(23, "GBE3_LED2"),
74 /* WEST3 */
75 PINCTRL_PIN(24, "NCSI_RXD0"),
76 PINCTRL_PIN(25, "NCSI_CLK_IN"),
77 PINCTRL_PIN(26, "NCSI_RXD1"),
78 PINCTRL_PIN(27, "NCSI_CRS_DV"),
79 PINCTRL_PIN(28, "NCSI_ARB_IN"),
80 PINCTRL_PIN(29, "NCSI_TX_EN"),
81 PINCTRL_PIN(30, "NCSI_TXD0"),
82 PINCTRL_PIN(31, "NCSI_TXD1"),
83 PINCTRL_PIN(32, "NCSI_ARB_OUT"),
84 PINCTRL_PIN(33, "GBE_SMB_CLK"),
85 PINCTRL_PIN(34, "GBE_SMB_DATA"),
86 PINCTRL_PIN(35, "GBE_SMB_ALRT_N"),
87 PINCTRL_PIN(36, "THERMTRIP_N"),
88 PINCTRL_PIN(37, "PCHHOT_N"),
89 PINCTRL_PIN(38, "ERROR0_N"),
90 PINCTRL_PIN(39, "ERROR1_N"),
91 PINCTRL_PIN(40, "ERROR2_N"),
92 PINCTRL_PIN(41, "MSMI_N"),
93 PINCTRL_PIN(42, "CATERR_N"),
94 PINCTRL_PIN(43, "MEMTRIP_N"),
95 PINCTRL_PIN(44, "UART0_RXD"),
96 PINCTRL_PIN(45, "UART0_TXD"),
97 PINCTRL_PIN(46, "UART1_RXD"),
98 PINCTRL_PIN(47, "UART1_TXD"),
99 /* WEST01 */
100 PINCTRL_PIN(48, "GBE_GPIO13"),
101 PINCTRL_PIN(49, "AUX_PWR"),
102 PINCTRL_PIN(50, "CPU_GP_2"),
103 PINCTRL_PIN(51, "CPU_GP_3"),
104 PINCTRL_PIN(52, "FAN_PWM_0"),
105 PINCTRL_PIN(53, "FAN_PWM_1"),
106 PINCTRL_PIN(54, "FAN_PWM_2"),
107 PINCTRL_PIN(55, "FAN_PWM_3"),
108 PINCTRL_PIN(56, "FAN_TACH_0"),
109 PINCTRL_PIN(57, "FAN_TACH_1"),
110 PINCTRL_PIN(58, "FAN_TACH_2"),
111 PINCTRL_PIN(59, "FAN_TACH_3"),
112 PINCTRL_PIN(60, "ME_SMB0_CLK"),
113 PINCTRL_PIN(61, "ME_SMB0_DATA"),
114 PINCTRL_PIN(62, "ME_SMB0_ALRT_N"),
115 PINCTRL_PIN(63, "ME_SMB1_CLK"),
116 PINCTRL_PIN(64, "ME_SMB1_DATA"),
117 PINCTRL_PIN(65, "ME_SMB1_ALRT_N"),
118 PINCTRL_PIN(66, "ME_SMB2_CLK"),
119 PINCTRL_PIN(67, "ME_SMB2_DATA"),
120 PINCTRL_PIN(68, "ME_SMB2_ALRT_N"),
121 PINCTRL_PIN(69, "GBE_MNG_I2C_CLK"),
122 PINCTRL_PIN(70, "GBE_MNG_I2C_DATA"),
123 /* WEST5 */
124 PINCTRL_PIN(71, "IE_UART_RXD"),
125 PINCTRL_PIN(72, "IE_UART_TXD"),
126 PINCTRL_PIN(73, "VPP_SMB_CLK"),
127 PINCTRL_PIN(74, "VPP_SMB_DATA"),
128 PINCTRL_PIN(75, "VPP_SMB_ALRT_N"),
129 PINCTRL_PIN(76, "PCIE_CLKREQ0_N"),
130 PINCTRL_PIN(77, "PCIE_CLKREQ1_N"),
131 PINCTRL_PIN(78, "PCIE_CLKREQ2_N"),
132 PINCTRL_PIN(79, "PCIE_CLKREQ3_N"),
133 PINCTRL_PIN(80, "PCIE_CLKREQ4_N"),
134 PINCTRL_PIN(81, "PCIE_CLKREQ5_N"),
135 PINCTRL_PIN(82, "PCIE_CLKREQ6_N"),
136 PINCTRL_PIN(83, "PCIE_CLKREQ7_N"),
137 PINCTRL_PIN(84, "PCIE_CLKREQ8_N"),
138 PINCTRL_PIN(85, "PCIE_CLKREQ9_N"),
139 PINCTRL_PIN(86, "FLEX_CLK_SE0"),
140 PINCTRL_PIN(87, "FLEX_CLK_SE1"),
141 PINCTRL_PIN(88, "FLEX_CLK1_50"),
142 PINCTRL_PIN(89, "FLEX_CLK2_50"),
143 PINCTRL_PIN(90, "FLEX_CLK_125"),
144 /* WESTC */
145 PINCTRL_PIN(91, "TCK_PCH"),
146 PINCTRL_PIN(92, "JTAGX_PCH"),
147 PINCTRL_PIN(93, "TRST_N_PCH"),
148 PINCTRL_PIN(94, "TMS_PCH"),
149 PINCTRL_PIN(95, "TDI_PCH"),
150 PINCTRL_PIN(96, "TDO_PCH"),
151 /* WESTC_DFX */
152 PINCTRL_PIN(97, "CX_PRDY_N"),
153 PINCTRL_PIN(98, "CX_PREQ_N"),
154 PINCTRL_PIN(99, "CPU_FBREAK_OUT_N"),
155 PINCTRL_PIN(100, "TRIGGER0_N"),
156 PINCTRL_PIN(101, "TRIGGER1_N"),
157 /* WESTA */
158 PINCTRL_PIN(102, "DBG_PTI_CLK0"),
159 PINCTRL_PIN(103, "DBG_PTI_CLK3"),
160 PINCTRL_PIN(104, "DBG_PTI_DATA0"),
161 PINCTRL_PIN(105, "DBG_PTI_DATA1"),
162 PINCTRL_PIN(106, "DBG_PTI_DATA2"),
163 PINCTRL_PIN(107, "DBG_PTI_DATA3"),
164 PINCTRL_PIN(108, "DBG_PTI_DATA4"),
165 PINCTRL_PIN(109, "DBG_PTI_DATA5"),
166 PINCTRL_PIN(110, "DBG_PTI_DATA6"),
167 PINCTRL_PIN(111, "DBG_PTI_DATA7"),
168 /* WESTB */
169 PINCTRL_PIN(112, "DBG_PTI_DATA8"),
170 PINCTRL_PIN(113, "DBG_PTI_DATA9"),
171 PINCTRL_PIN(114, "DBG_PTI_DATA10"),
172 PINCTRL_PIN(115, "DBG_PTI_DATA11"),
173 PINCTRL_PIN(116, "DBG_PTI_DATA12"),
174 PINCTRL_PIN(117, "DBG_PTI_DATA13"),
175 PINCTRL_PIN(118, "DBG_PTI_DATA14"),
176 PINCTRL_PIN(119, "DBG_PTI_DATA15"),
177 PINCTRL_PIN(120, "DBG_SPARE0"),
178 PINCTRL_PIN(121, "DBG_SPARE1"),
179 PINCTRL_PIN(122, "DBG_SPARE2"),
180 PINCTRL_PIN(123, "DBG_SPARE3"),
181 /* WESTD */
182 PINCTRL_PIN(124, "CPU_PWR_GOOD"),
183 PINCTRL_PIN(125, "PLTRST_CPU_N"),
184 PINCTRL_PIN(126, "NAC_RESET_NAC_N"),
185 PINCTRL_PIN(127, "PCH_SBLINK_RX"),
186 PINCTRL_PIN(128, "PCH_SBLINK_TX"),
187 PINCTRL_PIN(129, "PMSYNC_CLK"),
188 PINCTRL_PIN(130, "CPU_ERR0_N"),
189 PINCTRL_PIN(131, "CPU_ERR1_N"),
190 PINCTRL_PIN(132, "CPU_ERR2_N"),
191 PINCTRL_PIN(133, "CPU_THERMTRIP_N"),
192 PINCTRL_PIN(134, "CPU_MSMI_N"),
193 PINCTRL_PIN(135, "CPU_CATERR_N"),
194 PINCTRL_PIN(136, "CPU_MEMTRIP_N"),
195 PINCTRL_PIN(137, "NAC_GR_N"),
196 PINCTRL_PIN(138, "NAC_XTAL_VALID"),
197 PINCTRL_PIN(139, "NAC_WAKE_N"),
198 PINCTRL_PIN(140, "NAC_SBLINK_CLK_S2N"),
199 PINCTRL_PIN(141, "NAC_SBLINK_N2S"),
200 PINCTRL_PIN(142, "NAC_SBLINK_S2N"),
201 PINCTRL_PIN(143, "NAC_SBLINK_CLK_N2S"),
202 /* WESTD_PECI */
203 PINCTRL_PIN(144, "ME_PECI"),
204 /* WESTF */
205 PINCTRL_PIN(145, "NAC_RMII_CLK"),
206 PINCTRL_PIN(146, "NAC_RGMII_CLK"),
207 PINCTRL_PIN(147, "NAC_SPARE0"),
208 PINCTRL_PIN(148, "NAC_SPARE1"),
209 PINCTRL_PIN(149, "NAC_SPARE2"),
210 PINCTRL_PIN(150, "NAC_INIT_SX_WAKE_N"),
211 PINCTRL_PIN(151, "NAC_GBE_GPIO0_S2N"),
212 PINCTRL_PIN(152, "NAC_GBE_GPIO1_S2N"),
213 PINCTRL_PIN(153, "NAC_GBE_GPIO2_S2N"),
214 PINCTRL_PIN(154, "NAC_GBE_GPIO3_S2N"),
215 PINCTRL_PIN(155, "NAC_NCSI_RXD0"),
216 PINCTRL_PIN(156, "NAC_NCSI_CLK_IN"),
217 PINCTRL_PIN(157, "NAC_NCSI_RXD1"),
218 PINCTRL_PIN(158, "NAC_NCSI_CRS_DV"),
219 PINCTRL_PIN(159, "NAC_NCSI_ARB_IN"),
220 PINCTRL_PIN(160, "NAC_NCSI_TX_EN"),
221 PINCTRL_PIN(161, "NAC_NCSI_TXD0"),
222 PINCTRL_PIN(162, "NAC_NCSI_TXD1"),
223 PINCTRL_PIN(163, "NAC_NCSI_ARB_OUT"),
224 PINCTRL_PIN(164, "NAC_NCSI_OE_N"),
225 PINCTRL_PIN(165, "NAC_GBE_SMB_CLK"),
226 PINCTRL_PIN(166, "NAC_GBE_SMB_DATA"),
227 PINCTRL_PIN(167, "NAC_GBE_SMB_ALRT_N"),
228 /* EAST2 */
229 PINCTRL_PIN(168, "USB_OC0_N"),
230 PINCTRL_PIN(169, "GBE_GPIO0"),
231 PINCTRL_PIN(170, "GBE_GPIO1"),
232 PINCTRL_PIN(171, "GBE_GPIO2"),
233 PINCTRL_PIN(172, "GBE_GPIO3"),
234 PINCTRL_PIN(173, "GBE_GPIO4"),
235 PINCTRL_PIN(174, "GBE_GPIO5"),
236 PINCTRL_PIN(175, "GBE_GPIO6"),
237 PINCTRL_PIN(176, "GBE_GPIO7"),
238 PINCTRL_PIN(177, "GBE_GPIO8"),
239 PINCTRL_PIN(178, "GBE_GPIO9"),
240 PINCTRL_PIN(179, "GBE_GPIO10"),
241 PINCTRL_PIN(180, "GBE_GPIO11"),
242 PINCTRL_PIN(181, "GBE_GPIO12"),
243 PINCTRL_PIN(182, "SATA0_LED_N"),
244 PINCTRL_PIN(183, "SATA1_LED_N"),
245 PINCTRL_PIN(184, "SATA_PDETECT0"),
246 PINCTRL_PIN(185, "SATA_PDETECT1"),
247 PINCTRL_PIN(186, "SATA0_SDOUT"),
248 PINCTRL_PIN(187, "SATA1_SDOUT"),
249 PINCTRL_PIN(188, "SATA2_LED_N"),
250 PINCTRL_PIN(189, "SATA_PDETECT2"),
251 PINCTRL_PIN(190, "SATA2_SDOUT"),
252 /* EAST3 */
253 PINCTRL_PIN(191, "ESPI_IO0"),
254 PINCTRL_PIN(192, "ESPI_IO1"),
255 PINCTRL_PIN(193, "ESPI_IO2"),
256 PINCTRL_PIN(194, "ESPI_IO3"),
257 PINCTRL_PIN(195, "ESPI_CLK"),
258 PINCTRL_PIN(196, "ESPI_RST_N"),
259 PINCTRL_PIN(197, "ESPI_CS0_N"),
260 PINCTRL_PIN(198, "ESPI_ALRT0_N"),
261 PINCTRL_PIN(199, "ESPI_CS1_N"),
262 PINCTRL_PIN(200, "ESPI_ALRT1_N"),
263 PINCTRL_PIN(201, "ESPI_CLK_LOOPBK"),
264 /* EAST0 */
265 PINCTRL_PIN(202, "SPI_CS0_N"),
266 PINCTRL_PIN(203, "SPI_CS1_N"),
267 PINCTRL_PIN(204, "SPI_MOSI_IO0"),
268 PINCTRL_PIN(205, "SPI_MISO_IO1"),
269 PINCTRL_PIN(206, "SPI_IO2"),
270 PINCTRL_PIN(207, "SPI_IO3"),
271 PINCTRL_PIN(208, "SPI_CLK"),
272 PINCTRL_PIN(209, "SPI_CLK_LOOPBK"),
273 PINCTRL_PIN(210, "SUSPWRDNACK"),
274 PINCTRL_PIN(211, "PMU_SUSCLK"),
275 PINCTRL_PIN(212, "ADR_COMPLETE"),
276 PINCTRL_PIN(213, "ADR_TRIGGER_N"),
277 PINCTRL_PIN(214, "PMU_SLP_S45_N"),
278 PINCTRL_PIN(215, "PMU_SLP_S3_N"),
279 PINCTRL_PIN(216, "PMU_WAKE_N"),
280 PINCTRL_PIN(217, "PMU_PWRBTN_N"),
281 PINCTRL_PIN(218, "PMU_RESETBUTTON_N"),
282 PINCTRL_PIN(219, "PMU_PLTRST_N"),
283 PINCTRL_PIN(220, "SUS_STAT_N"),
284 PINCTRL_PIN(221, "PMU_I2C_CLK"),
285 PINCTRL_PIN(222, "PMU_I2C_DATA"),
286 PINCTRL_PIN(223, "PECI_SMB_CLK"),
287 PINCTRL_PIN(224, "PECI_SMB_DATA"),
288 PINCTRL_PIN(225, "PECI_SMB_ALRT_N"),
289 /* EMMC */
290 PINCTRL_PIN(226, "EMMC_CMD"),
291 PINCTRL_PIN(227, "EMMC_STROBE"),
292 PINCTRL_PIN(228, "EMMC_CLK"),
293 PINCTRL_PIN(229, "EMMC_D0"),
294 PINCTRL_PIN(230, "EMMC_D1"),
295 PINCTRL_PIN(231, "EMMC_D2"),
296 PINCTRL_PIN(232, "EMMC_D3"),
297 PINCTRL_PIN(233, "EMMC_D4"),
298 PINCTRL_PIN(234, "EMMC_D5"),
299 PINCTRL_PIN(235, "EMMC_D6"),
300 PINCTRL_PIN(236, "EMMC_D7"),
301};
302
303static const struct intel_padgroup cdf_community0_gpps[] = {
304 CDF_GPP(0, 0, 23), /* WEST2 */
305 CDF_GPP(1, 24, 47), /* WEST3 */
306 CDF_GPP(2, 48, 70), /* WEST01 */
307 CDF_GPP(3, 71, 90), /* WEST5 */
308 CDF_GPP(4, 91, 96), /* WESTC */
309 CDF_GPP(5, 97, 101), /* WESTC_DFX */
310 CDF_GPP(6, 102, 111), /* WESTA */
311 CDF_GPP(7, 112, 123), /* WESTB */
312 CDF_GPP(8, 124, 143), /* WESTD */
313 CDF_GPP(9, 144, 144), /* WESTD_PECI */
314 CDF_GPP(10, 145, 167), /* WESTF */
315};
316
317static const struct intel_padgroup cdf_community1_gpps[] = {
318 CDF_GPP(0, 168, 190), /* EAST2 */
319 CDF_GPP(1, 191, 201), /* EAST3 */
320 CDF_GPP(2, 202, 225), /* EAST0 */
321 CDF_GPP(3, 226, 236), /* EMMC */
322};
323
324static const struct intel_community cdf_communities[] = {
325 CDF_COMMUNITY(0, 0, 167, cdf_community0_gpps), /* West */
326 CDF_COMMUNITY(1, 168, 236, cdf_community1_gpps), /* East */
327};
328
329static const struct intel_pinctrl_soc_data cdf_soc_data = {
330 .pins = cdf_pins,
331 .npins = ARRAY_SIZE(cdf_pins),
332 .communities = cdf_communities,
333 .ncommunities = ARRAY_SIZE(cdf_communities),
334};
335
336static int cdf_pinctrl_probe(struct platform_device *pdev)
337{
338 return intel_pinctrl_probe(pdev, &cdf_soc_data);
339}
340
341static const struct dev_pm_ops cdf_pinctrl_pm_ops = {
342 SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
343 intel_pinctrl_resume)
344};
345
346static const struct acpi_device_id cdf_pinctrl_acpi_match[] = {
347 { "INTC3001" },
348 { }
349};
350MODULE_DEVICE_TABLE(acpi, cdf_pinctrl_acpi_match);
351
352static struct platform_driver cdf_pinctrl_driver = {
353 .probe = cdf_pinctrl_probe,
354 .driver = {
355 .name = "cedarfork-pinctrl",
356 .acpi_match_table = cdf_pinctrl_acpi_match,
357 .pm = &cdf_pinctrl_pm_ops,
358 },
359};
360
361static int __init cdf_pinctrl_init(void)
362{
363 return platform_driver_register(&cdf_pinctrl_driver);
364}
365subsys_initcall(cdf_pinctrl_init);
366
367static void __exit cdf_pinctrl_exit(void)
368{
369 platform_driver_unregister(&cdf_pinctrl_driver);
370}
371module_exit(cdf_pinctrl_exit);
372
373MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
374MODULE_DESCRIPTION("Intel Cedar Fork PCH pinctrl/GPIO driver");
375MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c
index bc2bb6b328ab..bdedb6325c72 100644
--- a/drivers/pinctrl/intel/pinctrl-cherryview.c
+++ b/drivers/pinctrl/intel/pinctrl-cherryview.c
@@ -491,7 +491,7 @@ static const struct chv_community north_community = {
491 .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges), 491 .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges),
492 .ngpios = ARRAY_SIZE(north_pins), 492 .ngpios = ARRAY_SIZE(north_pins),
493 /* 493 /*
494 * North community can benerate GPIO interrupts only for the first 494 * North community can generate GPIO interrupts only for the first
495 * 8 interrupts. The upper half (8-15) can only be used to trigger 495 * 8 interrupts. The upper half (8-15) can only be used to trigger
496 * GPEs. 496 * GPEs.
497 */ 497 */
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index ffda27bfd133..12a1af45acb9 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -30,8 +30,6 @@
30 30
31#define PADBAR 0x00c 31#define PADBAR 0x00c
32#define GPI_IS 0x100 32#define GPI_IS 0x100
33#define GPI_GPE_STS 0x140
34#define GPI_GPE_EN 0x160
35 33
36#define PADOWN_BITS 4 34#define PADOWN_BITS 4
37#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) 35#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
@@ -818,7 +816,7 @@ static void intel_gpio_irq_ack(struct irq_data *d)
818 community = intel_get_community(pctrl, pin); 816 community = intel_get_community(pctrl, pin);
819 if (community) { 817 if (community) {
820 const struct intel_padgroup *padgrp; 818 const struct intel_padgroup *padgrp;
821 unsigned gpp, gpp_offset; 819 unsigned gpp, gpp_offset, is_offset;
822 820
823 padgrp = intel_community_get_padgroup(community, pin); 821 padgrp = intel_community_get_padgroup(community, pin);
824 if (!padgrp) 822 if (!padgrp)
@@ -826,9 +824,10 @@ static void intel_gpio_irq_ack(struct irq_data *d)
826 824
827 gpp = padgrp->reg_num; 825 gpp = padgrp->reg_num;
828 gpp_offset = padgroup_offset(padgrp, pin); 826 gpp_offset = padgroup_offset(padgrp, pin);
827 is_offset = community->is_offset + gpp * 4;
829 828
830 raw_spin_lock(&pctrl->lock); 829 raw_spin_lock(&pctrl->lock);
831 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); 830 writel(BIT(gpp_offset), community->regs + is_offset);
832 raw_spin_unlock(&pctrl->lock); 831 raw_spin_unlock(&pctrl->lock);
833 } 832 }
834} 833}
@@ -843,7 +842,7 @@ static void intel_gpio_irq_enable(struct irq_data *d)
843 community = intel_get_community(pctrl, pin); 842 community = intel_get_community(pctrl, pin);
844 if (community) { 843 if (community) {
845 const struct intel_padgroup *padgrp; 844 const struct intel_padgroup *padgrp;
846 unsigned gpp, gpp_offset; 845 unsigned gpp, gpp_offset, is_offset;
847 unsigned long flags; 846 unsigned long flags;
848 u32 value; 847 u32 value;
849 848
@@ -853,10 +852,11 @@ static void intel_gpio_irq_enable(struct irq_data *d)
853 852
854 gpp = padgrp->reg_num; 853 gpp = padgrp->reg_num;
855 gpp_offset = padgroup_offset(padgrp, pin); 854 gpp_offset = padgroup_offset(padgrp, pin);
855 is_offset = community->is_offset + gpp * 4;
856 856
857 raw_spin_lock_irqsave(&pctrl->lock, flags); 857 raw_spin_lock_irqsave(&pctrl->lock, flags);
858 /* Clear interrupt status first to avoid unexpected interrupt */ 858 /* Clear interrupt status first to avoid unexpected interrupt */
859 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); 859 writel(BIT(gpp_offset), community->regs + is_offset);
860 860
861 value = readl(community->regs + community->ie_offset + gpp * 4); 861 value = readl(community->regs + community->ie_offset + gpp * 4);
862 value |= BIT(gpp_offset); 862 value |= BIT(gpp_offset);
@@ -991,7 +991,8 @@ static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
991 const struct intel_padgroup *padgrp = &community->gpps[gpp]; 991 const struct intel_padgroup *padgrp = &community->gpps[gpp];
992 unsigned long pending, enabled, gpp_offset; 992 unsigned long pending, enabled, gpp_offset;
993 993
994 pending = readl(community->regs + GPI_IS + padgrp->reg_num * 4); 994 pending = readl(community->regs + community->is_offset +
995 padgrp->reg_num * 4);
995 enabled = readl(community->regs + community->ie_offset + 996 enabled = readl(community->regs + community->ie_offset +
996 padgrp->reg_num * 4); 997 padgrp->reg_num * 4);
997 998
@@ -1241,6 +1242,9 @@ int intel_pinctrl_probe(struct platform_device *pdev,
1241 community->regs = regs; 1242 community->regs = regs;
1242 community->pad_regs = regs + padbar; 1243 community->pad_regs = regs + padbar;
1243 1244
1245 if (!community->is_offset)
1246 community->is_offset = GPI_IS;
1247
1244 ret = intel_pinctrl_add_padgroups(pctrl, community); 1248 ret = intel_pinctrl_add_padgroups(pctrl, community);
1245 if (ret) 1249 if (ret)
1246 return ret; 1250 return ret;
@@ -1356,7 +1360,7 @@ static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1356 for (gpp = 0; gpp < community->ngpps; gpp++) { 1360 for (gpp = 0; gpp < community->ngpps; gpp++) {
1357 /* Mask and clear all interrupts */ 1361 /* Mask and clear all interrupts */
1358 writel(0, base + community->ie_offset + gpp * 4); 1362 writel(0, base + community->ie_offset + gpp * 4);
1359 writel(0xffff, base + GPI_IS + gpp * 4); 1363 writel(0xffff, base + community->is_offset + gpp * 4);
1360 } 1364 }
1361 } 1365 }
1362} 1366}
diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h
index 7fdb07753c2d..13b0bd6eb2a2 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.h
+++ b/drivers/pinctrl/intel/pinctrl-intel.h
@@ -73,6 +73,8 @@ struct intel_padgroup {
73 * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it 73 * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
74 * is assumed that the host owns the pin (rather than 74 * is assumed that the host owns the pin (rather than
75 * ACPI). 75 * ACPI).
76 * @is_offset: Register offset of GPI_IS from @regs. If %0 then uses the
77 * default (%0x100).
76 * @ie_offset: Register offset of GPI_IE from @regs. 78 * @ie_offset: Register offset of GPI_IE from @regs.
77 * @pin_base: Starting pin of pins in this community 79 * @pin_base: Starting pin of pins in this community
78 * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK, 80 * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
@@ -98,6 +100,7 @@ struct intel_community {
98 unsigned padown_offset; 100 unsigned padown_offset;
99 unsigned padcfglock_offset; 101 unsigned padcfglock_offset;
100 unsigned hostown_offset; 102 unsigned hostown_offset;
103 unsigned is_offset;
101 unsigned ie_offset; 104 unsigned ie_offset;
102 unsigned pin_base; 105 unsigned pin_base;
103 unsigned gpp_size; 106 unsigned gpp_size;
diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
new file mode 100644
index 000000000000..1a51778759ea
--- /dev/null
+++ b/drivers/pinctrl/meson/Kconfig
@@ -0,0 +1,41 @@
1menuconfig PINCTRL_MESON
2 bool "Amlogic SoC pinctrl drivers"
3 depends on ARCH_MESON
4 depends on OF
5 select PINMUX
6 select PINCONF
7 select GENERIC_PINCONF
8 select GPIOLIB
9 select OF_GPIO
10 select REGMAP_MMIO
11
12if PINCTRL_MESON
13
14config PINCTRL_MESON8
15 bool "Meson 8 SoC pinctrl driver"
16 depends on ARM
17 select PINCTRL_MESON8_PMX
18 default y
19
20config PINCTRL_MESON8B
21 bool "Meson 8b SoC pinctrl driver"
22 depends on ARM
23 select PINCTRL_MESON8_PMX
24 default y
25
26config PINCTRL_MESON_GXBB
27 bool "Meson gxbb SoC pinctrl driver"
28 depends on ARM64
29 select PINCTRL_MESON8_PMX
30 default y
31
32config PINCTRL_MESON_GXL
33 bool "Meson gxl SoC pinctrl driver"
34 depends on ARM64
35 select PINCTRL_MESON8_PMX
36 default y
37
38config PINCTRL_MESON8_PMX
39 bool
40
41endif
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
index 27c5b5126008..cbd47bb74549 100644
--- a/drivers/pinctrl/meson/Makefile
+++ b/drivers/pinctrl/meson/Makefile
@@ -1,3 +1,6 @@
1obj-y += pinctrl-meson8.o pinctrl-meson8b.o 1obj-$(CONFIG_PINCTRL_MESON) += pinctrl-meson.o
2obj-y += pinctrl-meson-gxbb.o pinctrl-meson-gxl.o 2obj-$(CONFIG_PINCTRL_MESON8_PMX) += pinctrl-meson8-pmx.o
3obj-y += pinctrl-meson.o 3obj-$(CONFIG_PINCTRL_MESON8) += pinctrl-meson8.o
4obj-$(CONFIG_PINCTRL_MESON8B) += pinctrl-meson8b.o
5obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o
6obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index 7bbc0d3cddcf..9079020259c5 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -14,418 +14,417 @@
14 14
15#include <dt-bindings/gpio/meson-gxbb-gpio.h> 15#include <dt-bindings/gpio/meson-gxbb-gpio.h>
16#include "pinctrl-meson.h" 16#include "pinctrl-meson.h"
17 17#include "pinctrl-meson8-pmx.h"
18#define EE_OFF 14
19 18
20static const struct pinctrl_pin_desc meson_gxbb_periphs_pins[] = { 19static const struct pinctrl_pin_desc meson_gxbb_periphs_pins[] = {
21 MESON_PIN(GPIOZ_0, EE_OFF), 20 MESON_PIN(GPIOZ_0),
22 MESON_PIN(GPIOZ_1, EE_OFF), 21 MESON_PIN(GPIOZ_1),
23 MESON_PIN(GPIOZ_2, EE_OFF), 22 MESON_PIN(GPIOZ_2),
24 MESON_PIN(GPIOZ_3, EE_OFF), 23 MESON_PIN(GPIOZ_3),
25 MESON_PIN(GPIOZ_4, EE_OFF), 24 MESON_PIN(GPIOZ_4),
26 MESON_PIN(GPIOZ_5, EE_OFF), 25 MESON_PIN(GPIOZ_5),
27 MESON_PIN(GPIOZ_6, EE_OFF), 26 MESON_PIN(GPIOZ_6),
28 MESON_PIN(GPIOZ_7, EE_OFF), 27 MESON_PIN(GPIOZ_7),
29 MESON_PIN(GPIOZ_8, EE_OFF), 28 MESON_PIN(GPIOZ_8),
30 MESON_PIN(GPIOZ_9, EE_OFF), 29 MESON_PIN(GPIOZ_9),
31 MESON_PIN(GPIOZ_10, EE_OFF), 30 MESON_PIN(GPIOZ_10),
32 MESON_PIN(GPIOZ_11, EE_OFF), 31 MESON_PIN(GPIOZ_11),
33 MESON_PIN(GPIOZ_12, EE_OFF), 32 MESON_PIN(GPIOZ_12),
34 MESON_PIN(GPIOZ_13, EE_OFF), 33 MESON_PIN(GPIOZ_13),
35 MESON_PIN(GPIOZ_14, EE_OFF), 34 MESON_PIN(GPIOZ_14),
36 MESON_PIN(GPIOZ_15, EE_OFF), 35 MESON_PIN(GPIOZ_15),
37 36
38 MESON_PIN(GPIOH_0, EE_OFF), 37 MESON_PIN(GPIOH_0),
39 MESON_PIN(GPIOH_1, EE_OFF), 38 MESON_PIN(GPIOH_1),
40 MESON_PIN(GPIOH_2, EE_OFF), 39 MESON_PIN(GPIOH_2),
41 MESON_PIN(GPIOH_3, EE_OFF), 40 MESON_PIN(GPIOH_3),
42 41
43 MESON_PIN(BOOT_0, EE_OFF), 42 MESON_PIN(BOOT_0),
44 MESON_PIN(BOOT_1, EE_OFF), 43 MESON_PIN(BOOT_1),
45 MESON_PIN(BOOT_2, EE_OFF), 44 MESON_PIN(BOOT_2),
46 MESON_PIN(BOOT_3, EE_OFF), 45 MESON_PIN(BOOT_3),
47 MESON_PIN(BOOT_4, EE_OFF), 46 MESON_PIN(BOOT_4),
48 MESON_PIN(BOOT_5, EE_OFF), 47 MESON_PIN(BOOT_5),
49 MESON_PIN(BOOT_6, EE_OFF), 48 MESON_PIN(BOOT_6),
50 MESON_PIN(BOOT_7, EE_OFF), 49 MESON_PIN(BOOT_7),
51 MESON_PIN(BOOT_8, EE_OFF), 50 MESON_PIN(BOOT_8),
52 MESON_PIN(BOOT_9, EE_OFF), 51 MESON_PIN(BOOT_9),
53 MESON_PIN(BOOT_10, EE_OFF), 52 MESON_PIN(BOOT_10),
54 MESON_PIN(BOOT_11, EE_OFF), 53 MESON_PIN(BOOT_11),
55 MESON_PIN(BOOT_12, EE_OFF), 54 MESON_PIN(BOOT_12),
56 MESON_PIN(BOOT_13, EE_OFF), 55 MESON_PIN(BOOT_13),
57 MESON_PIN(BOOT_14, EE_OFF), 56 MESON_PIN(BOOT_14),
58 MESON_PIN(BOOT_15, EE_OFF), 57 MESON_PIN(BOOT_15),
59 MESON_PIN(BOOT_16, EE_OFF), 58 MESON_PIN(BOOT_16),
60 MESON_PIN(BOOT_17, EE_OFF), 59 MESON_PIN(BOOT_17),
61 60
62 MESON_PIN(CARD_0, EE_OFF), 61 MESON_PIN(CARD_0),
63 MESON_PIN(CARD_1, EE_OFF), 62 MESON_PIN(CARD_1),
64 MESON_PIN(CARD_2, EE_OFF), 63 MESON_PIN(CARD_2),
65 MESON_PIN(CARD_3, EE_OFF), 64 MESON_PIN(CARD_3),
66 MESON_PIN(CARD_4, EE_OFF), 65 MESON_PIN(CARD_4),
67 MESON_PIN(CARD_5, EE_OFF), 66 MESON_PIN(CARD_5),
68 MESON_PIN(CARD_6, EE_OFF), 67 MESON_PIN(CARD_6),
69 68
70 MESON_PIN(GPIODV_0, EE_OFF), 69 MESON_PIN(GPIODV_0),
71 MESON_PIN(GPIODV_1, EE_OFF), 70 MESON_PIN(GPIODV_1),
72 MESON_PIN(GPIODV_2, EE_OFF), 71 MESON_PIN(GPIODV_2),
73 MESON_PIN(GPIODV_3, EE_OFF), 72 MESON_PIN(GPIODV_3),
74 MESON_PIN(GPIODV_4, EE_OFF), 73 MESON_PIN(GPIODV_4),
75 MESON_PIN(GPIODV_5, EE_OFF), 74 MESON_PIN(GPIODV_5),
76 MESON_PIN(GPIODV_6, EE_OFF), 75 MESON_PIN(GPIODV_6),
77 MESON_PIN(GPIODV_7, EE_OFF), 76 MESON_PIN(GPIODV_7),
78 MESON_PIN(GPIODV_8, EE_OFF), 77 MESON_PIN(GPIODV_8),
79 MESON_PIN(GPIODV_9, EE_OFF), 78 MESON_PIN(GPIODV_9),
80 MESON_PIN(GPIODV_10, EE_OFF), 79 MESON_PIN(GPIODV_10),
81 MESON_PIN(GPIODV_11, EE_OFF), 80 MESON_PIN(GPIODV_11),
82 MESON_PIN(GPIODV_12, EE_OFF), 81 MESON_PIN(GPIODV_12),
83 MESON_PIN(GPIODV_13, EE_OFF), 82 MESON_PIN(GPIODV_13),
84 MESON_PIN(GPIODV_14, EE_OFF), 83 MESON_PIN(GPIODV_14),
85 MESON_PIN(GPIODV_15, EE_OFF), 84 MESON_PIN(GPIODV_15),
86 MESON_PIN(GPIODV_16, EE_OFF), 85 MESON_PIN(GPIODV_16),
87 MESON_PIN(GPIODV_17, EE_OFF), 86 MESON_PIN(GPIODV_17),
88 MESON_PIN(GPIODV_18, EE_OFF), 87 MESON_PIN(GPIODV_18),
89 MESON_PIN(GPIODV_19, EE_OFF), 88 MESON_PIN(GPIODV_19),
90 MESON_PIN(GPIODV_20, EE_OFF), 89 MESON_PIN(GPIODV_20),
91 MESON_PIN(GPIODV_21, EE_OFF), 90 MESON_PIN(GPIODV_21),
92 MESON_PIN(GPIODV_22, EE_OFF), 91 MESON_PIN(GPIODV_22),
93 MESON_PIN(GPIODV_23, EE_OFF), 92 MESON_PIN(GPIODV_23),
94 MESON_PIN(GPIODV_24, EE_OFF), 93 MESON_PIN(GPIODV_24),
95 MESON_PIN(GPIODV_25, EE_OFF), 94 MESON_PIN(GPIODV_25),
96 MESON_PIN(GPIODV_26, EE_OFF), 95 MESON_PIN(GPIODV_26),
97 MESON_PIN(GPIODV_27, EE_OFF), 96 MESON_PIN(GPIODV_27),
98 MESON_PIN(GPIODV_28, EE_OFF), 97 MESON_PIN(GPIODV_28),
99 MESON_PIN(GPIODV_29, EE_OFF), 98 MESON_PIN(GPIODV_29),
100 99
101 MESON_PIN(GPIOY_0, EE_OFF), 100 MESON_PIN(GPIOY_0),
102 MESON_PIN(GPIOY_1, EE_OFF), 101 MESON_PIN(GPIOY_1),
103 MESON_PIN(GPIOY_2, EE_OFF), 102 MESON_PIN(GPIOY_2),
104 MESON_PIN(GPIOY_3, EE_OFF), 103 MESON_PIN(GPIOY_3),
105 MESON_PIN(GPIOY_4, EE_OFF), 104 MESON_PIN(GPIOY_4),
106 MESON_PIN(GPIOY_5, EE_OFF), 105 MESON_PIN(GPIOY_5),
107 MESON_PIN(GPIOY_6, EE_OFF), 106 MESON_PIN(GPIOY_6),
108 MESON_PIN(GPIOY_7, EE_OFF), 107 MESON_PIN(GPIOY_7),
109 MESON_PIN(GPIOY_8, EE_OFF), 108 MESON_PIN(GPIOY_8),
110 MESON_PIN(GPIOY_9, EE_OFF), 109 MESON_PIN(GPIOY_9),
111 MESON_PIN(GPIOY_10, EE_OFF), 110 MESON_PIN(GPIOY_10),
112 MESON_PIN(GPIOY_11, EE_OFF), 111 MESON_PIN(GPIOY_11),
113 MESON_PIN(GPIOY_12, EE_OFF), 112 MESON_PIN(GPIOY_12),
114 MESON_PIN(GPIOY_13, EE_OFF), 113 MESON_PIN(GPIOY_13),
115 MESON_PIN(GPIOY_14, EE_OFF), 114 MESON_PIN(GPIOY_14),
116 MESON_PIN(GPIOY_15, EE_OFF), 115 MESON_PIN(GPIOY_15),
117 MESON_PIN(GPIOY_16, EE_OFF), 116 MESON_PIN(GPIOY_16),
118 117
119 MESON_PIN(GPIOX_0, EE_OFF), 118 MESON_PIN(GPIOX_0),
120 MESON_PIN(GPIOX_1, EE_OFF), 119 MESON_PIN(GPIOX_1),
121 MESON_PIN(GPIOX_2, EE_OFF), 120 MESON_PIN(GPIOX_2),
122 MESON_PIN(GPIOX_3, EE_OFF), 121 MESON_PIN(GPIOX_3),
123 MESON_PIN(GPIOX_4, EE_OFF), 122 MESON_PIN(GPIOX_4),
124 MESON_PIN(GPIOX_5, EE_OFF), 123 MESON_PIN(GPIOX_5),
125 MESON_PIN(GPIOX_6, EE_OFF), 124 MESON_PIN(GPIOX_6),
126 MESON_PIN(GPIOX_7, EE_OFF), 125 MESON_PIN(GPIOX_7),
127 MESON_PIN(GPIOX_8, EE_OFF), 126 MESON_PIN(GPIOX_8),
128 MESON_PIN(GPIOX_9, EE_OFF), 127 MESON_PIN(GPIOX_9),
129 MESON_PIN(GPIOX_10, EE_OFF), 128 MESON_PIN(GPIOX_10),
130 MESON_PIN(GPIOX_11, EE_OFF), 129 MESON_PIN(GPIOX_11),
131 MESON_PIN(GPIOX_12, EE_OFF), 130 MESON_PIN(GPIOX_12),
132 MESON_PIN(GPIOX_13, EE_OFF), 131 MESON_PIN(GPIOX_13),
133 MESON_PIN(GPIOX_14, EE_OFF), 132 MESON_PIN(GPIOX_14),
134 MESON_PIN(GPIOX_15, EE_OFF), 133 MESON_PIN(GPIOX_15),
135 MESON_PIN(GPIOX_16, EE_OFF), 134 MESON_PIN(GPIOX_16),
136 MESON_PIN(GPIOX_17, EE_OFF), 135 MESON_PIN(GPIOX_17),
137 MESON_PIN(GPIOX_18, EE_OFF), 136 MESON_PIN(GPIOX_18),
138 MESON_PIN(GPIOX_19, EE_OFF), 137 MESON_PIN(GPIOX_19),
139 MESON_PIN(GPIOX_20, EE_OFF), 138 MESON_PIN(GPIOX_20),
140 MESON_PIN(GPIOX_21, EE_OFF), 139 MESON_PIN(GPIOX_21),
141 140 MESON_PIN(GPIOX_22),
142 MESON_PIN(GPIOCLK_0, EE_OFF), 141
143 MESON_PIN(GPIOCLK_1, EE_OFF), 142 MESON_PIN(GPIOCLK_0),
144 MESON_PIN(GPIOCLK_2, EE_OFF), 143 MESON_PIN(GPIOCLK_1),
145 MESON_PIN(GPIOCLK_3, EE_OFF), 144 MESON_PIN(GPIOCLK_2),
146 145 MESON_PIN(GPIOCLK_3),
147 MESON_PIN(GPIO_TEST_N, EE_OFF),
148}; 146};
149 147
150static const unsigned int emmc_nand_d07_pins[] = { 148static const unsigned int emmc_nand_d07_pins[] = {
151 PIN(BOOT_0, EE_OFF), PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF), 149 BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7,
152 PIN(BOOT_3, EE_OFF), PIN(BOOT_4, EE_OFF), PIN(BOOT_5, EE_OFF), 150};
153 PIN(BOOT_6, EE_OFF), PIN(BOOT_7, EE_OFF), 151static const unsigned int emmc_clk_pins[] = { BOOT_8 };
154}; 152static const unsigned int emmc_cmd_pins[] = { BOOT_10 };
155static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) }; 153static const unsigned int emmc_ds_pins[] = { BOOT_15 };
156static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) }; 154
157static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) }; 155static const unsigned int nor_d_pins[] = { BOOT_11 };
158 156static const unsigned int nor_q_pins[] = { BOOT_12 };
159static const unsigned int nor_d_pins[] = { PIN(BOOT_11, EE_OFF) }; 157static const unsigned int nor_c_pins[] = { BOOT_13 };
160static const unsigned int nor_q_pins[] = { PIN(BOOT_12, EE_OFF) }; 158static const unsigned int nor_cs_pins[] = { BOOT_15 };
161static const unsigned int nor_c_pins[] = { PIN(BOOT_13, EE_OFF) }; 159
162static const unsigned int nor_cs_pins[] = { PIN(BOOT_15, EE_OFF) }; 160static const unsigned int spi_sclk_pins[] = { GPIOZ_6 };
163 161static const unsigned int spi_ss0_pins[] = { GPIOZ_7 };
164static const unsigned int spi_sclk_pins[] = { PIN(GPIOZ_6, EE_OFF) }; 162static const unsigned int spi_miso_pins[] = { GPIOZ_12 };
165static const unsigned int spi_ss0_pins[] = { PIN(GPIOZ_7, EE_OFF) }; 163static const unsigned int spi_mosi_pins[] = { GPIOZ_13 };
166static const unsigned int spi_miso_pins[] = { PIN(GPIOZ_12, EE_OFF) }; 164
167static const unsigned int spi_mosi_pins[] = { PIN(GPIOZ_13, EE_OFF) }; 165static const unsigned int sdcard_d0_pins[] = { CARD_1 };
168 166static const unsigned int sdcard_d1_pins[] = { CARD_0 };
169static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) }; 167static const unsigned int sdcard_d2_pins[] = { CARD_5 };
170static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) }; 168static const unsigned int sdcard_d3_pins[] = { CARD_4 };
171static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) }; 169static const unsigned int sdcard_cmd_pins[] = { CARD_3 };
172static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) }; 170static const unsigned int sdcard_clk_pins[] = { CARD_2 };
173static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) }; 171
174static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) }; 172static const unsigned int sdio_d0_pins[] = { GPIOX_0 };
175 173static const unsigned int sdio_d1_pins[] = { GPIOX_1 };
176static const unsigned int sdio_d0_pins[] = { PIN(GPIOX_0, EE_OFF) }; 174static const unsigned int sdio_d2_pins[] = { GPIOX_2 };
177static const unsigned int sdio_d1_pins[] = { PIN(GPIOX_1, EE_OFF) }; 175static const unsigned int sdio_d3_pins[] = { GPIOX_3 };
178static const unsigned int sdio_d2_pins[] = { PIN(GPIOX_2, EE_OFF) }; 176static const unsigned int sdio_cmd_pins[] = { GPIOX_4 };
179static const unsigned int sdio_d3_pins[] = { PIN(GPIOX_3, EE_OFF) }; 177static const unsigned int sdio_clk_pins[] = { GPIOX_5 };
180static const unsigned int sdio_cmd_pins[] = { PIN(GPIOX_4, EE_OFF) }; 178static const unsigned int sdio_irq_pins[] = { GPIOX_7 };
181static const unsigned int sdio_clk_pins[] = { PIN(GPIOX_5, EE_OFF) }; 179
182static const unsigned int sdio_irq_pins[] = { PIN(GPIOX_7, EE_OFF) }; 180static const unsigned int nand_ce0_pins[] = { BOOT_8 };
183 181static const unsigned int nand_ce1_pins[] = { BOOT_9 };
184static const unsigned int nand_ce0_pins[] = { PIN(BOOT_8, EE_OFF) }; 182static const unsigned int nand_rb0_pins[] = { BOOT_10 };
185static const unsigned int nand_ce1_pins[] = { PIN(BOOT_9, EE_OFF) }; 183static const unsigned int nand_ale_pins[] = { BOOT_11 };
186static const unsigned int nand_rb0_pins[] = { PIN(BOOT_10, EE_OFF) }; 184static const unsigned int nand_cle_pins[] = { BOOT_12 };
187static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, EE_OFF) }; 185static const unsigned int nand_wen_clk_pins[] = { BOOT_13 };
188static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, EE_OFF) }; 186static const unsigned int nand_ren_wr_pins[] = { BOOT_14 };
189static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, EE_OFF) }; 187static const unsigned int nand_dqs_pins[] = { BOOT_15 };
190static const unsigned int nand_ren_wr_pins[] = { PIN(BOOT_14, EE_OFF) }; 188
191static const unsigned int nand_dqs_pins[] = { PIN(BOOT_15, EE_OFF) }; 189static const unsigned int uart_tx_a_pins[] = { GPIOX_12 };
192 190static const unsigned int uart_rx_a_pins[] = { GPIOX_13 };
193static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_12, EE_OFF) }; 191static const unsigned int uart_cts_a_pins[] = { GPIOX_14 };
194static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_13, EE_OFF) }; 192static const unsigned int uart_rts_a_pins[] = { GPIOX_15 };
195static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_14, EE_OFF) }; 193
196static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_15, EE_OFF) }; 194static const unsigned int uart_tx_b_pins[] = { GPIODV_24 };
197 195static const unsigned int uart_rx_b_pins[] = { GPIODV_25 };
198static const unsigned int uart_tx_b_pins[] = { PIN(GPIODV_24, EE_OFF) }; 196static const unsigned int uart_cts_b_pins[] = { GPIODV_26 };
199static const unsigned int uart_rx_b_pins[] = { PIN(GPIODV_25, EE_OFF) }; 197static const unsigned int uart_rts_b_pins[] = { GPIODV_27 };
200static const unsigned int uart_cts_b_pins[] = { PIN(GPIODV_26, EE_OFF) }; 198
201static const unsigned int uart_rts_b_pins[] = { PIN(GPIODV_27, EE_OFF) }; 199static const unsigned int uart_tx_c_pins[] = { GPIOY_13 };
202 200static const unsigned int uart_rx_c_pins[] = { GPIOY_14 };
203static const unsigned int uart_tx_c_pins[] = { PIN(GPIOY_13, EE_OFF) }; 201static const unsigned int uart_cts_c_pins[] = { GPIOX_11 };
204static const unsigned int uart_rx_c_pins[] = { PIN(GPIOY_14, EE_OFF) }; 202static const unsigned int uart_rts_c_pins[] = { GPIOX_12 };
205static const unsigned int uart_cts_c_pins[] = { PIN(GPIOX_11, EE_OFF) }; 203
206static const unsigned int uart_rts_c_pins[] = { PIN(GPIOX_12, EE_OFF) }; 204static const unsigned int i2c_sck_a_pins[] = { GPIODV_25 };
207 205static const unsigned int i2c_sda_a_pins[] = { GPIODV_24 };
208static const unsigned int i2c_sck_a_pins[] = { PIN(GPIODV_25, EE_OFF) }; 206
209static const unsigned int i2c_sda_a_pins[] = { PIN(GPIODV_24, EE_OFF) }; 207static const unsigned int i2c_sck_b_pins[] = { GPIODV_27 };
210 208static const unsigned int i2c_sda_b_pins[] = { GPIODV_26 };
211static const unsigned int i2c_sck_b_pins[] = { PIN(GPIODV_27, EE_OFF) }; 209
212static const unsigned int i2c_sda_b_pins[] = { PIN(GPIODV_26, EE_OFF) }; 210static const unsigned int i2c_sck_c_pins[] = { GPIODV_29 };
213 211static const unsigned int i2c_sda_c_pins[] = { GPIODV_28 };
214static const unsigned int i2c_sck_c_pins[] = { PIN(GPIODV_29, EE_OFF) }; 212
215static const unsigned int i2c_sda_c_pins[] = { PIN(GPIODV_28, EE_OFF) }; 213static const unsigned int eth_mdio_pins[] = { GPIOZ_0 };
216 214static const unsigned int eth_mdc_pins[] = { GPIOZ_1 };
217static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_0, EE_OFF) }; 215static const unsigned int eth_clk_rx_clk_pins[] = { GPIOZ_2 };
218static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_1, EE_OFF) }; 216static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 };
219static const unsigned int eth_clk_rx_clk_pins[] = { PIN(GPIOZ_2, EE_OFF) }; 217static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 };
220static const unsigned int eth_rx_dv_pins[] = { PIN(GPIOZ_3, EE_OFF) }; 218static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 };
221static const unsigned int eth_rxd0_pins[] = { PIN(GPIOZ_4, EE_OFF) }; 219static const unsigned int eth_rxd2_pins[] = { GPIOZ_6 };
222static const unsigned int eth_rxd1_pins[] = { PIN(GPIOZ_5, EE_OFF) }; 220static const unsigned int eth_rxd3_pins[] = { GPIOZ_7 };
223static const unsigned int eth_rxd2_pins[] = { PIN(GPIOZ_6, EE_OFF) }; 221static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 };
224static const unsigned int eth_rxd3_pins[] = { PIN(GPIOZ_7, EE_OFF) }; 222static const unsigned int eth_tx_en_pins[] = { GPIOZ_9 };
225static const unsigned int eth_rgmii_tx_clk_pins[] = { PIN(GPIOZ_8, EE_OFF) }; 223static const unsigned int eth_txd0_pins[] = { GPIOZ_10 };
226static const unsigned int eth_tx_en_pins[] = { PIN(GPIOZ_9, EE_OFF) }; 224static const unsigned int eth_txd1_pins[] = { GPIOZ_11 };
227static const unsigned int eth_txd0_pins[] = { PIN(GPIOZ_10, EE_OFF) }; 225static const unsigned int eth_txd2_pins[] = { GPIOZ_12 };
228static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_11, EE_OFF) }; 226static const unsigned int eth_txd3_pins[] = { GPIOZ_13 };
229static const unsigned int eth_txd2_pins[] = { PIN(GPIOZ_12, EE_OFF) }; 227
230static const unsigned int eth_txd3_pins[] = { PIN(GPIOZ_13, EE_OFF) }; 228static const unsigned int pwm_a_x_pins[] = { GPIOX_6 };
231 229static const unsigned int pwm_a_y_pins[] = { GPIOY_16 };
232static const unsigned int pwm_a_x_pins[] = { PIN(GPIOX_6, EE_OFF) }; 230static const unsigned int pwm_b_pins[] = { GPIODV_29 };
233static const unsigned int pwm_a_y_pins[] = { PIN(GPIOY_16, EE_OFF) }; 231static const unsigned int pwm_d_pins[] = { GPIODV_28 };
234static const unsigned int pwm_b_pins[] = { PIN(GPIODV_29, EE_OFF) }; 232static const unsigned int pwm_e_pins[] = { GPIOX_19 };
235static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, EE_OFF) }; 233static const unsigned int pwm_f_x_pins[] = { GPIOX_7 };
236static const unsigned int pwm_e_pins[] = { PIN(GPIOX_19, EE_OFF) }; 234static const unsigned int pwm_f_y_pins[] = { GPIOY_15 };
237static const unsigned int pwm_f_x_pins[] = { PIN(GPIOX_7, EE_OFF) }; 235
238static const unsigned int pwm_f_y_pins[] = { PIN(GPIOY_15, EE_OFF) }; 236static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 };
239 237static const unsigned int hdmi_sda_pins[] = { GPIOH_1 };
240static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, EE_OFF) }; 238static const unsigned int hdmi_scl_pins[] = { GPIOH_2 };
241static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, EE_OFF) }; 239
242static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, EE_OFF) }; 240static const unsigned int i2s_out_ch23_y_pins[] = { GPIOY_8 };
243 241static const unsigned int i2s_out_ch45_y_pins[] = { GPIOY_9 };
244static const unsigned int i2s_out_ch23_y_pins[] = { PIN(GPIOY_8, EE_OFF) }; 242static const unsigned int i2s_out_ch67_y_pins[] = { GPIOY_10 };
245static const unsigned int i2s_out_ch45_y_pins[] = { PIN(GPIOY_9, EE_OFF) }; 243
246static const unsigned int i2s_out_ch67_y_pins[] = { PIN(GPIOY_10, EE_OFF) }; 244static const unsigned int spdif_out_y_pins[] = { GPIOY_12 };
247
248static const unsigned int spdif_out_y_pins[] = { PIN(GPIOY_12, EE_OFF) };
249 245
250static const struct pinctrl_pin_desc meson_gxbb_aobus_pins[] = { 246static const struct pinctrl_pin_desc meson_gxbb_aobus_pins[] = {
251 MESON_PIN(GPIOAO_0, 0), 247 MESON_PIN(GPIOAO_0),
252 MESON_PIN(GPIOAO_1, 0), 248 MESON_PIN(GPIOAO_1),
253 MESON_PIN(GPIOAO_2, 0), 249 MESON_PIN(GPIOAO_2),
254 MESON_PIN(GPIOAO_3, 0), 250 MESON_PIN(GPIOAO_3),
255 MESON_PIN(GPIOAO_4, 0), 251 MESON_PIN(GPIOAO_4),
256 MESON_PIN(GPIOAO_5, 0), 252 MESON_PIN(GPIOAO_5),
257 MESON_PIN(GPIOAO_6, 0), 253 MESON_PIN(GPIOAO_6),
258 MESON_PIN(GPIOAO_7, 0), 254 MESON_PIN(GPIOAO_7),
259 MESON_PIN(GPIOAO_8, 0), 255 MESON_PIN(GPIOAO_8),
260 MESON_PIN(GPIOAO_9, 0), 256 MESON_PIN(GPIOAO_9),
261 MESON_PIN(GPIOAO_10, 0), 257 MESON_PIN(GPIOAO_10),
262 MESON_PIN(GPIOAO_11, 0), 258 MESON_PIN(GPIOAO_11),
263 MESON_PIN(GPIOAO_12, 0), 259 MESON_PIN(GPIOAO_12),
264 MESON_PIN(GPIOAO_13, 0), 260 MESON_PIN(GPIOAO_13),
265}; 261
266 262 MESON_PIN(GPIO_TEST_N),
267static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, 0) }; 263};
268static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, 0) }; 264
269static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, 0) }; 265static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 };
270static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, 0) }; 266static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 };
271static const unsigned int uart_tx_ao_b_pins[] = { PIN(GPIOAO_4, 0) }; 267static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 };
272static const unsigned int uart_rx_ao_b_pins[] = { PIN(GPIOAO_5, 0) }; 268static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 };
273static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, 0) }; 269static const unsigned int uart_tx_ao_b_pins[] = { GPIOAO_4 };
274static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, 0) }; 270static const unsigned int uart_rx_ao_b_pins[] = { GPIOAO_5 };
275 271static const unsigned int uart_cts_ao_b_pins[] = { GPIOAO_2 };
276static const unsigned int i2c_sck_ao_pins[] = {PIN(GPIOAO_4, 0) }; 272static const unsigned int uart_rts_ao_b_pins[] = { GPIOAO_3 };
277static const unsigned int i2c_sda_ao_pins[] = {PIN(GPIOAO_5, 0) }; 273
278static const unsigned int i2c_slave_sck_ao_pins[] = {PIN(GPIOAO_4, 0) }; 274static const unsigned int i2c_sck_ao_pins[] = { GPIOAO_4 };
279static const unsigned int i2c_slave_sda_ao_pins[] = {PIN(GPIOAO_5, 0) }; 275static const unsigned int i2c_sda_ao_pins[] = { GPIOAO_5 };
280 276static const unsigned int i2c_slave_sck_ao_pins[] = {GPIOAO_4 };
281static const unsigned int remote_input_ao_pins[] = {PIN(GPIOAO_7, 0) }; 277static const unsigned int i2c_slave_sda_ao_pins[] = {GPIOAO_5 };
282 278
283static const unsigned int pwm_ao_a_3_pins[] = { PIN(GPIOAO_3, 0) }; 279static const unsigned int remote_input_ao_pins[] = { GPIOAO_7 };
284static const unsigned int pwm_ao_a_6_pins[] = { PIN(GPIOAO_6, 0) }; 280
285static const unsigned int pwm_ao_a_12_pins[] = { PIN(GPIOAO_12, 0) }; 281static const unsigned int pwm_ao_a_3_pins[] = { GPIOAO_3 };
286static const unsigned int pwm_ao_b_pins[] = { PIN(GPIOAO_13, 0) }; 282static const unsigned int pwm_ao_a_6_pins[] = { GPIOAO_6 };
287 283static const unsigned int pwm_ao_a_12_pins[] = { GPIOAO_12 };
288static const unsigned int i2s_am_clk_pins[] = { PIN(GPIOAO_8, 0) }; 284static const unsigned int pwm_ao_b_pins[] = { GPIOAO_13 };
289static const unsigned int i2s_out_ao_clk_pins[] = { PIN(GPIOAO_9, 0) }; 285
290static const unsigned int i2s_out_lr_clk_pins[] = { PIN(GPIOAO_10, 0) }; 286static const unsigned int i2s_am_clk_pins[] = { GPIOAO_8 };
291static const unsigned int i2s_out_ch01_ao_pins[] = { PIN(GPIOAO_11, 0) }; 287static const unsigned int i2s_out_ao_clk_pins[] = { GPIOAO_9 };
292static const unsigned int i2s_out_ch23_ao_pins[] = { PIN(GPIOAO_12, 0) }; 288static const unsigned int i2s_out_lr_clk_pins[] = { GPIOAO_10 };
293static const unsigned int i2s_out_ch45_ao_pins[] = { PIN(GPIOAO_13, 0) }; 289static const unsigned int i2s_out_ch01_ao_pins[] = { GPIOAO_11 };
294 290static const unsigned int i2s_out_ch23_ao_pins[] = { GPIOAO_12 };
295static const unsigned int spdif_out_ao_6_pins[] = { PIN(GPIOAO_6, 0) }; 291static const unsigned int i2s_out_ch45_ao_pins[] = { GPIOAO_13 };
296static const unsigned int spdif_out_ao_13_pins[] = { PIN(GPIOAO_13, 0) }; 292static const unsigned int i2s_out_ch67_ao_pins[] = { GPIO_TEST_N };
297 293
298static const unsigned int ao_cec_pins[] = { PIN(GPIOAO_12, 0) }; 294static const unsigned int spdif_out_ao_6_pins[] = { GPIOAO_6 };
299static const unsigned int ee_cec_pins[] = { PIN(GPIOAO_12, 0) }; 295static const unsigned int spdif_out_ao_13_pins[] = { GPIOAO_13 };
296
297static const unsigned int ao_cec_pins[] = { GPIOAO_12 };
298static const unsigned int ee_cec_pins[] = { GPIOAO_12 };
300 299
301static struct meson_pmx_group meson_gxbb_periphs_groups[] = { 300static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
302 GPIO_GROUP(GPIOZ_0, EE_OFF), 301 GPIO_GROUP(GPIOZ_0),
303 GPIO_GROUP(GPIOZ_1, EE_OFF), 302 GPIO_GROUP(GPIOZ_1),
304 GPIO_GROUP(GPIOZ_2, EE_OFF), 303 GPIO_GROUP(GPIOZ_2),
305 GPIO_GROUP(GPIOZ_3, EE_OFF), 304 GPIO_GROUP(GPIOZ_3),
306 GPIO_GROUP(GPIOZ_4, EE_OFF), 305 GPIO_GROUP(GPIOZ_4),
307 GPIO_GROUP(GPIOZ_5, EE_OFF), 306 GPIO_GROUP(GPIOZ_5),
308 GPIO_GROUP(GPIOZ_6, EE_OFF), 307 GPIO_GROUP(GPIOZ_6),
309 GPIO_GROUP(GPIOZ_7, EE_OFF), 308 GPIO_GROUP(GPIOZ_7),
310 GPIO_GROUP(GPIOZ_8, EE_OFF), 309 GPIO_GROUP(GPIOZ_8),
311 GPIO_GROUP(GPIOZ_9, EE_OFF), 310 GPIO_GROUP(GPIOZ_9),
312 GPIO_GROUP(GPIOZ_10, EE_OFF), 311 GPIO_GROUP(GPIOZ_10),
313 GPIO_GROUP(GPIOZ_11, EE_OFF), 312 GPIO_GROUP(GPIOZ_11),
314 GPIO_GROUP(GPIOZ_12, EE_OFF), 313 GPIO_GROUP(GPIOZ_12),
315 GPIO_GROUP(GPIOZ_13, EE_OFF), 314 GPIO_GROUP(GPIOZ_13),
316 GPIO_GROUP(GPIOZ_14, EE_OFF), 315 GPIO_GROUP(GPIOZ_14),
317 GPIO_GROUP(GPIOZ_15, EE_OFF), 316 GPIO_GROUP(GPIOZ_15),
318 317
319 GPIO_GROUP(GPIOH_0, EE_OFF), 318 GPIO_GROUP(GPIOH_0),
320 GPIO_GROUP(GPIOH_1, EE_OFF), 319 GPIO_GROUP(GPIOH_1),
321 GPIO_GROUP(GPIOH_2, EE_OFF), 320 GPIO_GROUP(GPIOH_2),
322 GPIO_GROUP(GPIOH_3, EE_OFF), 321 GPIO_GROUP(GPIOH_3),
323 322
324 GPIO_GROUP(BOOT_0, EE_OFF), 323 GPIO_GROUP(BOOT_0),
325 GPIO_GROUP(BOOT_1, EE_OFF), 324 GPIO_GROUP(BOOT_1),
326 GPIO_GROUP(BOOT_2, EE_OFF), 325 GPIO_GROUP(BOOT_2),
327 GPIO_GROUP(BOOT_3, EE_OFF), 326 GPIO_GROUP(BOOT_3),
328 GPIO_GROUP(BOOT_4, EE_OFF), 327 GPIO_GROUP(BOOT_4),
329 GPIO_GROUP(BOOT_5, EE_OFF), 328 GPIO_GROUP(BOOT_5),
330 GPIO_GROUP(BOOT_6, EE_OFF), 329 GPIO_GROUP(BOOT_6),
331 GPIO_GROUP(BOOT_7, EE_OFF), 330 GPIO_GROUP(BOOT_7),
332 GPIO_GROUP(BOOT_8, EE_OFF), 331 GPIO_GROUP(BOOT_8),
333 GPIO_GROUP(BOOT_9, EE_OFF), 332 GPIO_GROUP(BOOT_9),
334 GPIO_GROUP(BOOT_10, EE_OFF), 333 GPIO_GROUP(BOOT_10),
335 GPIO_GROUP(BOOT_11, EE_OFF), 334 GPIO_GROUP(BOOT_11),
336 GPIO_GROUP(BOOT_12, EE_OFF), 335 GPIO_GROUP(BOOT_12),
337 GPIO_GROUP(BOOT_13, EE_OFF), 336 GPIO_GROUP(BOOT_13),
338 GPIO_GROUP(BOOT_14, EE_OFF), 337 GPIO_GROUP(BOOT_14),
339 GPIO_GROUP(BOOT_15, EE_OFF), 338 GPIO_GROUP(BOOT_15),
340 GPIO_GROUP(BOOT_16, EE_OFF), 339 GPIO_GROUP(BOOT_16),
341 GPIO_GROUP(BOOT_17, EE_OFF), 340 GPIO_GROUP(BOOT_17),
342 341
343 GPIO_GROUP(CARD_0, EE_OFF), 342 GPIO_GROUP(CARD_0),
344 GPIO_GROUP(CARD_1, EE_OFF), 343 GPIO_GROUP(CARD_1),
345 GPIO_GROUP(CARD_2, EE_OFF), 344 GPIO_GROUP(CARD_2),
346 GPIO_GROUP(CARD_3, EE_OFF), 345 GPIO_GROUP(CARD_3),
347 GPIO_GROUP(CARD_4, EE_OFF), 346 GPIO_GROUP(CARD_4),
348 GPIO_GROUP(CARD_5, EE_OFF), 347 GPIO_GROUP(CARD_5),
349 GPIO_GROUP(CARD_6, EE_OFF), 348 GPIO_GROUP(CARD_6),
350 349
351 GPIO_GROUP(GPIODV_0, EE_OFF), 350 GPIO_GROUP(GPIODV_0),
352 GPIO_GROUP(GPIODV_1, EE_OFF), 351 GPIO_GROUP(GPIODV_1),
353 GPIO_GROUP(GPIODV_2, EE_OFF), 352 GPIO_GROUP(GPIODV_2),
354 GPIO_GROUP(GPIODV_3, EE_OFF), 353 GPIO_GROUP(GPIODV_3),
355 GPIO_GROUP(GPIODV_4, EE_OFF), 354 GPIO_GROUP(GPIODV_4),
356 GPIO_GROUP(GPIODV_5, EE_OFF), 355 GPIO_GROUP(GPIODV_5),
357 GPIO_GROUP(GPIODV_6, EE_OFF), 356 GPIO_GROUP(GPIODV_6),
358 GPIO_GROUP(GPIODV_7, EE_OFF), 357 GPIO_GROUP(GPIODV_7),
359 GPIO_GROUP(GPIODV_8, EE_OFF), 358 GPIO_GROUP(GPIODV_8),
360 GPIO_GROUP(GPIODV_9, EE_OFF), 359 GPIO_GROUP(GPIODV_9),
361 GPIO_GROUP(GPIODV_10, EE_OFF), 360 GPIO_GROUP(GPIODV_10),
362 GPIO_GROUP(GPIODV_11, EE_OFF), 361 GPIO_GROUP(GPIODV_11),
363 GPIO_GROUP(GPIODV_12, EE_OFF), 362 GPIO_GROUP(GPIODV_12),
364 GPIO_GROUP(GPIODV_13, EE_OFF), 363 GPIO_GROUP(GPIODV_13),
365 GPIO_GROUP(GPIODV_14, EE_OFF), 364 GPIO_GROUP(GPIODV_14),
366 GPIO_GROUP(GPIODV_15, EE_OFF), 365 GPIO_GROUP(GPIODV_15),
367 GPIO_GROUP(GPIODV_16, EE_OFF), 366 GPIO_GROUP(GPIODV_16),
368 GPIO_GROUP(GPIODV_17, EE_OFF), 367 GPIO_GROUP(GPIODV_17),
369 GPIO_GROUP(GPIODV_19, EE_OFF), 368 GPIO_GROUP(GPIODV_19),
370 GPIO_GROUP(GPIODV_20, EE_OFF), 369 GPIO_GROUP(GPIODV_20),
371 GPIO_GROUP(GPIODV_21, EE_OFF), 370 GPIO_GROUP(GPIODV_21),
372 GPIO_GROUP(GPIODV_22, EE_OFF), 371 GPIO_GROUP(GPIODV_22),
373 GPIO_GROUP(GPIODV_23, EE_OFF), 372 GPIO_GROUP(GPIODV_23),
374 GPIO_GROUP(GPIODV_24, EE_OFF), 373 GPIO_GROUP(GPIODV_24),
375 GPIO_GROUP(GPIODV_25, EE_OFF), 374 GPIO_GROUP(GPIODV_25),
376 GPIO_GROUP(GPIODV_26, EE_OFF), 375 GPIO_GROUP(GPIODV_26),
377 GPIO_GROUP(GPIODV_27, EE_OFF), 376 GPIO_GROUP(GPIODV_27),
378 GPIO_GROUP(GPIODV_28, EE_OFF), 377 GPIO_GROUP(GPIODV_28),
379 GPIO_GROUP(GPIODV_29, EE_OFF), 378 GPIO_GROUP(GPIODV_29),
380 379
381 GPIO_GROUP(GPIOY_0, EE_OFF), 380 GPIO_GROUP(GPIOY_0),
382 GPIO_GROUP(GPIOY_1, EE_OFF), 381 GPIO_GROUP(GPIOY_1),
383 GPIO_GROUP(GPIOY_2, EE_OFF), 382 GPIO_GROUP(GPIOY_2),
384 GPIO_GROUP(GPIOY_3, EE_OFF), 383 GPIO_GROUP(GPIOY_3),
385 GPIO_GROUP(GPIOY_4, EE_OFF), 384 GPIO_GROUP(GPIOY_4),
386 GPIO_GROUP(GPIOY_5, EE_OFF), 385 GPIO_GROUP(GPIOY_5),
387 GPIO_GROUP(GPIOY_6, EE_OFF), 386 GPIO_GROUP(GPIOY_6),
388 GPIO_GROUP(GPIOY_7, EE_OFF), 387 GPIO_GROUP(GPIOY_7),
389 GPIO_GROUP(GPIOY_8, EE_OFF), 388 GPIO_GROUP(GPIOY_8),
390 GPIO_GROUP(GPIOY_9, EE_OFF), 389 GPIO_GROUP(GPIOY_9),
391 GPIO_GROUP(GPIOY_10, EE_OFF), 390 GPIO_GROUP(GPIOY_10),
392 GPIO_GROUP(GPIOY_11, EE_OFF), 391 GPIO_GROUP(GPIOY_11),
393 GPIO_GROUP(GPIOY_12, EE_OFF), 392 GPIO_GROUP(GPIOY_12),
394 GPIO_GROUP(GPIOY_13, EE_OFF), 393 GPIO_GROUP(GPIOY_13),
395 GPIO_GROUP(GPIOY_14, EE_OFF), 394 GPIO_GROUP(GPIOY_14),
396 GPIO_GROUP(GPIOY_15, EE_OFF), 395 GPIO_GROUP(GPIOY_15),
397 GPIO_GROUP(GPIOY_16, EE_OFF), 396 GPIO_GROUP(GPIOY_16),
398 397
399 GPIO_GROUP(GPIOX_0, EE_OFF), 398 GPIO_GROUP(GPIOX_0),
400 GPIO_GROUP(GPIOX_1, EE_OFF), 399 GPIO_GROUP(GPIOX_1),
401 GPIO_GROUP(GPIOX_2, EE_OFF), 400 GPIO_GROUP(GPIOX_2),
402 GPIO_GROUP(GPIOX_3, EE_OFF), 401 GPIO_GROUP(GPIOX_3),
403 GPIO_GROUP(GPIOX_4, EE_OFF), 402 GPIO_GROUP(GPIOX_4),
404 GPIO_GROUP(GPIOX_5, EE_OFF), 403 GPIO_GROUP(GPIOX_5),
405 GPIO_GROUP(GPIOX_6, EE_OFF), 404 GPIO_GROUP(GPIOX_6),
406 GPIO_GROUP(GPIOX_7, EE_OFF), 405 GPIO_GROUP(GPIOX_7),
407 GPIO_GROUP(GPIOX_8, EE_OFF), 406 GPIO_GROUP(GPIOX_8),
408 GPIO_GROUP(GPIOX_9, EE_OFF), 407 GPIO_GROUP(GPIOX_9),
409 GPIO_GROUP(GPIOX_10, EE_OFF), 408 GPIO_GROUP(GPIOX_10),
410 GPIO_GROUP(GPIOX_11, EE_OFF), 409 GPIO_GROUP(GPIOX_11),
411 GPIO_GROUP(GPIOX_12, EE_OFF), 410 GPIO_GROUP(GPIOX_12),
412 GPIO_GROUP(GPIOX_13, EE_OFF), 411 GPIO_GROUP(GPIOX_13),
413 GPIO_GROUP(GPIOX_14, EE_OFF), 412 GPIO_GROUP(GPIOX_14),
414 GPIO_GROUP(GPIOX_15, EE_OFF), 413 GPIO_GROUP(GPIOX_15),
415 GPIO_GROUP(GPIOX_16, EE_OFF), 414 GPIO_GROUP(GPIOX_16),
416 GPIO_GROUP(GPIOX_17, EE_OFF), 415 GPIO_GROUP(GPIOX_17),
417 GPIO_GROUP(GPIOX_18, EE_OFF), 416 GPIO_GROUP(GPIOX_18),
418 GPIO_GROUP(GPIOX_19, EE_OFF), 417 GPIO_GROUP(GPIOX_19),
419 GPIO_GROUP(GPIOX_20, EE_OFF), 418 GPIO_GROUP(GPIOX_20),
420 GPIO_GROUP(GPIOX_21, EE_OFF), 419 GPIO_GROUP(GPIOX_21),
421 GPIO_GROUP(GPIOX_22, EE_OFF), 420 GPIO_GROUP(GPIOX_22),
422 421
423 GPIO_GROUP(GPIOCLK_0, EE_OFF), 422 GPIO_GROUP(GPIOCLK_0),
424 GPIO_GROUP(GPIOCLK_1, EE_OFF), 423 GPIO_GROUP(GPIOCLK_1),
425 GPIO_GROUP(GPIOCLK_2, EE_OFF), 424 GPIO_GROUP(GPIOCLK_2),
426 GPIO_GROUP(GPIOCLK_3, EE_OFF), 425 GPIO_GROUP(GPIOCLK_3),
427 426
428 GPIO_GROUP(GPIO_TEST_N, EE_OFF), 427 GPIO_GROUP(GPIO_TEST_N),
429 428
430 /* Bank X */ 429 /* Bank X */
431 GROUP(sdio_d0, 8, 5), 430 GROUP(sdio_d0, 8, 5),
@@ -522,20 +521,20 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
522}; 521};
523 522
524static struct meson_pmx_group meson_gxbb_aobus_groups[] = { 523static struct meson_pmx_group meson_gxbb_aobus_groups[] = {
525 GPIO_GROUP(GPIOAO_0, 0), 524 GPIO_GROUP(GPIOAO_0),
526 GPIO_GROUP(GPIOAO_1, 0), 525 GPIO_GROUP(GPIOAO_1),
527 GPIO_GROUP(GPIOAO_2, 0), 526 GPIO_GROUP(GPIOAO_2),
528 GPIO_GROUP(GPIOAO_3, 0), 527 GPIO_GROUP(GPIOAO_3),
529 GPIO_GROUP(GPIOAO_4, 0), 528 GPIO_GROUP(GPIOAO_4),
530 GPIO_GROUP(GPIOAO_5, 0), 529 GPIO_GROUP(GPIOAO_5),
531 GPIO_GROUP(GPIOAO_6, 0), 530 GPIO_GROUP(GPIOAO_6),
532 GPIO_GROUP(GPIOAO_7, 0), 531 GPIO_GROUP(GPIOAO_7),
533 GPIO_GROUP(GPIOAO_8, 0), 532 GPIO_GROUP(GPIOAO_8),
534 GPIO_GROUP(GPIOAO_9, 0), 533 GPIO_GROUP(GPIOAO_9),
535 GPIO_GROUP(GPIOAO_10, 0), 534 GPIO_GROUP(GPIOAO_10),
536 GPIO_GROUP(GPIOAO_11, 0), 535 GPIO_GROUP(GPIOAO_11),
537 GPIO_GROUP(GPIOAO_12, 0), 536 GPIO_GROUP(GPIOAO_12),
538 GPIO_GROUP(GPIOAO_13, 0), 537 GPIO_GROUP(GPIOAO_13),
539 538
540 /* bank AO */ 539 /* bank AO */
541 GROUP(uart_tx_ao_b, 0, 24), 540 GROUP(uart_tx_ao_b, 0, 24),
@@ -565,6 +564,9 @@ static struct meson_pmx_group meson_gxbb_aobus_groups[] = {
565 GROUP(spdif_out_ao_13, 0, 4), 564 GROUP(spdif_out_ao_13, 0, 4),
566 GROUP(ao_cec, 0, 15), 565 GROUP(ao_cec, 0, 15),
567 GROUP(ee_cec, 0, 14), 566 GROUP(ee_cec, 0, 14),
567
568 /* test n pin */
569 GROUP(i2s_out_ch67_ao, 1, 2),
568}; 570};
569 571
570static const char * const gpio_periphs_groups[] = { 572static const char * const gpio_periphs_groups[] = {
@@ -600,8 +602,6 @@ static const char * const gpio_periphs_groups[] = {
600 "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", 602 "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
601 "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19", 603 "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
602 "GPIOX_20", "GPIOX_21", "GPIOX_22", 604 "GPIOX_20", "GPIOX_21", "GPIOX_22",
603
604 "GPIO_TEST_N",
605}; 605};
606 606
607static const char * const emmc_groups[] = { 607static const char * const emmc_groups[] = {
@@ -710,6 +710,8 @@ static const char * const gpio_aobus_groups[] = {
710 "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", 710 "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
711 "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", 711 "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
712 "GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13", 712 "GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13",
713
714 "GPIO_TEST_N",
713}; 715};
714 716
715static const char * const uart_ao_groups[] = { 717static const char * const uart_ao_groups[] = {
@@ -751,6 +753,7 @@ static const char * const pwm_ao_b_groups[] = {
751static const char * const i2s_out_ao_groups[] = { 753static const char * const i2s_out_ao_groups[] = {
752 "i2s_am_clk", "i2s_out_ao_clk", "i2s_out_lr_clk", 754 "i2s_am_clk", "i2s_out_ao_clk", "i2s_out_lr_clk",
753 "i2s_out_ch01_ao", "i2s_out_ch23_ao", "i2s_out_ch45_ao", 755 "i2s_out_ch01_ao", "i2s_out_ch23_ao", "i2s_out_ch45_ao",
756 "i2s_out_ch67_ao",
754}; 757};
755 758
756static const char * const spdif_out_ao_groups[] = { 759static const char * const spdif_out_ao_groups[] = {
@@ -806,25 +809,24 @@ static struct meson_pmx_func meson_gxbb_aobus_functions[] = {
806}; 809};
807 810
808static struct meson_bank meson_gxbb_periphs_banks[] = { 811static struct meson_bank meson_gxbb_periphs_banks[] = {
809 /* name first last irq pullen pull dir out in */ 812 /* name first last irq pullen pull dir out in */
810 BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_22, EE_OFF), 106, 128, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), 813 BANK("X", GPIOX_0, GPIOX_22, 106, 128, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
811 BANK("Y", PIN(GPIOY_0, EE_OFF), PIN(GPIOY_16, EE_OFF), 89, 105, 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), 814 BANK("Y", GPIOY_0, GPIOY_16, 89, 105, 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
812 BANK("DV", PIN(GPIODV_0, EE_OFF), PIN(GPIODV_29, EE_OFF), 59, 88, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), 815 BANK("DV", GPIODV_0, GPIODV_29, 59, 88, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
813 BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_3, EE_OFF), 30, 33, 1, 20, 1, 20, 3, 20, 4, 20, 5, 20), 816 BANK("H", GPIOH_0, GPIOH_3, 30, 33, 1, 20, 1, 20, 3, 20, 4, 20, 5, 20),
814 BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 14, 29, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), 817 BANK("Z", GPIOZ_0, GPIOZ_15, 14, 29, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
815 BANK("CARD", PIN(CARD_0, EE_OFF), PIN(CARD_6, EE_OFF), 52, 58, 2, 20, 2, 20, 6, 20, 7, 20, 8, 20), 818 BANK("CARD", CARD_0, CARD_6, 52, 58, 2, 20, 2, 20, 6, 20, 7, 20, 8, 20),
816 BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_17, EE_OFF), 34, 51, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), 819 BANK("BOOT", BOOT_0, BOOT_17, 34, 51, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
817 BANK("CLK", PIN(GPIOCLK_0, EE_OFF), PIN(GPIOCLK_3, EE_OFF), 129, 132, 3, 28, 3, 28, 9, 28, 10, 28, 11, 28), 820 BANK("CLK", GPIOCLK_0, GPIOCLK_3, 129, 132, 3, 28, 3, 28, 9, 28, 10, 28, 11, 28),
818}; 821};
819 822
820static struct meson_bank meson_gxbb_aobus_banks[] = { 823static struct meson_bank meson_gxbb_aobus_banks[] = {
821 /* name first last irq pullen pull dir out in */ 824 /* name first last irq pullen pull dir out in */
822 BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_13, 0), 0, 13, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), 825 BANK("AO", GPIOAO_0, GPIOAO_13, 0, 13, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
823}; 826};
824 827
825struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = { 828static struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
826 .name = "periphs-banks", 829 .name = "periphs-banks",
827 .pin_base = 14,
828 .pins = meson_gxbb_periphs_pins, 830 .pins = meson_gxbb_periphs_pins,
829 .groups = meson_gxbb_periphs_groups, 831 .groups = meson_gxbb_periphs_groups,
830 .funcs = meson_gxbb_periphs_functions, 832 .funcs = meson_gxbb_periphs_functions,
@@ -833,11 +835,11 @@ struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = {
833 .num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups), 835 .num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups),
834 .num_funcs = ARRAY_SIZE(meson_gxbb_periphs_functions), 836 .num_funcs = ARRAY_SIZE(meson_gxbb_periphs_functions),
835 .num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks), 837 .num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks),
838 .pmx_ops = &meson8_pmx_ops,
836}; 839};
837 840
838struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = { 841static struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
839 .name = "aobus-banks", 842 .name = "aobus-banks",
840 .pin_base = 0,
841 .pins = meson_gxbb_aobus_pins, 843 .pins = meson_gxbb_aobus_pins,
842 .groups = meson_gxbb_aobus_groups, 844 .groups = meson_gxbb_aobus_groups,
843 .funcs = meson_gxbb_aobus_functions, 845 .funcs = meson_gxbb_aobus_functions,
@@ -846,4 +848,26 @@ struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = {
846 .num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups), 848 .num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups),
847 .num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions), 849 .num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions),
848 .num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks), 850 .num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks),
851 .pmx_ops = &meson8_pmx_ops,
852};
853
854static const struct of_device_id meson_gxbb_pinctrl_dt_match[] = {
855 {
856 .compatible = "amlogic,meson-gxbb-periphs-pinctrl",
857 .data = &meson_gxbb_periphs_pinctrl_data,
858 },
859 {
860 .compatible = "amlogic,meson-gxbb-aobus-pinctrl",
861 .data = &meson_gxbb_aobus_pinctrl_data,
862 },
863 { },
864};
865
866static struct platform_driver meson_gxbb_pinctrl_driver = {
867 .probe = meson_pinctrl_probe,
868 .driver = {
869 .name = "meson-gxbb-pinctrl",
870 .of_match_table = meson_gxbb_pinctrl_dt_match,
871 },
849}; 872};
873builtin_platform_driver(meson_gxbb_pinctrl_driver);
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
index 36c14b85fc7c..b3786cde963d 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
@@ -14,408 +14,400 @@
14 14
15#include <dt-bindings/gpio/meson-gxl-gpio.h> 15#include <dt-bindings/gpio/meson-gxl-gpio.h>
16#include "pinctrl-meson.h" 16#include "pinctrl-meson.h"
17 17#include "pinctrl-meson8-pmx.h"
18#define EE_OFF 10
19 18
20static const struct pinctrl_pin_desc meson_gxl_periphs_pins[] = { 19static const struct pinctrl_pin_desc meson_gxl_periphs_pins[] = {
21 MESON_PIN(GPIOZ_0, EE_OFF), 20 MESON_PIN(GPIOZ_0),
22 MESON_PIN(GPIOZ_1, EE_OFF), 21 MESON_PIN(GPIOZ_1),
23 MESON_PIN(GPIOZ_2, EE_OFF), 22 MESON_PIN(GPIOZ_2),
24 MESON_PIN(GPIOZ_3, EE_OFF), 23 MESON_PIN(GPIOZ_3),
25 MESON_PIN(GPIOZ_4, EE_OFF), 24 MESON_PIN(GPIOZ_4),
26 MESON_PIN(GPIOZ_5, EE_OFF), 25 MESON_PIN(GPIOZ_5),
27 MESON_PIN(GPIOZ_6, EE_OFF), 26 MESON_PIN(GPIOZ_6),
28 MESON_PIN(GPIOZ_7, EE_OFF), 27 MESON_PIN(GPIOZ_7),
29 MESON_PIN(GPIOZ_8, EE_OFF), 28 MESON_PIN(GPIOZ_8),
30 MESON_PIN(GPIOZ_9, EE_OFF), 29 MESON_PIN(GPIOZ_9),
31 MESON_PIN(GPIOZ_10, EE_OFF), 30 MESON_PIN(GPIOZ_10),
32 MESON_PIN(GPIOZ_11, EE_OFF), 31 MESON_PIN(GPIOZ_11),
33 MESON_PIN(GPIOZ_12, EE_OFF), 32 MESON_PIN(GPIOZ_12),
34 MESON_PIN(GPIOZ_13, EE_OFF), 33 MESON_PIN(GPIOZ_13),
35 MESON_PIN(GPIOZ_14, EE_OFF), 34 MESON_PIN(GPIOZ_14),
36 MESON_PIN(GPIOZ_15, EE_OFF), 35 MESON_PIN(GPIOZ_15),
37 36
38 MESON_PIN(GPIOH_0, EE_OFF), 37 MESON_PIN(GPIOH_0),
39 MESON_PIN(GPIOH_1, EE_OFF), 38 MESON_PIN(GPIOH_1),
40 MESON_PIN(GPIOH_2, EE_OFF), 39 MESON_PIN(GPIOH_2),
41 MESON_PIN(GPIOH_3, EE_OFF), 40 MESON_PIN(GPIOH_3),
42 MESON_PIN(GPIOH_4, EE_OFF), 41 MESON_PIN(GPIOH_4),
43 MESON_PIN(GPIOH_5, EE_OFF), 42 MESON_PIN(GPIOH_5),
44 MESON_PIN(GPIOH_6, EE_OFF), 43 MESON_PIN(GPIOH_6),
45 MESON_PIN(GPIOH_7, EE_OFF), 44 MESON_PIN(GPIOH_7),
46 MESON_PIN(GPIOH_8, EE_OFF), 45 MESON_PIN(GPIOH_8),
47 MESON_PIN(GPIOH_9, EE_OFF), 46 MESON_PIN(GPIOH_9),
48 47
49 MESON_PIN(BOOT_0, EE_OFF), 48 MESON_PIN(BOOT_0),
50 MESON_PIN(BOOT_1, EE_OFF), 49 MESON_PIN(BOOT_1),
51 MESON_PIN(BOOT_2, EE_OFF), 50 MESON_PIN(BOOT_2),
52 MESON_PIN(BOOT_3, EE_OFF), 51 MESON_PIN(BOOT_3),
53 MESON_PIN(BOOT_4, EE_OFF), 52 MESON_PIN(BOOT_4),
54 MESON_PIN(BOOT_5, EE_OFF), 53 MESON_PIN(BOOT_5),
55 MESON_PIN(BOOT_6, EE_OFF), 54 MESON_PIN(BOOT_6),
56 MESON_PIN(BOOT_7, EE_OFF), 55 MESON_PIN(BOOT_7),
57 MESON_PIN(BOOT_8, EE_OFF), 56 MESON_PIN(BOOT_8),
58 MESON_PIN(BOOT_9, EE_OFF), 57 MESON_PIN(BOOT_9),
59 MESON_PIN(BOOT_10, EE_OFF), 58 MESON_PIN(BOOT_10),
60 MESON_PIN(BOOT_11, EE_OFF), 59 MESON_PIN(BOOT_11),
61 MESON_PIN(BOOT_12, EE_OFF), 60 MESON_PIN(BOOT_12),
62 MESON_PIN(BOOT_13, EE_OFF), 61 MESON_PIN(BOOT_13),
63 MESON_PIN(BOOT_14, EE_OFF), 62 MESON_PIN(BOOT_14),
64 MESON_PIN(BOOT_15, EE_OFF), 63 MESON_PIN(BOOT_15),
65 64
66 MESON_PIN(CARD_0, EE_OFF), 65 MESON_PIN(CARD_0),
67 MESON_PIN(CARD_1, EE_OFF), 66 MESON_PIN(CARD_1),
68 MESON_PIN(CARD_2, EE_OFF), 67 MESON_PIN(CARD_2),
69 MESON_PIN(CARD_3, EE_OFF), 68 MESON_PIN(CARD_3),
70 MESON_PIN(CARD_4, EE_OFF), 69 MESON_PIN(CARD_4),
71 MESON_PIN(CARD_5, EE_OFF), 70 MESON_PIN(CARD_5),
72 MESON_PIN(CARD_6, EE_OFF), 71 MESON_PIN(CARD_6),
73 72
74 MESON_PIN(GPIODV_0, EE_OFF), 73 MESON_PIN(GPIODV_0),
75 MESON_PIN(GPIODV_1, EE_OFF), 74 MESON_PIN(GPIODV_1),
76 MESON_PIN(GPIODV_2, EE_OFF), 75 MESON_PIN(GPIODV_2),
77 MESON_PIN(GPIODV_3, EE_OFF), 76 MESON_PIN(GPIODV_3),
78 MESON_PIN(GPIODV_4, EE_OFF), 77 MESON_PIN(GPIODV_4),
79 MESON_PIN(GPIODV_5, EE_OFF), 78 MESON_PIN(GPIODV_5),
80 MESON_PIN(GPIODV_6, EE_OFF), 79 MESON_PIN(GPIODV_6),
81 MESON_PIN(GPIODV_7, EE_OFF), 80 MESON_PIN(GPIODV_7),
82 MESON_PIN(GPIODV_8, EE_OFF), 81 MESON_PIN(GPIODV_8),
83 MESON_PIN(GPIODV_9, EE_OFF), 82 MESON_PIN(GPIODV_9),
84 MESON_PIN(GPIODV_10, EE_OFF), 83 MESON_PIN(GPIODV_10),
85 MESON_PIN(GPIODV_11, EE_OFF), 84 MESON_PIN(GPIODV_11),
86 MESON_PIN(GPIODV_12, EE_OFF), 85 MESON_PIN(GPIODV_12),
87 MESON_PIN(GPIODV_13, EE_OFF), 86 MESON_PIN(GPIODV_13),
88 MESON_PIN(GPIODV_14, EE_OFF), 87 MESON_PIN(GPIODV_14),
89 MESON_PIN(GPIODV_15, EE_OFF), 88 MESON_PIN(GPIODV_15),
90 MESON_PIN(GPIODV_16, EE_OFF), 89 MESON_PIN(GPIODV_16),
91 MESON_PIN(GPIODV_17, EE_OFF), 90 MESON_PIN(GPIODV_17),
92 MESON_PIN(GPIODV_18, EE_OFF), 91 MESON_PIN(GPIODV_18),
93 MESON_PIN(GPIODV_19, EE_OFF), 92 MESON_PIN(GPIODV_19),
94 MESON_PIN(GPIODV_20, EE_OFF), 93 MESON_PIN(GPIODV_20),
95 MESON_PIN(GPIODV_21, EE_OFF), 94 MESON_PIN(GPIODV_21),
96 MESON_PIN(GPIODV_22, EE_OFF), 95 MESON_PIN(GPIODV_22),
97 MESON_PIN(GPIODV_23, EE_OFF), 96 MESON_PIN(GPIODV_23),
98 MESON_PIN(GPIODV_24, EE_OFF), 97 MESON_PIN(GPIODV_24),
99 MESON_PIN(GPIODV_25, EE_OFF), 98 MESON_PIN(GPIODV_25),
100 MESON_PIN(GPIODV_26, EE_OFF), 99 MESON_PIN(GPIODV_26),
101 MESON_PIN(GPIODV_27, EE_OFF), 100 MESON_PIN(GPIODV_27),
102 MESON_PIN(GPIODV_28, EE_OFF), 101 MESON_PIN(GPIODV_28),
103 MESON_PIN(GPIODV_29, EE_OFF), 102 MESON_PIN(GPIODV_29),
104 103
105 MESON_PIN(GPIOX_0, EE_OFF), 104 MESON_PIN(GPIOX_0),
106 MESON_PIN(GPIOX_1, EE_OFF), 105 MESON_PIN(GPIOX_1),
107 MESON_PIN(GPIOX_2, EE_OFF), 106 MESON_PIN(GPIOX_2),
108 MESON_PIN(GPIOX_3, EE_OFF), 107 MESON_PIN(GPIOX_3),
109 MESON_PIN(GPIOX_4, EE_OFF), 108 MESON_PIN(GPIOX_4),
110 MESON_PIN(GPIOX_5, EE_OFF), 109 MESON_PIN(GPIOX_5),
111 MESON_PIN(GPIOX_6, EE_OFF), 110 MESON_PIN(GPIOX_6),
112 MESON_PIN(GPIOX_7, EE_OFF), 111 MESON_PIN(GPIOX_7),
113 MESON_PIN(GPIOX_8, EE_OFF), 112 MESON_PIN(GPIOX_8),
114 MESON_PIN(GPIOX_9, EE_OFF), 113 MESON_PIN(GPIOX_9),
115 MESON_PIN(GPIOX_10, EE_OFF), 114 MESON_PIN(GPIOX_10),
116 MESON_PIN(GPIOX_11, EE_OFF), 115 MESON_PIN(GPIOX_11),
117 MESON_PIN(GPIOX_12, EE_OFF), 116 MESON_PIN(GPIOX_12),
118 MESON_PIN(GPIOX_13, EE_OFF), 117 MESON_PIN(GPIOX_13),
119 MESON_PIN(GPIOX_14, EE_OFF), 118 MESON_PIN(GPIOX_14),
120 MESON_PIN(GPIOX_15, EE_OFF), 119 MESON_PIN(GPIOX_15),
121 MESON_PIN(GPIOX_16, EE_OFF), 120 MESON_PIN(GPIOX_16),
122 MESON_PIN(GPIOX_17, EE_OFF), 121 MESON_PIN(GPIOX_17),
123 MESON_PIN(GPIOX_18, EE_OFF), 122 MESON_PIN(GPIOX_18),
124 123
125 MESON_PIN(GPIOCLK_0, EE_OFF), 124 MESON_PIN(GPIOCLK_0),
126 MESON_PIN(GPIOCLK_1, EE_OFF), 125 MESON_PIN(GPIOCLK_1),
127
128 MESON_PIN(GPIO_TEST_N, EE_OFF),
129}; 126};
130 127
131static const unsigned int emmc_nand_d07_pins[] = { 128static const unsigned int emmc_nand_d07_pins[] = {
132 PIN(BOOT_0, EE_OFF), PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF), 129 BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7,
133 PIN(BOOT_3, EE_OFF), PIN(BOOT_4, EE_OFF), PIN(BOOT_5, EE_OFF), 130};
134 PIN(BOOT_6, EE_OFF), PIN(BOOT_7, EE_OFF), 131static const unsigned int emmc_clk_pins[] = { BOOT_8 };
135}; 132static const unsigned int emmc_cmd_pins[] = { BOOT_10 };
136static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) }; 133static const unsigned int emmc_ds_pins[] = { BOOT_15 };
137static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) }; 134
138static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) }; 135static const unsigned int nor_d_pins[] = { BOOT_11 };
139 136static const unsigned int nor_q_pins[] = { BOOT_12 };
140static const unsigned int nor_d_pins[] = { PIN(BOOT_11, EE_OFF) }; 137static const unsigned int nor_c_pins[] = { BOOT_13 };
141static const unsigned int nor_q_pins[] = { PIN(BOOT_12, EE_OFF) }; 138static const unsigned int nor_cs_pins[] = { BOOT_15 };
142static const unsigned int nor_c_pins[] = { PIN(BOOT_13, EE_OFF) }; 139
143static const unsigned int nor_cs_pins[] = { PIN(BOOT_15, EE_OFF) }; 140static const unsigned int spi_mosi_pins[] = { GPIOX_8 };
144 141static const unsigned int spi_miso_pins[] = { GPIOX_9 };
145static const unsigned int spi_mosi_pins[] = { PIN(GPIOX_8, EE_OFF) }; 142static const unsigned int spi_ss0_pins[] = { GPIOX_10 };
146static const unsigned int spi_miso_pins[] = { PIN(GPIOX_9, EE_OFF) }; 143static const unsigned int spi_sclk_pins[] = { GPIOX_11 };
147static const unsigned int spi_ss0_pins[] = { PIN(GPIOX_10, EE_OFF) }; 144
148static const unsigned int spi_sclk_pins[] = { PIN(GPIOX_11, EE_OFF) }; 145static const unsigned int sdcard_d0_pins[] = { CARD_1 };
149 146static const unsigned int sdcard_d1_pins[] = { CARD_0 };
150static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) }; 147static const unsigned int sdcard_d2_pins[] = { CARD_5 };
151static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) }; 148static const unsigned int sdcard_d3_pins[] = { CARD_4 };
152static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) }; 149static const unsigned int sdcard_cmd_pins[] = { CARD_3 };
153static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) }; 150static const unsigned int sdcard_clk_pins[] = { CARD_2 };
154static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) }; 151
155static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) }; 152static const unsigned int sdio_d0_pins[] = { GPIOX_0 };
156 153static const unsigned int sdio_d1_pins[] = { GPIOX_1 };
157static const unsigned int sdio_d0_pins[] = { PIN(GPIOX_0, EE_OFF) }; 154static const unsigned int sdio_d2_pins[] = { GPIOX_2 };
158static const unsigned int sdio_d1_pins[] = { PIN(GPIOX_1, EE_OFF) }; 155static const unsigned int sdio_d3_pins[] = { GPIOX_3 };
159static const unsigned int sdio_d2_pins[] = { PIN(GPIOX_2, EE_OFF) }; 156static const unsigned int sdio_cmd_pins[] = { GPIOX_4 };
160static const unsigned int sdio_d3_pins[] = { PIN(GPIOX_3, EE_OFF) }; 157static const unsigned int sdio_clk_pins[] = { GPIOX_5 };
161static const unsigned int sdio_cmd_pins[] = { PIN(GPIOX_4, EE_OFF) }; 158static const unsigned int sdio_irq_pins[] = { GPIOX_7 };
162static const unsigned int sdio_clk_pins[] = { PIN(GPIOX_5, EE_OFF) }; 159
163static const unsigned int sdio_irq_pins[] = { PIN(GPIOX_7, EE_OFF) }; 160static const unsigned int nand_ce0_pins[] = { BOOT_8 };
164 161static const unsigned int nand_ce1_pins[] = { BOOT_9 };
165static const unsigned int nand_ce0_pins[] = { PIN(BOOT_8, EE_OFF) }; 162static const unsigned int nand_rb0_pins[] = { BOOT_10 };
166static const unsigned int nand_ce1_pins[] = { PIN(BOOT_9, EE_OFF) }; 163static const unsigned int nand_ale_pins[] = { BOOT_11 };
167static const unsigned int nand_rb0_pins[] = { PIN(BOOT_10, EE_OFF) }; 164static const unsigned int nand_cle_pins[] = { BOOT_12 };
168static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, EE_OFF) }; 165static const unsigned int nand_wen_clk_pins[] = { BOOT_13 };
169static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, EE_OFF) }; 166static const unsigned int nand_ren_wr_pins[] = { BOOT_14 };
170static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, EE_OFF) }; 167static const unsigned int nand_dqs_pins[] = { BOOT_15 };
171static const unsigned int nand_ren_wr_pins[] = { PIN(BOOT_14, EE_OFF) }; 168
172static const unsigned int nand_dqs_pins[] = { PIN(BOOT_15, EE_OFF) }; 169static const unsigned int uart_tx_a_pins[] = { GPIOX_12 };
173 170static const unsigned int uart_rx_a_pins[] = { GPIOX_13 };
174static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_12, EE_OFF) }; 171static const unsigned int uart_cts_a_pins[] = { GPIOX_14 };
175static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_13, EE_OFF) }; 172static const unsigned int uart_rts_a_pins[] = { GPIOX_15 };
176static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_14, EE_OFF) }; 173
177static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_15, EE_OFF) }; 174static const unsigned int uart_tx_b_pins[] = { GPIODV_24 };
178 175static const unsigned int uart_rx_b_pins[] = { GPIODV_25 };
179static const unsigned int uart_tx_b_pins[] = { PIN(GPIODV_24, EE_OFF) }; 176static const unsigned int uart_cts_b_pins[] = { GPIODV_26 };
180static const unsigned int uart_rx_b_pins[] = { PIN(GPIODV_25, EE_OFF) }; 177static const unsigned int uart_rts_b_pins[] = { GPIODV_27 };
181static const unsigned int uart_cts_b_pins[] = { PIN(GPIODV_26, EE_OFF) }; 178
182static const unsigned int uart_rts_b_pins[] = { PIN(GPIODV_27, EE_OFF) }; 179static const unsigned int uart_tx_c_pins[] = { GPIOX_8 };
183 180static const unsigned int uart_rx_c_pins[] = { GPIOX_9 };
184static const unsigned int uart_tx_c_pins[] = { PIN(GPIOX_8, EE_OFF) }; 181static const unsigned int uart_cts_c_pins[] = { GPIOX_10 };
185static const unsigned int uart_rx_c_pins[] = { PIN(GPIOX_9, EE_OFF) }; 182static const unsigned int uart_rts_c_pins[] = { GPIOX_11 };
186static const unsigned int uart_cts_c_pins[] = { PIN(GPIOX_10, EE_OFF) }; 183
187static const unsigned int uart_rts_c_pins[] = { PIN(GPIOX_11, EE_OFF) }; 184static const unsigned int i2c_sck_a_pins[] = { GPIODV_25 };
188 185static const unsigned int i2c_sda_a_pins[] = { GPIODV_24 };
189static const unsigned int i2c_sck_a_pins[] = { PIN(GPIODV_25, EE_OFF) }; 186
190static const unsigned int i2c_sda_a_pins[] = { PIN(GPIODV_24, EE_OFF) }; 187static const unsigned int i2c_sck_b_pins[] = { GPIODV_27 };
191 188static const unsigned int i2c_sda_b_pins[] = { GPIODV_26 };
192static const unsigned int i2c_sck_b_pins[] = { PIN(GPIODV_27, EE_OFF) }; 189
193static const unsigned int i2c_sda_b_pins[] = { PIN(GPIODV_26, EE_OFF) }; 190static const unsigned int i2c_sck_c_pins[] = { GPIODV_29 };
194 191static const unsigned int i2c_sda_c_pins[] = { GPIODV_28 };
195static const unsigned int i2c_sck_c_pins[] = { PIN(GPIODV_29, EE_OFF) }; 192
196static const unsigned int i2c_sda_c_pins[] = { PIN(GPIODV_28, EE_OFF) }; 193static const unsigned int i2c_sck_c_dv19_pins[] = { GPIODV_19 };
197 194static const unsigned int i2c_sda_c_dv18_pins[] = { GPIODV_18 };
198static const unsigned int i2c_sck_c_dv19_pins[] = { PIN(GPIODV_19, EE_OFF) }; 195
199static const unsigned int i2c_sda_c_dv18_pins[] = { PIN(GPIODV_18, EE_OFF) }; 196static const unsigned int eth_mdio_pins[] = { GPIOZ_0 };
200 197static const unsigned int eth_mdc_pins[] = { GPIOZ_1 };
201static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_0, EE_OFF) }; 198static const unsigned int eth_clk_rx_clk_pins[] = { GPIOZ_2 };
202static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_1, EE_OFF) }; 199static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 };
203static const unsigned int eth_clk_rx_clk_pins[] = { PIN(GPIOZ_2, EE_OFF) }; 200static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 };
204static const unsigned int eth_rx_dv_pins[] = { PIN(GPIOZ_3, EE_OFF) }; 201static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 };
205static const unsigned int eth_rxd0_pins[] = { PIN(GPIOZ_4, EE_OFF) }; 202static const unsigned int eth_rxd2_pins[] = { GPIOZ_6 };
206static const unsigned int eth_rxd1_pins[] = { PIN(GPIOZ_5, EE_OFF) }; 203static const unsigned int eth_rxd3_pins[] = { GPIOZ_7 };
207static const unsigned int eth_rxd2_pins[] = { PIN(GPIOZ_6, EE_OFF) }; 204static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 };
208static const unsigned int eth_rxd3_pins[] = { PIN(GPIOZ_7, EE_OFF) }; 205static const unsigned int eth_tx_en_pins[] = { GPIOZ_9 };
209static const unsigned int eth_rgmii_tx_clk_pins[] = { PIN(GPIOZ_8, EE_OFF) }; 206static const unsigned int eth_txd0_pins[] = { GPIOZ_10 };
210static const unsigned int eth_tx_en_pins[] = { PIN(GPIOZ_9, EE_OFF) }; 207static const unsigned int eth_txd1_pins[] = { GPIOZ_11 };
211static const unsigned int eth_txd0_pins[] = { PIN(GPIOZ_10, EE_OFF) }; 208static const unsigned int eth_txd2_pins[] = { GPIOZ_12 };
212static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_11, EE_OFF) }; 209static const unsigned int eth_txd3_pins[] = { GPIOZ_13 };
213static const unsigned int eth_txd2_pins[] = { PIN(GPIOZ_12, EE_OFF) }; 210
214static const unsigned int eth_txd3_pins[] = { PIN(GPIOZ_13, EE_OFF) }; 211static const unsigned int pwm_a_pins[] = { GPIOX_6 };
215 212
216static const unsigned int pwm_a_pins[] = { PIN(GPIOX_6, EE_OFF) }; 213static const unsigned int pwm_b_pins[] = { GPIODV_29 };
217 214
218static const unsigned int pwm_b_pins[] = { PIN(GPIODV_29, EE_OFF) }; 215static const unsigned int pwm_c_pins[] = { GPIOZ_15 };
219 216
220static const unsigned int pwm_c_pins[] = { PIN(GPIOZ_15, EE_OFF) }; 217static const unsigned int pwm_d_pins[] = { GPIODV_28 };
221 218
222static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, EE_OFF) }; 219static const unsigned int pwm_e_pins[] = { GPIOX_16 };
223 220
224static const unsigned int pwm_e_pins[] = { PIN(GPIOX_16, EE_OFF) }; 221static const unsigned int pwm_f_clk_pins[] = { GPIOCLK_1 };
225 222static const unsigned int pwm_f_x_pins[] = { GPIOX_7 };
226static const unsigned int pwm_f_clk_pins[] = { PIN(GPIOCLK_1, EE_OFF) }; 223
227static const unsigned int pwm_f_x_pins[] = { PIN(GPIOX_7, EE_OFF) }; 224static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 };
228 225static const unsigned int hdmi_sda_pins[] = { GPIOH_1 };
229static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, EE_OFF) }; 226static const unsigned int hdmi_scl_pins[] = { GPIOH_2 };
230static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, EE_OFF) }; 227
231static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, EE_OFF) }; 228static const unsigned int i2s_am_clk_pins[] = { GPIOH_6 };
232 229static const unsigned int i2s_out_ao_clk_pins[] = { GPIOH_7 };
233static const unsigned int i2s_am_clk_pins[] = { PIN(GPIOH_6, EE_OFF) }; 230static const unsigned int i2s_out_lr_clk_pins[] = { GPIOH_8 };
234static const unsigned int i2s_out_ao_clk_pins[] = { PIN(GPIOH_7, EE_OFF) }; 231static const unsigned int i2s_out_ch01_pins[] = { GPIOH_9 };
235static const unsigned int i2s_out_lr_clk_pins[] = { PIN(GPIOH_8, EE_OFF) }; 232static const unsigned int i2s_out_ch23_z_pins[] = { GPIOZ_5 };
236static const unsigned int i2s_out_ch01_pins[] = { PIN(GPIOH_9, EE_OFF) }; 233static const unsigned int i2s_out_ch45_z_pins[] = { GPIOZ_6 };
237static const unsigned int i2s_out_ch23_z_pins[] = { PIN(GPIOZ_5, EE_OFF) }; 234static const unsigned int i2s_out_ch67_z_pins[] = { GPIOZ_7 };
238static const unsigned int i2s_out_ch45_z_pins[] = { PIN(GPIOZ_6, EE_OFF) }; 235
239static const unsigned int i2s_out_ch67_z_pins[] = { PIN(GPIOZ_7, EE_OFF) }; 236static const unsigned int spdif_out_h_pins[] = { GPIOH_4 };
240 237
241static const unsigned int spdif_out_h_pins[] = { PIN(GPIOH_4, EE_OFF) }; 238static const unsigned int eth_link_led_pins[] = { GPIOZ_14 };
242 239static const unsigned int eth_act_led_pins[] = { GPIOZ_15 };
243static const unsigned int eth_link_led_pins[] = { PIN(GPIOZ_14, EE_OFF) }; 240
244static const unsigned int eth_act_led_pins[] = { PIN(GPIOZ_15, EE_OFF) }; 241static const unsigned int tsin_a_d0_pins[] = { GPIODV_0 };
245 242static const unsigned int tsin_a_d0_x_pins[] = { GPIOX_10 };
246static const unsigned int tsin_a_d0_pins[] = { PIN(GPIODV_0, EE_OFF) }; 243static const unsigned int tsin_a_clk_pins[] = { GPIODV_8 };
247static const unsigned int tsin_a_d0_x_pins[] = { PIN(GPIOX_10, EE_OFF) }; 244static const unsigned int tsin_a_clk_x_pins[] = { GPIOX_11 };
248static const unsigned int tsin_a_clk_pins[] = { PIN(GPIODV_8, EE_OFF) }; 245static const unsigned int tsin_a_sop_pins[] = { GPIODV_9 };
249static const unsigned int tsin_a_clk_x_pins[] = { PIN(GPIOX_11, EE_OFF) }; 246static const unsigned int tsin_a_sop_x_pins[] = { GPIOX_8 };
250static const unsigned int tsin_a_sop_pins[] = { PIN(GPIODV_9, EE_OFF) }; 247static const unsigned int tsin_a_d_valid_pins[] = { GPIODV_10 };
251static const unsigned int tsin_a_sop_x_pins[] = { PIN(GPIOX_8, EE_OFF) }; 248static const unsigned int tsin_a_d_valid_x_pins[] = { GPIOX_9 };
252static const unsigned int tsin_a_d_valid_pins[] = { PIN(GPIODV_10, EE_OFF) }; 249static const unsigned int tsin_a_fail_pins[] = { GPIODV_11 };
253static const unsigned int tsin_a_d_valid_x_pins[] = { PIN(GPIOX_9, EE_OFF) };
254static const unsigned int tsin_a_fail_pins[] = { PIN(GPIODV_11, EE_OFF) };
255static const unsigned int tsin_a_dp_pins[] = { 250static const unsigned int tsin_a_dp_pins[] = {
256 PIN(GPIODV_1, EE_OFF), 251 GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5, GPIODV_6, GPIODV_7,
257 PIN(GPIODV_2, EE_OFF),
258 PIN(GPIODV_3, EE_OFF),
259 PIN(GPIODV_4, EE_OFF),
260 PIN(GPIODV_5, EE_OFF),
261 PIN(GPIODV_6, EE_OFF),
262 PIN(GPIODV_7, EE_OFF),
263}; 252};
264 253
265static const struct pinctrl_pin_desc meson_gxl_aobus_pins[] = { 254static const struct pinctrl_pin_desc meson_gxl_aobus_pins[] = {
266 MESON_PIN(GPIOAO_0, 0), 255 MESON_PIN(GPIOAO_0),
267 MESON_PIN(GPIOAO_1, 0), 256 MESON_PIN(GPIOAO_1),
268 MESON_PIN(GPIOAO_2, 0), 257 MESON_PIN(GPIOAO_2),
269 MESON_PIN(GPIOAO_3, 0), 258 MESON_PIN(GPIOAO_3),
270 MESON_PIN(GPIOAO_4, 0), 259 MESON_PIN(GPIOAO_4),
271 MESON_PIN(GPIOAO_5, 0), 260 MESON_PIN(GPIOAO_5),
272 MESON_PIN(GPIOAO_6, 0), 261 MESON_PIN(GPIOAO_6),
273 MESON_PIN(GPIOAO_7, 0), 262 MESON_PIN(GPIOAO_7),
274 MESON_PIN(GPIOAO_8, 0), 263 MESON_PIN(GPIOAO_8),
275 MESON_PIN(GPIOAO_9, 0), 264 MESON_PIN(GPIOAO_9),
276}; 265
277 266 MESON_PIN(GPIO_TEST_N),
278static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, 0) }; 267};
279static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, 0) }; 268
280static const unsigned int uart_tx_ao_b_0_pins[] = { PIN(GPIOAO_0, 0) }; 269static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 };
281static const unsigned int uart_rx_ao_b_1_pins[] = { PIN(GPIOAO_1, 0) }; 270static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 };
282static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, 0) }; 271static const unsigned int uart_tx_ao_b_0_pins[] = { GPIOAO_0 };
283static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, 0) }; 272static const unsigned int uart_rx_ao_b_1_pins[] = { GPIOAO_1 };
284static const unsigned int uart_tx_ao_b_pins[] = { PIN(GPIOAO_4, 0) }; 273static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 };
285static const unsigned int uart_rx_ao_b_pins[] = { PIN(GPIOAO_5, 0) }; 274static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 };
286static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, 0) }; 275static const unsigned int uart_tx_ao_b_pins[] = { GPIOAO_4 };
287static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, 0) }; 276static const unsigned int uart_rx_ao_b_pins[] = { GPIOAO_5 };
288 277static const unsigned int uart_cts_ao_b_pins[] = { GPIOAO_2 };
289static const unsigned int i2c_sck_ao_pins[] = {PIN(GPIOAO_4, 0) }; 278static const unsigned int uart_rts_ao_b_pins[] = { GPIOAO_3 };
290static const unsigned int i2c_sda_ao_pins[] = {PIN(GPIOAO_5, 0) }; 279
291static const unsigned int i2c_slave_sck_ao_pins[] = {PIN(GPIOAO_4, 0) }; 280static const unsigned int i2c_sck_ao_pins[] = {GPIOAO_4 };
292static const unsigned int i2c_slave_sda_ao_pins[] = {PIN(GPIOAO_5, 0) }; 281static const unsigned int i2c_sda_ao_pins[] = {GPIOAO_5 };
293 282static const unsigned int i2c_slave_sck_ao_pins[] = {GPIOAO_4 };
294static const unsigned int remote_input_ao_pins[] = {PIN(GPIOAO_7, 0) }; 283static const unsigned int i2c_slave_sda_ao_pins[] = {GPIOAO_5 };
295 284
296static const unsigned int pwm_ao_a_3_pins[] = { PIN(GPIOAO_3, 0) }; 285static const unsigned int remote_input_ao_pins[] = {GPIOAO_7 };
297static const unsigned int pwm_ao_a_8_pins[] = { PIN(GPIOAO_8, 0) }; 286
298 287static const unsigned int pwm_ao_a_3_pins[] = { GPIOAO_3 };
299static const unsigned int pwm_ao_b_pins[] = { PIN(GPIOAO_9, 0) }; 288static const unsigned int pwm_ao_a_8_pins[] = { GPIOAO_8 };
300static const unsigned int pwm_ao_b_6_pins[] = { PIN(GPIOAO_6, 0) }; 289
301 290static const unsigned int pwm_ao_b_pins[] = { GPIOAO_9 };
302static const unsigned int i2s_out_ch23_ao_pins[] = { PIN(GPIOAO_8, 0) }; 291static const unsigned int pwm_ao_b_6_pins[] = { GPIOAO_6 };
303static const unsigned int i2s_out_ch45_ao_pins[] = { PIN(GPIOAO_9, 0) }; 292
304 293static const unsigned int i2s_out_ch23_ao_pins[] = { GPIOAO_8 };
305static const unsigned int spdif_out_ao_6_pins[] = { PIN(GPIOAO_6, 0) }; 294static const unsigned int i2s_out_ch45_ao_pins[] = { GPIOAO_9 };
306static const unsigned int spdif_out_ao_9_pins[] = { PIN(GPIOAO_9, 0) }; 295static const unsigned int i2s_out_ch67_ao_pins[] = { GPIO_TEST_N };
307 296
308static const unsigned int ao_cec_pins[] = { PIN(GPIOAO_8, 0) }; 297static const unsigned int spdif_out_ao_6_pins[] = { GPIOAO_6 };
309static const unsigned int ee_cec_pins[] = { PIN(GPIOAO_8, 0) }; 298static const unsigned int spdif_out_ao_9_pins[] = { GPIOAO_9 };
299
300static const unsigned int ao_cec_pins[] = { GPIOAO_8 };
301static const unsigned int ee_cec_pins[] = { GPIOAO_8 };
310 302
311static struct meson_pmx_group meson_gxl_periphs_groups[] = { 303static struct meson_pmx_group meson_gxl_periphs_groups[] = {
312 GPIO_GROUP(GPIOZ_0, EE_OFF), 304 GPIO_GROUP(GPIOZ_0),
313 GPIO_GROUP(GPIOZ_1, EE_OFF), 305 GPIO_GROUP(GPIOZ_1),
314 GPIO_GROUP(GPIOZ_2, EE_OFF), 306 GPIO_GROUP(GPIOZ_2),
315 GPIO_GROUP(GPIOZ_3, EE_OFF), 307 GPIO_GROUP(GPIOZ_3),
316 GPIO_GROUP(GPIOZ_4, EE_OFF), 308 GPIO_GROUP(GPIOZ_4),
317 GPIO_GROUP(GPIOZ_5, EE_OFF), 309 GPIO_GROUP(GPIOZ_5),
318 GPIO_GROUP(GPIOZ_6, EE_OFF), 310 GPIO_GROUP(GPIOZ_6),
319 GPIO_GROUP(GPIOZ_7, EE_OFF), 311 GPIO_GROUP(GPIOZ_7),
320 GPIO_GROUP(GPIOZ_8, EE_OFF), 312 GPIO_GROUP(GPIOZ_8),
321 GPIO_GROUP(GPIOZ_9, EE_OFF), 313 GPIO_GROUP(GPIOZ_9),
322 GPIO_GROUP(GPIOZ_10, EE_OFF), 314 GPIO_GROUP(GPIOZ_10),
323 GPIO_GROUP(GPIOZ_11, EE_OFF), 315 GPIO_GROUP(GPIOZ_11),
324 GPIO_GROUP(GPIOZ_12, EE_OFF), 316 GPIO_GROUP(GPIOZ_12),
325 GPIO_GROUP(GPIOZ_13, EE_OFF), 317 GPIO_GROUP(GPIOZ_13),
326 GPIO_GROUP(GPIOZ_14, EE_OFF), 318 GPIO_GROUP(GPIOZ_14),
327 GPIO_GROUP(GPIOZ_15, EE_OFF), 319 GPIO_GROUP(GPIOZ_15),
328 320
329 GPIO_GROUP(GPIOH_0, EE_OFF), 321 GPIO_GROUP(GPIOH_0),
330 GPIO_GROUP(GPIOH_1, EE_OFF), 322 GPIO_GROUP(GPIOH_1),
331 GPIO_GROUP(GPIOH_2, EE_OFF), 323 GPIO_GROUP(GPIOH_2),
332 GPIO_GROUP(GPIOH_3, EE_OFF), 324 GPIO_GROUP(GPIOH_3),
333 GPIO_GROUP(GPIOH_4, EE_OFF), 325 GPIO_GROUP(GPIOH_4),
334 GPIO_GROUP(GPIOH_5, EE_OFF), 326 GPIO_GROUP(GPIOH_5),
335 GPIO_GROUP(GPIOH_6, EE_OFF), 327 GPIO_GROUP(GPIOH_6),
336 GPIO_GROUP(GPIOH_7, EE_OFF), 328 GPIO_GROUP(GPIOH_7),
337 GPIO_GROUP(GPIOH_8, EE_OFF), 329 GPIO_GROUP(GPIOH_8),
338 GPIO_GROUP(GPIOH_9, EE_OFF), 330 GPIO_GROUP(GPIOH_9),
339 331
340 GPIO_GROUP(BOOT_0, EE_OFF), 332 GPIO_GROUP(BOOT_0),
341 GPIO_GROUP(BOOT_1, EE_OFF), 333 GPIO_GROUP(BOOT_1),
342 GPIO_GROUP(BOOT_2, EE_OFF), 334 GPIO_GROUP(BOOT_2),
343 GPIO_GROUP(BOOT_3, EE_OFF), 335 GPIO_GROUP(BOOT_3),
344 GPIO_GROUP(BOOT_4, EE_OFF), 336 GPIO_GROUP(BOOT_4),
345 GPIO_GROUP(BOOT_5, EE_OFF), 337 GPIO_GROUP(BOOT_5),
346 GPIO_GROUP(BOOT_6, EE_OFF), 338 GPIO_GROUP(BOOT_6),
347 GPIO_GROUP(BOOT_7, EE_OFF), 339 GPIO_GROUP(BOOT_7),
348 GPIO_GROUP(BOOT_8, EE_OFF), 340 GPIO_GROUP(BOOT_8),
349 GPIO_GROUP(BOOT_9, EE_OFF), 341 GPIO_GROUP(BOOT_9),
350 GPIO_GROUP(BOOT_10, EE_OFF), 342 GPIO_GROUP(BOOT_10),
351 GPIO_GROUP(BOOT_11, EE_OFF), 343 GPIO_GROUP(BOOT_11),
352 GPIO_GROUP(BOOT_12, EE_OFF), 344 GPIO_GROUP(BOOT_12),
353 GPIO_GROUP(BOOT_13, EE_OFF), 345 GPIO_GROUP(BOOT_13),
354 GPIO_GROUP(BOOT_14, EE_OFF), 346 GPIO_GROUP(BOOT_14),
355 GPIO_GROUP(BOOT_15, EE_OFF), 347 GPIO_GROUP(BOOT_15),
356 348
357 GPIO_GROUP(CARD_0, EE_OFF), 349 GPIO_GROUP(CARD_0),
358 GPIO_GROUP(CARD_1, EE_OFF), 350 GPIO_GROUP(CARD_1),
359 GPIO_GROUP(CARD_2, EE_OFF), 351 GPIO_GROUP(CARD_2),
360 GPIO_GROUP(CARD_3, EE_OFF), 352 GPIO_GROUP(CARD_3),
361 GPIO_GROUP(CARD_4, EE_OFF), 353 GPIO_GROUP(CARD_4),
362 GPIO_GROUP(CARD_5, EE_OFF), 354 GPIO_GROUP(CARD_5),
363 GPIO_GROUP(CARD_6, EE_OFF), 355 GPIO_GROUP(CARD_6),
364 356
365 GPIO_GROUP(GPIODV_0, EE_OFF), 357 GPIO_GROUP(GPIODV_0),
366 GPIO_GROUP(GPIODV_1, EE_OFF), 358 GPIO_GROUP(GPIODV_1),
367 GPIO_GROUP(GPIODV_2, EE_OFF), 359 GPIO_GROUP(GPIODV_2),
368 GPIO_GROUP(GPIODV_3, EE_OFF), 360 GPIO_GROUP(GPIODV_3),
369 GPIO_GROUP(GPIODV_4, EE_OFF), 361 GPIO_GROUP(GPIODV_4),
370 GPIO_GROUP(GPIODV_5, EE_OFF), 362 GPIO_GROUP(GPIODV_5),
371 GPIO_GROUP(GPIODV_6, EE_OFF), 363 GPIO_GROUP(GPIODV_6),
372 GPIO_GROUP(GPIODV_7, EE_OFF), 364 GPIO_GROUP(GPIODV_7),
373 GPIO_GROUP(GPIODV_8, EE_OFF), 365 GPIO_GROUP(GPIODV_8),
374 GPIO_GROUP(GPIODV_9, EE_OFF), 366 GPIO_GROUP(GPIODV_9),
375 GPIO_GROUP(GPIODV_10, EE_OFF), 367 GPIO_GROUP(GPIODV_10),
376 GPIO_GROUP(GPIODV_11, EE_OFF), 368 GPIO_GROUP(GPIODV_11),
377 GPIO_GROUP(GPIODV_12, EE_OFF), 369 GPIO_GROUP(GPIODV_12),
378 GPIO_GROUP(GPIODV_13, EE_OFF), 370 GPIO_GROUP(GPIODV_13),
379 GPIO_GROUP(GPIODV_14, EE_OFF), 371 GPIO_GROUP(GPIODV_14),
380 GPIO_GROUP(GPIODV_15, EE_OFF), 372 GPIO_GROUP(GPIODV_15),
381 GPIO_GROUP(GPIODV_16, EE_OFF), 373 GPIO_GROUP(GPIODV_16),
382 GPIO_GROUP(GPIODV_17, EE_OFF), 374 GPIO_GROUP(GPIODV_17),
383 GPIO_GROUP(GPIODV_19, EE_OFF), 375 GPIO_GROUP(GPIODV_19),
384 GPIO_GROUP(GPIODV_20, EE_OFF), 376 GPIO_GROUP(GPIODV_20),
385 GPIO_GROUP(GPIODV_21, EE_OFF), 377 GPIO_GROUP(GPIODV_21),
386 GPIO_GROUP(GPIODV_22, EE_OFF), 378 GPIO_GROUP(GPIODV_22),
387 GPIO_GROUP(GPIODV_23, EE_OFF), 379 GPIO_GROUP(GPIODV_23),
388 GPIO_GROUP(GPIODV_24, EE_OFF), 380 GPIO_GROUP(GPIODV_24),
389 GPIO_GROUP(GPIODV_25, EE_OFF), 381 GPIO_GROUP(GPIODV_25),
390 GPIO_GROUP(GPIODV_26, EE_OFF), 382 GPIO_GROUP(GPIODV_26),
391 GPIO_GROUP(GPIODV_27, EE_OFF), 383 GPIO_GROUP(GPIODV_27),
392 GPIO_GROUP(GPIODV_28, EE_OFF), 384 GPIO_GROUP(GPIODV_28),
393 GPIO_GROUP(GPIODV_29, EE_OFF), 385 GPIO_GROUP(GPIODV_29),
394 386
395 GPIO_GROUP(GPIOX_0, EE_OFF), 387 GPIO_GROUP(GPIOX_0),
396 GPIO_GROUP(GPIOX_1, EE_OFF), 388 GPIO_GROUP(GPIOX_1),
397 GPIO_GROUP(GPIOX_2, EE_OFF), 389 GPIO_GROUP(GPIOX_2),
398 GPIO_GROUP(GPIOX_3, EE_OFF), 390 GPIO_GROUP(GPIOX_3),
399 GPIO_GROUP(GPIOX_4, EE_OFF), 391 GPIO_GROUP(GPIOX_4),
400 GPIO_GROUP(GPIOX_5, EE_OFF), 392 GPIO_GROUP(GPIOX_5),
401 GPIO_GROUP(GPIOX_6, EE_OFF), 393 GPIO_GROUP(GPIOX_6),
402 GPIO_GROUP(GPIOX_7, EE_OFF), 394 GPIO_GROUP(GPIOX_7),
403 GPIO_GROUP(GPIOX_8, EE_OFF), 395 GPIO_GROUP(GPIOX_8),
404 GPIO_GROUP(GPIOX_9, EE_OFF), 396 GPIO_GROUP(GPIOX_9),
405 GPIO_GROUP(GPIOX_10, EE_OFF), 397 GPIO_GROUP(GPIOX_10),
406 GPIO_GROUP(GPIOX_11, EE_OFF), 398 GPIO_GROUP(GPIOX_11),
407 GPIO_GROUP(GPIOX_12, EE_OFF), 399 GPIO_GROUP(GPIOX_12),
408 GPIO_GROUP(GPIOX_13, EE_OFF), 400 GPIO_GROUP(GPIOX_13),
409 GPIO_GROUP(GPIOX_14, EE_OFF), 401 GPIO_GROUP(GPIOX_14),
410 GPIO_GROUP(GPIOX_15, EE_OFF), 402 GPIO_GROUP(GPIOX_15),
411 GPIO_GROUP(GPIOX_16, EE_OFF), 403 GPIO_GROUP(GPIOX_16),
412 GPIO_GROUP(GPIOX_17, EE_OFF), 404 GPIO_GROUP(GPIOX_17),
413 GPIO_GROUP(GPIOX_18, EE_OFF), 405 GPIO_GROUP(GPIOX_18),
414 406
415 GPIO_GROUP(GPIOCLK_0, EE_OFF), 407 GPIO_GROUP(GPIOCLK_0),
416 GPIO_GROUP(GPIOCLK_1, EE_OFF), 408 GPIO_GROUP(GPIOCLK_1),
417 409
418 GPIO_GROUP(GPIO_TEST_N, EE_OFF), 410 GPIO_GROUP(GPIO_TEST_N),
419 411
420 /* Bank X */ 412 /* Bank X */
421 GROUP(sdio_d0, 5, 31), 413 GROUP(sdio_d0, 5, 31),
@@ -530,16 +522,16 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = {
530}; 522};
531 523
532static struct meson_pmx_group meson_gxl_aobus_groups[] = { 524static struct meson_pmx_group meson_gxl_aobus_groups[] = {
533 GPIO_GROUP(GPIOAO_0, 0), 525 GPIO_GROUP(GPIOAO_0),
534 GPIO_GROUP(GPIOAO_1, 0), 526 GPIO_GROUP(GPIOAO_1),
535 GPIO_GROUP(GPIOAO_2, 0), 527 GPIO_GROUP(GPIOAO_2),
536 GPIO_GROUP(GPIOAO_3, 0), 528 GPIO_GROUP(GPIOAO_3),
537 GPIO_GROUP(GPIOAO_4, 0), 529 GPIO_GROUP(GPIOAO_4),
538 GPIO_GROUP(GPIOAO_5, 0), 530 GPIO_GROUP(GPIOAO_5),
539 GPIO_GROUP(GPIOAO_6, 0), 531 GPIO_GROUP(GPIOAO_6),
540 GPIO_GROUP(GPIOAO_7, 0), 532 GPIO_GROUP(GPIOAO_7),
541 GPIO_GROUP(GPIOAO_8, 0), 533 GPIO_GROUP(GPIOAO_8),
542 GPIO_GROUP(GPIOAO_9, 0), 534 GPIO_GROUP(GPIOAO_9),
543 535
544 /* bank AO */ 536 /* bank AO */
545 GROUP(uart_tx_ao_b_0, 0, 26), 537 GROUP(uart_tx_ao_b_0, 0, 26),
@@ -567,6 +559,9 @@ static struct meson_pmx_group meson_gxl_aobus_groups[] = {
567 GROUP(spdif_out_ao_9, 0, 4), 559 GROUP(spdif_out_ao_9, 0, 4),
568 GROUP(ao_cec, 0, 15), 560 GROUP(ao_cec, 0, 15),
569 GROUP(ee_cec, 0, 14), 561 GROUP(ee_cec, 0, 14),
562
563 /* test n pin */
564 GROUP(i2s_out_ch67_ao, 1, 2),
570}; 565};
571 566
572static const char * const gpio_periphs_groups[] = { 567static const char * const gpio_periphs_groups[] = {
@@ -597,8 +592,6 @@ static const char * const gpio_periphs_groups[] = {
597 "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", 592 "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
598 "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", 593 "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
599 "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", 594 "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18",
600
601 "GPIO_TEST_N",
602}; 595};
603 596
604static const char * const emmc_groups[] = { 597static const char * const emmc_groups[] = {
@@ -713,6 +706,8 @@ static const char * const tsin_a_groups[] = {
713static const char * const gpio_aobus_groups[] = { 706static const char * const gpio_aobus_groups[] = {
714 "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", 707 "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
715 "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", 708 "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
709
710 "GPIO_TEST_N",
716}; 711};
717 712
718static const char * const uart_ao_groups[] = { 713static const char * const uart_ao_groups[] = {
@@ -745,7 +740,7 @@ static const char * const pwm_ao_b_groups[] = {
745}; 740};
746 741
747static const char * const i2s_out_ao_groups[] = { 742static const char * const i2s_out_ao_groups[] = {
748 "i2s_out_ch23_ao", "i2s_out_ch45_ao", 743 "i2s_out_ch23_ao", "i2s_out_ch45_ao", "i2s_out_ch67_ao",
749}; 744};
750 745
751static const char * const spdif_out_ao_groups[] = { 746static const char * const spdif_out_ao_groups[] = {
@@ -800,24 +795,23 @@ static struct meson_pmx_func meson_gxl_aobus_functions[] = {
800}; 795};
801 796
802static struct meson_bank meson_gxl_periphs_banks[] = { 797static struct meson_bank meson_gxl_periphs_banks[] = {
803 /* name first last irq pullen pull dir out in */ 798 /* name first last irq pullen pull dir out in */
804 BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_18, EE_OFF), 89, 107, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), 799 BANK("X", GPIOX_0, GPIOX_18, 89, 107, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
805 BANK("DV", PIN(GPIODV_0, EE_OFF), PIN(GPIODV_29, EE_OFF), 83, 88, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), 800 BANK("DV", GPIODV_0, GPIODV_29, 83, 88, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
806 BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_9, EE_OFF), 26, 35, 1, 20, 1, 20, 3, 20, 4, 20, 5, 20), 801 BANK("H", GPIOH_0, GPIOH_9, 26, 35, 1, 20, 1, 20, 3, 20, 4, 20, 5, 20),
807 BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 10, 25, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), 802 BANK("Z", GPIOZ_0, GPIOZ_15, 10, 25, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
808 BANK("CARD", PIN(CARD_0, EE_OFF), PIN(CARD_6, EE_OFF), 52, 58, 2, 20, 2, 20, 6, 20, 7, 20, 8, 20), 803 BANK("CARD", CARD_0, CARD_6, 52, 58, 2, 20, 2, 20, 6, 20, 7, 20, 8, 20),
809 BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_15, EE_OFF), 36, 51, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), 804 BANK("BOOT", BOOT_0, BOOT_15, 36, 51, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
810 BANK("CLK", PIN(GPIOCLK_0, EE_OFF), PIN(GPIOCLK_1, EE_OFF), 108, 109, 3, 28, 3, 28, 9, 28, 10, 28, 11, 28), 805 BANK("CLK", GPIOCLK_0, GPIOCLK_1, 108, 109, 3, 28, 3, 28, 9, 28, 10, 28, 11, 28),
811}; 806};
812 807
813static struct meson_bank meson_gxl_aobus_banks[] = { 808static struct meson_bank meson_gxl_aobus_banks[] = {
814 /* name first last irq pullen pull dir out in */ 809 /* name first last irq pullen pull dir out in */
815 BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_9, 0), 0, 9, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), 810 BANK("AO", GPIOAO_0, GPIOAO_9, 0, 9, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
816}; 811};
817 812
818struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = { 813static struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = {
819 .name = "periphs-banks", 814 .name = "periphs-banks",
820 .pin_base = 10,
821 .pins = meson_gxl_periphs_pins, 815 .pins = meson_gxl_periphs_pins,
822 .groups = meson_gxl_periphs_groups, 816 .groups = meson_gxl_periphs_groups,
823 .funcs = meson_gxl_periphs_functions, 817 .funcs = meson_gxl_periphs_functions,
@@ -826,11 +820,11 @@ struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = {
826 .num_groups = ARRAY_SIZE(meson_gxl_periphs_groups), 820 .num_groups = ARRAY_SIZE(meson_gxl_periphs_groups),
827 .num_funcs = ARRAY_SIZE(meson_gxl_periphs_functions), 821 .num_funcs = ARRAY_SIZE(meson_gxl_periphs_functions),
828 .num_banks = ARRAY_SIZE(meson_gxl_periphs_banks), 822 .num_banks = ARRAY_SIZE(meson_gxl_periphs_banks),
823 .pmx_ops = &meson8_pmx_ops,
829}; 824};
830 825
831struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = { 826static struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = {
832 .name = "aobus-banks", 827 .name = "aobus-banks",
833 .pin_base = 0,
834 .pins = meson_gxl_aobus_pins, 828 .pins = meson_gxl_aobus_pins,
835 .groups = meson_gxl_aobus_groups, 829 .groups = meson_gxl_aobus_groups,
836 .funcs = meson_gxl_aobus_functions, 830 .funcs = meson_gxl_aobus_functions,
@@ -839,4 +833,26 @@ struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data = {
839 .num_groups = ARRAY_SIZE(meson_gxl_aobus_groups), 833 .num_groups = ARRAY_SIZE(meson_gxl_aobus_groups),
840 .num_funcs = ARRAY_SIZE(meson_gxl_aobus_functions), 834 .num_funcs = ARRAY_SIZE(meson_gxl_aobus_functions),
841 .num_banks = ARRAY_SIZE(meson_gxl_aobus_banks), 835 .num_banks = ARRAY_SIZE(meson_gxl_aobus_banks),
836 .pmx_ops = &meson8_pmx_ops,
837};
838
839static const struct of_device_id meson_gxl_pinctrl_dt_match[] = {
840 {
841 .compatible = "amlogic,meson-gxl-periphs-pinctrl",
842 .data = &meson_gxl_periphs_pinctrl_data,
843 },
844 {
845 .compatible = "amlogic,meson-gxl-aobus-pinctrl",
846 .data = &meson_gxl_aobus_pinctrl_data,
847 },
848 { },
849};
850
851static struct platform_driver meson_gxl_pinctrl_driver = {
852 .probe = meson_pinctrl_probe,
853 .driver = {
854 .name = "meson-gxl-pinctrl",
855 .of_match_table = meson_gxl_pinctrl_dt_match,
856 },
842}; 857};
858builtin_platform_driver(meson_gxl_pinctrl_driver);
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index 66ed70c12733..29a458da78db 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -31,10 +31,6 @@
31 * In some cases the register ranges for pull enable and pull 31 * In some cases the register ranges for pull enable and pull
32 * direction are the same and thus there are only 3 register ranges. 32 * direction are the same and thus there are only 3 register ranges.
33 * 33 *
34 * Every pinmux group can be enabled by a specific bit in the first
35 * register range; when all groups for a given pin are disabled the
36 * pin acts as a GPIO.
37 *
38 * For the pull and GPIO configuration every bank uses a contiguous 34 * For the pull and GPIO configuration every bank uses a contiguous
39 * set of bits in the register sets described above; the same register 35 * set of bits in the register sets described above; the same register
40 * can be shared by more banks with different offsets. 36 * can be shared by more banks with different offsets.
@@ -50,6 +46,7 @@
50#include <linux/io.h> 46#include <linux/io.h>
51#include <linux/of.h> 47#include <linux/of.h>
52#include <linux/of_address.h> 48#include <linux/of_address.h>
49#include <linux/of_device.h>
53#include <linux/pinctrl/pinconf-generic.h> 50#include <linux/pinctrl/pinconf-generic.h>
54#include <linux/pinctrl/pinconf.h> 51#include <linux/pinctrl/pinconf.h>
55#include <linux/pinctrl/pinctrl.h> 52#include <linux/pinctrl/pinctrl.h>
@@ -147,94 +144,24 @@ static const struct pinctrl_ops meson_pctrl_ops = {
147 .pin_dbg_show = meson_pin_dbg_show, 144 .pin_dbg_show = meson_pin_dbg_show,
148}; 145};
149 146
150/** 147int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev)
151 * meson_pmx_disable_other_groups() - disable other groups using a given pin
152 *
153 * @pc: meson pin controller device
154 * @pin: number of the pin
155 * @sel_group: index of the selected group, or -1 if none
156 *
157 * The function disables all pinmux groups using a pin except the
158 * selected one. If @sel_group is -1 all groups are disabled, leaving
159 * the pin in GPIO mode.
160 */
161static void meson_pmx_disable_other_groups(struct meson_pinctrl *pc,
162 unsigned int pin, int sel_group)
163{
164 struct meson_pmx_group *group;
165 int i, j;
166
167 for (i = 0; i < pc->data->num_groups; i++) {
168 group = &pc->data->groups[i];
169 if (group->is_gpio || i == sel_group)
170 continue;
171
172 for (j = 0; j < group->num_pins; j++) {
173 if (group->pins[j] == pin) {
174 /* We have found a group using the pin */
175 regmap_update_bits(pc->reg_mux,
176 group->reg * 4,
177 BIT(group->bit), 0);
178 }
179 }
180 }
181}
182
183static int meson_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num,
184 unsigned group_num)
185{
186 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
187 struct meson_pmx_func *func = &pc->data->funcs[func_num];
188 struct meson_pmx_group *group = &pc->data->groups[group_num];
189 int i, ret = 0;
190
191 dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
192 group->name);
193
194 /*
195 * Disable groups using the same pin.
196 * The selected group is not disabled to avoid glitches.
197 */
198 for (i = 0; i < group->num_pins; i++)
199 meson_pmx_disable_other_groups(pc, group->pins[i], group_num);
200
201 /* Function 0 (GPIO) doesn't need any additional setting */
202 if (func_num)
203 ret = regmap_update_bits(pc->reg_mux, group->reg * 4,
204 BIT(group->bit), BIT(group->bit));
205
206 return ret;
207}
208
209static int meson_pmx_request_gpio(struct pinctrl_dev *pcdev,
210 struct pinctrl_gpio_range *range,
211 unsigned offset)
212{
213 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
214
215 meson_pmx_disable_other_groups(pc, offset, -1);
216
217 return 0;
218}
219
220static int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev)
221{ 148{
222 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 149 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
223 150
224 return pc->data->num_funcs; 151 return pc->data->num_funcs;
225} 152}
226 153
227static const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, 154const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
228 unsigned selector) 155 unsigned selector)
229{ 156{
230 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 157 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
231 158
232 return pc->data->funcs[selector].name; 159 return pc->data->funcs[selector].name;
233} 160}
234 161
235static int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector, 162int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector,
236 const char * const **groups, 163 const char * const **groups,
237 unsigned * const num_groups) 164 unsigned * const num_groups)
238{ 165{
239 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev); 166 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
240 167
@@ -244,14 +171,6 @@ static int meson_pmx_get_groups(struct pinctrl_dev *pcdev, unsigned selector,
244 return 0; 171 return 0;
245} 172}
246 173
247static const struct pinmux_ops meson_pmx_ops = {
248 .set_mux = meson_pmx_set_mux,
249 .get_functions_count = meson_pmx_get_funcs_count,
250 .get_function_name = meson_pmx_get_func_name,
251 .get_function_groups = meson_pmx_get_groups,
252 .gpio_request_enable = meson_pmx_request_gpio,
253};
254
255static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin, 174static int meson_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
256 unsigned long *configs, unsigned num_configs) 175 unsigned long *configs, unsigned num_configs)
257{ 176{
@@ -399,7 +318,7 @@ static int meson_pinconf_group_set(struct pinctrl_dev *pcdev,
399static int meson_pinconf_group_get(struct pinctrl_dev *pcdev, 318static int meson_pinconf_group_get(struct pinctrl_dev *pcdev,
400 unsigned int group, unsigned long *config) 319 unsigned int group, unsigned long *config)
401{ 320{
402 return -ENOSYS; 321 return -ENOTSUPP;
403} 322}
404 323
405static const struct pinconf_ops meson_pinconf_ops = { 324static const struct pinconf_ops meson_pinconf_ops = {
@@ -410,31 +329,18 @@ static const struct pinconf_ops meson_pinconf_ops = {
410 .is_generic = true, 329 .is_generic = true,
411}; 330};
412 331
413static int meson_gpio_request(struct gpio_chip *chip, unsigned gpio)
414{
415 return pinctrl_request_gpio(chip->base + gpio);
416}
417
418static void meson_gpio_free(struct gpio_chip *chip, unsigned gpio)
419{
420 struct meson_pinctrl *pc = gpiochip_get_data(chip);
421
422 pinctrl_free_gpio(pc->data->pin_base + gpio);
423}
424
425static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 332static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
426{ 333{
427 struct meson_pinctrl *pc = gpiochip_get_data(chip); 334 struct meson_pinctrl *pc = gpiochip_get_data(chip);
428 unsigned int reg, bit, pin; 335 unsigned int reg, bit;
429 struct meson_bank *bank; 336 struct meson_bank *bank;
430 int ret; 337 int ret;
431 338
432 pin = pc->data->pin_base + gpio; 339 ret = meson_get_bank(pc, gpio, &bank);
433 ret = meson_get_bank(pc, pin, &bank);
434 if (ret) 340 if (ret)
435 return ret; 341 return ret;
436 342
437 meson_calc_reg_and_bit(bank, pin, REG_DIR, &reg, &bit); 343 meson_calc_reg_and_bit(bank, gpio, REG_DIR, &reg, &bit);
438 344
439 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), BIT(bit)); 345 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), BIT(bit));
440} 346}
@@ -443,21 +349,20 @@ static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
443 int value) 349 int value)
444{ 350{
445 struct meson_pinctrl *pc = gpiochip_get_data(chip); 351 struct meson_pinctrl *pc = gpiochip_get_data(chip);
446 unsigned int reg, bit, pin; 352 unsigned int reg, bit;
447 struct meson_bank *bank; 353 struct meson_bank *bank;
448 int ret; 354 int ret;
449 355
450 pin = pc->data->pin_base + gpio; 356 ret = meson_get_bank(pc, gpio, &bank);
451 ret = meson_get_bank(pc, pin, &bank);
452 if (ret) 357 if (ret)
453 return ret; 358 return ret;
454 359
455 meson_calc_reg_and_bit(bank, pin, REG_DIR, &reg, &bit); 360 meson_calc_reg_and_bit(bank, gpio, REG_DIR, &reg, &bit);
456 ret = regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 0); 361 ret = regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 0);
457 if (ret) 362 if (ret)
458 return ret; 363 return ret;
459 364
460 meson_calc_reg_and_bit(bank, pin, REG_OUT, &reg, &bit); 365 meson_calc_reg_and_bit(bank, gpio, REG_OUT, &reg, &bit);
461 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 366 return regmap_update_bits(pc->reg_gpio, reg, BIT(bit),
462 value ? BIT(bit) : 0); 367 value ? BIT(bit) : 0);
463} 368}
@@ -465,16 +370,15 @@ static int meson_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
465static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) 370static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
466{ 371{
467 struct meson_pinctrl *pc = gpiochip_get_data(chip); 372 struct meson_pinctrl *pc = gpiochip_get_data(chip);
468 unsigned int reg, bit, pin; 373 unsigned int reg, bit;
469 struct meson_bank *bank; 374 struct meson_bank *bank;
470 int ret; 375 int ret;
471 376
472 pin = pc->data->pin_base + gpio; 377 ret = meson_get_bank(pc, gpio, &bank);
473 ret = meson_get_bank(pc, pin, &bank);
474 if (ret) 378 if (ret)
475 return; 379 return;
476 380
477 meson_calc_reg_and_bit(bank, pin, REG_OUT, &reg, &bit); 381 meson_calc_reg_and_bit(bank, gpio, REG_OUT, &reg, &bit);
478 regmap_update_bits(pc->reg_gpio, reg, BIT(bit), 382 regmap_update_bits(pc->reg_gpio, reg, BIT(bit),
479 value ? BIT(bit) : 0); 383 value ? BIT(bit) : 0);
480} 384}
@@ -482,70 +386,33 @@ static void meson_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
482static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio) 386static int meson_gpio_get(struct gpio_chip *chip, unsigned gpio)
483{ 387{
484 struct meson_pinctrl *pc = gpiochip_get_data(chip); 388 struct meson_pinctrl *pc = gpiochip_get_data(chip);
485 unsigned int reg, bit, val, pin; 389 unsigned int reg, bit, val;
486 struct meson_bank *bank; 390 struct meson_bank *bank;
487 int ret; 391 int ret;
488 392
489 pin = pc->data->pin_base + gpio; 393 ret = meson_get_bank(pc, gpio, &bank);
490 ret = meson_get_bank(pc, pin, &bank);
491 if (ret) 394 if (ret)
492 return ret; 395 return ret;
493 396
494 meson_calc_reg_and_bit(bank, pin, REG_IN, &reg, &bit); 397 meson_calc_reg_and_bit(bank, gpio, REG_IN, &reg, &bit);
495 regmap_read(pc->reg_gpio, reg, &val); 398 regmap_read(pc->reg_gpio, reg, &val);
496 399
497 return !!(val & BIT(bit)); 400 return !!(val & BIT(bit));
498} 401}
499 402
500static const struct of_device_id meson_pinctrl_dt_match[] = {
501 {
502 .compatible = "amlogic,meson8-cbus-pinctrl",
503 .data = &meson8_cbus_pinctrl_data,
504 },
505 {
506 .compatible = "amlogic,meson8b-cbus-pinctrl",
507 .data = &meson8b_cbus_pinctrl_data,
508 },
509 {
510 .compatible = "amlogic,meson8-aobus-pinctrl",
511 .data = &meson8_aobus_pinctrl_data,
512 },
513 {
514 .compatible = "amlogic,meson8b-aobus-pinctrl",
515 .data = &meson8b_aobus_pinctrl_data,
516 },
517 {
518 .compatible = "amlogic,meson-gxbb-periphs-pinctrl",
519 .data = &meson_gxbb_periphs_pinctrl_data,
520 },
521 {
522 .compatible = "amlogic,meson-gxbb-aobus-pinctrl",
523 .data = &meson_gxbb_aobus_pinctrl_data,
524 },
525 {
526 .compatible = "amlogic,meson-gxl-periphs-pinctrl",
527 .data = &meson_gxl_periphs_pinctrl_data,
528 },
529 {
530 .compatible = "amlogic,meson-gxl-aobus-pinctrl",
531 .data = &meson_gxl_aobus_pinctrl_data,
532 },
533 { },
534};
535
536static int meson_gpiolib_register(struct meson_pinctrl *pc) 403static int meson_gpiolib_register(struct meson_pinctrl *pc)
537{ 404{
538 int ret; 405 int ret;
539 406
540 pc->chip.label = pc->data->name; 407 pc->chip.label = pc->data->name;
541 pc->chip.parent = pc->dev; 408 pc->chip.parent = pc->dev;
542 pc->chip.request = meson_gpio_request; 409 pc->chip.request = gpiochip_generic_request;
543 pc->chip.free = meson_gpio_free; 410 pc->chip.free = gpiochip_generic_free;
544 pc->chip.direction_input = meson_gpio_direction_input; 411 pc->chip.direction_input = meson_gpio_direction_input;
545 pc->chip.direction_output = meson_gpio_direction_output; 412 pc->chip.direction_output = meson_gpio_direction_output;
546 pc->chip.get = meson_gpio_get; 413 pc->chip.get = meson_gpio_get;
547 pc->chip.set = meson_gpio_set; 414 pc->chip.set = meson_gpio_set;
548 pc->chip.base = pc->data->pin_base; 415 pc->chip.base = -1;
549 pc->chip.ngpio = pc->data->num_pins; 416 pc->chip.ngpio = pc->data->num_pins;
550 pc->chip.can_sleep = false; 417 pc->chip.can_sleep = false;
551 pc->chip.of_node = pc->of_node; 418 pc->chip.of_node = pc->of_node;
@@ -640,9 +507,8 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc,
640 return 0; 507 return 0;
641} 508}
642 509
643static int meson_pinctrl_probe(struct platform_device *pdev) 510int meson_pinctrl_probe(struct platform_device *pdev)
644{ 511{
645 const struct of_device_id *match;
646 struct device *dev = &pdev->dev; 512 struct device *dev = &pdev->dev;
647 struct meson_pinctrl *pc; 513 struct meson_pinctrl *pc;
648 int ret; 514 int ret;
@@ -652,17 +518,16 @@ static int meson_pinctrl_probe(struct platform_device *pdev)
652 return -ENOMEM; 518 return -ENOMEM;
653 519
654 pc->dev = dev; 520 pc->dev = dev;
655 match = of_match_node(meson_pinctrl_dt_match, pdev->dev.of_node); 521 pc->data = (struct meson_pinctrl_data *) of_device_get_match_data(dev);
656 pc->data = (struct meson_pinctrl_data *) match->data;
657 522
658 ret = meson_pinctrl_parse_dt(pc, pdev->dev.of_node); 523 ret = meson_pinctrl_parse_dt(pc, dev->of_node);
659 if (ret) 524 if (ret)
660 return ret; 525 return ret;
661 526
662 pc->desc.name = "pinctrl-meson"; 527 pc->desc.name = "pinctrl-meson";
663 pc->desc.owner = THIS_MODULE; 528 pc->desc.owner = THIS_MODULE;
664 pc->desc.pctlops = &meson_pctrl_ops; 529 pc->desc.pctlops = &meson_pctrl_ops;
665 pc->desc.pmxops = &meson_pmx_ops; 530 pc->desc.pmxops = pc->data->pmx_ops;
666 pc->desc.confops = &meson_pinconf_ops; 531 pc->desc.confops = &meson_pinconf_ops;
667 pc->desc.pins = pc->data->pins; 532 pc->desc.pins = pc->data->pins;
668 pc->desc.npins = pc->data->num_pins; 533 pc->desc.npins = pc->data->num_pins;
@@ -675,12 +540,3 @@ static int meson_pinctrl_probe(struct platform_device *pdev)
675 540
676 return meson_gpiolib_register(pc); 541 return meson_gpiolib_register(pc);
677} 542}
678
679static struct platform_driver meson_pinctrl_driver = {
680 .probe = meson_pinctrl_probe,
681 .driver = {
682 .name = "meson-pinctrl",
683 .of_match_table = meson_pinctrl_dt_match,
684 },
685};
686builtin_platform_driver(meson_pinctrl_driver);
diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
index 890f296f5840..183b6e471635 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.h
+++ b/drivers/pinctrl/meson/pinctrl-meson.h
@@ -13,6 +13,7 @@
13 13
14#include <linux/gpio.h> 14#include <linux/gpio.h>
15#include <linux/pinctrl/pinctrl.h> 15#include <linux/pinctrl/pinctrl.h>
16#include <linux/platform_device.h>
16#include <linux/regmap.h> 17#include <linux/regmap.h>
17#include <linux/types.h> 18#include <linux/types.h>
18 19
@@ -31,9 +32,7 @@ struct meson_pmx_group {
31 const char *name; 32 const char *name;
32 const unsigned int *pins; 33 const unsigned int *pins;
33 unsigned int num_pins; 34 unsigned int num_pins;
34 bool is_gpio; 35 const void *data;
35 unsigned int reg;
36 unsigned int bit;
37}; 36};
38 37
39/** 38/**
@@ -103,12 +102,12 @@ struct meson_pinctrl_data {
103 const struct pinctrl_pin_desc *pins; 102 const struct pinctrl_pin_desc *pins;
104 struct meson_pmx_group *groups; 103 struct meson_pmx_group *groups;
105 struct meson_pmx_func *funcs; 104 struct meson_pmx_func *funcs;
106 unsigned int pin_base;
107 unsigned int num_pins; 105 unsigned int num_pins;
108 unsigned int num_groups; 106 unsigned int num_groups;
109 unsigned int num_funcs; 107 unsigned int num_funcs;
110 struct meson_bank *banks; 108 struct meson_bank *banks;
111 unsigned int num_banks; 109 unsigned int num_banks;
110 const struct pinmux_ops *pmx_ops;
112}; 111};
113 112
114struct meson_pinctrl { 113struct meson_pinctrl {
@@ -124,25 +123,6 @@ struct meson_pinctrl {
124 struct device_node *of_node; 123 struct device_node *of_node;
125}; 124};
126 125
127#define PIN(x, b) (b + x)
128
129#define GROUP(grp, r, b) \
130 { \
131 .name = #grp, \
132 .pins = grp ## _pins, \
133 .num_pins = ARRAY_SIZE(grp ## _pins), \
134 .reg = r, \
135 .bit = b, \
136 }
137
138#define GPIO_GROUP(gpio, b) \
139 { \
140 .name = #gpio, \
141 .pins = (const unsigned int[]){ PIN(gpio, b) }, \
142 .num_pins = 1, \
143 .is_gpio = true, \
144 }
145
146#define FUNCTION(fn) \ 126#define FUNCTION(fn) \
147 { \ 127 { \
148 .name = #fn, \ 128 .name = #fn, \
@@ -166,13 +146,16 @@ struct meson_pinctrl {
166 }, \ 146 }, \
167 } 147 }
168 148
169#define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x) 149#define MESON_PIN(x) PINCTRL_PIN(x, #x)
150
151/* Common pmx functions */
152int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev);
153const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev,
154 unsigned selector);
155int meson_pmx_get_groups(struct pinctrl_dev *pcdev,
156 unsigned selector,
157 const char * const **groups,
158 unsigned * const num_groups);
170 159
171extern struct meson_pinctrl_data meson8_cbus_pinctrl_data; 160/* Common probe function */
172extern struct meson_pinctrl_data meson8_aobus_pinctrl_data; 161int meson_pinctrl_probe(struct platform_device *pdev);
173extern struct meson_pinctrl_data meson8b_cbus_pinctrl_data;
174extern struct meson_pinctrl_data meson8b_aobus_pinctrl_data;
175extern struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data;
176extern struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data;
177extern struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data;
178extern struct meson_pinctrl_data meson_gxl_aobus_pinctrl_data;
diff --git a/drivers/pinctrl/meson/pinctrl-meson8-pmx.c b/drivers/pinctrl/meson/pinctrl-meson8-pmx.c
new file mode 100644
index 000000000000..b93b058c8a07
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson8-pmx.c
@@ -0,0 +1,108 @@
1/*
2 * First generation of pinmux driver for Amlogic Meson SoCs
3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 * Copyright (C) 2017 Jerome Brunet <jbrunet@baylibre.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program. If not, see <http://www.gnu.org/licenses/>.
13 */
14
15/* For this first generation of pinctrl driver every pinmux group can be
16 * enabled by a specific bit in the first register range. When all groups for
17 * a given pin are disabled the pin acts as a GPIO.
18 */
19#include <linux/device.h>
20#include <linux/regmap.h>
21#include <linux/pinctrl/pinctrl.h>
22#include <linux/pinctrl/pinmux.h>
23
24#include "pinctrl-meson.h"
25#include "pinctrl-meson8-pmx.h"
26
27/**
28 * meson8_pmx_disable_other_groups() - disable other groups using a given pin
29 *
30 * @pc: meson pin controller device
31 * @pin: number of the pin
32 * @sel_group: index of the selected group, or -1 if none
33 *
34 * The function disables all pinmux groups using a pin except the
35 * selected one. If @sel_group is -1 all groups are disabled, leaving
36 * the pin in GPIO mode.
37 */
38static void meson8_pmx_disable_other_groups(struct meson_pinctrl *pc,
39 unsigned int pin, int sel_group)
40{
41 struct meson_pmx_group *group;
42 struct meson8_pmx_data *pmx_data;
43 int i, j;
44
45 for (i = 0; i < pc->data->num_groups; i++) {
46 group = &pc->data->groups[i];
47 pmx_data = (struct meson8_pmx_data *)group->data;
48 if (pmx_data->is_gpio || i == sel_group)
49 continue;
50
51 for (j = 0; j < group->num_pins; j++) {
52 if (group->pins[j] == pin) {
53 /* We have found a group using the pin */
54 regmap_update_bits(pc->reg_mux,
55 pmx_data->reg * 4,
56 BIT(pmx_data->bit), 0);
57 }
58 }
59 }
60}
61
62static int meson8_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num,
63 unsigned group_num)
64{
65 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
66 struct meson_pmx_func *func = &pc->data->funcs[func_num];
67 struct meson_pmx_group *group = &pc->data->groups[group_num];
68 struct meson8_pmx_data *pmx_data =
69 (struct meson8_pmx_data *)group->data;
70 int i, ret = 0;
71
72 dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
73 group->name);
74
75 /*
76 * Disable groups using the same pin.
77 * The selected group is not disabled to avoid glitches.
78 */
79 for (i = 0; i < group->num_pins; i++)
80 meson8_pmx_disable_other_groups(pc, group->pins[i], group_num);
81
82 /* Function 0 (GPIO) doesn't need any additional setting */
83 if (func_num)
84 ret = regmap_update_bits(pc->reg_mux, pmx_data->reg * 4,
85 BIT(pmx_data->bit),
86 BIT(pmx_data->bit));
87
88 return ret;
89}
90
91static int meson8_pmx_request_gpio(struct pinctrl_dev *pcdev,
92 struct pinctrl_gpio_range *range,
93 unsigned offset)
94{
95 struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
96
97 meson8_pmx_disable_other_groups(pc, offset, -1);
98
99 return 0;
100}
101
102const struct pinmux_ops meson8_pmx_ops = {
103 .set_mux = meson8_pmx_set_mux,
104 .get_functions_count = meson_pmx_get_funcs_count,
105 .get_function_name = meson_pmx_get_func_name,
106 .get_function_groups = meson_pmx_get_groups,
107 .gpio_request_enable = meson8_pmx_request_gpio,
108};
diff --git a/drivers/pinctrl/meson/pinctrl-meson8-pmx.h b/drivers/pinctrl/meson/pinctrl-meson8-pmx.h
new file mode 100644
index 000000000000..47293c28f913
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson8-pmx.h
@@ -0,0 +1,48 @@
1/*
2 * First generation of pinmux driver for Amlogic Meson SoCs
3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 * Copyright (C) 2017 Jerome Brunet <jbrunet@baylibre.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program. If not, see <http://www.gnu.org/licenses/>.
13 */
14
15struct meson8_pmx_data {
16 bool is_gpio;
17 unsigned int reg;
18 unsigned int bit;
19};
20
21#define PMX_DATA(r, b, g) \
22 { \
23 .reg = r, \
24 .bit = b, \
25 .is_gpio = g, \
26 }
27
28#define GROUP(grp, r, b) \
29 { \
30 .name = #grp, \
31 .pins = grp ## _pins, \
32 .num_pins = ARRAY_SIZE(grp ## _pins), \
33 .data = (const struct meson8_pmx_data[]){ \
34 PMX_DATA(r, b, false), \
35 }, \
36 }
37
38#define GPIO_GROUP(gpio) \
39 { \
40 .name = #gpio, \
41 .pins = (const unsigned int[]){ gpio }, \
42 .num_pins = 1, \
43 .data = (const struct meson8_pmx_data[]){ \
44 PMX_DATA(0, 0, true), \
45 }, \
46 }
47
48extern const struct pinmux_ops meson8_pmx_ops;
diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c
index 970f6f14502c..49c7ce03547b 100644
--- a/drivers/pinctrl/meson/pinctrl-meson8.c
+++ b/drivers/pinctrl/meson/pinctrl-meson8.c
@@ -13,506 +13,495 @@
13 13
14#include <dt-bindings/gpio/meson8-gpio.h> 14#include <dt-bindings/gpio/meson8-gpio.h>
15#include "pinctrl-meson.h" 15#include "pinctrl-meson.h"
16 16#include "pinctrl-meson8-pmx.h"
17#define AO_OFF 120
18 17
19static const struct pinctrl_pin_desc meson8_cbus_pins[] = { 18static const struct pinctrl_pin_desc meson8_cbus_pins[] = {
20 MESON_PIN(GPIOX_0, 0), 19 MESON_PIN(GPIOX_0),
21 MESON_PIN(GPIOX_1, 0), 20 MESON_PIN(GPIOX_1),
22 MESON_PIN(GPIOX_2, 0), 21 MESON_PIN(GPIOX_2),
23 MESON_PIN(GPIOX_3, 0), 22 MESON_PIN(GPIOX_3),
24 MESON_PIN(GPIOX_4, 0), 23 MESON_PIN(GPIOX_4),
25 MESON_PIN(GPIOX_5, 0), 24 MESON_PIN(GPIOX_5),
26 MESON_PIN(GPIOX_6, 0), 25 MESON_PIN(GPIOX_6),
27 MESON_PIN(GPIOX_7, 0), 26 MESON_PIN(GPIOX_7),
28 MESON_PIN(GPIOX_8, 0), 27 MESON_PIN(GPIOX_8),
29 MESON_PIN(GPIOX_9, 0), 28 MESON_PIN(GPIOX_9),
30 MESON_PIN(GPIOX_10, 0), 29 MESON_PIN(GPIOX_10),
31 MESON_PIN(GPIOX_11, 0), 30 MESON_PIN(GPIOX_11),
32 MESON_PIN(GPIOX_12, 0), 31 MESON_PIN(GPIOX_12),
33 MESON_PIN(GPIOX_13, 0), 32 MESON_PIN(GPIOX_13),
34 MESON_PIN(GPIOX_14, 0), 33 MESON_PIN(GPIOX_14),
35 MESON_PIN(GPIOX_15, 0), 34 MESON_PIN(GPIOX_15),
36 MESON_PIN(GPIOX_16, 0), 35 MESON_PIN(GPIOX_16),
37 MESON_PIN(GPIOX_17, 0), 36 MESON_PIN(GPIOX_17),
38 MESON_PIN(GPIOX_18, 0), 37 MESON_PIN(GPIOX_18),
39 MESON_PIN(GPIOX_19, 0), 38 MESON_PIN(GPIOX_19),
40 MESON_PIN(GPIOX_20, 0), 39 MESON_PIN(GPIOX_20),
41 MESON_PIN(GPIOX_21, 0), 40 MESON_PIN(GPIOX_21),
42 MESON_PIN(GPIOY_0, 0), 41 MESON_PIN(GPIOY_0),
43 MESON_PIN(GPIOY_1, 0), 42 MESON_PIN(GPIOY_1),
44 MESON_PIN(GPIOY_2, 0), 43 MESON_PIN(GPIOY_2),
45 MESON_PIN(GPIOY_3, 0), 44 MESON_PIN(GPIOY_3),
46 MESON_PIN(GPIOY_4, 0), 45 MESON_PIN(GPIOY_4),
47 MESON_PIN(GPIOY_5, 0), 46 MESON_PIN(GPIOY_5),
48 MESON_PIN(GPIOY_6, 0), 47 MESON_PIN(GPIOY_6),
49 MESON_PIN(GPIOY_7, 0), 48 MESON_PIN(GPIOY_7),
50 MESON_PIN(GPIOY_8, 0), 49 MESON_PIN(GPIOY_8),
51 MESON_PIN(GPIOY_9, 0), 50 MESON_PIN(GPIOY_9),
52 MESON_PIN(GPIOY_10, 0), 51 MESON_PIN(GPIOY_10),
53 MESON_PIN(GPIOY_11, 0), 52 MESON_PIN(GPIOY_11),
54 MESON_PIN(GPIOY_12, 0), 53 MESON_PIN(GPIOY_12),
55 MESON_PIN(GPIOY_13, 0), 54 MESON_PIN(GPIOY_13),
56 MESON_PIN(GPIOY_14, 0), 55 MESON_PIN(GPIOY_14),
57 MESON_PIN(GPIOY_15, 0), 56 MESON_PIN(GPIOY_15),
58 MESON_PIN(GPIOY_16, 0), 57 MESON_PIN(GPIOY_16),
59 MESON_PIN(GPIODV_0, 0), 58 MESON_PIN(GPIODV_0),
60 MESON_PIN(GPIODV_1, 0), 59 MESON_PIN(GPIODV_1),
61 MESON_PIN(GPIODV_2, 0), 60 MESON_PIN(GPIODV_2),
62 MESON_PIN(GPIODV_3, 0), 61 MESON_PIN(GPIODV_3),
63 MESON_PIN(GPIODV_4, 0), 62 MESON_PIN(GPIODV_4),
64 MESON_PIN(GPIODV_5, 0), 63 MESON_PIN(GPIODV_5),
65 MESON_PIN(GPIODV_6, 0), 64 MESON_PIN(GPIODV_6),
66 MESON_PIN(GPIODV_7, 0), 65 MESON_PIN(GPIODV_7),
67 MESON_PIN(GPIODV_8, 0), 66 MESON_PIN(GPIODV_8),
68 MESON_PIN(GPIODV_9, 0), 67 MESON_PIN(GPIODV_9),
69 MESON_PIN(GPIODV_10, 0), 68 MESON_PIN(GPIODV_10),
70 MESON_PIN(GPIODV_11, 0), 69 MESON_PIN(GPIODV_11),
71 MESON_PIN(GPIODV_12, 0), 70 MESON_PIN(GPIODV_12),
72 MESON_PIN(GPIODV_13, 0), 71 MESON_PIN(GPIODV_13),
73 MESON_PIN(GPIODV_14, 0), 72 MESON_PIN(GPIODV_14),
74 MESON_PIN(GPIODV_15, 0), 73 MESON_PIN(GPIODV_15),
75 MESON_PIN(GPIODV_16, 0), 74 MESON_PIN(GPIODV_16),
76 MESON_PIN(GPIODV_17, 0), 75 MESON_PIN(GPIODV_17),
77 MESON_PIN(GPIODV_18, 0), 76 MESON_PIN(GPIODV_18),
78 MESON_PIN(GPIODV_19, 0), 77 MESON_PIN(GPIODV_19),
79 MESON_PIN(GPIODV_20, 0), 78 MESON_PIN(GPIODV_20),
80 MESON_PIN(GPIODV_21, 0), 79 MESON_PIN(GPIODV_21),
81 MESON_PIN(GPIODV_22, 0), 80 MESON_PIN(GPIODV_22),
82 MESON_PIN(GPIODV_23, 0), 81 MESON_PIN(GPIODV_23),
83 MESON_PIN(GPIODV_24, 0), 82 MESON_PIN(GPIODV_24),
84 MESON_PIN(GPIODV_25, 0), 83 MESON_PIN(GPIODV_25),
85 MESON_PIN(GPIODV_26, 0), 84 MESON_PIN(GPIODV_26),
86 MESON_PIN(GPIODV_27, 0), 85 MESON_PIN(GPIODV_27),
87 MESON_PIN(GPIODV_28, 0), 86 MESON_PIN(GPIODV_28),
88 MESON_PIN(GPIODV_29, 0), 87 MESON_PIN(GPIODV_29),
89 MESON_PIN(GPIOH_0, 0), 88 MESON_PIN(GPIOH_0),
90 MESON_PIN(GPIOH_1, 0), 89 MESON_PIN(GPIOH_1),
91 MESON_PIN(GPIOH_2, 0), 90 MESON_PIN(GPIOH_2),
92 MESON_PIN(GPIOH_3, 0), 91 MESON_PIN(GPIOH_3),
93 MESON_PIN(GPIOH_4, 0), 92 MESON_PIN(GPIOH_4),
94 MESON_PIN(GPIOH_5, 0), 93 MESON_PIN(GPIOH_5),
95 MESON_PIN(GPIOH_6, 0), 94 MESON_PIN(GPIOH_6),
96 MESON_PIN(GPIOH_7, 0), 95 MESON_PIN(GPIOH_7),
97 MESON_PIN(GPIOH_8, 0), 96 MESON_PIN(GPIOH_8),
98 MESON_PIN(GPIOH_9, 0), 97 MESON_PIN(GPIOH_9),
99 MESON_PIN(GPIOZ_0, 0), 98 MESON_PIN(GPIOZ_0),
100 MESON_PIN(GPIOZ_1, 0), 99 MESON_PIN(GPIOZ_1),
101 MESON_PIN(GPIOZ_2, 0), 100 MESON_PIN(GPIOZ_2),
102 MESON_PIN(GPIOZ_3, 0), 101 MESON_PIN(GPIOZ_3),
103 MESON_PIN(GPIOZ_4, 0), 102 MESON_PIN(GPIOZ_4),
104 MESON_PIN(GPIOZ_5, 0), 103 MESON_PIN(GPIOZ_5),
105 MESON_PIN(GPIOZ_6, 0), 104 MESON_PIN(GPIOZ_6),
106 MESON_PIN(GPIOZ_7, 0), 105 MESON_PIN(GPIOZ_7),
107 MESON_PIN(GPIOZ_8, 0), 106 MESON_PIN(GPIOZ_8),
108 MESON_PIN(GPIOZ_9, 0), 107 MESON_PIN(GPIOZ_9),
109 MESON_PIN(GPIOZ_10, 0), 108 MESON_PIN(GPIOZ_10),
110 MESON_PIN(GPIOZ_11, 0), 109 MESON_PIN(GPIOZ_11),
111 MESON_PIN(GPIOZ_12, 0), 110 MESON_PIN(GPIOZ_12),
112 MESON_PIN(GPIOZ_13, 0), 111 MESON_PIN(GPIOZ_13),
113 MESON_PIN(GPIOZ_14, 0), 112 MESON_PIN(GPIOZ_14),
114 MESON_PIN(CARD_0, 0), 113 MESON_PIN(CARD_0),
115 MESON_PIN(CARD_1, 0), 114 MESON_PIN(CARD_1),
116 MESON_PIN(CARD_2, 0), 115 MESON_PIN(CARD_2),
117 MESON_PIN(CARD_3, 0), 116 MESON_PIN(CARD_3),
118 MESON_PIN(CARD_4, 0), 117 MESON_PIN(CARD_4),
119 MESON_PIN(CARD_5, 0), 118 MESON_PIN(CARD_5),
120 MESON_PIN(CARD_6, 0), 119 MESON_PIN(CARD_6),
121 MESON_PIN(BOOT_0, 0), 120 MESON_PIN(BOOT_0),
122 MESON_PIN(BOOT_1, 0), 121 MESON_PIN(BOOT_1),
123 MESON_PIN(BOOT_2, 0), 122 MESON_PIN(BOOT_2),
124 MESON_PIN(BOOT_3, 0), 123 MESON_PIN(BOOT_3),
125 MESON_PIN(BOOT_4, 0), 124 MESON_PIN(BOOT_4),
126 MESON_PIN(BOOT_5, 0), 125 MESON_PIN(BOOT_5),
127 MESON_PIN(BOOT_6, 0), 126 MESON_PIN(BOOT_6),
128 MESON_PIN(BOOT_7, 0), 127 MESON_PIN(BOOT_7),
129 MESON_PIN(BOOT_8, 0), 128 MESON_PIN(BOOT_8),
130 MESON_PIN(BOOT_9, 0), 129 MESON_PIN(BOOT_9),
131 MESON_PIN(BOOT_10, 0), 130 MESON_PIN(BOOT_10),
132 MESON_PIN(BOOT_11, 0), 131 MESON_PIN(BOOT_11),
133 MESON_PIN(BOOT_12, 0), 132 MESON_PIN(BOOT_12),
134 MESON_PIN(BOOT_13, 0), 133 MESON_PIN(BOOT_13),
135 MESON_PIN(BOOT_14, 0), 134 MESON_PIN(BOOT_14),
136 MESON_PIN(BOOT_15, 0), 135 MESON_PIN(BOOT_15),
137 MESON_PIN(BOOT_16, 0), 136 MESON_PIN(BOOT_16),
138 MESON_PIN(BOOT_17, 0), 137 MESON_PIN(BOOT_17),
139 MESON_PIN(BOOT_18, 0), 138 MESON_PIN(BOOT_18),
140}; 139};
141 140
142static const struct pinctrl_pin_desc meson8_aobus_pins[] = { 141static const struct pinctrl_pin_desc meson8_aobus_pins[] = {
143 MESON_PIN(GPIOAO_0, AO_OFF), 142 MESON_PIN(GPIOAO_0),
144 MESON_PIN(GPIOAO_1, AO_OFF), 143 MESON_PIN(GPIOAO_1),
145 MESON_PIN(GPIOAO_2, AO_OFF), 144 MESON_PIN(GPIOAO_2),
146 MESON_PIN(GPIOAO_3, AO_OFF), 145 MESON_PIN(GPIOAO_3),
147 MESON_PIN(GPIOAO_4, AO_OFF), 146 MESON_PIN(GPIOAO_4),
148 MESON_PIN(GPIOAO_5, AO_OFF), 147 MESON_PIN(GPIOAO_5),
149 MESON_PIN(GPIOAO_6, AO_OFF), 148 MESON_PIN(GPIOAO_6),
150 MESON_PIN(GPIOAO_7, AO_OFF), 149 MESON_PIN(GPIOAO_7),
151 MESON_PIN(GPIOAO_8, AO_OFF), 150 MESON_PIN(GPIOAO_8),
152 MESON_PIN(GPIOAO_9, AO_OFF), 151 MESON_PIN(GPIOAO_9),
153 MESON_PIN(GPIOAO_10, AO_OFF), 152 MESON_PIN(GPIOAO_10),
154 MESON_PIN(GPIOAO_11, AO_OFF), 153 MESON_PIN(GPIOAO_11),
155 MESON_PIN(GPIOAO_12, AO_OFF), 154 MESON_PIN(GPIOAO_12),
156 MESON_PIN(GPIOAO_13, AO_OFF), 155 MESON_PIN(GPIOAO_13),
157 MESON_PIN(GPIO_BSD_EN, AO_OFF), 156 MESON_PIN(GPIO_BSD_EN),
158 MESON_PIN(GPIO_TEST_N, AO_OFF), 157 MESON_PIN(GPIO_TEST_N),
159}; 158};
160 159
161/* bank X */ 160/* bank X */
162static const unsigned int sd_d0_a_pins[] = { PIN(GPIOX_0, 0) }; 161static const unsigned int sd_d0_a_pins[] = { GPIOX_0 };
163static const unsigned int sd_d1_a_pins[] = { PIN(GPIOX_1, 0) }; 162static const unsigned int sd_d1_a_pins[] = { GPIOX_1 };
164static const unsigned int sd_d2_a_pins[] = { PIN(GPIOX_2, 0) }; 163static const unsigned int sd_d2_a_pins[] = { GPIOX_2 };
165static const unsigned int sd_d3_a_pins[] = { PIN(GPIOX_3, 0) }; 164static const unsigned int sd_d3_a_pins[] = { GPIOX_3 };
166static const unsigned int sd_clk_a_pins[] = { PIN(GPIOX_8, 0) }; 165static const unsigned int sd_clk_a_pins[] = { GPIOX_8 };
167static const unsigned int sd_cmd_a_pins[] = { PIN(GPIOX_9, 0) }; 166static const unsigned int sd_cmd_a_pins[] = { GPIOX_9 };
168 167
169static const unsigned int sdxc_d0_a_pins[] = { PIN(GPIOX_0, 0) }; 168static const unsigned int sdxc_d0_a_pins[] = { GPIOX_0 };
170static const unsigned int sdxc_d13_a_pins[] = { PIN(GPIOX_1, 0), PIN(GPIOX_2, 0), 169static const unsigned int sdxc_d13_a_pins[] = { GPIOX_1, GPIOX_2, GPIOX_3 };
171 PIN(GPIOX_3, 0) }; 170static const unsigned int sdxc_d47_a_pins[] = { GPIOX_4, GPIOX_5, GPIOX_6,
172static const unsigned int sdxc_d47_a_pins[] = { PIN(GPIOX_4, 0), PIN(GPIOX_5, 0), 171 GPIOX_7 };
173 PIN(GPIOX_6, 0), PIN(GPIOX_7, 0) }; 172static const unsigned int sdxc_clk_a_pins[] = { GPIOX_8 };
174static const unsigned int sdxc_clk_a_pins[] = { PIN(GPIOX_8, 0) }; 173static const unsigned int sdxc_cmd_a_pins[] = { GPIOX_9 };
175static const unsigned int sdxc_cmd_a_pins[] = { PIN(GPIOX_9, 0) }; 174
176 175static const unsigned int pcm_out_a_pins[] = { GPIOX_4 };
177static const unsigned int pcm_out_a_pins[] = { PIN(GPIOX_4, 0) }; 176static const unsigned int pcm_in_a_pins[] = { GPIOX_5 };
178static const unsigned int pcm_in_a_pins[] = { PIN(GPIOX_5, 0) }; 177static const unsigned int pcm_fs_a_pins[] = { GPIOX_6 };
179static const unsigned int pcm_fs_a_pins[] = { PIN(GPIOX_6, 0) }; 178static const unsigned int pcm_clk_a_pins[] = { GPIOX_7 };
180static const unsigned int pcm_clk_a_pins[] = { PIN(GPIOX_7, 0) }; 179
181 180static const unsigned int uart_tx_a0_pins[] = { GPIOX_4 };
182static const unsigned int uart_tx_a0_pins[] = { PIN(GPIOX_4, 0) }; 181static const unsigned int uart_rx_a0_pins[] = { GPIOX_5 };
183static const unsigned int uart_rx_a0_pins[] = { PIN(GPIOX_5, 0) }; 182static const unsigned int uart_cts_a0_pins[] = { GPIOX_6 };
184static const unsigned int uart_cts_a0_pins[] = { PIN(GPIOX_6, 0) }; 183static const unsigned int uart_rts_a0_pins[] = { GPIOX_7 };
185static const unsigned int uart_rts_a0_pins[] = { PIN(GPIOX_7, 0) }; 184
186 185static const unsigned int uart_tx_a1_pins[] = { GPIOX_12 };
187static const unsigned int uart_tx_a1_pins[] = { PIN(GPIOX_12, 0) }; 186static const unsigned int uart_rx_a1_pins[] = { GPIOX_13 };
188static const unsigned int uart_rx_a1_pins[] = { PIN(GPIOX_13, 0) }; 187static const unsigned int uart_cts_a1_pins[] = { GPIOX_14 };
189static const unsigned int uart_cts_a1_pins[] = { PIN(GPIOX_14, 0) }; 188static const unsigned int uart_rts_a1_pins[] = { GPIOX_15 };
190static const unsigned int uart_rts_a1_pins[] = { PIN(GPIOX_15, 0) }; 189
191 190static const unsigned int uart_tx_b0_pins[] = { GPIOX_16 };
192static const unsigned int uart_tx_b0_pins[] = { PIN(GPIOX_16, 0) }; 191static const unsigned int uart_rx_b0_pins[] = { GPIOX_17 };
193static const unsigned int uart_rx_b0_pins[] = { PIN(GPIOX_17, 0) }; 192static const unsigned int uart_cts_b0_pins[] = { GPIOX_18 };
194static const unsigned int uart_cts_b0_pins[] = { PIN(GPIOX_18, 0) }; 193static const unsigned int uart_rts_b0_pins[] = { GPIOX_19 };
195static const unsigned int uart_rts_b0_pins[] = { PIN(GPIOX_19, 0) }; 194
196 195static const unsigned int iso7816_det_pins[] = { GPIOX_16 };
197static const unsigned int iso7816_det_pins[] = { PIN(GPIOX_16, 0) }; 196static const unsigned int iso7816_reset_pins[] = { GPIOX_17 };
198static const unsigned int iso7816_reset_pins[] = { PIN(GPIOX_17, 0) }; 197static const unsigned int iso7816_clk_pins[] = { GPIOX_18 };
199static const unsigned int iso7816_clk_pins[] = { PIN(GPIOX_18, 0) }; 198static const unsigned int iso7816_data_pins[] = { GPIOX_19 };
200static const unsigned int iso7816_data_pins[] = { PIN(GPIOX_19, 0) }; 199
201 200static const unsigned int i2c_sda_d0_pins[] = { GPIOX_16 };
202static const unsigned int i2c_sda_d0_pins[] = { PIN(GPIOX_16, 0) }; 201static const unsigned int i2c_sck_d0_pins[] = { GPIOX_17 };
203static const unsigned int i2c_sck_d0_pins[] = { PIN(GPIOX_17, 0) }; 202
204 203static const unsigned int xtal_32k_out_pins[] = { GPIOX_10 };
205static const unsigned int xtal_32k_out_pins[] = { PIN(GPIOX_10, 0) }; 204static const unsigned int xtal_24m_out_pins[] = { GPIOX_11 };
206static const unsigned int xtal_24m_out_pins[] = { PIN(GPIOX_11, 0) }; 205
207 206static const unsigned int pwm_e_pins[] = { GPIOX_10 };
208static const unsigned int pwm_e_pins[] = { PIN(GPIOX_10, 0) }; 207static const unsigned int pwm_b_x_pins[] = { GPIOX_11 };
209static const unsigned int pwm_b_x_pins[] = { PIN(GPIOX_11, 0) };
210 208
211/* bank Y */ 209/* bank Y */
212static const unsigned int uart_tx_c_pins[] = { PIN(GPIOY_0, 0) }; 210static const unsigned int uart_tx_c_pins[] = { GPIOY_0 };
213static const unsigned int uart_rx_c_pins[] = { PIN(GPIOY_1, 0) }; 211static const unsigned int uart_rx_c_pins[] = { GPIOY_1 };
214static const unsigned int uart_cts_c_pins[] = { PIN(GPIOY_2, 0) }; 212static const unsigned int uart_cts_c_pins[] = { GPIOY_2 };
215static const unsigned int uart_rts_c_pins[] = { PIN(GPIOY_3, 0) }; 213static const unsigned int uart_rts_c_pins[] = { GPIOY_3 };
216 214
217static const unsigned int pcm_out_b_pins[] = { PIN(GPIOY_4, 0) }; 215static const unsigned int pcm_out_b_pins[] = { GPIOY_4 };
218static const unsigned int pcm_in_b_pins[] = { PIN(GPIOY_5, 0) }; 216static const unsigned int pcm_in_b_pins[] = { GPIOY_5 };
219static const unsigned int pcm_fs_b_pins[] = { PIN(GPIOY_6, 0) }; 217static const unsigned int pcm_fs_b_pins[] = { GPIOY_6 };
220static const unsigned int pcm_clk_b_pins[] = { PIN(GPIOY_7, 0) }; 218static const unsigned int pcm_clk_b_pins[] = { GPIOY_7 };
221 219
222static const unsigned int i2c_sda_c0_pins[] = { PIN(GPIOY_0, 0) }; 220static const unsigned int i2c_sda_c0_pins[] = { GPIOY_0 };
223static const unsigned int i2c_sck_c0_pins[] = { PIN(GPIOY_1, 0) }; 221static const unsigned int i2c_sck_c0_pins[] = { GPIOY_1 };
224 222
225static const unsigned int pwm_a_y_pins[] = { PIN(GPIOY_16, 0) }; 223static const unsigned int pwm_a_y_pins[] = { GPIOY_16 };
226 224
227static const unsigned int i2s_out_ch45_pins[] = { PIN(GPIOY_0, 0) }; 225static const unsigned int i2s_out_ch45_pins[] = { GPIOY_0 };
228static const unsigned int i2s_out_ch23_pins[] = { PIN(GPIOY_1, 0) }; 226static const unsigned int i2s_out_ch23_pins[] = { GPIOY_1 };
229static const unsigned int i2s_out_ch01_pins[] = { PIN(GPIOY_4, 0) }; 227static const unsigned int i2s_out_ch01_pins[] = { GPIOY_4 };
230static const unsigned int i2s_in_ch01_pins[] = { PIN(GPIOY_5, 0) }; 228static const unsigned int i2s_in_ch01_pins[] = { GPIOY_5 };
231static const unsigned int i2s_lr_clk_in_pins[] = { PIN(GPIOY_6, 0) }; 229static const unsigned int i2s_lr_clk_in_pins[] = { GPIOY_6 };
232static const unsigned int i2s_ao_clk_in_pins[] = { PIN(GPIOY_7, 0) }; 230static const unsigned int i2s_ao_clk_in_pins[] = { GPIOY_7 };
233static const unsigned int i2s_am_clk_pins[] = { PIN(GPIOY_8, 0) }; 231static const unsigned int i2s_am_clk_pins[] = { GPIOY_8 };
234static const unsigned int i2s_out_ch78_pins[] = { PIN(GPIOY_9, 0) }; 232static const unsigned int i2s_out_ch78_pins[] = { GPIOY_9 };
235 233
236static const unsigned int spdif_in_pins[] = { PIN(GPIOY_2, 0) }; 234static const unsigned int spdif_in_pins[] = { GPIOY_2 };
237static const unsigned int spdif_out_pins[] = { PIN(GPIOY_3, 0) }; 235static const unsigned int spdif_out_pins[] = { GPIOY_3 };
238 236
239/* bank DV */ 237/* bank DV */
240static const unsigned int dvin_rgb_pins[] = { PIN(GPIODV_0, 0), PIN(GPIODV_1, 0), 238static const unsigned int dvin_rgb_pins[] = {
241 PIN(GPIODV_2, 0), PIN(GPIODV_3, 0), 239 GPIODV_0, GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5,
242 PIN(GPIODV_4, 0), PIN(GPIODV_5, 0), 240 GPIODV_6, GPIODV_7, GPIODV_8, GPIODV_9, GPIODV_10, GPIODV_11,
243 PIN(GPIODV_6, 0), PIN(GPIODV_7, 0), 241 GPIODV_12, GPIODV_13, GPIODV_14, GPIODV_15, GPIODV_16, GPIODV_17,
244 PIN(GPIODV_8, 0), PIN(GPIODV_9, 0), 242 GPIODV_18, GPIODV_19, GPIODV_20, GPIODV_21, GPIODV_22, GPIODV_23
245 PIN(GPIODV_10, 0), PIN(GPIODV_11, 0), 243};
246 PIN(GPIODV_12, 0), PIN(GPIODV_13, 0), 244static const unsigned int dvin_vs_pins[] = { GPIODV_24 };
247 PIN(GPIODV_14, 0), PIN(GPIODV_15, 0), 245static const unsigned int dvin_hs_pins[] = { GPIODV_25 };
248 PIN(GPIODV_16, 0), PIN(GPIODV_17, 0), 246static const unsigned int dvin_clk_pins[] = { GPIODV_26 };
249 PIN(GPIODV_18, 0), PIN(GPIODV_19, 0), 247static const unsigned int dvin_de_pins[] = { GPIODV_27 };
250 PIN(GPIODV_20, 0), PIN(GPIODV_21, 0), 248
251 PIN(GPIODV_22, 0), PIN(GPIODV_23, 0) }; 249static const unsigned int enc_0_pins[] = { GPIODV_0 };
252static const unsigned int dvin_vs_pins[] = { PIN(GPIODV_24, 0) }; 250static const unsigned int enc_1_pins[] = { GPIODV_1 };
253static const unsigned int dvin_hs_pins[] = { PIN(GPIODV_25, 0) }; 251static const unsigned int enc_2_pins[] = { GPIODV_2 };
254static const unsigned int dvin_clk_pins[] = { PIN(GPIODV_26, 0) }; 252static const unsigned int enc_3_pins[] = { GPIODV_3 };
255static const unsigned int dvin_de_pins[] = { PIN(GPIODV_27, 0) }; 253static const unsigned int enc_4_pins[] = { GPIODV_4 };
256 254static const unsigned int enc_5_pins[] = { GPIODV_5 };
257static const unsigned int enc_0_pins[] = { PIN(GPIODV_0, 0) }; 255static const unsigned int enc_6_pins[] = { GPIODV_6 };
258static const unsigned int enc_1_pins[] = { PIN(GPIODV_1, 0) }; 256static const unsigned int enc_7_pins[] = { GPIODV_7 };
259static const unsigned int enc_2_pins[] = { PIN(GPIODV_2, 0) }; 257static const unsigned int enc_8_pins[] = { GPIODV_8 };
260static const unsigned int enc_3_pins[] = { PIN(GPIODV_3, 0) }; 258static const unsigned int enc_9_pins[] = { GPIODV_9 };
261static const unsigned int enc_4_pins[] = { PIN(GPIODV_4, 0) }; 259static const unsigned int enc_10_pins[] = { GPIODV_10 };
262static const unsigned int enc_5_pins[] = { PIN(GPIODV_5, 0) }; 260static const unsigned int enc_11_pins[] = { GPIODV_11 };
263static const unsigned int enc_6_pins[] = { PIN(GPIODV_6, 0) }; 261static const unsigned int enc_12_pins[] = { GPIODV_12 };
264static const unsigned int enc_7_pins[] = { PIN(GPIODV_7, 0) }; 262static const unsigned int enc_13_pins[] = { GPIODV_13 };
265static const unsigned int enc_8_pins[] = { PIN(GPIODV_8, 0) }; 263static const unsigned int enc_14_pins[] = { GPIODV_14 };
266static const unsigned int enc_9_pins[] = { PIN(GPIODV_9, 0) }; 264static const unsigned int enc_15_pins[] = { GPIODV_15 };
267static const unsigned int enc_10_pins[] = { PIN(GPIODV_10, 0) }; 265static const unsigned int enc_16_pins[] = { GPIODV_16 };
268static const unsigned int enc_11_pins[] = { PIN(GPIODV_11, 0) }; 266static const unsigned int enc_17_pins[] = { GPIODV_17 };
269static const unsigned int enc_12_pins[] = { PIN(GPIODV_12, 0) }; 267
270static const unsigned int enc_13_pins[] = { PIN(GPIODV_13, 0) }; 268static const unsigned int uart_tx_b1_pins[] = { GPIODV_24 };
271static const unsigned int enc_14_pins[] = { PIN(GPIODV_14, 0) }; 269static const unsigned int uart_rx_b1_pins[] = { GPIODV_25 };
272static const unsigned int enc_15_pins[] = { PIN(GPIODV_15, 0) }; 270static const unsigned int uart_cts_b1_pins[] = { GPIODV_26 };
273static const unsigned int enc_16_pins[] = { PIN(GPIODV_16, 0) }; 271static const unsigned int uart_rts_b1_pins[] = { GPIODV_27 };
274static const unsigned int enc_17_pins[] = { PIN(GPIODV_17, 0) }; 272
275 273static const unsigned int vga_vs_pins[] = { GPIODV_24 };
276static const unsigned int uart_tx_b1_pins[] = { PIN(GPIODV_24, 0) }; 274static const unsigned int vga_hs_pins[] = { GPIODV_25 };
277static const unsigned int uart_rx_b1_pins[] = { PIN(GPIODV_25, 0) }; 275
278static const unsigned int uart_cts_b1_pins[] = { PIN(GPIODV_26, 0) }; 276static const unsigned int pwm_c_dv9_pins[] = { GPIODV_9 };
279static const unsigned int uart_rts_b1_pins[] = { PIN(GPIODV_27, 0) }; 277static const unsigned int pwm_c_dv29_pins[] = { GPIODV_29 };
280 278static const unsigned int pwm_d_pins[] = { GPIODV_28 };
281static const unsigned int vga_vs_pins[] = { PIN(GPIODV_24, 0) };
282static const unsigned int vga_hs_pins[] = { PIN(GPIODV_25, 0) };
283
284static const unsigned int pwm_c_dv9_pins[] = { PIN(GPIODV_9, 0) };
285static const unsigned int pwm_c_dv29_pins[] = { PIN(GPIODV_29, 0) };
286static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, 0) };
287 279
288/* bank H */ 280/* bank H */
289static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, 0) }; 281static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 };
290static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, 0) }; 282static const unsigned int hdmi_sda_pins[] = { GPIOH_1 };
291static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, 0) }; 283static const unsigned int hdmi_scl_pins[] = { GPIOH_2 };
292static const unsigned int hdmi_cec_pins[] = { PIN(GPIOH_3, 0) }; 284static const unsigned int hdmi_cec_pins[] = { GPIOH_3 };
293 285
294static const unsigned int spi_ss0_0_pins[] = { PIN(GPIOH_3, 0) }; 286static const unsigned int spi_ss0_0_pins[] = { GPIOH_3 };
295static const unsigned int spi_miso_0_pins[] = { PIN(GPIOH_4, 0) }; 287static const unsigned int spi_miso_0_pins[] = { GPIOH_4 };
296static const unsigned int spi_mosi_0_pins[] = { PIN(GPIOH_5, 0) }; 288static const unsigned int spi_mosi_0_pins[] = { GPIOH_5 };
297static const unsigned int spi_sclk_0_pins[] = { PIN(GPIOH_6, 0) }; 289static const unsigned int spi_sclk_0_pins[] = { GPIOH_6 };
298 290
299static const unsigned int i2c_sda_d1_pins[] = { PIN(GPIOH_7, 0) }; 291static const unsigned int i2c_sda_d1_pins[] = { GPIOH_7 };
300static const unsigned int i2c_sck_d1_pins[] = { PIN(GPIOH_8, 0) }; 292static const unsigned int i2c_sck_d1_pins[] = { GPIOH_8 };
301 293
302/* bank Z */ 294/* bank Z */
303static const unsigned int spi_ss0_1_pins[] = { PIN(GPIOZ_9, 0) }; 295static const unsigned int spi_ss0_1_pins[] = { GPIOZ_9 };
304static const unsigned int spi_ss1_1_pins[] = { PIN(GPIOZ_10, 0) }; 296static const unsigned int spi_ss1_1_pins[] = { GPIOZ_10 };
305static const unsigned int spi_sclk_1_pins[] = { PIN(GPIOZ_11, 0) }; 297static const unsigned int spi_sclk_1_pins[] = { GPIOZ_11 };
306static const unsigned int spi_mosi_1_pins[] = { PIN(GPIOZ_12, 0) }; 298static const unsigned int spi_mosi_1_pins[] = { GPIOZ_12 };
307static const unsigned int spi_miso_1_pins[] = { PIN(GPIOZ_13, 0) }; 299static const unsigned int spi_miso_1_pins[] = { GPIOZ_13 };
308static const unsigned int spi_ss2_1_pins[] = { PIN(GPIOZ_14, 0) }; 300static const unsigned int spi_ss2_1_pins[] = { GPIOZ_14 };
309 301
310static const unsigned int eth_tx_clk_50m_pins[] = { PIN(GPIOZ_4, 0) }; 302static const unsigned int eth_tx_clk_50m_pins[] = { GPIOZ_4 };
311static const unsigned int eth_tx_en_pins[] = { PIN(GPIOZ_5, 0) }; 303static const unsigned int eth_tx_en_pins[] = { GPIOZ_5 };
312static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_6, 0) }; 304static const unsigned int eth_txd1_pins[] = { GPIOZ_6 };
313static const unsigned int eth_txd0_pins[] = { PIN(GPIOZ_7, 0) }; 305static const unsigned int eth_txd0_pins[] = { GPIOZ_7 };
314static const unsigned int eth_rx_clk_in_pins[] = { PIN(GPIOZ_8, 0) }; 306static const unsigned int eth_rx_clk_in_pins[] = { GPIOZ_8 };
315static const unsigned int eth_rx_dv_pins[] = { PIN(GPIOZ_9, 0) }; 307static const unsigned int eth_rx_dv_pins[] = { GPIOZ_9 };
316static const unsigned int eth_rxd1_pins[] = { PIN(GPIOZ_10, 0) }; 308static const unsigned int eth_rxd1_pins[] = { GPIOZ_10 };
317static const unsigned int eth_rxd0_pins[] = { PIN(GPIOZ_11, 0) }; 309static const unsigned int eth_rxd0_pins[] = { GPIOZ_11 };
318static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_12, 0) }; 310static const unsigned int eth_mdio_pins[] = { GPIOZ_12 };
319static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_13, 0) }; 311static const unsigned int eth_mdc_pins[] = { GPIOZ_13 };
320 312
321static const unsigned int i2c_sda_a0_pins[] = { PIN(GPIOZ_0, 0) }; 313static const unsigned int i2c_sda_a0_pins[] = { GPIOZ_0 };
322static const unsigned int i2c_sck_a0_pins[] = { PIN(GPIOZ_1, 0) }; 314static const unsigned int i2c_sck_a0_pins[] = { GPIOZ_1 };
323 315
324static const unsigned int i2c_sda_b_pins[] = { PIN(GPIOZ_2, 0) }; 316static const unsigned int i2c_sda_b_pins[] = { GPIOZ_2 };
325static const unsigned int i2c_sck_b_pins[] = { PIN(GPIOZ_3, 0) }; 317static const unsigned int i2c_sck_b_pins[] = { GPIOZ_3 };
326 318
327static const unsigned int i2c_sda_c1_pins[] = { PIN(GPIOZ_4, 0) }; 319static const unsigned int i2c_sda_c1_pins[] = { GPIOZ_4 };
328static const unsigned int i2c_sck_c1_pins[] = { PIN(GPIOZ_5, 0) }; 320static const unsigned int i2c_sck_c1_pins[] = { GPIOZ_5 };
329 321
330static const unsigned int i2c_sda_a1_pins[] = { PIN(GPIOZ_0, 0) }; 322static const unsigned int i2c_sda_a1_pins[] = { GPIOZ_0 };
331static const unsigned int i2c_sck_a1_pins[] = { PIN(GPIOZ_1, 0) }; 323static const unsigned int i2c_sck_a1_pins[] = { GPIOZ_1 };
332 324
333static const unsigned int i2c_sda_a2_pins[] = { PIN(GPIOZ_0, 0) }; 325static const unsigned int i2c_sda_a2_pins[] = { GPIOZ_0 };
334static const unsigned int i2c_sck_a2_pins[] = { PIN(GPIOZ_1, 0) }; 326static const unsigned int i2c_sck_a2_pins[] = { GPIOZ_1 };
335 327
336static const unsigned int pwm_a_z0_pins[] = { PIN(GPIOZ_0, 0) }; 328static const unsigned int pwm_a_z0_pins[] = { GPIOZ_0 };
337static const unsigned int pwm_a_z7_pins[] = { PIN(GPIOZ_7, 0) }; 329static const unsigned int pwm_a_z7_pins[] = { GPIOZ_7 };
338static const unsigned int pwm_b_z_pins[] = { PIN(GPIOZ_1, 0) }; 330static const unsigned int pwm_b_z_pins[] = { GPIOZ_1 };
339static const unsigned int pwm_c_z_pins[] = { PIN(GPIOZ_8, 0) }; 331static const unsigned int pwm_c_z_pins[] = { GPIOZ_8 };
340 332
341/* bank BOOT */ 333/* bank BOOT */
342static const unsigned int sd_d0_c_pins[] = { PIN(BOOT_0, 0) }; 334static const unsigned int sd_d0_c_pins[] = { BOOT_0 };
343static const unsigned int sd_d1_c_pins[] = { PIN(BOOT_1, 0) }; 335static const unsigned int sd_d1_c_pins[] = { BOOT_1 };
344static const unsigned int sd_d2_c_pins[] = { PIN(BOOT_2, 0) }; 336static const unsigned int sd_d2_c_pins[] = { BOOT_2 };
345static const unsigned int sd_d3_c_pins[] = { PIN(BOOT_3, 0) }; 337static const unsigned int sd_d3_c_pins[] = { BOOT_3 };
346static const unsigned int sd_cmd_c_pins[] = { PIN(BOOT_16, 0) }; 338static const unsigned int sd_cmd_c_pins[] = { BOOT_16 };
347static const unsigned int sd_clk_c_pins[] = { PIN(BOOT_17, 0) }; 339static const unsigned int sd_clk_c_pins[] = { BOOT_17 };
348 340
349static const unsigned int sdxc_d0_c_pins[] = { PIN(BOOT_0, 0)}; 341static const unsigned int sdxc_d0_c_pins[] = { BOOT_0};
350static const unsigned int sdxc_d13_c_pins[] = { PIN(BOOT_1, 0), PIN(BOOT_2, 0), 342static const unsigned int sdxc_d13_c_pins[] = { BOOT_1, BOOT_2, BOOT_3 };
351 PIN(BOOT_3, 0) }; 343static const unsigned int sdxc_d47_c_pins[] = { BOOT_4, BOOT_5, BOOT_6,
352static const unsigned int sdxc_d47_c_pins[] = { PIN(BOOT_4, 0), PIN(BOOT_5, 0), 344 BOOT_7 };
353 PIN(BOOT_6, 0), PIN(BOOT_7, 0) }; 345static const unsigned int sdxc_cmd_c_pins[] = { BOOT_16 };
354static const unsigned int sdxc_cmd_c_pins[] = { PIN(BOOT_16, 0) }; 346static const unsigned int sdxc_clk_c_pins[] = { BOOT_17 };
355static const unsigned int sdxc_clk_c_pins[] = { PIN(BOOT_17, 0) }; 347
356 348static const unsigned int nand_io_pins[] = {
357static const unsigned int nand_io_pins[] = { PIN(BOOT_0, 0), PIN(BOOT_1, 0), 349 BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7
358 PIN(BOOT_2, 0), PIN(BOOT_3, 0), 350};
359 PIN(BOOT_4, 0), PIN(BOOT_5, 0), 351static const unsigned int nand_io_ce0_pins[] = { BOOT_8 };
360 PIN(BOOT_6, 0), PIN(BOOT_7, 0) }; 352static const unsigned int nand_io_ce1_pins[] = { BOOT_9 };
361static const unsigned int nand_io_ce0_pins[] = { PIN(BOOT_8, 0) }; 353static const unsigned int nand_io_rb0_pins[] = { BOOT_10 };
362static const unsigned int nand_io_ce1_pins[] = { PIN(BOOT_9, 0) }; 354static const unsigned int nand_ale_pins[] = { BOOT_11 };
363static const unsigned int nand_io_rb0_pins[] = { PIN(BOOT_10, 0) }; 355static const unsigned int nand_cle_pins[] = { BOOT_12 };
364static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, 0) }; 356static const unsigned int nand_wen_clk_pins[] = { BOOT_13 };
365static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, 0) }; 357static const unsigned int nand_ren_clk_pins[] = { BOOT_14 };
366static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, 0) }; 358static const unsigned int nand_dqs_pins[] = { BOOT_15 };
367static const unsigned int nand_ren_clk_pins[] = { PIN(BOOT_14, 0) }; 359static const unsigned int nand_ce2_pins[] = { BOOT_16 };
368static const unsigned int nand_dqs_pins[] = { PIN(BOOT_15, 0) }; 360static const unsigned int nand_ce3_pins[] = { BOOT_17 };
369static const unsigned int nand_ce2_pins[] = { PIN(BOOT_16, 0) }; 361
370static const unsigned int nand_ce3_pins[] = { PIN(BOOT_17, 0) }; 362static const unsigned int nor_d_pins[] = { BOOT_11 };
371 363static const unsigned int nor_q_pins[] = { BOOT_12 };
372static const unsigned int nor_d_pins[] = { PIN(BOOT_11, 0) }; 364static const unsigned int nor_c_pins[] = { BOOT_13 };
373static const unsigned int nor_q_pins[] = { PIN(BOOT_12, 0) }; 365static const unsigned int nor_cs_pins[] = { BOOT_18 };
374static const unsigned int nor_c_pins[] = { PIN(BOOT_13, 0) };
375static const unsigned int nor_cs_pins[] = { PIN(BOOT_18, 0) };
376 366
377/* bank CARD */ 367/* bank CARD */
378static const unsigned int sd_d1_b_pins[] = { PIN(CARD_0, 0) }; 368static const unsigned int sd_d1_b_pins[] = { CARD_0 };
379static const unsigned int sd_d0_b_pins[] = { PIN(CARD_1, 0) }; 369static const unsigned int sd_d0_b_pins[] = { CARD_1 };
380static const unsigned int sd_clk_b_pins[] = { PIN(CARD_2, 0) }; 370static const unsigned int sd_clk_b_pins[] = { CARD_2 };
381static const unsigned int sd_cmd_b_pins[] = { PIN(CARD_3, 0) }; 371static const unsigned int sd_cmd_b_pins[] = { CARD_3 };
382static const unsigned int sd_d3_b_pins[] = { PIN(CARD_4, 0) }; 372static const unsigned int sd_d3_b_pins[] = { CARD_4 };
383static const unsigned int sd_d2_b_pins[] = { PIN(CARD_5, 0) }; 373static const unsigned int sd_d2_b_pins[] = { CARD_5 };
384 374
385static const unsigned int sdxc_d13_b_pins[] = { PIN(CARD_0, 0), PIN(CARD_4, 0), 375static const unsigned int sdxc_d13_b_pins[] = { CARD_0, CARD_4, CARD_5 };
386 PIN(CARD_5, 0) }; 376static const unsigned int sdxc_d0_b_pins[] = { CARD_1 };
387static const unsigned int sdxc_d0_b_pins[] = { PIN(CARD_1, 0) }; 377static const unsigned int sdxc_clk_b_pins[] = { CARD_2 };
388static const unsigned int sdxc_clk_b_pins[] = { PIN(CARD_2, 0) }; 378static const unsigned int sdxc_cmd_b_pins[] = { CARD_3 };
389static const unsigned int sdxc_cmd_b_pins[] = { PIN(CARD_3, 0) };
390 379
391/* bank AO */ 380/* bank AO */
392static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, AO_OFF) }; 381static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 };
393static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, AO_OFF) }; 382static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 };
394static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, AO_OFF) }; 383static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 };
395static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, AO_OFF) }; 384static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 };
396 385
397static const unsigned int remote_input_pins[] = { PIN(GPIOAO_7, AO_OFF) }; 386static const unsigned int remote_input_pins[] = { GPIOAO_7 };
398static const unsigned int remote_output_ao_pins[] = { PIN(GPIOAO_13, AO_OFF) }; 387static const unsigned int remote_output_ao_pins[] = { GPIOAO_13 };
399 388
400static const unsigned int i2c_slave_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) }; 389static const unsigned int i2c_slave_sck_ao_pins[] = { GPIOAO_4 };
401static const unsigned int i2c_slave_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; 390static const unsigned int i2c_slave_sda_ao_pins[] = { GPIOAO_5 };
402 391
403static const unsigned int uart_tx_ao_b0_pins[] = { PIN(GPIOAO_0, AO_OFF) }; 392static const unsigned int uart_tx_ao_b0_pins[] = { GPIOAO_0 };
404static const unsigned int uart_rx_ao_b0_pins[] = { PIN(GPIOAO_1, AO_OFF) }; 393static const unsigned int uart_rx_ao_b0_pins[] = { GPIOAO_1 };
405 394
406static const unsigned int uart_tx_ao_b1_pins[] = { PIN(GPIOAO_4, AO_OFF) }; 395static const unsigned int uart_tx_ao_b1_pins[] = { GPIOAO_4 };
407static const unsigned int uart_rx_ao_b1_pins[] = { PIN(GPIOAO_5, AO_OFF) }; 396static const unsigned int uart_rx_ao_b1_pins[] = { GPIOAO_5 };
408 397
409static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) }; 398static const unsigned int i2c_mst_sck_ao_pins[] = { GPIOAO_4 };
410static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; 399static const unsigned int i2c_mst_sda_ao_pins[] = { GPIOAO_5 };
411 400
412static const unsigned int pwm_f_ao_pins[] = { PIN(GPIO_TEST_N, AO_OFF) }; 401static const unsigned int pwm_f_ao_pins[] = { GPIO_TEST_N };
413 402
414static const unsigned int i2s_am_clk_out_ao_pins[] = { PIN(GPIOAO_8, AO_OFF) }; 403static const unsigned int i2s_am_clk_out_ao_pins[] = { GPIOAO_8 };
415static const unsigned int i2s_ao_clk_out_ao_pins[] = { PIN(GPIOAO_9, AO_OFF) }; 404static const unsigned int i2s_ao_clk_out_ao_pins[] = { GPIOAO_9 };
416static const unsigned int i2s_lr_clk_out_ao_pins[] = { PIN(GPIOAO_10, AO_OFF) }; 405static const unsigned int i2s_lr_clk_out_ao_pins[] = { GPIOAO_10 };
417static const unsigned int i2s_out_ch01_ao_pins[] = { PIN(GPIOAO_11, AO_OFF) }; 406static const unsigned int i2s_out_ch01_ao_pins[] = { GPIOAO_11 };
418 407
419static const unsigned int hdmi_cec_ao_pins[] = { PIN(GPIOAO_12, AO_OFF) }; 408static const unsigned int hdmi_cec_ao_pins[] = { GPIOAO_12 };
420 409
421static struct meson_pmx_group meson8_cbus_groups[] = { 410static struct meson_pmx_group meson8_cbus_groups[] = {
422 GPIO_GROUP(GPIOX_0, 0), 411 GPIO_GROUP(GPIOX_0),
423 GPIO_GROUP(GPIOX_1, 0), 412 GPIO_GROUP(GPIOX_1),
424 GPIO_GROUP(GPIOX_2, 0), 413 GPIO_GROUP(GPIOX_2),
425 GPIO_GROUP(GPIOX_3, 0), 414 GPIO_GROUP(GPIOX_3),
426 GPIO_GROUP(GPIOX_4, 0), 415 GPIO_GROUP(GPIOX_4),
427 GPIO_GROUP(GPIOX_5, 0), 416 GPIO_GROUP(GPIOX_5),
428 GPIO_GROUP(GPIOX_6, 0), 417 GPIO_GROUP(GPIOX_6),
429 GPIO_GROUP(GPIOX_7, 0), 418 GPIO_GROUP(GPIOX_7),
430 GPIO_GROUP(GPIOX_8, 0), 419 GPIO_GROUP(GPIOX_8),
431 GPIO_GROUP(GPIOX_9, 0), 420 GPIO_GROUP(GPIOX_9),
432 GPIO_GROUP(GPIOX_10, 0), 421 GPIO_GROUP(GPIOX_10),
433 GPIO_GROUP(GPIOX_11, 0), 422 GPIO_GROUP(GPIOX_11),
434 GPIO_GROUP(GPIOX_12, 0), 423 GPIO_GROUP(GPIOX_12),
435 GPIO_GROUP(GPIOX_13, 0), 424 GPIO_GROUP(GPIOX_13),
436 GPIO_GROUP(GPIOX_14, 0), 425 GPIO_GROUP(GPIOX_14),
437 GPIO_GROUP(GPIOX_15, 0), 426 GPIO_GROUP(GPIOX_15),
438 GPIO_GROUP(GPIOX_16, 0), 427 GPIO_GROUP(GPIOX_16),
439 GPIO_GROUP(GPIOX_17, 0), 428 GPIO_GROUP(GPIOX_17),
440 GPIO_GROUP(GPIOX_18, 0), 429 GPIO_GROUP(GPIOX_18),
441 GPIO_GROUP(GPIOX_19, 0), 430 GPIO_GROUP(GPIOX_19),
442 GPIO_GROUP(GPIOX_20, 0), 431 GPIO_GROUP(GPIOX_20),
443 GPIO_GROUP(GPIOX_21, 0), 432 GPIO_GROUP(GPIOX_21),
444 GPIO_GROUP(GPIOY_0, 0), 433 GPIO_GROUP(GPIOY_0),
445 GPIO_GROUP(GPIOY_1, 0), 434 GPIO_GROUP(GPIOY_1),
446 GPIO_GROUP(GPIOY_2, 0), 435 GPIO_GROUP(GPIOY_2),
447 GPIO_GROUP(GPIOY_3, 0), 436 GPIO_GROUP(GPIOY_3),
448 GPIO_GROUP(GPIOY_4, 0), 437 GPIO_GROUP(GPIOY_4),
449 GPIO_GROUP(GPIOY_5, 0), 438 GPIO_GROUP(GPIOY_5),
450 GPIO_GROUP(GPIOY_6, 0), 439 GPIO_GROUP(GPIOY_6),
451 GPIO_GROUP(GPIOY_7, 0), 440 GPIO_GROUP(GPIOY_7),
452 GPIO_GROUP(GPIOY_8, 0), 441 GPIO_GROUP(GPIOY_8),
453 GPIO_GROUP(GPIOY_9, 0), 442 GPIO_GROUP(GPIOY_9),
454 GPIO_GROUP(GPIOY_10, 0), 443 GPIO_GROUP(GPIOY_10),
455 GPIO_GROUP(GPIOY_11, 0), 444 GPIO_GROUP(GPIOY_11),
456 GPIO_GROUP(GPIOY_12, 0), 445 GPIO_GROUP(GPIOY_12),
457 GPIO_GROUP(GPIOY_13, 0), 446 GPIO_GROUP(GPIOY_13),
458 GPIO_GROUP(GPIOY_14, 0), 447 GPIO_GROUP(GPIOY_14),
459 GPIO_GROUP(GPIOY_15, 0), 448 GPIO_GROUP(GPIOY_15),
460 GPIO_GROUP(GPIOY_16, 0), 449 GPIO_GROUP(GPIOY_16),
461 GPIO_GROUP(GPIODV_0, 0), 450 GPIO_GROUP(GPIODV_0),
462 GPIO_GROUP(GPIODV_1, 0), 451 GPIO_GROUP(GPIODV_1),
463 GPIO_GROUP(GPIODV_2, 0), 452 GPIO_GROUP(GPIODV_2),
464 GPIO_GROUP(GPIODV_3, 0), 453 GPIO_GROUP(GPIODV_3),
465 GPIO_GROUP(GPIODV_4, 0), 454 GPIO_GROUP(GPIODV_4),
466 GPIO_GROUP(GPIODV_5, 0), 455 GPIO_GROUP(GPIODV_5),
467 GPIO_GROUP(GPIODV_6, 0), 456 GPIO_GROUP(GPIODV_6),
468 GPIO_GROUP(GPIODV_7, 0), 457 GPIO_GROUP(GPIODV_7),
469 GPIO_GROUP(GPIODV_8, 0), 458 GPIO_GROUP(GPIODV_8),
470 GPIO_GROUP(GPIODV_9, 0), 459 GPIO_GROUP(GPIODV_9),
471 GPIO_GROUP(GPIODV_10, 0), 460 GPIO_GROUP(GPIODV_10),
472 GPIO_GROUP(GPIODV_11, 0), 461 GPIO_GROUP(GPIODV_11),
473 GPIO_GROUP(GPIODV_12, 0), 462 GPIO_GROUP(GPIODV_12),
474 GPIO_GROUP(GPIODV_13, 0), 463 GPIO_GROUP(GPIODV_13),
475 GPIO_GROUP(GPIODV_14, 0), 464 GPIO_GROUP(GPIODV_14),
476 GPIO_GROUP(GPIODV_15, 0), 465 GPIO_GROUP(GPIODV_15),
477 GPIO_GROUP(GPIODV_16, 0), 466 GPIO_GROUP(GPIODV_16),
478 GPIO_GROUP(GPIODV_17, 0), 467 GPIO_GROUP(GPIODV_17),
479 GPIO_GROUP(GPIODV_18, 0), 468 GPIO_GROUP(GPIODV_18),
480 GPIO_GROUP(GPIODV_19, 0), 469 GPIO_GROUP(GPIODV_19),
481 GPIO_GROUP(GPIODV_20, 0), 470 GPIO_GROUP(GPIODV_20),
482 GPIO_GROUP(GPIODV_21, 0), 471 GPIO_GROUP(GPIODV_21),
483 GPIO_GROUP(GPIODV_22, 0), 472 GPIO_GROUP(GPIODV_22),
484 GPIO_GROUP(GPIODV_23, 0), 473 GPIO_GROUP(GPIODV_23),
485 GPIO_GROUP(GPIODV_24, 0), 474 GPIO_GROUP(GPIODV_24),
486 GPIO_GROUP(GPIODV_25, 0), 475 GPIO_GROUP(GPIODV_25),
487 GPIO_GROUP(GPIODV_26, 0), 476 GPIO_GROUP(GPIODV_26),
488 GPIO_GROUP(GPIODV_27, 0), 477 GPIO_GROUP(GPIODV_27),
489 GPIO_GROUP(GPIODV_28, 0), 478 GPIO_GROUP(GPIODV_28),
490 GPIO_GROUP(GPIODV_29, 0), 479 GPIO_GROUP(GPIODV_29),
491 GPIO_GROUP(GPIOH_0, 0), 480 GPIO_GROUP(GPIOH_0),
492 GPIO_GROUP(GPIOH_1, 0), 481 GPIO_GROUP(GPIOH_1),
493 GPIO_GROUP(GPIOH_2, 0), 482 GPIO_GROUP(GPIOH_2),
494 GPIO_GROUP(GPIOH_3, 0), 483 GPIO_GROUP(GPIOH_3),
495 GPIO_GROUP(GPIOH_4, 0), 484 GPIO_GROUP(GPIOH_4),
496 GPIO_GROUP(GPIOH_5, 0), 485 GPIO_GROUP(GPIOH_5),
497 GPIO_GROUP(GPIOH_6, 0), 486 GPIO_GROUP(GPIOH_6),
498 GPIO_GROUP(GPIOH_7, 0), 487 GPIO_GROUP(GPIOH_7),
499 GPIO_GROUP(GPIOH_8, 0), 488 GPIO_GROUP(GPIOH_8),
500 GPIO_GROUP(GPIOH_9, 0), 489 GPIO_GROUP(GPIOH_9),
501 GPIO_GROUP(GPIOZ_0, 0), 490 GPIO_GROUP(GPIOZ_0),
502 GPIO_GROUP(GPIOZ_1, 0), 491 GPIO_GROUP(GPIOZ_1),
503 GPIO_GROUP(GPIOZ_2, 0), 492 GPIO_GROUP(GPIOZ_2),
504 GPIO_GROUP(GPIOZ_3, 0), 493 GPIO_GROUP(GPIOZ_3),
505 GPIO_GROUP(GPIOZ_4, 0), 494 GPIO_GROUP(GPIOZ_4),
506 GPIO_GROUP(GPIOZ_5, 0), 495 GPIO_GROUP(GPIOZ_5),
507 GPIO_GROUP(GPIOZ_6, 0), 496 GPIO_GROUP(GPIOZ_6),
508 GPIO_GROUP(GPIOZ_7, 0), 497 GPIO_GROUP(GPIOZ_7),
509 GPIO_GROUP(GPIOZ_8, 0), 498 GPIO_GROUP(GPIOZ_8),
510 GPIO_GROUP(GPIOZ_9, 0), 499 GPIO_GROUP(GPIOZ_9),
511 GPIO_GROUP(GPIOZ_10, 0), 500 GPIO_GROUP(GPIOZ_10),
512 GPIO_GROUP(GPIOZ_11, 0), 501 GPIO_GROUP(GPIOZ_11),
513 GPIO_GROUP(GPIOZ_12, 0), 502 GPIO_GROUP(GPIOZ_12),
514 GPIO_GROUP(GPIOZ_13, 0), 503 GPIO_GROUP(GPIOZ_13),
515 GPIO_GROUP(GPIOZ_14, 0), 504 GPIO_GROUP(GPIOZ_14),
516 505
517 /* bank X */ 506 /* bank X */
518 GROUP(sd_d0_a, 8, 5), 507 GROUP(sd_d0_a, 8, 5),
@@ -727,22 +716,22 @@ static struct meson_pmx_group meson8_cbus_groups[] = {
727}; 716};
728 717
729static struct meson_pmx_group meson8_aobus_groups[] = { 718static struct meson_pmx_group meson8_aobus_groups[] = {
730 GPIO_GROUP(GPIOAO_0, AO_OFF), 719 GPIO_GROUP(GPIOAO_0),
731 GPIO_GROUP(GPIOAO_1, AO_OFF), 720 GPIO_GROUP(GPIOAO_1),
732 GPIO_GROUP(GPIOAO_2, AO_OFF), 721 GPIO_GROUP(GPIOAO_2),
733 GPIO_GROUP(GPIOAO_3, AO_OFF), 722 GPIO_GROUP(GPIOAO_3),
734 GPIO_GROUP(GPIOAO_4, AO_OFF), 723 GPIO_GROUP(GPIOAO_4),
735 GPIO_GROUP(GPIOAO_5, AO_OFF), 724 GPIO_GROUP(GPIOAO_5),
736 GPIO_GROUP(GPIOAO_6, AO_OFF), 725 GPIO_GROUP(GPIOAO_6),
737 GPIO_GROUP(GPIOAO_7, AO_OFF), 726 GPIO_GROUP(GPIOAO_7),
738 GPIO_GROUP(GPIOAO_8, AO_OFF), 727 GPIO_GROUP(GPIOAO_8),
739 GPIO_GROUP(GPIOAO_9, AO_OFF), 728 GPIO_GROUP(GPIOAO_9),
740 GPIO_GROUP(GPIOAO_10, AO_OFF), 729 GPIO_GROUP(GPIOAO_10),
741 GPIO_GROUP(GPIOAO_11, AO_OFF), 730 GPIO_GROUP(GPIOAO_11),
742 GPIO_GROUP(GPIOAO_12, AO_OFF), 731 GPIO_GROUP(GPIOAO_12),
743 GPIO_GROUP(GPIOAO_13, AO_OFF), 732 GPIO_GROUP(GPIOAO_13),
744 GPIO_GROUP(GPIO_BSD_EN, AO_OFF), 733 GPIO_GROUP(GPIO_BSD_EN),
745 GPIO_GROUP(GPIO_TEST_N, AO_OFF), 734 GPIO_GROUP(GPIO_TEST_N),
746 735
747 /* bank AO */ 736 /* bank AO */
748 GROUP(uart_tx_ao_a, 0, 12), 737 GROUP(uart_tx_ao_a, 0, 12),
@@ -1041,24 +1030,23 @@ static struct meson_pmx_func meson8_aobus_functions[] = {
1041}; 1030};
1042 1031
1043static struct meson_bank meson8_cbus_banks[] = { 1032static struct meson_bank meson8_cbus_banks[] = {
1044 /* name first last irq pullen pull dir out in */ 1033 /* name first last irq pullen pull dir out in */
1045 BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 112, 133, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), 1034 BANK("X", GPIOX_0, GPIOX_21, 112, 133, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
1046 BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_16, 0), 95, 111, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), 1035 BANK("Y", GPIOY_0, GPIOY_16, 95, 111, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
1047 BANK("DV", PIN(GPIODV_0, 0), PIN(GPIODV_29, 0), 65, 94, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0), 1036 BANK("DV", GPIODV_0, GPIODV_29, 65, 94, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0),
1048 BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), 29, 38, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), 1037 BANK("H", GPIOH_0, GPIOH_9, 29, 38, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
1049 BANK("Z", PIN(GPIOZ_0, 0), PIN(GPIOZ_14, 0), 14, 28, 1, 0, 1, 0, 3, 17, 4, 17, 5, 17), 1038 BANK("Z", GPIOZ_0, GPIOZ_14, 14, 28, 1, 0, 1, 0, 3, 17, 4, 17, 5, 17),
1050 BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), 58, 64, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), 1039 BANK("CARD", CARD_0, CARD_6, 58, 64, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
1051 BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 39, 57, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), 1040 BANK("BOOT", BOOT_0, BOOT_18, 39, 57, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
1052}; 1041};
1053 1042
1054static struct meson_bank meson8_aobus_banks[] = { 1043static struct meson_bank meson8_aobus_banks[] = {
1055 /* name first last irq pullen pull dir out in */ 1044 /* name first last irq pullen pull dir out in */
1056 BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 13, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), 1045 BANK("AO", GPIOAO_0, GPIO_TEST_N, 0, 13, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
1057}; 1046};
1058 1047
1059struct meson_pinctrl_data meson8_cbus_pinctrl_data = { 1048static struct meson_pinctrl_data meson8_cbus_pinctrl_data = {
1060 .name = "cbus-banks", 1049 .name = "cbus-banks",
1061 .pin_base = 0,
1062 .pins = meson8_cbus_pins, 1050 .pins = meson8_cbus_pins,
1063 .groups = meson8_cbus_groups, 1051 .groups = meson8_cbus_groups,
1064 .funcs = meson8_cbus_functions, 1052 .funcs = meson8_cbus_functions,
@@ -1067,11 +1055,11 @@ struct meson_pinctrl_data meson8_cbus_pinctrl_data = {
1067 .num_groups = ARRAY_SIZE(meson8_cbus_groups), 1055 .num_groups = ARRAY_SIZE(meson8_cbus_groups),
1068 .num_funcs = ARRAY_SIZE(meson8_cbus_functions), 1056 .num_funcs = ARRAY_SIZE(meson8_cbus_functions),
1069 .num_banks = ARRAY_SIZE(meson8_cbus_banks), 1057 .num_banks = ARRAY_SIZE(meson8_cbus_banks),
1058 .pmx_ops = &meson8_pmx_ops,
1070}; 1059};
1071 1060
1072struct meson_pinctrl_data meson8_aobus_pinctrl_data = { 1061static struct meson_pinctrl_data meson8_aobus_pinctrl_data = {
1073 .name = "ao-bank", 1062 .name = "ao-bank",
1074 .pin_base = 120,
1075 .pins = meson8_aobus_pins, 1063 .pins = meson8_aobus_pins,
1076 .groups = meson8_aobus_groups, 1064 .groups = meson8_aobus_groups,
1077 .funcs = meson8_aobus_functions, 1065 .funcs = meson8_aobus_functions,
@@ -1080,4 +1068,26 @@ struct meson_pinctrl_data meson8_aobus_pinctrl_data = {
1080 .num_groups = ARRAY_SIZE(meson8_aobus_groups), 1068 .num_groups = ARRAY_SIZE(meson8_aobus_groups),
1081 .num_funcs = ARRAY_SIZE(meson8_aobus_functions), 1069 .num_funcs = ARRAY_SIZE(meson8_aobus_functions),
1082 .num_banks = ARRAY_SIZE(meson8_aobus_banks), 1070 .num_banks = ARRAY_SIZE(meson8_aobus_banks),
1071 .pmx_ops = &meson8_pmx_ops,
1072};
1073
1074static const struct of_device_id meson8_pinctrl_dt_match[] = {
1075 {
1076 .compatible = "amlogic,meson8-cbus-pinctrl",
1077 .data = &meson8_cbus_pinctrl_data,
1078 },
1079 {
1080 .compatible = "amlogic,meson8-aobus-pinctrl",
1081 .data = &meson8_aobus_pinctrl_data,
1082 },
1083 { },
1084};
1085
1086static struct platform_driver meson8_pinctrl_driver = {
1087 .probe = meson_pinctrl_probe,
1088 .driver = {
1089 .name = "meson8-pinctrl",
1090 .of_match_table = meson8_pinctrl_dt_match,
1091 },
1083}; 1092};
1093builtin_platform_driver(meson8_pinctrl_driver);
diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c
index 71f216b5b0b9..5bd808dc81e1 100644
--- a/drivers/pinctrl/meson/pinctrl-meson8b.c
+++ b/drivers/pinctrl/meson/pinctrl-meson8b.c
@@ -14,408 +14,405 @@
14 14
15#include <dt-bindings/gpio/meson8b-gpio.h> 15#include <dt-bindings/gpio/meson8b-gpio.h>
16#include "pinctrl-meson.h" 16#include "pinctrl-meson.h"
17 17#include "pinctrl-meson8-pmx.h"
18#define AO_OFF 130
19 18
20static const struct pinctrl_pin_desc meson8b_cbus_pins[] = { 19static const struct pinctrl_pin_desc meson8b_cbus_pins[] = {
21 MESON_PIN(GPIOX_0, 0), 20 MESON_PIN(GPIOX_0),
22 MESON_PIN(GPIOX_1, 0), 21 MESON_PIN(GPIOX_1),
23 MESON_PIN(GPIOX_2, 0), 22 MESON_PIN(GPIOX_2),
24 MESON_PIN(GPIOX_3, 0), 23 MESON_PIN(GPIOX_3),
25 MESON_PIN(GPIOX_4, 0), 24 MESON_PIN(GPIOX_4),
26 MESON_PIN(GPIOX_5, 0), 25 MESON_PIN(GPIOX_5),
27 MESON_PIN(GPIOX_6, 0), 26 MESON_PIN(GPIOX_6),
28 MESON_PIN(GPIOX_7, 0), 27 MESON_PIN(GPIOX_7),
29 MESON_PIN(GPIOX_8, 0), 28 MESON_PIN(GPIOX_8),
30 MESON_PIN(GPIOX_9, 0), 29 MESON_PIN(GPIOX_9),
31 MESON_PIN(GPIOX_10, 0), 30 MESON_PIN(GPIOX_10),
32 MESON_PIN(GPIOX_11, 0), 31 MESON_PIN(GPIOX_11),
33 MESON_PIN(GPIOX_16, 0), 32 MESON_PIN(GPIOX_16),
34 MESON_PIN(GPIOX_17, 0), 33 MESON_PIN(GPIOX_17),
35 MESON_PIN(GPIOX_18, 0), 34 MESON_PIN(GPIOX_18),
36 MESON_PIN(GPIOX_19, 0), 35 MESON_PIN(GPIOX_19),
37 MESON_PIN(GPIOX_20, 0), 36 MESON_PIN(GPIOX_20),
38 MESON_PIN(GPIOX_21, 0), 37 MESON_PIN(GPIOX_21),
39 38
40 MESON_PIN(GPIOY_0, 0), 39 MESON_PIN(GPIOY_0),
41 MESON_PIN(GPIOY_1, 0), 40 MESON_PIN(GPIOY_1),
42 MESON_PIN(GPIOY_3, 0), 41 MESON_PIN(GPIOY_3),
43 MESON_PIN(GPIOY_6, 0), 42 MESON_PIN(GPIOY_6),
44 MESON_PIN(GPIOY_7, 0), 43 MESON_PIN(GPIOY_7),
45 MESON_PIN(GPIOY_8, 0), 44 MESON_PIN(GPIOY_8),
46 MESON_PIN(GPIOY_9, 0), 45 MESON_PIN(GPIOY_9),
47 MESON_PIN(GPIOY_10, 0), 46 MESON_PIN(GPIOY_10),
48 MESON_PIN(GPIOY_11, 0), 47 MESON_PIN(GPIOY_11),
49 MESON_PIN(GPIOY_12, 0), 48 MESON_PIN(GPIOY_12),
50 MESON_PIN(GPIOY_13, 0), 49 MESON_PIN(GPIOY_13),
51 MESON_PIN(GPIOY_14, 0), 50 MESON_PIN(GPIOY_14),
52 51
53 MESON_PIN(GPIODV_9, 0), 52 MESON_PIN(GPIODV_9),
54 MESON_PIN(GPIODV_24, 0), 53 MESON_PIN(GPIODV_24),
55 MESON_PIN(GPIODV_25, 0), 54 MESON_PIN(GPIODV_25),
56 MESON_PIN(GPIODV_26, 0), 55 MESON_PIN(GPIODV_26),
57 MESON_PIN(GPIODV_27, 0), 56 MESON_PIN(GPIODV_27),
58 MESON_PIN(GPIODV_28, 0), 57 MESON_PIN(GPIODV_28),
59 MESON_PIN(GPIODV_29, 0), 58 MESON_PIN(GPIODV_29),
60 59
61 MESON_PIN(GPIOH_0, 0), 60 MESON_PIN(GPIOH_0),
62 MESON_PIN(GPIOH_1, 0), 61 MESON_PIN(GPIOH_1),
63 MESON_PIN(GPIOH_2, 0), 62 MESON_PIN(GPIOH_2),
64 MESON_PIN(GPIOH_3, 0), 63 MESON_PIN(GPIOH_3),
65 MESON_PIN(GPIOH_4, 0), 64 MESON_PIN(GPIOH_4),
66 MESON_PIN(GPIOH_5, 0), 65 MESON_PIN(GPIOH_5),
67 MESON_PIN(GPIOH_6, 0), 66 MESON_PIN(GPIOH_6),
68 MESON_PIN(GPIOH_7, 0), 67 MESON_PIN(GPIOH_7),
69 MESON_PIN(GPIOH_8, 0), 68 MESON_PIN(GPIOH_8),
70 MESON_PIN(GPIOH_9, 0), 69 MESON_PIN(GPIOH_9),
71 70
72 MESON_PIN(CARD_0, 0), 71 MESON_PIN(CARD_0),
73 MESON_PIN(CARD_1, 0), 72 MESON_PIN(CARD_1),
74 MESON_PIN(CARD_2, 0), 73 MESON_PIN(CARD_2),
75 MESON_PIN(CARD_3, 0), 74 MESON_PIN(CARD_3),
76 MESON_PIN(CARD_4, 0), 75 MESON_PIN(CARD_4),
77 MESON_PIN(CARD_5, 0), 76 MESON_PIN(CARD_5),
78 MESON_PIN(CARD_6, 0), 77 MESON_PIN(CARD_6),
79 78
80 MESON_PIN(BOOT_0, 0), 79 MESON_PIN(BOOT_0),
81 MESON_PIN(BOOT_1, 0), 80 MESON_PIN(BOOT_1),
82 MESON_PIN(BOOT_2, 0), 81 MESON_PIN(BOOT_2),
83 MESON_PIN(BOOT_3, 0), 82 MESON_PIN(BOOT_3),
84 MESON_PIN(BOOT_4, 0), 83 MESON_PIN(BOOT_4),
85 MESON_PIN(BOOT_5, 0), 84 MESON_PIN(BOOT_5),
86 MESON_PIN(BOOT_6, 0), 85 MESON_PIN(BOOT_6),
87 MESON_PIN(BOOT_7, 0), 86 MESON_PIN(BOOT_7),
88 MESON_PIN(BOOT_8, 0), 87 MESON_PIN(BOOT_8),
89 MESON_PIN(BOOT_9, 0), 88 MESON_PIN(BOOT_9),
90 MESON_PIN(BOOT_10, 0), 89 MESON_PIN(BOOT_10),
91 MESON_PIN(BOOT_11, 0), 90 MESON_PIN(BOOT_11),
92 MESON_PIN(BOOT_12, 0), 91 MESON_PIN(BOOT_12),
93 MESON_PIN(BOOT_13, 0), 92 MESON_PIN(BOOT_13),
94 MESON_PIN(BOOT_14, 0), 93 MESON_PIN(BOOT_14),
95 MESON_PIN(BOOT_15, 0), 94 MESON_PIN(BOOT_15),
96 MESON_PIN(BOOT_16, 0), 95 MESON_PIN(BOOT_16),
97 MESON_PIN(BOOT_17, 0), 96 MESON_PIN(BOOT_17),
98 MESON_PIN(BOOT_18, 0), 97 MESON_PIN(BOOT_18),
99 98
100 MESON_PIN(DIF_0_P, 0), 99 MESON_PIN(DIF_0_P),
101 MESON_PIN(DIF_0_N, 0), 100 MESON_PIN(DIF_0_N),
102 MESON_PIN(DIF_1_P, 0), 101 MESON_PIN(DIF_1_P),
103 MESON_PIN(DIF_1_N, 0), 102 MESON_PIN(DIF_1_N),
104 MESON_PIN(DIF_2_P, 0), 103 MESON_PIN(DIF_2_P),
105 MESON_PIN(DIF_2_N, 0), 104 MESON_PIN(DIF_2_N),
106 MESON_PIN(DIF_3_P, 0), 105 MESON_PIN(DIF_3_P),
107 MESON_PIN(DIF_3_N, 0), 106 MESON_PIN(DIF_3_N),
108 MESON_PIN(DIF_4_P, 0), 107 MESON_PIN(DIF_4_P),
109 MESON_PIN(DIF_4_N, 0), 108 MESON_PIN(DIF_4_N),
110}; 109};
111 110
112static const struct pinctrl_pin_desc meson8b_aobus_pins[] = { 111static const struct pinctrl_pin_desc meson8b_aobus_pins[] = {
113 MESON_PIN(GPIOAO_0, AO_OFF), 112 MESON_PIN(GPIOAO_0),
114 MESON_PIN(GPIOAO_1, AO_OFF), 113 MESON_PIN(GPIOAO_1),
115 MESON_PIN(GPIOAO_2, AO_OFF), 114 MESON_PIN(GPIOAO_2),
116 MESON_PIN(GPIOAO_3, AO_OFF), 115 MESON_PIN(GPIOAO_3),
117 MESON_PIN(GPIOAO_4, AO_OFF), 116 MESON_PIN(GPIOAO_4),
118 MESON_PIN(GPIOAO_5, AO_OFF), 117 MESON_PIN(GPIOAO_5),
119 MESON_PIN(GPIOAO_6, AO_OFF), 118 MESON_PIN(GPIOAO_6),
120 MESON_PIN(GPIOAO_7, AO_OFF), 119 MESON_PIN(GPIOAO_7),
121 MESON_PIN(GPIOAO_8, AO_OFF), 120 MESON_PIN(GPIOAO_8),
122 MESON_PIN(GPIOAO_9, AO_OFF), 121 MESON_PIN(GPIOAO_9),
123 MESON_PIN(GPIOAO_10, AO_OFF), 122 MESON_PIN(GPIOAO_10),
124 MESON_PIN(GPIOAO_11, AO_OFF), 123 MESON_PIN(GPIOAO_11),
125 MESON_PIN(GPIOAO_12, AO_OFF), 124 MESON_PIN(GPIOAO_12),
126 MESON_PIN(GPIOAO_13, AO_OFF), 125 MESON_PIN(GPIOAO_13),
127 126
128 /* 127 /*
129 * The following 2 pins are not mentionned in the public datasheet 128 * The following 2 pins are not mentionned in the public datasheet
130 * According to this datasheet, they can't be used with the gpio 129 * According to this datasheet, they can't be used with the gpio
131 * interrupt controller 130 * interrupt controller
132 */ 131 */
133 MESON_PIN(GPIO_BSD_EN, AO_OFF), 132 MESON_PIN(GPIO_BSD_EN),
134 MESON_PIN(GPIO_TEST_N, AO_OFF), 133 MESON_PIN(GPIO_TEST_N),
135}; 134};
136 135
137/* bank X */ 136/* bank X */
138static const unsigned int sd_d0_a_pins[] = { PIN(GPIOX_0, 0) }; 137static const unsigned int sd_d0_a_pins[] = { GPIOX_0 };
139static const unsigned int sd_d1_a_pins[] = { PIN(GPIOX_1, 0) }; 138static const unsigned int sd_d1_a_pins[] = { GPIOX_1 };
140static const unsigned int sd_d2_a_pins[] = { PIN(GPIOX_2, 0) }; 139static const unsigned int sd_d2_a_pins[] = { GPIOX_2 };
141static const unsigned int sd_d3_a_pins[] = { PIN(GPIOX_3, 0) }; 140static const unsigned int sd_d3_a_pins[] = { GPIOX_3 };
142static const unsigned int sdxc_d0_0_a_pins[] = { PIN(GPIOX_4, 0) }; 141static const unsigned int sdxc_d0_0_a_pins[] = { GPIOX_4 };
143static const unsigned int sdxc_d47_a_pins[] = { PIN(GPIOX_4, 0), PIN(GPIOX_5, 0), 142static const unsigned int sdxc_d47_a_pins[] = { GPIOX_4, GPIOX_5,
144 PIN(GPIOX_6, 0), PIN(GPIOX_7, 0) }; 143 GPIOX_6, GPIOX_7 };
145static const unsigned int sdxc_d13_0_a_pins[] = { PIN(GPIOX_5, 0), PIN(GPIOX_6, 0), 144static const unsigned int sdxc_d13_0_a_pins[] = { GPIOX_5, GPIOX_6,
146 PIN(GPIOX_7, 0) }; 145 GPIOX_7 };
147static const unsigned int sd_clk_a_pins[] = { PIN(GPIOX_8, 0) }; 146static const unsigned int sd_clk_a_pins[] = { GPIOX_8 };
148static const unsigned int sd_cmd_a_pins[] = { PIN(GPIOX_9, 0) }; 147static const unsigned int sd_cmd_a_pins[] = { GPIOX_9 };
149static const unsigned int xtal_32k_out_pins[] = { PIN(GPIOX_10, 0) }; 148static const unsigned int xtal_32k_out_pins[] = { GPIOX_10 };
150static const unsigned int xtal_24m_out_pins[] = { PIN(GPIOX_11, 0) }; 149static const unsigned int xtal_24m_out_pins[] = { GPIOX_11 };
151static const unsigned int uart_tx_b0_pins[] = { PIN(GPIOX_16, 0) }; 150static const unsigned int uart_tx_b0_pins[] = { GPIOX_16 };
152static const unsigned int uart_rx_b0_pins[] = { PIN(GPIOX_17, 0) }; 151static const unsigned int uart_rx_b0_pins[] = { GPIOX_17 };
153static const unsigned int uart_cts_b0_pins[] = { PIN(GPIOX_18, 0) }; 152static const unsigned int uart_cts_b0_pins[] = { GPIOX_18 };
154static const unsigned int uart_rts_b0_pins[] = { PIN(GPIOX_19, 0) }; 153static const unsigned int uart_rts_b0_pins[] = { GPIOX_19 };
155 154
156static const unsigned int sdxc_d0_1_a_pins[] = { PIN(GPIOX_0, 0) }; 155static const unsigned int sdxc_d0_1_a_pins[] = { GPIOX_0 };
157static const unsigned int sdxc_d13_1_a_pins[] = { PIN(GPIOX_1, 0), PIN(GPIOX_2, 0), 156static const unsigned int sdxc_d13_1_a_pins[] = { GPIOX_1, GPIOX_2,
158 PIN(GPIOX_3, 0) }; 157 GPIOX_3 };
159static const unsigned int pcm_out_a_pins[] = { PIN(GPIOX_4, 0) }; 158static const unsigned int pcm_out_a_pins[] = { GPIOX_4 };
160static const unsigned int pcm_in_a_pins[] = { PIN(GPIOX_5, 0) }; 159static const unsigned int pcm_in_a_pins[] = { GPIOX_5 };
161static const unsigned int pcm_fs_a_pins[] = { PIN(GPIOX_6, 0) }; 160static const unsigned int pcm_fs_a_pins[] = { GPIOX_6 };
162static const unsigned int pcm_clk_a_pins[] = { PIN(GPIOX_7, 0) }; 161static const unsigned int pcm_clk_a_pins[] = { GPIOX_7 };
163static const unsigned int sdxc_clk_a_pins[] = { PIN(GPIOX_8, 0) }; 162static const unsigned int sdxc_clk_a_pins[] = { GPIOX_8 };
164static const unsigned int sdxc_cmd_a_pins[] = { PIN(GPIOX_9, 0) }; 163static const unsigned int sdxc_cmd_a_pins[] = { GPIOX_9 };
165static const unsigned int pwm_vs_0_pins[] = { PIN(GPIOX_10, 0) }; 164static const unsigned int pwm_vs_0_pins[] = { GPIOX_10 };
166static const unsigned int pwm_e_pins[] = { PIN(GPIOX_10, 0) }; 165static const unsigned int pwm_e_pins[] = { GPIOX_10 };
167static const unsigned int pwm_vs_1_pins[] = { PIN(GPIOX_11, 0) }; 166static const unsigned int pwm_vs_1_pins[] = { GPIOX_11 };
168 167
169static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_4, 0) }; 168static const unsigned int uart_tx_a_pins[] = { GPIOX_4 };
170static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_5, 0) }; 169static const unsigned int uart_rx_a_pins[] = { GPIOX_5 };
171static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_6, 0) }; 170static const unsigned int uart_cts_a_pins[] = { GPIOX_6 };
172static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_7, 0) }; 171static const unsigned int uart_rts_a_pins[] = { GPIOX_7 };
173static const unsigned int uart_tx_b1_pins[] = { PIN(GPIOX_8, 0) }; 172static const unsigned int uart_tx_b1_pins[] = { GPIOX_8 };
174static const unsigned int uart_rx_b1_pins[] = { PIN(GPIOX_9, 0) }; 173static const unsigned int uart_rx_b1_pins[] = { GPIOX_9 };
175static const unsigned int uart_cts_b1_pins[] = { PIN(GPIOX_10, 0) }; 174static const unsigned int uart_cts_b1_pins[] = { GPIOX_10 };
176static const unsigned int uart_rts_b1_pins[] = { PIN(GPIOX_20, 0) }; 175static const unsigned int uart_rts_b1_pins[] = { GPIOX_20 };
177 176
178static const unsigned int iso7816_0_clk_pins[] = { PIN(GPIOX_6, 0) }; 177static const unsigned int iso7816_0_clk_pins[] = { GPIOX_6 };
179static const unsigned int iso7816_0_data_pins[] = { PIN(GPIOX_7, 0) }; 178static const unsigned int iso7816_0_data_pins[] = { GPIOX_7 };
180static const unsigned int spi_sclk_0_pins[] = { PIN(GPIOX_8, 0) }; 179static const unsigned int spi_sclk_0_pins[] = { GPIOX_8 };
181static const unsigned int spi_miso_0_pins[] = { PIN(GPIOX_9, 0) }; 180static const unsigned int spi_miso_0_pins[] = { GPIOX_9 };
182static const unsigned int spi_mosi_0_pins[] = { PIN(GPIOX_10, 0) }; 181static const unsigned int spi_mosi_0_pins[] = { GPIOX_10 };
183static const unsigned int iso7816_det_pins[] = { PIN(GPIOX_16, 0) }; 182static const unsigned int iso7816_det_pins[] = { GPIOX_16 };
184static const unsigned int iso7816_reset_pins[] = { PIN(GPIOX_17, 0) }; 183static const unsigned int iso7816_reset_pins[] = { GPIOX_17 };
185static const unsigned int iso7816_1_clk_pins[] = { PIN(GPIOX_18, 0) }; 184static const unsigned int iso7816_1_clk_pins[] = { GPIOX_18 };
186static const unsigned int iso7816_1_data_pins[] = { PIN(GPIOX_19, 0) }; 185static const unsigned int iso7816_1_data_pins[] = { GPIOX_19 };
187static const unsigned int spi_ss0_0_pins[] = { PIN(GPIOX_20, 0) }; 186static const unsigned int spi_ss0_0_pins[] = { GPIOX_20 };
188 187
189static const unsigned int tsin_clk_b_pins[] = { PIN(GPIOX_8, 0) }; 188static const unsigned int tsin_clk_b_pins[] = { GPIOX_8 };
190static const unsigned int tsin_sop_b_pins[] = { PIN(GPIOX_9, 0) }; 189static const unsigned int tsin_sop_b_pins[] = { GPIOX_9 };
191static const unsigned int tsin_d0_b_pins[] = { PIN(GPIOX_10, 0) }; 190static const unsigned int tsin_d0_b_pins[] = { GPIOX_10 };
192static const unsigned int pwm_b_pins[] = { PIN(GPIOX_11, 0) }; 191static const unsigned int pwm_b_pins[] = { GPIOX_11 };
193static const unsigned int i2c_sda_d0_pins[] = { PIN(GPIOX_16, 0) }; 192static const unsigned int i2c_sda_d0_pins[] = { GPIOX_16 };
194static const unsigned int i2c_sck_d0_pins[] = { PIN(GPIOX_17, 0) }; 193static const unsigned int i2c_sck_d0_pins[] = { GPIOX_17 };
195static const unsigned int tsin_d_valid_b_pins[] = { PIN(GPIOX_20, 0) }; 194static const unsigned int tsin_d_valid_b_pins[] = { GPIOX_20 };
196 195
197/* bank Y */ 196/* bank Y */
198static const unsigned int tsin_d_valid_a_pins[] = { PIN(GPIOY_0, 0) }; 197static const unsigned int tsin_d_valid_a_pins[] = { GPIOY_0 };
199static const unsigned int tsin_sop_a_pins[] = { PIN(GPIOY_1, 0) }; 198static const unsigned int tsin_sop_a_pins[] = { GPIOY_1 };
200static const unsigned int tsin_d17_a_pins[] = { PIN(GPIOY_6, 0), PIN(GPIOY_7, 0), 199static const unsigned int tsin_d17_a_pins[] = {
201 PIN(GPIOY_10, 0), PIN(GPIOY_11, 0), 200 GPIOY_6, GPIOY_7, GPIOY_10, GPIOY_11, GPIOY_12, GPIOY_13, GPIOY_14,
202 PIN(GPIOY_12, 0), PIN(GPIOY_13, 0), 201};
203 PIN(GPIOY_14, 0) }; 202static const unsigned int tsin_clk_a_pins[] = { GPIOY_8 };
204static const unsigned int tsin_clk_a_pins[] = { PIN(GPIOY_8, 0) }; 203static const unsigned int tsin_d0_a_pins[] = { GPIOY_9 };
205static const unsigned int tsin_d0_a_pins[] = { PIN(GPIOY_9, 0) };
206 204
207static const unsigned int spdif_out_0_pins[] = { PIN(GPIOY_3, 0) }; 205static const unsigned int spdif_out_0_pins[] = { GPIOY_3 };
208 206
209static const unsigned int xtal_24m_pins[] = { PIN(GPIOY_3, 0) }; 207static const unsigned int xtal_24m_pins[] = { GPIOY_3 };
210static const unsigned int iso7816_2_clk_pins[] = { PIN(GPIOY_13, 0) }; 208static const unsigned int iso7816_2_clk_pins[] = { GPIOY_13 };
211static const unsigned int iso7816_2_data_pins[] = { PIN(GPIOY_14, 0) }; 209static const unsigned int iso7816_2_data_pins[] = { GPIOY_14 };
212 210
213/* bank DV */ 211/* bank DV */
214static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, 0) }; 212static const unsigned int pwm_d_pins[] = { GPIODV_28 };
215static const unsigned int pwm_c0_pins[] = { PIN(GPIODV_29, 0) }; 213static const unsigned int pwm_c0_pins[] = { GPIODV_29 };
216 214
217static const unsigned int pwm_vs_2_pins[] = { PIN(GPIODV_9, 0) }; 215static const unsigned int pwm_vs_2_pins[] = { GPIODV_9 };
218static const unsigned int pwm_vs_3_pins[] = { PIN(GPIODV_28, 0) }; 216static const unsigned int pwm_vs_3_pins[] = { GPIODV_28 };
219static const unsigned int pwm_vs_4_pins[] = { PIN(GPIODV_29, 0) }; 217static const unsigned int pwm_vs_4_pins[] = { GPIODV_29 };
220 218
221static const unsigned int xtal24_out_pins[] = { PIN(GPIODV_29, 0) }; 219static const unsigned int xtal24_out_pins[] = { GPIODV_29 };
222 220
223static const unsigned int uart_tx_c_pins[] = { PIN(GPIODV_24, 0) }; 221static const unsigned int uart_tx_c_pins[] = { GPIODV_24 };
224static const unsigned int uart_rx_c_pins[] = { PIN(GPIODV_25, 0) }; 222static const unsigned int uart_rx_c_pins[] = { GPIODV_25 };
225static const unsigned int uart_cts_c_pins[] = { PIN(GPIODV_26, 0) }; 223static const unsigned int uart_cts_c_pins[] = { GPIODV_26 };
226static const unsigned int uart_rts_c_pins[] = { PIN(GPIODV_27, 0) }; 224static const unsigned int uart_rts_c_pins[] = { GPIODV_27 };
227 225
228static const unsigned int pwm_c1_pins[] = { PIN(GPIODV_9, 0) }; 226static const unsigned int pwm_c1_pins[] = { GPIODV_9 };
229 227
230static const unsigned int i2c_sda_a_pins[] = { PIN(GPIODV_24, 0) }; 228static const unsigned int i2c_sda_a_pins[] = { GPIODV_24 };
231static const unsigned int i2c_sck_a_pins[] = { PIN(GPIODV_25, 0) }; 229static const unsigned int i2c_sck_a_pins[] = { GPIODV_25 };
232static const unsigned int i2c_sda_b0_pins[] = { PIN(GPIODV_26, 0) }; 230static const unsigned int i2c_sda_b0_pins[] = { GPIODV_26 };
233static const unsigned int i2c_sck_b0_pins[] = { PIN(GPIODV_27, 0) }; 231static const unsigned int i2c_sck_b0_pins[] = { GPIODV_27 };
234static const unsigned int i2c_sda_c0_pins[] = { PIN(GPIODV_28, 0) }; 232static const unsigned int i2c_sda_c0_pins[] = { GPIODV_28 };
235static const unsigned int i2c_sck_c0_pins[] = { PIN(GPIODV_29, 0) }; 233static const unsigned int i2c_sck_c0_pins[] = { GPIODV_29 };
236 234
237/* bank H */ 235/* bank H */
238static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, 0) }; 236static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 };
239static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, 0) }; 237static const unsigned int hdmi_sda_pins[] = { GPIOH_1 };
240static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, 0) }; 238static const unsigned int hdmi_scl_pins[] = { GPIOH_2 };
241static const unsigned int hdmi_cec_0_pins[] = { PIN(GPIOH_3, 0) }; 239static const unsigned int hdmi_cec_0_pins[] = { GPIOH_3 };
242static const unsigned int eth_txd1_0_pins[] = { PIN(GPIOH_5, 0) }; 240static const unsigned int eth_txd1_0_pins[] = { GPIOH_5 };
243static const unsigned int eth_txd0_0_pins[] = { PIN(GPIOH_6, 0) }; 241static const unsigned int eth_txd0_0_pins[] = { GPIOH_6 };
244static const unsigned int clk_24m_out_pins[] = { PIN(GPIOH_9, 0) }; 242static const unsigned int clk_24m_out_pins[] = { GPIOH_9 };
245 243
246static const unsigned int spi_ss1_pins[] = { PIN(GPIOH_0, 0) }; 244static const unsigned int spi_ss1_pins[] = { GPIOH_0 };
247static const unsigned int spi_ss2_pins[] = { PIN(GPIOH_1, 0) }; 245static const unsigned int spi_ss2_pins[] = { GPIOH_1 };
248static const unsigned int spi_ss0_1_pins[] = { PIN(GPIOH_3, 0) }; 246static const unsigned int spi_ss0_1_pins[] = { GPIOH_3 };
249static const unsigned int spi_miso_1_pins[] = { PIN(GPIOH_4, 0) }; 247static const unsigned int spi_miso_1_pins[] = { GPIOH_4 };
250static const unsigned int spi_mosi_1_pins[] = { PIN(GPIOH_5, 0) }; 248static const unsigned int spi_mosi_1_pins[] = { GPIOH_5 };
251static const unsigned int spi_sclk_1_pins[] = { PIN(GPIOH_6, 0) }; 249static const unsigned int spi_sclk_1_pins[] = { GPIOH_6 };
252 250
253static const unsigned int eth_txd3_pins[] = { PIN(GPIOH_7, 0) }; 251static const unsigned int eth_txd3_pins[] = { GPIOH_7 };
254static const unsigned int eth_txd2_pins[] = { PIN(GPIOH_8, 0) }; 252static const unsigned int eth_txd2_pins[] = { GPIOH_8 };
255static const unsigned int eth_tx_clk_pins[] = { PIN(GPIOH_9, 0) }; 253static const unsigned int eth_tx_clk_pins[] = { GPIOH_9 };
256 254
257static const unsigned int i2c_sda_b1_pins[] = { PIN(GPIOH_3, 0) }; 255static const unsigned int i2c_sda_b1_pins[] = { GPIOH_3 };
258static const unsigned int i2c_sck_b1_pins[] = { PIN(GPIOH_4, 0) }; 256static const unsigned int i2c_sck_b1_pins[] = { GPIOH_4 };
259static const unsigned int i2c_sda_c1_pins[] = { PIN(GPIOH_5, 0) }; 257static const unsigned int i2c_sda_c1_pins[] = { GPIOH_5 };
260static const unsigned int i2c_sck_c1_pins[] = { PIN(GPIOH_6, 0) }; 258static const unsigned int i2c_sck_c1_pins[] = { GPIOH_6 };
261static const unsigned int i2c_sda_d1_pins[] = { PIN(GPIOH_7, 0) }; 259static const unsigned int i2c_sda_d1_pins[] = { GPIOH_7 };
262static const unsigned int i2c_sck_d1_pins[] = { PIN(GPIOH_8, 0) }; 260static const unsigned int i2c_sck_d1_pins[] = { GPIOH_8 };
263 261
264/* bank BOOT */ 262/* bank BOOT */
265static const unsigned int nand_io_pins[] = { PIN(BOOT_0, 0), PIN(BOOT_1, 0), 263static const unsigned int nand_io_pins[] = {
266 PIN(BOOT_2, 0), PIN(BOOT_3, 0), 264 BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7
267 PIN(BOOT_4, 0), PIN(BOOT_5, 0), 265};
268 PIN(BOOT_6, 0), PIN(BOOT_7, 0) }; 266static const unsigned int nand_io_ce0_pins[] = { BOOT_8 };
269static const unsigned int nand_io_ce0_pins[] = { PIN(BOOT_8, 0) }; 267static const unsigned int nand_io_ce1_pins[] = { BOOT_9 };
270static const unsigned int nand_io_ce1_pins[] = { PIN(BOOT_9, 0) }; 268static const unsigned int nand_io_rb0_pins[] = { BOOT_10 };
271static const unsigned int nand_io_rb0_pins[] = { PIN(BOOT_10, 0) }; 269static const unsigned int nand_ale_pins[] = { BOOT_11 };
272static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, 0) }; 270static const unsigned int nand_cle_pins[] = { BOOT_12 };
273static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, 0) }; 271static const unsigned int nand_wen_clk_pins[] = { BOOT_13 };
274static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, 0) }; 272static const unsigned int nand_ren_clk_pins[] = { BOOT_14 };
275static const unsigned int nand_ren_clk_pins[] = { PIN(BOOT_14, 0) }; 273static const unsigned int nand_dqs_15_pins[] = { BOOT_15 };
276static const unsigned int nand_dqs_15_pins[] = { PIN(BOOT_15, 0) }; 274static const unsigned int nand_dqs_18_pins[] = { BOOT_18 };
277static const unsigned int nand_dqs_18_pins[] = { PIN(BOOT_18, 0) }; 275
278 276static const unsigned int sdxc_d0_c_pins[] = { BOOT_0};
279static const unsigned int sdxc_d0_c_pins[] = { PIN(BOOT_0, 0)}; 277static const unsigned int sdxc_d13_c_pins[] = { BOOT_1, BOOT_2,
280static const unsigned int sdxc_d13_c_pins[] = { PIN(BOOT_1, 0), PIN(BOOT_2, 0), 278 BOOT_3 };
281 PIN(BOOT_3, 0) }; 279static const unsigned int sdxc_d47_c_pins[] = { BOOT_4, BOOT_5,
282static const unsigned int sdxc_d47_c_pins[] = { PIN(BOOT_4, 0), PIN(BOOT_5, 0), 280 BOOT_6, BOOT_7 };
283 PIN(BOOT_6, 0), PIN(BOOT_7, 0) }; 281static const unsigned int sdxc_clk_c_pins[] = { BOOT_8 };
284static const unsigned int sdxc_clk_c_pins[] = { PIN(BOOT_8, 0) }; 282static const unsigned int sdxc_cmd_c_pins[] = { BOOT_10 };
285static const unsigned int sdxc_cmd_c_pins[] = { PIN(BOOT_10, 0) }; 283static const unsigned int nor_d_pins[] = { BOOT_11 };
286static const unsigned int nor_d_pins[] = { PIN(BOOT_11, 0) }; 284static const unsigned int nor_q_pins[] = { BOOT_12 };
287static const unsigned int nor_q_pins[] = { PIN(BOOT_12, 0) }; 285static const unsigned int nor_c_pins[] = { BOOT_13 };
288static const unsigned int nor_c_pins[] = { PIN(BOOT_13, 0) }; 286static const unsigned int nor_cs_pins[] = { BOOT_18 };
289static const unsigned int nor_cs_pins[] = { PIN(BOOT_18, 0) }; 287
290 288static const unsigned int sd_d0_c_pins[] = { BOOT_0 };
291static const unsigned int sd_d0_c_pins[] = { PIN(BOOT_0, 0) }; 289static const unsigned int sd_d1_c_pins[] = { BOOT_1 };
292static const unsigned int sd_d1_c_pins[] = { PIN(BOOT_1, 0) }; 290static const unsigned int sd_d2_c_pins[] = { BOOT_2 };
293static const unsigned int sd_d2_c_pins[] = { PIN(BOOT_2, 0) }; 291static const unsigned int sd_d3_c_pins[] = { BOOT_3 };
294static const unsigned int sd_d3_c_pins[] = { PIN(BOOT_3, 0) }; 292static const unsigned int sd_cmd_c_pins[] = { BOOT_8 };
295static const unsigned int sd_cmd_c_pins[] = { PIN(BOOT_8, 0) }; 293static const unsigned int sd_clk_c_pins[] = { BOOT_10 };
296static const unsigned int sd_clk_c_pins[] = { PIN(BOOT_10, 0) };
297 294
298/* bank CARD */ 295/* bank CARD */
299static const unsigned int sd_d1_b_pins[] = { PIN(CARD_0, 0) }; 296static const unsigned int sd_d1_b_pins[] = { CARD_0 };
300static const unsigned int sd_d0_b_pins[] = { PIN(CARD_1, 0) }; 297static const unsigned int sd_d0_b_pins[] = { CARD_1 };
301static const unsigned int sd_clk_b_pins[] = { PIN(CARD_2, 0) }; 298static const unsigned int sd_clk_b_pins[] = { CARD_2 };
302static const unsigned int sd_cmd_b_pins[] = { PIN(CARD_3, 0) }; 299static const unsigned int sd_cmd_b_pins[] = { CARD_3 };
303static const unsigned int sd_d3_b_pins[] = { PIN(CARD_4, 0) }; 300static const unsigned int sd_d3_b_pins[] = { CARD_4 };
304static const unsigned int sd_d2_b_pins[] = { PIN(CARD_5, 0) }; 301static const unsigned int sd_d2_b_pins[] = { CARD_5 };
305 302
306static const unsigned int sdxc_d13_b_pins[] = { PIN(CARD_0, 0), PIN(CARD_4, 0), 303static const unsigned int sdxc_d13_b_pins[] = { CARD_0, CARD_4,
307 PIN(CARD_5, 0) }; 304 CARD_5 };
308static const unsigned int sdxc_d0_b_pins[] = { PIN(CARD_1, 0) }; 305static const unsigned int sdxc_d0_b_pins[] = { CARD_1 };
309static const unsigned int sdxc_clk_b_pins[] = { PIN(CARD_2, 0) }; 306static const unsigned int sdxc_clk_b_pins[] = { CARD_2 };
310static const unsigned int sdxc_cmd_b_pins[] = { PIN(CARD_3, 0) }; 307static const unsigned int sdxc_cmd_b_pins[] = { CARD_3 };
311 308
312/* bank AO */ 309/* bank AO */
313static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, AO_OFF) }; 310static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 };
314static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, AO_OFF) }; 311static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 };
315static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, AO_OFF) }; 312static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 };
316static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, AO_OFF) }; 313static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 };
317static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) }; 314static const unsigned int i2c_mst_sck_ao_pins[] = { GPIOAO_4 };
318static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; 315static const unsigned int i2c_mst_sda_ao_pins[] = { GPIOAO_5 };
319static const unsigned int clk_32k_in_out_pins[] = { PIN(GPIOAO_6, AO_OFF) }; 316static const unsigned int clk_32k_in_out_pins[] = { GPIOAO_6 };
320static const unsigned int remote_input_pins[] = { PIN(GPIOAO_7, AO_OFF) }; 317static const unsigned int remote_input_pins[] = { GPIOAO_7 };
321static const unsigned int hdmi_cec_1_pins[] = { PIN(GPIOAO_12, AO_OFF) }; 318static const unsigned int hdmi_cec_1_pins[] = { GPIOAO_12 };
322static const unsigned int ir_blaster_pins[] = { PIN(GPIOAO_13, AO_OFF) }; 319static const unsigned int ir_blaster_pins[] = { GPIOAO_13 };
323 320
324static const unsigned int pwm_c2_pins[] = { PIN(GPIOAO_3, AO_OFF) }; 321static const unsigned int pwm_c2_pins[] = { GPIOAO_3 };
325static const unsigned int i2c_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) }; 322static const unsigned int i2c_sck_ao_pins[] = { GPIOAO_4 };
326static const unsigned int i2c_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; 323static const unsigned int i2c_sda_ao_pins[] = { GPIOAO_5 };
327static const unsigned int ir_remote_out_pins[] = { PIN(GPIOAO_7, AO_OFF) }; 324static const unsigned int ir_remote_out_pins[] = { GPIOAO_7 };
328static const unsigned int i2s_am_clk_out_pins[] = { PIN(GPIOAO_8, AO_OFF) }; 325static const unsigned int i2s_am_clk_out_pins[] = { GPIOAO_8 };
329static const unsigned int i2s_ao_clk_out_pins[] = { PIN(GPIOAO_9, AO_OFF) }; 326static const unsigned int i2s_ao_clk_out_pins[] = { GPIOAO_9 };
330static const unsigned int i2s_lr_clk_out_pins[] = { PIN(GPIOAO_10, AO_OFF) }; 327static const unsigned int i2s_lr_clk_out_pins[] = { GPIOAO_10 };
331static const unsigned int i2s_out_01_pins[] = { PIN(GPIOAO_11, AO_OFF) }; 328static const unsigned int i2s_out_01_pins[] = { GPIOAO_11 };
332 329
333static const unsigned int uart_tx_ao_b0_pins[] = { PIN(GPIOAO_0, AO_OFF) }; 330static const unsigned int uart_tx_ao_b0_pins[] = { GPIOAO_0 };
334static const unsigned int uart_rx_ao_b0_pins[] = { PIN(GPIOAO_1, AO_OFF) }; 331static const unsigned int uart_rx_ao_b0_pins[] = { GPIOAO_1 };
335static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, AO_OFF) }; 332static const unsigned int uart_cts_ao_b_pins[] = { GPIOAO_2 };
336static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, AO_OFF) }; 333static const unsigned int uart_rts_ao_b_pins[] = { GPIOAO_3 };
337static const unsigned int uart_tx_ao_b1_pins[] = { PIN(GPIOAO_4, AO_OFF) }; 334static const unsigned int uart_tx_ao_b1_pins[] = { GPIOAO_4 };
338static const unsigned int uart_rx_ao_b1_pins[] = { PIN(GPIOAO_5, AO_OFF) }; 335static const unsigned int uart_rx_ao_b1_pins[] = { GPIOAO_5 };
339static const unsigned int spdif_out_1_pins[] = { PIN(GPIOAO_6, AO_OFF) }; 336static const unsigned int spdif_out_1_pins[] = { GPIOAO_6 };
340 337
341static const unsigned int i2s_in_ch01_pins[] = { PIN(GPIOAO_6, AO_OFF) }; 338static const unsigned int i2s_in_ch01_pins[] = { GPIOAO_6 };
342static const unsigned int i2s_ao_clk_in_pins[] = { PIN(GPIOAO_9, AO_OFF) }; 339static const unsigned int i2s_ao_clk_in_pins[] = { GPIOAO_9 };
343static const unsigned int i2s_lr_clk_in_pins[] = { PIN(GPIOAO_10, AO_OFF) }; 340static const unsigned int i2s_lr_clk_in_pins[] = { GPIOAO_10 };
344 341
345/* bank DIF */ 342/* bank DIF */
346static const unsigned int eth_rxd1_pins[] = { PIN(DIF_0_P, 0) }; 343static const unsigned int eth_rxd1_pins[] = { DIF_0_P };
347static const unsigned int eth_rxd0_pins[] = { PIN(DIF_0_N, 0) }; 344static const unsigned int eth_rxd0_pins[] = { DIF_0_N };
348static const unsigned int eth_rx_dv_pins[] = { PIN(DIF_1_P, 0) }; 345static const unsigned int eth_rx_dv_pins[] = { DIF_1_P };
349static const unsigned int eth_rx_clk_pins[] = { PIN(DIF_1_N, 0) }; 346static const unsigned int eth_rx_clk_pins[] = { DIF_1_N };
350static const unsigned int eth_txd0_1_pins[] = { PIN(DIF_2_P, 0) }; 347static const unsigned int eth_txd0_1_pins[] = { DIF_2_P };
351static const unsigned int eth_txd1_1_pins[] = { PIN(DIF_2_N, 0) }; 348static const unsigned int eth_txd1_1_pins[] = { DIF_2_N };
352static const unsigned int eth_tx_en_pins[] = { PIN(DIF_3_P, 0) }; 349static const unsigned int eth_tx_en_pins[] = { DIF_3_P };
353static const unsigned int eth_ref_clk_pins[] = { PIN(DIF_3_N, 0) }; 350static const unsigned int eth_ref_clk_pins[] = { DIF_3_N };
354static const unsigned int eth_mdc_pins[] = { PIN(DIF_4_P, 0) }; 351static const unsigned int eth_mdc_pins[] = { DIF_4_P };
355static const unsigned int eth_mdio_en_pins[] = { PIN(DIF_4_N, 0) }; 352static const unsigned int eth_mdio_en_pins[] = { DIF_4_N };
356 353
357static struct meson_pmx_group meson8b_cbus_groups[] = { 354static struct meson_pmx_group meson8b_cbus_groups[] = {
358 GPIO_GROUP(GPIOX_0, 0), 355 GPIO_GROUP(GPIOX_0),
359 GPIO_GROUP(GPIOX_1, 0), 356 GPIO_GROUP(GPIOX_1),
360 GPIO_GROUP(GPIOX_2, 0), 357 GPIO_GROUP(GPIOX_2),
361 GPIO_GROUP(GPIOX_3, 0), 358 GPIO_GROUP(GPIOX_3),
362 GPIO_GROUP(GPIOX_4, 0), 359 GPIO_GROUP(GPIOX_4),
363 GPIO_GROUP(GPIOX_5, 0), 360 GPIO_GROUP(GPIOX_5),
364 GPIO_GROUP(GPIOX_6, 0), 361 GPIO_GROUP(GPIOX_6),
365 GPIO_GROUP(GPIOX_7, 0), 362 GPIO_GROUP(GPIOX_7),
366 GPIO_GROUP(GPIOX_8, 0), 363 GPIO_GROUP(GPIOX_8),
367 GPIO_GROUP(GPIOX_9, 0), 364 GPIO_GROUP(GPIOX_9),
368 GPIO_GROUP(GPIOX_10, 0), 365 GPIO_GROUP(GPIOX_10),
369 GPIO_GROUP(GPIOX_11, 0), 366 GPIO_GROUP(GPIOX_11),
370 GPIO_GROUP(GPIOX_16, 0), 367 GPIO_GROUP(GPIOX_16),
371 GPIO_GROUP(GPIOX_17, 0), 368 GPIO_GROUP(GPIOX_17),
372 GPIO_GROUP(GPIOX_18, 0), 369 GPIO_GROUP(GPIOX_18),
373 GPIO_GROUP(GPIOX_19, 0), 370 GPIO_GROUP(GPIOX_19),
374 GPIO_GROUP(GPIOX_20, 0), 371 GPIO_GROUP(GPIOX_20),
375 GPIO_GROUP(GPIOX_21, 0), 372 GPIO_GROUP(GPIOX_21),
376 373
377 GPIO_GROUP(GPIOY_0, 0), 374 GPIO_GROUP(GPIOY_0),
378 GPIO_GROUP(GPIOY_1, 0), 375 GPIO_GROUP(GPIOY_1),
379 GPIO_GROUP(GPIOY_3, 0), 376 GPIO_GROUP(GPIOY_3),
380 GPIO_GROUP(GPIOY_6, 0), 377 GPIO_GROUP(GPIOY_6),
381 GPIO_GROUP(GPIOY_7, 0), 378 GPIO_GROUP(GPIOY_7),
382 GPIO_GROUP(GPIOY_8, 0), 379 GPIO_GROUP(GPIOY_8),
383 GPIO_GROUP(GPIOY_9, 0), 380 GPIO_GROUP(GPIOY_9),
384 GPIO_GROUP(GPIOY_10, 0), 381 GPIO_GROUP(GPIOY_10),
385 GPIO_GROUP(GPIOY_11, 0), 382 GPIO_GROUP(GPIOY_11),
386 GPIO_GROUP(GPIOY_12, 0), 383 GPIO_GROUP(GPIOY_12),
387 GPIO_GROUP(GPIOY_13, 0), 384 GPIO_GROUP(GPIOY_13),
388 GPIO_GROUP(GPIOY_14, 0), 385 GPIO_GROUP(GPIOY_14),
389 386
390 GPIO_GROUP(GPIODV_9, 0), 387 GPIO_GROUP(GPIODV_9),
391 GPIO_GROUP(GPIODV_24, 0), 388 GPIO_GROUP(GPIODV_24),
392 GPIO_GROUP(GPIODV_25, 0), 389 GPIO_GROUP(GPIODV_25),
393 GPIO_GROUP(GPIODV_26, 0), 390 GPIO_GROUP(GPIODV_26),
394 GPIO_GROUP(GPIODV_27, 0), 391 GPIO_GROUP(GPIODV_27),
395 GPIO_GROUP(GPIODV_28, 0), 392 GPIO_GROUP(GPIODV_28),
396 GPIO_GROUP(GPIODV_29, 0), 393 GPIO_GROUP(GPIODV_29),
397 394
398 GPIO_GROUP(GPIOH_0, 0), 395 GPIO_GROUP(GPIOH_0),
399 GPIO_GROUP(GPIOH_1, 0), 396 GPIO_GROUP(GPIOH_1),
400 GPIO_GROUP(GPIOH_2, 0), 397 GPIO_GROUP(GPIOH_2),
401 GPIO_GROUP(GPIOH_3, 0), 398 GPIO_GROUP(GPIOH_3),
402 GPIO_GROUP(GPIOH_4, 0), 399 GPIO_GROUP(GPIOH_4),
403 GPIO_GROUP(GPIOH_5, 0), 400 GPIO_GROUP(GPIOH_5),
404 GPIO_GROUP(GPIOH_6, 0), 401 GPIO_GROUP(GPIOH_6),
405 GPIO_GROUP(GPIOH_7, 0), 402 GPIO_GROUP(GPIOH_7),
406 GPIO_GROUP(GPIOH_8, 0), 403 GPIO_GROUP(GPIOH_8),
407 GPIO_GROUP(GPIOH_9, 0), 404 GPIO_GROUP(GPIOH_9),
408 405
409 GPIO_GROUP(DIF_0_P, 0), 406 GPIO_GROUP(DIF_0_P),
410 GPIO_GROUP(DIF_0_N, 0), 407 GPIO_GROUP(DIF_0_N),
411 GPIO_GROUP(DIF_1_P, 0), 408 GPIO_GROUP(DIF_1_P),
412 GPIO_GROUP(DIF_1_N, 0), 409 GPIO_GROUP(DIF_1_N),
413 GPIO_GROUP(DIF_2_P, 0), 410 GPIO_GROUP(DIF_2_P),
414 GPIO_GROUP(DIF_2_N, 0), 411 GPIO_GROUP(DIF_2_N),
415 GPIO_GROUP(DIF_3_P, 0), 412 GPIO_GROUP(DIF_3_P),
416 GPIO_GROUP(DIF_3_N, 0), 413 GPIO_GROUP(DIF_3_N),
417 GPIO_GROUP(DIF_4_P, 0), 414 GPIO_GROUP(DIF_4_P),
418 GPIO_GROUP(DIF_4_N, 0), 415 GPIO_GROUP(DIF_4_N),
419 416
420 /* bank X */ 417 /* bank X */
421 GROUP(sd_d0_a, 8, 5), 418 GROUP(sd_d0_a, 8, 5),
@@ -577,22 +574,22 @@ static struct meson_pmx_group meson8b_cbus_groups[] = {
577}; 574};
578 575
579static struct meson_pmx_group meson8b_aobus_groups[] = { 576static struct meson_pmx_group meson8b_aobus_groups[] = {
580 GPIO_GROUP(GPIOAO_0, AO_OFF), 577 GPIO_GROUP(GPIOAO_0),
581 GPIO_GROUP(GPIOAO_1, AO_OFF), 578 GPIO_GROUP(GPIOAO_1),
582 GPIO_GROUP(GPIOAO_2, AO_OFF), 579 GPIO_GROUP(GPIOAO_2),
583 GPIO_GROUP(GPIOAO_3, AO_OFF), 580 GPIO_GROUP(GPIOAO_3),
584 GPIO_GROUP(GPIOAO_4, AO_OFF), 581 GPIO_GROUP(GPIOAO_4),
585 GPIO_GROUP(GPIOAO_5, AO_OFF), 582 GPIO_GROUP(GPIOAO_5),
586 GPIO_GROUP(GPIOAO_6, AO_OFF), 583 GPIO_GROUP(GPIOAO_6),
587 GPIO_GROUP(GPIOAO_7, AO_OFF), 584 GPIO_GROUP(GPIOAO_7),
588 GPIO_GROUP(GPIOAO_8, AO_OFF), 585 GPIO_GROUP(GPIOAO_8),
589 GPIO_GROUP(GPIOAO_9, AO_OFF), 586 GPIO_GROUP(GPIOAO_9),
590 GPIO_GROUP(GPIOAO_10, AO_OFF), 587 GPIO_GROUP(GPIOAO_10),
591 GPIO_GROUP(GPIOAO_11, AO_OFF), 588 GPIO_GROUP(GPIOAO_11),
592 GPIO_GROUP(GPIOAO_12, AO_OFF), 589 GPIO_GROUP(GPIOAO_12),
593 GPIO_GROUP(GPIOAO_13, AO_OFF), 590 GPIO_GROUP(GPIOAO_13),
594 GPIO_GROUP(GPIO_BSD_EN, AO_OFF), 591 GPIO_GROUP(GPIO_BSD_EN),
595 GPIO_GROUP(GPIO_TEST_N, AO_OFF), 592 GPIO_GROUP(GPIO_TEST_N),
596 593
597 /* bank AO */ 594 /* bank AO */
598 GROUP(uart_tx_ao_a, 0, 12), 595 GROUP(uart_tx_ao_a, 0, 12),
@@ -887,30 +884,29 @@ static struct meson_pmx_func meson8b_aobus_functions[] = {
887}; 884};
888 885
889static struct meson_bank meson8b_cbus_banks[] = { 886static struct meson_bank meson8b_cbus_banks[] = {
890 /* name first last irq pullen pull dir out in */ 887 /* name first last irq pullen pull dir out in */
891 BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 97, 118, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), 888 BANK("X", GPIOX_0, GPIOX_21, 97, 118, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
892 BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_14, 0), 80, 96, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), 889 BANK("Y", GPIOY_0, GPIOY_14, 80, 96, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
893 BANK("DV", PIN(GPIODV_9, 0), PIN(GPIODV_29, 0), 59, 79, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0), 890 BANK("DV", GPIODV_9, GPIODV_29, 59, 79, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0),
894 BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), 14, 23, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), 891 BANK("H", GPIOH_0, GPIOH_9, 14, 23, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
895 BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), 43, 49, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), 892 BANK("CARD", CARD_0, CARD_6, 43, 49, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
896 BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 24, 42, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), 893 BANK("BOOT", BOOT_0, BOOT_18, 24, 42, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
897 894
898 /* 895 /*
899 * The following bank is not mentionned in the public datasheet 896 * The following bank is not mentionned in the public datasheet
900 * There is no information whether it can be used with the gpio 897 * There is no information whether it can be used with the gpio
901 * interrupt controller 898 * interrupt controller
902 */ 899 */
903 BANK("DIF", PIN(DIF_0_P, 0), PIN(DIF_4_N, 0), -1, -1, 5, 8, 5, 8, 12, 12, 13, 12, 14, 12), 900 BANK("DIF", DIF_0_P, DIF_4_N, -1, -1, 5, 8, 5, 8, 12, 12, 13, 12, 14, 12),
904}; 901};
905 902
906static struct meson_bank meson8b_aobus_banks[] = { 903static struct meson_bank meson8b_aobus_banks[] = {
907 /* name first last irq pullen pull dir out in */ 904 /* name first lastc irq pullen pull dir out in */
908 BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 13, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), 905 BANK("AO", GPIOAO_0, GPIO_TEST_N, 0, 13, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
909}; 906};
910 907
911struct meson_pinctrl_data meson8b_cbus_pinctrl_data = { 908static struct meson_pinctrl_data meson8b_cbus_pinctrl_data = {
912 .name = "cbus-banks", 909 .name = "cbus-banks",
913 .pin_base = 0,
914 .pins = meson8b_cbus_pins, 910 .pins = meson8b_cbus_pins,
915 .groups = meson8b_cbus_groups, 911 .groups = meson8b_cbus_groups,
916 .funcs = meson8b_cbus_functions, 912 .funcs = meson8b_cbus_functions,
@@ -919,11 +915,11 @@ struct meson_pinctrl_data meson8b_cbus_pinctrl_data = {
919 .num_groups = ARRAY_SIZE(meson8b_cbus_groups), 915 .num_groups = ARRAY_SIZE(meson8b_cbus_groups),
920 .num_funcs = ARRAY_SIZE(meson8b_cbus_functions), 916 .num_funcs = ARRAY_SIZE(meson8b_cbus_functions),
921 .num_banks = ARRAY_SIZE(meson8b_cbus_banks), 917 .num_banks = ARRAY_SIZE(meson8b_cbus_banks),
918 .pmx_ops = &meson8_pmx_ops,
922}; 919};
923 920
924struct meson_pinctrl_data meson8b_aobus_pinctrl_data = { 921static struct meson_pinctrl_data meson8b_aobus_pinctrl_data = {
925 .name = "aobus-banks", 922 .name = "aobus-banks",
926 .pin_base = 130,
927 .pins = meson8b_aobus_pins, 923 .pins = meson8b_aobus_pins,
928 .groups = meson8b_aobus_groups, 924 .groups = meson8b_aobus_groups,
929 .funcs = meson8b_aobus_functions, 925 .funcs = meson8b_aobus_functions,
@@ -932,4 +928,26 @@ struct meson_pinctrl_data meson8b_aobus_pinctrl_data = {
932 .num_groups = ARRAY_SIZE(meson8b_aobus_groups), 928 .num_groups = ARRAY_SIZE(meson8b_aobus_groups),
933 .num_funcs = ARRAY_SIZE(meson8b_aobus_functions), 929 .num_funcs = ARRAY_SIZE(meson8b_aobus_functions),
934 .num_banks = ARRAY_SIZE(meson8b_aobus_banks), 930 .num_banks = ARRAY_SIZE(meson8b_aobus_banks),
931 .pmx_ops = &meson8_pmx_ops,
932};
933
934static const struct of_device_id meson8b_pinctrl_dt_match[] = {
935 {
936 .compatible = "amlogic,meson8b-cbus-pinctrl",
937 .data = &meson8b_cbus_pinctrl_data,
938 },
939 {
940 .compatible = "amlogic,meson8b-aobus-pinctrl",
941 .data = &meson8b_aobus_pinctrl_data,
942 },
943 { },
944};
945
946static struct platform_driver meson8b_pinctrl_driver = {
947 .probe = meson_pinctrl_probe,
948 .driver = {
949 .name = "meson8b-pinctrl",
950 .of_match_table = meson8b_pinctrl_dt_match,
951 },
935}; 952};
953builtin_platform_driver(meson8b_pinctrl_driver);
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
index d754a9b10e19..d45af31b86b4 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
@@ -576,6 +576,19 @@ static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
576 case IRQ_TYPE_EDGE_FALLING: 576 case IRQ_TYPE_EDGE_FALLING:
577 val |= (BIT(d->hwirq % GPIO_PER_REG)); 577 val |= (BIT(d->hwirq % GPIO_PER_REG));
578 break; 578 break;
579 case IRQ_TYPE_EDGE_BOTH: {
580 u32 in_val, in_reg = INPUT_VAL;
581
582 armada_37xx_irq_update_reg(&in_reg, d);
583 regmap_read(info->regmap, in_reg, &in_val);
584
585 /* Set initial polarity based on current input level. */
586 if (in_val & d->mask)
587 val |= d->mask; /* falling */
588 else
589 val &= ~d->mask; /* rising */
590 break;
591 }
579 default: 592 default:
580 spin_unlock_irqrestore(&info->irq_lock, flags); 593 spin_unlock_irqrestore(&info->irq_lock, flags);
581 return -EINVAL; 594 return -EINVAL;
@@ -586,6 +599,40 @@ static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
586 return 0; 599 return 0;
587} 600}
588 601
602static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info,
603 u32 pin_idx)
604{
605 u32 reg_idx = pin_idx / GPIO_PER_REG;
606 u32 bit_num = pin_idx % GPIO_PER_REG;
607 u32 p, l, ret;
608 unsigned long flags;
609
610 regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l);
611
612 spin_lock_irqsave(&info->irq_lock, flags);
613 p = readl(info->base + IRQ_POL + 4 * reg_idx);
614 if ((p ^ l) & (1 << bit_num)) {
615 /*
616 * For the gpios which are used for both-edge irqs, when their
617 * interrupts happen, their input levels are changed,
618 * yet their interrupt polarities are kept in old values, we
619 * should synchronize their interrupt polarities; for example,
620 * at first a gpio's input level is low and its interrupt
621 * polarity control is "Detect rising edge", then the gpio has
622 * a interrupt , its level turns to high, we should change its
623 * polarity control to "Detect falling edge" correspondingly.
624 */
625 p ^= 1 << bit_num;
626 writel(p, info->base + IRQ_POL + 4 * reg_idx);
627 ret = 0;
628 } else {
629 /* Spurious irq */
630 ret = -1;
631 }
632
633 spin_unlock_irqrestore(&info->irq_lock, flags);
634 return ret;
635}
589 636
590static void armada_37xx_irq_handler(struct irq_desc *desc) 637static void armada_37xx_irq_handler(struct irq_desc *desc)
591{ 638{
@@ -609,6 +656,23 @@ static void armada_37xx_irq_handler(struct irq_desc *desc)
609 u32 hwirq = ffs(status) - 1; 656 u32 hwirq = ffs(status) - 1;
610 u32 virq = irq_find_mapping(d, hwirq + 657 u32 virq = irq_find_mapping(d, hwirq +
611 i * GPIO_PER_REG); 658 i * GPIO_PER_REG);
659 u32 t = irq_get_trigger_type(virq);
660
661 if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
662 /* Swap polarity (race with GPIO line) */
663 if (armada_37xx_edge_both_irq_swap_pol(info,
664 hwirq + i * GPIO_PER_REG)) {
665 /*
666 * For spurious irq, which gpio level
667 * is not as expected after incoming
668 * edge, just ack the gpio irq.
669 */
670 writel(1 << hwirq,
671 info->base +
672 IRQ_STATUS + 4 * i);
673 continue;
674 }
675 }
612 676
613 generic_handle_irq(virq); 677 generic_handle_irq(virq);
614 678
diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c
index 8eaa25c3384f..b4f7f8a458ea 100644
--- a/drivers/pinctrl/pinconf-generic.c
+++ b/drivers/pinctrl/pinconf-generic.c
@@ -49,6 +49,7 @@ static const struct pin_config_item conf_items[] = {
49 PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true), 49 PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true),
50 PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false), 50 PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false),
51 PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true), 51 PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true),
52 PCONFDUMP(PIN_CONFIG_SKEW_DELAY, "skew delay", NULL, true),
52}; 53};
53 54
54static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev, 55static void pinconf_generic_dump_one(struct pinctrl_dev *pctldev,
@@ -181,6 +182,7 @@ static const struct pinconf_generic_params dt_params[] = {
181 { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, 182 { "power-source", PIN_CONFIG_POWER_SOURCE, 0 },
182 { "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 }, 183 { "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 },
183 { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, 184 { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
185 { "skew-delay", PIN_CONFIG_SKEW_DELAY, 0 },
184}; 186};
185 187
186/** 188/**
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 8ed2a90a8d44..61d830c2bc17 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -753,7 +753,7 @@ static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
753 return false; 753 return false;
754} 754}
755 755
756int amd_gpio_suspend(struct device *dev) 756static int amd_gpio_suspend(struct device *dev)
757{ 757{
758 struct platform_device *pdev = to_platform_device(dev); 758 struct platform_device *pdev = to_platform_device(dev);
759 struct amd_gpio *gpio_dev = platform_get_drvdata(pdev); 759 struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
@@ -772,7 +772,7 @@ int amd_gpio_suspend(struct device *dev)
772 return 0; 772 return 0;
773} 773}
774 774
775int amd_gpio_resume(struct device *dev) 775static int amd_gpio_resume(struct device *dev)
776{ 776{
777 struct platform_device *pdev = to_platform_device(dev); 777 struct platform_device *pdev = to_platform_device(dev);
778 struct amd_gpio *gpio_dev = platform_get_drvdata(pdev); 778 struct amd_gpio *gpio_dev = platform_get_drvdata(pdev);
diff --git a/drivers/pinctrl/pinctrl-gemini.c b/drivers/pinctrl/pinctrl-gemini.c
index 39e6221e7100..e9b83e291edf 100644
--- a/drivers/pinctrl/pinctrl-gemini.c
+++ b/drivers/pinctrl/pinctrl-gemini.c
@@ -13,6 +13,8 @@
13#include <linux/pinctrl/machine.h> 13#include <linux/pinctrl/machine.h>
14#include <linux/pinctrl/pinctrl.h> 14#include <linux/pinctrl/pinctrl.h>
15#include <linux/pinctrl/pinmux.h> 15#include <linux/pinctrl/pinmux.h>
16#include <linux/pinctrl/pinconf.h>
17#include <linux/pinctrl/pinconf-generic.h>
16#include <linux/platform_device.h> 18#include <linux/platform_device.h>
17#include <linux/slab.h> 19#include <linux/slab.h>
18#include <linux/regmap.h> 20#include <linux/regmap.h>
@@ -22,6 +24,19 @@
22#define DRIVER_NAME "pinctrl-gemini" 24#define DRIVER_NAME "pinctrl-gemini"
23 25
24/** 26/**
27 * struct gemini_pin_conf - information about configuring a pin
28 * @pin: the pin number
29 * @reg: config register
30 * @mask: the bits affecting the configuration of the pin
31 */
32struct gemini_pin_conf {
33 unsigned int pin;
34 u32 reg;
35 u32 mask;
36};
37
38/**
39 * struct gemini_pmx - state holder for the gemini pin controller
25 * @dev: a pointer back to containing device 40 * @dev: a pointer back to containing device
26 * @virtbase: the offset to the controller in virtual memory 41 * @virtbase: the offset to the controller in virtual memory
27 * @map: regmap to access registers 42 * @map: regmap to access registers
@@ -29,6 +44,8 @@
29 * @is_3516: whether the SoC/package is the 3516 variant 44 * @is_3516: whether the SoC/package is the 3516 variant
30 * @flash_pin: whether the flash pin (extended pins for parallel 45 * @flash_pin: whether the flash pin (extended pins for parallel
31 * flash) is set 46 * flash) is set
47 * @confs: pin config information
48 * @nconfs: number of pin config information items
32 */ 49 */
33struct gemini_pmx { 50struct gemini_pmx {
34 struct device *dev; 51 struct device *dev;
@@ -37,6 +54,8 @@ struct gemini_pmx {
37 bool is_3512; 54 bool is_3512;
38 bool is_3516; 55 bool is_3516;
39 bool flash_pin; 56 bool flash_pin;
57 const struct gemini_pin_conf *confs;
58 unsigned int nconfs;
40}; 59};
41 60
42/** 61/**
@@ -57,6 +76,13 @@ struct gemini_pin_group {
57 u32 value; 76 u32 value;
58}; 77};
59 78
79/* Some straight-forward control registers */
80#define GLOBAL_WORD_ID 0x00
81#define GLOBAL_STATUS 0x04
82#define GLOBAL_STATUS_FLPIN BIT(20)
83#define GLOBAL_GMAC_CTRL_SKEW 0x1c
84#define GLOBAL_GMAC0_DATA_SKEW 0x20
85#define GLOBAL_GMAC1_DATA_SKEW 0x24
60/* 86/*
61 * Global Miscellaneous Control Register 87 * Global Miscellaneous Control Register
62 * This register controls all Gemini pad/pin multiplexing 88 * This register controls all Gemini pad/pin multiplexing
@@ -69,10 +95,14 @@ struct gemini_pin_group {
69 * DISABLED again. So you select a flash configuration once, and then 95 * DISABLED again. So you select a flash configuration once, and then
70 * you are stuck with it. 96 * you are stuck with it.
71 */ 97 */
72#define GLOBAL_WORD_ID 0x00
73#define GLOBAL_STATUS 0x04
74#define GLOBAL_STATUS_FLPIN BIT(20)
75#define GLOBAL_MISC_CTRL 0x30 98#define GLOBAL_MISC_CTRL 0x30
99#define GEMINI_GMAC_IOSEL_MASK GENMASK(28, 27)
100/* Not really used */
101#define GEMINI_GMAC_IOSEL_GMAC0_GMII BIT(28)
102/* Activated with GMAC1 */
103#define GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII BIT(27)
104/* This will be the default */
105#define GEMINI_GMAC_IOSEL_GMAC0_RGMII_GMAC1_GPIO2 0
76#define TVC_CLK_PAD_ENABLE BIT(20) 106#define TVC_CLK_PAD_ENABLE BIT(20)
77#define PCI_CLK_PAD_ENABLE BIT(17) 107#define PCI_CLK_PAD_ENABLE BIT(17)
78#define LPC_CLK_PAD_ENABLE BIT(16) 108#define LPC_CLK_PAD_ENABLE BIT(16)
@@ -86,8 +116,8 @@ struct gemini_pin_group {
86#define NAND_PADS_DISABLE BIT(2) 116#define NAND_PADS_DISABLE BIT(2)
87#define PFLASH_PADS_DISABLE BIT(1) 117#define PFLASH_PADS_DISABLE BIT(1)
88#define SFLASH_PADS_DISABLE BIT(0) 118#define SFLASH_PADS_DISABLE BIT(0)
89#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20)) 119#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20) | BIT(27))
90#define PADS_MAXBIT 20 120#define PADS_MAXBIT 27
91 121
92/* Ordered by bit index */ 122/* Ordered by bit index */
93static const char * const gemini_padgroups[] = { 123static const char * const gemini_padgroups[] = {
@@ -106,6 +136,8 @@ static const char * const gemini_padgroups[] = {
106 "PCI CLK", 136 "PCI CLK",
107 NULL, NULL, 137 NULL, NULL,
108 "TVC CLK", 138 "TVC CLK",
139 NULL, NULL, NULL, NULL, NULL,
140 "GMAC1",
109}; 141};
110 142
111static const struct pinctrl_pin_desc gemini_3512_pins[] = { 143static const struct pinctrl_pin_desc gemini_3512_pins[] = {
@@ -493,9 +525,12 @@ static const unsigned int usb_3512_pins[] = {
493}; 525};
494 526
495/* GMII, ethernet pins */ 527/* GMII, ethernet pins */
496static const unsigned int gmii_3512_pins[] = { 528static const unsigned int gmii_gmac0_3512_pins[] = {
497 311, 240, 258, 276, 294, 312, 241, 259, 277, 295, 313, 242, 260, 278, 296, 529 240, 241, 242, 258, 259, 260, 276, 277, 278, 294, 295, 311, 312, 313
498 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281 530};
531
532static const unsigned int gmii_gmac1_3512_pins[] = {
533 243, 244, 261, 262, 279, 280, 281, 296, 297, 298, 299, 315, 316, 317
499}; 534};
500 535
501static const unsigned int pci_3512_pins[] = { 536static const unsigned int pci_3512_pins[] = {
@@ -645,10 +680,10 @@ static const unsigned int gpio1c_3512_pins[] = {
645/* The GPIO1D (28-31) pins overlap with LCD and TVC */ 680/* The GPIO1D (28-31) pins overlap with LCD and TVC */
646static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 }; 681static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 };
647 682
648/* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */ 683/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
649static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 }; 684static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 };
650 685
651/* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */ 686/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
652static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 }; 687static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 };
653 688
654/* The GPIO2C (8-31) pins overlap with PCI */ 689/* The GPIO2C (8-31) pins overlap with PCI */
@@ -715,9 +750,16 @@ static const struct gemini_pin_group gemini_3512_pin_groups[] = {
715 .num_pins = ARRAY_SIZE(usb_3512_pins), 750 .num_pins = ARRAY_SIZE(usb_3512_pins),
716 }, 751 },
717 { 752 {
718 .name = "gmiigrp", 753 .name = "gmii_gmac0_grp",
719 .pins = gmii_3512_pins, 754 .pins = gmii_gmac0_3512_pins,
720 .num_pins = ARRAY_SIZE(gmii_3512_pins), 755 .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins),
756 },
757 {
758 .name = "gmii_gmac1_grp",
759 .pins = gmii_gmac1_3512_pins,
760 .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins),
761 /* Bring out RGMII on the GMAC1 pins */
762 .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
721 }, 763 },
722 { 764 {
723 .name = "pcigrp", 765 .name = "pcigrp",
@@ -931,14 +973,15 @@ static const struct gemini_pin_group gemini_3512_pin_groups[] = {
931 .name = "gpio2agrp", 973 .name = "gpio2agrp",
932 .pins = gpio2a_3512_pins, 974 .pins = gpio2a_3512_pins,
933 .num_pins = ARRAY_SIZE(gpio2a_3512_pins), 975 .num_pins = ARRAY_SIZE(gpio2a_3512_pins),
934 /* Conflict with GMII and extended parallel flash */ 976 .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
977 /* Conflict with GMII GMAC1 and extended parallel flash */
935 }, 978 },
936 { 979 {
937 .name = "gpio2bgrp", 980 .name = "gpio2bgrp",
938 .pins = gpio2b_3512_pins, 981 .pins = gpio2b_3512_pins,
939 .num_pins = ARRAY_SIZE(gpio2b_3512_pins), 982 .num_pins = ARRAY_SIZE(gpio2b_3512_pins),
940 /* Conflict with GMII, extended parallel flash and LCD */ 983 /* Conflict with GMII GMAC1, extended parallel flash and LCD */
941 .mask = LCD_PADS_ENABLE, 984 .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
942 }, 985 },
943 { 986 {
944 .name = "gpio2cgrp", 987 .name = "gpio2cgrp",
@@ -1418,9 +1461,12 @@ static const unsigned int usb_3516_pins[] = {
1418}; 1461};
1419 1462
1420/* GMII, ethernet pins */ 1463/* GMII, ethernet pins */
1421static const unsigned int gmii_3516_pins[] = { 1464static const unsigned int gmii_gmac0_3516_pins[] = {
1422 306, 307, 308, 309, 310, 325, 326, 327, 328, 329, 330, 345, 346, 347, 1465 306, 307, 325, 326, 327, 328, 345, 346, 347, 348, 367, 368, 386, 387
1423 348, 349, 350, 351, 367, 368, 369, 370, 371, 386, 387, 389, 390, 391 1466};
1467
1468static const unsigned int gmii_gmac1_3516_pins[] = {
1469 308, 309, 310, 329, 330, 349, 350, 351, 369, 370, 371, 389, 390, 391
1424}; 1470};
1425 1471
1426static const unsigned int pci_3516_pins[] = { 1472static const unsigned int pci_3516_pins[] = {
@@ -1562,10 +1608,10 @@ static const unsigned int gpio1c_3516_pins[] = {
1562/* The GPIO1D (28-31) pins overlap with TVC */ 1608/* The GPIO1D (28-31) pins overlap with TVC */
1563static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 }; 1609static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 };
1564 1610
1565/* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */ 1611/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
1566static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 }; 1612static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 };
1567 1613
1568/* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */ 1614/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
1569static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 }; 1615static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 };
1570 1616
1571/* The GPIO2C (8-31) pins overlap with PCI */ 1617/* The GPIO2C (8-31) pins overlap with PCI */
@@ -1637,9 +1683,16 @@ static const struct gemini_pin_group gemini_3516_pin_groups[] = {
1637 .num_pins = ARRAY_SIZE(usb_3516_pins), 1683 .num_pins = ARRAY_SIZE(usb_3516_pins),
1638 }, 1684 },
1639 { 1685 {
1640 .name = "gmiigrp", 1686 .name = "gmii_gmac0_grp",
1641 .pins = gmii_3516_pins, 1687 .pins = gmii_gmac0_3516_pins,
1642 .num_pins = ARRAY_SIZE(gmii_3516_pins), 1688 .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins),
1689 },
1690 {
1691 .name = "gmii_gmac1_grp",
1692 .pins = gmii_gmac1_3516_pins,
1693 .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins),
1694 /* Bring out RGMII on the GMAC1 pins */
1695 .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
1643 }, 1696 },
1644 { 1697 {
1645 .name = "pcigrp", 1698 .name = "pcigrp",
@@ -1838,14 +1891,15 @@ static const struct gemini_pin_group gemini_3516_pin_groups[] = {
1838 .name = "gpio2agrp", 1891 .name = "gpio2agrp",
1839 .pins = gpio2a_3516_pins, 1892 .pins = gpio2a_3516_pins,
1840 .num_pins = ARRAY_SIZE(gpio2a_3516_pins), 1893 .num_pins = ARRAY_SIZE(gpio2a_3516_pins),
1841 /* Conflict with GMII and extended parallel flash */ 1894 .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
1895 /* Conflict with GMII GMAC1 and extended parallel flash */
1842 }, 1896 },
1843 { 1897 {
1844 .name = "gpio2bgrp", 1898 .name = "gpio2bgrp",
1845 .pins = gpio2b_3516_pins, 1899 .pins = gpio2b_3516_pins,
1846 .num_pins = ARRAY_SIZE(gpio2b_3516_pins), 1900 .num_pins = ARRAY_SIZE(gpio2b_3516_pins),
1847 /* Conflict with GMII, extended parallel flash and LCD */ 1901 /* Conflict with GMII GMAC1, extended parallel flash and LCD */
1848 .mask = LCD_PADS_ENABLE, 1902 .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
1849 }, 1903 },
1850 { 1904 {
1851 .name = "gpio2cgrp", 1905 .name = "gpio2cgrp",
@@ -1918,73 +1972,13 @@ static void gemini_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1918 seq_printf(s, " " DRIVER_NAME); 1972 seq_printf(s, " " DRIVER_NAME);
1919} 1973}
1920 1974
1921static int gemini_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1922 struct device_node *np,
1923 struct pinctrl_map **map,
1924 unsigned int *reserved_maps,
1925 unsigned int *num_maps)
1926{
1927 int ret;
1928 const char *function = NULL;
1929 const char *group;
1930 struct property *prop;
1931
1932 ret = of_property_read_string(np, "function", &function);
1933 if (ret < 0)
1934 return ret;
1935
1936 ret = of_property_count_strings(np, "groups");
1937 if (ret < 0)
1938 return ret;
1939
1940 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
1941 num_maps, ret);
1942 if (ret < 0)
1943 return ret;
1944
1945 of_property_for_each_string(np, "groups", prop, group) {
1946 ret = pinctrl_utils_add_map_mux(pctldev, map, reserved_maps,
1947 num_maps, group, function);
1948 if (ret < 0)
1949 return ret;
1950 pr_debug("ADDED FUNCTION %s <-> GROUP %s\n",
1951 function, group);
1952 }
1953
1954 return 0;
1955}
1956
1957static int gemini_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1958 struct device_node *np_config,
1959 struct pinctrl_map **map,
1960 unsigned int *num_maps)
1961{
1962 unsigned int reserved_maps = 0;
1963 struct device_node *np;
1964 int ret;
1965
1966 *map = NULL;
1967 *num_maps = 0;
1968
1969 for_each_child_of_node(np_config, np) {
1970 ret = gemini_pinctrl_dt_subnode_to_map(pctldev, np, map,
1971 &reserved_maps, num_maps);
1972 if (ret < 0) {
1973 pinctrl_utils_free_map(pctldev, *map, *num_maps);
1974 return ret;
1975 }
1976 }
1977
1978 return 0;
1979};
1980
1981static const struct pinctrl_ops gemini_pctrl_ops = { 1975static const struct pinctrl_ops gemini_pctrl_ops = {
1982 .get_groups_count = gemini_get_groups_count, 1976 .get_groups_count = gemini_get_groups_count,
1983 .get_group_name = gemini_get_group_name, 1977 .get_group_name = gemini_get_group_name,
1984 .get_group_pins = gemini_get_group_pins, 1978 .get_group_pins = gemini_get_group_pins,
1985 .pin_dbg_show = gemini_pin_dbg_show, 1979 .pin_dbg_show = gemini_pin_dbg_show,
1986 .dt_node_to_map = gemini_pinctrl_dt_node_to_map, 1980 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
1987 .dt_free_map = pinctrl_utils_free_map, 1981 .dt_free_map = pinconf_generic_dt_free_map,
1988}; 1982};
1989 1983
1990/** 1984/**
@@ -2008,7 +2002,7 @@ static const char * const icegrps[] = { "icegrp" };
2008static const char * const idegrps[] = { "idegrp" }; 2002static const char * const idegrps[] = { "idegrp" };
2009static const char * const satagrps[] = { "satagrp" }; 2003static const char * const satagrps[] = { "satagrp" };
2010static const char * const usbgrps[] = { "usbgrp" }; 2004static const char * const usbgrps[] = { "usbgrp" };
2011static const char * const gmiigrps[] = { "gmiigrp" }; 2005static const char * const gmiigrps[] = { "gmii_gmac0_grp", "gmii_gmac1_grp" };
2012static const char * const pcigrps[] = { "pcigrp" }; 2006static const char * const pcigrps[] = { "pcigrp" };
2013static const char * const lpcgrps[] = { "lpcgrp" }; 2007static const char * const lpcgrps[] = { "lpcgrp" };
2014static const char * const lcdgrps[] = { "lcdgrp" }; 2008static const char * const lcdgrps[] = { "lcdgrp" };
@@ -2074,6 +2068,16 @@ static const struct gemini_pmx_func gemini_pmx_functions[] = {
2074 .num_groups = ARRAY_SIZE(satagrps), 2068 .num_groups = ARRAY_SIZE(satagrps),
2075 }, 2069 },
2076 { 2070 {
2071 .name = "usb",
2072 .groups = usbgrps,
2073 .num_groups = ARRAY_SIZE(usbgrps),
2074 },
2075 {
2076 .name = "gmii",
2077 .groups = gmiigrps,
2078 .num_groups = ARRAY_SIZE(gmiigrps),
2079 },
2080 {
2077 .name = "pci", 2081 .name = "pci",
2078 .groups = pcigrps, 2082 .groups = pcigrps,
2079 .num_groups = ARRAY_SIZE(pcigrps), 2083 .num_groups = ARRAY_SIZE(pcigrps),
@@ -2251,10 +2255,155 @@ static const struct pinmux_ops gemini_pmx_ops = {
2251 .set_mux = gemini_pmx_set_mux, 2255 .set_mux = gemini_pmx_set_mux,
2252}; 2256};
2253 2257
2258#define GEMINI_CFGPIN(_n, _r, _lb, _hb) { \
2259 .pin = _n, \
2260 .reg = _r, \
2261 .mask = GENMASK(_hb, _lb) \
2262}
2263
2264static const struct gemini_pin_conf gemini_confs_3512[] = {
2265 GEMINI_CFGPIN(259, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */
2266 GEMINI_CFGPIN(277, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */
2267 GEMINI_CFGPIN(241, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */
2268 GEMINI_CFGPIN(312, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */
2269 GEMINI_CFGPIN(298, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */
2270 GEMINI_CFGPIN(280, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */
2271 GEMINI_CFGPIN(316, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */
2272 GEMINI_CFGPIN(243, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */
2273 GEMINI_CFGPIN(295, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */
2274 GEMINI_CFGPIN(313, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */
2275 GEMINI_CFGPIN(242, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */
2276 GEMINI_CFGPIN(260, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */
2277 GEMINI_CFGPIN(294, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */
2278 GEMINI_CFGPIN(276, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */
2279 GEMINI_CFGPIN(258, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */
2280 GEMINI_CFGPIN(240, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */
2281 GEMINI_CFGPIN(262, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */
2282 GEMINI_CFGPIN(244, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */
2283 GEMINI_CFGPIN(317, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */
2284 GEMINI_CFGPIN(299, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */
2285 GEMINI_CFGPIN(261, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */
2286 GEMINI_CFGPIN(279, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */
2287 GEMINI_CFGPIN(297, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */
2288 GEMINI_CFGPIN(315, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */
2289};
2290
2291static const struct gemini_pin_conf gemini_confs_3516[] = {
2292 GEMINI_CFGPIN(347, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */
2293 GEMINI_CFGPIN(386, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */
2294 GEMINI_CFGPIN(307, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */
2295 GEMINI_CFGPIN(327, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */
2296 GEMINI_CFGPIN(309, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */
2297 GEMINI_CFGPIN(390, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */
2298 GEMINI_CFGPIN(370, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */
2299 GEMINI_CFGPIN(350, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */
2300 GEMINI_CFGPIN(367, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */
2301 GEMINI_CFGPIN(348, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */
2302 GEMINI_CFGPIN(387, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */
2303 GEMINI_CFGPIN(328, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */
2304 GEMINI_CFGPIN(306, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */
2305 GEMINI_CFGPIN(325, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */
2306 GEMINI_CFGPIN(346, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */
2307 GEMINI_CFGPIN(326, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */
2308 GEMINI_CFGPIN(391, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */
2309 GEMINI_CFGPIN(351, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */
2310 GEMINI_CFGPIN(310, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */
2311 GEMINI_CFGPIN(371, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */
2312 GEMINI_CFGPIN(329, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */
2313 GEMINI_CFGPIN(389, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */
2314 GEMINI_CFGPIN(369, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */
2315 GEMINI_CFGPIN(308, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */
2316};
2317
2318static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx,
2319 unsigned int pin)
2320{
2321 const struct gemini_pin_conf *retconf;
2322 int i;
2323
2324 for (i = 0; i < pmx->nconfs; i++) {
2325 retconf = &gemini_confs_3516[i];
2326 if (retconf->pin == pin)
2327 return retconf;
2328 }
2329 return NULL;
2330}
2331
2332static int gemini_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2333 unsigned long *config)
2334{
2335 struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
2336 enum pin_config_param param = pinconf_to_config_param(*config);
2337 const struct gemini_pin_conf *conf;
2338 u32 val;
2339
2340 switch (param) {
2341 case PIN_CONFIG_SKEW_DELAY:
2342 conf = gemini_get_pin_conf(pmx, pin);
2343 if (!conf)
2344 return -ENOTSUPP;
2345 regmap_read(pmx->map, conf->reg, &val);
2346 val &= conf->mask;
2347 val >>= (ffs(conf->mask) - 1);
2348 *config = pinconf_to_config_packed(PIN_CONFIG_SKEW_DELAY, val);
2349 break;
2350 default:
2351 return -ENOTSUPP;
2352 }
2353
2354 return 0;
2355}
2356
2357static int gemini_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
2358 unsigned long *configs, unsigned int num_configs)
2359{
2360 struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
2361 const struct gemini_pin_conf *conf;
2362 enum pin_config_param param;
2363 u32 arg;
2364 int ret = 0;
2365 int i;
2366
2367 for (i = 0; i < num_configs; i++) {
2368 param = pinconf_to_config_param(configs[i]);
2369 arg = pinconf_to_config_argument(configs[i]);
2370
2371 switch (param) {
2372 case PIN_CONFIG_SKEW_DELAY:
2373 if (arg > 0xf)
2374 return -EINVAL;
2375 conf = gemini_get_pin_conf(pmx, pin);
2376 if (!conf) {
2377 dev_err(pmx->dev,
2378 "invalid pin for skew delay %d\n", pin);
2379 return -ENOTSUPP;
2380 }
2381 arg <<= (ffs(conf->mask) - 1);
2382 dev_dbg(pmx->dev,
2383 "set pin %d to skew delay mask %08x, val %08x\n",
2384 pin, conf->mask, arg);
2385 regmap_update_bits(pmx->map, conf->reg, conf->mask, arg);
2386 break;
2387 default:
2388 dev_err(pmx->dev, "Invalid config param %04x\n", param);
2389 return -ENOTSUPP;
2390 }
2391 }
2392
2393 return ret;
2394}
2395
2396static const struct pinconf_ops gemini_pinconf_ops = {
2397 .pin_config_get = gemini_pinconf_get,
2398 .pin_config_set = gemini_pinconf_set,
2399 .is_generic = true,
2400};
2401
2254static struct pinctrl_desc gemini_pmx_desc = { 2402static struct pinctrl_desc gemini_pmx_desc = {
2255 .name = DRIVER_NAME, 2403 .name = DRIVER_NAME,
2256 .pctlops = &gemini_pctrl_ops, 2404 .pctlops = &gemini_pctrl_ops,
2257 .pmxops = &gemini_pmx_ops, 2405 .pmxops = &gemini_pmx_ops,
2406 .confops = &gemini_pinconf_ops,
2258 .owner = THIS_MODULE, 2407 .owner = THIS_MODULE,
2259}; 2408};
2260 2409
@@ -2297,11 +2446,15 @@ static int gemini_pmx_probe(struct platform_device *pdev)
2297 val &= 0xffff; 2446 val &= 0xffff;
2298 if (val == 0x3512) { 2447 if (val == 0x3512) {
2299 pmx->is_3512 = true; 2448 pmx->is_3512 = true;
2449 pmx->confs = gemini_confs_3512;
2450 pmx->nconfs = ARRAY_SIZE(gemini_confs_3512);
2300 gemini_pmx_desc.pins = gemini_3512_pins; 2451 gemini_pmx_desc.pins = gemini_3512_pins;
2301 gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3512_pins); 2452 gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3512_pins);
2302 dev_info(dev, "detected 3512 chip variant\n"); 2453 dev_info(dev, "detected 3512 chip variant\n");
2303 } else if (val == 0x3516) { 2454 } else if (val == 0x3516) {
2304 pmx->is_3516 = true; 2455 pmx->is_3516 = true;
2456 pmx->confs = gemini_confs_3516;
2457 pmx->nconfs = ARRAY_SIZE(gemini_confs_3516);
2305 gemini_pmx_desc.pins = gemini_3516_pins; 2458 gemini_pmx_desc.pins = gemini_3516_pins;
2306 gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3516_pins); 2459 gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3516_pins);
2307 dev_info(dev, "detected 3516 chip variant\n"); 2460 dev_info(dev, "detected 3516 chip variant\n");
diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c
index d84761822243..372ddf386bdb 100644
--- a/drivers/pinctrl/pinctrl-ingenic.c
+++ b/drivers/pinctrl/pinctrl-ingenic.c
@@ -717,7 +717,7 @@ static const struct of_device_id ingenic_pinctrl_of_match[] = {
717 {}, 717 {},
718}; 718};
719 719
720int ingenic_pinctrl_probe(struct platform_device *pdev) 720static int ingenic_pinctrl_probe(struct platform_device *pdev)
721{ 721{
722 struct device *dev = &pdev->dev; 722 struct device *dev = &pdev->dev;
723 struct ingenic_pinctrl *jzpc; 723 struct ingenic_pinctrl *jzpc;
diff --git a/drivers/pinctrl/pinctrl-max77620.c b/drivers/pinctrl/pinctrl-max77620.c
index b8d2180a2bea..a7f37063518e 100644
--- a/drivers/pinctrl/pinctrl-max77620.c
+++ b/drivers/pinctrl/pinctrl-max77620.c
@@ -420,11 +420,9 @@ static int max77620_pinconf_set(struct pinctrl_dev *pctldev,
420 MAX77620_REG_GPIO0 + pin, 420 MAX77620_REG_GPIO0 + pin,
421 MAX77620_CNFG_GPIO_DRV_MASK, 421 MAX77620_CNFG_GPIO_DRV_MASK,
422 val); 422 val);
423 if (ret < 0) { 423 if (ret)
424 dev_err(dev, "Reg 0x%02x update failed %d\n", 424 goto report_update_failure;
425 MAX77620_REG_GPIO0 + pin, ret); 425
426 return ret;
427 }
428 mpci->pin_info[pin].drv_type = val ? 426 mpci->pin_info[pin].drv_type = val ?
429 MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV; 427 MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
430 break; 428 break;
@@ -435,11 +433,9 @@ static int max77620_pinconf_set(struct pinctrl_dev *pctldev,
435 MAX77620_REG_GPIO0 + pin, 433 MAX77620_REG_GPIO0 + pin,
436 MAX77620_CNFG_GPIO_DRV_MASK, 434 MAX77620_CNFG_GPIO_DRV_MASK,
437 val); 435 val);
438 if (ret < 0) { 436 if (ret)
439 dev_err(dev, "Reg 0x%02x update failed %d\n", 437 goto report_update_failure;
440 MAX77620_REG_GPIO0 + pin, ret); 438
441 return ret;
442 }
443 mpci->pin_info[pin].drv_type = val ? 439 mpci->pin_info[pin].drv_type = val ?
444 MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV; 440 MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV;
445 break; 441 break;
@@ -536,6 +532,11 @@ static int max77620_pinconf_set(struct pinctrl_dev *pctldev,
536 } 532 }
537 533
538 return 0; 534 return 0;
535
536report_update_failure:
537 dev_err(dev, "Reg 0x%02x update failed %d\n",
538 MAX77620_REG_GPIO0 + pin, ret);
539 return ret;
539} 540}
540 541
541static const struct pinconf_ops max77620_pinconf_ops = { 542static const struct pinconf_ops max77620_pinconf_ops = {
diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c
index 59c899c205fb..4a6ea159c65d 100644
--- a/drivers/pinctrl/pinctrl-mcp23s08.c
+++ b/drivers/pinctrl/pinctrl-mcp23s08.c
@@ -25,6 +25,7 @@
25#define MCP_TYPE_008 2 25#define MCP_TYPE_008 2
26#define MCP_TYPE_017 3 26#define MCP_TYPE_017 3
27#define MCP_TYPE_S18 4 27#define MCP_TYPE_S18 4
28#define MCP_TYPE_018 5
28 29
29#define MCP_MAX_DEV_PER_CS 8 30#define MCP_MAX_DEV_PER_CS 8
30 31
@@ -278,8 +279,7 @@ static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
278{ 279{
279 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); 280 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
280 enum pin_config_param param; 281 enum pin_config_param param;
281 u32 arg, mask; 282 u32 arg;
282 u16 val;
283 int ret = 0; 283 int ret = 0;
284 int i; 284 int i;
285 285
@@ -289,8 +289,6 @@ static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
289 289
290 switch (param) { 290 switch (param) {
291 case PIN_CONFIG_BIAS_PULL_UP: 291 case PIN_CONFIG_BIAS_PULL_UP:
292 val = arg ? 0xFFFF : 0x0000;
293 mask = BIT(pin);
294 ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg); 292 ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg);
295 break; 293 break;
296 default: 294 default:
@@ -837,6 +835,13 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
837 mcp->chip.ngpio = 16; 835 mcp->chip.ngpio = 16;
838 mcp->chip.label = "mcp23017"; 836 mcp->chip.label = "mcp23017";
839 break; 837 break;
838
839 case MCP_TYPE_018:
840 mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap);
841 mcp->reg_shift = 1;
842 mcp->chip.ngpio = 16;
843 mcp->chip.label = "mcp23018";
844 break;
840#endif /* CONFIG_I2C */ 845#endif /* CONFIG_I2C */
841 846
842 default: 847 default:
@@ -883,7 +888,7 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
883 if (mirror) 888 if (mirror)
884 status |= IOCON_MIRROR | (IOCON_MIRROR << 8); 889 status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
885 890
886 if (type == MCP_TYPE_S18) 891 if (type == MCP_TYPE_S18 || type == MCP_TYPE_018)
887 status |= IOCON_INTCC | (IOCON_INTCC << 8); 892 status |= IOCON_INTCC | (IOCON_INTCC << 8);
888 893
889 ret = mcp_write(mcp, MCP_IOCON, status); 894 ret = mcp_write(mcp, MCP_IOCON, status);
@@ -964,6 +969,10 @@ static const struct of_device_id mcp23s08_i2c_of_match[] = {
964 .compatible = "microchip,mcp23017", 969 .compatible = "microchip,mcp23017",
965 .data = (void *) MCP_TYPE_017, 970 .data = (void *) MCP_TYPE_017,
966 }, 971 },
972 {
973 .compatible = "microchip,mcp23018",
974 .data = (void *) MCP_TYPE_018,
975 },
967/* NOTE: The use of the mcp prefix is deprecated and will be removed. */ 976/* NOTE: The use of the mcp prefix is deprecated and will be removed. */
968 { 977 {
969 .compatible = "mcp,mcp23008", 978 .compatible = "mcp,mcp23008",
@@ -1013,6 +1022,7 @@ static int mcp230xx_probe(struct i2c_client *client,
1013static const struct i2c_device_id mcp230xx_id[] = { 1022static const struct i2c_device_id mcp230xx_id[] = {
1014 { "mcp23008", MCP_TYPE_008 }, 1023 { "mcp23008", MCP_TYPE_008 },
1015 { "mcp23017", MCP_TYPE_017 }, 1024 { "mcp23017", MCP_TYPE_017 },
1025 { "mcp23018", MCP_TYPE_018 },
1016 { }, 1026 { },
1017}; 1027};
1018MODULE_DEVICE_TABLE(i2c, mcp230xx_id); 1028MODULE_DEVICE_TABLE(i2c, mcp230xx_id);
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index b5cb7858ffdc..2ba17548ad5b 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -884,6 +884,24 @@ static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
884 }, 884 },
885}; 885};
886 886
887static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
888 {
889 /* edphdmi_cecinoutt1 */
890 .bank_num = 7,
891 .pin = 16,
892 .func = 2,
893 .route_offset = 0x264,
894 .route_val = BIT(16 + 12) | BIT(12),
895 }, {
896 /* edphdmi_cecinout */
897 .bank_num = 7,
898 .pin = 23,
899 .func = 4,
900 .route_offset = 0x264,
901 .route_val = BIT(16 + 12),
902 },
903};
904
887static struct rockchip_mux_route_data rk3328_mux_route_data[] = { 905static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
888 { 906 {
889 /* uart2dbg_rxm0 */ 907 /* uart2dbg_rxm0 */
@@ -900,12 +918,19 @@ static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
900 .route_offset = 0x50, 918 .route_offset = 0x50,
901 .route_val = BIT(16) | BIT(16 + 1) | BIT(0), 919 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
902 }, { 920 }, {
903 /* gmac-m1-optimized_rxd0 */ 921 /* gmac-m1_rxd0 */
904 .bank_num = 1, 922 .bank_num = 1,
905 .pin = 11, 923 .pin = 11,
906 .func = 2, 924 .func = 2,
907 .route_offset = 0x50, 925 .route_offset = 0x50,
908 .route_val = BIT(16 + 2) | BIT(16 + 10) | BIT(2) | BIT(10), 926 .route_val = BIT(16 + 2) | BIT(2),
927 }, {
928 /* gmac-m1-optimized_rxd3 */
929 .bank_num = 1,
930 .pin = 14,
931 .func = 2,
932 .route_offset = 0x50,
933 .route_val = BIT(16 + 10) | BIT(10),
909 }, { 934 }, {
910 /* pdm_sdi0m0 */ 935 /* pdm_sdi0m0 */
911 .bank_num = 2, 936 .bank_num = 2,
@@ -3391,6 +3416,8 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3391 .type = RK3288, 3416 .type = RK3288,
3392 .grf_mux_offset = 0x0, 3417 .grf_mux_offset = 0x0,
3393 .pmu_mux_offset = 0x84, 3418 .pmu_mux_offset = 0x84,
3419 .iomux_routes = rk3288_mux_route_data,
3420 .niomux_routes = ARRAY_SIZE(rk3288_mux_route_data),
3394 .pull_calc_reg = rk3288_calc_pull_reg_and_bit, 3421 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
3395 .drv_calc_reg = rk3288_calc_drv_reg_and_bit, 3422 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
3396}; 3423};
@@ -3456,8 +3483,8 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = {
3456 DRV_TYPE_IO_1V8_ONLY, 3483 DRV_TYPE_IO_1V8_ONLY,
3457 DRV_TYPE_IO_DEFAULT, 3484 DRV_TYPE_IO_DEFAULT,
3458 DRV_TYPE_IO_DEFAULT, 3485 DRV_TYPE_IO_DEFAULT,
3459 0x0, 3486 0x80,
3460 0x8, 3487 0x88,
3461 -1, 3488 -1,
3462 -1, 3489 -1,
3463 PULL_TYPE_IO_1V8_ONLY, 3490 PULL_TYPE_IO_1V8_ONLY,
@@ -3473,10 +3500,10 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = {
3473 DRV_TYPE_IO_1V8_OR_3V0, 3500 DRV_TYPE_IO_1V8_OR_3V0,
3474 DRV_TYPE_IO_1V8_OR_3V0, 3501 DRV_TYPE_IO_1V8_OR_3V0,
3475 DRV_TYPE_IO_1V8_OR_3V0, 3502 DRV_TYPE_IO_1V8_OR_3V0,
3476 0x20, 3503 0xa0,
3477 0x28, 3504 0xa8,
3478 0x30, 3505 0xb0,
3479 0x38 3506 0xb8
3480 ), 3507 ),
3481 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0, 3508 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3482 DRV_TYPE_IO_1V8_OR_3V0, 3509 DRV_TYPE_IO_1V8_OR_3V0,
diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/pinctrl-rza1.c
index 04d058706b80..717c0f4449a0 100644
--- a/drivers/pinctrl/pinctrl-rza1.c
+++ b/drivers/pinctrl/pinctrl-rza1.c
@@ -303,6 +303,134 @@ static const struct rza1_pinmux_conf rza1h_pmx_conf = {
303}; 303};
304 304
305/* ---------------------------------------------------------------------------- 305/* ----------------------------------------------------------------------------
306 * RZ/A1L (r7s72102) pinmux flags
307 */
308
309static const struct rza1_bidir_pin rza1l_bidir_pins_p1[] = {
310 { .pin = 0, .func = 1 },
311 { .pin = 1, .func = 1 },
312 { .pin = 2, .func = 1 },
313 { .pin = 3, .func = 1 },
314 { .pin = 4, .func = 1 },
315 { .pin = 5, .func = 1 },
316 { .pin = 6, .func = 1 },
317 { .pin = 7, .func = 1 },
318};
319
320static const struct rza1_bidir_pin rza1l_bidir_pins_p3[] = {
321 { .pin = 0, .func = 2 },
322 { .pin = 1, .func = 2 },
323 { .pin = 2, .func = 2 },
324 { .pin = 4, .func = 2 },
325 { .pin = 5, .func = 2 },
326 { .pin = 10, .func = 2 },
327 { .pin = 11, .func = 2 },
328 { .pin = 12, .func = 2 },
329 { .pin = 13, .func = 2 },
330};
331
332static const struct rza1_bidir_pin rza1l_bidir_pins_p4[] = {
333 { .pin = 1, .func = 4 },
334 { .pin = 2, .func = 2 },
335 { .pin = 3, .func = 2 },
336 { .pin = 6, .func = 2 },
337 { .pin = 7, .func = 2 },
338};
339
340static const struct rza1_bidir_pin rza1l_bidir_pins_p5[] = {
341 { .pin = 0, .func = 1 },
342 { .pin = 1, .func = 1 },
343 { .pin = 2, .func = 1 },
344 { .pin = 3, .func = 1 },
345 { .pin = 4, .func = 1 },
346 { .pin = 5, .func = 1 },
347 { .pin = 6, .func = 1 },
348 { .pin = 7, .func = 1 },
349 { .pin = 8, .func = 1 },
350 { .pin = 9, .func = 1 },
351 { .pin = 10, .func = 1 },
352 { .pin = 11, .func = 1 },
353 { .pin = 12, .func = 1 },
354 { .pin = 13, .func = 1 },
355 { .pin = 14, .func = 1 },
356 { .pin = 15, .func = 1 },
357 { .pin = 0, .func = 2 },
358 { .pin = 1, .func = 2 },
359 { .pin = 2, .func = 2 },
360 { .pin = 3, .func = 2 },
361};
362
363static const struct rza1_bidir_pin rza1l_bidir_pins_p6[] = {
364 { .pin = 0, .func = 1 },
365 { .pin = 1, .func = 1 },
366 { .pin = 2, .func = 1 },
367 { .pin = 3, .func = 1 },
368 { .pin = 4, .func = 1 },
369 { .pin = 5, .func = 1 },
370 { .pin = 6, .func = 1 },
371 { .pin = 7, .func = 1 },
372 { .pin = 8, .func = 1 },
373 { .pin = 9, .func = 1 },
374 { .pin = 10, .func = 1 },
375 { .pin = 11, .func = 1 },
376 { .pin = 12, .func = 1 },
377 { .pin = 13, .func = 1 },
378 { .pin = 14, .func = 1 },
379 { .pin = 15, .func = 1 },
380};
381
382static const struct rza1_bidir_pin rza1l_bidir_pins_p7[] = {
383 { .pin = 2, .func = 2 },
384 { .pin = 3, .func = 2 },
385 { .pin = 5, .func = 2 },
386 { .pin = 6, .func = 2 },
387 { .pin = 7, .func = 2 },
388 { .pin = 2, .func = 3 },
389 { .pin = 3, .func = 3 },
390 { .pin = 5, .func = 3 },
391 { .pin = 6, .func = 3 },
392 { .pin = 7, .func = 3 },
393};
394
395static const struct rza1_bidir_pin rza1l_bidir_pins_p9[] = {
396 { .pin = 1, .func = 2 },
397 { .pin = 0, .func = 3 },
398 { .pin = 1, .func = 3 },
399 { .pin = 3, .func = 3 },
400 { .pin = 4, .func = 3 },
401 { .pin = 5, .func = 3 },
402};
403
404static const struct rza1_swio_pin rza1l_swio_pins[] = {
405 { .port = 2, .pin = 8, .func = 2, .input = 0 },
406 { .port = 5, .pin = 6, .func = 3, .input = 0 },
407 { .port = 6, .pin = 6, .func = 3, .input = 0 },
408 { .port = 6, .pin = 10, .func = 3, .input = 0 },
409 { .port = 7, .pin = 10, .func = 2, .input = 0 },
410 { .port = 8, .pin = 2, .func = 3, .input = 0 },
411};
412
413static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = {
414 [1] = { ARRAY_SIZE(rza1l_bidir_pins_p1), rza1l_bidir_pins_p1 },
415 [3] = { ARRAY_SIZE(rza1l_bidir_pins_p3), rza1l_bidir_pins_p3 },
416 [4] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p4 },
417 [5] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p5 },
418 [6] = { ARRAY_SIZE(rza1l_bidir_pins_p6), rza1l_bidir_pins_p6 },
419 [7] = { ARRAY_SIZE(rza1l_bidir_pins_p7), rza1l_bidir_pins_p7 },
420 [9] = { ARRAY_SIZE(rza1l_bidir_pins_p9), rza1l_bidir_pins_p9 },
421};
422
423static const struct rza1_swio_entry rza1l_swio_entries[] = {
424 [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins },
425};
426
427/* RZ/A1L (r7s72102x) pinmux flags table */
428static const struct rza1_pinmux_conf rza1l_pmx_conf = {
429 .bidir_entries = rza1l_bidir_entries,
430 .swio_entries = rza1l_swio_entries,
431};
432
433/* ----------------------------------------------------------------------------
306 * RZ/A1 types 434 * RZ/A1 types
307 */ 435 */
308/** 436/**
@@ -1283,9 +1411,15 @@ static int rza1_pinctrl_probe(struct platform_device *pdev)
1283 1411
1284static const struct of_device_id rza1_pinctrl_of_match[] = { 1412static const struct of_device_id rza1_pinctrl_of_match[] = {
1285 { 1413 {
1414 /* RZ/A1H, RZ/A1M */
1286 .compatible = "renesas,r7s72100-ports", 1415 .compatible = "renesas,r7s72100-ports",
1287 .data = &rza1h_pmx_conf, 1416 .data = &rza1h_pmx_conf,
1288 }, 1417 },
1418 {
1419 /* RZ/A1L */
1420 .compatible = "renesas,r7s72102-ports",
1421 .data = &rza1l_pmx_conf,
1422 },
1289 { } 1423 { }
1290}; 1424};
1291 1425
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index b8b3d932cd73..e6cd8de793e2 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -873,13 +873,13 @@ static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
873 int i = 0, nconfs = 0; 873 int i = 0, nconfs = 0;
874 unsigned long *settings = NULL, *s = NULL; 874 unsigned long *settings = NULL, *s = NULL;
875 struct pcs_conf_vals *conf = NULL; 875 struct pcs_conf_vals *conf = NULL;
876 struct pcs_conf_type prop2[] = { 876 static const struct pcs_conf_type prop2[] = {
877 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, 877 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
878 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, 878 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
879 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, 879 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
880 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, }, 880 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
881 }; 881 };
882 struct pcs_conf_type prop4[] = { 882 static const struct pcs_conf_type prop4[] = {
883 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, 883 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
884 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, }, 884 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
885 { "pinctrl-single,input-schmitt-enable", 885 { "pinctrl-single,input-schmitt-enable",
diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c
index 7db4f6a6eb17..fb242c542dc9 100644
--- a/drivers/pinctrl/pinctrl-sx150x.c
+++ b/drivers/pinctrl/pinctrl-sx150x.c
@@ -1087,7 +1087,7 @@ static bool sx150x_reg_volatile(struct device *dev, unsigned int reg)
1087 return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data; 1087 return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data;
1088} 1088}
1089 1089
1090const struct regmap_config sx150x_regmap_config = { 1090static const struct regmap_config sx150x_regmap_config = {
1091 .reg_bits = 8, 1091 .reg_bits = 8,
1092 .val_bits = 32, 1092 .val_bits = 32,
1093 1093
diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
index c2c0bab04257..3e66e0d10010 100644
--- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
@@ -453,6 +453,7 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
453 453
454 pad = pctldev->desc->pins[pin].drv_data; 454 pad = pctldev->desc->pins[pin].drv_data;
455 455
456 pad->is_enabled = true;
456 for (i = 0; i < nconfs; i++) { 457 for (i = 0; i < nconfs; i++) {
457 param = pinconf_to_config_param(configs[i]); 458 param = pinconf_to_config_param(configs[i]);
458 arg = pinconf_to_config_argument(configs[i]); 459 arg = pinconf_to_config_argument(configs[i]);
@@ -600,6 +601,10 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
600 return ret; 601 return ret;
601 } 602 }
602 603
604 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
605
606 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
607
603 return ret; 608 return ret;
604} 609}
605 610
@@ -1032,6 +1037,7 @@ static const struct of_device_id pmic_gpio_of_match[] = {
1032 { .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */ 1037 { .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */
1033 { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */ 1038 { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */
1034 { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ 1039 { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
1040 { .compatible = "qcom,pmi8994-gpio" }, /* 10 GPIO's */
1035 { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */ 1041 { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */
1036 { .compatible = "qcom,spmi-gpio" }, /* Generic */ 1042 { .compatible = "qcom,spmi-gpio" }, /* Generic */
1037 { }, 1043 { },
diff --git a/drivers/pinctrl/samsung/Kconfig b/drivers/pinctrl/samsung/Kconfig
index 0357f9701eb9..ecfb90059eeb 100644
--- a/drivers/pinctrl/samsung/Kconfig
+++ b/drivers/pinctrl/samsung/Kconfig
@@ -29,7 +29,7 @@ config PINCTRL_EXYNOS5440
29 29
30config PINCTRL_S3C24XX 30config PINCTRL_S3C24XX
31 bool "Samsung S3C24XX SoC pinctrl driver" 31 bool "Samsung S3C24XX SoC pinctrl driver"
32 depends on ARCH_S3C24XX 32 depends on ARCH_S3C24XX && OF
33 select PINCTRL_SAMSUNG 33 select PINCTRL_SAMSUNG
34 34
35config PINCTRL_S3C64XX 35config PINCTRL_S3C64XX
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 0c5e952461fd..cf4ae4bc9115 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -24,6 +24,7 @@
24#include <linux/of_device.h> 24#include <linux/of_device.h>
25#include <linux/pinctrl/machine.h> 25#include <linux/pinctrl/machine.h>
26#include <linux/platform_device.h> 26#include <linux/platform_device.h>
27#include <linux/psci.h>
27#include <linux/slab.h> 28#include <linux/slab.h>
28 29
29#include "core.h" 30#include "core.h"
@@ -175,19 +176,19 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
175 BUG(); 176 BUG();
176} 177}
177 178
178u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width) 179u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
179{ 180{
180 return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), width); 181 return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
181} 182}
182 183
183void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data) 184void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
184{ 185{
185 if (pfc->info->unlock_reg) 186 if (pfc->info->unlock_reg)
186 sh_pfc_write_raw_reg( 187 sh_pfc_write_raw_reg(
187 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32, 188 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
188 ~data); 189 ~data);
189 190
190 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), width, data); 191 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
191} 192}
192 193
193static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, 194static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
@@ -389,15 +390,20 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
389 return 0; 390 return 0;
390} 391}
391 392
392const struct sh_pfc_bias_info * 393const struct pinmux_bias_reg *
393sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info, 394sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
394 unsigned int num, unsigned int pin) 395 unsigned int *bit)
395{ 396{
396 unsigned int i; 397 unsigned int i, j;
397 398
398 for (i = 0; i < num; i++) 399 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
399 if (info[i].pin == pin) 400 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
400 return &info[i]; 401 if (pfc->info->bias_regs[i].pins[j] == pin) {
402 *bit = j;
403 return &pfc->info->bias_regs[i];
404 }
405 }
406 }
401 407
402 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin); 408 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
403 409
@@ -567,9 +573,99 @@ static const struct of_device_id sh_pfc_of_table[] = {
567}; 573};
568#endif 574#endif
569 575
576#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
577static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
578{
579}
580
581static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
582{
583 pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
584}
585
586static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
587{
588 sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
589}
590
591static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
592 void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
593{
594 unsigned int i, n = 0;
595
596 if (pfc->info->cfg_regs)
597 for (i = 0; pfc->info->cfg_regs[i].reg; i++)
598 do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
599
600 if (pfc->info->drive_regs)
601 for (i = 0; pfc->info->drive_regs[i].reg; i++)
602 do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
603
604 if (pfc->info->bias_regs)
605 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
606 do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
607 if (pfc->info->bias_regs[i].pud)
608 do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
609 }
610
611 if (pfc->info->ioctrl_regs)
612 for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
613 do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
614
615 return n;
616}
617
618static int sh_pfc_suspend_init(struct sh_pfc *pfc)
619{
620 unsigned int n;
621
622 /* This is the best we can do to check for the presence of PSCI */
623 if (!psci_ops.cpu_suspend)
624 return 0;
625
626 n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
627 if (!n)
628 return 0;
629
630 pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
631 sizeof(*pfc->saved_regs),
632 GFP_KERNEL);
633 if (!pfc->saved_regs)
634 return -ENOMEM;
635
636 dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
637 return 0;
638}
639
640static int sh_pfc_suspend_noirq(struct device *dev)
641{
642 struct sh_pfc *pfc = dev_get_drvdata(dev);
643
644 if (pfc->saved_regs)
645 sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
646 return 0;
647}
648
649static int sh_pfc_resume_noirq(struct device *dev)
650{
651 struct sh_pfc *pfc = dev_get_drvdata(dev);
652
653 if (pfc->saved_regs)
654 sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
655 return 0;
656}
657
658static const struct dev_pm_ops sh_pfc_pm = {
659 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq)
660};
661#define DEV_PM_OPS &sh_pfc_pm
662#else
663static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
664#define DEV_PM_OPS NULL
665#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
666
570static int sh_pfc_probe(struct platform_device *pdev) 667static int sh_pfc_probe(struct platform_device *pdev)
571{ 668{
572 const struct platform_device_id *platid = platform_get_device_id(pdev);
573#ifdef CONFIG_OF 669#ifdef CONFIG_OF
574 struct device_node *np = pdev->dev.of_node; 670 struct device_node *np = pdev->dev.of_node;
575#endif 671#endif
@@ -582,10 +678,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
582 info = of_device_get_match_data(&pdev->dev); 678 info = of_device_get_match_data(&pdev->dev);
583 else 679 else
584#endif 680#endif
585 info = platid ? (const void *)platid->driver_data : NULL; 681 info = (const void *)platform_get_device_id(pdev)->driver_data;
586
587 if (info == NULL)
588 return -ENODEV;
589 682
590 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL); 683 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
591 if (pfc == NULL) 684 if (pfc == NULL)
@@ -609,6 +702,10 @@ static int sh_pfc_probe(struct platform_device *pdev)
609 info = pfc->info; 702 info = pfc->info;
610 } 703 }
611 704
705 ret = sh_pfc_suspend_init(pfc);
706 if (ret)
707 return ret;
708
612 /* Enable dummy states for those platforms without pinctrl support */ 709 /* Enable dummy states for those platforms without pinctrl support */
613 if (!of_have_populated_dt()) 710 if (!of_have_populated_dt())
614 pinctrl_provide_dummies(); 711 pinctrl_provide_dummies();
@@ -683,7 +780,6 @@ static const struct platform_device_id sh_pfc_id_table[] = {
683#ifdef CONFIG_PINCTRL_PFC_SHX3 780#ifdef CONFIG_PINCTRL_PFC_SHX3
684 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info }, 781 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
685#endif 782#endif
686 { "sh-pfc", 0 },
687 { }, 783 { },
688}; 784};
689 785
@@ -693,6 +789,7 @@ static struct platform_driver sh_pfc_driver = {
693 .driver = { 789 .driver = {
694 .name = DRV_NAME, 790 .name = DRV_NAME,
695 .of_match_table = of_match_ptr(sh_pfc_of_table), 791 .of_match_table = of_match_ptr(sh_pfc_of_table),
792 .pm = DEV_PM_OPS,
696 }, 793 },
697}; 794};
698 795
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 6d598dd63720..5af8ee26c03e 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -26,15 +26,14 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc);
26u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width); 26u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width);
27void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width, 27void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
28 u32 data); 28 u32 data);
29u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width); 29u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg);
30void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, 30void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data);
31 u32 data);
32 31
33int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin); 32int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
34int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type); 33int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
35 34
36const struct sh_pfc_bias_info * 35const struct pinmux_bias_reg *
37sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info, 36sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
38 unsigned int num, unsigned int pin); 37 unsigned int *bit);
39 38
40#endif /* __SH_PFC_CORE_H__ */ 39#endif /* __SH_PFC_CORE_H__ */
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 6b5422766f13..946d9be50b62 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -139,12 +139,12 @@ static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
139 if (idx < 0 || pfc->info->pins[idx].enum_id == 0) 139 if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
140 return -EINVAL; 140 return -EINVAL;
141 141
142 return pinctrl_request_gpio(offset); 142 return pinctrl_gpio_request(offset);
143} 143}
144 144
145static void gpio_pin_free(struct gpio_chip *gc, unsigned offset) 145static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
146{ 146{
147 return pinctrl_free_gpio(offset); 147 return pinctrl_gpio_free(offset);
148} 148}
149 149
150static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset, 150static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index c3af9ebee4af..00d61d175249 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -2912,189 +2912,230 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2912 { }, 2912 { },
2913}; 2913};
2914 2914
2915#define PUPR0 0x100 2915#define PIN_NONE U16_MAX
2916#define PUPR1 0x104 2916
2917#define PUPR2 0x108 2917static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2918#define PUPR3 0x10c 2918 { PINMUX_BIAS_REG("PUPR0", 0x100, "N/A", 0) {
2919#define PUPR4 0x110 2919 [ 0] = RCAR_GP_PIN(0, 6), /* A0 */
2920#define PUPR5 0x114 2920 [ 1] = RCAR_GP_PIN(0, 7), /* A1 */
2921 2921 [ 2] = RCAR_GP_PIN(0, 8), /* A2 */
2922static const struct sh_pfc_bias_info bias_info[] = { 2922 [ 3] = RCAR_GP_PIN(0, 9), /* A3 */
2923 { RCAR_GP_PIN(0, 6), PUPR0, 0 }, /* A0 */ 2923 [ 4] = RCAR_GP_PIN(0, 10), /* A4 */
2924 { RCAR_GP_PIN(0, 7), PUPR0, 1 }, /* A1 */ 2924 [ 5] = RCAR_GP_PIN(0, 11), /* A5 */
2925 { RCAR_GP_PIN(0, 8), PUPR0, 2 }, /* A2 */ 2925 [ 6] = RCAR_GP_PIN(0, 12), /* A6 */
2926 { RCAR_GP_PIN(0, 9), PUPR0, 3 }, /* A3 */ 2926 [ 7] = RCAR_GP_PIN(0, 13), /* A7 */
2927 { RCAR_GP_PIN(0, 10), PUPR0, 4 }, /* A4 */ 2927 [ 8] = RCAR_GP_PIN(0, 14), /* A8 */
2928 { RCAR_GP_PIN(0, 11), PUPR0, 5 }, /* A5 */ 2928 [ 9] = RCAR_GP_PIN(0, 15), /* A9 */
2929 { RCAR_GP_PIN(0, 12), PUPR0, 6 }, /* A6 */ 2929 [10] = RCAR_GP_PIN(0, 16), /* A10 */
2930 { RCAR_GP_PIN(0, 13), PUPR0, 7 }, /* A7 */ 2930 [11] = RCAR_GP_PIN(0, 17), /* A11 */
2931 { RCAR_GP_PIN(0, 14), PUPR0, 8 }, /* A8 */ 2931 [12] = RCAR_GP_PIN(0, 18), /* A12 */
2932 { RCAR_GP_PIN(0, 15), PUPR0, 9 }, /* A9 */ 2932 [13] = RCAR_GP_PIN(0, 19), /* A13 */
2933 { RCAR_GP_PIN(0, 16), PUPR0, 10 }, /* A10 */ 2933 [14] = RCAR_GP_PIN(0, 20), /* A14 */
2934 { RCAR_GP_PIN(0, 17), PUPR0, 11 }, /* A11 */ 2934 [15] = RCAR_GP_PIN(0, 21), /* A15 */
2935 { RCAR_GP_PIN(0, 18), PUPR0, 12 }, /* A12 */ 2935 [16] = RCAR_GP_PIN(0, 22), /* A16 */
2936 { RCAR_GP_PIN(0, 19), PUPR0, 13 }, /* A13 */ 2936 [17] = RCAR_GP_PIN(0, 23), /* A17 */
2937 { RCAR_GP_PIN(0, 20), PUPR0, 14 }, /* A14 */ 2937 [18] = RCAR_GP_PIN(0, 24), /* A18 */
2938 { RCAR_GP_PIN(0, 21), PUPR0, 15 }, /* A15 */ 2938 [19] = RCAR_GP_PIN(0, 25), /* A19 */
2939 { RCAR_GP_PIN(0, 22), PUPR0, 16 }, /* A16 */ 2939 [20] = RCAR_GP_PIN(0, 26), /* A20 */
2940 { RCAR_GP_PIN(0, 23), PUPR0, 17 }, /* A17 */ 2940 [21] = RCAR_GP_PIN(0, 27), /* A21 */
2941 { RCAR_GP_PIN(0, 24), PUPR0, 18 }, /* A18 */ 2941 [22] = RCAR_GP_PIN(0, 28), /* A22 */
2942 { RCAR_GP_PIN(0, 25), PUPR0, 19 }, /* A19 */ 2942 [23] = RCAR_GP_PIN(0, 29), /* A23 */
2943 { RCAR_GP_PIN(0, 26), PUPR0, 20 }, /* A20 */ 2943 [24] = RCAR_GP_PIN(0, 30), /* A24 */
2944 { RCAR_GP_PIN(0, 27), PUPR0, 21 }, /* A21 */ 2944 [25] = RCAR_GP_PIN(0, 31), /* A25 */
2945 { RCAR_GP_PIN(0, 28), PUPR0, 22 }, /* A22 */ 2945 [26] = RCAR_GP_PIN(1, 3), /* /EX_CS0 */
2946 { RCAR_GP_PIN(0, 29), PUPR0, 23 }, /* A23 */ 2946 [27] = RCAR_GP_PIN(1, 4), /* /EX_CS1 */
2947 { RCAR_GP_PIN(0, 30), PUPR0, 24 }, /* A24 */ 2947 [28] = RCAR_GP_PIN(1, 5), /* /EX_CS2 */
2948 { RCAR_GP_PIN(0, 31), PUPR0, 25 }, /* A25 */ 2948 [29] = RCAR_GP_PIN(1, 6), /* /EX_CS3 */
2949 { RCAR_GP_PIN(1, 3), PUPR0, 26 }, /* /EX_CS0 */ 2949 [30] = RCAR_GP_PIN(1, 7), /* /EX_CS4 */
2950 { RCAR_GP_PIN(1, 4), PUPR0, 27 }, /* /EX_CS1 */ 2950 [31] = RCAR_GP_PIN(1, 8), /* /EX_CS5 */
2951 { RCAR_GP_PIN(1, 5), PUPR0, 28 }, /* /EX_CS2 */ 2951 } },
2952 { RCAR_GP_PIN(1, 6), PUPR0, 29 }, /* /EX_CS3 */ 2952 { PINMUX_BIAS_REG("PUPR1", 0x104, "N/A", 0) {
2953 { RCAR_GP_PIN(1, 7), PUPR0, 30 }, /* /EX_CS4 */ 2953 [ 0] = RCAR_GP_PIN(0, 0), /* /PRESETOUT */
2954 { RCAR_GP_PIN(1, 8), PUPR0, 31 }, /* /EX_CS5 */ 2954 [ 1] = RCAR_GP_PIN(0, 5), /* /BS */
2955 2955 [ 2] = RCAR_GP_PIN(1, 0), /* RD//WR */
2956 { RCAR_GP_PIN(0, 0), PUPR1, 0 }, /* /PRESETOUT */ 2956 [ 3] = RCAR_GP_PIN(1, 1), /* /WE0 */
2957 { RCAR_GP_PIN(0, 5), PUPR1, 1 }, /* /BS */ 2957 [ 4] = RCAR_GP_PIN(1, 2), /* /WE1 */
2958 { RCAR_GP_PIN(1, 0), PUPR1, 2 }, /* RD//WR */ 2958 [ 5] = RCAR_GP_PIN(1, 11), /* EX_WAIT0 */
2959 { RCAR_GP_PIN(1, 1), PUPR1, 3 }, /* /WE0 */ 2959 [ 6] = RCAR_GP_PIN(1, 9), /* DREQ0 */
2960 { RCAR_GP_PIN(1, 2), PUPR1, 4 }, /* /WE1 */ 2960 [ 7] = RCAR_GP_PIN(1, 10), /* DACK0 */
2961 { RCAR_GP_PIN(1, 11), PUPR1, 5 }, /* EX_WAIT0 */ 2961 [ 8] = RCAR_GP_PIN(1, 12), /* IRQ0 */
2962 { RCAR_GP_PIN(1, 9), PUPR1, 6 }, /* DREQ0 */ 2962 [ 9] = RCAR_GP_PIN(1, 13), /* IRQ1 */
2963 { RCAR_GP_PIN(1, 10), PUPR1, 7 }, /* DACK0 */ 2963 [10] = PIN_NONE,
2964 { RCAR_GP_PIN(1, 12), PUPR1, 8 }, /* IRQ0 */ 2964 [11] = PIN_NONE,
2965 { RCAR_GP_PIN(1, 13), PUPR1, 9 }, /* IRQ1 */ 2965 [12] = PIN_NONE,
2966 2966 [13] = PIN_NONE,
2967 { RCAR_GP_PIN(1, 22), PUPR2, 0 }, /* DU0_DR0 */ 2967 [14] = PIN_NONE,
2968 { RCAR_GP_PIN(1, 23), PUPR2, 1 }, /* DU0_DR1 */ 2968 [15] = PIN_NONE,
2969 { RCAR_GP_PIN(1, 24), PUPR2, 2 }, /* DU0_DR2 */ 2969 [16] = PIN_NONE,
2970 { RCAR_GP_PIN(1, 25), PUPR2, 3 }, /* DU0_DR3 */ 2970 [17] = PIN_NONE,
2971 { RCAR_GP_PIN(1, 26), PUPR2, 4 }, /* DU0_DR4 */ 2971 [18] = PIN_NONE,
2972 { RCAR_GP_PIN(1, 27), PUPR2, 5 }, /* DU0_DR5 */ 2972 [19] = PIN_NONE,
2973 { RCAR_GP_PIN(1, 28), PUPR2, 6 }, /* DU0_DR6 */ 2973 [20] = PIN_NONE,
2974 { RCAR_GP_PIN(1, 29), PUPR2, 7 }, /* DU0_DR7 */ 2974 [21] = PIN_NONE,
2975 { RCAR_GP_PIN(1, 30), PUPR2, 8 }, /* DU0_DG0 */ 2975 [22] = PIN_NONE,
2976 { RCAR_GP_PIN(1, 31), PUPR2, 9 }, /* DU0_DG1 */ 2976 [23] = PIN_NONE,
2977 { RCAR_GP_PIN(2, 0), PUPR2, 10 }, /* DU0_DG2 */ 2977 [24] = PIN_NONE,
2978 { RCAR_GP_PIN(2, 1), PUPR2, 11 }, /* DU0_DG3 */ 2978 [25] = PIN_NONE,
2979 { RCAR_GP_PIN(2, 2), PUPR2, 12 }, /* DU0_DG4 */ 2979 [26] = PIN_NONE,
2980 { RCAR_GP_PIN(2, 3), PUPR2, 13 }, /* DU0_DG5 */ 2980 [27] = PIN_NONE,
2981 { RCAR_GP_PIN(2, 4), PUPR2, 14 }, /* DU0_DG6 */ 2981 [28] = PIN_NONE,
2982 { RCAR_GP_PIN(2, 5), PUPR2, 15 }, /* DU0_DG7 */ 2982 [29] = PIN_NONE,
2983 { RCAR_GP_PIN(2, 6), PUPR2, 16 }, /* DU0_DB0 */ 2983 [30] = PIN_NONE,
2984 { RCAR_GP_PIN(2, 7), PUPR2, 17 }, /* DU0_DB1 */ 2984 [31] = PIN_NONE,
2985 { RCAR_GP_PIN(2, 8), PUPR2, 18 }, /* DU0_DB2 */ 2985 } },
2986 { RCAR_GP_PIN(2, 9), PUPR2, 19 }, /* DU0_DB3 */ 2986 { PINMUX_BIAS_REG("PUPR2", 0x108, "N/A", 0) {
2987 { RCAR_GP_PIN(2, 10), PUPR2, 20 }, /* DU0_DB4 */ 2987 [ 0] = RCAR_GP_PIN(1, 22), /* DU0_DR0 */
2988 { RCAR_GP_PIN(2, 11), PUPR2, 21 }, /* DU0_DB5 */ 2988 [ 1] = RCAR_GP_PIN(1, 23), /* DU0_DR1 */
2989 { RCAR_GP_PIN(2, 12), PUPR2, 22 }, /* DU0_DB6 */ 2989 [ 2] = RCAR_GP_PIN(1, 24), /* DU0_DR2 */
2990 { RCAR_GP_PIN(2, 13), PUPR2, 23 }, /* DU0_DB7 */ 2990 [ 3] = RCAR_GP_PIN(1, 25), /* DU0_DR3 */
2991 { RCAR_GP_PIN(2, 14), PUPR2, 24 }, /* DU0_DOTCLKIN */ 2991 [ 4] = RCAR_GP_PIN(1, 26), /* DU0_DR4 */
2992 { RCAR_GP_PIN(2, 15), PUPR2, 25 }, /* DU0_DOTCLKOUT0 */ 2992 [ 5] = RCAR_GP_PIN(1, 27), /* DU0_DR5 */
2993 { RCAR_GP_PIN(2, 17), PUPR2, 26 }, /* DU0_HSYNC */ 2993 [ 6] = RCAR_GP_PIN(1, 28), /* DU0_DR6 */
2994 { RCAR_GP_PIN(2, 18), PUPR2, 27 }, /* DU0_VSYNC */ 2994 [ 7] = RCAR_GP_PIN(1, 29), /* DU0_DR7 */
2995 { RCAR_GP_PIN(2, 19), PUPR2, 28 }, /* DU0_EXODDF */ 2995 [ 8] = RCAR_GP_PIN(1, 30), /* DU0_DG0 */
2996 { RCAR_GP_PIN(2, 20), PUPR2, 29 }, /* DU0_DISP */ 2996 [ 9] = RCAR_GP_PIN(1, 31), /* DU0_DG1 */
2997 { RCAR_GP_PIN(2, 21), PUPR2, 30 }, /* DU0_CDE */ 2997 [10] = RCAR_GP_PIN(2, 0), /* DU0_DG2 */
2998 { RCAR_GP_PIN(2, 16), PUPR2, 31 }, /* DU0_DOTCLKOUT1 */ 2998 [11] = RCAR_GP_PIN(2, 1), /* DU0_DG3 */
2999 2999 [12] = RCAR_GP_PIN(2, 2), /* DU0_DG4 */
3000 { RCAR_GP_PIN(3, 24), PUPR3, 0 }, /* VI0_CLK */ 3000 [13] = RCAR_GP_PIN(2, 3), /* DU0_DG5 */
3001 { RCAR_GP_PIN(3, 25), PUPR3, 1 }, /* VI0_CLKENB */ 3001 [14] = RCAR_GP_PIN(2, 4), /* DU0_DG6 */
3002 { RCAR_GP_PIN(3, 26), PUPR3, 2 }, /* VI0_FIELD */ 3002 [15] = RCAR_GP_PIN(2, 5), /* DU0_DG7 */
3003 { RCAR_GP_PIN(3, 27), PUPR3, 3 }, /* /VI0_HSYNC */ 3003 [16] = RCAR_GP_PIN(2, 6), /* DU0_DB0 */
3004 { RCAR_GP_PIN(3, 28), PUPR3, 4 }, /* /VI0_VSYNC */ 3004 [17] = RCAR_GP_PIN(2, 7), /* DU0_DB1 */
3005 { RCAR_GP_PIN(3, 29), PUPR3, 5 }, /* VI0_DATA0 */ 3005 [18] = RCAR_GP_PIN(2, 8), /* DU0_DB2 */
3006 { RCAR_GP_PIN(3, 30), PUPR3, 6 }, /* VI0_DATA1 */ 3006 [19] = RCAR_GP_PIN(2, 9), /* DU0_DB3 */
3007 { RCAR_GP_PIN(3, 31), PUPR3, 7 }, /* VI0_DATA2 */ 3007 [20] = RCAR_GP_PIN(2, 10), /* DU0_DB4 */
3008 { RCAR_GP_PIN(4, 0), PUPR3, 8 }, /* VI0_DATA3 */ 3008 [21] = RCAR_GP_PIN(2, 11), /* DU0_DB5 */
3009 { RCAR_GP_PIN(4, 1), PUPR3, 9 }, /* VI0_DATA4 */ 3009 [22] = RCAR_GP_PIN(2, 12), /* DU0_DB6 */
3010 { RCAR_GP_PIN(4, 2), PUPR3, 10 }, /* VI0_DATA5 */ 3010 [23] = RCAR_GP_PIN(2, 13), /* DU0_DB7 */
3011 { RCAR_GP_PIN(4, 3), PUPR3, 11 }, /* VI0_DATA6 */ 3011 [24] = RCAR_GP_PIN(2, 14), /* DU0_DOTCLKIN */
3012 { RCAR_GP_PIN(4, 4), PUPR3, 12 }, /* VI0_DATA7 */ 3012 [25] = RCAR_GP_PIN(2, 15), /* DU0_DOTCLKOUT0 */
3013 { RCAR_GP_PIN(4, 5), PUPR3, 13 }, /* VI0_G2 */ 3013 [26] = RCAR_GP_PIN(2, 17), /* DU0_HSYNC */
3014 { RCAR_GP_PIN(4, 6), PUPR3, 14 }, /* VI0_G3 */ 3014 [27] = RCAR_GP_PIN(2, 18), /* DU0_VSYNC */
3015 { RCAR_GP_PIN(4, 7), PUPR3, 15 }, /* VI0_G4 */ 3015 [28] = RCAR_GP_PIN(2, 19), /* DU0_EXODDF */
3016 { RCAR_GP_PIN(4, 8), PUPR3, 16 }, /* VI0_G5 */ 3016 [29] = RCAR_GP_PIN(2, 20), /* DU0_DISP */
3017 { RCAR_GP_PIN(4, 21), PUPR3, 17 }, /* VI1_DATA12 */ 3017 [30] = RCAR_GP_PIN(2, 21), /* DU0_CDE */
3018 { RCAR_GP_PIN(4, 22), PUPR3, 18 }, /* VI1_DATA13 */ 3018 [31] = RCAR_GP_PIN(2, 16), /* DU0_DOTCLKOUT1 */
3019 { RCAR_GP_PIN(4, 23), PUPR3, 19 }, /* VI1_DATA14 */ 3019 } },
3020 { RCAR_GP_PIN(4, 24), PUPR3, 20 }, /* VI1_DATA15 */ 3020 { PINMUX_BIAS_REG("PUPR3", 0x10c, "N/A", 0) {
3021 { RCAR_GP_PIN(4, 9), PUPR3, 21 }, /* ETH_REF_CLK */ 3021 [ 0] = RCAR_GP_PIN(3, 24), /* VI0_CLK */
3022 { RCAR_GP_PIN(4, 10), PUPR3, 22 }, /* ETH_TXD0 */ 3022 [ 1] = RCAR_GP_PIN(3, 25), /* VI0_CLKENB */
3023 { RCAR_GP_PIN(4, 11), PUPR3, 23 }, /* ETH_TXD1 */ 3023 [ 2] = RCAR_GP_PIN(3, 26), /* VI0_FIELD */
3024 { RCAR_GP_PIN(4, 12), PUPR3, 24 }, /* ETH_CRS_DV */ 3024 [ 3] = RCAR_GP_PIN(3, 27), /* /VI0_HSYNC */
3025 { RCAR_GP_PIN(4, 13), PUPR3, 25 }, /* ETH_TX_EN */ 3025 [ 4] = RCAR_GP_PIN(3, 28), /* /VI0_VSYNC */
3026 { RCAR_GP_PIN(4, 14), PUPR3, 26 }, /* ETH_RX_ER */ 3026 [ 5] = RCAR_GP_PIN(3, 29), /* VI0_DATA0 */
3027 { RCAR_GP_PIN(4, 15), PUPR3, 27 }, /* ETH_RXD0 */ 3027 [ 6] = RCAR_GP_PIN(3, 30), /* VI0_DATA1 */
3028 { RCAR_GP_PIN(4, 16), PUPR3, 28 }, /* ETH_RXD1 */ 3028 [ 7] = RCAR_GP_PIN(3, 31), /* VI0_DATA2 */
3029 { RCAR_GP_PIN(4, 17), PUPR3, 29 }, /* ETH_MDC */ 3029 [ 8] = RCAR_GP_PIN(4, 0), /* VI0_DATA3 */
3030 { RCAR_GP_PIN(4, 18), PUPR3, 30 }, /* ETH_MDIO */ 3030 [ 9] = RCAR_GP_PIN(4, 1), /* VI0_DATA4 */
3031 { RCAR_GP_PIN(4, 19), PUPR3, 31 }, /* ETH_LINK */ 3031 [10] = RCAR_GP_PIN(4, 2), /* VI0_DATA5 */
3032 3032 [11] = RCAR_GP_PIN(4, 3), /* VI0_DATA6 */
3033 { RCAR_GP_PIN(3, 6), PUPR4, 0 }, /* SSI_SCK012 */ 3033 [12] = RCAR_GP_PIN(4, 4), /* VI0_DATA7 */
3034 { RCAR_GP_PIN(3, 7), PUPR4, 1 }, /* SSI_WS012 */ 3034 [13] = RCAR_GP_PIN(4, 5), /* VI0_G2 */
3035 { RCAR_GP_PIN(3, 10), PUPR4, 2 }, /* SSI_SDATA0 */ 3035 [14] = RCAR_GP_PIN(4, 6), /* VI0_G3 */
3036 { RCAR_GP_PIN(3, 9), PUPR4, 3 }, /* SSI_SDATA1 */ 3036 [15] = RCAR_GP_PIN(4, 7), /* VI0_G4 */
3037 { RCAR_GP_PIN(3, 8), PUPR4, 4 }, /* SSI_SDATA2 */ 3037 [16] = RCAR_GP_PIN(4, 8), /* VI0_G5 */
3038 { RCAR_GP_PIN(3, 2), PUPR4, 5 }, /* SSI_SCK34 */ 3038 [17] = RCAR_GP_PIN(4, 21), /* VI1_DATA12 */
3039 { RCAR_GP_PIN(3, 3), PUPR4, 6 }, /* SSI_WS34 */ 3039 [18] = RCAR_GP_PIN(4, 22), /* VI1_DATA13 */
3040 { RCAR_GP_PIN(3, 5), PUPR4, 7 }, /* SSI_SDATA3 */ 3040 [19] = RCAR_GP_PIN(4, 23), /* VI1_DATA14 */
3041 { RCAR_GP_PIN(3, 4), PUPR4, 8 }, /* SSI_SDATA4 */ 3041 [20] = RCAR_GP_PIN(4, 24), /* VI1_DATA15 */
3042 { RCAR_GP_PIN(2, 31), PUPR4, 9 }, /* SSI_SCK5 */ 3042 [21] = RCAR_GP_PIN(4, 9), /* ETH_REF_CLK */
3043 { RCAR_GP_PIN(3, 0), PUPR4, 10 }, /* SSI_WS5 */ 3043 [22] = RCAR_GP_PIN(4, 10), /* ETH_TXD0 */
3044 { RCAR_GP_PIN(3, 1), PUPR4, 11 }, /* SSI_SDATA5 */ 3044 [23] = RCAR_GP_PIN(4, 11), /* ETH_TXD1 */
3045 { RCAR_GP_PIN(2, 28), PUPR4, 12 }, /* SSI_SCK6 */ 3045 [24] = RCAR_GP_PIN(4, 12), /* ETH_CRS_DV */
3046 { RCAR_GP_PIN(2, 29), PUPR4, 13 }, /* SSI_WS6 */ 3046 [25] = RCAR_GP_PIN(4, 13), /* ETH_TX_EN */
3047 { RCAR_GP_PIN(2, 30), PUPR4, 14 }, /* SSI_SDATA6 */ 3047 [26] = RCAR_GP_PIN(4, 14), /* ETH_RX_ER */
3048 { RCAR_GP_PIN(2, 24), PUPR4, 15 }, /* SSI_SCK78 */ 3048 [27] = RCAR_GP_PIN(4, 15), /* ETH_RXD0 */
3049 { RCAR_GP_PIN(2, 25), PUPR4, 16 }, /* SSI_WS78 */ 3049 [28] = RCAR_GP_PIN(4, 16), /* ETH_RXD1 */
3050 { RCAR_GP_PIN(2, 27), PUPR4, 17 }, /* SSI_SDATA7 */ 3050 [29] = RCAR_GP_PIN(4, 17), /* ETH_MDC */
3051 { RCAR_GP_PIN(2, 26), PUPR4, 18 }, /* SSI_SDATA8 */ 3051 [30] = RCAR_GP_PIN(4, 18), /* ETH_MDIO */
3052 { RCAR_GP_PIN(3, 23), PUPR4, 19 }, /* TCLK0 */ 3052 [31] = RCAR_GP_PIN(4, 19), /* ETH_LINK */
3053 { RCAR_GP_PIN(3, 11), PUPR4, 20 }, /* SD0_CLK */ 3053 } },
3054 { RCAR_GP_PIN(3, 12), PUPR4, 21 }, /* SD0_CMD */ 3054 { PINMUX_BIAS_REG("PUPR4", 0x110, "N/A", 0) {
3055 { RCAR_GP_PIN(3, 13), PUPR4, 22 }, /* SD0_DAT0 */ 3055 [ 0] = RCAR_GP_PIN(3, 6), /* SSI_SCK012 */
3056 { RCAR_GP_PIN(3, 14), PUPR4, 23 }, /* SD0_DAT1 */ 3056 [ 1] = RCAR_GP_PIN(3, 7), /* SSI_WS012 */
3057 { RCAR_GP_PIN(3, 15), PUPR4, 24 }, /* SD0_DAT2 */ 3057 [ 2] = RCAR_GP_PIN(3, 10), /* SSI_SDATA0 */
3058 { RCAR_GP_PIN(3, 16), PUPR4, 25 }, /* SD0_DAT3 */ 3058 [ 3] = RCAR_GP_PIN(3, 9), /* SSI_SDATA1 */
3059 { RCAR_GP_PIN(3, 17), PUPR4, 26 }, /* SD0_CD */ 3059 [ 4] = RCAR_GP_PIN(3, 8), /* SSI_SDATA2 */
3060 { RCAR_GP_PIN(3, 18), PUPR4, 27 }, /* SD0_WP */ 3060 [ 5] = RCAR_GP_PIN(3, 2), /* SSI_SCK34 */
3061 { RCAR_GP_PIN(2, 22), PUPR4, 28 }, /* AUDIO_CLKA */ 3061 [ 6] = RCAR_GP_PIN(3, 3), /* SSI_WS34 */
3062 { RCAR_GP_PIN(2, 23), PUPR4, 29 }, /* AUDIO_CLKB */ 3062 [ 7] = RCAR_GP_PIN(3, 5), /* SSI_SDATA3 */
3063 { RCAR_GP_PIN(1, 14), PUPR4, 30 }, /* IRQ2 */ 3063 [ 8] = RCAR_GP_PIN(3, 4), /* SSI_SDATA4 */
3064 { RCAR_GP_PIN(1, 15), PUPR4, 31 }, /* IRQ3 */ 3064 [ 9] = RCAR_GP_PIN(2, 31), /* SSI_SCK5 */
3065 3065 [10] = RCAR_GP_PIN(3, 0), /* SSI_WS5 */
3066 { RCAR_GP_PIN(0, 1), PUPR5, 0 }, /* PENC0 */ 3066 [11] = RCAR_GP_PIN(3, 1), /* SSI_SDATA5 */
3067 { RCAR_GP_PIN(0, 2), PUPR5, 1 }, /* PENC1 */ 3067 [12] = RCAR_GP_PIN(2, 28), /* SSI_SCK6 */
3068 { RCAR_GP_PIN(0, 3), PUPR5, 2 }, /* USB_OVC0 */ 3068 [13] = RCAR_GP_PIN(2, 29), /* SSI_WS6 */
3069 { RCAR_GP_PIN(0, 4), PUPR5, 3 }, /* USB_OVC1 */ 3069 [14] = RCAR_GP_PIN(2, 30), /* SSI_SDATA6 */
3070 { RCAR_GP_PIN(1, 16), PUPR5, 4 }, /* SCIF_CLK */ 3070 [15] = RCAR_GP_PIN(2, 24), /* SSI_SCK78 */
3071 { RCAR_GP_PIN(1, 17), PUPR5, 5 }, /* TX0 */ 3071 [16] = RCAR_GP_PIN(2, 25), /* SSI_WS78 */
3072 { RCAR_GP_PIN(1, 18), PUPR5, 6 }, /* RX0 */ 3072 [17] = RCAR_GP_PIN(2, 27), /* SSI_SDATA7 */
3073 { RCAR_GP_PIN(1, 19), PUPR5, 7 }, /* SCK0 */ 3073 [18] = RCAR_GP_PIN(2, 26), /* SSI_SDATA8 */
3074 { RCAR_GP_PIN(1, 20), PUPR5, 8 }, /* /CTS0 */ 3074 [19] = RCAR_GP_PIN(3, 23), /* TCLK0 */
3075 { RCAR_GP_PIN(1, 21), PUPR5, 9 }, /* /RTS0 */ 3075 [20] = RCAR_GP_PIN(3, 11), /* SD0_CLK */
3076 { RCAR_GP_PIN(3, 19), PUPR5, 10 }, /* HSPI_CLK0 */ 3076 [21] = RCAR_GP_PIN(3, 12), /* SD0_CMD */
3077 { RCAR_GP_PIN(3, 20), PUPR5, 11 }, /* /HSPI_CS0 */ 3077 [22] = RCAR_GP_PIN(3, 13), /* SD0_DAT0 */
3078 { RCAR_GP_PIN(3, 21), PUPR5, 12 }, /* HSPI_RX0 */ 3078 [23] = RCAR_GP_PIN(3, 14), /* SD0_DAT1 */
3079 { RCAR_GP_PIN(3, 22), PUPR5, 13 }, /* HSPI_TX0 */ 3079 [24] = RCAR_GP_PIN(3, 15), /* SD0_DAT2 */
3080 { RCAR_GP_PIN(4, 20), PUPR5, 14 }, /* ETH_MAGIC */ 3080 [25] = RCAR_GP_PIN(3, 16), /* SD0_DAT3 */
3081 { RCAR_GP_PIN(4, 25), PUPR5, 15 }, /* AVS1 */ 3081 [26] = RCAR_GP_PIN(3, 17), /* SD0_CD */
3082 { RCAR_GP_PIN(4, 26), PUPR5, 16 }, /* AVS2 */ 3082 [27] = RCAR_GP_PIN(3, 18), /* SD0_WP */
3083 [28] = RCAR_GP_PIN(2, 22), /* AUDIO_CLKA */
3084 [29] = RCAR_GP_PIN(2, 23), /* AUDIO_CLKB */
3085 [30] = RCAR_GP_PIN(1, 14), /* IRQ2 */
3086 [31] = RCAR_GP_PIN(1, 15), /* IRQ3 */
3087 } },
3088 { PINMUX_BIAS_REG("PUPR5", 0x114, "N/A", 0) {
3089 [ 0] = RCAR_GP_PIN(0, 1), /* PENC0 */
3090 [ 1] = RCAR_GP_PIN(0, 2), /* PENC1 */
3091 [ 2] = RCAR_GP_PIN(0, 3), /* USB_OVC0 */
3092 [ 3] = RCAR_GP_PIN(0, 4), /* USB_OVC1 */
3093 [ 4] = RCAR_GP_PIN(1, 16), /* SCIF_CLK */
3094 [ 5] = RCAR_GP_PIN(1, 17), /* TX0 */
3095 [ 6] = RCAR_GP_PIN(1, 18), /* RX0 */
3096 [ 7] = RCAR_GP_PIN(1, 19), /* SCK0 */
3097 [ 8] = RCAR_GP_PIN(1, 20), /* /CTS0 */
3098 [ 9] = RCAR_GP_PIN(1, 21), /* /RTS0 */
3099 [10] = RCAR_GP_PIN(3, 19), /* HSPI_CLK0 */
3100 [11] = RCAR_GP_PIN(3, 20), /* /HSPI_CS0 */
3101 [12] = RCAR_GP_PIN(3, 21), /* HSPI_RX0 */
3102 [13] = RCAR_GP_PIN(3, 22), /* HSPI_TX0 */
3103 [14] = RCAR_GP_PIN(4, 20), /* ETH_MAGIC */
3104 [15] = RCAR_GP_PIN(4, 25), /* AVS1 */
3105 [16] = RCAR_GP_PIN(4, 26), /* AVS2 */
3106 [17] = PIN_NONE,
3107 [18] = PIN_NONE,
3108 [19] = PIN_NONE,
3109 [20] = PIN_NONE,
3110 [21] = PIN_NONE,
3111 [22] = PIN_NONE,
3112 [23] = PIN_NONE,
3113 [24] = PIN_NONE,
3114 [25] = PIN_NONE,
3115 [26] = PIN_NONE,
3116 [27] = PIN_NONE,
3117 [28] = PIN_NONE,
3118 [29] = PIN_NONE,
3119 [30] = PIN_NONE,
3120 [31] = PIN_NONE,
3121 } },
3122 { /* sentinel */ },
3083}; 3123};
3084 3124
3085static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc, 3125static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc,
3086 unsigned int pin) 3126 unsigned int pin)
3087{ 3127{
3088 const struct sh_pfc_bias_info *info; 3128 const struct pinmux_bias_reg *reg;
3089 void __iomem *addr; 3129 void __iomem *addr;
3130 unsigned int bit;
3090 3131
3091 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); 3132 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
3092 if (!info) 3133 if (!reg)
3093 return PIN_CONFIG_BIAS_DISABLE; 3134 return PIN_CONFIG_BIAS_DISABLE;
3094 3135
3095 addr = pfc->windows->virt + info->reg; 3136 addr = pfc->windows->virt + reg->puen;
3096 3137
3097 if (ioread32(addr) & BIT(info->bit)) 3138 if (ioread32(addr) & BIT(bit))
3098 return PIN_CONFIG_BIAS_PULL_UP; 3139 return PIN_CONFIG_BIAS_PULL_UP;
3099 else 3140 else
3100 return PIN_CONFIG_BIAS_DISABLE; 3141 return PIN_CONFIG_BIAS_DISABLE;
@@ -3103,21 +3144,20 @@ static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc,
3103static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 3144static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3104 unsigned int bias) 3145 unsigned int bias)
3105{ 3146{
3106 const struct sh_pfc_bias_info *info; 3147 const struct pinmux_bias_reg *reg;
3107 void __iomem *addr; 3148 void __iomem *addr;
3149 unsigned int bit;
3108 u32 value; 3150 u32 value;
3109 u32 bit;
3110 3151
3111 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); 3152 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
3112 if (!info) 3153 if (!reg)
3113 return; 3154 return;
3114 3155
3115 addr = pfc->windows->virt + info->reg; 3156 addr = pfc->windows->virt + reg->puen;
3116 bit = BIT(info->bit);
3117 3157
3118 value = ioread32(addr) & ~bit; 3158 value = ioread32(addr) & ~BIT(bit);
3119 if (bias == PIN_CONFIG_BIAS_PULL_UP) 3159 if (bias == PIN_CONFIG_BIAS_PULL_UP)
3120 value |= bit; 3160 value |= BIT(bit);
3121 iowrite32(value, addr); 3161 iowrite32(value, addr);
3122} 3162}
3123 3163
@@ -3144,6 +3184,7 @@ const struct sh_pfc_soc_info r8a7778_pinmux_info = {
3144 .nr_functions = ARRAY_SIZE(pinmux_functions), 3184 .nr_functions = ARRAY_SIZE(pinmux_functions),
3145 3185
3146 .cfg_regs = pinmux_config_regs, 3186 .cfg_regs = pinmux_config_regs,
3187 .bias_regs = pinmux_bias_regs,
3147 3188
3148 .pinmux_data = pinmux_data, 3189 .pinmux_data = pinmux_data,
3149 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 3190 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
index a0ed220071f5..333a3470e842 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c
@@ -5097,6 +5097,7 @@ static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
5097#ifdef CONFIG_PINCTRL_PFC_R8A7745 5097#ifdef CONFIG_PINCTRL_PFC_R8A7745
5098const struct sh_pfc_soc_info r8a7745_pinmux_info = { 5098const struct sh_pfc_soc_info r8a7745_pinmux_info = {
5099 .name = "r8a77450_pfc", 5099 .name = "r8a77450_pfc",
5100 .ops = &r8a7794_pinmux_ops,
5100 .unlock_reg = 0xe6060000, /* PMMR */ 5101 .unlock_reg = 0xe6060000, /* PMMR */
5101 5102
5102 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 5103 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
index 95fd0994893a..1d4d84f34d60 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c
@@ -1443,12 +1443,13 @@ static const u16 pinmux_data[] = {
1443}; 1443};
1444 1444
1445/* 1445/*
1446 * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs. 1446 * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1447 * Physical layout rows: A - AW, cols: 1 - 39. 1447 * Physical layout rows: A - AW, cols: 1 - 39.
1448 */ 1448 */
1449#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) 1449#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1450#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) 1450#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1451#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) 1451#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1452#define PIN_NONE U16_MAX
1452 1453
1453static const struct sh_pfc_pin pinmux_pins[] = { 1454static const struct sh_pfc_pin pinmux_pins[] = {
1454 PINMUX_GPIO_GP_ALL(), 1455 PINMUX_GPIO_GP_ALL(),
@@ -3774,6 +3775,23 @@ static const unsigned int usb2_mux[] = {
3774 USB2_PWEN_MARK, USB2_OVC_MARK, 3775 USB2_PWEN_MARK, USB2_OVC_MARK,
3775}; 3776};
3776 3777
3778/* - USB30 ------------------------------------------------------------------ */
3779static const unsigned int usb30_pins[] = {
3780 /* PWEN, OVC */
3781 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3782};
3783static const unsigned int usb30_mux[] = {
3784 USB30_PWEN_MARK, USB30_OVC_MARK,
3785};
3786/* - USB31 ------------------------------------------------------------------ */
3787static const unsigned int usb31_pins[] = {
3788 /* PWEN, OVC */
3789 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3790};
3791static const unsigned int usb31_mux[] = {
3792 USB31_PWEN_MARK, USB31_OVC_MARK,
3793};
3794
3777static const struct sh_pfc_pin_group pinmux_groups[] = { 3795static const struct sh_pfc_pin_group pinmux_groups[] = {
3778 SH_PFC_PIN_GROUP(audio_clk_a_a), 3796 SH_PFC_PIN_GROUP(audio_clk_a_a),
3779 SH_PFC_PIN_GROUP(audio_clk_a_b), 3797 SH_PFC_PIN_GROUP(audio_clk_a_b),
@@ -4080,6 +4098,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
4080 SH_PFC_PIN_GROUP(usb0), 4098 SH_PFC_PIN_GROUP(usb0),
4081 SH_PFC_PIN_GROUP(usb1), 4099 SH_PFC_PIN_GROUP(usb1),
4082 SH_PFC_PIN_GROUP(usb2), 4100 SH_PFC_PIN_GROUP(usb2),
4101 SH_PFC_PIN_GROUP(usb30),
4102 SH_PFC_PIN_GROUP(usb31),
4083}; 4103};
4084 4104
4085static const char * const audio_clk_groups[] = { 4105static const char * const audio_clk_groups[] = {
@@ -4537,6 +4557,14 @@ static const char * const usb2_groups[] = {
4537 "usb2", 4557 "usb2",
4538}; 4558};
4539 4559
4560static const char * const usb30_groups[] = {
4561 "usb30",
4562};
4563
4564static const char * const usb31_groups[] = {
4565 "usb31",
4566};
4567
4540static const struct sh_pfc_function pinmux_functions[] = { 4568static const struct sh_pfc_function pinmux_functions[] = {
4541 SH_PFC_FUNCTION(audio_clk), 4569 SH_PFC_FUNCTION(audio_clk),
4542 SH_PFC_FUNCTION(avb), 4570 SH_PFC_FUNCTION(avb),
@@ -4588,6 +4616,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
4588 SH_PFC_FUNCTION(usb0), 4616 SH_PFC_FUNCTION(usb0),
4589 SH_PFC_FUNCTION(usb1), 4617 SH_PFC_FUNCTION(usb1),
4590 SH_PFC_FUNCTION(usb2), 4618 SH_PFC_FUNCTION(usb2),
4619 SH_PFC_FUNCTION(usb30),
4620 SH_PFC_FUNCTION(usb31),
4591}; 4621};
4592 4622
4593static const struct pinmux_cfg_reg pinmux_config_regs[] = { 4623static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -5393,12 +5423,21 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5393 { }, 5423 { },
5394}; 5424};
5395 5425
5426enum ioctrl_regs {
5427 POCCTRL,
5428};
5429
5430static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5431 [POCCTRL] = { 0xe6060380, },
5432 { /* sentinel */ },
5433};
5434
5396static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, 5435static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
5397 u32 *pocctrl) 5436 u32 *pocctrl)
5398{ 5437{
5399 int bit = -EINVAL; 5438 int bit = -EINVAL;
5400 5439
5401 *pocctrl = 0xe6060380; 5440 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5402 5441
5403 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) 5442 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5404 bit = pin & 0x1f; 5443 bit = pin & 0x1f;
@@ -5409,242 +5448,261 @@ static int r8a7795es1_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
5409 return bit; 5448 return bit;
5410} 5449}
5411 5450
5412#define PUEN 0xe6060400 5451static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5413#define PUD 0xe6060440 5452 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5414 5453 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5415#define PU0 0x00 5454 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5416#define PU1 0x04 5455 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5417#define PU2 0x08 5456 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5418#define PU3 0x0c 5457 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5419#define PU4 0x10 5458 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5420#define PU5 0x14 5459 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5421#define PU6 0x18 5460 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5422 5461 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5423static const struct sh_pfc_bias_info bias_info[] = { 5462 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5424 { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */ 5463 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5425 { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */ 5464 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5426 { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */ 5465 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5427 { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */ 5466 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5428 { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */ 5467 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5429 { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */ 5468 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5430 { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */ 5469 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5431 { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */ 5470 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5432 { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */ 5471 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5433 { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */ 5472 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5434 { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */ 5473 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5435 { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */ 5474 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5436 { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */ 5475 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5437 { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */ 5476 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5438 { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */ 5477 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5439 { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */ 5478 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5440 { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */ 5479 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5441 { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */ 5480 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5442 { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */ 5481 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5443 { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */ 5482 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5444 { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */ 5483 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5445 { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */ 5484 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5446 { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */ 5485 } },
5447 { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */ 5486 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5448 { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */ 5487 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5449 { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */ 5488 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5450 { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */ 5489 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5451 { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */ 5490 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5452 { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */ 5491 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5453 { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */ 5492 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5454 { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */ 5493 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5455 { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */ 5494 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5456 5495 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5457 { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */ 5496 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5458 { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */ 5497 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5459 { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */ 5498 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5460 { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */ 5499 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5461 { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */ 5500 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5462 { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */ 5501 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5463 { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */ 5502 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5464 { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */ 5503 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5465 { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */ 5504 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5466 { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */ 5505 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5467 { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */ 5506 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5468 { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */ 5507 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5469 { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */ 5508 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5470 { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */ 5509 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5471 { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */ 5510 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5472 { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */ 5511 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5473 { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */ 5512 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5474 { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */ 5513 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5475 { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */ 5514 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5476 { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */ 5515 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5477 { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */ 5516 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5478 { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */ 5517 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5479 { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */ 5518 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5480 { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */ 5519 } },
5481 { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */ 5520 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5482 { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */ 5521 [ 0] = PIN_NUMBER('F', 1), /* CLKOUT */
5483 { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */ 5522 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5484 { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */ 5523 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N_A26 */
5485 { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */ 5524 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5486 { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ 5525 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5487 { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */ 5526 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5488 { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */ 5527 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5489 5528 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5490 { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */ 5529 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5491 { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */ 5530 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
5492 { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */ 5531 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5493 { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */ 5532 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5494 { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */ 5533 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5495 { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */ 5534 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5496 { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */ 5535 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5497 { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */ 5536 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5498 { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */ 5537 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5499 { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */ 5538 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5500 { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */ 5539 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5501 { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */ 5540 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5502 { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */ 5541 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5503 { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */ 5542 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5504 { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */ 5543 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5505 { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */ 5544 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5506 { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */ 5545 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5507 { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */ 5546 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5508 { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */ 5547 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5509 { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */ 5548 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
5510 { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */ 5549 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
5511 { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */ 5550 [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */
5512 { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */ 5551 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
5513 { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */ 5552 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
5514 { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */ 5553 } },
5515 { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */ 5554 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5516 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ 5555 [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
5517 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ 5556 [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
5518 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ 5557 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
5519 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */ 5558 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
5520 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ 5559 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
5521 { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */ 5560 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
5522 5561 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
5523 { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */ 5562 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
5524 { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */ 5563 [ 8] = PIN_NONE,
5525 { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */ 5564 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
5526 { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */ 5565 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5527 { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */ 5566 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
5528 { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */ 5567 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
5529 { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */ 5568 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
5530 { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */ 5569 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
5531 { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */ 5570 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
5532 { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */ 5571 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
5533 { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */ 5572 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
5534 { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */ 5573 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
5535 { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */ 5574 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
5536 { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */ 5575 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
5537 { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */ 5576 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
5538 { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */ 5577 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
5539 { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */ 5578 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
5540 { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */ 5579 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
5541 { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */ 5580 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
5542 { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */ 5581 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
5543 { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */ 5582 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
5544 { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */ 5583 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
5545 { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */ 5584 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
5546 /* bit 8 n/a */ 5585 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
5547 { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */ 5586 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
5548 { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */ 5587 } },
5549 { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */ 5588 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5550 { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */ 5589 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
5551 { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/ 5590 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
5552 { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */ 5591 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
5553 { PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */ 5592 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
5554 { PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */ 5593 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
5555 5594 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
5556 { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */ 5595 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
5557 { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */ 5596 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
5558 { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */ 5597 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
5559 { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */ 5598 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
5560 { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */ 5599 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
5561 { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */ 5600 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
5562 { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */ 5601 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
5563 { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */ 5602 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
5564 { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */ 5603 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
5565 { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */ 5604 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
5566 { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */ 5605 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N_TANS */
5567 { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */ 5606 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
5568 { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */ 5607 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
5569 { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */ 5608 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
5570 { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */ 5609 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N_TANS */
5571 { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */ 5610 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
5572 { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */ 5611 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
5573 { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */ 5612 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
5574 { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */ 5613 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
5575 { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */ 5614 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
5576 { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */ 5615 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
5577 { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */ 5616 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
5578 { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */ 5617 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
5579 { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */ 5618 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
5580 { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */ 5619 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
5581 { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */ 5620 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
5582 { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */ 5621 } },
5583 { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */ 5622 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5584 { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */ 5623 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
5585 { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */ 5624 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
5586 { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */ 5625 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
5587 { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */ 5626 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
5588 5627 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
5589 { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */ 5628 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
5590 { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */ 5629 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
5591 { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */ 5630 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
5592 { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */ 5631 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
5593 { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */ 5632 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
5594 { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */ 5633 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
5595 { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */ 5634 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
5596 { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */ 5635 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
5597 { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */ 5636 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
5598 { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */ 5637 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
5599 { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */ 5638 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
5600 { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */ 5639 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
5601 { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */ 5640 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
5602 { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */ 5641 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
5603 { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */ 5642 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
5604 { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ 5643 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
5605 { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ 5644 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
5606 { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ 5645 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
5607 { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */ 5646 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
5608 { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */ 5647 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
5609 { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ 5648 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
5610 { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ 5649 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
5611 { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ 5650 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
5612 { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */ 5651 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
5613 { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */ 5652 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
5614 { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */ 5653 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
5615 { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */ 5654 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
5616 { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */ 5655 } },
5617 { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */ 5656 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
5618 { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */ 5657 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
5619 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ 5658 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
5620 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ 5659 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
5621 5660 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
5622 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB31_OVC */ 5661 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
5623 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB31_PWEN */ 5662 [ 5] = RCAR_GP_PIN(6, 30), /* USB31_PWEN */
5624 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ 5663 [ 6] = RCAR_GP_PIN(6, 31), /* USB31_OVC */
5625 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ 5664 [ 7] = PIN_NONE,
5626 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ 5665 [ 8] = PIN_NONE,
5627 { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */ 5666 [ 9] = PIN_NONE,
5628 { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */ 5667 [10] = PIN_NONE,
5668 [11] = PIN_NONE,
5669 [12] = PIN_NONE,
5670 [13] = PIN_NONE,
5671 [14] = PIN_NONE,
5672 [15] = PIN_NONE,
5673 [16] = PIN_NONE,
5674 [17] = PIN_NONE,
5675 [18] = PIN_NONE,
5676 [19] = PIN_NONE,
5677 [20] = PIN_NONE,
5678 [21] = PIN_NONE,
5679 [22] = PIN_NONE,
5680 [23] = PIN_NONE,
5681 [24] = PIN_NONE,
5682 [25] = PIN_NONE,
5683 [26] = PIN_NONE,
5684 [27] = PIN_NONE,
5685 [28] = PIN_NONE,
5686 [29] = PIN_NONE,
5687 [30] = PIN_NONE,
5688 [31] = PIN_NONE,
5689 } },
5690 { /* sentinel */ },
5629}; 5691};
5630 5692
5631static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc, 5693static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc,
5632 unsigned int pin) 5694 unsigned int pin)
5633{ 5695{
5634 const struct sh_pfc_bias_info *info; 5696 const struct pinmux_bias_reg *reg;
5635 u32 reg; 5697 unsigned int bit;
5636 u32 bit;
5637 5698
5638 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); 5699 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5639 if (!info) 5700 if (!reg)
5640 return PIN_CONFIG_BIAS_DISABLE; 5701 return PIN_CONFIG_BIAS_DISABLE;
5641 5702
5642 reg = info->reg; 5703 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
5643 bit = BIT(info->bit);
5644
5645 if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
5646 return PIN_CONFIG_BIAS_DISABLE; 5704 return PIN_CONFIG_BIAS_DISABLE;
5647 else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit) 5705 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
5648 return PIN_CONFIG_BIAS_PULL_UP; 5706 return PIN_CONFIG_BIAS_PULL_UP;
5649 else 5707 else
5650 return PIN_CONFIG_BIAS_PULL_DOWN; 5708 return PIN_CONFIG_BIAS_PULL_DOWN;
@@ -5653,28 +5711,24 @@ static unsigned int r8a7795es1_pinmux_get_bias(struct sh_pfc *pfc,
5653static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 5711static void r8a7795es1_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5654 unsigned int bias) 5712 unsigned int bias)
5655{ 5713{
5656 const struct sh_pfc_bias_info *info; 5714 const struct pinmux_bias_reg *reg;
5657 u32 enable, updown; 5715 u32 enable, updown;
5658 u32 reg; 5716 unsigned int bit;
5659 u32 bit;
5660 5717
5661 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); 5718 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5662 if (!info) 5719 if (!reg)
5663 return; 5720 return;
5664 5721
5665 reg = info->reg; 5722 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
5666 bit = BIT(info->bit);
5667
5668 enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
5669 if (bias != PIN_CONFIG_BIAS_DISABLE) 5723 if (bias != PIN_CONFIG_BIAS_DISABLE)
5670 enable |= bit; 5724 enable |= BIT(bit);
5671 5725
5672 updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit; 5726 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
5673 if (bias == PIN_CONFIG_BIAS_PULL_UP) 5727 if (bias == PIN_CONFIG_BIAS_PULL_UP)
5674 updown |= bit; 5728 updown |= BIT(bit);
5675 5729
5676 sh_pfc_write_reg(pfc, PUD + reg, 32, updown); 5730 sh_pfc_write(pfc, reg->pud, updown);
5677 sh_pfc_write_reg(pfc, PUEN + reg, 32, enable); 5731 sh_pfc_write(pfc, reg->puen, enable);
5678} 5732}
5679 5733
5680static const struct sh_pfc_soc_operations r8a7795es1_pinmux_ops = { 5734static const struct sh_pfc_soc_operations r8a7795es1_pinmux_ops = {
@@ -5699,6 +5753,8 @@ const struct sh_pfc_soc_info r8a7795es1_pinmux_info = {
5699 5753
5700 .cfg_regs = pinmux_config_regs, 5754 .cfg_regs = pinmux_config_regs,
5701 .drive_regs = pinmux_drive_regs, 5755 .drive_regs = pinmux_drive_regs,
5756 .bias_regs = pinmux_bias_regs,
5757 .ioctrl_regs = pinmux_ioctrl_regs,
5702 5758
5703 .pinmux_data = pinmux_data, 5759 .pinmux_data = pinmux_data,
5704 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 5760 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 8b35772cda98..d1cec6d12e81 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -1508,12 +1508,13 @@ static const u16 pinmux_data[] = {
1508}; 1508};
1509 1509
1510/* 1510/*
1511 * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs. 1511 * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1512 * Physical layout rows: A - AW, cols: 1 - 39. 1512 * Physical layout rows: A - AW, cols: 1 - 39.
1513 */ 1513 */
1514#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) 1514#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1515#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) 1515#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1516#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) 1516#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1517#define PIN_NONE U16_MAX
1517 1518
1518static const struct sh_pfc_pin pinmux_pins[] = { 1519static const struct sh_pfc_pin pinmux_pins[] = {
1519 PINMUX_GPIO_GP_ALL(), 1520 PINMUX_GPIO_GP_ALL(),
@@ -1572,6 +1573,127 @@ static const struct sh_pfc_pin pinmux_pins[] = {
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), 1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1573}; 1574};
1574 1575
1576/* - AUDIO CLOCK ------------------------------------------------------------ */
1577static const unsigned int audio_clk_a_a_pins[] = {
1578 /* CLK A */
1579 RCAR_GP_PIN(6, 22),
1580};
1581static const unsigned int audio_clk_a_a_mux[] = {
1582 AUDIO_CLKA_A_MARK,
1583};
1584static const unsigned int audio_clk_a_b_pins[] = {
1585 /* CLK A */
1586 RCAR_GP_PIN(5, 4),
1587};
1588static const unsigned int audio_clk_a_b_mux[] = {
1589 AUDIO_CLKA_B_MARK,
1590};
1591static const unsigned int audio_clk_a_c_pins[] = {
1592 /* CLK A */
1593 RCAR_GP_PIN(5, 19),
1594};
1595static const unsigned int audio_clk_a_c_mux[] = {
1596 AUDIO_CLKA_C_MARK,
1597};
1598static const unsigned int audio_clk_b_a_pins[] = {
1599 /* CLK B */
1600 RCAR_GP_PIN(5, 12),
1601};
1602static const unsigned int audio_clk_b_a_mux[] = {
1603 AUDIO_CLKB_A_MARK,
1604};
1605static const unsigned int audio_clk_b_b_pins[] = {
1606 /* CLK B */
1607 RCAR_GP_PIN(6, 23),
1608};
1609static const unsigned int audio_clk_b_b_mux[] = {
1610 AUDIO_CLKB_B_MARK,
1611};
1612static const unsigned int audio_clk_c_a_pins[] = {
1613 /* CLK C */
1614 RCAR_GP_PIN(5, 21),
1615};
1616static const unsigned int audio_clk_c_a_mux[] = {
1617 AUDIO_CLKC_A_MARK,
1618};
1619static const unsigned int audio_clk_c_b_pins[] = {
1620 /* CLK C */
1621 RCAR_GP_PIN(5, 0),
1622};
1623static const unsigned int audio_clk_c_b_mux[] = {
1624 AUDIO_CLKC_B_MARK,
1625};
1626static const unsigned int audio_clkout_a_pins[] = {
1627 /* CLKOUT */
1628 RCAR_GP_PIN(5, 18),
1629};
1630static const unsigned int audio_clkout_a_mux[] = {
1631 AUDIO_CLKOUT_A_MARK,
1632};
1633static const unsigned int audio_clkout_b_pins[] = {
1634 /* CLKOUT */
1635 RCAR_GP_PIN(6, 28),
1636};
1637static const unsigned int audio_clkout_b_mux[] = {
1638 AUDIO_CLKOUT_B_MARK,
1639};
1640static const unsigned int audio_clkout_c_pins[] = {
1641 /* CLKOUT */
1642 RCAR_GP_PIN(5, 3),
1643};
1644static const unsigned int audio_clkout_c_mux[] = {
1645 AUDIO_CLKOUT_C_MARK,
1646};
1647static const unsigned int audio_clkout_d_pins[] = {
1648 /* CLKOUT */
1649 RCAR_GP_PIN(5, 21),
1650};
1651static const unsigned int audio_clkout_d_mux[] = {
1652 AUDIO_CLKOUT_D_MARK,
1653};
1654static const unsigned int audio_clkout1_a_pins[] = {
1655 /* CLKOUT1 */
1656 RCAR_GP_PIN(5, 15),
1657};
1658static const unsigned int audio_clkout1_a_mux[] = {
1659 AUDIO_CLKOUT1_A_MARK,
1660};
1661static const unsigned int audio_clkout1_b_pins[] = {
1662 /* CLKOUT1 */
1663 RCAR_GP_PIN(6, 29),
1664};
1665static const unsigned int audio_clkout1_b_mux[] = {
1666 AUDIO_CLKOUT1_B_MARK,
1667};
1668static const unsigned int audio_clkout2_a_pins[] = {
1669 /* CLKOUT2 */
1670 RCAR_GP_PIN(5, 16),
1671};
1672static const unsigned int audio_clkout2_a_mux[] = {
1673 AUDIO_CLKOUT2_A_MARK,
1674};
1675static const unsigned int audio_clkout2_b_pins[] = {
1676 /* CLKOUT2 */
1677 RCAR_GP_PIN(6, 30),
1678};
1679static const unsigned int audio_clkout2_b_mux[] = {
1680 AUDIO_CLKOUT2_B_MARK,
1681};
1682static const unsigned int audio_clkout3_a_pins[] = {
1683 /* CLKOUT3 */
1684 RCAR_GP_PIN(5, 19),
1685};
1686static const unsigned int audio_clkout3_a_mux[] = {
1687 AUDIO_CLKOUT3_A_MARK,
1688};
1689static const unsigned int audio_clkout3_b_pins[] = {
1690 /* CLKOUT3 */
1691 RCAR_GP_PIN(6, 31),
1692};
1693static const unsigned int audio_clkout3_b_mux[] = {
1694 AUDIO_CLKOUT3_B_MARK,
1695};
1696
1575/* - EtherAVB --------------------------------------------------------------- */ 1697/* - EtherAVB --------------------------------------------------------------- */
1576static const unsigned int avb_link_pins[] = { 1698static const unsigned int avb_link_pins[] = {
1577 /* AVB_LINK */ 1699 /* AVB_LINK */
@@ -1659,6 +1781,221 @@ static const unsigned int avb_avtp_capture_b_mux[] = {
1659 AVB_AVTP_CAPTURE_B_MARK, 1781 AVB_AVTP_CAPTURE_B_MARK,
1660}; 1782};
1661 1783
1784/* - DRIF0 --------------------------------------------------------------- */
1785static const unsigned int drif0_ctrl_a_pins[] = {
1786 /* CLK, SYNC */
1787 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1788};
1789static const unsigned int drif0_ctrl_a_mux[] = {
1790 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1791};
1792static const unsigned int drif0_data0_a_pins[] = {
1793 /* D0 */
1794 RCAR_GP_PIN(6, 10),
1795};
1796static const unsigned int drif0_data0_a_mux[] = {
1797 RIF0_D0_A_MARK,
1798};
1799static const unsigned int drif0_data1_a_pins[] = {
1800 /* D1 */
1801 RCAR_GP_PIN(6, 7),
1802};
1803static const unsigned int drif0_data1_a_mux[] = {
1804 RIF0_D1_A_MARK,
1805};
1806static const unsigned int drif0_ctrl_b_pins[] = {
1807 /* CLK, SYNC */
1808 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1809};
1810static const unsigned int drif0_ctrl_b_mux[] = {
1811 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1812};
1813static const unsigned int drif0_data0_b_pins[] = {
1814 /* D0 */
1815 RCAR_GP_PIN(5, 1),
1816};
1817static const unsigned int drif0_data0_b_mux[] = {
1818 RIF0_D0_B_MARK,
1819};
1820static const unsigned int drif0_data1_b_pins[] = {
1821 /* D1 */
1822 RCAR_GP_PIN(5, 2),
1823};
1824static const unsigned int drif0_data1_b_mux[] = {
1825 RIF0_D1_B_MARK,
1826};
1827static const unsigned int drif0_ctrl_c_pins[] = {
1828 /* CLK, SYNC */
1829 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1830};
1831static const unsigned int drif0_ctrl_c_mux[] = {
1832 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1833};
1834static const unsigned int drif0_data0_c_pins[] = {
1835 /* D0 */
1836 RCAR_GP_PIN(5, 13),
1837};
1838static const unsigned int drif0_data0_c_mux[] = {
1839 RIF0_D0_C_MARK,
1840};
1841static const unsigned int drif0_data1_c_pins[] = {
1842 /* D1 */
1843 RCAR_GP_PIN(5, 14),
1844};
1845static const unsigned int drif0_data1_c_mux[] = {
1846 RIF0_D1_C_MARK,
1847};
1848/* - DRIF1 --------------------------------------------------------------- */
1849static const unsigned int drif1_ctrl_a_pins[] = {
1850 /* CLK, SYNC */
1851 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1852};
1853static const unsigned int drif1_ctrl_a_mux[] = {
1854 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1855};
1856static const unsigned int drif1_data0_a_pins[] = {
1857 /* D0 */
1858 RCAR_GP_PIN(6, 19),
1859};
1860static const unsigned int drif1_data0_a_mux[] = {
1861 RIF1_D0_A_MARK,
1862};
1863static const unsigned int drif1_data1_a_pins[] = {
1864 /* D1 */
1865 RCAR_GP_PIN(6, 20),
1866};
1867static const unsigned int drif1_data1_a_mux[] = {
1868 RIF1_D1_A_MARK,
1869};
1870static const unsigned int drif1_ctrl_b_pins[] = {
1871 /* CLK, SYNC */
1872 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1873};
1874static const unsigned int drif1_ctrl_b_mux[] = {
1875 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1876};
1877static const unsigned int drif1_data0_b_pins[] = {
1878 /* D0 */
1879 RCAR_GP_PIN(5, 7),
1880};
1881static const unsigned int drif1_data0_b_mux[] = {
1882 RIF1_D0_B_MARK,
1883};
1884static const unsigned int drif1_data1_b_pins[] = {
1885 /* D1 */
1886 RCAR_GP_PIN(5, 8),
1887};
1888static const unsigned int drif1_data1_b_mux[] = {
1889 RIF1_D1_B_MARK,
1890};
1891static const unsigned int drif1_ctrl_c_pins[] = {
1892 /* CLK, SYNC */
1893 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1894};
1895static const unsigned int drif1_ctrl_c_mux[] = {
1896 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1897};
1898static const unsigned int drif1_data0_c_pins[] = {
1899 /* D0 */
1900 RCAR_GP_PIN(5, 6),
1901};
1902static const unsigned int drif1_data0_c_mux[] = {
1903 RIF1_D0_C_MARK,
1904};
1905static const unsigned int drif1_data1_c_pins[] = {
1906 /* D1 */
1907 RCAR_GP_PIN(5, 10),
1908};
1909static const unsigned int drif1_data1_c_mux[] = {
1910 RIF1_D1_C_MARK,
1911};
1912/* - DRIF2 --------------------------------------------------------------- */
1913static const unsigned int drif2_ctrl_a_pins[] = {
1914 /* CLK, SYNC */
1915 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1916};
1917static const unsigned int drif2_ctrl_a_mux[] = {
1918 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1919};
1920static const unsigned int drif2_data0_a_pins[] = {
1921 /* D0 */
1922 RCAR_GP_PIN(6, 7),
1923};
1924static const unsigned int drif2_data0_a_mux[] = {
1925 RIF2_D0_A_MARK,
1926};
1927static const unsigned int drif2_data1_a_pins[] = {
1928 /* D1 */
1929 RCAR_GP_PIN(6, 10),
1930};
1931static const unsigned int drif2_data1_a_mux[] = {
1932 RIF2_D1_A_MARK,
1933};
1934static const unsigned int drif2_ctrl_b_pins[] = {
1935 /* CLK, SYNC */
1936 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1937};
1938static const unsigned int drif2_ctrl_b_mux[] = {
1939 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1940};
1941static const unsigned int drif2_data0_b_pins[] = {
1942 /* D0 */
1943 RCAR_GP_PIN(6, 30),
1944};
1945static const unsigned int drif2_data0_b_mux[] = {
1946 RIF2_D0_B_MARK,
1947};
1948static const unsigned int drif2_data1_b_pins[] = {
1949 /* D1 */
1950 RCAR_GP_PIN(6, 31),
1951};
1952static const unsigned int drif2_data1_b_mux[] = {
1953 RIF2_D1_B_MARK,
1954};
1955/* - DRIF3 --------------------------------------------------------------- */
1956static const unsigned int drif3_ctrl_a_pins[] = {
1957 /* CLK, SYNC */
1958 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1959};
1960static const unsigned int drif3_ctrl_a_mux[] = {
1961 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1962};
1963static const unsigned int drif3_data0_a_pins[] = {
1964 /* D0 */
1965 RCAR_GP_PIN(6, 19),
1966};
1967static const unsigned int drif3_data0_a_mux[] = {
1968 RIF3_D0_A_MARK,
1969};
1970static const unsigned int drif3_data1_a_pins[] = {
1971 /* D1 */
1972 RCAR_GP_PIN(6, 20),
1973};
1974static const unsigned int drif3_data1_a_mux[] = {
1975 RIF3_D1_A_MARK,
1976};
1977static const unsigned int drif3_ctrl_b_pins[] = {
1978 /* CLK, SYNC */
1979 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1980};
1981static const unsigned int drif3_ctrl_b_mux[] = {
1982 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1983};
1984static const unsigned int drif3_data0_b_pins[] = {
1985 /* D0 */
1986 RCAR_GP_PIN(6, 28),
1987};
1988static const unsigned int drif3_data0_b_mux[] = {
1989 RIF3_D0_B_MARK,
1990};
1991static const unsigned int drif3_data1_b_pins[] = {
1992 /* D1 */
1993 RCAR_GP_PIN(6, 29),
1994};
1995static const unsigned int drif3_data1_b_mux[] = {
1996 RIF3_D1_B_MARK,
1997};
1998
1662/* - DU --------------------------------------------------------------------- */ 1999/* - DU --------------------------------------------------------------------- */
1663static const unsigned int du_rgb666_pins[] = { 2000static const unsigned int du_rgb666_pins[] = {
1664 /* R[7:2], G[7:2], B[7:2] */ 2001 /* R[7:2], G[7:2], B[7:2] */
@@ -1740,6 +2077,308 @@ static const unsigned int du_disp_mux[] = {
1740 DU_DISP_MARK, 2077 DU_DISP_MARK,
1741}; 2078};
1742 2079
2080/* - HSCIF0 ----------------------------------------------------------------- */
2081static const unsigned int hscif0_data_pins[] = {
2082 /* RX, TX */
2083 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2084};
2085static const unsigned int hscif0_data_mux[] = {
2086 HRX0_MARK, HTX0_MARK,
2087};
2088static const unsigned int hscif0_clk_pins[] = {
2089 /* SCK */
2090 RCAR_GP_PIN(5, 12),
2091};
2092static const unsigned int hscif0_clk_mux[] = {
2093 HSCK0_MARK,
2094};
2095static const unsigned int hscif0_ctrl_pins[] = {
2096 /* RTS, CTS */
2097 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2098};
2099static const unsigned int hscif0_ctrl_mux[] = {
2100 HRTS0_N_MARK, HCTS0_N_MARK,
2101};
2102/* - HSCIF1 ----------------------------------------------------------------- */
2103static const unsigned int hscif1_data_a_pins[] = {
2104 /* RX, TX */
2105 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2106};
2107static const unsigned int hscif1_data_a_mux[] = {
2108 HRX1_A_MARK, HTX1_A_MARK,
2109};
2110static const unsigned int hscif1_clk_a_pins[] = {
2111 /* SCK */
2112 RCAR_GP_PIN(6, 21),
2113};
2114static const unsigned int hscif1_clk_a_mux[] = {
2115 HSCK1_A_MARK,
2116};
2117static const unsigned int hscif1_ctrl_a_pins[] = {
2118 /* RTS, CTS */
2119 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2120};
2121static const unsigned int hscif1_ctrl_a_mux[] = {
2122 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2123};
2124
2125static const unsigned int hscif1_data_b_pins[] = {
2126 /* RX, TX */
2127 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2128};
2129static const unsigned int hscif1_data_b_mux[] = {
2130 HRX1_B_MARK, HTX1_B_MARK,
2131};
2132static const unsigned int hscif1_clk_b_pins[] = {
2133 /* SCK */
2134 RCAR_GP_PIN(5, 0),
2135};
2136static const unsigned int hscif1_clk_b_mux[] = {
2137 HSCK1_B_MARK,
2138};
2139static const unsigned int hscif1_ctrl_b_pins[] = {
2140 /* RTS, CTS */
2141 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2142};
2143static const unsigned int hscif1_ctrl_b_mux[] = {
2144 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2145};
2146/* - HSCIF2 ----------------------------------------------------------------- */
2147static const unsigned int hscif2_data_a_pins[] = {
2148 /* RX, TX */
2149 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2150};
2151static const unsigned int hscif2_data_a_mux[] = {
2152 HRX2_A_MARK, HTX2_A_MARK,
2153};
2154static const unsigned int hscif2_clk_a_pins[] = {
2155 /* SCK */
2156 RCAR_GP_PIN(6, 10),
2157};
2158static const unsigned int hscif2_clk_a_mux[] = {
2159 HSCK2_A_MARK,
2160};
2161static const unsigned int hscif2_ctrl_a_pins[] = {
2162 /* RTS, CTS */
2163 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2164};
2165static const unsigned int hscif2_ctrl_a_mux[] = {
2166 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2167};
2168
2169static const unsigned int hscif2_data_b_pins[] = {
2170 /* RX, TX */
2171 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2172};
2173static const unsigned int hscif2_data_b_mux[] = {
2174 HRX2_B_MARK, HTX2_B_MARK,
2175};
2176static const unsigned int hscif2_clk_b_pins[] = {
2177 /* SCK */
2178 RCAR_GP_PIN(6, 21),
2179};
2180static const unsigned int hscif2_clk_b_mux[] = {
2181 HSCK2_B_MARK,
2182};
2183static const unsigned int hscif2_ctrl_b_pins[] = {
2184 /* RTS, CTS */
2185 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2186};
2187static const unsigned int hscif2_ctrl_b_mux[] = {
2188 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2189};
2190
2191static const unsigned int hscif2_data_c_pins[] = {
2192 /* RX, TX */
2193 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2194};
2195static const unsigned int hscif2_data_c_mux[] = {
2196 HRX2_C_MARK, HTX2_C_MARK,
2197};
2198static const unsigned int hscif2_clk_c_pins[] = {
2199 /* SCK */
2200 RCAR_GP_PIN(6, 24),
2201};
2202static const unsigned int hscif2_clk_c_mux[] = {
2203 HSCK2_C_MARK,
2204};
2205static const unsigned int hscif2_ctrl_c_pins[] = {
2206 /* RTS, CTS */
2207 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2208};
2209static const unsigned int hscif2_ctrl_c_mux[] = {
2210 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2211};
2212/* - HSCIF3 ----------------------------------------------------------------- */
2213static const unsigned int hscif3_data_a_pins[] = {
2214 /* RX, TX */
2215 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2216};
2217static const unsigned int hscif3_data_a_mux[] = {
2218 HRX3_A_MARK, HTX3_A_MARK,
2219};
2220static const unsigned int hscif3_clk_pins[] = {
2221 /* SCK */
2222 RCAR_GP_PIN(1, 22),
2223};
2224static const unsigned int hscif3_clk_mux[] = {
2225 HSCK3_MARK,
2226};
2227static const unsigned int hscif3_ctrl_pins[] = {
2228 /* RTS, CTS */
2229 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2230};
2231static const unsigned int hscif3_ctrl_mux[] = {
2232 HRTS3_N_MARK, HCTS3_N_MARK,
2233};
2234
2235static const unsigned int hscif3_data_b_pins[] = {
2236 /* RX, TX */
2237 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2238};
2239static const unsigned int hscif3_data_b_mux[] = {
2240 HRX3_B_MARK, HTX3_B_MARK,
2241};
2242static const unsigned int hscif3_data_c_pins[] = {
2243 /* RX, TX */
2244 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2245};
2246static const unsigned int hscif3_data_c_mux[] = {
2247 HRX3_C_MARK, HTX3_C_MARK,
2248};
2249static const unsigned int hscif3_data_d_pins[] = {
2250 /* RX, TX */
2251 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2252};
2253static const unsigned int hscif3_data_d_mux[] = {
2254 HRX3_D_MARK, HTX3_D_MARK,
2255};
2256/* - HSCIF4 ----------------------------------------------------------------- */
2257static const unsigned int hscif4_data_a_pins[] = {
2258 /* RX, TX */
2259 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2260};
2261static const unsigned int hscif4_data_a_mux[] = {
2262 HRX4_A_MARK, HTX4_A_MARK,
2263};
2264static const unsigned int hscif4_clk_pins[] = {
2265 /* SCK */
2266 RCAR_GP_PIN(1, 11),
2267};
2268static const unsigned int hscif4_clk_mux[] = {
2269 HSCK4_MARK,
2270};
2271static const unsigned int hscif4_ctrl_pins[] = {
2272 /* RTS, CTS */
2273 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2274};
2275static const unsigned int hscif4_ctrl_mux[] = {
2276 HRTS4_N_MARK, HCTS4_N_MARK,
2277};
2278
2279static const unsigned int hscif4_data_b_pins[] = {
2280 /* RX, TX */
2281 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2282};
2283static const unsigned int hscif4_data_b_mux[] = {
2284 HRX4_B_MARK, HTX4_B_MARK,
2285};
2286
2287/* - I2C -------------------------------------------------------------------- */
2288static const unsigned int i2c1_a_pins[] = {
2289 /* SDA, SCL */
2290 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2291};
2292static const unsigned int i2c1_a_mux[] = {
2293 SDA1_A_MARK, SCL1_A_MARK,
2294};
2295static const unsigned int i2c1_b_pins[] = {
2296 /* SDA, SCL */
2297 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2298};
2299static const unsigned int i2c1_b_mux[] = {
2300 SDA1_B_MARK, SCL1_B_MARK,
2301};
2302static const unsigned int i2c2_a_pins[] = {
2303 /* SDA, SCL */
2304 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2305};
2306static const unsigned int i2c2_a_mux[] = {
2307 SDA2_A_MARK, SCL2_A_MARK,
2308};
2309static const unsigned int i2c2_b_pins[] = {
2310 /* SDA, SCL */
2311 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2312};
2313static const unsigned int i2c2_b_mux[] = {
2314 SDA2_B_MARK, SCL2_B_MARK,
2315};
2316static const unsigned int i2c6_a_pins[] = {
2317 /* SDA, SCL */
2318 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2319};
2320static const unsigned int i2c6_a_mux[] = {
2321 SDA6_A_MARK, SCL6_A_MARK,
2322};
2323static const unsigned int i2c6_b_pins[] = {
2324 /* SDA, SCL */
2325 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2326};
2327static const unsigned int i2c6_b_mux[] = {
2328 SDA6_B_MARK, SCL6_B_MARK,
2329};
2330static const unsigned int i2c6_c_pins[] = {
2331 /* SDA, SCL */
2332 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2333};
2334static const unsigned int i2c6_c_mux[] = {
2335 SDA6_C_MARK, SCL6_C_MARK,
2336};
2337
2338/* - INTC-EX ---------------------------------------------------------------- */
2339static const unsigned int intc_ex_irq0_pins[] = {
2340 /* IRQ0 */
2341 RCAR_GP_PIN(2, 0),
2342};
2343static const unsigned int intc_ex_irq0_mux[] = {
2344 IRQ0_MARK,
2345};
2346static const unsigned int intc_ex_irq1_pins[] = {
2347 /* IRQ1 */
2348 RCAR_GP_PIN(2, 1),
2349};
2350static const unsigned int intc_ex_irq1_mux[] = {
2351 IRQ1_MARK,
2352};
2353static const unsigned int intc_ex_irq2_pins[] = {
2354 /* IRQ2 */
2355 RCAR_GP_PIN(2, 2),
2356};
2357static const unsigned int intc_ex_irq2_mux[] = {
2358 IRQ2_MARK,
2359};
2360static const unsigned int intc_ex_irq3_pins[] = {
2361 /* IRQ3 */
2362 RCAR_GP_PIN(2, 3),
2363};
2364static const unsigned int intc_ex_irq3_mux[] = {
2365 IRQ3_MARK,
2366};
2367static const unsigned int intc_ex_irq4_pins[] = {
2368 /* IRQ4 */
2369 RCAR_GP_PIN(2, 4),
2370};
2371static const unsigned int intc_ex_irq4_mux[] = {
2372 IRQ4_MARK,
2373};
2374static const unsigned int intc_ex_irq5_pins[] = {
2375 /* IRQ5 */
2376 RCAR_GP_PIN(2, 5),
2377};
2378static const unsigned int intc_ex_irq5_mux[] = {
2379 IRQ5_MARK,
2380};
2381
1743/* - MSIOF0 ----------------------------------------------------------------- */ 2382/* - MSIOF0 ----------------------------------------------------------------- */
1744static const unsigned int msiof0_clk_pins[] = { 2383static const unsigned int msiof0_clk_pins[] = {
1745 /* SCK */ 2384 /* SCK */
@@ -2750,6 +3389,390 @@ static const unsigned int scif_clk_b_mux[] = {
2750 SCIF_CLK_B_MARK, 3389 SCIF_CLK_B_MARK,
2751}; 3390};
2752 3391
3392/* - SDHI0 ------------------------------------------------------------------ */
3393static const unsigned int sdhi0_data1_pins[] = {
3394 /* D0 */
3395 RCAR_GP_PIN(3, 2),
3396};
3397static const unsigned int sdhi0_data1_mux[] = {
3398 SD0_DAT0_MARK,
3399};
3400static const unsigned int sdhi0_data4_pins[] = {
3401 /* D[0:3] */
3402 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3403 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3404};
3405static const unsigned int sdhi0_data4_mux[] = {
3406 SD0_DAT0_MARK, SD0_DAT1_MARK,
3407 SD0_DAT2_MARK, SD0_DAT3_MARK,
3408};
3409static const unsigned int sdhi0_ctrl_pins[] = {
3410 /* CLK, CMD */
3411 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3412};
3413static const unsigned int sdhi0_ctrl_mux[] = {
3414 SD0_CLK_MARK, SD0_CMD_MARK,
3415};
3416static const unsigned int sdhi0_cd_pins[] = {
3417 /* CD */
3418 RCAR_GP_PIN(3, 12),
3419};
3420static const unsigned int sdhi0_cd_mux[] = {
3421 SD0_CD_MARK,
3422};
3423static const unsigned int sdhi0_wp_pins[] = {
3424 /* WP */
3425 RCAR_GP_PIN(3, 13),
3426};
3427static const unsigned int sdhi0_wp_mux[] = {
3428 SD0_WP_MARK,
3429};
3430/* - SDHI1 ------------------------------------------------------------------ */
3431static const unsigned int sdhi1_data1_pins[] = {
3432 /* D0 */
3433 RCAR_GP_PIN(3, 8),
3434};
3435static const unsigned int sdhi1_data1_mux[] = {
3436 SD1_DAT0_MARK,
3437};
3438static const unsigned int sdhi1_data4_pins[] = {
3439 /* D[0:3] */
3440 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3441 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3442};
3443static const unsigned int sdhi1_data4_mux[] = {
3444 SD1_DAT0_MARK, SD1_DAT1_MARK,
3445 SD1_DAT2_MARK, SD1_DAT3_MARK,
3446};
3447static const unsigned int sdhi1_ctrl_pins[] = {
3448 /* CLK, CMD */
3449 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3450};
3451static const unsigned int sdhi1_ctrl_mux[] = {
3452 SD1_CLK_MARK, SD1_CMD_MARK,
3453};
3454static const unsigned int sdhi1_cd_pins[] = {
3455 /* CD */
3456 RCAR_GP_PIN(3, 14),
3457};
3458static const unsigned int sdhi1_cd_mux[] = {
3459 SD1_CD_MARK,
3460};
3461static const unsigned int sdhi1_wp_pins[] = {
3462 /* WP */
3463 RCAR_GP_PIN(3, 15),
3464};
3465static const unsigned int sdhi1_wp_mux[] = {
3466 SD1_WP_MARK,
3467};
3468/* - SDHI2 ------------------------------------------------------------------ */
3469static const unsigned int sdhi2_data1_pins[] = {
3470 /* D0 */
3471 RCAR_GP_PIN(4, 2),
3472};
3473static const unsigned int sdhi2_data1_mux[] = {
3474 SD2_DAT0_MARK,
3475};
3476static const unsigned int sdhi2_data4_pins[] = {
3477 /* D[0:3] */
3478 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3479 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3480};
3481static const unsigned int sdhi2_data4_mux[] = {
3482 SD2_DAT0_MARK, SD2_DAT1_MARK,
3483 SD2_DAT2_MARK, SD2_DAT3_MARK,
3484};
3485static const unsigned int sdhi2_data8_pins[] = {
3486 /* D[0:7] */
3487 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3488 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3489 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3490 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3491};
3492static const unsigned int sdhi2_data8_mux[] = {
3493 SD2_DAT0_MARK, SD2_DAT1_MARK,
3494 SD2_DAT2_MARK, SD2_DAT3_MARK,
3495 SD2_DAT4_MARK, SD2_DAT5_MARK,
3496 SD2_DAT6_MARK, SD2_DAT7_MARK,
3497};
3498static const unsigned int sdhi2_ctrl_pins[] = {
3499 /* CLK, CMD */
3500 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3501};
3502static const unsigned int sdhi2_ctrl_mux[] = {
3503 SD2_CLK_MARK, SD2_CMD_MARK,
3504};
3505static const unsigned int sdhi2_cd_a_pins[] = {
3506 /* CD */
3507 RCAR_GP_PIN(4, 13),
3508};
3509static const unsigned int sdhi2_cd_a_mux[] = {
3510 SD2_CD_A_MARK,
3511};
3512static const unsigned int sdhi2_cd_b_pins[] = {
3513 /* CD */
3514 RCAR_GP_PIN(5, 10),
3515};
3516static const unsigned int sdhi2_cd_b_mux[] = {
3517 SD2_CD_B_MARK,
3518};
3519static const unsigned int sdhi2_wp_a_pins[] = {
3520 /* WP */
3521 RCAR_GP_PIN(4, 14),
3522};
3523static const unsigned int sdhi2_wp_a_mux[] = {
3524 SD2_WP_A_MARK,
3525};
3526static const unsigned int sdhi2_wp_b_pins[] = {
3527 /* WP */
3528 RCAR_GP_PIN(5, 11),
3529};
3530static const unsigned int sdhi2_wp_b_mux[] = {
3531 SD2_WP_B_MARK,
3532};
3533static const unsigned int sdhi2_ds_pins[] = {
3534 /* DS */
3535 RCAR_GP_PIN(4, 6),
3536};
3537static const unsigned int sdhi2_ds_mux[] = {
3538 SD2_DS_MARK,
3539};
3540/* - SDHI3 ------------------------------------------------------------------ */
3541static const unsigned int sdhi3_data1_pins[] = {
3542 /* D0 */
3543 RCAR_GP_PIN(4, 9),
3544};
3545static const unsigned int sdhi3_data1_mux[] = {
3546 SD3_DAT0_MARK,
3547};
3548static const unsigned int sdhi3_data4_pins[] = {
3549 /* D[0:3] */
3550 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3551 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3552};
3553static const unsigned int sdhi3_data4_mux[] = {
3554 SD3_DAT0_MARK, SD3_DAT1_MARK,
3555 SD3_DAT2_MARK, SD3_DAT3_MARK,
3556};
3557static const unsigned int sdhi3_data8_pins[] = {
3558 /* D[0:7] */
3559 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3560 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3561 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3562 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3563};
3564static const unsigned int sdhi3_data8_mux[] = {
3565 SD3_DAT0_MARK, SD3_DAT1_MARK,
3566 SD3_DAT2_MARK, SD3_DAT3_MARK,
3567 SD3_DAT4_MARK, SD3_DAT5_MARK,
3568 SD3_DAT6_MARK, SD3_DAT7_MARK,
3569};
3570static const unsigned int sdhi3_ctrl_pins[] = {
3571 /* CLK, CMD */
3572 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3573};
3574static const unsigned int sdhi3_ctrl_mux[] = {
3575 SD3_CLK_MARK, SD3_CMD_MARK,
3576};
3577static const unsigned int sdhi3_cd_pins[] = {
3578 /* CD */
3579 RCAR_GP_PIN(4, 15),
3580};
3581static const unsigned int sdhi3_cd_mux[] = {
3582 SD3_CD_MARK,
3583};
3584static const unsigned int sdhi3_wp_pins[] = {
3585 /* WP */
3586 RCAR_GP_PIN(4, 16),
3587};
3588static const unsigned int sdhi3_wp_mux[] = {
3589 SD3_WP_MARK,
3590};
3591static const unsigned int sdhi3_ds_pins[] = {
3592 /* DS */
3593 RCAR_GP_PIN(4, 17),
3594};
3595static const unsigned int sdhi3_ds_mux[] = {
3596 SD3_DS_MARK,
3597};
3598
3599/* - SSI -------------------------------------------------------------------- */
3600static const unsigned int ssi0_data_pins[] = {
3601 /* SDATA */
3602 RCAR_GP_PIN(6, 2),
3603};
3604static const unsigned int ssi0_data_mux[] = {
3605 SSI_SDATA0_MARK,
3606};
3607static const unsigned int ssi01239_ctrl_pins[] = {
3608 /* SCK, WS */
3609 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3610};
3611static const unsigned int ssi01239_ctrl_mux[] = {
3612 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3613};
3614static const unsigned int ssi1_data_a_pins[] = {
3615 /* SDATA */
3616 RCAR_GP_PIN(6, 3),
3617};
3618static const unsigned int ssi1_data_a_mux[] = {
3619 SSI_SDATA1_A_MARK,
3620};
3621static const unsigned int ssi1_data_b_pins[] = {
3622 /* SDATA */
3623 RCAR_GP_PIN(5, 12),
3624};
3625static const unsigned int ssi1_data_b_mux[] = {
3626 SSI_SDATA1_B_MARK,
3627};
3628static const unsigned int ssi1_ctrl_a_pins[] = {
3629 /* SCK, WS */
3630 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3631};
3632static const unsigned int ssi1_ctrl_a_mux[] = {
3633 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3634};
3635static const unsigned int ssi1_ctrl_b_pins[] = {
3636 /* SCK, WS */
3637 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3638};
3639static const unsigned int ssi1_ctrl_b_mux[] = {
3640 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3641};
3642static const unsigned int ssi2_data_a_pins[] = {
3643 /* SDATA */
3644 RCAR_GP_PIN(6, 4),
3645};
3646static const unsigned int ssi2_data_a_mux[] = {
3647 SSI_SDATA2_A_MARK,
3648};
3649static const unsigned int ssi2_data_b_pins[] = {
3650 /* SDATA */
3651 RCAR_GP_PIN(5, 13),
3652};
3653static const unsigned int ssi2_data_b_mux[] = {
3654 SSI_SDATA2_B_MARK,
3655};
3656static const unsigned int ssi2_ctrl_a_pins[] = {
3657 /* SCK, WS */
3658 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3659};
3660static const unsigned int ssi2_ctrl_a_mux[] = {
3661 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3662};
3663static const unsigned int ssi2_ctrl_b_pins[] = {
3664 /* SCK, WS */
3665 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3666};
3667static const unsigned int ssi2_ctrl_b_mux[] = {
3668 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3669};
3670static const unsigned int ssi3_data_pins[] = {
3671 /* SDATA */
3672 RCAR_GP_PIN(6, 7),
3673};
3674static const unsigned int ssi3_data_mux[] = {
3675 SSI_SDATA3_MARK,
3676};
3677static const unsigned int ssi349_ctrl_pins[] = {
3678 /* SCK, WS */
3679 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3680};
3681static const unsigned int ssi349_ctrl_mux[] = {
3682 SSI_SCK349_MARK, SSI_WS349_MARK,
3683};
3684static const unsigned int ssi4_data_pins[] = {
3685 /* SDATA */
3686 RCAR_GP_PIN(6, 10),
3687};
3688static const unsigned int ssi4_data_mux[] = {
3689 SSI_SDATA4_MARK,
3690};
3691static const unsigned int ssi4_ctrl_pins[] = {
3692 /* SCK, WS */
3693 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3694};
3695static const unsigned int ssi4_ctrl_mux[] = {
3696 SSI_SCK4_MARK, SSI_WS4_MARK,
3697};
3698static const unsigned int ssi5_data_pins[] = {
3699 /* SDATA */
3700 RCAR_GP_PIN(6, 13),
3701};
3702static const unsigned int ssi5_data_mux[] = {
3703 SSI_SDATA5_MARK,
3704};
3705static const unsigned int ssi5_ctrl_pins[] = {
3706 /* SCK, WS */
3707 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3708};
3709static const unsigned int ssi5_ctrl_mux[] = {
3710 SSI_SCK5_MARK, SSI_WS5_MARK,
3711};
3712static const unsigned int ssi6_data_pins[] = {
3713 /* SDATA */
3714 RCAR_GP_PIN(6, 16),
3715};
3716static const unsigned int ssi6_data_mux[] = {
3717 SSI_SDATA6_MARK,
3718};
3719static const unsigned int ssi6_ctrl_pins[] = {
3720 /* SCK, WS */
3721 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3722};
3723static const unsigned int ssi6_ctrl_mux[] = {
3724 SSI_SCK6_MARK, SSI_WS6_MARK,
3725};
3726static const unsigned int ssi7_data_pins[] = {
3727 /* SDATA */
3728 RCAR_GP_PIN(6, 19),
3729};
3730static const unsigned int ssi7_data_mux[] = {
3731 SSI_SDATA7_MARK,
3732};
3733static const unsigned int ssi78_ctrl_pins[] = {
3734 /* SCK, WS */
3735 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3736};
3737static const unsigned int ssi78_ctrl_mux[] = {
3738 SSI_SCK78_MARK, SSI_WS78_MARK,
3739};
3740static const unsigned int ssi8_data_pins[] = {
3741 /* SDATA */
3742 RCAR_GP_PIN(6, 20),
3743};
3744static const unsigned int ssi8_data_mux[] = {
3745 SSI_SDATA8_MARK,
3746};
3747static const unsigned int ssi9_data_a_pins[] = {
3748 /* SDATA */
3749 RCAR_GP_PIN(6, 21),
3750};
3751static const unsigned int ssi9_data_a_mux[] = {
3752 SSI_SDATA9_A_MARK,
3753};
3754static const unsigned int ssi9_data_b_pins[] = {
3755 /* SDATA */
3756 RCAR_GP_PIN(5, 14),
3757};
3758static const unsigned int ssi9_data_b_mux[] = {
3759 SSI_SDATA9_B_MARK,
3760};
3761static const unsigned int ssi9_ctrl_a_pins[] = {
3762 /* SCK, WS */
3763 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3764};
3765static const unsigned int ssi9_ctrl_a_mux[] = {
3766 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3767};
3768static const unsigned int ssi9_ctrl_b_pins[] = {
3769 /* SCK, WS */
3770 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3771};
3772static const unsigned int ssi9_ctrl_b_mux[] = {
3773 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3774};
3775
2753/* - USB0 ------------------------------------------------------------------- */ 3776/* - USB0 ------------------------------------------------------------------- */
2754static const unsigned int usb0_pins[] = { 3777static const unsigned int usb0_pins[] = {
2755 /* PWEN, OVC */ 3778 /* PWEN, OVC */
@@ -2783,7 +3806,33 @@ static const unsigned int usb2_ch3_mux[] = {
2783 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK, 3806 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
2784}; 3807};
2785 3808
3809/* - USB30 ------------------------------------------------------------------ */
3810static const unsigned int usb30_pins[] = {
3811 /* PWEN, OVC */
3812 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3813};
3814static const unsigned int usb30_mux[] = {
3815 USB30_PWEN_MARK, USB30_OVC_MARK,
3816};
3817
2786static const struct sh_pfc_pin_group pinmux_groups[] = { 3818static const struct sh_pfc_pin_group pinmux_groups[] = {
3819 SH_PFC_PIN_GROUP(audio_clk_a_a),
3820 SH_PFC_PIN_GROUP(audio_clk_a_b),
3821 SH_PFC_PIN_GROUP(audio_clk_a_c),
3822 SH_PFC_PIN_GROUP(audio_clk_b_a),
3823 SH_PFC_PIN_GROUP(audio_clk_b_b),
3824 SH_PFC_PIN_GROUP(audio_clk_c_a),
3825 SH_PFC_PIN_GROUP(audio_clk_c_b),
3826 SH_PFC_PIN_GROUP(audio_clkout_a),
3827 SH_PFC_PIN_GROUP(audio_clkout_b),
3828 SH_PFC_PIN_GROUP(audio_clkout_c),
3829 SH_PFC_PIN_GROUP(audio_clkout_d),
3830 SH_PFC_PIN_GROUP(audio_clkout1_a),
3831 SH_PFC_PIN_GROUP(audio_clkout1_b),
3832 SH_PFC_PIN_GROUP(audio_clkout2_a),
3833 SH_PFC_PIN_GROUP(audio_clkout2_b),
3834 SH_PFC_PIN_GROUP(audio_clkout3_a),
3835 SH_PFC_PIN_GROUP(audio_clkout3_b),
2787 SH_PFC_PIN_GROUP(avb_link), 3836 SH_PFC_PIN_GROUP(avb_link),
2788 SH_PFC_PIN_GROUP(avb_magic), 3837 SH_PFC_PIN_GROUP(avb_magic),
2789 SH_PFC_PIN_GROUP(avb_phy_int), 3838 SH_PFC_PIN_GROUP(avb_phy_int),
@@ -2794,6 +3843,36 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2794 SH_PFC_PIN_GROUP(avb_avtp_capture_a), 3843 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
2795 SH_PFC_PIN_GROUP(avb_avtp_match_b), 3844 SH_PFC_PIN_GROUP(avb_avtp_match_b),
2796 SH_PFC_PIN_GROUP(avb_avtp_capture_b), 3845 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3846 SH_PFC_PIN_GROUP(drif0_ctrl_a),
3847 SH_PFC_PIN_GROUP(drif0_data0_a),
3848 SH_PFC_PIN_GROUP(drif0_data1_a),
3849 SH_PFC_PIN_GROUP(drif0_ctrl_b),
3850 SH_PFC_PIN_GROUP(drif0_data0_b),
3851 SH_PFC_PIN_GROUP(drif0_data1_b),
3852 SH_PFC_PIN_GROUP(drif0_ctrl_c),
3853 SH_PFC_PIN_GROUP(drif0_data0_c),
3854 SH_PFC_PIN_GROUP(drif0_data1_c),
3855 SH_PFC_PIN_GROUP(drif1_ctrl_a),
3856 SH_PFC_PIN_GROUP(drif1_data0_a),
3857 SH_PFC_PIN_GROUP(drif1_data1_a),
3858 SH_PFC_PIN_GROUP(drif1_ctrl_b),
3859 SH_PFC_PIN_GROUP(drif1_data0_b),
3860 SH_PFC_PIN_GROUP(drif1_data1_b),
3861 SH_PFC_PIN_GROUP(drif1_ctrl_c),
3862 SH_PFC_PIN_GROUP(drif1_data0_c),
3863 SH_PFC_PIN_GROUP(drif1_data1_c),
3864 SH_PFC_PIN_GROUP(drif2_ctrl_a),
3865 SH_PFC_PIN_GROUP(drif2_data0_a),
3866 SH_PFC_PIN_GROUP(drif2_data1_a),
3867 SH_PFC_PIN_GROUP(drif2_ctrl_b),
3868 SH_PFC_PIN_GROUP(drif2_data0_b),
3869 SH_PFC_PIN_GROUP(drif2_data1_b),
3870 SH_PFC_PIN_GROUP(drif3_ctrl_a),
3871 SH_PFC_PIN_GROUP(drif3_data0_a),
3872 SH_PFC_PIN_GROUP(drif3_data1_a),
3873 SH_PFC_PIN_GROUP(drif3_ctrl_b),
3874 SH_PFC_PIN_GROUP(drif3_data0_b),
3875 SH_PFC_PIN_GROUP(drif3_data1_b),
2797 SH_PFC_PIN_GROUP(du_rgb666), 3876 SH_PFC_PIN_GROUP(du_rgb666),
2798 SH_PFC_PIN_GROUP(du_rgb888), 3877 SH_PFC_PIN_GROUP(du_rgb888),
2799 SH_PFC_PIN_GROUP(du_clk_out_0), 3878 SH_PFC_PIN_GROUP(du_clk_out_0),
@@ -2802,6 +3881,47 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2802 SH_PFC_PIN_GROUP(du_oddf), 3881 SH_PFC_PIN_GROUP(du_oddf),
2803 SH_PFC_PIN_GROUP(du_cde), 3882 SH_PFC_PIN_GROUP(du_cde),
2804 SH_PFC_PIN_GROUP(du_disp), 3883 SH_PFC_PIN_GROUP(du_disp),
3884 SH_PFC_PIN_GROUP(hscif0_data),
3885 SH_PFC_PIN_GROUP(hscif0_clk),
3886 SH_PFC_PIN_GROUP(hscif0_ctrl),
3887 SH_PFC_PIN_GROUP(hscif1_data_a),
3888 SH_PFC_PIN_GROUP(hscif1_clk_a),
3889 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3890 SH_PFC_PIN_GROUP(hscif1_data_b),
3891 SH_PFC_PIN_GROUP(hscif1_clk_b),
3892 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3893 SH_PFC_PIN_GROUP(hscif2_data_a),
3894 SH_PFC_PIN_GROUP(hscif2_clk_a),
3895 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3896 SH_PFC_PIN_GROUP(hscif2_data_b),
3897 SH_PFC_PIN_GROUP(hscif2_clk_b),
3898 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3899 SH_PFC_PIN_GROUP(hscif2_data_c),
3900 SH_PFC_PIN_GROUP(hscif2_clk_c),
3901 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
3902 SH_PFC_PIN_GROUP(hscif3_data_a),
3903 SH_PFC_PIN_GROUP(hscif3_clk),
3904 SH_PFC_PIN_GROUP(hscif3_ctrl),
3905 SH_PFC_PIN_GROUP(hscif3_data_b),
3906 SH_PFC_PIN_GROUP(hscif3_data_c),
3907 SH_PFC_PIN_GROUP(hscif3_data_d),
3908 SH_PFC_PIN_GROUP(hscif4_data_a),
3909 SH_PFC_PIN_GROUP(hscif4_clk),
3910 SH_PFC_PIN_GROUP(hscif4_ctrl),
3911 SH_PFC_PIN_GROUP(hscif4_data_b),
3912 SH_PFC_PIN_GROUP(i2c1_a),
3913 SH_PFC_PIN_GROUP(i2c1_b),
3914 SH_PFC_PIN_GROUP(i2c2_a),
3915 SH_PFC_PIN_GROUP(i2c2_b),
3916 SH_PFC_PIN_GROUP(i2c6_a),
3917 SH_PFC_PIN_GROUP(i2c6_b),
3918 SH_PFC_PIN_GROUP(i2c6_c),
3919 SH_PFC_PIN_GROUP(intc_ex_irq0),
3920 SH_PFC_PIN_GROUP(intc_ex_irq1),
3921 SH_PFC_PIN_GROUP(intc_ex_irq2),
3922 SH_PFC_PIN_GROUP(intc_ex_irq3),
3923 SH_PFC_PIN_GROUP(intc_ex_irq4),
3924 SH_PFC_PIN_GROUP(intc_ex_irq5),
2805 SH_PFC_PIN_GROUP(msiof0_clk), 3925 SH_PFC_PIN_GROUP(msiof0_clk),
2806 SH_PFC_PIN_GROUP(msiof0_sync), 3926 SH_PFC_PIN_GROUP(msiof0_sync),
2807 SH_PFC_PIN_GROUP(msiof0_ss1), 3927 SH_PFC_PIN_GROUP(msiof0_ss1),
@@ -2943,10 +4063,82 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2943 SH_PFC_PIN_GROUP(scif5_clk_b), 4063 SH_PFC_PIN_GROUP(scif5_clk_b),
2944 SH_PFC_PIN_GROUP(scif_clk_a), 4064 SH_PFC_PIN_GROUP(scif_clk_a),
2945 SH_PFC_PIN_GROUP(scif_clk_b), 4065 SH_PFC_PIN_GROUP(scif_clk_b),
4066 SH_PFC_PIN_GROUP(sdhi0_data1),
4067 SH_PFC_PIN_GROUP(sdhi0_data4),
4068 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4069 SH_PFC_PIN_GROUP(sdhi0_cd),
4070 SH_PFC_PIN_GROUP(sdhi0_wp),
4071 SH_PFC_PIN_GROUP(sdhi1_data1),
4072 SH_PFC_PIN_GROUP(sdhi1_data4),
4073 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4074 SH_PFC_PIN_GROUP(sdhi1_cd),
4075 SH_PFC_PIN_GROUP(sdhi1_wp),
4076 SH_PFC_PIN_GROUP(sdhi2_data1),
4077 SH_PFC_PIN_GROUP(sdhi2_data4),
4078 SH_PFC_PIN_GROUP(sdhi2_data8),
4079 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4080 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4081 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4082 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4083 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4084 SH_PFC_PIN_GROUP(sdhi2_ds),
4085 SH_PFC_PIN_GROUP(sdhi3_data1),
4086 SH_PFC_PIN_GROUP(sdhi3_data4),
4087 SH_PFC_PIN_GROUP(sdhi3_data8),
4088 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4089 SH_PFC_PIN_GROUP(sdhi3_cd),
4090 SH_PFC_PIN_GROUP(sdhi3_wp),
4091 SH_PFC_PIN_GROUP(sdhi3_ds),
4092 SH_PFC_PIN_GROUP(ssi0_data),
4093 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4094 SH_PFC_PIN_GROUP(ssi1_data_a),
4095 SH_PFC_PIN_GROUP(ssi1_data_b),
4096 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4097 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4098 SH_PFC_PIN_GROUP(ssi2_data_a),
4099 SH_PFC_PIN_GROUP(ssi2_data_b),
4100 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4101 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4102 SH_PFC_PIN_GROUP(ssi3_data),
4103 SH_PFC_PIN_GROUP(ssi349_ctrl),
4104 SH_PFC_PIN_GROUP(ssi4_data),
4105 SH_PFC_PIN_GROUP(ssi4_ctrl),
4106 SH_PFC_PIN_GROUP(ssi5_data),
4107 SH_PFC_PIN_GROUP(ssi5_ctrl),
4108 SH_PFC_PIN_GROUP(ssi6_data),
4109 SH_PFC_PIN_GROUP(ssi6_ctrl),
4110 SH_PFC_PIN_GROUP(ssi7_data),
4111 SH_PFC_PIN_GROUP(ssi78_ctrl),
4112 SH_PFC_PIN_GROUP(ssi8_data),
4113 SH_PFC_PIN_GROUP(ssi9_data_a),
4114 SH_PFC_PIN_GROUP(ssi9_data_b),
4115 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4116 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
2946 SH_PFC_PIN_GROUP(usb0), 4117 SH_PFC_PIN_GROUP(usb0),
2947 SH_PFC_PIN_GROUP(usb1), 4118 SH_PFC_PIN_GROUP(usb1),
2948 SH_PFC_PIN_GROUP(usb2), 4119 SH_PFC_PIN_GROUP(usb2),
2949 SH_PFC_PIN_GROUP(usb2_ch3), 4120 SH_PFC_PIN_GROUP(usb2_ch3),
4121 SH_PFC_PIN_GROUP(usb30),
4122};
4123
4124static const char * const audio_clk_groups[] = {
4125 "audio_clk_a_a",
4126 "audio_clk_a_b",
4127 "audio_clk_a_c",
4128 "audio_clk_b_a",
4129 "audio_clk_b_b",
4130 "audio_clk_c_a",
4131 "audio_clk_c_b",
4132 "audio_clkout_a",
4133 "audio_clkout_b",
4134 "audio_clkout_c",
4135 "audio_clkout_d",
4136 "audio_clkout1_a",
4137 "audio_clkout1_b",
4138 "audio_clkout2_a",
4139 "audio_clkout2_b",
4140 "audio_clkout3_a",
4141 "audio_clkout3_b",
2950}; 4142};
2951 4143
2952static const char * const avb_groups[] = { 4144static const char * const avb_groups[] = {
@@ -2962,6 +4154,48 @@ static const char * const avb_groups[] = {
2962 "avb_avtp_capture_b", 4154 "avb_avtp_capture_b",
2963}; 4155};
2964 4156
4157static const char * const drif0_groups[] = {
4158 "drif0_ctrl_a",
4159 "drif0_data0_a",
4160 "drif0_data1_a",
4161 "drif0_ctrl_b",
4162 "drif0_data0_b",
4163 "drif0_data1_b",
4164 "drif0_ctrl_c",
4165 "drif0_data0_c",
4166 "drif0_data1_c",
4167};
4168
4169static const char * const drif1_groups[] = {
4170 "drif1_ctrl_a",
4171 "drif1_data0_a",
4172 "drif1_data1_a",
4173 "drif1_ctrl_b",
4174 "drif1_data0_b",
4175 "drif1_data1_b",
4176 "drif1_ctrl_c",
4177 "drif1_data0_c",
4178 "drif1_data1_c",
4179};
4180
4181static const char * const drif2_groups[] = {
4182 "drif2_ctrl_a",
4183 "drif2_data0_a",
4184 "drif2_data1_a",
4185 "drif2_ctrl_b",
4186 "drif2_data0_b",
4187 "drif2_data1_b",
4188};
4189
4190static const char * const drif3_groups[] = {
4191 "drif3_ctrl_a",
4192 "drif3_data0_a",
4193 "drif3_data1_a",
4194 "drif3_ctrl_b",
4195 "drif3_data0_b",
4196 "drif3_data1_b",
4197};
4198
2965static const char * const du_groups[] = { 4199static const char * const du_groups[] = {
2966 "du_rgb666", 4200 "du_rgb666",
2967 "du_rgb888", 4201 "du_rgb888",
@@ -2973,6 +4207,74 @@ static const char * const du_groups[] = {
2973 "du_disp", 4207 "du_disp",
2974}; 4208};
2975 4209
4210static const char * const hscif0_groups[] = {
4211 "hscif0_data",
4212 "hscif0_clk",
4213 "hscif0_ctrl",
4214};
4215
4216static const char * const hscif1_groups[] = {
4217 "hscif1_data_a",
4218 "hscif1_clk_a",
4219 "hscif1_ctrl_a",
4220 "hscif1_data_b",
4221 "hscif1_clk_b",
4222 "hscif1_ctrl_b",
4223};
4224
4225static const char * const hscif2_groups[] = {
4226 "hscif2_data_a",
4227 "hscif2_clk_a",
4228 "hscif2_ctrl_a",
4229 "hscif2_data_b",
4230 "hscif2_clk_b",
4231 "hscif2_ctrl_b",
4232 "hscif2_data_c",
4233 "hscif2_clk_c",
4234 "hscif2_ctrl_c",
4235};
4236
4237static const char * const hscif3_groups[] = {
4238 "hscif3_data_a",
4239 "hscif3_clk",
4240 "hscif3_ctrl",
4241 "hscif3_data_b",
4242 "hscif3_data_c",
4243 "hscif3_data_d",
4244};
4245
4246static const char * const hscif4_groups[] = {
4247 "hscif4_data_a",
4248 "hscif4_clk",
4249 "hscif4_ctrl",
4250 "hscif4_data_b",
4251};
4252
4253static const char * const i2c1_groups[] = {
4254 "i2c1_a",
4255 "i2c1_b",
4256};
4257
4258static const char * const i2c2_groups[] = {
4259 "i2c2_a",
4260 "i2c2_b",
4261};
4262
4263static const char * const i2c6_groups[] = {
4264 "i2c6_a",
4265 "i2c6_b",
4266 "i2c6_c",
4267};
4268
4269static const char * const intc_ex_groups[] = {
4270 "intc_ex_irq0",
4271 "intc_ex_irq1",
4272 "intc_ex_irq2",
4273 "intc_ex_irq3",
4274 "intc_ex_irq4",
4275 "intc_ex_irq5",
4276};
4277
2976static const char * const msiof0_groups[] = { 4278static const char * const msiof0_groups[] = {
2977 "msiof0_clk", 4279 "msiof0_clk",
2978 "msiof0_sync", 4280 "msiof0_sync",
@@ -3168,6 +4470,72 @@ static const char * const scif_clk_groups[] = {
3168 "scif_clk_b", 4470 "scif_clk_b",
3169}; 4471};
3170 4472
4473static const char * const sdhi0_groups[] = {
4474 "sdhi0_data1",
4475 "sdhi0_data4",
4476 "sdhi0_ctrl",
4477 "sdhi0_cd",
4478 "sdhi0_wp",
4479};
4480
4481static const char * const sdhi1_groups[] = {
4482 "sdhi1_data1",
4483 "sdhi1_data4",
4484 "sdhi1_ctrl",
4485 "sdhi1_cd",
4486 "sdhi1_wp",
4487};
4488
4489static const char * const sdhi2_groups[] = {
4490 "sdhi2_data1",
4491 "sdhi2_data4",
4492 "sdhi2_data8",
4493 "sdhi2_ctrl",
4494 "sdhi2_cd_a",
4495 "sdhi2_wp_a",
4496 "sdhi2_cd_b",
4497 "sdhi2_wp_b",
4498 "sdhi2_ds",
4499};
4500
4501static const char * const sdhi3_groups[] = {
4502 "sdhi3_data1",
4503 "sdhi3_data4",
4504 "sdhi3_data8",
4505 "sdhi3_ctrl",
4506 "sdhi3_cd",
4507 "sdhi3_wp",
4508 "sdhi3_ds",
4509};
4510
4511static const char * const ssi_groups[] = {
4512 "ssi0_data",
4513 "ssi01239_ctrl",
4514 "ssi1_data_a",
4515 "ssi1_data_b",
4516 "ssi1_ctrl_a",
4517 "ssi1_ctrl_b",
4518 "ssi2_data_a",
4519 "ssi2_data_b",
4520 "ssi2_ctrl_a",
4521 "ssi2_ctrl_b",
4522 "ssi3_data",
4523 "ssi349_ctrl",
4524 "ssi4_data",
4525 "ssi4_ctrl",
4526 "ssi5_data",
4527 "ssi5_ctrl",
4528 "ssi6_data",
4529 "ssi6_ctrl",
4530 "ssi7_data",
4531 "ssi78_ctrl",
4532 "ssi8_data",
4533 "ssi9_data_a",
4534 "ssi9_data_b",
4535 "ssi9_ctrl_a",
4536 "ssi9_ctrl_b",
4537};
4538
3171static const char * const usb0_groups[] = { 4539static const char * const usb0_groups[] = {
3172 "usb0", 4540 "usb0",
3173}; 4541};
@@ -3184,9 +4552,27 @@ static const char * const usb2_ch3_groups[] = {
3184 "usb2_ch3", 4552 "usb2_ch3",
3185}; 4553};
3186 4554
4555static const char * const usb30_groups[] = {
4556 "usb30",
4557};
4558
3187static const struct sh_pfc_function pinmux_functions[] = { 4559static const struct sh_pfc_function pinmux_functions[] = {
4560 SH_PFC_FUNCTION(audio_clk),
3188 SH_PFC_FUNCTION(avb), 4561 SH_PFC_FUNCTION(avb),
4562 SH_PFC_FUNCTION(drif0),
4563 SH_PFC_FUNCTION(drif1),
4564 SH_PFC_FUNCTION(drif2),
4565 SH_PFC_FUNCTION(drif3),
3189 SH_PFC_FUNCTION(du), 4566 SH_PFC_FUNCTION(du),
4567 SH_PFC_FUNCTION(hscif0),
4568 SH_PFC_FUNCTION(hscif1),
4569 SH_PFC_FUNCTION(hscif2),
4570 SH_PFC_FUNCTION(hscif3),
4571 SH_PFC_FUNCTION(hscif4),
4572 SH_PFC_FUNCTION(i2c1),
4573 SH_PFC_FUNCTION(i2c2),
4574 SH_PFC_FUNCTION(i2c6),
4575 SH_PFC_FUNCTION(intc_ex),
3190 SH_PFC_FUNCTION(msiof0), 4576 SH_PFC_FUNCTION(msiof0),
3191 SH_PFC_FUNCTION(msiof1), 4577 SH_PFC_FUNCTION(msiof1),
3192 SH_PFC_FUNCTION(msiof2), 4578 SH_PFC_FUNCTION(msiof2),
@@ -3205,10 +4591,16 @@ static const struct sh_pfc_function pinmux_functions[] = {
3205 SH_PFC_FUNCTION(scif4), 4591 SH_PFC_FUNCTION(scif4),
3206 SH_PFC_FUNCTION(scif5), 4592 SH_PFC_FUNCTION(scif5),
3207 SH_PFC_FUNCTION(scif_clk), 4593 SH_PFC_FUNCTION(scif_clk),
4594 SH_PFC_FUNCTION(sdhi0),
4595 SH_PFC_FUNCTION(sdhi1),
4596 SH_PFC_FUNCTION(sdhi2),
4597 SH_PFC_FUNCTION(sdhi3),
4598 SH_PFC_FUNCTION(ssi),
3208 SH_PFC_FUNCTION(usb0), 4599 SH_PFC_FUNCTION(usb0),
3209 SH_PFC_FUNCTION(usb1), 4600 SH_PFC_FUNCTION(usb1),
3210 SH_PFC_FUNCTION(usb2), 4601 SH_PFC_FUNCTION(usb2),
3211 SH_PFC_FUNCTION(usb2_ch3), 4602 SH_PFC_FUNCTION(usb2_ch3),
4603 SH_PFC_FUNCTION(usb30),
3212}; 4604};
3213 4605
3214static const struct pinmux_cfg_reg pinmux_config_regs[] = { 4606static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -4021,11 +5413,20 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
4021 { }, 5413 { },
4022}; 5414};
4023 5415
5416enum ioctrl_regs {
5417 POCCTRL,
5418};
5419
5420static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5421 [POCCTRL] = { 0xe6060380, },
5422 { /* sentinel */ },
5423};
5424
4024static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) 5425static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
4025{ 5426{
4026 int bit = -EINVAL; 5427 int bit = -EINVAL;
4027 5428
4028 *pocctrl = 0xe6060380; 5429 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
4029 5430
4030 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) 5431 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
4031 bit = pin & 0x1f; 5432 bit = pin & 0x1f;
@@ -4036,242 +5437,261 @@ static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
4036 return bit; 5437 return bit;
4037} 5438}
4038 5439
4039#define PUEN 0xe6060400 5440static const struct pinmux_bias_reg pinmux_bias_regs[] = {
4040#define PUD 0xe6060440 5441 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
4041 5442 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
4042#define PU0 0x00 5443 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
4043#define PU1 0x04 5444 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
4044#define PU2 0x08 5445 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
4045#define PU3 0x0c 5446 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
4046#define PU4 0x10 5447 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
4047#define PU5 0x14 5448 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
4048#define PU6 0x18 5449 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
4049 5450 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
4050static const struct sh_pfc_bias_info bias_info[] = { 5451 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
4051 { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */ 5452 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
4052 { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */ 5453 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
4053 { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */ 5454 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
4054 { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */ 5455 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
4055 { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */ 5456 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
4056 { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */ 5457 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
4057 { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */ 5458 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
4058 { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */ 5459 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
4059 { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */ 5460 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
4060 { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */ 5461 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
4061 { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */ 5462 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
4062 { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */ 5463 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
4063 { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */ 5464 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
4064 { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */ 5465 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
4065 { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */ 5466 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
4066 { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */ 5467 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
4067 { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */ 5468 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
4068 { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */ 5469 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
4069 { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */ 5470 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
4070 { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */ 5471 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
4071 { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */ 5472 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
4072 { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */ 5473 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
4073 { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */ 5474 } },
4074 { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */ 5475 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
4075 { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */ 5476 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
4076 { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */ 5477 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
4077 { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */ 5478 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
4078 { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */ 5479 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
4079 { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */ 5480 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
4080 { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */ 5481 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
4081 { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */ 5482 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
4082 { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */ 5483 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
4083 5484 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
4084 { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */ 5485 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
4085 { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */ 5486 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
4086 { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */ 5487 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
4087 { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */ 5488 [12] = RCAR_GP_PIN(1, 0), /* A0 */
4088 { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */ 5489 [13] = RCAR_GP_PIN(1, 1), /* A1 */
4089 { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */ 5490 [14] = RCAR_GP_PIN(1, 2), /* A2 */
4090 { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */ 5491 [15] = RCAR_GP_PIN(1, 3), /* A3 */
4091 { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */ 5492 [16] = RCAR_GP_PIN(1, 4), /* A4 */
4092 { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */ 5493 [17] = RCAR_GP_PIN(1, 5), /* A5 */
4093 { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */ 5494 [18] = RCAR_GP_PIN(1, 6), /* A6 */
4094 { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */ 5495 [19] = RCAR_GP_PIN(1, 7), /* A7 */
4095 { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */ 5496 [20] = RCAR_GP_PIN(1, 8), /* A8 */
4096 { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */ 5497 [21] = RCAR_GP_PIN(1, 9), /* A9 */
4097 { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */ 5498 [22] = RCAR_GP_PIN(1, 10), /* A10 */
4098 { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */ 5499 [23] = RCAR_GP_PIN(1, 11), /* A11 */
4099 { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */ 5500 [24] = RCAR_GP_PIN(1, 12), /* A12 */
4100 { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */ 5501 [25] = RCAR_GP_PIN(1, 13), /* A13 */
4101 { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */ 5502 [26] = RCAR_GP_PIN(1, 14), /* A14 */
4102 { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */ 5503 [27] = RCAR_GP_PIN(1, 15), /* A15 */
4103 { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */ 5504 [28] = RCAR_GP_PIN(1, 16), /* A16 */
4104 { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */ 5505 [29] = RCAR_GP_PIN(1, 17), /* A17 */
4105 { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */ 5506 [30] = RCAR_GP_PIN(1, 18), /* A18 */
4106 { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */ 5507 [31] = RCAR_GP_PIN(1, 19), /* A19 */
4107 { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */ 5508 } },
4108 { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */ 5509 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
4109 { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */ 5510 [ 0] = PIN_NUMBER('F', 1), /* CLKOUT */
4110 { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */ 5511 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
4111 { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */ 5512 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
4112 { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */ 5513 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
4113 { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ 5514 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
4114 { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */ 5515 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
4115 { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */ 5516 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
4116 5517 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
4117 { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */ 5518 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
4118 { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */ 5519 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
4119 { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */ 5520 [10] = RCAR_GP_PIN(0, 0), /* D0 */
4120 { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */ 5521 [11] = RCAR_GP_PIN(0, 1), /* D1 */
4121 { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */ 5522 [12] = RCAR_GP_PIN(0, 2), /* D2 */
4122 { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */ 5523 [13] = RCAR_GP_PIN(0, 3), /* D3 */
4123 { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */ 5524 [14] = RCAR_GP_PIN(0, 4), /* D4 */
4124 { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */ 5525 [15] = RCAR_GP_PIN(0, 5), /* D5 */
4125 { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */ 5526 [16] = RCAR_GP_PIN(0, 6), /* D6 */
4126 { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */ 5527 [17] = RCAR_GP_PIN(0, 7), /* D7 */
4127 { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */ 5528 [18] = RCAR_GP_PIN(0, 8), /* D8 */
4128 { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */ 5529 [19] = RCAR_GP_PIN(0, 9), /* D9 */
4129 { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */ 5530 [20] = RCAR_GP_PIN(0, 10), /* D10 */
4130 { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */ 5531 [21] = RCAR_GP_PIN(0, 11), /* D11 */
4131 { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */ 5532 [22] = RCAR_GP_PIN(0, 12), /* D12 */
4132 { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */ 5533 [23] = RCAR_GP_PIN(0, 13), /* D13 */
4133 { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */ 5534 [24] = RCAR_GP_PIN(0, 14), /* D14 */
4134 { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */ 5535 [25] = RCAR_GP_PIN(0, 15), /* D15 */
4135 { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */ 5536 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
4136 { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */ 5537 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
4137 { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */ 5538 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
4138 { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */ 5539 [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */
4139 { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */ 5540 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
4140 { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */ 5541 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
4141 { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */ 5542 } },
4142 { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */ 5543 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
4143 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ 5544 [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
4144 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ 5545 [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
4145 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ 5546 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
4146 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N */ 5547 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
4147 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ 5548 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
4148 { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */ 5549 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
4149 5550 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
4150 { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */ 5551 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
4151 { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */ 5552 [ 8] = PIN_NONE,
4152 { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */ 5553 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
4153 { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */ 5554 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
4154 { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */ 5555 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
4155 { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */ 5556 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
4156 { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */ 5557 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
4157 { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */ 5558 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
4158 { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */ 5559 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
4159 { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */ 5560 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
4160 { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */ 5561 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
4161 { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */ 5562 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
4162 { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */ 5563 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
4163 { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */ 5564 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
4164 { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */ 5565 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
4165 { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */ 5566 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
4166 { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */ 5567 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
4167 { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */ 5568 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
4168 { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */ 5569 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
4169 { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */ 5570 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
4170 { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */ 5571 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
4171 { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */ 5572 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
4172 { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */ 5573 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
4173 /* bit 8 n/a */ 5574 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
4174 { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */ 5575 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
4175 { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */ 5576 } },
4176 { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */ 5577 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
4177 { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */ 5578 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
4178 { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/ 5579 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
4179 { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */ 5580 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
4180 { PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */ 5581 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
4181 { PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */ 5582 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
4182 5583 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
4183 { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */ 5584 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
4184 { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */ 5585 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
4185 { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */ 5586 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
4186 { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */ 5587 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
4187 { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */ 5588 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
4188 { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */ 5589 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
4189 { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */ 5590 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
4190 { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */ 5591 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
4191 { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */ 5592 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
4192 { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */ 5593 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
4193 { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */ 5594 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N_TANS */
4194 { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */ 5595 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
4195 { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */ 5596 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
4196 { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */ 5597 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
4197 { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */ 5598 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N_TANS */
4198 { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */ 5599 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
4199 { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */ 5600 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
4200 { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */ 5601 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
4201 { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */ 5602 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
4202 { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */ 5603 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
4203 { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */ 5604 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
4204 { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */ 5605 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
4205 { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */ 5606 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
4206 { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */ 5607 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
4207 { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */ 5608 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
4208 { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */ 5609 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
4209 { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */ 5610 } },
4210 { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */ 5611 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
4211 { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */ 5612 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
4212 { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */ 5613 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
4213 { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */ 5614 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
4214 { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */ 5615 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
4215 5616 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
4216 { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */ 5617 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
4217 { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */ 5618 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
4218 { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */ 5619 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
4219 { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */ 5620 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
4220 { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */ 5621 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
4221 { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */ 5622 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
4222 { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */ 5623 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
4223 { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */ 5624 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
4224 { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */ 5625 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
4225 { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */ 5626 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
4226 { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */ 5627 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
4227 { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */ 5628 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
4228 { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */ 5629 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
4229 { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */ 5630 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
4230 { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */ 5631 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
4231 { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ 5632 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
4232 { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ 5633 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
4233 { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ 5634 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
4234 { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */ 5635 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
4235 { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */ 5636 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
4236 { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ 5637 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
4237 { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ 5638 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
4238 { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ 5639 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
4239 { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */ 5640 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
4240 { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */ 5641 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
4241 { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */ 5642 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
4242 { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */ 5643 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
4243 { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */ 5644 } },
4244 { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */ 5645 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
4245 { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */ 5646 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
4246 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ 5647 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
4247 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ 5648 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
4248 5649 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
4249 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB2_CH3_OVC */ 5650 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
4250 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB2_CH3_PWEN */ 5651 [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
4251 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ 5652 [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
4252 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ 5653 [ 7] = PIN_NONE,
4253 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ 5654 [ 8] = PIN_NONE,
4254 { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */ 5655 [ 9] = PIN_NONE,
4255 { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */ 5656 [10] = PIN_NONE,
5657 [11] = PIN_NONE,
5658 [12] = PIN_NONE,
5659 [13] = PIN_NONE,
5660 [14] = PIN_NONE,
5661 [15] = PIN_NONE,
5662 [16] = PIN_NONE,
5663 [17] = PIN_NONE,
5664 [18] = PIN_NONE,
5665 [19] = PIN_NONE,
5666 [20] = PIN_NONE,
5667 [21] = PIN_NONE,
5668 [22] = PIN_NONE,
5669 [23] = PIN_NONE,
5670 [24] = PIN_NONE,
5671 [25] = PIN_NONE,
5672 [26] = PIN_NONE,
5673 [27] = PIN_NONE,
5674 [28] = PIN_NONE,
5675 [29] = PIN_NONE,
5676 [30] = PIN_NONE,
5677 [31] = PIN_NONE,
5678 } },
5679 { /* sentinel */ },
4256}; 5680};
4257 5681
4258static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc, 5682static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
4259 unsigned int pin) 5683 unsigned int pin)
4260{ 5684{
4261 const struct sh_pfc_bias_info *info; 5685 const struct pinmux_bias_reg *reg;
4262 u32 reg; 5686 unsigned int bit;
4263 u32 bit;
4264 5687
4265 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); 5688 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
4266 if (!info) 5689 if (!reg)
4267 return PIN_CONFIG_BIAS_DISABLE; 5690 return PIN_CONFIG_BIAS_DISABLE;
4268 5691
4269 reg = info->reg; 5692 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
4270 bit = BIT(info->bit);
4271
4272 if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
4273 return PIN_CONFIG_BIAS_DISABLE; 5693 return PIN_CONFIG_BIAS_DISABLE;
4274 else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit) 5694 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
4275 return PIN_CONFIG_BIAS_PULL_UP; 5695 return PIN_CONFIG_BIAS_PULL_UP;
4276 else 5696 else
4277 return PIN_CONFIG_BIAS_PULL_DOWN; 5697 return PIN_CONFIG_BIAS_PULL_DOWN;
@@ -4280,28 +5700,24 @@ static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
4280static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 5700static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
4281 unsigned int bias) 5701 unsigned int bias)
4282{ 5702{
4283 const struct sh_pfc_bias_info *info; 5703 const struct pinmux_bias_reg *reg;
4284 u32 enable, updown; 5704 u32 enable, updown;
4285 u32 reg; 5705 unsigned int bit;
4286 u32 bit;
4287 5706
4288 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); 5707 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
4289 if (!info) 5708 if (!reg)
4290 return; 5709 return;
4291 5710
4292 reg = info->reg; 5711 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
4293 bit = BIT(info->bit);
4294
4295 enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
4296 if (bias != PIN_CONFIG_BIAS_DISABLE) 5712 if (bias != PIN_CONFIG_BIAS_DISABLE)
4297 enable |= bit; 5713 enable |= BIT(bit);
4298 5714
4299 updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit; 5715 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
4300 if (bias == PIN_CONFIG_BIAS_PULL_UP) 5716 if (bias == PIN_CONFIG_BIAS_PULL_UP)
4301 updown |= bit; 5717 updown |= BIT(bit);
4302 5718
4303 sh_pfc_write_reg(pfc, PUD + reg, 32, updown); 5719 sh_pfc_write(pfc, reg->pud, updown);
4304 sh_pfc_write_reg(pfc, PUEN + reg, 32, enable); 5720 sh_pfc_write(pfc, reg->puen, enable);
4305} 5721}
4306 5722
4307static const struct soc_device_attribute r8a7795es1[] = { 5723static const struct soc_device_attribute r8a7795es1[] = {
@@ -4340,6 +5756,8 @@ const struct sh_pfc_soc_info r8a7795_pinmux_info = {
4340 5756
4341 .cfg_regs = pinmux_config_regs, 5757 .cfg_regs = pinmux_config_regs,
4342 .drive_regs = pinmux_drive_regs, 5758 .drive_regs = pinmux_drive_regs,
5759 .bias_regs = pinmux_bias_regs,
5760 .ioctrl_regs = pinmux_ioctrl_regs,
4343 5761
4344 .pinmux_data = pinmux_data, 5762 .pinmux_data = pinmux_data,
4345 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 5763 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 200e1f4f6db9..73ed9c74c137 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -495,7 +495,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
495#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1) 495#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
496#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1) 496#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
497 497
498/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ 498/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
499#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1) 499#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
500#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1) 500#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
501#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1) 501#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
@@ -1518,6 +1518,7 @@ static const u16 pinmux_data[] = {
1518#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) 1518#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1519#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300) 1519#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1520#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) 1520#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1521#define PIN_NONE U16_MAX
1521 1522
1522static const struct sh_pfc_pin pinmux_pins[] = { 1523static const struct sh_pfc_pin pinmux_pins[] = {
1523 PINMUX_GPIO_GP_ALL(), 1524 PINMUX_GPIO_GP_ALL(),
@@ -2392,6 +2393,50 @@ static const unsigned int i2c6_c_mux[] = {
2392 SDA6_C_MARK, SCL6_C_MARK, 2393 SDA6_C_MARK, SCL6_C_MARK,
2393}; 2394};
2394 2395
2396/* - INTC-EX ---------------------------------------------------------------- */
2397static const unsigned int intc_ex_irq0_pins[] = {
2398 /* IRQ0 */
2399 RCAR_GP_PIN(2, 0),
2400};
2401static const unsigned int intc_ex_irq0_mux[] = {
2402 IRQ0_MARK,
2403};
2404static const unsigned int intc_ex_irq1_pins[] = {
2405 /* IRQ1 */
2406 RCAR_GP_PIN(2, 1),
2407};
2408static const unsigned int intc_ex_irq1_mux[] = {
2409 IRQ1_MARK,
2410};
2411static const unsigned int intc_ex_irq2_pins[] = {
2412 /* IRQ2 */
2413 RCAR_GP_PIN(2, 2),
2414};
2415static const unsigned int intc_ex_irq2_mux[] = {
2416 IRQ2_MARK,
2417};
2418static const unsigned int intc_ex_irq3_pins[] = {
2419 /* IRQ3 */
2420 RCAR_GP_PIN(2, 3),
2421};
2422static const unsigned int intc_ex_irq3_mux[] = {
2423 IRQ3_MARK,
2424};
2425static const unsigned int intc_ex_irq4_pins[] = {
2426 /* IRQ4 */
2427 RCAR_GP_PIN(2, 4),
2428};
2429static const unsigned int intc_ex_irq4_mux[] = {
2430 IRQ4_MARK,
2431};
2432static const unsigned int intc_ex_irq5_pins[] = {
2433 /* IRQ5 */
2434 RCAR_GP_PIN(2, 5),
2435};
2436static const unsigned int intc_ex_irq5_mux[] = {
2437 IRQ5_MARK,
2438};
2439
2395/* - MSIOF0 ----------------------------------------------------------------- */ 2440/* - MSIOF0 ----------------------------------------------------------------- */
2396static const unsigned int msiof0_clk_pins[] = { 2441static const unsigned int msiof0_clk_pins[] = {
2397 /* SCK */ 2442 /* SCK */
@@ -3922,6 +3967,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3922 SH_PFC_PIN_GROUP(i2c6_a), 3967 SH_PFC_PIN_GROUP(i2c6_a),
3923 SH_PFC_PIN_GROUP(i2c6_b), 3968 SH_PFC_PIN_GROUP(i2c6_b),
3924 SH_PFC_PIN_GROUP(i2c6_c), 3969 SH_PFC_PIN_GROUP(i2c6_c),
3970 SH_PFC_PIN_GROUP(intc_ex_irq0),
3971 SH_PFC_PIN_GROUP(intc_ex_irq1),
3972 SH_PFC_PIN_GROUP(intc_ex_irq2),
3973 SH_PFC_PIN_GROUP(intc_ex_irq3),
3974 SH_PFC_PIN_GROUP(intc_ex_irq4),
3975 SH_PFC_PIN_GROUP(intc_ex_irq5),
3925 SH_PFC_PIN_GROUP(msiof0_clk), 3976 SH_PFC_PIN_GROUP(msiof0_clk),
3926 SH_PFC_PIN_GROUP(msiof0_sync), 3977 SH_PFC_PIN_GROUP(msiof0_sync),
3927 SH_PFC_PIN_GROUP(msiof0_ss1), 3978 SH_PFC_PIN_GROUP(msiof0_ss1),
@@ -4286,6 +4337,15 @@ static const char * const i2c6_groups[] = {
4286 "i2c6_c", 4337 "i2c6_c",
4287}; 4338};
4288 4339
4340static const char * const intc_ex_groups[] = {
4341 "intc_ex_irq0",
4342 "intc_ex_irq1",
4343 "intc_ex_irq2",
4344 "intc_ex_irq3",
4345 "intc_ex_irq4",
4346 "intc_ex_irq5",
4347};
4348
4289static const char * const msiof0_groups[] = { 4349static const char * const msiof0_groups[] = {
4290 "msiof0_clk", 4350 "msiof0_clk",
4291 "msiof0_sync", 4351 "msiof0_sync",
@@ -4580,6 +4640,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
4580 SH_PFC_FUNCTION(i2c1), 4640 SH_PFC_FUNCTION(i2c1),
4581 SH_PFC_FUNCTION(i2c2), 4641 SH_PFC_FUNCTION(i2c2),
4582 SH_PFC_FUNCTION(i2c6), 4642 SH_PFC_FUNCTION(i2c6),
4643 SH_PFC_FUNCTION(intc_ex),
4583 SH_PFC_FUNCTION(msiof0), 4644 SH_PFC_FUNCTION(msiof0),
4584 SH_PFC_FUNCTION(msiof1), 4645 SH_PFC_FUNCTION(msiof1),
4585 SH_PFC_FUNCTION(msiof2), 4646 SH_PFC_FUNCTION(msiof2),
@@ -5416,11 +5477,20 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5416 { }, 5477 { },
5417}; 5478};
5418 5479
5480enum ioctrl_regs {
5481 POCCTRL,
5482};
5483
5484static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5485 [POCCTRL] = { 0xe6060380, },
5486 { /* sentinel */ },
5487};
5488
5419static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) 5489static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5420{ 5490{
5421 int bit = -EINVAL; 5491 int bit = -EINVAL;
5422 5492
5423 *pocctrl = 0xe6060380; 5493 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5424 5494
5425 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11)) 5495 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5426 bit = pin & 0x1f; 5496 bit = pin & 0x1f;
@@ -5431,242 +5501,261 @@ static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc
5431 return bit; 5501 return bit;
5432} 5502}
5433 5503
5434#define PUEN 0xe6060400 5504static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5435#define PUD 0xe6060440 5505 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5436 5506 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5437#define PU0 0x00 5507 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5438#define PU1 0x04 5508 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5439#define PU2 0x08 5509 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5440#define PU3 0x0c 5510 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5441#define PU4 0x10 5511 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5442#define PU5 0x14 5512 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5443#define PU6 0x18 5513 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5444 5514 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5445static const struct sh_pfc_bias_info bias_info[] = { 5515 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5446 { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */ 5516 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5447 { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */ 5517 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5448 { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */ 5518 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5449 { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */ 5519 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5450 { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */ 5520 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5451 { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */ 5521 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5452 { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */ 5522 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5453 { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */ 5523 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5454 { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */ 5524 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5455 { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */ 5525 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5456 { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */ 5526 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5457 { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */ 5527 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5458 { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */ 5528 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5459 { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */ 5529 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5460 { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */ 5530 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5461 { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */ 5531 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5462 { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */ 5532 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5463 { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */ 5533 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5464 { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */ 5534 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5465 { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */ 5535 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5466 { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */ 5536 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5467 { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */ 5537 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5468 { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */ 5538 } },
5469 { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */ 5539 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5470 { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */ 5540 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5471 { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */ 5541 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5472 { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */ 5542 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5473 { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */ 5543 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5474 { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */ 5544 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5475 { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */ 5545 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5476 { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */ 5546 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5477 { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */ 5547 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5478 5548 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5479 { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */ 5549 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5480 { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */ 5550 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5481 { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */ 5551 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5482 { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */ 5552 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5483 { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */ 5553 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5484 { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */ 5554 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5485 { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */ 5555 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5486 { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */ 5556 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5487 { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */ 5557 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5488 { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */ 5558 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5489 { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */ 5559 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5490 { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */ 5560 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5491 { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */ 5561 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5492 { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */ 5562 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5493 { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */ 5563 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5494 { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */ 5564 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5495 { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */ 5565 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5496 { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */ 5566 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5497 { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */ 5567 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5498 { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */ 5568 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5499 { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */ 5569 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5500 { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */ 5570 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5501 { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */ 5571 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5502 { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */ 5572 } },
5503 { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */ 5573 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5504 { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */ 5574 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
5505 { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */ 5575 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5506 { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */ 5576 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5507 { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */ 5577 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5508 { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */ 5578 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5509 { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */ 5579 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5510 { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */ 5580 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5511 5581 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5512 { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */ 5582 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5513 { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */ 5583 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
5514 { RCAR_GP_PIN(7, 3), PU2, 29 }, /* GP7_03 */ 5584 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5515 { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */ 5585 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5516 { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */ 5586 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5517 { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */ 5587 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5518 { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */ 5588 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5519 { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */ 5589 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5520 { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */ 5590 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5521 { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */ 5591 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5522 { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */ 5592 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5523 { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */ 5593 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5524 { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */ 5594 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5525 { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */ 5595 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5526 { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */ 5596 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5527 { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */ 5597 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5528 { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */ 5598 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5529 { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */ 5599 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5530 { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */ 5600 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5531 { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */ 5601 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
5532 { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */ 5602 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
5533 { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */ 5603 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
5534 { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */ 5604 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
5535 { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */ 5605 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
5536 { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */ 5606 } },
5537 { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */ 5607 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5538 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */ 5608 [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN2 */
5539 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */ 5609 [ 1] = PIN_NONE,
5540 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */ 5610 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
5541 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N */ 5611 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
5542 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */ 5612 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
5543 { RCAR_GP_PIN(1, 28), PU2, 0 }, /* CLKOUT */ 5613 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
5544 5614 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
5545 { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */ 5615 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
5546 { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */ 5616 [ 8] = PIN_NONE,
5547 { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */ 5617 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
5548 { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */ 5618 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5549 { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */ 5619 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
5550 { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */ 5620 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
5551 { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */ 5621 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
5552 { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */ 5622 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
5553 { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */ 5623 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
5554 { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */ 5624 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
5555 { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */ 5625 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
5556 { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */ 5626 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
5557 { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */ 5627 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
5558 { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */ 5628 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
5559 { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */ 5629 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
5560 { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */ 5630 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
5561 { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */ 5631 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
5562 { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */ 5632 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
5563 { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */ 5633 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
5564 { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */ 5634 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
5565 { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */ 5635 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
5566 { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */ 5636 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
5567 { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */ 5637 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
5568 /* bit 8 n/a */ 5638 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
5569 { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */ 5639 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
5570 { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */ 5640 } },
5571 { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */ 5641 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5572 { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */ 5642 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
5573 { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/ 5643 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
5574 { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST */ 5644 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
5575 /* bit 1 n/a on M3*/ 5645 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
5576 { PIN_A_NUMBER('R', 8), PU3, 0 }, /* DU_DOTCLKIN2 */ 5646 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
5577 5647 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
5578 { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */ 5648 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
5579 { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */ 5649 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
5580 { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */ 5650 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
5581 { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */ 5651 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
5582 { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */ 5652 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
5583 { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */ 5653 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
5584 { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */ 5654 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
5585 { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */ 5655 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
5586 { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */ 5656 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
5587 { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */ 5657 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
5588 { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */ 5658 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N_TANS */
5589 { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */ 5659 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
5590 { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */ 5660 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
5591 { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */ 5661 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
5592 { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */ 5662 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N_TANS */
5593 { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */ 5663 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
5594 { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */ 5664 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
5595 { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */ 5665 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
5596 { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */ 5666 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
5597 { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */ 5667 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
5598 { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */ 5668 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
5599 { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */ 5669 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
5600 { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */ 5670 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
5601 { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */ 5671 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
5602 { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */ 5672 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
5603 { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */ 5673 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
5604 { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */ 5674 } },
5605 { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */ 5675 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5606 { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */ 5676 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
5607 { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */ 5677 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
5608 { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */ 5678 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
5609 { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */ 5679 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
5610 5680 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
5611 { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */ 5681 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
5612 { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */ 5682 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
5613 { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */ 5683 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
5614 { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */ 5684 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
5615 { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */ 5685 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
5616 { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */ 5686 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
5617 { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */ 5687 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
5618 { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */ 5688 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
5619 { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */ 5689 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
5620 { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */ 5690 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
5621 { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */ 5691 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
5622 { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */ 5692 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
5623 { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */ 5693 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
5624 { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */ 5694 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
5625 { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */ 5695 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
5626 { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ 5696 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
5627 { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ 5697 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
5628 { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ 5698 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
5629 { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */ 5699 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
5630 { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */ 5700 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
5631 { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ 5701 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
5632 { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ 5702 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
5633 { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ 5703 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
5634 { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */ 5704 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
5635 { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */ 5705 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
5636 { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */ 5706 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
5637 { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */ 5707 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
5638 { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */ 5708 } },
5639 { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */ 5709 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
5640 { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */ 5710 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
5641 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */ 5711 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
5642 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */ 5712 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
5643 5713 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
5644 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* GP6_31 */ 5714 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
5645 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* GP6_30 */ 5715 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
5646 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */ 5716 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
5647 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */ 5717 [ 7] = PIN_NONE,
5648 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */ 5718 [ 8] = PIN_NONE,
5649 { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */ 5719 [ 9] = PIN_NONE,
5650 { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */ 5720 [10] = PIN_NONE,
5721 [11] = PIN_NONE,
5722 [12] = PIN_NONE,
5723 [13] = PIN_NONE,
5724 [14] = PIN_NONE,
5725 [15] = PIN_NONE,
5726 [16] = PIN_NONE,
5727 [17] = PIN_NONE,
5728 [18] = PIN_NONE,
5729 [19] = PIN_NONE,
5730 [20] = PIN_NONE,
5731 [21] = PIN_NONE,
5732 [22] = PIN_NONE,
5733 [23] = PIN_NONE,
5734 [24] = PIN_NONE,
5735 [25] = PIN_NONE,
5736 [26] = PIN_NONE,
5737 [27] = PIN_NONE,
5738 [28] = PIN_NONE,
5739 [29] = PIN_NONE,
5740 [30] = PIN_NONE,
5741 [31] = PIN_NONE,
5742 } },
5743 { /* sentinel */ },
5651}; 5744};
5652 5745
5653static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc, 5746static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
5654 unsigned int pin) 5747 unsigned int pin)
5655{ 5748{
5656 const struct sh_pfc_bias_info *info; 5749 const struct pinmux_bias_reg *reg;
5657 u32 reg; 5750 unsigned int bit;
5658 u32 bit;
5659 5751
5660 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); 5752 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5661 if (!info) 5753 if (!reg)
5662 return PIN_CONFIG_BIAS_DISABLE; 5754 return PIN_CONFIG_BIAS_DISABLE;
5663 5755
5664 reg = info->reg; 5756 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
5665 bit = BIT(info->bit);
5666
5667 if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
5668 return PIN_CONFIG_BIAS_DISABLE; 5757 return PIN_CONFIG_BIAS_DISABLE;
5669 else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit) 5758 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
5670 return PIN_CONFIG_BIAS_PULL_UP; 5759 return PIN_CONFIG_BIAS_PULL_UP;
5671 else 5760 else
5672 return PIN_CONFIG_BIAS_PULL_DOWN; 5761 return PIN_CONFIG_BIAS_PULL_DOWN;
@@ -5675,28 +5764,24 @@ static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
5675static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 5764static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5676 unsigned int bias) 5765 unsigned int bias)
5677{ 5766{
5678 const struct sh_pfc_bias_info *info; 5767 const struct pinmux_bias_reg *reg;
5679 u32 enable, updown; 5768 u32 enable, updown;
5680 u32 reg; 5769 unsigned int bit;
5681 u32 bit;
5682 5770
5683 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin); 5771 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5684 if (!info) 5772 if (!reg)
5685 return; 5773 return;
5686 5774
5687 reg = info->reg; 5775 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
5688 bit = BIT(info->bit);
5689
5690 enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
5691 if (bias != PIN_CONFIG_BIAS_DISABLE) 5776 if (bias != PIN_CONFIG_BIAS_DISABLE)
5692 enable |= bit; 5777 enable |= BIT(bit);
5693 5778
5694 updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit; 5779 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
5695 if (bias == PIN_CONFIG_BIAS_PULL_UP) 5780 if (bias == PIN_CONFIG_BIAS_PULL_UP)
5696 updown |= bit; 5781 updown |= BIT(bit);
5697 5782
5698 sh_pfc_write_reg(pfc, PUD + reg, 32, updown); 5783 sh_pfc_write(pfc, reg->pud, updown);
5699 sh_pfc_write_reg(pfc, PUEN + reg, 32, enable); 5784 sh_pfc_write(pfc, reg->puen, enable);
5700} 5785}
5701 5786
5702static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = { 5787static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
@@ -5721,6 +5806,8 @@ const struct sh_pfc_soc_info r8a7796_pinmux_info = {
5721 5806
5722 .cfg_regs = pinmux_config_regs, 5807 .cfg_regs = pinmux_config_regs,
5723 .drive_regs = pinmux_drive_regs, 5808 .drive_regs = pinmux_drive_regs,
5809 .bias_regs = pinmux_bias_regs,
5810 .ioctrl_regs = pinmux_ioctrl_regs,
5724 5811
5725 .pinmux_data = pinmux_data, 5812 .pinmux_data = pinmux_data,
5726 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 5813 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
index 4f5ee1d7317d..89b7541ab1ed 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
@@ -198,8 +198,8 @@
198#define GPSR6_0 FM(QSPI0_SPCLK) 198#define GPSR6_0 FM(QSPI0_SPCLK)
199 199
200/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ 200/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
201#define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) FM(USB0_IDIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 201#define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202#define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) FM(USB0_IDPU) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 202#define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203#define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 203#define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204#define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 204#define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205#define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 205#define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@@ -522,10 +522,8 @@ static const u16 pinmux_data[] = {
522 /* IPSR0 */ 522 /* IPSR0 */
523 PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0), 523 PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0),
524 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), 524 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
525 PINMUX_IPSR_GPSR(IP0_3_0, USB0_IDIN),
526 525
527 PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK), 526 PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK),
528 PINMUX_IPSR_GPSR(IP0_7_4, USB0_IDPU),
529 527
530 PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD), 528 PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD),
531 PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0), 529 PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0),
@@ -936,6 +934,129 @@ static const struct sh_pfc_pin pinmux_pins[] = {
936 PINMUX_GPIO_GP_ALL(), 934 PINMUX_GPIO_GP_ALL(),
937}; 935};
938 936
937/* - AUDIO CLOCK ------------------------------------------------------------- */
938static const unsigned int audio_clk_a_pins[] = {
939 /* CLK A */
940 RCAR_GP_PIN(4, 1),
941};
942static const unsigned int audio_clk_a_mux[] = {
943 AUDIO_CLKA_MARK,
944};
945static const unsigned int audio_clk_b_pins[] = {
946 /* CLK B */
947 RCAR_GP_PIN(2, 27),
948};
949static const unsigned int audio_clk_b_mux[] = {
950 AUDIO_CLKB_MARK,
951};
952static const unsigned int audio_clkout_pins[] = {
953 /* CLKOUT */
954 RCAR_GP_PIN(4, 5),
955};
956static const unsigned int audio_clkout_mux[] = {
957 AUDIO_CLKOUT_MARK,
958};
959static const unsigned int audio_clkout1_pins[] = {
960 /* CLKOUT1 */
961 RCAR_GP_PIN(4, 22),
962};
963static const unsigned int audio_clkout1_mux[] = {
964 AUDIO_CLKOUT1_MARK,
965};
966
967/* - EtherAVB --------------------------------------------------------------- */
968static const unsigned int avb0_link_pins[] = {
969 /* AVB0_LINK */
970 RCAR_GP_PIN(5, 20),
971};
972static const unsigned int avb0_link_mux[] = {
973 AVB0_LINK_MARK,
974};
975static const unsigned int avb0_magic_pins[] = {
976 /* AVB0_MAGIC */
977 RCAR_GP_PIN(5, 18),
978};
979static const unsigned int avb0_magic_mux[] = {
980 AVB0_MAGIC_MARK,
981};
982static const unsigned int avb0_phy_int_pins[] = {
983 /* AVB0_PHY_INT */
984 RCAR_GP_PIN(5, 19),
985};
986static const unsigned int avb0_phy_int_mux[] = {
987 AVB0_PHY_INT_MARK,
988};
989static const unsigned int avb0_mdc_pins[] = {
990 /* AVB0_MDC, AVB0_MDIO */
991 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 16),
992};
993static const unsigned int avb0_mdc_mux[] = {
994 AVB0_MDC_MARK, AVB0_MDIO_MARK,
995};
996static const unsigned int avb0_mii_pins[] = {
997 /*
998 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0,
999 * AVB0_TD1, AVB0_TD2, AVB0_TD3,
1000 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0,
1001 * AVB0_RD1, AVB0_RD2, AVB0_RD3,
1002 * AVB0_TXCREFCLK
1003 */
1004 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1005 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1006 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1007 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1008 RCAR_GP_PIN(5, 15),
1009};
1010static const unsigned int avb0_mii_mux[] = {
1011 AVB0_TX_CTL_MARK, AVB0_TXC_MARK, AVB0_TD0_MARK,
1012 AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
1013 AVB0_RX_CTL_MARK, AVB0_RXC_MARK, AVB0_RD0_MARK,
1014 AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
1015 AVB0_TXCREFCLK_MARK,
1016};
1017static const unsigned int avb0_avtp_pps_a_pins[] = {
1018 /* AVB0_AVTP_PPS_A */
1019 RCAR_GP_PIN(5, 2),
1020};
1021static const unsigned int avb0_avtp_pps_a_mux[] = {
1022 AVB0_AVTP_PPS_A_MARK,
1023};
1024static const unsigned int avb0_avtp_match_a_pins[] = {
1025 /* AVB0_AVTP_MATCH_A */
1026 RCAR_GP_PIN(5, 1),
1027};
1028static const unsigned int avb0_avtp_match_a_mux[] = {
1029 AVB0_AVTP_MATCH_A_MARK,
1030};
1031static const unsigned int avb0_avtp_capture_a_pins[] = {
1032 /* AVB0_AVTP_CAPTURE_A */
1033 RCAR_GP_PIN(5, 0),
1034};
1035static const unsigned int avb0_avtp_capture_a_mux[] = {
1036 AVB0_AVTP_CAPTURE_A_MARK,
1037};
1038static const unsigned int avb0_avtp_pps_b_pins[] = {
1039 /* AVB0_AVTP_PPS_B */
1040 RCAR_GP_PIN(4, 16),
1041};
1042static const unsigned int avb0_avtp_pps_b_mux[] = {
1043 AVB0_AVTP_PPS_B_MARK,
1044};
1045static const unsigned int avb0_avtp_match_b_pins[] = {
1046 /* AVB0_AVTP_MATCH_B */
1047 RCAR_GP_PIN(4, 18),
1048};
1049static const unsigned int avb0_avtp_match_b_mux[] = {
1050 AVB0_AVTP_MATCH_B_MARK,
1051};
1052static const unsigned int avb0_avtp_capture_b_pins[] = {
1053 /* AVB0_AVTP_CAPTURE_B */
1054 RCAR_GP_PIN(4, 17),
1055};
1056static const unsigned int avb0_avtp_capture_b_mux[] = {
1057 AVB0_AVTP_CAPTURE_B_MARK,
1058};
1059
939/* - I2C -------------------------------------------------------------------- */ 1060/* - I2C -------------------------------------------------------------------- */
940static const unsigned int i2c0_pins[] = { 1061static const unsigned int i2c0_pins[] = {
941 /* SCL, SDA */ 1062 /* SCL, SDA */
@@ -1018,6 +1139,118 @@ static const unsigned int mmc_ctrl_mux[] = {
1018 MMC_CLK_MARK, MMC_CMD_MARK, 1139 MMC_CLK_MARK, MMC_CMD_MARK,
1019}; 1140};
1020 1141
1142/* - PWM0 ------------------------------------------------------------------ */
1143static const unsigned int pwm0_a_pins[] = {
1144 /* PWM */
1145 RCAR_GP_PIN(2, 1),
1146};
1147
1148static const unsigned int pwm0_a_mux[] = {
1149 PWM0_A_MARK,
1150};
1151
1152static const unsigned int pwm0_b_pins[] = {
1153 /* PWM */
1154 RCAR_GP_PIN(1, 18),
1155};
1156
1157static const unsigned int pwm0_b_mux[] = {
1158 PWM0_B_MARK,
1159};
1160
1161static const unsigned int pwm0_c_pins[] = {
1162 /* PWM */
1163 RCAR_GP_PIN(2, 29),
1164};
1165
1166static const unsigned int pwm0_c_mux[] = {
1167 PWM0_C_MARK,
1168};
1169
1170/* - PWM1 ------------------------------------------------------------------ */
1171static const unsigned int pwm1_a_pins[] = {
1172 /* PWM */
1173 RCAR_GP_PIN(2, 2),
1174};
1175
1176static const unsigned int pwm1_a_mux[] = {
1177 PWM1_A_MARK,
1178};
1179
1180static const unsigned int pwm1_b_pins[] = {
1181 /* PWM */
1182 RCAR_GP_PIN(1, 19),
1183};
1184
1185static const unsigned int pwm1_b_mux[] = {
1186 PWM1_B_MARK,
1187};
1188
1189static const unsigned int pwm1_c_pins[] = {
1190 /* PWM */
1191 RCAR_GP_PIN(2, 30),
1192};
1193
1194static const unsigned int pwm1_c_mux[] = {
1195 PWM1_C_MARK,
1196};
1197
1198/* - PWM2 ------------------------------------------------------------------ */
1199static const unsigned int pwm2_a_pins[] = {
1200 /* PWM */
1201 RCAR_GP_PIN(2, 3),
1202};
1203
1204static const unsigned int pwm2_a_mux[] = {
1205 PWM2_A_MARK,
1206};
1207
1208static const unsigned int pwm2_b_pins[] = {
1209 /* PWM */
1210 RCAR_GP_PIN(1, 22),
1211};
1212
1213static const unsigned int pwm2_b_mux[] = {
1214 PWM2_B_MARK,
1215};
1216
1217static const unsigned int pwm2_c_pins[] = {
1218 /* PWM */
1219 RCAR_GP_PIN(2, 31),
1220};
1221
1222static const unsigned int pwm2_c_mux[] = {
1223 PWM2_C_MARK,
1224};
1225
1226/* - PWM3 ------------------------------------------------------------------ */
1227static const unsigned int pwm3_a_pins[] = {
1228 /* PWM */
1229 RCAR_GP_PIN(2, 4),
1230};
1231
1232static const unsigned int pwm3_a_mux[] = {
1233 PWM3_A_MARK,
1234};
1235
1236static const unsigned int pwm3_b_pins[] = {
1237 /* PWM */
1238 RCAR_GP_PIN(1, 27),
1239};
1240
1241static const unsigned int pwm3_b_mux[] = {
1242 PWM3_B_MARK,
1243};
1244
1245static const unsigned int pwm3_c_pins[] = {
1246 /* PWM */
1247 RCAR_GP_PIN(4, 0),
1248};
1249
1250static const unsigned int pwm3_c_mux[] = {
1251 PWM3_C_MARK,
1252};
1253
1021/* - SCIF0 ------------------------------------------------------------------ */ 1254/* - SCIF0 ------------------------------------------------------------------ */
1022static const unsigned int scif0_data_a_pins[] = { 1255static const unsigned int scif0_data_a_pins[] = {
1023 /* RX, TX */ 1256 /* RX, TX */
@@ -1202,7 +1435,75 @@ static const unsigned int scif_clk_mux[] = {
1202 SCIF_CLK_MARK, 1435 SCIF_CLK_MARK,
1203}; 1436};
1204 1437
1438/* - SSI ---------------------------------------------------------------*/
1439static const unsigned int ssi3_data_pins[] = {
1440 /* SDATA */
1441 RCAR_GP_PIN(4, 3),
1442};
1443static const unsigned int ssi3_data_mux[] = {
1444 SSI_SDATA3_MARK,
1445};
1446static const unsigned int ssi34_ctrl_pins[] = {
1447 /* SCK, WS */
1448 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 4),
1449};
1450static const unsigned int ssi34_ctrl_mux[] = {
1451 SSI_SCK34_MARK, SSI_WS34_MARK,
1452};
1453static const unsigned int ssi4_ctrl_a_pins[] = {
1454 /* SCK, WS */
1455 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
1456};
1457static const unsigned int ssi4_ctrl_a_mux[] = {
1458 SSI_SCK4_A_MARK, SSI_WS4_A_MARK,
1459};
1460static const unsigned int ssi4_data_a_pins[] = {
1461 /* SDATA */
1462 RCAR_GP_PIN(4, 6),
1463};
1464static const unsigned int ssi4_data_a_mux[] = {
1465 SSI_SDATA4_A_MARK,
1466};
1467static const unsigned int ssi4_ctrl_b_pins[] = {
1468 /* SCK, WS */
1469 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 20),
1470};
1471static const unsigned int ssi4_ctrl_b_mux[] = {
1472 SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
1473};
1474static const unsigned int ssi4_data_b_pins[] = {
1475 /* SDATA */
1476 RCAR_GP_PIN(2, 16),
1477};
1478static const unsigned int ssi4_data_b_mux[] = {
1479 SSI_SDATA4_B_MARK,
1480};
1481
1482/* - USB0 ------------------------------------------------------------------- */
1483static const unsigned int usb0_pins[] = {
1484 /* PWEN, OVC */
1485 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
1486};
1487static const unsigned int usb0_mux[] = {
1488 USB0_PWEN_MARK, USB0_OVC_MARK,
1489};
1490
1205static const struct sh_pfc_pin_group pinmux_groups[] = { 1491static const struct sh_pfc_pin_group pinmux_groups[] = {
1492 SH_PFC_PIN_GROUP(audio_clk_a),
1493 SH_PFC_PIN_GROUP(audio_clk_b),
1494 SH_PFC_PIN_GROUP(audio_clkout),
1495 SH_PFC_PIN_GROUP(audio_clkout1),
1496 SH_PFC_PIN_GROUP(avb0_link),
1497 SH_PFC_PIN_GROUP(avb0_magic),
1498 SH_PFC_PIN_GROUP(avb0_phy_int),
1499 SH_PFC_PIN_GROUP(avb0_mdc),
1500 SH_PFC_PIN_GROUP(avb0_mii),
1501 SH_PFC_PIN_GROUP(avb0_avtp_pps_a),
1502 SH_PFC_PIN_GROUP(avb0_avtp_match_a),
1503 SH_PFC_PIN_GROUP(avb0_avtp_capture_a),
1504 SH_PFC_PIN_GROUP(avb0_avtp_pps_b),
1505 SH_PFC_PIN_GROUP(avb0_avtp_match_b),
1506 SH_PFC_PIN_GROUP(avb0_avtp_capture_b),
1206 SH_PFC_PIN_GROUP(i2c0), 1507 SH_PFC_PIN_GROUP(i2c0),
1207 SH_PFC_PIN_GROUP(i2c1), 1508 SH_PFC_PIN_GROUP(i2c1),
1208 SH_PFC_PIN_GROUP(i2c2_a), 1509 SH_PFC_PIN_GROUP(i2c2_a),
@@ -1213,6 +1514,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
1213 SH_PFC_PIN_GROUP(mmc_data4), 1514 SH_PFC_PIN_GROUP(mmc_data4),
1214 SH_PFC_PIN_GROUP(mmc_data8), 1515 SH_PFC_PIN_GROUP(mmc_data8),
1215 SH_PFC_PIN_GROUP(mmc_ctrl), 1516 SH_PFC_PIN_GROUP(mmc_ctrl),
1517 SH_PFC_PIN_GROUP(pwm0_a),
1518 SH_PFC_PIN_GROUP(pwm0_b),
1519 SH_PFC_PIN_GROUP(pwm0_c),
1520 SH_PFC_PIN_GROUP(pwm1_a),
1521 SH_PFC_PIN_GROUP(pwm1_b),
1522 SH_PFC_PIN_GROUP(pwm1_c),
1523 SH_PFC_PIN_GROUP(pwm2_a),
1524 SH_PFC_PIN_GROUP(pwm2_b),
1525 SH_PFC_PIN_GROUP(pwm2_c),
1526 SH_PFC_PIN_GROUP(pwm3_a),
1527 SH_PFC_PIN_GROUP(pwm3_b),
1528 SH_PFC_PIN_GROUP(pwm3_c),
1216 SH_PFC_PIN_GROUP(scif0_data_a), 1529 SH_PFC_PIN_GROUP(scif0_data_a),
1217 SH_PFC_PIN_GROUP(scif0_clk_a), 1530 SH_PFC_PIN_GROUP(scif0_clk_a),
1218 SH_PFC_PIN_GROUP(scif0_data_b), 1531 SH_PFC_PIN_GROUP(scif0_data_b),
@@ -1238,6 +1551,34 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
1238 SH_PFC_PIN_GROUP(scif5_data_b), 1551 SH_PFC_PIN_GROUP(scif5_data_b),
1239 SH_PFC_PIN_GROUP(scif5_clk_b), 1552 SH_PFC_PIN_GROUP(scif5_clk_b),
1240 SH_PFC_PIN_GROUP(scif_clk), 1553 SH_PFC_PIN_GROUP(scif_clk),
1554 SH_PFC_PIN_GROUP(ssi3_data),
1555 SH_PFC_PIN_GROUP(ssi34_ctrl),
1556 SH_PFC_PIN_GROUP(ssi4_ctrl_a),
1557 SH_PFC_PIN_GROUP(ssi4_data_a),
1558 SH_PFC_PIN_GROUP(ssi4_ctrl_b),
1559 SH_PFC_PIN_GROUP(ssi4_data_b),
1560 SH_PFC_PIN_GROUP(usb0),
1561};
1562
1563static const char * const audio_clk_groups[] = {
1564 "audio_clk_a",
1565 "audio_clk_b",
1566 "audio_clkout",
1567 "audio_clkout1",
1568};
1569
1570static const char * const avb0_groups[] = {
1571 "avb0_link",
1572 "avb0_magic",
1573 "avb0_phy_int",
1574 "avb0_mdc",
1575 "avb0_mii",
1576 "avb0_avtp_pps_a",
1577 "avb0_avtp_match_a",
1578 "avb0_avtp_capture_a",
1579 "avb0_avtp_pps_b",
1580 "avb0_avtp_match_b",
1581 "avb0_avtp_capture_b",
1241}; 1582};
1242 1583
1243static const char * const i2c0_groups[] = { 1584static const char * const i2c0_groups[] = {
@@ -1264,6 +1605,30 @@ static const char * const mmc_groups[] = {
1264 "mmc_ctrl", 1605 "mmc_ctrl",
1265}; 1606};
1266 1607
1608static const char * const pwm0_groups[] = {
1609 "pwm0_a",
1610 "pwm0_b",
1611 "pwm0_c",
1612};
1613
1614static const char * const pwm1_groups[] = {
1615 "pwm1_a",
1616 "pwm1_b",
1617 "pwm1_c",
1618};
1619
1620static const char * const pwm2_groups[] = {
1621 "pwm2_a",
1622 "pwm2_b",
1623 "pwm2_c",
1624};
1625
1626static const char * const pwm3_groups[] = {
1627 "pwm3_a",
1628 "pwm3_b",
1629 "pwm3_c",
1630};
1631
1267static const char * const scif0_groups[] = { 1632static const char * const scif0_groups[] = {
1268 "scif0_data_a", 1633 "scif0_data_a",
1269 "scif0_clk_a", 1634 "scif0_clk_a",
@@ -1310,12 +1675,31 @@ static const char * const scif_clk_groups[] = {
1310 "scif_clk", 1675 "scif_clk",
1311}; 1676};
1312 1677
1678static const char * const ssi_groups[] = {
1679 "ssi3_data",
1680 "ssi34_ctrl",
1681 "ssi4_ctrl_a",
1682 "ssi4_data_a",
1683 "ssi4_ctrl_b",
1684 "ssi4_data_b",
1685};
1686
1687static const char * const usb0_groups[] = {
1688 "usb0",
1689};
1690
1313static const struct sh_pfc_function pinmux_functions[] = { 1691static const struct sh_pfc_function pinmux_functions[] = {
1692 SH_PFC_FUNCTION(audio_clk),
1693 SH_PFC_FUNCTION(avb0),
1314 SH_PFC_FUNCTION(i2c0), 1694 SH_PFC_FUNCTION(i2c0),
1315 SH_PFC_FUNCTION(i2c1), 1695 SH_PFC_FUNCTION(i2c1),
1316 SH_PFC_FUNCTION(i2c2), 1696 SH_PFC_FUNCTION(i2c2),
1317 SH_PFC_FUNCTION(i2c3), 1697 SH_PFC_FUNCTION(i2c3),
1318 SH_PFC_FUNCTION(mmc), 1698 SH_PFC_FUNCTION(mmc),
1699 SH_PFC_FUNCTION(pwm0),
1700 SH_PFC_FUNCTION(pwm1),
1701 SH_PFC_FUNCTION(pwm2),
1702 SH_PFC_FUNCTION(pwm3),
1319 SH_PFC_FUNCTION(scif0), 1703 SH_PFC_FUNCTION(scif0),
1320 SH_PFC_FUNCTION(scif1), 1704 SH_PFC_FUNCTION(scif1),
1321 SH_PFC_FUNCTION(scif2), 1705 SH_PFC_FUNCTION(scif2),
@@ -1323,6 +1707,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
1323 SH_PFC_FUNCTION(scif4), 1707 SH_PFC_FUNCTION(scif4),
1324 SH_PFC_FUNCTION(scif5), 1708 SH_PFC_FUNCTION(scif5),
1325 SH_PFC_FUNCTION(scif_clk), 1709 SH_PFC_FUNCTION(scif_clk),
1710 SH_PFC_FUNCTION(ssi),
1711 SH_PFC_FUNCTION(usb0),
1326}; 1712};
1327 1713
1328static const struct pinmux_cfg_reg pinmux_config_regs[] = { 1714static const struct pinmux_cfg_reg pinmux_config_regs[] = {
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 5c9d79981e6d..736634aee500 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -513,7 +513,7 @@ static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc,
513 return -EINVAL; 513 return -EINVAL;
514 514
515 spin_lock_irqsave(&pfc->lock, flags); 515 spin_lock_irqsave(&pfc->lock, flags);
516 val = sh_pfc_read_reg(pfc, reg, 32); 516 val = sh_pfc_read(pfc, reg);
517 spin_unlock_irqrestore(&pfc->lock, flags); 517 spin_unlock_irqrestore(&pfc->lock, flags);
518 518
519 val = (val >> offset) & GENMASK(size - 1, 0); 519 val = (val >> offset) & GENMASK(size - 1, 0);
@@ -550,11 +550,11 @@ static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
550 550
551 spin_lock_irqsave(&pfc->lock, flags); 551 spin_lock_irqsave(&pfc->lock, flags);
552 552
553 val = sh_pfc_read_reg(pfc, reg, 32); 553 val = sh_pfc_read(pfc, reg);
554 val &= ~GENMASK(offset + size - 1, offset); 554 val &= ~GENMASK(offset + size - 1, offset);
555 val |= strength << offset; 555 val |= strength << offset;
556 556
557 sh_pfc_write_reg(pfc, reg, 32, val); 557 sh_pfc_write(pfc, reg, val);
558 558
559 spin_unlock_irqrestore(&pfc->lock, flags); 559 spin_unlock_irqrestore(&pfc->lock, flags);
560 560
@@ -645,7 +645,7 @@ static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
645 return bit; 645 return bit;
646 646
647 spin_lock_irqsave(&pfc->lock, flags); 647 spin_lock_irqsave(&pfc->lock, flags);
648 val = sh_pfc_read_reg(pfc, pocctrl, 32); 648 val = sh_pfc_read(pfc, pocctrl);
649 spin_unlock_irqrestore(&pfc->lock, flags); 649 spin_unlock_irqrestore(&pfc->lock, flags);
650 650
651 arg = (val & BIT(bit)) ? 3300 : 1800; 651 arg = (val & BIT(bit)) ? 3300 : 1800;
@@ -716,12 +716,12 @@ static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
716 return -EINVAL; 716 return -EINVAL;
717 717
718 spin_lock_irqsave(&pfc->lock, flags); 718 spin_lock_irqsave(&pfc->lock, flags);
719 val = sh_pfc_read_reg(pfc, pocctrl, 32); 719 val = sh_pfc_read(pfc, pocctrl);
720 if (mV == 3300) 720 if (mV == 3300)
721 val |= BIT(bit); 721 val |= BIT(bit);
722 else 722 else
723 val &= ~BIT(bit); 723 val &= ~BIT(bit);
724 sh_pfc_write_reg(pfc, pocctrl, 32, val); 724 sh_pfc_write(pfc, pocctrl, val);
725 spin_unlock_irqrestore(&pfc->lock, flags); 725 spin_unlock_irqrestore(&pfc->lock, flags);
726 726
727 break; 727 break;
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 8688b405e081..213108a058fe 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -148,6 +148,21 @@ struct pinmux_drive_reg {
148 .reg = r, \ 148 .reg = r, \
149 .fields = 149 .fields =
150 150
151struct pinmux_bias_reg {
152 u32 puen; /* Pull-enable or pull-up control register */
153 u32 pud; /* Pull-up/down control register (optional) */
154 const u16 pins[32];
155};
156
157#define PINMUX_BIAS_REG(name1, r1, name2, r2) \
158 .puen = r1, \
159 .pud = r2, \
160 .pins =
161
162struct pinmux_ioctrl_reg {
163 u32 reg;
164};
165
151struct pinmux_data_reg { 166struct pinmux_data_reg {
152 u32 reg; 167 u32 reg;
153 u8 reg_width; 168 u8 reg_width;
@@ -189,12 +204,6 @@ struct sh_pfc_window {
189 unsigned long size; 204 unsigned long size;
190}; 205};
191 206
192struct sh_pfc_bias_info {
193 u16 pin;
194 u16 reg : 11;
195 u16 bit : 5;
196};
197
198struct sh_pfc_pin_range; 207struct sh_pfc_pin_range;
199 208
200struct sh_pfc { 209struct sh_pfc {
@@ -213,6 +222,7 @@ struct sh_pfc {
213 unsigned int nr_gpio_pins; 222 unsigned int nr_gpio_pins;
214 223
215 struct sh_pfc_chip *gpio; 224 struct sh_pfc_chip *gpio;
225 u32 *saved_regs;
216}; 226};
217 227
218struct sh_pfc_soc_operations { 228struct sh_pfc_soc_operations {
@@ -245,6 +255,8 @@ struct sh_pfc_soc_info {
245 255
246 const struct pinmux_cfg_reg *cfg_regs; 256 const struct pinmux_cfg_reg *cfg_regs;
247 const struct pinmux_drive_reg *drive_regs; 257 const struct pinmux_drive_reg *drive_regs;
258 const struct pinmux_bias_reg *bias_regs;
259 const struct pinmux_ioctrl_reg *ioctrl_regs;
248 const struct pinmux_data_reg *data_regs; 260 const struct pinmux_data_reg *data_regs;
249 261
250 const u16 *pinmux_data; 262 const u16 *pinmux_data;
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas7.c b/drivers/pinctrl/sirf/pinctrl-atlas7.c
index f5cef6e5fa3e..3abb028f6158 100644
--- a/drivers/pinctrl/sirf/pinctrl-atlas7.c
+++ b/drivers/pinctrl/sirf/pinctrl-atlas7.c
@@ -5860,7 +5860,7 @@ static int atlas7_gpio_request(struct gpio_chip *chip,
5860 if (ret < 0) 5860 if (ret < 0)
5861 return ret; 5861 return ret;
5862 5862
5863 if (pinctrl_request_gpio(chip->base + gpio)) 5863 if (pinctrl_gpio_request(chip->base + gpio))
5864 return -ENODEV; 5864 return -ENODEV;
5865 5865
5866 raw_spin_lock_irqsave(&a7gc->lock, flags); 5866 raw_spin_lock_irqsave(&a7gc->lock, flags);
@@ -5890,7 +5890,7 @@ static void atlas7_gpio_free(struct gpio_chip *chip,
5890 5890
5891 raw_spin_unlock_irqrestore(&a7gc->lock, flags); 5891 raw_spin_unlock_irqrestore(&a7gc->lock, flags);
5892 5892
5893 pinctrl_free_gpio(chip->base + gpio); 5893 pinctrl_gpio_free(chip->base + gpio);
5894} 5894}
5895 5895
5896static int atlas7_gpio_direction_input(struct gpio_chip *chip, 5896static int atlas7_gpio_direction_input(struct gpio_chip *chip,
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c
index 8b14a1f1e671..ca2347d0d579 100644
--- a/drivers/pinctrl/sirf/pinctrl-sirf.c
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.c
@@ -614,7 +614,7 @@ static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
614 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset); 614 struct sirfsoc_gpio_bank *bank = sirfsoc_gpio_to_bank(sgpio, offset);
615 unsigned long flags; 615 unsigned long flags;
616 616
617 if (pinctrl_request_gpio(chip->base + offset)) 617 if (pinctrl_gpio_request(chip->base + offset))
618 return -ENODEV; 618 return -ENODEV;
619 619
620 spin_lock_irqsave(&bank->lock, flags); 620 spin_lock_irqsave(&bank->lock, flags);
@@ -644,7 +644,7 @@ static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
644 644
645 spin_unlock_irqrestore(&bank->lock, flags); 645 spin_unlock_irqrestore(&bank->lock, flags);
646 646
647 pinctrl_free_gpio(chip->base + offset); 647 pinctrl_gpio_free(chip->base + offset);
648} 648}
649 649
650static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) 650static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c
index 72ae6bccee55..6a0ed8ab33b9 100644
--- a/drivers/pinctrl/spear/pinctrl-plgpio.c
+++ b/drivers/pinctrl/spear/pinctrl-plgpio.c
@@ -204,7 +204,7 @@ static int plgpio_request(struct gpio_chip *chip, unsigned offset)
204 if (offset >= chip->ngpio) 204 if (offset >= chip->ngpio)
205 return -EINVAL; 205 return -EINVAL;
206 206
207 ret = pinctrl_request_gpio(gpio); 207 ret = pinctrl_gpio_request(gpio);
208 if (ret) 208 if (ret)
209 return ret; 209 return ret;
210 210
@@ -242,7 +242,7 @@ err1:
242 if (!IS_ERR(plgpio->clk)) 242 if (!IS_ERR(plgpio->clk))
243 clk_disable(plgpio->clk); 243 clk_disable(plgpio->clk);
244err0: 244err0:
245 pinctrl_free_gpio(gpio); 245 pinctrl_gpio_free(gpio);
246 return ret; 246 return ret;
247} 247}
248 248
@@ -273,7 +273,7 @@ disable_clk:
273 if (!IS_ERR(plgpio->clk)) 273 if (!IS_ERR(plgpio->clk))
274 clk_disable(plgpio->clk); 274 clk_disable(plgpio->clk);
275 275
276 pinctrl_free_gpio(gpio); 276 pinctrl_gpio_free(gpio);
277} 277}
278 278
279/* PLGPIO IRQ */ 279/* PLGPIO IRQ */
diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c
index 02b66588cac6..a276c61be217 100644
--- a/drivers/pinctrl/stm32/pinctrl-stm32.c
+++ b/drivers/pinctrl/stm32/pinctrl-stm32.c
@@ -150,12 +150,12 @@ static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
150 return -EINVAL; 150 return -EINVAL;
151 } 151 }
152 152
153 return pinctrl_request_gpio(chip->base + offset); 153 return pinctrl_gpio_request(chip->base + offset);
154} 154}
155 155
156static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset) 156static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
157{ 157{
158 pinctrl_free_gpio(chip->base + offset); 158 pinctrl_gpio_free(chip->base + offset);
159} 159}
160 160
161static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) 161static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index f763d8d62d6e..295e48fc94bc 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
@@ -1289,6 +1289,7 @@ static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
1289 .npins = ARRAY_SIZE(sun4i_a10_pins), 1289 .npins = ARRAY_SIZE(sun4i_a10_pins),
1290 .irq_banks = 1, 1290 .irq_banks = 1,
1291 .irq_read_needs_mux = true, 1291 .irq_read_needs_mux = true,
1292 .disable_strict_mode = true,
1292}; 1293};
1293 1294
1294static int sun4i_a10_pinctrl_probe(struct platform_device *pdev) 1295static int sun4i_a10_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i.c b/drivers/pinctrl/sunxi/pinctrl-sun5i.c
index 47afd558b114..27ec99e81c4c 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun5i.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun5i.c
@@ -713,6 +713,7 @@ static const struct sunxi_pinctrl_desc sun5i_pinctrl_data = {
713 .pins = sun5i_pins, 713 .pins = sun5i_pins,
714 .npins = ARRAY_SIZE(sun5i_pins), 714 .npins = ARRAY_SIZE(sun5i_pins),
715 .irq_banks = 1, 715 .irq_banks = 1,
716 .disable_strict_mode = true,
716}; 717};
717 718
718static int sun5i_pinctrl_probe(struct platform_device *pdev) 719static int sun5i_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
index 49a1deb97bb7..a00246d3dd49 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
@@ -106,6 +106,7 @@ static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = {
106 .npins = ARRAY_SIZE(sun6i_a31_r_pins), 106 .npins = ARRAY_SIZE(sun6i_a31_r_pins),
107 .pin_base = PL_BASE, 107 .pin_base = PL_BASE,
108 .irq_banks = 2, 108 .irq_banks = 2,
109 .disable_strict_mode = true,
109}; 110};
110 111
111static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev) 112static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
index 951a25c18815..82ffaf466892 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
@@ -965,6 +965,7 @@ static const struct sunxi_pinctrl_desc sun6i_a31_pinctrl_data = {
965 .pins = sun6i_a31_pins, 965 .pins = sun6i_a31_pins,
966 .npins = ARRAY_SIZE(sun6i_a31_pins), 966 .npins = ARRAY_SIZE(sun6i_a31_pins),
967 .irq_banks = 4, 967 .irq_banks = 4,
968 .disable_strict_mode = true,
968}; 969};
969 970
970static int sun6i_a31_pinctrl_probe(struct platform_device *pdev) 971static int sun6i_a31_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
index 67ee6f9b3b68..8a08c4afc6a8 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
@@ -93,6 +93,7 @@ static const struct sunxi_pinctrl_desc sun8i_a23_r_pinctrl_data = {
93 .npins = ARRAY_SIZE(sun8i_a23_r_pins), 93 .npins = ARRAY_SIZE(sun8i_a23_r_pins),
94 .pin_base = PL_BASE, 94 .pin_base = PL_BASE,
95 .irq_banks = 1, 95 .irq_banks = 1,
96 .disable_strict_mode = true,
96}; 97};
97 98
98static int sun8i_a23_r_pinctrl_probe(struct platform_device *pdev) 99static int sun8i_a23_r_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
index 721b6935baf3..402fd7d21e7b 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
@@ -563,6 +563,7 @@ static const struct sunxi_pinctrl_desc sun8i_a23_pinctrl_data = {
563 .pins = sun8i_a23_pins, 563 .pins = sun8i_a23_pins,
564 .npins = ARRAY_SIZE(sun8i_a23_pins), 564 .npins = ARRAY_SIZE(sun8i_a23_pins),
565 .irq_banks = 3, 565 .irq_banks = 3,
566 .disable_strict_mode = true,
566}; 567};
567 568
568static int sun8i_a23_pinctrl_probe(struct platform_device *pdev) 569static int sun8i_a23_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
index ef1e0bef4099..da387211a75e 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
@@ -486,6 +486,7 @@ static const struct sunxi_pinctrl_desc sun8i_a33_pinctrl_data = {
486 .npins = ARRAY_SIZE(sun8i_a33_pins), 486 .npins = ARRAY_SIZE(sun8i_a33_pins),
487 .irq_banks = 2, 487 .irq_banks = 2,
488 .irq_bank_base = 1, 488 .irq_bank_base = 1,
489 .disable_strict_mode = true,
489}; 490};
490 491
491static int sun8i_a33_pinctrl_probe(struct platform_device *pdev) 492static int sun8i_a33_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c
index ebfd9a26628c..b795a199e240 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c
@@ -82,7 +82,8 @@ static const struct sunxi_pinctrl_desc sun8i_h3_r_pinctrl_data = {
82 .npins = ARRAY_SIZE(sun8i_h3_r_pins), 82 .npins = ARRAY_SIZE(sun8i_h3_r_pins),
83 .irq_banks = 1, 83 .irq_banks = 1,
84 .pin_base = PL_BASE, 84 .pin_base = PL_BASE,
85 .irq_read_needs_mux = true 85 .irq_read_needs_mux = true,
86 .disable_strict_mode = true,
86}; 87};
87 88
88static int sun8i_h3_r_pinctrl_probe(struct platform_device *pdev) 89static int sun8i_h3_r_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c
index 518a92df4418..d1719a738c20 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c
@@ -491,7 +491,8 @@ static const struct sunxi_pinctrl_desc sun8i_h3_pinctrl_data = {
491 .pins = sun8i_h3_pins, 491 .pins = sun8i_h3_pins,
492 .npins = ARRAY_SIZE(sun8i_h3_pins), 492 .npins = ARRAY_SIZE(sun8i_h3_pins),
493 .irq_banks = 2, 493 .irq_banks = 2,
494 .irq_read_needs_mux = true 494 .irq_read_needs_mux = true,
495 .disable_strict_mode = true,
495}; 496};
496 497
497static int sun8i_h3_pinctrl_probe(struct platform_device *pdev) 498static int sun8i_h3_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
index 92a873f73697..c63086c98335 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
@@ -152,6 +152,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = {
152 .npins = ARRAY_SIZE(sun9i_a80_r_pins), 152 .npins = ARRAY_SIZE(sun9i_a80_r_pins),
153 .pin_base = PL_BASE, 153 .pin_base = PL_BASE,
154 .irq_banks = 2, 154 .irq_banks = 2,
155 .disable_strict_mode = true,
155}; 156};
156 157
157static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev) 158static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c
index bc14e954d7a2..472ef0d91b99 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c
@@ -721,6 +721,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_data = {
721 .pins = sun9i_a80_pins, 721 .pins = sun9i_a80_pins,
722 .npins = ARRAY_SIZE(sun9i_a80_pins), 722 .npins = ARRAY_SIZE(sun9i_a80_pins),
723 .irq_banks = 5, 723 .irq_banks = 5,
724 .disable_strict_mode = true,
724}; 725};
725 726
726static int sun9i_a80_pinctrl_probe(struct platform_device *pdev) 727static int sun9i_a80_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 52edf3b5988d..4b6cb25bc796 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -696,6 +696,7 @@ static const struct pinmux_ops sunxi_pmx_ops = {
696 .get_function_groups = sunxi_pmx_get_func_groups, 696 .get_function_groups = sunxi_pmx_get_func_groups,
697 .set_mux = sunxi_pmx_set_mux, 697 .set_mux = sunxi_pmx_set_mux,
698 .gpio_set_direction = sunxi_pmx_gpio_set_direction, 698 .gpio_set_direction = sunxi_pmx_gpio_set_direction,
699 .strict = true,
699}; 700};
700 701
701static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, 702static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
@@ -1245,6 +1246,7 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
1245 struct pinctrl_desc *pctrl_desc; 1246 struct pinctrl_desc *pctrl_desc;
1246 struct pinctrl_pin_desc *pins; 1247 struct pinctrl_pin_desc *pins;
1247 struct sunxi_pinctrl *pctl; 1248 struct sunxi_pinctrl *pctl;
1249 struct pinmux_ops *pmxops;
1248 struct resource *res; 1250 struct resource *res;
1249 int i, ret, last_pin, pin_idx; 1251 int i, ret, last_pin, pin_idx;
1250 struct clk *clk; 1252 struct clk *clk;
@@ -1305,7 +1307,16 @@ int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
1305 pctrl_desc->npins = pctl->ngroups; 1307 pctrl_desc->npins = pctl->ngroups;
1306 pctrl_desc->confops = &sunxi_pconf_ops; 1308 pctrl_desc->confops = &sunxi_pconf_ops;
1307 pctrl_desc->pctlops = &sunxi_pctrl_ops; 1309 pctrl_desc->pctlops = &sunxi_pctrl_ops;
1308 pctrl_desc->pmxops = &sunxi_pmx_ops; 1310
1311 pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops),
1312 GFP_KERNEL);
1313 if (!pmxops)
1314 return -ENOMEM;
1315
1316 if (desc->disable_strict_mode)
1317 pmxops->strict = false;
1318
1319 pctrl_desc->pmxops = pmxops;
1309 1320
1310 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl); 1321 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
1311 if (IS_ERR(pctl->pctl_dev)) { 1322 if (IS_ERR(pctl->pctl_dev)) {
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index 1bfc0d8a55df..11b128f54ed2 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -112,6 +112,7 @@ struct sunxi_pinctrl_desc {
112 unsigned irq_banks; 112 unsigned irq_banks;
113 unsigned irq_bank_base; 113 unsigned irq_bank_base;
114 bool irq_read_needs_mux; 114 bool irq_read_needs_mux;
115 bool disable_strict_mode;
115}; 116};
116 117
117struct sunxi_pinctrl_function { 118struct sunxi_pinctrl_function {
diff --git a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c
index 5c1b6325d80d..a8a6510183b6 100644
--- a/drivers/pinctrl/ti/pinctrl-ti-iodelay.c
+++ b/drivers/pinctrl/ti/pinctrl-ti-iodelay.c
@@ -575,11 +575,9 @@ static int ti_iodelay_pinconf_group_get(struct pinctrl_dev *pctldev,
575 unsigned long *config) 575 unsigned long *config)
576{ 576{
577 struct ti_iodelay_device *iod; 577 struct ti_iodelay_device *iod;
578 struct device *dev;
579 struct ti_iodelay_pingroup *group; 578 struct ti_iodelay_pingroup *group;
580 579
581 iod = pinctrl_dev_get_drvdata(pctldev); 580 iod = pinctrl_dev_get_drvdata(pctldev);
582 dev = iod->dev;
583 group = ti_iodelay_get_pingroup(iod, selector); 581 group = ti_iodelay_get_pingroup(iod, selector);
584 582
585 if (!group) 583 if (!group)
@@ -693,12 +691,10 @@ static void ti_iodelay_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
693 unsigned int selector) 691 unsigned int selector)
694{ 692{
695 struct ti_iodelay_device *iod; 693 struct ti_iodelay_device *iod;
696 struct device *dev;
697 struct ti_iodelay_pingroup *group; 694 struct ti_iodelay_pingroup *group;
698 int i; 695 int i;
699 696
700 iod = pinctrl_dev_get_drvdata(pctldev); 697 iod = pinctrl_dev_get_drvdata(pctldev);
701 dev = iod->dev;
702 group = ti_iodelay_get_pingroup(iod, selector); 698 group = ti_iodelay_get_pingroup(iod, selector);
703 if (!group) 699 if (!group)
704 return; 700 return;
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
index f9267fabe6b0..26fda5c53e65 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c
@@ -204,9 +204,10 @@ static int uniphier_conf_pin_drive_get(struct pinctrl_dev *pctldev,
204 const struct pin_desc *desc = pin_desc_get(pctldev, pin); 204 const struct pin_desc *desc = pin_desc_get(pctldev, pin);
205 enum uniphier_pin_drv_type type = 205 enum uniphier_pin_drv_type type =
206 uniphier_pin_get_drv_type(desc->drv_data); 206 uniphier_pin_get_drv_type(desc->drv_data);
207 const unsigned int strength_1bit[] = {4, 8}; 207 static const unsigned int strength_1bit[] = {4, 8};
208 const unsigned int strength_2bit[] = {8, 12, 16, 20}; 208 static const unsigned int strength_2bit[] = {8, 12, 16, 20};
209 const unsigned int strength_3bit[] = {4, 5, 7, 9, 11, 12, 14, 16}; 209 static const unsigned int strength_3bit[] = {4, 5, 7, 9, 11, 12,
210 14, 16};
210 const unsigned int *supported_strength; 211 const unsigned int *supported_strength;
211 unsigned int drvctrl, reg, shift, mask, width, val; 212 unsigned int drvctrl, reg, shift, mask, width, val;
212 int ret; 213 int ret;
@@ -399,9 +400,10 @@ static int uniphier_conf_pin_drive_set(struct pinctrl_dev *pctldev,
399 const struct pin_desc *desc = pin_desc_get(pctldev, pin); 400 const struct pin_desc *desc = pin_desc_get(pctldev, pin);
400 enum uniphier_pin_drv_type type = 401 enum uniphier_pin_drv_type type =
401 uniphier_pin_get_drv_type(desc->drv_data); 402 uniphier_pin_get_drv_type(desc->drv_data);
402 const unsigned int strength_1bit[] = {4, 8, -1}; 403 static const unsigned int strength_1bit[] = {4, 8, -1};
403 const unsigned int strength_2bit[] = {8, 12, 16, 20, -1}; 404 static const unsigned int strength_2bit[] = {8, 12, 16, 20, -1};
404 const unsigned int strength_3bit[] = {4, 5, 7, 9, 11, 12, 14, 16, -1}; 405 static const unsigned int strength_3bit[] = {4, 5, 7, 9, 11, 12, 14,
406 16, -1};
405 const unsigned int *supported_strength; 407 const unsigned int *supported_strength;
406 unsigned int drvctrl, reg, shift, mask, width, val; 408 unsigned int drvctrl, reg, shift, mask, width, val;
407 409
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
index 9c5e359a63de..8a5ecd6277d8 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c
@@ -472,8 +472,8 @@ static const struct pinctrl_pin_desc uniphier_ld11_pins[] = {
472 472
473static const unsigned aout_pins[] = {135, 136, 137, 138, 139, 140, 141, 142}; 473static const unsigned aout_pins[] = {135, 136, 137, 138, 139, 140, 141, 142};
474static const int aout_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0}; 474static const int aout_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
475static const unsigned emmc_pins[] = {18, 19, 20, 21, 22, 23, 24, 25}; 475static const unsigned int emmc_pins[] = {19, 20, 21, 22, 23, 24, 25};
476static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0}; 476static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
477static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29}; 477static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
478static const int emmc_dat8_muxvals[] = {0, 0, 0, 0}; 478static const int emmc_dat8_muxvals[] = {0, 0, 0, 0};
479static const unsigned ether_rmii_pins[] = {6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 479static const unsigned ether_rmii_pins[] = {6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
index 83341284dc44..3be7967edae0 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c
@@ -553,8 +553,8 @@ static const struct pinctrl_pin_desc uniphier_ld20_pins[] = {
553 553
554static const unsigned aout_pins[] = {135, 136, 137, 138, 139, 140, 141, 142}; 554static const unsigned aout_pins[] = {135, 136, 137, 138, 139, 140, 141, 142};
555static const int aout_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0}; 555static const int aout_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0};
556static const unsigned emmc_pins[] = {18, 19, 20, 21, 22, 23, 24, 25}; 556static const unsigned int emmc_pins[] = {19, 20, 21, 22, 23, 24, 25};
557static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0}; 557static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
558static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29}; 558static const unsigned emmc_dat8_pins[] = {26, 27, 28, 29};
559static const int emmc_dat8_muxvals[] = {0, 0, 0, 0}; 559static const int emmc_dat8_muxvals[] = {0, 0, 0, 0};
560static const unsigned ether_rgmii_pins[] = {30, 31, 32, 33, 34, 35, 36, 37, 38, 560static const unsigned ether_rgmii_pins[] = {30, 31, 32, 33, 34, 35, 36, 37, 38,
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
index d9f166f0cc86..dbe94a9a0353 100644
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
+++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c
@@ -776,8 +776,8 @@ static const struct pinctrl_pin_desc uniphier_pxs3_pins[] = {
776 250, UNIPHIER_PIN_PULL_DOWN), 776 250, UNIPHIER_PIN_PULL_DOWN),
777}; 777};
778 778
779static const unsigned int emmc_pins[] = {31, 32, 33, 34, 35, 36, 37, 38}; 779static const unsigned int emmc_pins[] = {32, 33, 34, 35, 36, 37, 38};
780static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0}; 780static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0};
781static const unsigned int emmc_dat8_pins[] = {39, 40, 41, 42}; 781static const unsigned int emmc_dat8_pins[] = {39, 40, 41, 42};
782static const int emmc_dat8_muxvals[] = {0, 0, 0, 0}; 782static const int emmc_dat8_muxvals[] = {0, 0, 0, 0};
783static const unsigned int ether_rgmii_pins[] = {52, 53, 54, 55, 56, 57, 58, 59, 783static const unsigned int ether_rgmii_pins[] = {52, 53, 54, 55, 56, 57, 58, 59,
diff --git a/include/dt-bindings/gpio/meson-gxbb-gpio.h b/include/dt-bindings/gpio/meson-gxbb-gpio.h
index 58654fd7aa1e..43a68a1110f0 100644
--- a/include/dt-bindings/gpio/meson-gxbb-gpio.h
+++ b/include/dt-bindings/gpio/meson-gxbb-gpio.h
@@ -29,6 +29,7 @@
29#define GPIOAO_11 11 29#define GPIOAO_11 11
30#define GPIOAO_12 12 30#define GPIOAO_12 12
31#define GPIOAO_13 13 31#define GPIOAO_13 13
32#define GPIO_TEST_N 14
32 33
33#define GPIOZ_0 0 34#define GPIOZ_0 0
34#define GPIOZ_1 1 35#define GPIOZ_1 1
@@ -149,6 +150,5 @@
149#define GPIOCLK_1 116 150#define GPIOCLK_1 116
150#define GPIOCLK_2 117 151#define GPIOCLK_2 117
151#define GPIOCLK_3 118 152#define GPIOCLK_3 118
152#define GPIO_TEST_N 119
153 153
154#endif 154#endif
diff --git a/include/dt-bindings/gpio/meson-gxl-gpio.h b/include/dt-bindings/gpio/meson-gxl-gpio.h
index 684d0d7add1c..01f2a2abd35e 100644
--- a/include/dt-bindings/gpio/meson-gxl-gpio.h
+++ b/include/dt-bindings/gpio/meson-gxl-gpio.h
@@ -25,6 +25,7 @@
25#define GPIOAO_7 7 25#define GPIOAO_7 7
26#define GPIOAO_8 8 26#define GPIOAO_8 8
27#define GPIOAO_9 9 27#define GPIOAO_9 9
28#define GPIO_TEST_N 10
28 29
29#define GPIOZ_0 0 30#define GPIOZ_0 0
30#define GPIOZ_1 1 31#define GPIOZ_1 1
@@ -126,6 +127,5 @@
126#define GPIOX_18 97 127#define GPIOX_18 97
127#define GPIOCLK_0 98 128#define GPIOCLK_0 98
128#define GPIOCLK_1 99 129#define GPIOCLK_1 99
129#define GPIO_TEST_N 100
130 130
131#endif 131#endif
diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consumer.h
index a0f2aba72fa9..0412cc9833e9 100644
--- a/include/linux/pinctrl/consumer.h
+++ b/include/linux/pinctrl/consumer.h
@@ -25,8 +25,8 @@ struct device;
25#ifdef CONFIG_PINCTRL 25#ifdef CONFIG_PINCTRL
26 26
27/* External interface to pin control */ 27/* External interface to pin control */
28extern int pinctrl_request_gpio(unsigned gpio); 28extern int pinctrl_gpio_request(unsigned gpio);
29extern void pinctrl_free_gpio(unsigned gpio); 29extern void pinctrl_gpio_free(unsigned gpio);
30extern int pinctrl_gpio_direction_input(unsigned gpio); 30extern int pinctrl_gpio_direction_input(unsigned gpio);
31extern int pinctrl_gpio_direction_output(unsigned gpio); 31extern int pinctrl_gpio_direction_output(unsigned gpio);
32extern int pinctrl_gpio_set_config(unsigned gpio, unsigned long config); 32extern int pinctrl_gpio_set_config(unsigned gpio, unsigned long config);
@@ -62,12 +62,12 @@ static inline int pinctrl_pm_select_idle_state(struct device *dev)
62 62
63#else /* !CONFIG_PINCTRL */ 63#else /* !CONFIG_PINCTRL */
64 64
65static inline int pinctrl_request_gpio(unsigned gpio) 65static inline int pinctrl_gpio_request(unsigned gpio)
66{ 66{
67 return 0; 67 return 0;
68} 68}
69 69
70static inline void pinctrl_free_gpio(unsigned gpio) 70static inline void pinctrl_gpio_free(unsigned gpio)
71{ 71{
72} 72}
73 73
diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h
index 5d8bc7f21c2a..ec6dadcc1fde 100644
--- a/include/linux/pinctrl/pinconf-generic.h
+++ b/include/linux/pinctrl/pinconf-generic.h
@@ -90,6 +90,10 @@
90 * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to 90 * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to
91 * this parameter (on a custom format) tells the driver which alternative 91 * this parameter (on a custom format) tells the driver which alternative
92 * slew rate to use. 92 * slew rate to use.
93 * @PIN_CONFIG_SKEW_DELAY: if the pin has programmable skew rate (on inputs)
94 * or latch delay (on outputs) this parameter (in a custom format)
95 * specifies the clock skew or latch delay. It typically controls how
96 * many double inverters are put in front of the line.
93 * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if 97 * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if
94 * you need to pass in custom configurations to the pin controller, use 98 * you need to pass in custom configurations to the pin controller, use
95 * PIN_CONFIG_END+1 as the base offset. 99 * PIN_CONFIG_END+1 as the base offset.
@@ -117,6 +121,7 @@ enum pin_config_param {
117 PIN_CONFIG_POWER_SOURCE, 121 PIN_CONFIG_POWER_SOURCE,
118 PIN_CONFIG_SLEEP_HARDWARE_STATE, 122 PIN_CONFIG_SLEEP_HARDWARE_STATE,
119 PIN_CONFIG_SLEW_RATE, 123 PIN_CONFIG_SLEW_RATE,
124 PIN_CONFIG_SKEW_DELAY,
120 PIN_CONFIG_END = 0x7F, 125 PIN_CONFIG_END = 0x7F,
121 PIN_CONFIG_MAX = 0xFF, 126 PIN_CONFIG_MAX = 0xFF,
122}; 127};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-25 05:25:24 -0500