13 files changed, 41 insertions, 35 deletions

diff --git a/Documentation/devicetree/bindings/clock/uniphier-clock.txt b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
index c7179d3b5c33..812163060fa3 100644
--- a/Documentation/devicetree/bindings/clock/uniphier-clock.txt
+++ b/Documentation/devicetree/bindings/clock/uniphier-clock.txt
@@ -24,7 +24,7 @@ Example:
                 reg = <0x61840000 0x4000>;
 
                 clock {
-                        compatible = "socionext,uniphier-ld20-clock";
+                        compatible = "socionext,uniphier-ld11-clock";
                         #clock-cells = <1>;
                 };
 
@@ -43,8 +43,8 @@ Provided clocks:
 21: USB3 ch1 PHY1
 
 
-Media I/O (MIO) clock
----------------------
+Media I/O (MIO) clock, SD clock
+-------------------------------
 
 Required properties:
 - compatible: should be one of the following:
@@ -52,10 +52,10 @@ Required properties:
     "socionext,uniphier-ld4-mio-clock"  - for LD4 SoC.
     "socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
     "socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
-    "socionext,uniphier-pro5-mio-clock" - for Pro5 SoC.
-    "socionext,uniphier-pxs2-mio-clock" - for PXs2/LD6b SoC.
+    "socionext,uniphier-pro5-sd-clock"  - for Pro5 SoC.
+    "socionext,uniphier-pxs2-sd-clock"  - for PXs2/LD6b SoC.
     "socionext,uniphier-ld11-mio-clock" - for LD11 SoC.
-    "socionext,uniphier-ld20-mio-clock" - for LD20 SoC.
+    "socionext,uniphier-ld20-sd-clock"  - for LD20 SoC.
 - #clock-cells: should be 1.
 
 Example:
@@ -66,7 +66,7 @@ Example:
                 reg = <0x59810000 0x800>;
 
                 clock {
-                        compatible = "socionext,uniphier-ld20-mio-clock";
+                        compatible = "socionext,uniphier-ld11-mio-clock";
                         #clock-cells = <1>;
                 };
 
@@ -112,7 +112,7 @@ Example:
                 reg = <0x59820000 0x200>;
 
                 clock {
-                        compatible = "socionext,uniphier-ld20-peri-clock";
+                        compatible = "socionext,uniphier-ld11-peri-clock";
                         #clock-cells = <1>;
                 };
 
diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c
index 190122e64a3a..85a449cf61e3 100644
--- a/drivers/clk/at91/clk-programmable.c
+++ b/drivers/clk/at91/clk-programmable.c
@@ -203,7 +203,7 @@ at91_clk_register_programmable(struct regmap *regmap,
         ret = clk_hw_register(NULL, &prog->hw);
         if (ret) {
                 kfree(prog);
-                hw = &prog->hw;
+                hw = ERR_PTR(ret);
         }
 
         return hw;
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index b68bf573dcfb..8c7763fd9efc 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -502,8 +502,12 @@ static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate,
 static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate,
                                    unsigned long *parent_rate)
 {
+        struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
+        const struct bcm2835_pll_data *data = pll->data;
         u32 ndiv, fdiv;
 
+        rate = clamp(rate, data->min_rate, data->max_rate);
+
         bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv);
 
         return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1);
@@ -608,13 +612,6 @@ static int bcm2835_pll_set_rate(struct clk_hw *hw,
         u32 ana[4];
         int i;
 
-        if (rate < data->min_rate || rate > data->max_rate) {
-                dev_err(cprman->dev, "%s: rate out of spec: %lu vs (%lu, %lu)\n",
-                        clk_hw_get_name(hw), rate,
-                        data->min_rate, data->max_rate);
-                return -EINVAL;
-        }
-
         if (rate > data->max_fb_rate) {
                 use_fb_prediv = true;
                 rate /= 2;
diff --git a/drivers/clk/clk-max77686.c b/drivers/clk/clk-max77686.c
index b637f5979023..eb953d3b0b69 100644
--- a/drivers/clk/clk-max77686.c
+++ b/drivers/clk/clk-max77686.c
@@ -216,6 +216,7 @@ static int max77686_clk_probe(struct platform_device *pdev)
                 return -EINVAL;
         }
 
+        drv_data->num_clks = num_clks;
         drv_data->max_clk_data = devm_kcalloc(dev, num_clks,
                                               sizeof(*drv_data->max_clk_data),
                                               GFP_KERNEL);
diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c
index fe364e63f8de..c0e8e1f196aa 100644
--- a/drivers/clk/hisilicon/clk-hi6220.c
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -195,7 +195,7 @@ static void __init hi6220_clk_sys_init(struct device_node *np)
         hi6220_clk_register_divider(hi6220_div_clks_sys,
                         ARRAY_SIZE(hi6220_div_clks_sys), clk_data);
 }
-CLK_OF_DECLARE(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init);
+CLK_OF_DECLARE_DRIVER(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init);
 
 
 /* clocks in media controller */
@@ -252,7 +252,7 @@ static void __init hi6220_clk_media_init(struct device_node *np)
         hi6220_clk_register_divider(hi6220_div_clks_media,
                                 ARRAY_SIZE(hi6220_div_clks_media), clk_data);
 }
-CLK_OF_DECLARE(hi6220_clk_media, "hisilicon,hi6220-mediactrl", hi6220_clk_media_init);
+CLK_OF_DECLARE_DRIVER(hi6220_clk_media, "hisilicon,hi6220-mediactrl", hi6220_clk_media_init);
 
 
 /* clocks in pmctrl */
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 380c372d528e..f042bd2a6a99 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -8,6 +8,7 @@ config COMMON_CLK_MEDIATEK
 
 config COMMON_CLK_MT8135
         bool "Clock driver for Mediatek MT8135"
+        depends on ARCH_MEDIATEK || COMPILE_TEST
         select COMMON_CLK_MEDIATEK
         default ARCH_MEDIATEK
         ---help---
@@ -15,6 +16,7 @@ config COMMON_CLK_MT8135
 
 config COMMON_CLK_MT8173
         bool "Clock driver for Mediatek MT8173"
+        depends on ARCH_MEDIATEK || COMPILE_TEST
         select COMMON_CLK_MEDIATEK
         default ARCH_MEDIATEK
         ---help---
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
index 45905fc0d75b..cecb0fdfaef6 100644
--- a/drivers/clk/mvebu/armada-37xx-periph.c
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
@@ -305,7 +305,7 @@ static const struct of_device_id armada_3700_periph_clock_of_match[] = {
 };
 static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
                                          void __iomem *reg, spinlock_t *lock,
-                                         struct device *dev, struct clk_hw *hw)
+                                         struct device *dev, struct clk_hw **hw)
 {
         const struct clk_ops *mux_ops = NULL, *gate_ops = NULL,
                 *rate_ops = NULL;
@@ -329,6 +329,7 @@ static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
                 gate->lock = lock;
                 gate_ops = gate_hw->init->ops;
                 gate->reg = reg + (u64)gate->reg;
+                gate->flags = CLK_GATE_SET_TO_DISABLE;
         }
 
         if (data->rate_hw) {
@@ -353,13 +354,13 @@ static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
                 }
         }
 
-        hw = clk_hw_register_composite(dev, data->name, data->parent_names,
+        *hw = clk_hw_register_composite(dev, data->name, data->parent_names,
                                        data->num_parents, mux_hw,
                                        mux_ops, rate_hw, rate_ops,
                                        gate_hw, gate_ops, CLK_IGNORE_UNUSED);
 
-        if (IS_ERR(hw))
-                return PTR_ERR(hw);
+        if (IS_ERR(*hw))
+                return PTR_ERR(*hw);
 
         return 0;
 }
@@ -400,7 +401,7 @@ static int armada_3700_periph_clock_probe(struct platform_device *pdev)
         spin_lock_init(&driver_data->lock);
 
         for (i = 0; i < num_periph; i++) {
-                struct clk_hw *hw = driver_data->hw_data->hws[i];
+                struct clk_hw **hw = &driver_data->hw_data->hws[i];
 
                 if (armada_3700_add_composite_clk(&data[i], reg,
                                                   &driver_data->lock, dev, hw))
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index 51d152f735cc..17e68a724945 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -106,6 +106,7 @@ static const struct of_device_id exynos_audss_clk_of_match[] = {
         },
         { },
 };
+MODULE_DEVICE_TABLE(of, exynos_audss_clk_of_match);
 
 static void exynos_audss_clk_teardown(void)
 {
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
index 5ffb898d0839..26c53f7963a4 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -79,7 +79,7 @@ static int uniphier_clk_probe(struct platform_device *pdev)
         hw_data->num = clk_num;
 
         /* avoid returning NULL for unused idx */
-        for (; clk_num >= 0; clk_num--)
+        while (--clk_num >= 0)
                 hw_data->hws[clk_num] = ERR_PTR(-EINVAL);
 
         for (p = data; p->name; p++) {
@@ -111,6 +111,10 @@ static int uniphier_clk_remove(struct platform_device *pdev)
 static const struct of_device_id uniphier_clk_match[] = {
         /* System clock */
         {
+                .compatible = "socionext,uniphier-sld3-clock",
+                .data = uniphier_sld3_sys_clk_data,
+        },
+        {
                 .compatible = "socionext,uniphier-ld4-clock",
                 .data = uniphier_ld4_sys_clk_data,
         },
@@ -138,7 +142,7 @@ static const struct of_device_id uniphier_clk_match[] = {
                 .compatible = "socionext,uniphier-ld20-clock",
                 .data = uniphier_ld20_sys_clk_data,
         },
-        /* Media I/O clock */
+        /* Media I/O clock, SD clock */
         {
                 .compatible = "socionext,uniphier-sld3-mio-clock",
                 .data = uniphier_sld3_mio_clk_data,
@@ -156,20 +160,20 @@ static const struct of_device_id uniphier_clk_match[] = {
                 .data = uniphier_sld3_mio_clk_data,
         },
         {
-                .compatible = "socionext,uniphier-pro5-mio-clock",
-                .data = uniphier_pro5_mio_clk_data,
+                .compatible = "socionext,uniphier-pro5-sd-clock",
+                .data = uniphier_pro5_sd_clk_data,
         },
         {
-                .compatible = "socionext,uniphier-pxs2-mio-clock",
-                .data = uniphier_pro5_mio_clk_data,
+                .compatible = "socionext,uniphier-pxs2-sd-clock",
+                .data = uniphier_pro5_sd_clk_data,
         },
         {
                 .compatible = "socionext,uniphier-ld11-mio-clock",
                 .data = uniphier_sld3_mio_clk_data,
         },
         {
-                .compatible = "socionext,uniphier-ld20-mio-clock",
-                .data = uniphier_pro5_mio_clk_data,
+                .compatible = "socionext,uniphier-ld20-sd-clock",
+                .data = uniphier_pro5_sd_clk_data,
         },
         /* Peripheral clock */
         {
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
index 6aa7ec768d0b..218d20f099ce 100644
--- a/drivers/clk/uniphier/clk-uniphier-mio.c
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -93,7 +93,7 @@ const struct uniphier_clk_data uniphier_sld3_mio_clk_data[] = {
         { /* sentinel */ }
 };
 
-const struct uniphier_clk_data uniphier_pro5_mio_clk_data[] = {
+const struct uniphier_clk_data uniphier_pro5_sd_clk_data[] = {
         UNIPHIER_MIO_CLK_SD_FIXED,
         UNIPHIER_MIO_CLK_SD(0, 0),
         UNIPHIER_MIO_CLK_SD(1, 1),
diff --git a/drivers/clk/uniphier/clk-uniphier-mux.c b/drivers/clk/uniphier/clk-uniphier-mux.c
index 15a2f2cbe0d9..2c243a894f3b 100644
--- a/drivers/clk/uniphier/clk-uniphier-mux.c
+++ b/drivers/clk/uniphier/clk-uniphier-mux.c
@@ -42,7 +42,7 @@ static u8 uniphier_clk_mux_get_parent(struct clk_hw *hw)
         struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);
         int num_parents = clk_hw_get_num_parents(hw);
         int ret;
-        u32 val;
+        unsigned int val;
         u8 i;
 
         ret = regmap_read(mux->regmap, mux->reg, &val);
diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h
index 3ae184062388..0244dba1f4cf 100644
--- a/drivers/clk/uniphier/clk-uniphier.h
+++ b/drivers/clk/uniphier/clk-uniphier.h
@@ -115,7 +115,7 @@ extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[];
 extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[];
 extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
 extern const struct uniphier_clk_data uniphier_sld3_mio_clk_data[];
-extern const struct uniphier_clk_data uniphier_pro5_mio_clk_data[];
+extern const struct uniphier_clk_data uniphier_pro5_sd_clk_data[];
 extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];
 extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[];
 
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index af596381fa0f..a428aec36ace 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -785,7 +785,7 @@ extern struct of_device_id __clk_of_table;
  * routines, one at of_clk_init(), and one at platform device probe
  */
 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
-        static void name##_of_clk_init_driver(struct device_node *np)   \
+        static void __init name##_of_clk_init_driver(struct device_node *np) \
         {                                                               \
                 of_node_clear_flag(np, OF_POPULATED);                   \
                 fn(np);                                                 \