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-rw-r--r--arch/x86/include/asm/set_memory.h1
-rw-r--r--arch/x86/mm/pageattr.c17
2 files changed, 0 insertions, 18 deletions
diff --git a/arch/x86/include/asm/set_memory.h b/arch/x86/include/asm/set_memory.h
index fd549c3ebb17..2ee8e469dcf5 100644
--- a/arch/x86/include/asm/set_memory.h
+++ b/arch/x86/include/asm/set_memory.h
@@ -40,7 +40,6 @@ int _set_memory_wt(unsigned long addr, int numpages);
40int _set_memory_wb(unsigned long addr, int numpages); 40int _set_memory_wb(unsigned long addr, int numpages);
41int set_memory_uc(unsigned long addr, int numpages); 41int set_memory_uc(unsigned long addr, int numpages);
42int set_memory_wc(unsigned long addr, int numpages); 42int set_memory_wc(unsigned long addr, int numpages);
43int set_memory_wt(unsigned long addr, int numpages);
44int set_memory_wb(unsigned long addr, int numpages); 43int set_memory_wb(unsigned long addr, int numpages);
45int set_memory_np(unsigned long addr, int numpages); 44int set_memory_np(unsigned long addr, int numpages);
46int set_memory_4k(unsigned long addr, int numpages); 45int set_memory_4k(unsigned long addr, int numpages);
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index d5586a012745..0d09cc5aad61 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -1858,23 +1858,6 @@ int _set_memory_wt(unsigned long addr, int numpages)
1858 cachemode2pgprot(_PAGE_CACHE_MODE_WT), 0); 1858 cachemode2pgprot(_PAGE_CACHE_MODE_WT), 0);
1859} 1859}
1860 1860
1861int set_memory_wt(unsigned long addr, int numpages)
1862{
1863 int ret;
1864
1865 ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
1866 _PAGE_CACHE_MODE_WT, NULL);
1867 if (ret)
1868 return ret;
1869
1870 ret = _set_memory_wt(addr, numpages);
1871 if (ret)
1872 free_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
1873
1874 return ret;
1875}
1876EXPORT_SYMBOL_GPL(set_memory_wt);
1877
1878int _set_memory_wb(unsigned long addr, int numpages) 1861int _set_memory_wb(unsigned long addr, int numpages)
1879{ 1862{
1880 /* WB cache mode is hard wired to all cache attribute bits being 0 */ 1863 /* WB cache mode is hard wired to all cache attribute bits being 0 */