158 files changed, 4350 insertions, 2596 deletions

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 6571fbfdb2a1..78cdf6a637fc 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -3675,7 +3675,11 @@
                         [KNL, SMP] Set scheduler's default relax_domain_level.
                         See Documentation/cgroup-v1/cpusets.txt.
 
-        reserve=        [KNL,BUGS] Force the kernel to ignore some iomem area
+        reserve=        [KNL,BUGS] Force kernel to ignore I/O ports or memory
+                        Format: <base1>,<size1>[,<base2>,<size2>,...]
+                        Reserve I/O ports or memory so the kernel won't use
+                        them.  If <base> is less than 0x10000, the region
+                        is assumed to be I/O ports; otherwise it is memory.
 
         reservetop=     [X86-32]
                         Format: nn[KMG]
diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
index 4e4aee4439ea..979dc7b6cfe8 100644
--- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt
@@ -4,7 +4,10 @@ This PCIe host controller is based on the Synopsys DesignWare PCIe IP
 and thus inherits all the common properties defined in designware-pcie.txt.
 
 Required properties:
-- compatible: "axis,artpec6-pcie", "snps,dw-pcie"
+- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
+              "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
+              "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
+              "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
 - reg: base addresses and lengths of the PCIe controller (DBI),
         the PHY controller, and configuration address space.
 - reg-names: Must include the following entries:
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
new file mode 100644
index 000000000000..9a305237fa6e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
@@ -0,0 +1,22 @@
+* Cadence PCIe endpoint controller
+
+Required properties:
+- compatible: Should contain "cdns,cdns-pcie-ep" to identify the IP used.
+- reg: Should contain the controller register base address and AXI interface
+  region base address respectively.
+- reg-names: Must be "reg" and "mem" respectively.
+- cdns,max-outbound-regions: Set to maximum number of outbound regions
+
+Optional properties:
+- max-functions: Maximum number of functions that can be configured (default 1).
+
+Example:
+
+pcie@fc000000 {
+        compatible = "cdns,cdns-pcie-ep";
+        reg = <0x0 0xfc000000 0x0 0x01000000>,
+              <0x0 0x80000000 0x0 0x40000000>;
+        reg-names = "reg", "mem";
+        cdns,max-outbound-regions = <16>;
+        max-functions = /bits/ 8 <8>;
+};
diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
new file mode 100644
index 000000000000..20a33f38f69d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
@@ -0,0 +1,60 @@
+* Cadence PCIe host controller
+
+This PCIe controller inherits the base properties defined in
+host-generic-pci.txt.
+
+Required properties:
+- compatible: Should contain "cdns,cdns-pcie-host" to identify the IP used.
+- reg: Should contain the controller register base address, PCIe configuration
+  window base address, and AXI interface region base address respectively.
+- reg-names: Must be "reg", "cfg" and "mem" respectively.
+- #address-cells: Set to <3>
+- #size-cells: Set to <2>
+- device_type: Set to "pci"
+- ranges: Ranges for the PCI memory and I/O regions
+- #interrupt-cells: Set to <1>
+- interrupt-map-mask and interrupt-map: Standard PCI properties to define the
+  mapping of the PCIe interface to interrupt numbers.
+
+Optional properties:
+- cdns,max-outbound-regions: Set to maximum number of outbound regions
+  (default 32)
+- cdns,no-bar-match-nbits: Set into the no BAR match register to configure the
+  number of least significant bits kept during inbound (PCIe -> AXI) address
+  translations (default 32)
+- vendor-id: The PCI vendor ID (16 bits, default is design dependent)
+- device-id: The PCI device ID (16 bits, default is design dependent)
+
+Example:
+
+pcie@fb000000 {
+        compatible = "cdns,cdns-pcie-host";
+        device_type = "pci";
+        #address-cells = <3>;
+        #size-cells = <2>;
+        bus-range = <0x0 0xff>;
+        linux,pci-domain = <0>;
+        cdns,max-outbound-regions = <16>;
+        cdns,no-bar-match-nbits = <32>;
+        vendor-id = /bits/ 16 <0x17cd>;
+        device-id = /bits/ 16 <0x0200>;
+
+        reg = <0x0 0xfb000000  0x0 0x01000000>,
+              <0x0 0x41000000  0x0 0x00001000>,
+              <0x0 0x40000000  0x0 0x04000000>;
+        reg-names = "reg", "cfg", "mem";
+
+        ranges = <0x02000000 0x0 0x42000000  0x0 0x42000000  0x0 0x1000000>,
+                 <0x01000000 0x0 0x43000000  0x0 0x43000000  0x0 0x0010000>;
+
+        #interrupt-cells = <0x1>;
+
+        interrupt-map = <0x0 0x0 0x0  0x1  &gic  0x0 0x0 0x0 14 0x1
+                         0x0 0x0 0x0  0x2  &gic  0x0 0x0 0x0 15 0x1
+                         0x0 0x0 0x0  0x3  &gic  0x0 0x0 0x0 16 0x1
+                         0x0 0x0 0x0  0x4  &gic  0x0 0x0 0x0 17 0x1>;
+
+        interrupt-map-mask = <0x0 0x0 0x0  0x7>;
+
+        msi-parent = <&its_pci>;
+};
diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
index 34a11bfbfb60..651d957d1051 100644
--- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
@@ -6,9 +6,6 @@ and thus inherits all the common properties defined in designware-pcie.txt.
 Required properties:
 - compatible: "samsung,exynos5440-pcie"
 - reg: base addresses and lengths of the PCIe controller,
-        the PHY controller, additional register for the PHY controller.
-        (Registers for the PHY controller are DEPRECATED.
-         Use the PHY framework.)
 - reg-names : First name should be set to "elbi".
         And use the "config" instead of getting the configuration address space
         from "ranges".
@@ -23,49 +20,8 @@ For other common properties, refer to
 
 Example:
 
-SoC-specific DT Entry:
+SoC-specific DT Entry (with using PHY framework):
 
-        pcie@290000 {
-                compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-                reg = <0x290000 0x1000
-                        0x270000 0x1000
-                        0x271000 0x40>;
-                interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
-                clocks = <&clock 28>, <&clock 27>;
-                clock-names = "pcie", "pcie_bus";
-                #address-cells = <3>;
-                #size-cells = <2>;
-                device_type = "pci";
-                ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */
-                          0x81000000 0 0          0x40001000 0 0x00010000   /* downstream I/O */
-                          0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
-                #interrupt-cells = <1>;
-                interrupt-map-mask = <0 0 0 0>;
-                interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
-                num-lanes = <4>;
-        };
-
-        pcie@2a0000 {
-                compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
-                reg = <0x2a0000 0x1000
-                        0x272000 0x1000
-                        0x271040 0x40>;
-                interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
-                clocks = <&clock 29>, <&clock 27>;
-                clock-names = "pcie", "pcie_bus";
-                #address-cells = <3>;
-                #size-cells = <2>;
-                device_type = "pci";
-                ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */
-                          0x81000000 0 0          0x60001000 0 0x00010000   /* downstream I/O */
-                          0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
-                #interrupt-cells = <1>;
-                interrupt-map-mask = <0 0 0 0>;
-                interrupt-map = <0 0 0 0 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-                num-lanes = <4>;
-        };
-
-With using PHY framework:
         pcie_phy0: pcie-phy@270000 {
                 ...
                 reg = <0x270000 0x1000>, <0x271000 0x40>;
@@ -74,13 +30,21 @@ With using PHY framework:
         };
 
         pcie@290000 {
-                ...
+                compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
                 reg = <0x290000 0x1000>, <0x40000000 0x1000>;
                 reg-names = "elbi", "config";
+                clocks = <&clock 28>, <&clock 27>;
+                clock-names = "pcie", "pcie_bus";
+                #address-cells = <3>;
+                #size-cells = <2>;
+                device_type = "pci";
                 phys = <&pcie_phy0>;
                 ranges = <0x81000000 0 0          0x60001000 0 0x00010000
                           0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;
-                ...
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+                num-lanes = <4>;
         };
 
 Board-specific DT Entry:
diff --git a/MAINTAINERS b/MAINTAINERS
index a6e86e20761e..cc24c74a946e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10402,6 +10402,13 @@ S:	Maintained
 F:      Documentation/devicetree/bindings/pci/pci-armada8k.txt
 F:      drivers/pci/dwc/pcie-armada8k.c
 
+PCI DRIVER FOR CADENCE PCIE IP
+M:      Alan Douglas <adouglas@cadence.com>
+L:      linux-pci@vger.kernel.org
+S:      Maintained
+F:      Documentation/devicetree/bindings/pci/cdns,*.txt
+F:      drivers/pci/cadence/pcie-cadence*
+
 PCI DRIVER FOR FREESCALE LAYERSCAPE
 M:      Minghuan Lian <minghuan.Lian@freescale.com>
 M:      Mingkai Hu <mingkai.hu@freescale.com>
@@ -10552,8 +10559,12 @@ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git
 S:      Supported
 F:      Documentation/devicetree/bindings/pci/
 F:      Documentation/PCI/
+F:      drivers/acpi/pci*
 F:      drivers/pci/
+F:      include/asm-generic/pci*
 F:      include/linux/pci*
+F:      include/uapi/linux/pci*
+F:      lib/pci*
 F:      arch/x86/pci/
 F:      arch/x86/kernel/quirks.c
 
diff --git a/arch/alpha/kernel/console.c b/arch/alpha/kernel/console.c
index 8e9a41966881..5476279329a6 100644
--- a/arch/alpha/kernel/console.c
+++ b/arch/alpha/kernel/console.c
@@ -21,6 +21,7 @@
 struct pci_controller *pci_vga_hose;
 static struct resource alpha_vga = {
         .name   = "alpha-vga+",
+        .flags  = IORESOURCE_IO,
         .start  = 0x3C0,
         .end    = 0x3DF
 };
diff --git a/arch/alpha/kernel/pci.c b/arch/alpha/kernel/pci.c
index 87da00579946..2e86ebb680ae 100644
--- a/arch/alpha/kernel/pci.c
+++ b/arch/alpha/kernel/pci.c
@@ -425,7 +425,7 @@ sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn)
                 if (bus == 0 && dfn == 0) {
                         hose = pci_isa_hose;
                 } else {
-                        dev = pci_get_bus_and_slot(bus, dfn);
+                        dev = pci_get_domain_bus_and_slot(0, bus, dfn);
                         if (!dev)
                                 return -ENODEV;
                         hose = dev->sysdata;
diff --git a/arch/alpha/kernel/sys_nautilus.c b/arch/alpha/kernel/sys_nautilus.c
index 239dc0e601d5..ff4f54b86c7f 100644
--- a/arch/alpha/kernel/sys_nautilus.c
+++ b/arch/alpha/kernel/sys_nautilus.c
@@ -237,7 +237,7 @@ nautilus_init_pci(void)
         bus = hose->bus = bridge->bus;
         pcibios_claim_one_bus(bus);
 
-        irongate = pci_get_bus_and_slot(0, 0);
+        irongate = pci_get_domain_bus_and_slot(pci_domain_nr(bus), 0, 0);
         bus->self = irongate;
         bus->resource[0] = &irongate_io;
         bus->resource[1] = &irongate_mem;
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
index 960d9dc4f380..1f0de808d111 100644
--- a/arch/arm/include/asm/pci.h
+++ b/arch/arm/include/asm/pci.h
@@ -10,10 +10,7 @@ extern unsigned long pcibios_min_io;
 extern unsigned long pcibios_min_mem;
 #define PCIBIOS_MIN_MEM pcibios_min_mem
 
-static inline int pcibios_assign_all_busses(void)
-{
-        return pci_has_flag(PCI_REASSIGN_ALL_RSRC);
-}
+#define pcibios_assign_all_busses()     pci_has_flag(PCI_REASSIGN_ALL_BUS)
 
 #ifdef CONFIG_PCI_DOMAINS
 static inline int pci_proc_domain(struct pci_bus *bus)
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 0cd0aefb3a8f..ed46ca69813d 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -527,7 +527,7 @@ void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
         struct pci_sys_data *sys;
         LIST_HEAD(head);
 
-        pci_add_flags(PCI_REASSIGN_ALL_RSRC);
+        pci_add_flags(PCI_REASSIGN_ALL_BUS);
         if (hw->preinit)
                 hw->preinit();
         pcibios_init_hw(parent, hw, &head);
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 9b49867154bf..6b32dc527edc 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -10,7 +10,6 @@ menuconfig ARCH_MVEBU
         select ZONE_DMA if ARM_LPAE
         select GPIOLIB
         select PCI_QUIRKS if PCI
-        select OF_ADDRESS_PCI
 
 if ARCH_MVEBU
 
diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c
index e4374a5651ce..448fd41792e4 100644
--- a/arch/mips/jazz/setup.c
+++ b/arch/mips/jazz/setup.c
@@ -32,22 +32,22 @@ static struct resource jazz_io_resources[] = {
                 .start  = 0x00,
                 .end    = 0x1f,
                 .name   = "dma1",
-                .flags  = IORESOURCE_BUSY
+                .flags  = IORESOURCE_IO | IORESOURCE_BUSY
         }, {
                 .start  = 0x40,
                 .end    = 0x5f,
                 .name   = "timer",
-                .flags  = IORESOURCE_BUSY
+                .flags  = IORESOURCE_IO | IORESOURCE_BUSY
         }, {
                 .start  = 0x80,
                 .end    = 0x8f,
                 .name   = "dma page reg",
-                .flags  = IORESOURCE_BUSY
+                .flags  = IORESOURCE_IO | IORESOURCE_BUSY
         }, {
                 .start  = 0xc0,
                 .end    = 0xdf,
                 .name   = "dma2",
-                .flags  = IORESOURCE_BUSY
+                .flags  = IORESOURCE_IO | IORESOURCE_BUSY
         }
 };
 
diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index de34adb76157..7b63914d2e58 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -47,31 +47,31 @@ static struct resource standard_io_resources[] = {
                 .name = "dma1",
                 .start = 0x00,
                 .end = 0x1f,
-                .flags = IORESOURCE_BUSY
+                .flags = IORESOURCE_IO | IORESOURCE_BUSY
         },
         {
                 .name = "timer",
                 .start = 0x40,
                 .end = 0x5f,
-                .flags = IORESOURCE_BUSY
+                .flags = IORESOURCE_IO | IORESOURCE_BUSY
         },
         {
                 .name = "keyboard",
                 .start = 0x60,
                 .end = 0x6f,
-                .flags = IORESOURCE_BUSY
+                .flags = IORESOURCE_IO | IORESOURCE_BUSY
         },
         {
                 .name = "dma page reg",
                 .start = 0x80,
                 .end = 0x8f,
-                .flags = IORESOURCE_BUSY
+                .flags = IORESOURCE_IO | IORESOURCE_BUSY
         },
         {
                 .name = "dma2",
                 .start = 0xc0,
                 .end = 0xdf,
-                .flags = IORESOURCE_BUSY
+                .flags = IORESOURCE_IO | IORESOURCE_BUSY
         },
 };
 
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 0ac7aa346c69..344af823c3c4 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -339,8 +339,7 @@ struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
  */
 static int pci_read_irq_line(struct pci_dev *pci_dev)
 {
-        struct of_phandle_args oirq;
-        unsigned int virq;
+        unsigned int virq = 0;
 
         pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
 
@@ -348,7 +347,7 @@ static int pci_read_irq_line(struct pci_dev *pci_dev)
         memset(&oirq, 0xff, sizeof(oirq));
 #endif
         /* Try to get a mapping from the device-tree */
-        if (of_irq_parse_pci(pci_dev, &oirq)) {
+        if (!of_irq_parse_and_map_pci(pci_dev, 0, 0)) {
                 u8 line, pin;
 
                 /* If that fails, lets fallback to what is in the config
@@ -372,11 +371,6 @@ static int pci_read_irq_line(struct pci_dev *pci_dev)
                 virq = irq_create_mapping(NULL, line);
                 if (virq)
                         irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
-        } else {
-                pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %pOF\n",
-                         oirq.args_count, oirq.args[0], oirq.args[1], oirq.np);
-
-                virq = irq_create_of_mapping(&oirq);
         }
 
         if (!virq) {
diff --git a/arch/powerpc/kernel/pci-hotplug.c b/arch/powerpc/kernel/pci-hotplug.c
index 2d71269e7dc1..cf47b1aec4c2 100644
--- a/arch/powerpc/kernel/pci-hotplug.c
+++ b/arch/powerpc/kernel/pci-hotplug.c
@@ -104,7 +104,7 @@ EXPORT_SYMBOL_GPL(pci_hp_remove_devices);
  */
 void pci_hp_add_devices(struct pci_bus *bus)
 {
-        int slotno, mode, pass, max;
+        int slotno, mode, max;
         struct pci_dev *dev;
         struct pci_controller *phb;
         struct device_node *dn = pci_bus_to_OF_node(bus);
@@ -133,13 +133,17 @@ void pci_hp_add_devices(struct pci_bus *bus)
                 pci_scan_slot(bus, PCI_DEVFN(slotno, 0));
                 pcibios_setup_bus_devices(bus);
                 max = bus->busn_res.start;
-                for (pass = 0; pass < 2; pass++) {
-                        list_for_each_entry(dev, &bus->devices, bus_list) {
-                                if (pci_is_bridge(dev))
-                                        max = pci_scan_bridge(bus, dev,
-                                                              max, pass);
-                        }
-                }
+                /*
+                 * Scan bridges that are already configured. We don't touch
+                 * them unless they are misconfigured (which will be done in
+                 * the second scan below).
+                 */
+                for_each_pci_bridge(dev, bus)
+                        max = pci_scan_bridge(bus, dev, max, 0);
+
+                /* Scan bridges that need to be reconfigured */
+                for_each_pci_bridge(dev, bus)
+                        max = pci_scan_bridge(bus, dev, max, 1);
         }
         pcibios_finish_adding_to_bus(bus);
 }
diff --git a/arch/powerpc/kernel/pci_32.c b/arch/powerpc/kernel/pci_32.c
index 1d817f4d97d9..85ad2f78b889 100644
--- a/arch/powerpc/kernel/pci_32.c
+++ b/arch/powerpc/kernel/pci_32.c
@@ -96,7 +96,8 @@ make_one_node_map(struct device_node* node, u8 pci_bus)
                 reg = of_get_property(node, "reg", NULL);
                 if (!reg)
                         continue;
-                dev = pci_get_bus_and_slot(pci_bus, ((reg[0] >> 8) & 0xff));
+                dev = pci_get_domain_bus_and_slot(0, pci_bus,
+                                                  ((reg[0] >> 8) & 0xff));
                 if (!dev || !dev->subordinate) {
                         pci_dev_put(dev);
                         continue;
diff --git a/arch/powerpc/kernel/pci_of_scan.c b/arch/powerpc/kernel/pci_of_scan.c
index 0d790f8432d2..8bdaa2a6fa62 100644
--- a/arch/powerpc/kernel/pci_of_scan.c
+++ b/arch/powerpc/kernel/pci_of_scan.c
@@ -369,11 +369,8 @@ static void __of_scan_bus(struct device_node *node, struct pci_bus *bus,
         pcibios_setup_bus_devices(bus);
 
         /* Now scan child busses */
-        list_for_each_entry(dev, &bus->devices, bus_list) {
-                if (pci_is_bridge(dev)) {
-                        of_scan_pci_bridge(dev);
-                }
-        }
+        for_each_pci_bridge(dev, bus)
+                of_scan_pci_bridge(dev);
 }
 
 /**
diff --git a/arch/powerpc/platforms/maple/time.c b/arch/powerpc/platforms/maple/time.c
index 81799d70a1ee..cfddc87f81bf 100644
--- a/arch/powerpc/platforms/maple/time.c
+++ b/arch/powerpc/platforms/maple/time.c
@@ -134,7 +134,7 @@ int maple_set_rtc_time(struct rtc_time *tm)
 
 static struct resource rtc_iores = {
         .name = "rtc",
-        .flags = IORESOURCE_BUSY,
+        .flags = IORESOURCE_IO | IORESOURCE_BUSY,
 };
 
 unsigned long __init maple_get_boot_time(void)
diff --git a/arch/powerpc/platforms/powermac/feature.c b/arch/powerpc/platforms/powermac/feature.c
index 9e3f39d36e88..ed8b16694153 100644
--- a/arch/powerpc/platforms/powermac/feature.c
+++ b/arch/powerpc/platforms/powermac/feature.c
@@ -829,7 +829,7 @@ core99_ata100_enable(struct device_node *node, long value)
 
         if (value) {
                 if (pci_device_from_OF_node(node, &pbus, &pid) == 0)
-                        pdev = pci_get_bus_and_slot(pbus, pid);
+                        pdev = pci_get_domain_bus_and_slot(0, pbus, pid);
                 if (pdev == NULL)
                         return 0;
                 rc = pci_enable_device(pdev);
diff --git a/arch/powerpc/platforms/powernv/eeh-powernv.c b/arch/powerpc/platforms/powernv/eeh-powernv.c
index 4650fb294e7a..2f7cd0ef3cdc 100644
--- a/arch/powerpc/platforms/powernv/eeh-powernv.c
+++ b/arch/powerpc/platforms/powernv/eeh-powernv.c
@@ -1654,14 +1654,14 @@ static int pnv_eeh_restore_vf_config(struct pci_dn *pdn)
                 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
                                       2, devctl);
 
-                /* Disable Completion Timeout */
+                /* Disable Completion Timeout if possible */
                 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP2,
                                      4, &cap2);
-                if (cap2 & 0x10) {
+                if (cap2 & PCI_EXP_DEVCAP2_COMP_TMOUT_DIS) {
                         eeh_ops->read_config(pdn,
                                              edev->pcie_cap + PCI_EXP_DEVCTL2,
                                              4, &cap2);
-                        cap2 |= 0x10;
+                        cap2 |= PCI_EXP_DEVCTL2_COMP_TMOUT_DIS;
                         eeh_ops->write_config(pdn,
                                               edev->pcie_cap + PCI_EXP_DEVCTL2,
                                               4, cap2);
diff --git a/arch/powerpc/sysdev/i8259.c b/arch/powerpc/sysdev/i8259.c
index bafb014e1a7e..cb9a8b71fd0f 100644
--- a/arch/powerpc/sysdev/i8259.c
+++ b/arch/powerpc/sysdev/i8259.c
@@ -145,21 +145,21 @@ static struct resource pic1_iores = {
         .name = "8259 (master)",
         .start = 0x20,
         .end = 0x21,
-        .flags = IORESOURCE_BUSY,
+        .flags = IORESOURCE_IO | IORESOURCE_BUSY,
 };
 
 static struct resource pic2_iores = {
         .name = "8259 (slave)",
         .start = 0xa0,
         .end = 0xa1,
-        .flags = IORESOURCE_BUSY,
+        .flags = IORESOURCE_IO | IORESOURCE_BUSY,
 };
 
 static struct resource pic_edgectrl_iores = {
         .name = "8259 edge control",
         .start = 0x4d0,
         .end = 0x4d1,
-        .flags = IORESOURCE_BUSY,
+        .flags = IORESOURCE_IO | IORESOURCE_BUSY,
 };
 
 static int i8259_host_match(struct irq_domain *h, struct device_node *node,
diff --git a/arch/powerpc/sysdev/mv64x60_pci.c b/arch/powerpc/sysdev/mv64x60_pci.c
index d52b3b81e05f..6fe9104632a0 100644
--- a/arch/powerpc/sysdev/mv64x60_pci.c
+++ b/arch/powerpc/sysdev/mv64x60_pci.c
@@ -37,7 +37,7 @@ static ssize_t mv64x60_hs_reg_read(struct file *filp, struct kobject *kobj,
         if (count < MV64X60_VAL_LEN_MAX)
                 return -EINVAL;
 
-        phb = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
+        phb = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
         if (!phb)
                 return -ENODEV;
         pci_read_config_dword(phb, MV64X60_PCICFG_CPCI_HOTSWAP, &v);
@@ -61,7 +61,7 @@ static ssize_t mv64x60_hs_reg_write(struct file *filp, struct kobject *kobj,
         if (sscanf(buf, "%i", &v) != 1)
                 return -EINVAL;
 
-        phb = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
+        phb = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
         if (!phb)
                 return -ENODEV;
         pci_write_config_dword(phb, MV64X60_PCICFG_CPCI_HOTSWAP, v);
diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c
index 0452629148be..52e55108404e 100644
--- a/arch/x86/pci/irq.c
+++ b/arch/x86/pci/irq.c
@@ -839,7 +839,8 @@ static void __init pirq_find_router(struct irq_router *r)
         DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for [%04x:%04x]\n",
             rt->rtr_vendor, rt->rtr_device);
 
-        pirq_router_dev = pci_get_bus_and_slot(rt->rtr_bus, rt->rtr_devfn);
+        pirq_router_dev = pci_get_domain_bus_and_slot(0, rt->rtr_bus,
+                                                      rt->rtr_devfn);
         if (!pirq_router_dev) {
                 DBG(KERN_DEBUG "PCI: Interrupt router not found at "
                         "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c
index c4b3646bd04c..9542a746dc50 100644
--- a/arch/x86/pci/xen.c
+++ b/arch/x86/pci/xen.c
@@ -409,10 +409,8 @@ int __init pci_xen_init(void)
         pcibios_enable_irq = xen_pcifront_enable_irq;
         pcibios_disable_irq = NULL;
 
-#ifdef CONFIG_ACPI
         /* Keep ACPI out of the picture */
-        acpi_noirq = 1;
-#endif
+        acpi_noirq_set();
 
 #ifdef CONFIG_PCI_MSI
         x86_msi.setup_msi_irqs = xen_setup_msi_irqs;
diff --git a/drivers/Makefile b/drivers/Makefile
index e06f7f633f73..8189b1edec00 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -16,10 +16,7 @@ obj-$(CONFIG_PINCTRL)		+= pinctrl/
 obj-$(CONFIG_GPIOLIB)           += gpio/
 obj-y                           += pwm/
 
-obj-$(CONFIG_PCI)               += pci/
-obj-$(CONFIG_PCI_ENDPOINT)      += pci/endpoint/
-# PCI dwc controller drivers
-obj-y                           += pci/dwc/
+obj-y                           += pci/
 
 obj-$(CONFIG_PARISC)            += parisc/
 obj-$(CONFIG_RAPIDIO)           += rapidio/
diff --git a/drivers/ata/pata_ali.c b/drivers/ata/pata_ali.c
index d19cd88ed2d3..0b122f903b8a 100644
--- a/drivers/ata/pata_ali.c
+++ b/drivers/ata/pata_ali.c
@@ -466,7 +466,8 @@ static void ali_init_chipset(struct pci_dev *pdev)
                         tmp |= 0x01;    /* CD_ROM enable for DMA */
                 pci_write_config_byte(pdev, 0x53, tmp);
         }
-        north = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
+        north = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 0,
+                                            PCI_DEVFN(0, 0));
         if (north && north->vendor == PCI_VENDOR_ID_AL && ali_isa_bridge) {
                 /* Configure the ALi bridge logic. For non ALi rely on BIOS.
                    Set the south bridge enable bit */
diff --git a/drivers/block/DAC960.c b/drivers/block/DAC960.c
index 442e777bdfb2..a7dbd184af86 100644
--- a/drivers/block/DAC960.c
+++ b/drivers/block/DAC960.c
@@ -268,17 +268,17 @@ static bool DAC960_CreateAuxiliaryStructures(DAC960_Controller_T *Controller)
   void *AllocationPointer = NULL;
   void *ScatterGatherCPU = NULL;
   dma_addr_t ScatterGatherDMA;
-  struct pci_pool *ScatterGatherPool;
+  struct dma_pool *ScatterGatherPool;
   void *RequestSenseCPU = NULL;
   dma_addr_t RequestSenseDMA;
-  struct pci_pool *RequestSensePool = NULL;
+  struct dma_pool *RequestSensePool = NULL;
 
   if (Controller->FirmwareType == DAC960_V1_Controller)
     {
       CommandAllocationLength = offsetof(DAC960_Command_T, V1.EndMarker);
       CommandAllocationGroupSize = DAC960_V1_CommandAllocationGroupSize;
-      ScatterGatherPool = pci_pool_create("DAC960_V1_ScatterGather",
-                Controller->PCIDevice,
+      ScatterGatherPool = dma_pool_create("DAC960_V1_ScatterGather",
+                &Controller->PCIDevice->dev,
         DAC960_V1_ScatterGatherLimit * sizeof(DAC960_V1_ScatterGatherSegment_T),
         sizeof(DAC960_V1_ScatterGatherSegment_T), 0);
       if (ScatterGatherPool == NULL)
@@ -290,18 +290,18 @@ static bool DAC960_CreateAuxiliaryStructures(DAC960_Controller_T *Controller)
     {
       CommandAllocationLength = offsetof(DAC960_Command_T, V2.EndMarker);
       CommandAllocationGroupSize = DAC960_V2_CommandAllocationGroupSize;
-      ScatterGatherPool = pci_pool_create("DAC960_V2_ScatterGather",
-                Controller->PCIDevice,
+      ScatterGatherPool = dma_pool_create("DAC960_V2_ScatterGather",
+                &Controller->PCIDevice->dev,
         DAC960_V2_ScatterGatherLimit * sizeof(DAC960_V2_ScatterGatherSegment_T),
         sizeof(DAC960_V2_ScatterGatherSegment_T), 0);
       if (ScatterGatherPool == NULL)
             return DAC960_Failure(Controller,
                         "AUXILIARY STRUCTURE CREATION (SG)");
-      RequestSensePool = pci_pool_create("DAC960_V2_RequestSense",
-                Controller->PCIDevice, sizeof(DAC960_SCSI_RequestSense_T),
+      RequestSensePool = dma_pool_create("DAC960_V2_RequestSense",
+                &Controller->PCIDevice->dev, sizeof(DAC960_SCSI_RequestSense_T),
                 sizeof(int), 0);
       if (RequestSensePool == NULL) {
-            pci_pool_destroy(ScatterGatherPool);
+            dma_pool_destroy(ScatterGatherPool);
             return DAC960_Failure(Controller,
                         "AUXILIARY STRUCTURE CREATION (SG)");
       }
@@ -335,16 +335,16 @@ static bool DAC960_CreateAuxiliaryStructures(DAC960_Controller_T *Controller)
       Command->Next = Controller->FreeCommands;
       Controller->FreeCommands = Command;
       Controller->Commands[CommandIdentifier-1] = Command;
-      ScatterGatherCPU = pci_pool_alloc(ScatterGatherPool, GFP_ATOMIC,
+      ScatterGatherCPU = dma_pool_alloc(ScatterGatherPool, GFP_ATOMIC,
                                                         &ScatterGatherDMA);
       if (ScatterGatherCPU == NULL)
           return DAC960_Failure(Controller, "AUXILIARY STRUCTURE CREATION");
 
       if (RequestSensePool != NULL) {
-          RequestSenseCPU = pci_pool_alloc(RequestSensePool, GFP_ATOMIC,
+          RequestSenseCPU = dma_pool_alloc(RequestSensePool, GFP_ATOMIC,
                                                 &RequestSenseDMA);
           if (RequestSenseCPU == NULL) {
-                pci_pool_free(ScatterGatherPool, ScatterGatherCPU,
+                dma_pool_free(ScatterGatherPool, ScatterGatherCPU,
                                 ScatterGatherDMA);
                 return DAC960_Failure(Controller,
                                         "AUXILIARY STRUCTURE CREATION");
@@ -379,8 +379,8 @@ static bool DAC960_CreateAuxiliaryStructures(DAC960_Controller_T *Controller)
 static void DAC960_DestroyAuxiliaryStructures(DAC960_Controller_T *Controller)
 {
   int i;
-  struct pci_pool *ScatterGatherPool = Controller->ScatterGatherPool;
-  struct pci_pool *RequestSensePool = NULL;
+  struct dma_pool *ScatterGatherPool = Controller->ScatterGatherPool;
+  struct dma_pool *RequestSensePool = NULL;
   void *ScatterGatherCPU;
   dma_addr_t ScatterGatherDMA;
   void *RequestSenseCPU;
@@ -411,9 +411,9 @@ static void DAC960_DestroyAuxiliaryStructures(DAC960_Controller_T *Controller)
           RequestSenseDMA = Command->V2.RequestSenseDMA;
       }
       if (ScatterGatherCPU != NULL)
-          pci_pool_free(ScatterGatherPool, ScatterGatherCPU, ScatterGatherDMA);
+          dma_pool_free(ScatterGatherPool, ScatterGatherCPU, ScatterGatherDMA);
       if (RequestSenseCPU != NULL)
-          pci_pool_free(RequestSensePool, RequestSenseCPU, RequestSenseDMA);
+          dma_pool_free(RequestSensePool, RequestSenseCPU, RequestSenseDMA);
 
       if ((Command->CommandIdentifier
            % Controller->CommandAllocationGroupSize) == 1) {
@@ -437,13 +437,11 @@ static void DAC960_DestroyAuxiliaryStructures(DAC960_Controller_T *Controller)
       Controller->CurrentStatusBuffer = NULL;
     }
 
-  if (ScatterGatherPool != NULL)
-        pci_pool_destroy(ScatterGatherPool);
+  dma_pool_destroy(ScatterGatherPool);
   if (Controller->FirmwareType == DAC960_V1_Controller)
         return;
 
-  if (RequestSensePool != NULL)
-        pci_pool_destroy(RequestSensePool);
+  dma_pool_destroy(RequestSensePool);
 
   for (i = 0; i < DAC960_MaxLogicalDrives; i++) {
         kfree(Controller->V2.LogicalDeviceInformation[i]);
diff --git a/drivers/block/DAC960.h b/drivers/block/DAC960.h
index 6a6226a2b932..21aff470d268 100644
--- a/drivers/block/DAC960.h
+++ b/drivers/block/DAC960.h
@@ -2316,7 +2316,7 @@ typedef struct DAC960_Controller
   bool SuppressEnclosureMessages;
   struct timer_list MonitoringTimer;
   struct gendisk *disks[DAC960_MaxLogicalDrives];
-  struct pci_pool *ScatterGatherPool;
+  struct dma_pool *ScatterGatherPool;
   DAC960_Command_T *FreeCommands;
   unsigned char *CombinedStatusBuffer;
   unsigned char *CurrentStatusBuffer;
@@ -2429,7 +2429,7 @@ typedef struct DAC960_Controller
       bool NeedDeviceSerialNumberInformation;
       bool StartLogicalDeviceInformationScan;
       bool StartPhysicalDeviceInformationScan;
-      struct pci_pool *RequestSensePool;
+      struct dma_pool *RequestSensePool;
 
       dma_addr_t        FirstCommandMailboxDMA;
       DAC960_V2_CommandMailbox_T *FirstCommandMailbox;
diff --git a/drivers/char/agp/nvidia-agp.c b/drivers/char/agp/nvidia-agp.c
index 828b34445203..623205bcd04a 100644
--- a/drivers/char/agp/nvidia-agp.c
+++ b/drivers/char/agp/nvidia-agp.c
@@ -340,11 +340,17 @@ static int agp_nvidia_probe(struct pci_dev *pdev,
         u8 cap_ptr;
 
         nvidia_private.dev_1 =
-                pci_get_bus_and_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 1));
+                pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
+                                            (unsigned int)pdev->bus->number,
+                                            PCI_DEVFN(0, 1));
         nvidia_private.dev_2 =
-                pci_get_bus_and_slot((unsigned int)pdev->bus->number, PCI_DEVFN(0, 2));
+                pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
+                                            (unsigned int)pdev->bus->number,
+                                            PCI_DEVFN(0, 2));
         nvidia_private.dev_3 =
-                pci_get_bus_and_slot((unsigned int)pdev->bus->number, PCI_DEVFN(30, 0));
+                pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
+                                            (unsigned int)pdev->bus->number,
+                                            PCI_DEVFN(30, 0));
 
         if (!nvidia_private.dev_1 || !nvidia_private.dev_2 || !nvidia_private.dev_3) {
                 printk(KERN_INFO PFX "Detected an NVIDIA nForce/nForce2 "
diff --git a/drivers/char/agp/sworks-agp.c b/drivers/char/agp/sworks-agp.c
index 03be4ac79b0d..4dbdd3bc9bb8 100644
--- a/drivers/char/agp/sworks-agp.c
+++ b/drivers/char/agp/sworks-agp.c
@@ -474,7 +474,8 @@ static int agp_serverworks_probe(struct pci_dev *pdev,
         }
 
         /* Everything is on func 1 here so we are hardcoding function one */
-        bridge_dev = pci_get_bus_and_slot((unsigned int)pdev->bus->number,
+        bridge_dev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
+                        (unsigned int)pdev->bus->number,
                         PCI_DEVFN(0, 1));
         if (!bridge_dev) {
                 dev_info(&pdev->dev, "can't find secondary device\n");
diff --git a/drivers/firmware/edd.c b/drivers/firmware/edd.c
index e22957665808..60a8f1363a10 100644
--- a/drivers/firmware/edd.c
+++ b/drivers/firmware/edd.c
@@ -669,10 +669,10 @@ edd_get_pci_dev(struct edd_device *edev)
         struct edd_info *info = edd_dev_get_info(edev);
 
         if (edd_dev_is_type(edev, "PCI") || edd_dev_is_type(edev, "XPRS")) {
-                return pci_get_bus_and_slot(info->params.interface_path.pci.bus,
-                                     PCI_DEVFN(info->params.interface_path.pci.slot,
-                                               info->params.interface_path.pci.
-                                               function));
+                return pci_get_domain_bus_and_slot(0,
+                                info->params.interface_path.pci.bus,
+                                PCI_DEVFN(info->params.interface_path.pci.slot,
+                                info->params.interface_path.pci.function));
         }
         return NULL;
 }
diff --git a/drivers/firmware/iscsi_ibft.c b/drivers/firmware/iscsi_ibft.c
index 14042a64bdd5..6bc8e6640d71 100644
--- a/drivers/firmware/iscsi_ibft.c
+++ b/drivers/firmware/iscsi_ibft.c
@@ -719,8 +719,9 @@ static int __init ibft_create_kobject(struct acpi_table_ibft *header,
                 * executes only devices which are in domain 0. Furthermore, the
                 * iBFT spec doesn't have a domain id field :-(
                 */
-                pci_dev = pci_get_bus_and_slot((nic->pci_bdf & 0xff00) >> 8,
-                                               (nic->pci_bdf & 0xff));
+                pci_dev = pci_get_domain_bus_and_slot(0,
+                                                (nic->pci_bdf & 0xff00) >> 8,
+                                                (nic->pci_bdf & 0xff));
                 if (pci_dev) {
                         rc = sysfs_create_link(&boot_kobj->kobj,
                                                &pci_dev->dev.kobj, "device");
diff --git a/drivers/gpu/drm/gma500/cdv_device.c b/drivers/gpu/drm/gma500/cdv_device.c
index 8745971a7680..3a3bf752e03a 100644
--- a/drivers/gpu/drm/gma500/cdv_device.c
+++ b/drivers/gpu/drm/gma500/cdv_device.c
@@ -185,21 +185,22 @@ static int cdv_backlight_init(struct drm_device *dev)
  *      for this and the MID devices.
  */
 
-static inline u32 CDV_MSG_READ32(uint port, uint offset)
+static inline u32 CDV_MSG_READ32(int domain, uint port, uint offset)
 {
         int mcr = (0x10<<24) | (port << 16) | (offset << 8);
         uint32_t ret_val = 0;
-        struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
+        struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
         pci_write_config_dword(pci_root, 0xD0, mcr);
         pci_read_config_dword(pci_root, 0xD4, &ret_val);
         pci_dev_put(pci_root);
         return ret_val;
 }
 
-static inline void CDV_MSG_WRITE32(uint port, uint offset, u32 value)
+static inline void CDV_MSG_WRITE32(int domain, uint port, uint offset,
+                                   u32 value)
 {
         int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
-        struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
+        struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
         pci_write_config_dword(pci_root, 0xD4, value);
         pci_write_config_dword(pci_root, 0xD0, mcr);
         pci_dev_put(pci_root);
@@ -216,11 +217,12 @@ static void cdv_init_pm(struct drm_device *dev)
 {
         struct drm_psb_private *dev_priv = dev->dev_private;
         u32 pwr_cnt;
+        int domain = pci_domain_nr(dev->pdev->bus);
         int i;
 
-        dev_priv->apm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
+        dev_priv->apm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT,
                                                         PSB_APMBA) & 0xFFFF;
-        dev_priv->ospm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
+        dev_priv->ospm_base = CDV_MSG_READ32(domain, PSB_PUNIT_PORT,
                                                         PSB_OSPMBA) & 0xFFFF;
 
         /* Power status */
@@ -251,7 +253,7 @@ static void cdv_errata(struct drm_device *dev)
          *      Bonus Launch to work around the issue, by degrading
          *      performance.
          */
-         CDV_MSG_WRITE32(3, 0x30, 0x08027108);
+         CDV_MSG_WRITE32(pci_domain_nr(dev->pdev->bus), 3, 0x30, 0x08027108);
 }
 
 /**
diff --git a/drivers/gpu/drm/gma500/gma_device.c b/drivers/gpu/drm/gma500/gma_device.c
index 4a295f9ba067..a7fb6de4dd15 100644
--- a/drivers/gpu/drm/gma500/gma_device.c
+++ b/drivers/gpu/drm/gma500/gma_device.c
@@ -19,7 +19,9 @@
 void gma_get_core_freq(struct drm_device *dev)
 {
         uint32_t clock;
-        struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
+        struct pci_dev *pci_root =
+                pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
+                                            0, 0);
         struct drm_psb_private *dev_priv = dev->dev_private;
 
         /*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/
diff --git a/drivers/gpu/drm/gma500/mid_bios.c b/drivers/gpu/drm/gma500/mid_bios.c
index 1fa163373a47..7171b7475f58 100644
--- a/drivers/gpu/drm/gma500/mid_bios.c
+++ b/drivers/gpu/drm/gma500/mid_bios.c
@@ -32,7 +32,9 @@
 static void mid_get_fuse_settings(struct drm_device *dev)
 {
         struct drm_psb_private *dev_priv = dev->dev_private;
-        struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
+        struct pci_dev *pci_root =
+                pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
+                                            0, 0);
         uint32_t fuse_value = 0;
         uint32_t fuse_value_tmp = 0;
 
@@ -104,7 +106,9 @@ static void mid_get_fuse_settings(struct drm_device *dev)
 static void mid_get_pci_revID(struct drm_psb_private *dev_priv)
 {
         uint32_t platform_rev_id = 0;
-        struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
+        int domain = pci_domain_nr(dev_priv->dev->pdev->bus);
+        struct pci_dev *pci_gfx_root =
+                pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(2, 0));
 
         if (pci_gfx_root == NULL) {
                 WARN_ON(1);
@@ -281,7 +285,9 @@ static void mid_get_vbt_data(struct drm_psb_private *dev_priv)
         u32 addr;
         u8 __iomem *vbt_virtual;
         struct mid_vbt_header vbt_header;
-        struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
+        struct pci_dev *pci_gfx_root =
+                pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
+                                            0, PCI_DEVFN(2, 0));
         int ret = -1;
 
         /* Get the address of the platform config vbt */
diff --git a/drivers/gpu/drm/gma500/psb_drv.c b/drivers/gpu/drm/gma500/psb_drv.c
index 37a3be71acd9..99d6527923de 100644
--- a/drivers/gpu/drm/gma500/psb_drv.c
+++ b/drivers/gpu/drm/gma500/psb_drv.c
@@ -261,7 +261,11 @@ static int psb_driver_load(struct drm_device *dev, unsigned long flags)
                 goto out_err;
 
         if (IS_MRST(dev)) {
-                dev_priv->aux_pdev = pci_get_bus_and_slot(0, PCI_DEVFN(3, 0));
+                int domain = pci_domain_nr(dev->pdev->bus);
+
+                dev_priv->aux_pdev =
+                        pci_get_domain_bus_and_slot(domain, 0,
+                                                    PCI_DEVFN(3, 0));
 
                 if (dev_priv->aux_pdev) {
                         resource_start = pci_resource_start(dev_priv->aux_pdev,
@@ -281,7 +285,9 @@ static int psb_driver_load(struct drm_device *dev, unsigned long flags)
                 }
                 dev_priv->gmbus_reg = dev_priv->aux_reg;
 
-                dev_priv->lpc_pdev = pci_get_bus_and_slot(0, PCI_DEVFN(31, 0));
+                dev_priv->lpc_pdev =
+                        pci_get_domain_bus_and_slot(domain, 0,
+                                                    PCI_DEVFN(31, 0));
                 if (dev_priv->lpc_pdev) {
                         pci_read_config_word(dev_priv->lpc_pdev, PSB_LPC_GBA,
                                 &dev_priv->lpc_gpio_base);
diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h
index 821497dbd3fc..d409e02bf540 100644
--- a/drivers/gpu/drm/gma500/psb_drv.h
+++ b/drivers/gpu/drm/gma500/psb_drv.h
@@ -781,38 +781,40 @@ extern const struct psb_ops cdv_chip_ops;
 extern int drm_idle_check_interval;
 
 /* Utilities */
-static inline u32 MRST_MSG_READ32(uint port, uint offset)
+static inline u32 MRST_MSG_READ32(int domain, uint port, uint offset)
 {
         int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
         uint32_t ret_val = 0;
-        struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
+        struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
         pci_write_config_dword(pci_root, 0xD0, mcr);
         pci_read_config_dword(pci_root, 0xD4, &ret_val);
         pci_dev_put(pci_root);
         return ret_val;
 }
-static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
+static inline void MRST_MSG_WRITE32(int domain, uint port, uint offset,
+                                    u32 value)
 {
         int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
-        struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
+        struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
         pci_write_config_dword(pci_root, 0xD4, value);
         pci_write_config_dword(pci_root, 0xD0, mcr);
         pci_dev_put(pci_root);
 }
-static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
+static inline u32 MDFLD_MSG_READ32(int domain, uint port, uint offset)
 {
         int mcr = (0x10<<24) | (port << 16) | (offset << 8);
         uint32_t ret_val = 0;
-        struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
+        struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
         pci_write_config_dword(pci_root, 0xD0, mcr);
         pci_read_config_dword(pci_root, 0xD4, &ret_val);
         pci_dev_put(pci_root);
         return ret_val;
 }
-static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
+static inline void MDFLD_MSG_WRITE32(int domain, uint port, uint offset,
+                                     u32 value)
 {
         int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
-        struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
+        struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
         pci_write_config_dword(pci_root, 0xD4, value);
         pci_write_config_dword(pci_root, 0xD0, mcr);
         pci_dev_put(pci_root);
diff --git a/drivers/gpu/drm/nouveau/dispnv04/arb.c b/drivers/gpu/drm/nouveau/dispnv04/arb.c
index 90075b676256..c79160c37f84 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/arb.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/arb.c
@@ -213,8 +213,10 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
         if ((dev->pdev->device & 0xffff) == 0x01a0 /*CHIPSET_NFORCE*/ ||
             (dev->pdev->device & 0xffff) == 0x01f0 /*CHIPSET_NFORCE2*/) {
                 uint32_t type;
+                int domain = pci_domain_nr(dev->pdev->bus);
 
-                pci_read_config_dword(pci_get_bus_and_slot(0, 1), 0x7c, &type);
+                pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 1),
+                                      0x7c, &type);
 
                 sim_data.memory_type = (type >> 12) & 1;
                 sim_data.memory_width = 64;
diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c
index b98599002831..0c9bdf023f5b 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/hw.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
@@ -216,12 +216,15 @@ nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype)
 {
         struct nvkm_pll_vals pllvals;
         int ret;
+        int domain;
+
+        domain = pci_domain_nr(dev->pdev->bus);
 
         if (plltype == PLL_MEMORY &&
             (dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) {
                 uint32_t mpllP;
-
-                pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
+                pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 3),
+                                      0x6c, &mpllP);
                 mpllP = (mpllP >> 8) & 0xf;
                 if (!mpllP)
                         mpllP = 4;
@@ -232,7 +235,8 @@ nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype)
             (dev->pdev->device & 0xff0) == CHIPSET_NFORCE2) {
                 uint32_t clock;
 
-                pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock);
+                pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 5),
+                                      0x4c, &clock);
                 return clock / 1000;
         }
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c
index 8d4a5be3b913..33b6139c1bf1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drm.c
@@ -524,7 +524,8 @@ nouveau_get_hdmi_dev(struct nouveau_drm *drm)
         }
 
         /* subfunction one is a hdmi audio device? */
-        drm->hdmi_device = pci_get_bus_and_slot((unsigned int)pdev->bus->number,
+        drm->hdmi_device = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus),
+                                                (unsigned int)pdev->bus->number,
                                                 PCI_DEVFN(PCI_SLOT(pdev->devfn), 1));
 
         if (!drm->hdmi_device) {
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c
index 4c07d10bb976..18241c6ba5fa 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c
@@ -28,8 +28,16 @@ nv1a_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram)
 {
         struct pci_dev *bridge;
         u32 mem, mib;
+        int domain = 0;
+        struct pci_dev *pdev = NULL;
 
-        bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
+        if (dev_is_pci(fb->subdev.device->dev))
+                pdev = to_pci_dev(fb->subdev.device->dev);
+
+        if (pdev)
+                domain = pci_domain_nr(pdev->bus);
+
+        bridge = pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 1));
         if (!bridge) {
                 nvkm_error(&fb->subdev, "no bridge device\n");
                 return -ENODEV;
diff --git a/drivers/ide/sl82c105.c b/drivers/ide/sl82c105.c
index 8755df3330a0..3300dac56390 100644
--- a/drivers/ide/sl82c105.c
+++ b/drivers/ide/sl82c105.c
@@ -239,8 +239,9 @@ static u8 sl82c105_bridge_revision(struct pci_dev *dev)
         /*
          * The bridge should be part of the same device, but function 0.
          */
-        bridge = pci_get_bus_and_slot(dev->bus->number,
-                               PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
+        bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus),
+                                        dev->bus->number,
+                                        PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
         if (!bridge)
                 return -1;
 
diff --git a/drivers/infiniband/hw/qedr/main.c b/drivers/infiniband/hw/qedr/main.c
index 50812b33291b..b3786474e84a 100644
--- a/drivers/infiniband/hw/qedr/main.c
+++ b/drivers/infiniband/hw/qedr/main.c
@@ -430,59 +430,16 @@ static void qedr_remove_sysfiles(struct qedr_dev *dev)
 
 static void qedr_pci_set_atomic(struct qedr_dev *dev, struct pci_dev *pdev)
 {
-        struct pci_dev *bridge;
-        u32 ctl2, cap2;
-        u16 flags;
-        int rc;
-
-        bridge = pdev->bus->self;
-        if (!bridge)
-                goto disable;
-
-        /* Check atomic routing support all the way to root complex */
-        while (bridge->bus->parent) {
-                rc = pcie_capability_read_word(bridge, PCI_EXP_FLAGS, &flags);
-                if (rc || ((flags & PCI_EXP_FLAGS_VERS) < 2))
-                        goto disable;
-
-                rc = pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap2);
-                if (rc)
-                        goto disable;
+        int rc = pci_enable_atomic_ops_to_root(pdev,
+                                               PCI_EXP_DEVCAP2_ATOMIC_COMP64);
 
-                rc = pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl2);
-                if (rc)
-                        goto disable;
-
-                if (!(cap2 & PCI_EXP_DEVCAP2_ATOMIC_ROUTE) ||
-                    (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK))
-                        goto disable;
-                bridge = bridge->bus->parent->self;
+        if (rc) {
+                dev->atomic_cap = IB_ATOMIC_NONE;
+                DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability disabled\n");
+        } else {
+                dev->atomic_cap = IB_ATOMIC_GLOB;
+                DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability enabled\n");
         }
-
-        rc = pcie_capability_read_word(bridge, PCI_EXP_FLAGS, &flags);
-        if (rc || ((flags & PCI_EXP_FLAGS_VERS) < 2))
-                goto disable;
-
-        rc = pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap2);
-        if (rc || !(cap2 & PCI_EXP_DEVCAP2_ATOMIC_COMP64))
-                goto disable;
-
-        /* Set atomic operations */
-        pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,
-                                 PCI_EXP_DEVCTL2_ATOMIC_REQ);
-        dev->atomic_cap = IB_ATOMIC_GLOB;
-
-        DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability enabled\n");
-
-        return;
-
-disable:
-        pcie_capability_clear_word(pdev, PCI_EXP_DEVCTL2,
-                                   PCI_EXP_DEVCTL2_ATOMIC_REQ);
-        dev->atomic_cap = IB_ATOMIC_NONE;
-
-        DP_DEBUG(dev, QEDR_MSG_INIT, "Atomic capability disabled\n");
-
 }
 
 static const struct qed_rdma_ops *qed_ops;
diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
index 7d5eb004091d..821547b23c65 100644
--- a/drivers/iommu/amd_iommu.c
+++ b/drivers/iommu/amd_iommu.c
@@ -527,7 +527,8 @@ static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
         struct iommu_dev_data *dev_data = NULL;
         struct pci_dev *pdev;
 
-        pdev = pci_get_bus_and_slot(PCI_BUS_NUM(devid), devid & 0xff);
+        pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
+                                           devid & 0xff);
         if (pdev)
                 dev_data = get_dev_data(&pdev->dev);
 
diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c
index 6fe2d0346073..4e4a615bf13f 100644
--- a/drivers/iommu/amd_iommu_init.c
+++ b/drivers/iommu/amd_iommu_init.c
@@ -1697,8 +1697,8 @@ static int iommu_init_pci(struct amd_iommu *iommu)
         u32 range, misc, low, high;
         int ret;
 
-        iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
-                                          iommu->devid & 0xff);
+        iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid),
+                                                 iommu->devid & 0xff);
         if (!iommu->dev)
                 return -ENODEV;
 
@@ -1764,8 +1764,9 @@ static int iommu_init_pci(struct amd_iommu *iommu)
         if (is_rd890_iommu(iommu->dev)) {
                 int i, j;
 
-                iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
-                                PCI_DEVFN(0, 0));
+                iommu->root_pdev =
+                        pci_get_domain_bus_and_slot(0, iommu->dev->bus->number,
+                                                    PCI_DEVFN(0, 0));
 
                 /*
                  * Some rd890 systems may not be fully reconfigured by the
diff --git a/drivers/iommu/amd_iommu_v2.c b/drivers/iommu/amd_iommu_v2.c
index 7d94e1d39e5e..8696382be837 100644
--- a/drivers/iommu/amd_iommu_v2.c
+++ b/drivers/iommu/amd_iommu_v2.c
@@ -564,7 +564,8 @@ static int ppr_notifier(struct notifier_block *nb, unsigned long e, void *data)
         finish      = (iommu_fault->tag >> 9) & 1;
 
         devid = iommu_fault->device_id;
-        pdev = pci_get_bus_and_slot(PCI_BUS_NUM(devid), devid & 0xff);
+        pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
+                                           devid & 0xff);
         if (!pdev)
                 return -ENODEV;
         dev_data = get_dev_data(&pdev->dev);
diff --git a/drivers/irqchip/irq-i8259.c b/drivers/irqchip/irq-i8259.c
index 7aafbb091b67..b0d4aab1a58c 100644
--- a/drivers/irqchip/irq-i8259.c
+++ b/drivers/irqchip/irq-i8259.c
@@ -289,14 +289,14 @@ static struct resource pic1_io_resource = {
         .name = "pic1",
         .start = PIC_MASTER_CMD,
         .end = PIC_MASTER_IMR,
-        .flags = IORESOURCE_BUSY
+        .flags = IORESOURCE_IO | IORESOURCE_BUSY
 };
 
 static struct resource pic2_io_resource = {
         .name = "pic2",
         .start = PIC_SLAVE_CMD,
         .end = PIC_SLAVE_IMR,
-        .flags = IORESOURCE_BUSY
+        .flags = IORESOURCE_IO | IORESOURCE_BUSY
 };
 
 static int i8259A_irq_domain_map(struct irq_domain *d, unsigned int virq,
diff --git a/drivers/macintosh/via-pmu.c b/drivers/macintosh/via-pmu.c
index c4c2b3b85ebc..3e8b3b68dcb4 100644
--- a/drivers/macintosh/via-pmu.c
+++ b/drivers/macintosh/via-pmu.c
@@ -1799,7 +1799,7 @@ static int powerbook_sleep_grackle(void)
         struct adb_request req;
         struct pci_dev *grackle;
 
-        grackle = pci_get_bus_and_slot(0, 0);
+        grackle = pci_get_domain_bus_and_slot(0, 0, 0);
         if (!grackle)
                 return -ENODEV;
 
diff --git a/drivers/media/usb/ttusb-budget/dvb-ttusb-budget.c b/drivers/media/usb/ttusb-budget/dvb-ttusb-budget.c
index a142b9dc0feb..ea40a24947ba 100644
--- a/drivers/media/usb/ttusb-budget/dvb-ttusb-budget.c
+++ b/drivers/media/usb/ttusb-budget/dvb-ttusb-budget.c
@@ -102,7 +102,6 @@ struct ttusb {
         unsigned int isoc_in_pipe;
 
         void *iso_buffer;
-        dma_addr_t iso_dma_handle;
 
         struct urb *iso_urb[ISO_BUF_COUNT];
 
@@ -792,26 +791,17 @@ static void ttusb_free_iso_urbs(struct ttusb *ttusb)
 
         for (i = 0; i < ISO_BUF_COUNT; i++)
                 usb_free_urb(ttusb->iso_urb[i]);
-
-        pci_free_consistent(NULL,
-                            ISO_FRAME_SIZE * FRAMES_PER_ISO_BUF *
-                            ISO_BUF_COUNT, ttusb->iso_buffer,
-                            ttusb->iso_dma_handle);
+        kfree(ttusb->iso_buffer);
 }
 
 static int ttusb_alloc_iso_urbs(struct ttusb *ttusb)
 {
         int i;
 
-        ttusb->iso_buffer = pci_zalloc_consistent(NULL,
-                                                  ISO_FRAME_SIZE * FRAMES_PER_ISO_BUF * ISO_BUF_COUNT,
-                                                  &ttusb->iso_dma_handle);
-
-        if (!ttusb->iso_buffer) {
-                dprintk("%s: pci_alloc_consistent - not enough memory\n",
-                        __func__);
+        ttusb->iso_buffer = kcalloc(FRAMES_PER_ISO_BUF * ISO_BUF_COUNT,
+                        ISO_FRAME_SIZE, GFP_KERNEL);
+        if (!ttusb->iso_buffer)
                 return -ENOMEM;
-        }
 
         for (i = 0; i < ISO_BUF_COUNT; i++) {
                 struct urb *urb;
diff --git a/drivers/media/usb/ttusb-dec/ttusb_dec.c b/drivers/media/usb/ttusb-dec/ttusb_dec.c
index cdefb5dfbbdc..4d5acdf578a6 100644
--- a/drivers/media/usb/ttusb-dec/ttusb_dec.c
+++ b/drivers/media/usb/ttusb-dec/ttusb_dec.c
@@ -127,7 +127,6 @@ struct ttusb_dec {
         struct urb              *irq_urb;
         dma_addr_t              irq_dma_handle;
         void                    *iso_buffer;
-        dma_addr_t              iso_dma_handle;
         struct urb              *iso_urb[ISO_BUF_COUNT];
         int                     iso_stream_count;
         struct mutex            iso_mutex;
@@ -1185,11 +1184,7 @@ static void ttusb_dec_free_iso_urbs(struct ttusb_dec *dec)
 
         for (i = 0; i < ISO_BUF_COUNT; i++)
                 usb_free_urb(dec->iso_urb[i]);
-
-        pci_free_consistent(NULL,
-                            ISO_FRAME_SIZE * (FRAMES_PER_ISO_BUF *
-                                              ISO_BUF_COUNT),
-                            dec->iso_buffer, dec->iso_dma_handle);
+        kfree(dec->iso_buffer);
 }
 
 static int ttusb_dec_alloc_iso_urbs(struct ttusb_dec *dec)
@@ -1198,15 +1193,10 @@ static int ttusb_dec_alloc_iso_urbs(struct ttusb_dec *dec)
 
         dprintk("%s\n", __func__);
 
-        dec->iso_buffer = pci_zalloc_consistent(NULL,
-                                                ISO_FRAME_SIZE * (FRAMES_PER_ISO_BUF * ISO_BUF_COUNT),
-                                                &dec->iso_dma_handle);
-
-        if (!dec->iso_buffer) {
-                dprintk("%s: pci_alloc_consistent - not enough memory\n",
-                        __func__);
+        dec->iso_buffer = kcalloc(FRAMES_PER_ISO_BUF * ISO_BUF_COUNT,
+                        ISO_FRAME_SIZE, GFP_KERNEL);
+        if (!dec->iso_buffer)
                 return -ENOMEM;
-        }
 
         for (i = 0; i < ISO_BUF_COUNT; i++) {
                 struct urb *urb;
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c
index 3591077a5f6b..ffa7959f6b31 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c
@@ -812,7 +812,7 @@ static u8 bnx2x_vf_is_pcie_pending(struct bnx2x *bp, u8 abs_vfid)
         if (!vf)
                 return false;
 
-        dev = pci_get_bus_and_slot(vf->bus, vf->devfn);
+        dev = pci_get_domain_bus_and_slot(vf->domain, vf->bus, vf->devfn);
         if (dev)
                 return bnx2x_is_pcie_pending(dev);
         return false;
@@ -1041,6 +1041,13 @@ void bnx2x_iov_init_dmae(struct bnx2x *bp)
                 REG_WR(bp, DMAE_REG_BACKWARD_COMP_EN, 0);
 }
 
+static int bnx2x_vf_domain(struct bnx2x *bp, int vfid)
+{
+        struct pci_dev *dev = bp->pdev;
+
+        return pci_domain_nr(dev->bus);
+}
+
 static int bnx2x_vf_bus(struct bnx2x *bp, int vfid)
 {
         struct pci_dev *dev = bp->pdev;
@@ -1606,6 +1613,7 @@ int bnx2x_iov_nic_init(struct bnx2x *bp)
                 struct bnx2x_virtf *vf = BP_VF(bp, vfid);
 
                 /* fill in the BDF and bars */
+                vf->domain = bnx2x_vf_domain(bp, vfid);
                 vf->bus = bnx2x_vf_bus(bp, vfid);
                 vf->devfn = bnx2x_vf_devfn(bp, vfid);
                 bnx2x_vf_set_bars(bp, vf);
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.h
index 53466f6cebab..eb814c65152f 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.h
@@ -182,6 +182,7 @@ struct bnx2x_virtf {
         u32 error;      /* 0 means all's-well */
 
         /* BDF */
+        unsigned int domain;
         unsigned int bus;
         unsigned int devfn;
 
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c b/drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c
index 7d95f0866fb0..28a81ac97af5 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c
+++ b/drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c
@@ -143,7 +143,7 @@ int hinic_alloc_cmdq_buf(struct hinic_cmdqs *cmdqs,
         struct hinic_hwif *hwif = cmdqs->hwif;
         struct pci_dev *pdev = hwif->pdev;
 
-        cmdq_buf->buf = pci_pool_alloc(cmdqs->cmdq_buf_pool, GFP_KERNEL,
+        cmdq_buf->buf = dma_pool_alloc(cmdqs->cmdq_buf_pool, GFP_KERNEL,
                                        &cmdq_buf->dma_addr);
         if (!cmdq_buf->buf) {
                 dev_err(&pdev->dev, "Failed to allocate cmd from the pool\n");
@@ -161,7 +161,7 @@ int hinic_alloc_cmdq_buf(struct hinic_cmdqs *cmdqs,
 void hinic_free_cmdq_buf(struct hinic_cmdqs *cmdqs,
                          struct hinic_cmdq_buf *cmdq_buf)
 {
-        pci_pool_free(cmdqs->cmdq_buf_pool, cmdq_buf->buf, cmdq_buf->dma_addr);
+        dma_pool_free(cmdqs->cmdq_buf_pool, cmdq_buf->buf, cmdq_buf->dma_addr);
 }
 
 static unsigned int cmdq_wqe_size_from_bdlen(enum bufdesc_len len)
@@ -875,7 +875,7 @@ int hinic_init_cmdqs(struct hinic_cmdqs *cmdqs, struct hinic_hwif *hwif,
         int err;
 
         cmdqs->hwif = hwif;
-        cmdqs->cmdq_buf_pool = pci_pool_create("hinic_cmdq", pdev,
+        cmdqs->cmdq_buf_pool = dma_pool_create("hinic_cmdq", &pdev->dev,
                                                HINIC_CMDQ_BUF_SIZE,
                                                HINIC_CMDQ_BUF_SIZE, 0);
         if (!cmdqs->cmdq_buf_pool)
@@ -916,7 +916,7 @@ err_cmdq_wqs:
         devm_kfree(&pdev->dev, cmdqs->saved_wqs);
 
 err_saved_wqs:
-        pci_pool_destroy(cmdqs->cmdq_buf_pool);
+        dma_pool_destroy(cmdqs->cmdq_buf_pool);
         return err;
 }
 
@@ -942,5 +942,5 @@ void hinic_free_cmdqs(struct hinic_cmdqs *cmdqs)
 
         devm_kfree(&pdev->dev, cmdqs->saved_wqs);
 
-        pci_pool_destroy(cmdqs->cmdq_buf_pool);
+        dma_pool_destroy(cmdqs->cmdq_buf_pool);
 }
diff --git a/drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h b/drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h
index b35583400cb6..23f8d39eab68 100644
--- a/drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h
+++ b/drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h
@@ -157,7 +157,7 @@ struct hinic_cmdq {
 struct hinic_cmdqs {
         struct hinic_hwif       *hwif;
 
-        struct pci_pool         *cmdq_buf_pool;
+        struct dma_pool         *cmdq_buf_pool;
 
         struct hinic_wq         *saved_wqs;
 
diff --git a/drivers/net/ethernet/intel/e100.c b/drivers/net/ethernet/intel/e100.c
index 44b3937f7e81..29486478836e 100644
--- a/drivers/net/ethernet/intel/e100.c
+++ b/drivers/net/ethernet/intel/e100.c
@@ -607,7 +607,7 @@ struct nic {
         struct mem *mem;
         dma_addr_t dma_addr;
 
-        struct pci_pool *cbs_pool;
+        struct dma_pool *cbs_pool;
         dma_addr_t cbs_dma_addr;
         u8 adaptive_ifs;
         u8 tx_threshold;
@@ -1892,7 +1892,7 @@ static void e100_clean_cbs(struct nic *nic)
                         nic->cb_to_clean = nic->cb_to_clean->next;
                         nic->cbs_avail++;
                 }
-                pci_pool_free(nic->cbs_pool, nic->cbs, nic->cbs_dma_addr);
+                dma_pool_free(nic->cbs_pool, nic->cbs, nic->cbs_dma_addr);
                 nic->cbs = NULL;
                 nic->cbs_avail = 0;
         }
@@ -1910,7 +1910,7 @@ static int e100_alloc_cbs(struct nic *nic)
         nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
         nic->cbs_avail = 0;
 
-        nic->cbs = pci_pool_zalloc(nic->cbs_pool, GFP_KERNEL,
+        nic->cbs = dma_pool_zalloc(nic->cbs_pool, GFP_KERNEL,
                                    &nic->cbs_dma_addr);
         if (!nic->cbs)
                 return -ENOMEM;
@@ -2960,8 +2960,8 @@ static int e100_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                 netif_err(nic, probe, nic->netdev, "Cannot register net device, aborting\n");
                 goto err_out_free;
         }
-        nic->cbs_pool = pci_pool_create(netdev->name,
-                           nic->pdev,
+        nic->cbs_pool = dma_pool_create(netdev->name,
+                           &nic->pdev->dev,
                            nic->params.cbs.max * sizeof(struct cb),
                            sizeof(u32),
                            0);
@@ -3001,7 +3001,7 @@ static void e100_remove(struct pci_dev *pdev)
                 unregister_netdev(netdev);
                 e100_free(nic);
                 pci_iounmap(pdev, nic->csr);
-                pci_pool_destroy(nic->cbs_pool);
+                dma_pool_destroy(nic->cbs_pool);
                 free_netdev(netdev);
                 pci_release_regions(pdev);
                 pci_disable_device(pdev);
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
index 40e52ffb732f..7cd494611a74 100644
--- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
+++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
@@ -2594,8 +2594,10 @@ static int pch_gbe_probe(struct pci_dev *pdev,
         if (adapter->pdata && adapter->pdata->platform_init)
                 adapter->pdata->platform_init(pdev);
 
-        adapter->ptp_pdev = pci_get_bus_and_slot(adapter->pdev->bus->number,
-                                               PCI_DEVFN(12, 4));
+        adapter->ptp_pdev =
+                pci_get_domain_bus_and_slot(pci_domain_nr(adapter->pdev->bus),
+                                            adapter->pdev->bus->number,
+                                            PCI_DEVFN(12, 4));
 
         netdev->netdev_ops = &pch_gbe_netdev_ops;
         netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
diff --git a/drivers/net/ethernet/tundra/tsi108_eth.c b/drivers/net/ethernet/tundra/tsi108_eth.c
index 0624b71ab5d4..edcd1e60b30d 100644
--- a/drivers/net/ethernet/tundra/tsi108_eth.c
+++ b/drivers/net/ethernet/tundra/tsi108_eth.c
@@ -152,6 +152,8 @@ struct tsi108_prv_data {
         u32 msg_enable;                 /* debug message level */
         struct mii_if_info mii_if;
         unsigned int init_media;
+
+        struct platform_device *pdev;
 };
 
 /* Structure for a device driver */
@@ -703,17 +705,18 @@ static int tsi108_send_packet(struct sk_buff * skb, struct net_device *dev)
                 data->txskbs[tx] = skb;
 
                 if (i == 0) {
-                        data->txring[tx].buf0 = dma_map_single(NULL, skb->data,
-                                        skb_headlen(skb), DMA_TO_DEVICE);
+                        data->txring[tx].buf0 = dma_map_single(&data->pdev->dev,
+                                        skb->data, skb_headlen(skb),
+                                        DMA_TO_DEVICE);
                         data->txring[tx].len = skb_headlen(skb);
                         misc |= TSI108_TX_SOF;
                 } else {
                         const skb_frag_t *frag = &skb_shinfo(skb)->frags[i - 1];
 
-                        data->txring[tx].buf0 = skb_frag_dma_map(NULL, frag,
-                                                                 0,
-                                                                 skb_frag_size(frag),
-                                                                 DMA_TO_DEVICE);
+                        data->txring[tx].buf0 =
+                                skb_frag_dma_map(&data->pdev->dev, frag,
+                                                0, skb_frag_size(frag),
+                                                DMA_TO_DEVICE);
                         data->txring[tx].len = skb_frag_size(frag);
                 }
 
@@ -808,9 +811,9 @@ static int tsi108_refill_rx(struct net_device *dev, int budget)
                 if (!skb)
                         break;
 
-                data->rxring[rx].buf0 = dma_map_single(NULL, skb->data,
-                                                        TSI108_RX_SKB_SIZE,
-                                                        DMA_FROM_DEVICE);
+                data->rxring[rx].buf0 = dma_map_single(&data->pdev->dev,
+                                skb->data, TSI108_RX_SKB_SIZE,
+                                DMA_FROM_DEVICE);
 
                 /* Sometimes the hardware sets blen to zero after packet
                  * reception, even though the manual says that it's only ever
@@ -1308,15 +1311,15 @@ static int tsi108_open(struct net_device *dev)
                        data->id, dev->irq, dev->name);
         }
 
-        data->rxring = dma_zalloc_coherent(NULL, rxring_size, &data->rxdma,
-                                           GFP_KERNEL);
+        data->rxring = dma_zalloc_coherent(&data->pdev->dev, rxring_size,
+                        &data->rxdma, GFP_KERNEL);
         if (!data->rxring)
                 return -ENOMEM;
 
-        data->txring = dma_zalloc_coherent(NULL, txring_size, &data->txdma,
-                                           GFP_KERNEL);
+        data->txring = dma_zalloc_coherent(&data->pdev->dev, txring_size,
+                        &data->txdma, GFP_KERNEL);
         if (!data->txring) {
-                pci_free_consistent(NULL, rxring_size, data->rxring,
+                dma_free_coherent(&data->pdev->dev, rxring_size, data->rxring,
                                     data->rxdma);
                 return -ENOMEM;
         }
@@ -1428,10 +1431,10 @@ static int tsi108_close(struct net_device *dev)
                 dev_kfree_skb(skb);
         }
 
-        dma_free_coherent(0,
+        dma_free_coherent(&data->pdev->dev,
                             TSI108_RXRING_LEN * sizeof(rx_desc),
                             data->rxring, data->rxdma);
-        dma_free_coherent(0,
+        dma_free_coherent(&data->pdev->dev,
                             TSI108_TXRING_LEN * sizeof(tx_desc),
                             data->txring, data->txdma);
 
@@ -1576,6 +1579,7 @@ tsi108_init_one(struct platform_device *pdev)
         printk("tsi108_eth%d: probe...\n", pdev->id);
         data = netdev_priv(dev);
         data->dev = dev;
+        data->pdev = pdev;
 
         pr_debug("tsi108_eth%d:regs:phyresgs:phy:irq_num=0x%x:0x%x:0x%x:0x%x\n",
                         pdev->id, einfo->regs, einfo->phyregs,
diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
index ad9a9578f9c4..ee244c2e8c2b 100644
--- a/drivers/of/Kconfig
+++ b/drivers/of/Kconfig
@@ -62,10 +62,6 @@ config OF_DYNAMIC
 config OF_ADDRESS
         def_bool y
         depends on !SPARC && HAS_IOMEM
-        select OF_ADDRESS_PCI if PCI
-
-config OF_ADDRESS_PCI
-        bool
 
 config OF_IRQ
         def_bool y
@@ -82,18 +78,6 @@ config OF_MDIO
         help
           OpenFirmware MDIO bus (Ethernet PHY) accessors
 
-config OF_PCI
-        def_tristate PCI
-        depends on PCI
-        help
-          OpenFirmware PCI bus accessors
-
-config OF_PCI_IRQ
-        def_tristate PCI
-        depends on OF_PCI && OF_IRQ
-        help
-          OpenFirmware PCI IRQ routing helpers
-
 config OF_RESERVED_MEM
         depends on OF_EARLY_FLATTREE
         bool
diff --git a/drivers/of/Makefile b/drivers/of/Makefile
index 63a4be62ce19..663a4af0cccd 100644
--- a/drivers/of/Makefile
+++ b/drivers/of/Makefile
@@ -10,8 +10,6 @@ obj-$(CONFIG_OF_IRQ)    += irq.o
 obj-$(CONFIG_OF_NET)    += of_net.o
 obj-$(CONFIG_OF_UNITTEST) += unittest.o
 obj-$(CONFIG_OF_MDIO)   += of_mdio.o
-obj-$(CONFIG_OF_PCI)    += of_pci.o
-obj-$(CONFIG_OF_PCI_IRQ)  += of_pci_irq.o
 obj-$(CONFIG_OF_RESERVED_MEM) += of_reserved_mem.o
 obj-$(CONFIG_OF_RESOLVE)  += resolver.o
 obj-$(CONFIG_OF_OVERLAY) += overlay.o
diff --git a/drivers/of/address.c b/drivers/of/address.c
index fa6cabfc3cb9..a4984e7364b1 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -96,7 +96,7 @@ static unsigned int of_bus_default_get_flags(const __be32 *addr)
         return IORESOURCE_MEM;
 }
 
-#ifdef CONFIG_OF_ADDRESS_PCI
+#ifdef CONFIG_PCI
 /*
  * PCI bus specific translator
  */
@@ -171,9 +171,7 @@ static int of_bus_pci_translate(__be32 *addr, u64 offset, int na)
 {
         return of_bus_default_translate(addr + 1, offset, na - 1);
 }
-#endif /* CONFIG_OF_ADDRESS_PCI */
 
-#ifdef CONFIG_PCI
 const __be32 *of_get_pci_address(struct device_node *dev, int bar_no, u64 *size,
                         unsigned int *flags)
 {
@@ -361,6 +359,7 @@ invalid_range:
         res->end = (resource_size_t)OF_BAD_ADDR;
         return err;
 }
+EXPORT_SYMBOL(of_pci_range_to_resource);
 #endif /* CONFIG_PCI */
 
 /*
@@ -426,7 +425,7 @@ static unsigned int of_bus_isa_get_flags(const __be32 *addr)
  */
 
 static struct of_bus of_busses[] = {
-#ifdef CONFIG_OF_ADDRESS_PCI
+#ifdef CONFIG_PCI
         /* PCI */
         {
                 .name = "pci",
@@ -437,7 +436,7 @@ static struct of_bus of_busses[] = {
                 .translate = of_bus_pci_translate,
                 .get_flags = of_bus_pci_get_flags,
         },
-#endif /* CONFIG_OF_ADDRESS_PCI */
+#endif /* CONFIG_PCI */
         /* ISA */
         {
                 .name = "isa",
diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c
deleted file mode 100644
index a7b1cb6c2f65..000000000000
--- a/drivers/of/of_pci.c
+++ /dev/null
@@ -1,384 +0,0 @@
-#define pr_fmt(fmt)     "OF: PCI: " fmt
-
-#include <linux/kernel.h>
-#include <linux/export.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/of_pci.h>
-#include <linux/slab.h>
-
-static inline int __of_pci_pci_compare(struct device_node *node,
-                                       unsigned int data)
-{
-        int devfn;
-
-        devfn = of_pci_get_devfn(node);
-        if (devfn < 0)
-                return 0;
-
-        return devfn == data;
-}
-
-struct device_node *of_pci_find_child_device(struct device_node *parent,
-                                             unsigned int devfn)
-{
-        struct device_node *node, *node2;
-
-        for_each_child_of_node(parent, node) {
-                if (__of_pci_pci_compare(node, devfn))
-                        return node;
-                /*
-                 * Some OFs create a parent node "multifunc-device" as
-                 * a fake root for all functions of a multi-function
-                 * device we go down them as well.
-                 */
-                if (!strcmp(node->name, "multifunc-device")) {
-                        for_each_child_of_node(node, node2) {
-                                if (__of_pci_pci_compare(node2, devfn)) {
-                                        of_node_put(node);
-                                        return node2;
-                                }
-                        }
-                }
-        }
-        return NULL;
-}
-EXPORT_SYMBOL_GPL(of_pci_find_child_device);
-
-/**
- * of_pci_get_devfn() - Get device and function numbers for a device node
- * @np: device node
- *
- * Parses a standard 5-cell PCI resource and returns an 8-bit value that can
- * be passed to the PCI_SLOT() and PCI_FUNC() macros to extract the device
- * and function numbers respectively. On error a negative error code is
- * returned.
- */
-int of_pci_get_devfn(struct device_node *np)
-{
-        u32 reg[5];
-        int error;
-
-        error = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg));
-        if (error)
-                return error;
-
-        return (reg[0] >> 8) & 0xff;
-}
-EXPORT_SYMBOL_GPL(of_pci_get_devfn);
-
-/**
- * of_pci_parse_bus_range() - parse the bus-range property of a PCI device
- * @node: device node
- * @res: address to a struct resource to return the bus-range
- *
- * Returns 0 on success or a negative error-code on failure.
- */
-int of_pci_parse_bus_range(struct device_node *node, struct resource *res)
-{
-        u32 bus_range[2];
-        int error;
-
-        error = of_property_read_u32_array(node, "bus-range", bus_range,
-                                           ARRAY_SIZE(bus_range));
-        if (error)
-                return error;
-
-        res->name = node->name;
-        res->start = bus_range[0];
-        res->end = bus_range[1];
-        res->flags = IORESOURCE_BUS;
-
-        return 0;
-}
-EXPORT_SYMBOL_GPL(of_pci_parse_bus_range);
-
-/**
- * This function will try to obtain the host bridge domain number by
- * finding a property called "linux,pci-domain" of the given device node.
- *
- * @node: device tree node with the domain information
- *
- * Returns the associated domain number from DT in the range [0-0xffff], or
- * a negative value if the required property is not found.
- */
-int of_get_pci_domain_nr(struct device_node *node)
-{
-        u32 domain;
-        int error;
-
-        error = of_property_read_u32(node, "linux,pci-domain", &domain);
-        if (error)
-                return error;
-
-        return (u16)domain;
-}
-EXPORT_SYMBOL_GPL(of_get_pci_domain_nr);
-
-/**
- * This function will try to find the limitation of link speed by finding
- * a property called "max-link-speed" of the given device node.
- *
- * @node: device tree node with the max link speed information
- *
- * Returns the associated max link speed from DT, or a negative value if the
- * required property is not found or is invalid.
- */
-int of_pci_get_max_link_speed(struct device_node *node)
-{
-        u32 max_link_speed;
-
-        if (of_property_read_u32(node, "max-link-speed", &max_link_speed) ||
-            max_link_speed > 4)
-                return -EINVAL;
-
-        return max_link_speed;
-}
-EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed);
-
-/**
- * of_pci_check_probe_only - Setup probe only mode if linux,pci-probe-only
- *                           is present and valid
- */
-void of_pci_check_probe_only(void)
-{
-        u32 val;
-        int ret;
-
-        ret = of_property_read_u32(of_chosen, "linux,pci-probe-only", &val);
-        if (ret) {
-                if (ret == -ENODATA || ret == -EOVERFLOW)
-                        pr_warn("linux,pci-probe-only without valid value, ignoring\n");
-                return;
-        }
-
-        if (val)
-                pci_add_flags(PCI_PROBE_ONLY);
-        else
-                pci_clear_flags(PCI_PROBE_ONLY);
-
-        pr_info("PROBE_ONLY %sabled\n", val ? "en" : "dis");
-}
-EXPORT_SYMBOL_GPL(of_pci_check_probe_only);
-
-#if defined(CONFIG_OF_ADDRESS)
-/**
- * of_pci_get_host_bridge_resources - Parse PCI host bridge resources from DT
- * @dev: device node of the host bridge having the range property
- * @busno: bus number associated with the bridge root bus
- * @bus_max: maximum number of buses for this bridge
- * @resources: list where the range of resources will be added after DT parsing
- * @io_base: pointer to a variable that will contain on return the physical
- * address for the start of the I/O range. Can be NULL if the caller doesn't
- * expect IO ranges to be present in the device tree.
- *
- * It is the caller's job to free the @resources list.
- *
- * This function will parse the "ranges" property of a PCI host bridge device
- * node and setup the resource mapping based on its content. It is expected
- * that the property conforms with the Power ePAPR document.
- *
- * It returns zero if the range parsing has been successful or a standard error
- * value if it failed.
- */
-int of_pci_get_host_bridge_resources(struct device_node *dev,
-                        unsigned char busno, unsigned char bus_max,
-                        struct list_head *resources, resource_size_t *io_base)
-{
-        struct resource_entry *window;
-        struct resource *res;
-        struct resource *bus_range;
-        struct of_pci_range range;
-        struct of_pci_range_parser parser;
-        char range_type[4];
-        int err;
-
-        if (io_base)
-                *io_base = (resource_size_t)OF_BAD_ADDR;
-
-        bus_range = kzalloc(sizeof(*bus_range), GFP_KERNEL);
-        if (!bus_range)
-                return -ENOMEM;
-
-        pr_info("host bridge %pOF ranges:\n", dev);
-
-        err = of_pci_parse_bus_range(dev, bus_range);
-        if (err) {
-                bus_range->start = busno;
-                bus_range->end = bus_max;
-                bus_range->flags = IORESOURCE_BUS;
-                pr_info("  No bus range found for %pOF, using %pR\n",
-                        dev, bus_range);
-        } else {
-                if (bus_range->end > bus_range->start + bus_max)
-                        bus_range->end = bus_range->start + bus_max;
-        }
-        pci_add_resource(resources, bus_range);
-
-        /* Check for ranges property */
-        err = of_pci_range_parser_init(&parser, dev);
-        if (err)
-                goto parse_failed;
-
-        pr_debug("Parsing ranges property...\n");
-        for_each_of_pci_range(&parser, &range) {
-                /* Read next ranges element */
-                if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO)
-                        snprintf(range_type, 4, " IO");
-                else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM)
-                        snprintf(range_type, 4, "MEM");
-                else
-                        snprintf(range_type, 4, "err");
-                pr_info("  %s %#010llx..%#010llx -> %#010llx\n", range_type,
-                        range.cpu_addr, range.cpu_addr + range.size - 1,
-                        range.pci_addr);
-
-                /*
-                 * If we failed translation or got a zero-sized region
-                 * then skip this range
-                 */
-                if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
-                        continue;
-
-                res = kzalloc(sizeof(struct resource), GFP_KERNEL);
-                if (!res) {
-                        err = -ENOMEM;
-                        goto parse_failed;
-                }
-
-                err = of_pci_range_to_resource(&range, dev, res);
-                if (err) {
-                        kfree(res);
-                        continue;
-                }
-
-                if (resource_type(res) == IORESOURCE_IO) {
-                        if (!io_base) {
-                                pr_err("I/O range found for %pOF. Please provide an io_base pointer to save CPU base address\n",
-                                        dev);
-                                err = -EINVAL;
-                                goto conversion_failed;
-                        }
-                        if (*io_base != (resource_size_t)OF_BAD_ADDR)
-                                pr_warn("More than one I/O resource converted for %pOF. CPU base address for old range lost!\n",
-                                        dev);
-                        *io_base = range.cpu_addr;
-                }
-
-                pci_add_resource_offset(resources, res, res->start - range.pci_addr);
-        }
-
-        return 0;
-
-conversion_failed:
-        kfree(res);
-parse_failed:
-        resource_list_for_each_entry(window, resources)
-                kfree(window->res);
-        pci_free_resource_list(resources);
-        return err;
-}
-EXPORT_SYMBOL_GPL(of_pci_get_host_bridge_resources);
-#endif /* CONFIG_OF_ADDRESS */
-
-/**
- * of_pci_map_rid - Translate a requester ID through a downstream mapping.
- * @np: root complex device node.
- * @rid: PCI requester ID to map.
- * @map_name: property name of the map to use.
- * @map_mask_name: optional property name of the mask to use.
- * @target: optional pointer to a target device node.
- * @id_out: optional pointer to receive the translated ID.
- *
- * Given a PCI requester ID, look up the appropriate implementation-defined
- * platform ID and/or the target device which receives transactions on that
- * ID, as per the "iommu-map" and "msi-map" bindings. Either of @target or
- * @id_out may be NULL if only the other is required. If @target points to
- * a non-NULL device node pointer, only entries targeting that node will be
- * matched; if it points to a NULL value, it will receive the device node of
- * the first matching target phandle, with a reference held.
- *
- * Return: 0 on success or a standard error code on failure.
- */
-int of_pci_map_rid(struct device_node *np, u32 rid,
-                   const char *map_name, const char *map_mask_name,
-                   struct device_node **target, u32 *id_out)
-{
-        u32 map_mask, masked_rid;
-        int map_len;
-        const __be32 *map = NULL;
-
-        if (!np || !map_name || (!target && !id_out))
-                return -EINVAL;
-
-        map = of_get_property(np, map_name, &map_len);
-        if (!map) {
-                if (target)
-                        return -ENODEV;
-                /* Otherwise, no map implies no translation */
-                *id_out = rid;
-                return 0;
-        }
-
-        if (!map_len || map_len % (4 * sizeof(*map))) {
-                pr_err("%pOF: Error: Bad %s length: %d\n", np,
-                        map_name, map_len);
-                return -EINVAL;
-        }
-
-        /* The default is to select all bits. */
-        map_mask = 0xffffffff;
-
-        /*
-         * Can be overridden by "{iommu,msi}-map-mask" property.
-         * If of_property_read_u32() fails, the default is used.
-         */
-        if (map_mask_name)
-                of_property_read_u32(np, map_mask_name, &map_mask);
-
-        masked_rid = map_mask & rid;
-        for ( ; map_len > 0; map_len -= 4 * sizeof(*map), map += 4) {
-                struct device_node *phandle_node;
-                u32 rid_base = be32_to_cpup(map + 0);
-                u32 phandle = be32_to_cpup(map + 1);
-                u32 out_base = be32_to_cpup(map + 2);
-                u32 rid_len = be32_to_cpup(map + 3);
-
-                if (rid_base & ~map_mask) {
-                        pr_err("%pOF: Invalid %s translation - %s-mask (0x%x) ignores rid-base (0x%x)\n",
-                                np, map_name, map_name,
-                                map_mask, rid_base);
-                        return -EFAULT;
-                }
-
-                if (masked_rid < rid_base || masked_rid >= rid_base + rid_len)
-                        continue;
-
-                phandle_node = of_find_node_by_phandle(phandle);
-                if (!phandle_node)
-                        return -ENODEV;
-
-                if (target) {
-                        if (*target)
-                                of_node_put(phandle_node);
-                        else
-                                *target = phandle_node;
-
-                        if (*target != phandle_node)
-                                continue;
-                }
-
-                if (id_out)
-                        *id_out = masked_rid - rid_base + out_base;
-
-                pr_debug("%pOF: %s, using mask %08x, rid-base: %08x, out-base: %08x, length: %08x, rid: %08x -> %08x\n",
-                        np, map_name, map_mask, rid_base, out_base,
-                        rid_len, rid, masked_rid - rid_base + out_base);
-                return 0;
-        }
-
-        pr_err("%pOF: Invalid %s translation - no match for rid 0x%x on %pOF\n",
-                np, map_name, rid, target && *target ? *target : NULL);
-        return -EFAULT;
-}
diff --git a/drivers/of/of_pci_irq.c b/drivers/of/of_pci_irq.c
deleted file mode 100644
index 3a05568f65df..000000000000
--- a/drivers/of/of_pci_irq.c
+++ /dev/null
@@ -1,131 +0,0 @@
-#include <linux/kernel.h>
-#include <linux/of_pci.h>
-#include <linux/of_irq.h>
-#include <linux/export.h>
-
-/**
- * of_irq_parse_pci - Resolve the interrupt for a PCI device
- * @pdev:       the device whose interrupt is to be resolved
- * @out_irq:    structure of_irq filled by this function
- *
- * This function resolves the PCI interrupt for a given PCI device. If a
- * device-node exists for a given pci_dev, it will use normal OF tree
- * walking. If not, it will implement standard swizzling and walk up the
- * PCI tree until an device-node is found, at which point it will finish
- * resolving using the OF tree walking.
- */
-int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *out_irq)
-{
-        struct device_node *dn, *ppnode;
-        struct pci_dev *ppdev;
-        __be32 laddr[3];
-        u8 pin;
-        int rc;
-
-        /* Check if we have a device node, if yes, fallback to standard
-         * device tree parsing
-         */
-        dn = pci_device_to_OF_node(pdev);
-        if (dn) {
-                rc = of_irq_parse_one(dn, 0, out_irq);
-                if (!rc)
-                        return rc;
-        }
-
-        /* Ok, we don't, time to have fun. Let's start by building up an
-         * interrupt spec.  we assume #interrupt-cells is 1, which is standard
-         * for PCI. If you do different, then don't use that routine.
-         */
-        rc = pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pin);
-        if (rc != 0)
-                goto err;
-        /* No pin, exit with no error message. */
-        if (pin == 0)
-                return -ENODEV;
-
-        /* Now we walk up the PCI tree */
-        for (;;) {
-                /* Get the pci_dev of our parent */
-                ppdev = pdev->bus->self;
-
-                /* Ouch, it's a host bridge... */
-                if (ppdev == NULL) {
-                        ppnode = pci_bus_to_OF_node(pdev->bus);
-
-                        /* No node for host bridge ? give up */
-                        if (ppnode == NULL) {
-                                rc = -EINVAL;
-                                goto err;
-                        }
-                } else {
-                        /* We found a P2P bridge, check if it has a node */
-                        ppnode = pci_device_to_OF_node(ppdev);
-                }
-
-                /* Ok, we have found a parent with a device-node, hand over to
-                 * the OF parsing code.
-                 * We build a unit address from the linux device to be used for
-                 * resolution. Note that we use the linux bus number which may
-                 * not match your firmware bus numbering.
-                 * Fortunately, in most cases, interrupt-map-mask doesn't
-                 * include the bus number as part of the matching.
-                 * You should still be careful about that though if you intend
-                 * to rely on this function (you ship  a firmware that doesn't
-                 * create device nodes for all PCI devices).
-                 */
-                if (ppnode)
-                        break;
-
-                /* We can only get here if we hit a P2P bridge with no node,
-                 * let's do standard swizzling and try again
-                 */
-                pin = pci_swizzle_interrupt_pin(pdev, pin);
-                pdev = ppdev;
-        }
-
-        out_irq->np = ppnode;
-        out_irq->args_count = 1;
-        out_irq->args[0] = pin;
-        laddr[0] = cpu_to_be32((pdev->bus->number << 16) | (pdev->devfn << 8));
-        laddr[1] = laddr[2] = cpu_to_be32(0);
-        rc = of_irq_parse_raw(laddr, out_irq);
-        if (rc)
-                goto err;
-        return 0;
-err:
-        if (rc == -ENOENT) {
-                dev_warn(&pdev->dev,
-                        "%s: no interrupt-map found, INTx interrupts not available\n",
-                        __func__);
-                pr_warn_once("%s: possibly some PCI slots don't have level triggered interrupts capability\n",
-                        __func__);
-        } else {
-                dev_err(&pdev->dev, "%s: failed with rc=%d\n", __func__, rc);
-        }
-        return rc;
-}
-EXPORT_SYMBOL_GPL(of_irq_parse_pci);
-
-/**
- * of_irq_parse_and_map_pci() - Decode a PCI irq from the device tree and map to a virq
- * @dev: The pci device needing an irq
- * @slot: PCI slot number; passed when used as map_irq callback. Unused
- * @pin: PCI irq pin number; passed when used as map_irq callback. Unused
- *
- * @slot and @pin are unused, but included in the function so that this
- * function can be used directly as the map_irq callback to
- * pci_assign_irq() and struct pci_host_bridge.map_irq pointer
- */
-int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-        struct of_phandle_args oirq;
-        int ret;
-
-        ret = of_irq_parse_pci(dev, &oirq);
-        if (ret)
-                return 0; /* Proper return code 0 == NO_IRQ */
-
-        return irq_create_of_mapping(&oirq);
-}
-EXPORT_SYMBOL_GPL(of_irq_parse_and_map_pci);
-
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 949aa74206cd..34b56a8f8480 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -126,6 +126,7 @@ config PCI_PASID
 
 config PCI_LABEL
         def_bool y if (DMI || ACPI)
+        depends on PCI
         select NLS
 
 config PCI_HYPERV
@@ -136,6 +137,7 @@ config PCI_HYPERV
           PCI devices from a PCI backend to support PCI driver domains.
 
 source "drivers/pci/hotplug/Kconfig"
+source "drivers/pci/cadence/Kconfig"
 source "drivers/pci/dwc/Kconfig"
 source "drivers/pci/host/Kconfig"
 source "drivers/pci/endpoint/Kconfig"
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index c7819b973df7..941970936840 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -3,12 +3,15 @@
 # Makefile for the PCI bus specific drivers.
 #
 
-obj-y           += access.o bus.o probe.o host-bridge.o remove.o pci.o \
+obj-$(CONFIG_PCI)       += access.o bus.o probe.o host-bridge.o remove.o pci.o \
                         pci-driver.o search.o pci-sysfs.o rom.o setup-res.o \
                         irq.o vpd.o setup-bus.o vc.o mmap.o setup-irq.o
 
+ifdef CONFIG_PCI
 obj-$(CONFIG_PROC_FS) += proc.o
 obj-$(CONFIG_SYSFS) += slot.o
+obj-$(CONFIG_OF) += of.o
+endif
 
 obj-$(CONFIG_PCI_QUIRKS) += quirks.o
 
@@ -44,10 +47,15 @@ obj-$(CONFIG_PCI_ECAM) += ecam.o
 
 obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen-pcifront.o
 
-obj-$(CONFIG_OF) += of.o
-
 ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG
 
 # PCI host controller drivers
 obj-y += host/
 obj-y += switch/
+
+obj-$(CONFIG_PCI_ENDPOINT)      += endpoint/
+
+# Endpoint library must be initialized before its users
+obj-$(CONFIG_PCIE_CADENCE)      += cadence/
+# pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
+obj-y                           += dwc/
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 5a64da3fb033..5e9a9822d9d4 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -334,8 +334,7 @@ static size_t pci_vpd_size(struct pci_dev *dev, size_t old_size)
                             (tag == PCI_VPD_LTIN_RW_DATA)) {
                                 if (pci_read_vpd(dev, off+1, 2,
                                                  &header[1]) != 2) {
-                                        dev_warn(&dev->dev,
-                                                 "invalid large VPD tag %02x size at offset %zu",
+                                        pci_warn(dev, "invalid large VPD tag %02x size at offset %zu",
                                                  tag, off + 1);
                                         return 0;
                                 }
@@ -355,8 +354,7 @@ static size_t pci_vpd_size(struct pci_dev *dev, size_t old_size)
                 if ((tag != PCI_VPD_LTIN_ID_STRING) &&
                     (tag != PCI_VPD_LTIN_RO_DATA) &&
                     (tag != PCI_VPD_LTIN_RW_DATA)) {
-                        dev_warn(&dev->dev,
-                                 "invalid %s VPD tag %02x at offset %zu",
+                        pci_warn(dev, "invalid %s VPD tag %02x at offset %zu",
                                  (header[0] & PCI_VPD_LRDT) ? "large" : "short",
                                  tag, off);
                         return 0;
@@ -403,7 +401,7 @@ static int pci_vpd_wait(struct pci_dev *dev)
                         max_sleep *= 2;
         }
 
-        dev_warn(&dev->dev, "VPD access failed.  This is likely a firmware bug on this device.  Contact the card vendor for a firmware update\n");
+        pci_warn(dev, "VPD access failed.  This is likely a firmware bug on this device.  Contact the card vendor for a firmware update\n");
         return -ETIMEDOUT;
 }
 
diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c
index 30a4d33038bf..737d1c52f002 100644
--- a/drivers/pci/bus.c
+++ b/drivers/pci/bus.c
@@ -290,7 +290,7 @@ bool pci_bus_clip_resource(struct pci_dev *dev, int idx)
                 res->end = end;
                 res->flags &= ~IORESOURCE_UNSET;
                 orig_res.flags &= ~IORESOURCE_UNSET;
-                dev_printk(KERN_DEBUG, &dev->dev, "%pR clipped to %pR\n",
+                pci_printk(KERN_DEBUG, dev, "%pR clipped to %pR\n",
                                  &orig_res, res);
 
                 return true;
@@ -326,7 +326,7 @@ void pci_bus_add_device(struct pci_dev *dev)
         dev->match_driver = true;
         retval = device_attach(&dev->dev);
         if (retval < 0 && retval != -EPROBE_DEFER) {
-                dev_warn(&dev->dev, "device attach failed (%d)\n", retval);
+                pci_warn(dev, "device attach failed (%d)\n", retval);
                 pci_proc_detach_device(dev);
                 pci_remove_sysfs_dev_files(dev);
                 return;
diff --git a/drivers/pci/cadence/Kconfig b/drivers/pci/cadence/Kconfig
new file mode 100644
index 000000000000..e6824cb56c16
--- /dev/null
+++ b/drivers/pci/cadence/Kconfig
@@ -0,0 +1,27 @@
+menu "Cadence PCIe controllers support"
+
+config PCIE_CADENCE
+        bool
+
+config PCIE_CADENCE_HOST
+        bool "Cadence PCIe host controller"
+        depends on OF
+        depends on PCI
+        select IRQ_DOMAIN
+        select PCIE_CADENCE
+        help
+          Say Y here if you want to support the Cadence PCIe controller in host
+          mode. This PCIe controller may be embedded into many different vendors
+          SoCs.
+
+config PCIE_CADENCE_EP
+        bool "Cadence PCIe endpoint controller"
+        depends on OF
+        depends on PCI_ENDPOINT
+        select PCIE_CADENCE
+        help
+          Say Y here if you want to support the Cadence PCIe  controller in
+          endpoint mode. This PCIe controller may be embedded into many
+          different vendors SoCs.
+
+endmenu
diff --git a/drivers/pci/cadence/Makefile b/drivers/pci/cadence/Makefile
new file mode 100644
index 000000000000..719392b97998
--- /dev/null
+++ b/drivers/pci/cadence/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o
+obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o
+obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o
diff --git a/drivers/pci/cadence/pcie-cadence-ep.c b/drivers/pci/cadence/pcie-cadence-ep.c
new file mode 100644
index 000000000000..3c3a97743453
--- /dev/null
+++ b/drivers/pci/cadence/pcie-cadence-ep.c
@@ -0,0 +1,542 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2017 Cadence
+// Cadence PCIe endpoint controller driver.
+// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
+
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/pci-epc.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/sizes.h>
+
+#include "pcie-cadence.h"
+
+#define CDNS_PCIE_EP_MIN_APERTURE               128     /* 128 bytes */
+#define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE          0x1
+#define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY        0x3
+
+/**
+ * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver
+ * @pcie: Cadence PCIe controller
+ * @max_regions: maximum number of regions supported by hardware
+ * @ob_region_map: bitmask of mapped outbound regions
+ * @ob_addr: base addresses in the AXI bus where the outbound regions start
+ * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ
+ *                 dedicated outbound regions is mapped.
+ * @irq_cpu_addr: base address in the CPU space where a write access triggers
+ *                the sending of a memory write (MSI) / normal message (legacy
+ *                IRQ) TLP through the PCIe bus.
+ * @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ
+ *                dedicated outbound region.
+ * @irq_pci_fn: the latest PCI function that has updated the mapping of
+ *              the MSI/legacy IRQ dedicated outbound region.
+ * @irq_pending: bitmask of asserted legacy IRQs.
+ */
+struct cdns_pcie_ep {
+        struct cdns_pcie                pcie;
+        u32                             max_regions;
+        unsigned long                   ob_region_map;
+        phys_addr_t                     *ob_addr;
+        phys_addr_t                     irq_phys_addr;
+        void __iomem                    *irq_cpu_addr;
+        u64                             irq_pci_addr;
+        u8                              irq_pci_fn;
+        u8                              irq_pending;
+};
+
+static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn,
+                                     struct pci_epf_header *hdr)
+{
+        struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+        struct cdns_pcie *pcie = &ep->pcie;
+
+        cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
+        cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
+        cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code);
+        cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE,
+                               hdr->subclass_code | hdr->baseclass_code << 8);
+        cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
+                               hdr->cache_line_size);
+        cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id);
+        cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin);
+
+        /*
+         * Vendor ID can only be modified from function 0, all other functions
+         * use the same vendor ID as function 0.
+         */
+        if (fn == 0) {
+                /* Update the vendor IDs. */
+                u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) |
+                         CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id);
+
+                cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
+        }
+
+        return 0;
+}
+
+static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, enum pci_barno bar,
+                                dma_addr_t bar_phys, size_t size, int flags)
+{
+        struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+        struct cdns_pcie *pcie = &ep->pcie;
+        u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
+        u64 sz;
+
+        /* BAR size is 2^(aperture + 7) */
+        sz = max_t(size_t, size, CDNS_PCIE_EP_MIN_APERTURE);
+        /*
+         * roundup_pow_of_two() returns an unsigned long, which is not suited
+         * for 64bit values.
+         */
+        sz = 1ULL << fls64(sz - 1);
+        aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
+
+        if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
+                ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS;
+        } else {
+                bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
+                bool is_64bits = sz > SZ_2G;
+
+                if (is_64bits && (bar & 1))
+                        return -EINVAL;
+
+                if (is_64bits && is_prefetch)
+                        ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
+                else if (is_prefetch)
+                        ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
+                else if (is_64bits)
+                        ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS;
+                else
+                        ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS;
+        }
+
+        addr0 = lower_32_bits(bar_phys);
+        addr1 = upper_32_bits(bar_phys);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
+                         addr0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
+                         addr1);
+
+        if (bar < BAR_4) {
+                reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
+                b = bar;
+        } else {
+                reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
+                b = bar - BAR_4;
+        }
+
+        cfg = cdns_pcie_readl(pcie, reg);
+        cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
+                 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
+        cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
+                CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
+        cdns_pcie_writel(pcie, reg, cfg);
+
+        return 0;
+}
+
+static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn,
+                                   enum pci_barno bar)
+{
+        struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+        struct cdns_pcie *pcie = &ep->pcie;
+        u32 reg, cfg, b, ctrl;
+
+        if (bar < BAR_4) {
+                reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
+                b = bar;
+        } else {
+                reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
+                b = bar - BAR_4;
+        }
+
+        ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
+        cfg = cdns_pcie_readl(pcie, reg);
+        cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
+                 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
+        cfg |= CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);
+        cdns_pcie_writel(pcie, reg, cfg);
+
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0);
+}
+
+static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr,
+                                 u64 pci_addr, size_t size)
+{
+        struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+        struct cdns_pcie *pcie = &ep->pcie;
+        u32 r;
+
+        r = find_first_zero_bit(&ep->ob_region_map,
+                                sizeof(ep->ob_region_map) * BITS_PER_LONG);
+        if (r >= ep->max_regions - 1) {
+                dev_err(&epc->dev, "no free outbound region\n");
+                return -EINVAL;
+        }
+
+        cdns_pcie_set_outbound_region(pcie, fn, r, false, addr, pci_addr, size);
+
+        set_bit(r, &ep->ob_region_map);
+        ep->ob_addr[r] = addr;
+
+        return 0;
+}
+
+static void cdns_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn,
+                                    phys_addr_t addr)
+{
+        struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+        struct cdns_pcie *pcie = &ep->pcie;
+        u32 r;
+
+        for (r = 0; r < ep->max_regions - 1; r++)
+                if (ep->ob_addr[r] == addr)
+                        break;
+
+        if (r == ep->max_regions - 1)
+                return;
+
+        cdns_pcie_reset_outbound_region(pcie, r);
+
+        ep->ob_addr[r] = 0;
+        clear_bit(r, &ep->ob_region_map);
+}
+
+static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 mmc)
+{
+        struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+        struct cdns_pcie *pcie = &ep->pcie;
+        u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
+        u16 flags;
+
+        /*
+         * Set the Multiple Message Capable bitfield into the Message Control
+         * register.
+         */
+        flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
+        flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1);
+        flags |= PCI_MSI_FLAGS_64BIT;
+        flags &= ~PCI_MSI_FLAGS_MASKBIT;
+        cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags);
+
+        return 0;
+}
+
+static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn)
+{
+        struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+        struct cdns_pcie *pcie = &ep->pcie;
+        u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
+        u16 flags, mmc, mme;
+
+        /* Validate that the MSI feature is actually enabled. */
+        flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
+        if (!(flags & PCI_MSI_FLAGS_ENABLE))
+                return -EINVAL;
+
+        /*
+         * Get the Multiple Message Enable bitfield from the Message Control
+         * register.
+         */
+        mmc = (flags & PCI_MSI_FLAGS_QMASK) >> 1;
+        mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
+
+        return mme;
+}
+
+static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn,
+                                     u8 intx, bool is_asserted)
+{
+        struct cdns_pcie *pcie = &ep->pcie;
+        u32 r = ep->max_regions - 1;
+        u32 offset;
+        u16 status;
+        u8 msg_code;
+
+        intx &= 3;
+
+        /* Set the outbound region if needed. */
+        if (unlikely(ep->irq_pci_addr != CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY ||
+                     ep->irq_pci_fn != fn)) {
+                /* Last region was reserved for IRQ writes. */
+                cdns_pcie_set_outbound_region_for_normal_msg(pcie, fn, r,
+                                                             ep->irq_phys_addr);
+                ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY;
+                ep->irq_pci_fn = fn;
+        }
+
+        if (is_asserted) {
+                ep->irq_pending |= BIT(intx);
+                msg_code = MSG_CODE_ASSERT_INTA + intx;
+        } else {
+                ep->irq_pending &= ~BIT(intx);
+                msg_code = MSG_CODE_DEASSERT_INTA + intx;
+        }
+
+        status = cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS);
+        if (((status & PCI_STATUS_INTERRUPT) != 0) ^ (ep->irq_pending != 0)) {
+                status ^= PCI_STATUS_INTERRUPT;
+                cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status);
+        }
+
+        offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) |
+                 CDNS_PCIE_NORMAL_MSG_CODE(msg_code) |
+                 CDNS_PCIE_MSG_NO_DATA;
+        writel(0, ep->irq_cpu_addr + offset);
+}
+
+static int cdns_pcie_ep_send_legacy_irq(struct cdns_pcie_ep *ep, u8 fn, u8 intx)
+{
+        u16 cmd;
+
+        cmd = cdns_pcie_ep_fn_readw(&ep->pcie, fn, PCI_COMMAND);
+        if (cmd & PCI_COMMAND_INTX_DISABLE)
+                return -EINVAL;
+
+        cdns_pcie_ep_assert_intx(ep, fn, intx, true);
+        /*
+         * The mdelay() value was taken from dra7xx_pcie_raise_legacy_irq()
+         * from drivers/pci/dwc/pci-dra7xx.c
+         */
+        mdelay(1);
+        cdns_pcie_ep_assert_intx(ep, fn, intx, false);
+        return 0;
+}
+
+static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
+                                     u8 interrupt_num)
+{
+        struct cdns_pcie *pcie = &ep->pcie;
+        u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
+        u16 flags, mme, data, data_mask;
+        u8 msi_count;
+        u64 pci_addr, pci_addr_mask = 0xff;
+
+        /* Check whether the MSI feature has been enabled by the PCI host. */
+        flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
+        if (!(flags & PCI_MSI_FLAGS_ENABLE))
+                return -EINVAL;
+
+        /* Get the number of enabled MSIs */
+        mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
+        msi_count = 1 << mme;
+        if (!interrupt_num || interrupt_num > msi_count)
+                return -EINVAL;
+
+        /* Compute the data value to be written. */
+        data_mask = msi_count - 1;
+        data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64);
+        data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask);
+
+        /* Get the PCI address where to write the data into. */
+        pci_addr = cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI);
+        pci_addr <<= 32;
+        pci_addr |= cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO);
+        pci_addr &= GENMASK_ULL(63, 2);
+
+        /* Set the outbound region if needed. */
+        if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) ||
+                     ep->irq_pci_fn != fn)) {
+                /* Last region was reserved for IRQ writes. */
+                cdns_pcie_set_outbound_region(pcie, fn, ep->max_regions - 1,
+                                              false,
+                                              ep->irq_phys_addr,
+                                              pci_addr & ~pci_addr_mask,
+                                              pci_addr_mask + 1);
+                ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
+                ep->irq_pci_fn = fn;
+        }
+        writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
+
+        return 0;
+}
+
+static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
+                                  enum pci_epc_irq_type type, u8 interrupt_num)
+{
+        struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+
+        switch (type) {
+        case PCI_EPC_IRQ_LEGACY:
+                return cdns_pcie_ep_send_legacy_irq(ep, fn, 0);
+
+        case PCI_EPC_IRQ_MSI:
+                return cdns_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
+
+        default:
+                break;
+        }
+
+        return -EINVAL;
+}
+
+static int cdns_pcie_ep_start(struct pci_epc *epc)
+{
+        struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
+        struct cdns_pcie *pcie = &ep->pcie;
+        struct pci_epf *epf;
+        u32 cfg;
+
+        /*
+         * BIT(0) is hardwired to 1, hence function 0 is always enabled
+         * and can't be disabled anyway.
+         */
+        cfg = BIT(0);
+        list_for_each_entry(epf, &epc->pci_epf, list)
+                cfg |= BIT(epf->func_no);
+        cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, cfg);
+
+        /*
+         * The PCIe links are automatically established by the controller
+         * once for all at powerup: the software can neither start nor stop
+         * those links later at runtime.
+         *
+         * Then we only have to notify the EP core that our links are already
+         * established. However we don't call directly pci_epc_linkup() because
+         * we've already locked the epc->lock.
+         */
+        list_for_each_entry(epf, &epc->pci_epf, list)
+                pci_epf_linkup(epf);
+
+        return 0;
+}
+
+static const struct pci_epc_ops cdns_pcie_epc_ops = {
+        .write_header   = cdns_pcie_ep_write_header,
+        .set_bar        = cdns_pcie_ep_set_bar,
+        .clear_bar      = cdns_pcie_ep_clear_bar,
+        .map_addr       = cdns_pcie_ep_map_addr,
+        .unmap_addr     = cdns_pcie_ep_unmap_addr,
+        .set_msi        = cdns_pcie_ep_set_msi,
+        .get_msi        = cdns_pcie_ep_get_msi,
+        .raise_irq      = cdns_pcie_ep_raise_irq,
+        .start          = cdns_pcie_ep_start,
+};
+
+static const struct of_device_id cdns_pcie_ep_of_match[] = {
+        { .compatible = "cdns,cdns-pcie-ep" },
+
+        { },
+};
+
+static int cdns_pcie_ep_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct device_node *np = dev->of_node;
+        struct cdns_pcie_ep *ep;
+        struct cdns_pcie *pcie;
+        struct pci_epc *epc;
+        struct resource *res;
+        int ret;
+
+        ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
+        if (!ep)
+                return -ENOMEM;
+
+        pcie = &ep->pcie;
+        pcie->is_rc = false;
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
+        pcie->reg_base = devm_ioremap_resource(dev, res);
+        if (IS_ERR(pcie->reg_base)) {
+                dev_err(dev, "missing \"reg\"\n");
+                return PTR_ERR(pcie->reg_base);
+        }
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
+        if (!res) {
+                dev_err(dev, "missing \"mem\"\n");
+                return -EINVAL;
+        }
+        pcie->mem_res = res;
+
+        ret = of_property_read_u32(np, "cdns,max-outbound-regions",
+                                   &ep->max_regions);
+        if (ret < 0) {
+                dev_err(dev, "missing \"cdns,max-outbound-regions\"\n");
+                return ret;
+        }
+        ep->ob_addr = devm_kzalloc(dev, ep->max_regions * sizeof(*ep->ob_addr),
+                                   GFP_KERNEL);
+        if (!ep->ob_addr)
+                return -ENOMEM;
+
+        pm_runtime_enable(dev);
+        ret = pm_runtime_get_sync(dev);
+        if (ret < 0) {
+                dev_err(dev, "pm_runtime_get_sync() failed\n");
+                goto err_get_sync;
+        }
+
+        /* Disable all but function 0 (anyway BIT(0) is hardwired to 1). */
+        cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, BIT(0));
+
+        epc = devm_pci_epc_create(dev, &cdns_pcie_epc_ops);
+        if (IS_ERR(epc)) {
+                dev_err(dev, "failed to create epc device\n");
+                ret = PTR_ERR(epc);
+                goto err_init;
+        }
+
+        epc_set_drvdata(epc, ep);
+
+        if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0)
+                epc->max_functions = 1;
+
+        ret = pci_epc_mem_init(epc, pcie->mem_res->start,
+                               resource_size(pcie->mem_res));
+        if (ret < 0) {
+                dev_err(dev, "failed to initialize the memory space\n");
+                goto err_init;
+        }
+
+        ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
+                                                  SZ_128K);
+        if (!ep->irq_cpu_addr) {
+                dev_err(dev, "failed to reserve memory space for MSI\n");
+                ret = -ENOMEM;
+                goto free_epc_mem;
+        }
+        ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE;
+
+        return 0;
+
+ free_epc_mem:
+        pci_epc_mem_exit(epc);
+
+ err_init:
+        pm_runtime_put_sync(dev);
+
+ err_get_sync:
+        pm_runtime_disable(dev);
+
+        return ret;
+}
+
+static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        int ret;
+
+        ret = pm_runtime_put_sync(dev);
+        if (ret < 0)
+                dev_dbg(dev, "pm_runtime_put_sync failed\n");
+
+        pm_runtime_disable(dev);
+
+        /* The PCIe controller can't be disabled. */
+}
+
+static struct platform_driver cdns_pcie_ep_driver = {
+        .driver = {
+                .name = "cdns-pcie-ep",
+                .of_match_table = cdns_pcie_ep_of_match,
+        },
+        .probe = cdns_pcie_ep_probe,
+        .shutdown = cdns_pcie_ep_shutdown,
+};
+builtin_platform_driver(cdns_pcie_ep_driver);
diff --git a/drivers/pci/cadence/pcie-cadence-host.c b/drivers/pci/cadence/pcie-cadence-host.c
new file mode 100644
index 000000000000..a4ebbd37b553
--- /dev/null
+++ b/drivers/pci/cadence/pcie-cadence-host.c
@@ -0,0 +1,336 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2017 Cadence
+// Cadence PCIe host controller driver.
+// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
+
+#include <linux/kernel.h>
+#include <linux/of_address.h>
+#include <linux/of_pci.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include "pcie-cadence.h"
+
+/**
+ * struct cdns_pcie_rc - private data for this PCIe Root Complex driver
+ * @pcie: Cadence PCIe controller
+ * @dev: pointer to PCIe device
+ * @cfg_res: start/end offsets in the physical system memory to map PCI
+ *           configuration space accesses
+ * @bus_range: first/last buses behind the PCIe host controller
+ * @cfg_base: IO mapped window to access the PCI configuration space of a
+ *            single function at a time
+ * @max_regions: maximum number of regions supported by the hardware
+ * @no_bar_nbits: Number of bits to keep for inbound (PCIe -> CPU) address
+ *                translation (nbits sets into the "no BAR match" register)
+ * @vendor_id: PCI vendor ID
+ * @device_id: PCI device ID
+ */
+struct cdns_pcie_rc {
+        struct cdns_pcie        pcie;
+        struct device           *dev;
+        struct resource         *cfg_res;
+        struct resource         *bus_range;
+        void __iomem            *cfg_base;
+        u32                     max_regions;
+        u32                     no_bar_nbits;
+        u16                     vendor_id;
+        u16                     device_id;
+};
+
+static void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
+                                      int where)
+{
+        struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
+        struct cdns_pcie_rc *rc = pci_host_bridge_priv(bridge);
+        struct cdns_pcie *pcie = &rc->pcie;
+        unsigned int busn = bus->number;
+        u32 addr0, desc0;
+
+        if (busn == rc->bus_range->start) {
+                /*
+                 * Only the root port (devfn == 0) is connected to this bus.
+                 * All other PCI devices are behind some bridge hence on another
+                 * bus.
+                 */
+                if (devfn)
+                        return NULL;
+
+                return pcie->reg_base + (where & 0xfff);
+        }
+
+        /* Update Output registers for AXI region 0. */
+        addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(12) |
+                CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) |
+                CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(busn);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(0), addr0);
+
+        /* Configuration Type 0 or Type 1 access. */
+        desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
+                CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
+        /*
+         * The bus number was already set once for all in desc1 by
+         * cdns_pcie_host_init_address_translation().
+         */
+        if (busn == rc->bus_range->start + 1)
+                desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0;
+        else
+                desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1;
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(0), desc0);
+
+        return rc->cfg_base + (where & 0xfff);
+}
+
+static struct pci_ops cdns_pcie_host_ops = {
+        .map_bus        = cdns_pci_map_bus,
+        .read           = pci_generic_config_read,
+        .write          = pci_generic_config_write,
+};
+
+static const struct of_device_id cdns_pcie_host_of_match[] = {
+        { .compatible = "cdns,cdns-pcie-host" },
+
+        { },
+};
+
+static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
+{
+        struct cdns_pcie *pcie = &rc->pcie;
+        u32 value, ctrl;
+
+        /*
+         * Set the root complex BAR configuration register:
+         * - disable both BAR0 and BAR1.
+         * - enable Prefetchable Memory Base and Limit registers in type 1
+         *   config space (64 bits).
+         * - enable IO Base and Limit registers in type 1 config
+         *   space (32 bits).
+         */
+        ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
+        value = CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) |
+                CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) |
+                CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE |
+                CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS |
+                CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE |
+                CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS;
+        cdns_pcie_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value);
+
+        /* Set root port configuration space */
+        if (rc->vendor_id != 0xffff)
+                cdns_pcie_rp_writew(pcie, PCI_VENDOR_ID, rc->vendor_id);
+        if (rc->device_id != 0xffff)
+                cdns_pcie_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id);
+
+        cdns_pcie_rp_writeb(pcie, PCI_CLASS_REVISION, 0);
+        cdns_pcie_rp_writeb(pcie, PCI_CLASS_PROG, 0);
+        cdns_pcie_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI);
+
+        return 0;
+}
+
+static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
+{
+        struct cdns_pcie *pcie = &rc->pcie;
+        struct resource *cfg_res = rc->cfg_res;
+        struct resource *mem_res = pcie->mem_res;
+        struct resource *bus_range = rc->bus_range;
+        struct device *dev = rc->dev;
+        struct device_node *np = dev->of_node;
+        struct of_pci_range_parser parser;
+        struct of_pci_range range;
+        u32 addr0, addr1, desc1;
+        u64 cpu_addr;
+        int r, err;
+
+        /*
+         * Reserve region 0 for PCI configure space accesses:
+         * OB_REGION_PCI_ADDR0 and OB_REGION_DESC0 are updated dynamically by
+         * cdns_pci_map_bus(), other region registers are set here once for all.
+         */
+        addr1 = 0; /* Should be programmed to zero. */
+        desc1 = CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus_range->start);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1);
+
+        cpu_addr = cfg_res->start - mem_res->start;
+        addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) |
+                (lower_32_bits(cpu_addr) & GENMASK(31, 8));
+        addr1 = upper_32_bits(cpu_addr);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(0), addr0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(0), addr1);
+
+        err = of_pci_range_parser_init(&parser, np);
+        if (err)
+                return err;
+
+        r = 1;
+        for_each_of_pci_range(&parser, &range) {
+                bool is_io;
+
+                if (r >= rc->max_regions)
+                        break;
+
+                if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM)
+                        is_io = false;
+                else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO)
+                        is_io = true;
+                else
+                        continue;
+
+                cdns_pcie_set_outbound_region(pcie, 0, r, is_io,
+                                              range.cpu_addr,
+                                              range.pci_addr,
+                                              range.size);
+                r++;
+        }
+
+        /*
+         * Set Root Port no BAR match Inbound Translation registers:
+         * needed for MSI and DMA.
+         * Root Port BAR0 and BAR1 are disabled, hence no need to set their
+         * inbound translation registers.
+         */
+        addr0 = CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(rc->no_bar_nbits);
+        addr1 = 0;
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR0(RP_NO_BAR), addr0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR1(RP_NO_BAR), addr1);
+
+        return 0;
+}
+
+static int cdns_pcie_host_init(struct device *dev,
+                               struct list_head *resources,
+                               struct cdns_pcie_rc *rc)
+{
+        struct resource *bus_range = NULL;
+        int err;
+
+        /* Parse our PCI ranges and request their resources */
+        err = pci_parse_request_of_pci_ranges(dev, resources, &bus_range);
+        if (err)
+                return err;
+
+        rc->bus_range = bus_range;
+        rc->pcie.bus = bus_range->start;
+
+        err = cdns_pcie_host_init_root_port(rc);
+        if (err)
+                goto err_out;
+
+        err = cdns_pcie_host_init_address_translation(rc);
+        if (err)
+                goto err_out;
+
+        return 0;
+
+ err_out:
+        pci_free_resource_list(resources);
+        return err;
+}
+
+static int cdns_pcie_host_probe(struct platform_device *pdev)
+{
+        const char *type;
+        struct device *dev = &pdev->dev;
+        struct device_node *np = dev->of_node;
+        struct pci_host_bridge *bridge;
+        struct list_head resources;
+        struct cdns_pcie_rc *rc;
+        struct cdns_pcie *pcie;
+        struct resource *res;
+        int ret;
+
+        bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
+        if (!bridge)
+                return -ENOMEM;
+
+        rc = pci_host_bridge_priv(bridge);
+        rc->dev = dev;
+
+        pcie = &rc->pcie;
+        pcie->is_rc = true;
+
+        rc->max_regions = 32;
+        of_property_read_u32(np, "cdns,max-outbound-regions", &rc->max_regions);
+
+        rc->no_bar_nbits = 32;
+        of_property_read_u32(np, "cdns,no-bar-match-nbits", &rc->no_bar_nbits);
+
+        rc->vendor_id = 0xffff;
+        of_property_read_u16(np, "vendor-id", &rc->vendor_id);
+
+        rc->device_id = 0xffff;
+        of_property_read_u16(np, "device-id", &rc->device_id);
+
+        type = of_get_property(np, "device_type", NULL);
+        if (!type || strcmp(type, "pci")) {
+                dev_err(dev, "invalid \"device_type\" %s\n", type);
+                return -EINVAL;
+        }
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
+        pcie->reg_base = devm_ioremap_resource(dev, res);
+        if (IS_ERR(pcie->reg_base)) {
+                dev_err(dev, "missing \"reg\"\n");
+                return PTR_ERR(pcie->reg_base);
+        }
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
+        rc->cfg_base = devm_pci_remap_cfg_resource(dev, res);
+        if (IS_ERR(rc->cfg_base)) {
+                dev_err(dev, "missing \"cfg\"\n");
+                return PTR_ERR(rc->cfg_base);
+        }
+        rc->cfg_res = res;
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
+        if (!res) {
+                dev_err(dev, "missing \"mem\"\n");
+                return -EINVAL;
+        }
+        pcie->mem_res = res;
+
+        pm_runtime_enable(dev);
+        ret = pm_runtime_get_sync(dev);
+        if (ret < 0) {
+                dev_err(dev, "pm_runtime_get_sync() failed\n");
+                goto err_get_sync;
+        }
+
+        ret = cdns_pcie_host_init(dev, &resources, rc);
+        if (ret)
+                goto err_init;
+
+        list_splice_init(&resources, &bridge->windows);
+        bridge->dev.parent = dev;
+        bridge->busnr = pcie->bus;
+        bridge->ops = &cdns_pcie_host_ops;
+        bridge->map_irq = of_irq_parse_and_map_pci;
+        bridge->swizzle_irq = pci_common_swizzle;
+
+        ret = pci_host_probe(bridge);
+        if (ret < 0)
+                goto err_host_probe;
+
+        return 0;
+
+ err_host_probe:
+        pci_free_resource_list(&resources);
+
+ err_init:
+        pm_runtime_put_sync(dev);
+
+ err_get_sync:
+        pm_runtime_disable(dev);
+
+        return ret;
+}
+
+static struct platform_driver cdns_pcie_host_driver = {
+        .driver = {
+                .name = "cdns-pcie-host",
+                .of_match_table = cdns_pcie_host_of_match,
+        },
+        .probe = cdns_pcie_host_probe,
+};
+builtin_platform_driver(cdns_pcie_host_driver);
diff --git a/drivers/pci/cadence/pcie-cadence.c b/drivers/pci/cadence/pcie-cadence.c
new file mode 100644
index 000000000000..138d113eb45d
--- /dev/null
+++ b/drivers/pci/cadence/pcie-cadence.c
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2017 Cadence
+// Cadence PCIe controller driver.
+// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
+
+#include <linux/kernel.h>
+
+#include "pcie-cadence.h"
+
+void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 fn,
+                                   u32 r, bool is_io,
+                                   u64 cpu_addr, u64 pci_addr, size_t size)
+{
+        /*
+         * roundup_pow_of_two() returns an unsigned long, which is not suited
+         * for 64bit values.
+         */
+        u64 sz = 1ULL << fls64(size - 1);
+        int nbits = ilog2(sz);
+        u32 addr0, addr1, desc0, desc1;
+
+        if (nbits < 8)
+                nbits = 8;
+
+        /* Set the PCI address */
+        addr0 = CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) |
+                (lower_32_bits(pci_addr) & GENMASK(31, 8));
+        addr1 = upper_32_bits(pci_addr);
+
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), addr1);
+
+        /* Set the PCIe header descriptor */
+        if (is_io)
+                desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO;
+        else
+                desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM;
+        desc1 = 0;
+
+        /*
+         * Whatever Bit [23] is set or not inside DESC0 register of the outbound
+         * PCIe descriptor, the PCI function number must be set into
+         * Bits [26:24] of DESC0 anyway.
+         *
+         * In Root Complex mode, the function number is always 0 but in Endpoint
+         * mode, the PCIe controller may support more than one function. This
+         * function number needs to be set properly into the outbound PCIe
+         * descriptor.
+         *
+         * Besides, setting Bit [23] is mandatory when in Root Complex mode:
+         * then the driver must provide the bus, resp. device, number in
+         * Bits [7:0] of DESC1, resp. Bits[31:27] of DESC0. Like the function
+         * number, the device number is always 0 in Root Complex mode.
+         *
+         * However when in Endpoint mode, we can clear Bit [23] of DESC0, hence
+         * the PCIe controller will use the captured values for the bus and
+         * device numbers.
+         */
+        if (pcie->is_rc) {
+                /* The device and function numbers are always 0. */
+                desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
+                         CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
+                desc1 |= CDNS_PCIE_AT_OB_REGION_DESC1_BUS(pcie->bus);
+        } else {
+                /*
+                 * Use captured values for bus and device numbers but still
+                 * need to set the function number.
+                 */
+                desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(fn);
+        }
+
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(r), desc0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1);
+
+        /* Set the CPU address */
+        cpu_addr -= pcie->mem_res->start;
+        addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) |
+                (lower_32_bits(cpu_addr) & GENMASK(31, 8));
+        addr1 = upper_32_bits(cpu_addr);
+
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), addr0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), addr1);
+}
+
+void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn,
+                                                  u32 r, u64 cpu_addr)
+{
+        u32 addr0, addr1, desc0, desc1;
+
+        desc0 = CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG;
+        desc1 = 0;
+
+        /* See cdns_pcie_set_outbound_region() comments above. */
+        if (pcie->is_rc) {
+                desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID |
+                         CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(0);
+                desc1 |= CDNS_PCIE_AT_OB_REGION_DESC1_BUS(pcie->bus);
+        } else {
+                desc0 |= CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(fn);
+        }
+
+        /* Set the CPU address */
+        cpu_addr -= pcie->mem_res->start;
+        addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(17) |
+                (lower_32_bits(cpu_addr) & GENMASK(31, 8));
+        addr1 = upper_32_bits(cpu_addr);
+
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), 0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), 0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(r), desc0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), addr0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), addr1);
+}
+
+void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r)
+{
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), 0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), 0);
+
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(r), 0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), 0);
+
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r), 0);
+        cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r), 0);
+}
diff --git a/drivers/pci/cadence/pcie-cadence.h b/drivers/pci/cadence/pcie-cadence.h
new file mode 100644
index 000000000000..4bb27333b05c
--- /dev/null
+++ b/drivers/pci/cadence/pcie-cadence.h
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2017 Cadence
+// Cadence PCIe controller driver.
+// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
+
+#ifndef _PCIE_CADENCE_H
+#define _PCIE_CADENCE_H
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+
+/*
+ * Local Management Registers
+ */
+#define CDNS_PCIE_LM_BASE       0x00100000
+
+/* Vendor ID Register */
+#define CDNS_PCIE_LM_ID         (CDNS_PCIE_LM_BASE + 0x0044)
+#define  CDNS_PCIE_LM_ID_VENDOR_MASK    GENMASK(15, 0)
+#define  CDNS_PCIE_LM_ID_VENDOR_SHIFT   0
+#define  CDNS_PCIE_LM_ID_VENDOR(vid) \
+        (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK)
+#define  CDNS_PCIE_LM_ID_SUBSYS_MASK    GENMASK(31, 16)
+#define  CDNS_PCIE_LM_ID_SUBSYS_SHIFT   16
+#define  CDNS_PCIE_LM_ID_SUBSYS(sub) \
+        (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK)
+
+/* Root Port Requestor ID Register */
+#define CDNS_PCIE_LM_RP_RID     (CDNS_PCIE_LM_BASE + 0x0228)
+#define  CDNS_PCIE_LM_RP_RID_MASK       GENMASK(15, 0)
+#define  CDNS_PCIE_LM_RP_RID_SHIFT      0
+#define  CDNS_PCIE_LM_RP_RID_(rid) \
+        (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK)
+
+/* Endpoint Bus and Device Number Register */
+#define CDNS_PCIE_LM_EP_ID      (CDNS_PCIE_LM_BASE + 0x022c)
+#define  CDNS_PCIE_LM_EP_ID_DEV_MASK    GENMASK(4, 0)
+#define  CDNS_PCIE_LM_EP_ID_DEV_SHIFT   0
+#define  CDNS_PCIE_LM_EP_ID_BUS_MASK    GENMASK(15, 8)
+#define  CDNS_PCIE_LM_EP_ID_BUS_SHIFT   8
+
+/* Endpoint Function f BAR b Configuration Registers */
+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \
+        (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008)
+#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \
+        (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008)
+#define  CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \
+        (GENMASK(4, 0) << ((b) * 8))
+#define  CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \
+        (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b))
+#define  CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \
+        (GENMASK(7, 5) << ((b) * 8))
+#define  CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \
+        (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))
+
+/* Endpoint Function Configuration Register */
+#define CDNS_PCIE_LM_EP_FUNC_CFG        (CDNS_PCIE_LM_BASE + 0x02c0)
+
+/* Root Complex BAR Configuration Register */
+#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK     GENMASK(5, 0)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \
+        (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK         GENMASK(8, 6)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \
+        (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK     GENMASK(13, 9)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \
+        (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK         GENMASK(16, 14)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \
+        (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE    BIT(17)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS    0
+#define  CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS    BIT(18)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE              BIT(19)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS              0
+#define  CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS              BIT(20)
+#define  CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE           BIT(31)
+
+/* BAR control values applicable to both Endpoint Function and Root Complex */
+#define  CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED             0x0
+#define  CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS            0x1
+#define  CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS           0x4
+#define  CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS  0x5
+#define  CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS           0x6
+#define  CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS  0x7
+
+
+/*
+ * Endpoint Function Registers (PCI configuration space for endpoint functions)
+ */
+#define CDNS_PCIE_EP_FUNC_BASE(fn)      (((fn) << 12) & GENMASK(19, 12))
+
+#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET        0x90
+
+/*
+ * Root Port Registers (PCI configuration space for the root port function)
+ */
+#define CDNS_PCIE_RP_BASE       0x00200000
+
+
+/*
+ * Address Translation Registers
+ */
+#define CDNS_PCIE_AT_BASE       0x00400000
+
+/* Region r Outbound AXI to PCIe Address Translation Register 0 */
+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \
+        (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020)
+#define  CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK    GENMASK(5, 0)
+#define  CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \
+        (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
+#define  CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK    GENMASK(19, 12)
+#define  CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \
+        (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK)
+#define  CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK      GENMASK(27, 20)
+#define  CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \
+        (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK)
+
+/* Region r Outbound AXI to PCIe Address Translation Register 1 */
+#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \
+        (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020)
+
+/* Region r Outbound PCIe Descriptor Register 0 */
+#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \
+        (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020)
+#define  CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK         GENMASK(3, 0)
+#define  CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM          0x2
+#define  CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO           0x6
+#define  CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0   0xa
+#define  CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1   0xb
+#define  CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG   0xc
+#define  CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG   0xd
+/* Bit 23 MUST be set in RC mode. */
+#define  CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID     BIT(23)
+#define  CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK        GENMASK(31, 24)
+#define  CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \
+        (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK)
+
+/* Region r Outbound PCIe Descriptor Register 1 */
+#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \
+        (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020)
+#define  CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK  GENMASK(7, 0)
+#define  CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \
+        ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK)
+
+/* Region r AXI Region Base Address Register 0 */
+#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \
+        (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020)
+#define  CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK    GENMASK(5, 0)
+#define  CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \
+        (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
+
+/* Region r AXI Region Base Address Register 1 */
+#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \
+        (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020)
+
+/* Root Port BAR Inbound PCIe to AXI Address Translation Register */
+#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \
+        (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008)
+#define  CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK        GENMASK(5, 0)
+#define  CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \
+        (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
+#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
+        (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
+
+enum cdns_pcie_rp_bar {
+        RP_BAR0,
+        RP_BAR1,
+        RP_NO_BAR
+};
+
+/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */
+#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \
+        (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008)
+#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \
+        (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008)
+
+/* Normal/Vendor specific message access: offset inside some outbound region */
+#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK       GENMASK(7, 5)
+#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \
+        (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK)
+#define CDNS_PCIE_NORMAL_MSG_CODE_MASK          GENMASK(15, 8)
+#define CDNS_PCIE_NORMAL_MSG_CODE(code) \
+        (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK)
+#define CDNS_PCIE_MSG_NO_DATA                   BIT(16)
+
+enum cdns_pcie_msg_code {
+        MSG_CODE_ASSERT_INTA    = 0x20,
+        MSG_CODE_ASSERT_INTB    = 0x21,
+        MSG_CODE_ASSERT_INTC    = 0x22,
+        MSG_CODE_ASSERT_INTD    = 0x23,
+        MSG_CODE_DEASSERT_INTA  = 0x24,
+        MSG_CODE_DEASSERT_INTB  = 0x25,
+        MSG_CODE_DEASSERT_INTC  = 0x26,
+        MSG_CODE_DEASSERT_INTD  = 0x27,
+};
+
+enum cdns_pcie_msg_routing {
+        /* Route to Root Complex */
+        MSG_ROUTING_TO_RC,
+
+        /* Use Address Routing */
+        MSG_ROUTING_BY_ADDR,
+
+        /* Use ID Routing */
+        MSG_ROUTING_BY_ID,
+
+        /* Route as Broadcast Message from Root Complex */
+        MSG_ROUTING_BCAST,
+
+        /* Local message; terminate at receiver (INTx messages) */
+        MSG_ROUTING_LOCAL,
+
+        /* Gather & route to Root Complex (PME_TO_Ack message) */
+        MSG_ROUTING_GATHER,
+};
+
+/**
+ * struct cdns_pcie - private data for Cadence PCIe controller drivers
+ * @reg_base: IO mapped register base
+ * @mem_res: start/end offsets in the physical system memory to map PCI accesses
+ * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
+ * @bus: In Root Complex mode, the bus number
+ */
+struct cdns_pcie {
+        void __iomem            *reg_base;
+        struct resource         *mem_res;
+        bool                    is_rc;
+        u8                      bus;
+};
+
+/* Register access */
+static inline void cdns_pcie_writeb(struct cdns_pcie *pcie, u32 reg, u8 value)
+{
+        writeb(value, pcie->reg_base + reg);
+}
+
+static inline void cdns_pcie_writew(struct cdns_pcie *pcie, u32 reg, u16 value)
+{
+        writew(value, pcie->reg_base + reg);
+}
+
+static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value)
+{
+        writel(value, pcie->reg_base + reg);
+}
+
+static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg)
+{
+        return readl(pcie->reg_base + reg);
+}
+
+/* Root Port register access */
+static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie,
+                                       u32 reg, u8 value)
+{
+        writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg);
+}
+
+static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie,
+                                       u32 reg, u16 value)
+{
+        writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg);
+}
+
+/* Endpoint Function register access */
+static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn,
+                                          u32 reg, u8 value)
+{
+        writeb(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
+}
+
+static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn,
+                                          u32 reg, u16 value)
+{
+        writew(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
+}
+
+static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn,
+                                          u32 reg, u16 value)
+{
+        writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
+}
+
+static inline u8 cdns_pcie_ep_fn_readb(struct cdns_pcie *pcie, u8 fn, u32 reg)
+{
+        return readb(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
+}
+
+static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg)
+{
+        return readw(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
+}
+
+static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg)
+{
+        return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
+}
+
+void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 fn,
+                                   u32 r, bool is_io,
+                                   u64 cpu_addr, u64 pci_addr, size_t size);
+
+void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn,
+                                                  u32 r, u64 cpu_addr);
+
+void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r);
+
+#endif /* _PCIE_CADENCE_H */
diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
index fe1cb56b71f1..0f666b1ce289 100644
--- a/drivers/pci/dwc/Kconfig
+++ b/drivers/pci/dwc/Kconfig
@@ -17,39 +17,38 @@ config PCIE_DW_EP
         select PCIE_DW
 
 config PCI_DRA7XX
-        bool "TI DRA7xx PCIe controller"
-        depends on SOC_DRA7XX || COMPILE_TEST
-        depends on (PCI && PCI_MSI_IRQ_DOMAIN) || PCI_ENDPOINT
-        depends on OF && HAS_IOMEM && TI_PIPE3
-        help
-         Enables support for the PCIe controller in the DRA7xx SoC. There
-         are two instances of PCIe controller in DRA7xx. This controller can
-         work either as EP or RC. In order to enable host-specific features
-         PCI_DRA7XX_HOST must be selected and in order to enable device-
-         specific features PCI_DRA7XX_EP must be selected. This uses
-         the DesignWare core.
-
-if PCI_DRA7XX
+        bool
 
 config PCI_DRA7XX_HOST
-        bool "PCI DRA7xx Host Mode"
-        depends on PCI
-        depends on PCI_MSI_IRQ_DOMAIN
+        bool "TI DRA7xx PCIe controller Host Mode"
+        depends on SOC_DRA7XX || COMPILE_TEST
+        depends on PCI && PCI_MSI_IRQ_DOMAIN
+        depends on OF && HAS_IOMEM && TI_PIPE3
         select PCIE_DW_HOST
+        select PCI_DRA7XX
         default y
         help
-         Enables support for the PCIe controller in the DRA7xx SoC to work in
-         host mode.
+          Enables support for the PCIe controller in the DRA7xx SoC to work in
+          host mode. There are two instances of PCIe controller in DRA7xx.
+          This controller can work either as EP or RC. In order to enable
+          host-specific features PCI_DRA7XX_HOST must be selected and in order
+          to enable device-specific features PCI_DRA7XX_EP must be selected.
+          This uses the DesignWare core.
 
 config PCI_DRA7XX_EP
-        bool "PCI DRA7xx Endpoint Mode"
+        bool "TI DRA7xx PCIe controller Endpoint Mode"
+        depends on SOC_DRA7XX || COMPILE_TEST
         depends on PCI_ENDPOINT
+        depends on OF && HAS_IOMEM && TI_PIPE3
         select PCIE_DW_EP
+        select PCI_DRA7XX
         help
-         Enables support for the PCIe controller in the DRA7xx SoC to work in
-         endpoint mode.
-
-endif
+          Enables support for the PCIe controller in the DRA7xx SoC to work in
+          endpoint mode. There are two instances of PCIe controller in DRA7xx.
+          This controller can work either as EP or RC. In order to enable
+          host-specific features PCI_DRA7XX_HOST must be selected and in order
+          to enable device-specific features PCI_DRA7XX_EP must be selected.
+          This uses the DesignWare core.
 
 config PCIE_DW_PLAT
         bool "Platform bus based DesignWare PCIe Controller"
@@ -151,15 +150,28 @@ config PCIE_ARMADA_8K
           DesignWare core functions to implement the driver.
 
 config PCIE_ARTPEC6
-        bool "Axis ARTPEC-6 PCIe controller"
-        depends on PCI
+        bool
+
+config PCIE_ARTPEC6_HOST
+        bool "Axis ARTPEC-6 PCIe controller Host Mode"
         depends on MACH_ARTPEC6
-        depends on PCI_MSI_IRQ_DOMAIN
+        depends on PCI && PCI_MSI_IRQ_DOMAIN
         select PCIEPORTBUS
         select PCIE_DW_HOST
+        select PCIE_ARTPEC6
+        help
+          Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
+          host mode. This uses the DesignWare core.
+
+config PCIE_ARTPEC6_EP
+        bool "Axis ARTPEC-6 PCIe controller Endpoint Mode"
+        depends on MACH_ARTPEC6
+        depends on PCI_ENDPOINT
+        select PCIE_DW_EP
+        select PCIE_ARTPEC6
         help
-          Say Y here to enable PCIe controller support on Axis ARTPEC-6
-          SoCs.  This PCIe controller uses the DesignWare core.
+          Enables support for the PCIe controller in the ARTPEC-6 SoC to work in
+          endpoint mode. This uses the DesignWare core.
 
 config PCIE_KIRIN
         depends on OF && ARM64
diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
index 41ba499c96ee..5d2ce72c7a52 100644
--- a/drivers/pci/dwc/Makefile
+++ b/drivers/pci/dwc/Makefile
@@ -3,9 +3,7 @@ obj-$(CONFIG_PCIE_DW) += pcie-designware.o
 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
-ifneq ($(filter y,$(CONFIG_PCI_DRA7XX_HOST) $(CONFIG_PCI_DRA7XX_EP)),)
-        obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
-endif
+obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
 obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
 obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
 obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
@@ -27,4 +25,6 @@ obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
 # ARM64 and use internal ifdefs to only build the pieces we need
 # depending on whether ACPI, the DT driver, or both are enabled.
 
+ifdef CONFIG_PCI
 obj-$(CONFIG_ARM64) += pcie-hisi.o
+endif
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 47855f7c5a6f..ed8558d638e5 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -107,7 +107,7 @@ static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
         writel(value, pcie->base + offset);
 }
 
-static u64 dra7xx_pcie_cpu_addr_fixup(u64 pci_addr)
+static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
 {
         return pci_addr & DRA7XX_CPU_TO_BUS_ADDR;
 }
@@ -223,6 +223,7 @@ static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
 
 static const struct irq_domain_ops intx_domain_ops = {
         .map = dra7xx_pcie_intx_map,
+        .xlate = pci_irqd_intx_xlate,
 };
 
 static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
@@ -253,7 +254,8 @@ static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
         struct dra7xx_pcie *dra7xx = arg;
         struct dw_pcie *pci = dra7xx->pci;
         struct pcie_port *pp = &pci->pp;
-        u32 reg;
+        unsigned long reg;
+        u32 virq, bit;
 
         reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
 
@@ -265,8 +267,11 @@ static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
         case INTB:
         case INTC:
         case INTD:
-                generic_handle_irq(irq_find_mapping(dra7xx->irq_domain,
-                                                    ffs(reg)));
+                for_each_set_bit(bit, &reg, PCI_NUM_INTX) {
+                        virq = irq_find_mapping(dra7xx->irq_domain, bit);
+                        if (virq)
+                                generic_handle_irq(virq);
+                }
                 break;
         }
 
@@ -334,15 +339,6 @@ static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
         return IRQ_HANDLED;
 }
 
-static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
-{
-        u32 reg;
-
-        reg = PCI_BASE_ADDRESS_0 + (4 * bar);
-        dw_pcie_writel_dbi2(pci, reg, 0x0);
-        dw_pcie_writel_dbi(pci, reg, 0x0);
-}
-
 static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
 {
         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -372,7 +368,7 @@ static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
         dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg);
 }
 
-static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep,
+static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
                                  enum pci_epc_irq_type type, u8 interrupt_num)
 {
         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -467,6 +463,8 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
         if (!pci->dbi_base)
                 return -ENOMEM;
 
+        pp->ops = &dra7xx_pcie_host_ops;
+
         ret = dw_pcie_host_init(pp);
         if (ret) {
                 dev_err(dev, "failed to initialize host\n");
@@ -596,7 +594,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
         void __iomem *base;
         struct resource *res;
         struct dw_pcie *pci;
-        struct pcie_port *pp;
         struct dra7xx_pcie *dra7xx;
         struct device *dev = &pdev->dev;
         struct device_node *np = dev->of_node;
@@ -624,9 +621,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
         pci->dev = dev;
         pci->ops = &dw_pcie_ops;
 
-        pp = &pci->pp;
-        pp->ops = &dra7xx_pcie_host_ops;
-
         irq = platform_get_irq(pdev, 0);
         if (irq < 0) {
                 dev_err(dev, "missing IRQ resource: %d\n", irq);
@@ -702,6 +696,11 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 
         switch (mode) {
         case DW_PCIE_RC_TYPE:
+                if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {
+                        ret = -ENODEV;
+                        goto err_gpio;
+                }
+
                 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
                                    DEVICE_TYPE_RC);
                 ret = dra7xx_add_pcie_port(dra7xx, pdev);
@@ -709,6 +708,11 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
                         goto err_gpio;
                 break;
         case DW_PCIE_EP_TYPE:
+                if (!IS_ENABLED(CONFIG_PCI_DRA7XX_EP)) {
+                        ret = -ENODEV;
+                        goto err_gpio;
+                }
+
                 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
                                    DEVICE_TYPE_EP);
 
@@ -807,7 +811,7 @@ static int dra7xx_pcie_resume_noirq(struct device *dev)
 }
 #endif
 
-void dra7xx_pcie_shutdown(struct platform_device *pdev)
+static void dra7xx_pcie_shutdown(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
         struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
index 328cc9f53865..ca6278113936 100644
--- a/drivers/pci/dwc/pci-exynos.c
+++ b/drivers/pci/dwc/pci-exynos.c
@@ -52,49 +52,8 @@
 #define PCIE_ELBI_SLV_ARMISC            0x120
 #define PCIE_ELBI_SLV_DBI_ENABLE        BIT(21)
 
-/* PCIe Purple registers */
-#define PCIE_PHY_GLOBAL_RESET           0x000
-#define PCIE_PHY_COMMON_RESET           0x004
-#define PCIE_PHY_CMN_REG                0x008
-#define PCIE_PHY_MAC_RESET              0x00c
-#define PCIE_PHY_PLL_LOCKED             0x010
-#define PCIE_PHY_TRSVREG_RESET          0x020
-#define PCIE_PHY_TRSV_RESET             0x024
-
-/* PCIe PHY registers */
-#define PCIE_PHY_IMPEDANCE              0x004
-#define PCIE_PHY_PLL_DIV_0              0x008
-#define PCIE_PHY_PLL_BIAS               0x00c
-#define PCIE_PHY_DCC_FEEDBACK           0x014
-#define PCIE_PHY_PLL_DIV_1              0x05c
-#define PCIE_PHY_COMMON_POWER           0x064
-#define PCIE_PHY_COMMON_PD_CMN          BIT(3)
-#define PCIE_PHY_TRSV0_EMP_LVL          0x084
-#define PCIE_PHY_TRSV0_DRV_LVL          0x088
-#define PCIE_PHY_TRSV0_RXCDR            0x0ac
-#define PCIE_PHY_TRSV0_POWER            0x0c4
-#define PCIE_PHY_TRSV0_PD_TSV           BIT(7)
-#define PCIE_PHY_TRSV0_LVCC             0x0dc
-#define PCIE_PHY_TRSV1_EMP_LVL          0x144
-#define PCIE_PHY_TRSV1_RXCDR            0x16c
-#define PCIE_PHY_TRSV1_POWER            0x184
-#define PCIE_PHY_TRSV1_PD_TSV           BIT(7)
-#define PCIE_PHY_TRSV1_LVCC             0x19c
-#define PCIE_PHY_TRSV2_EMP_LVL          0x204
-#define PCIE_PHY_TRSV2_RXCDR            0x22c
-#define PCIE_PHY_TRSV2_POWER            0x244
-#define PCIE_PHY_TRSV2_PD_TSV           BIT(7)
-#define PCIE_PHY_TRSV2_LVCC             0x25c
-#define PCIE_PHY_TRSV3_EMP_LVL          0x2c4
-#define PCIE_PHY_TRSV3_RXCDR            0x2ec
-#define PCIE_PHY_TRSV3_POWER            0x304
-#define PCIE_PHY_TRSV3_PD_TSV           BIT(7)
-#define PCIE_PHY_TRSV3_LVCC             0x31c
-
 struct exynos_pcie_mem_res {
         void __iomem *elbi_base;   /* DT 0th resource: PCIe CTRL */
-        void __iomem *phy_base;    /* DT 1st resource: PHY CTRL */
-        void __iomem *block_base;  /* DT 2nd resource: PHY ADDITIONAL CTRL */
 };
 
 struct exynos_pcie_clk_res {
@@ -109,8 +68,6 @@ struct exynos_pcie {
         const struct exynos_pcie_ops    *ops;
         int                             reset_gpio;
 
-        /* For Generic PHY Framework */
-        bool                            using_phy;
         struct phy                      *phy;
 };
 
@@ -138,20 +95,6 @@ static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
         if (IS_ERR(ep->mem_res->elbi_base))
                 return PTR_ERR(ep->mem_res->elbi_base);
 
-        /* If using the PHY framework, doesn't need to get other resource */
-        if (ep->using_phy)
-                return 0;
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-        ep->mem_res->phy_base = devm_ioremap_resource(dev, res);
-        if (IS_ERR(ep->mem_res->phy_base))
-                return PTR_ERR(ep->mem_res->phy_base);
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
-        ep->mem_res->block_base = devm_ioremap_resource(dev, res);
-        if (IS_ERR(ep->mem_res->block_base))
-                return PTR_ERR(ep->mem_res->block_base);
-
         return 0;
 }
 
@@ -276,111 +219,6 @@ static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep)
         exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_NONSTICKY_RESET);
         exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_APP_INIT_RESET);
         exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_APP_INIT_RESET);
-        exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_MAC_RESET);
-}
-
-static void exynos_pcie_assert_phy_reset(struct exynos_pcie *ep)
-{
-        exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_MAC_RESET);
-        exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_GLOBAL_RESET);
-}
-
-static void exynos_pcie_deassert_phy_reset(struct exynos_pcie *ep)
-{
-        exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_GLOBAL_RESET);
-        exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_PWR_RESET);
-        exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_COMMON_RESET);
-        exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_CMN_REG);
-        exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_TRSVREG_RESET);
-        exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_TRSV_RESET);
-}
-
-static void exynos_pcie_power_on_phy(struct exynos_pcie *ep)
-{
-        u32 val;
-
-        val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_COMMON_POWER);
-        val &= ~PCIE_PHY_COMMON_PD_CMN;
-        exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_COMMON_POWER);
-
-        val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV0_POWER);
-        val &= ~PCIE_PHY_TRSV0_PD_TSV;
-        exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV0_POWER);
-
-        val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV1_POWER);
-        val &= ~PCIE_PHY_TRSV1_PD_TSV;
-        exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV1_POWER);
-
-        val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV2_POWER);
-        val &= ~PCIE_PHY_TRSV2_PD_TSV;
-        exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV2_POWER);
-
-        val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV3_POWER);
-        val &= ~PCIE_PHY_TRSV3_PD_TSV;
-        exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV3_POWER);
-}
-
-static void exynos_pcie_power_off_phy(struct exynos_pcie *ep)
-{
-        u32 val;
-
-        val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_COMMON_POWER);
-        val |= PCIE_PHY_COMMON_PD_CMN;
-        exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_COMMON_POWER);
-
-        val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV0_POWER);
-        val |= PCIE_PHY_TRSV0_PD_TSV;
-        exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV0_POWER);
-
-        val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV1_POWER);
-        val |= PCIE_PHY_TRSV1_PD_TSV;
-        exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV1_POWER);
-
-        val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV2_POWER);
-        val |= PCIE_PHY_TRSV2_PD_TSV;
-        exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV2_POWER);
-
-        val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV3_POWER);
-        val |= PCIE_PHY_TRSV3_PD_TSV;
-        exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV3_POWER);
-}
-
-static void exynos_pcie_init_phy(struct exynos_pcie *ep)
-{
-        /* DCC feedback control off */
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
-
-        /* set TX/RX impedance */
-        exynos_pcie_writel(ep->mem_res->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
-
-        /* set 50Mhz PHY clock */
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
-
-        /* set TX Differential output for lane 0 */
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
-
-        /* set TX Pre-emphasis Level Control for lane 0 to minimum */
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
-
-        /* set RX clock and data recovery bandwidth */
-        exynos_pcie_writel(ep->mem_res->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
-
-        /* change TX Pre-emphasis Level Control for lanes */
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
-
-        /* set LVCC */
-        exynos_pcie_writel(ep->mem_res->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
-        exynos_pcie_writel(ep->mem_res->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
 }
 
 static void exynos_pcie_assert_reset(struct exynos_pcie *ep)
@@ -398,7 +236,6 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep)
         struct dw_pcie *pci = ep->pci;
         struct pcie_port *pp = &pci->pp;
         struct device *dev = pci->dev;
-        u32 val;
 
         if (dw_pcie_link_up(pci)) {
                 dev_err(dev, "Link already up\n");
@@ -407,32 +244,13 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep)
 
         exynos_pcie_assert_core_reset(ep);
 
-        if (ep->using_phy) {
-                phy_reset(ep->phy);
-
-                exynos_pcie_writel(ep->mem_res->elbi_base, 1,
-                                PCIE_PWR_RESET);
-
-                phy_power_on(ep->phy);
-                phy_init(ep->phy);
-        } else {
-                exynos_pcie_assert_phy_reset(ep);
-                exynos_pcie_deassert_phy_reset(ep);
-                exynos_pcie_power_on_phy(ep);
-                exynos_pcie_init_phy(ep);
-
-                /* pulse for common reset */
-                exynos_pcie_writel(ep->mem_res->block_base, 1,
-                                        PCIE_PHY_COMMON_RESET);
-                udelay(500);
-                exynos_pcie_writel(ep->mem_res->block_base, 0,
-                                        PCIE_PHY_COMMON_RESET);
-        }
+        phy_reset(ep->phy);
 
-        /* pulse for common reset */
-        exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_COMMON_RESET);
-        udelay(500);
-        exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_COMMON_RESET);
+        exynos_pcie_writel(ep->mem_res->elbi_base, 1,
+                        PCIE_PWR_RESET);
+
+        phy_power_on(ep->phy);
+        phy_init(ep->phy);
 
         exynos_pcie_deassert_core_reset(ep);
         dw_pcie_setup_rc(pp);
@@ -446,18 +264,7 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep)
         if (!dw_pcie_wait_for_link(pci))
                 return 0;
 
-        if (ep->using_phy) {
-                phy_power_off(ep->phy);
-                return -ETIMEDOUT;
-        }
-
-        while (exynos_pcie_readl(ep->mem_res->phy_base,
-                                PCIE_PHY_PLL_LOCKED) == 0) {
-                val = exynos_pcie_readl(ep->mem_res->block_base,
-                                PCIE_PHY_PLL_LOCKED);
-                dev_info(dev, "PLL Locked: 0x%x\n", val);
-        }
-        exynos_pcie_power_off_phy(ep);
+        phy_power_off(ep->phy);
         return -ETIMEDOUT;
 }
 
@@ -675,16 +482,13 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
 
         ep->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
 
-        /* Assume that controller doesn't use the PHY framework */
-        ep->using_phy = false;
-
         ep->phy = devm_of_phy_get(dev, np, NULL);
         if (IS_ERR(ep->phy)) {
                 if (PTR_ERR(ep->phy) == -EPROBE_DEFER)
                         return PTR_ERR(ep->phy);
-                dev_warn(dev, "Use the 'phy' property. Current DT of pci-exynos was deprecated!!\n");
-        } else
-                ep->using_phy = true;
+
+                ep->phy = NULL;
+        }
 
         if (ep->ops && ep->ops->get_mem_resources) {
                 ret = ep->ops->get_mem_resources(pdev, ep);
@@ -692,7 +496,8 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
                         return ret;
         }
 
-        if (ep->ops && ep->ops->get_clk_resources) {
+        if (ep->ops && ep->ops->get_clk_resources &&
+                        ep->ops->init_clk_resources) {
                 ret = ep->ops->get_clk_resources(ep);
                 if (ret)
                         return ret;
@@ -710,8 +515,7 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
         return 0;
 
 fail_probe:
-        if (ep->using_phy)
-                phy_exit(ep->phy);
+        phy_exit(ep->phy);
 
         if (ep->ops && ep->ops->deinit_clk_resources)
                 ep->ops->deinit_clk_resources(ep);
diff --git a/drivers/pci/dwc/pci-keystone.c b/drivers/pci/dwc/pci-keystone.c
index 8d8d49e44c50..d4f8ab90c018 100644
--- a/drivers/pci/dwc/pci-keystone.c
+++ b/drivers/pci/dwc/pci-keystone.c
@@ -175,7 +175,7 @@ static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
         }
 
         /* interrupt controller is in a child node */
-        *np_temp = of_find_node_by_name(np_pcie, controller);
+        *np_temp = of_get_child_by_name(np_pcie, controller);
         if (!(*np_temp)) {
                 dev_err(dev, "Node for %s is absent\n", controller);
                 return -EINVAL;
@@ -184,6 +184,7 @@ static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
         temp = of_irq_count(*np_temp);
         if (!temp) {
                 dev_err(dev, "No IRQ entries in %s\n", controller);
+                of_node_put(*np_temp);
                 return -EINVAL;
         }
 
@@ -201,6 +202,8 @@ static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
                         break;
         }
 
+        of_node_put(*np_temp);
+
         if (temp) {
                 *num_irqs = temp;
                 return 0;
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index b89884919423..93b3df9ed1b5 100644
--- a/drivers/pci/dwc/pcie-artpec6.c
+++ b/drivers/pci/dwc/pcie-artpec6.c
@@ -10,6 +10,7 @@
 #include <linux/delay.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/of_device.h>
 #include <linux/pci.h>
 #include <linux/platform_device.h>
 #include <linux/resource.h>
@@ -23,44 +24,72 @@
 
 #define to_artpec6_pcie(x)      dev_get_drvdata((x)->dev)
 
+enum artpec_pcie_variants {
+        ARTPEC6,
+        ARTPEC7,
+};
+
 struct artpec6_pcie {
         struct dw_pcie          *pci;
         struct regmap           *regmap;        /* DT axis,syscon-pcie */
         void __iomem            *phy_base;      /* DT phy */
+        enum artpec_pcie_variants variant;
+        enum dw_pcie_device_mode mode;
+};
+
+struct artpec_pcie_of_data {
+        enum artpec_pcie_variants variant;
+        enum dw_pcie_device_mode mode;
 };
 
+static const struct of_device_id artpec6_pcie_of_match[];
+
 /* PCIe Port Logic registers (memory-mapped) */
 #define PL_OFFSET                       0x700
-#define PCIE_PHY_DEBUG_R0               (PL_OFFSET + 0x28)
-#define PCIE_PHY_DEBUG_R1               (PL_OFFSET + 0x2c)
 
-#define MISC_CONTROL_1_OFF              (PL_OFFSET + 0x1bc)
-#define  DBI_RO_WR_EN                   1
+#define ACK_F_ASPM_CTRL_OFF             (PL_OFFSET + 0xc)
+#define ACK_N_FTS_MASK                  GENMASK(15, 8)
+#define ACK_N_FTS(x)                    (((x) << 8) & ACK_N_FTS_MASK)
+
+#define FAST_TRAINING_SEQ_MASK          GENMASK(7, 0)
+#define FAST_TRAINING_SEQ(x)            (((x) << 0) & FAST_TRAINING_SEQ_MASK)
 
 /* ARTPEC-6 specific registers */
 #define PCIECFG                         0x18
-#define  PCIECFG_DBG_OEN                (1 << 24)
-#define  PCIECFG_CORE_RESET_REQ         (1 << 21)
-#define  PCIECFG_LTSSM_ENABLE           (1 << 20)
-#define  PCIECFG_CLKREQ_B               (1 << 11)
-#define  PCIECFG_REFCLK_ENABLE          (1 << 10)
-#define  PCIECFG_PLL_ENABLE             (1 << 9)
-#define  PCIECFG_PCLK_ENABLE            (1 << 8)
-#define  PCIECFG_RISRCREN               (1 << 4)
-#define  PCIECFG_MODE_TX_DRV_EN         (1 << 3)
-#define  PCIECFG_CISRREN                (1 << 2)
-#define  PCIECFG_MACRO_ENABLE           (1 << 0)
+#define  PCIECFG_DBG_OEN                BIT(24)
+#define  PCIECFG_CORE_RESET_REQ         BIT(21)
+#define  PCIECFG_LTSSM_ENABLE           BIT(20)
+#define  PCIECFG_DEVICE_TYPE_MASK       GENMASK(19, 16)
+#define  PCIECFG_CLKREQ_B               BIT(11)
+#define  PCIECFG_REFCLK_ENABLE          BIT(10)
+#define  PCIECFG_PLL_ENABLE             BIT(9)
+#define  PCIECFG_PCLK_ENABLE            BIT(8)
+#define  PCIECFG_RISRCREN               BIT(4)
+#define  PCIECFG_MODE_TX_DRV_EN         BIT(3)
+#define  PCIECFG_CISRREN                BIT(2)
+#define  PCIECFG_MACRO_ENABLE           BIT(0)
+/* ARTPEC-7 specific fields */
+#define  PCIECFG_REFCLKSEL              BIT(23)
+#define  PCIECFG_NOC_RESET              BIT(3)
+
+#define PCIESTAT                        0x1c
+/* ARTPEC-7 specific fields */
+#define  PCIESTAT_EXTREFCLK             BIT(3)
 
 #define NOCCFG                          0x40
-#define NOCCFG_ENABLE_CLK_PCIE          (1 << 4)
-#define NOCCFG_POWER_PCIE_IDLEACK       (1 << 3)
-#define NOCCFG_POWER_PCIE_IDLE          (1 << 2)
-#define NOCCFG_POWER_PCIE_IDLEREQ       (1 << 1)
+#define  NOCCFG_ENABLE_CLK_PCIE         BIT(4)
+#define  NOCCFG_POWER_PCIE_IDLEACK      BIT(3)
+#define  NOCCFG_POWER_PCIE_IDLE         BIT(2)
+#define  NOCCFG_POWER_PCIE_IDLEREQ      BIT(1)
 
 #define PHY_STATUS                      0x118
-#define PHY_COSPLLLOCK                  (1 << 0)
+#define  PHY_COSPLLLOCK                 BIT(0)
 
-#define ARTPEC6_CPU_TO_BUS_ADDR         0x0fffffff
+#define PHY_TX_ASIC_OUT                 0x4040
+#define  PHY_TX_ASIC_OUT_TX_ACK         BIT(0)
+
+#define PHY_RX_ASIC_OUT                 0x405c
+#define  PHY_RX_ASIC_OUT_ACK            BIT(0)
 
 static u32 artpec6_pcie_readl(struct artpec6_pcie *artpec6_pcie, u32 offset)
 {
@@ -75,22 +104,123 @@ static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u
         regmap_write(artpec6_pcie->regmap, offset, val);
 }
 
-static u64 artpec6_pcie_cpu_addr_fixup(u64 pci_addr)
+static u64 artpec6_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
 {
-        return pci_addr & ARTPEC6_CPU_TO_BUS_ADDR;
+        struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
+        struct pcie_port *pp = &pci->pp;
+        struct dw_pcie_ep *ep = &pci->ep;
+
+        switch (artpec6_pcie->mode) {
+        case DW_PCIE_RC_TYPE:
+                return pci_addr - pp->cfg0_base;
+        case DW_PCIE_EP_TYPE:
+                return pci_addr - ep->phys_base;
+        default:
+                dev_err(pci->dev, "UNKNOWN device type\n");
+        }
+        return pci_addr;
 }
 
-static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
+static int artpec6_pcie_establish_link(struct dw_pcie *pci)
 {
-        struct dw_pcie *pci = artpec6_pcie->pci;
-        struct pcie_port *pp = &pci->pp;
+        struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
+        u32 val;
+
+        val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
+        val |= PCIECFG_LTSSM_ENABLE;
+        artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
+
+        return 0;
+}
+
+static void artpec6_pcie_stop_link(struct dw_pcie *pci)
+{
+        struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
         u32 val;
-        unsigned int retries;
 
-        /* Hold DW core in reset */
         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
-        val |= PCIECFG_CORE_RESET_REQ;
+        val &= ~PCIECFG_LTSSM_ENABLE;
         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
+}
+
+static const struct dw_pcie_ops dw_pcie_ops = {
+        .cpu_addr_fixup = artpec6_pcie_cpu_addr_fixup,
+        .start_link = artpec6_pcie_establish_link,
+        .stop_link = artpec6_pcie_stop_link,
+};
+
+static void artpec6_pcie_wait_for_phy_a6(struct artpec6_pcie *artpec6_pcie)
+{
+        struct dw_pcie *pci = artpec6_pcie->pci;
+        struct device *dev = pci->dev;
+        u32 val;
+        unsigned int retries;
+
+        retries = 50;
+        do {
+                usleep_range(1000, 2000);
+                val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
+                retries--;
+        } while (retries &&
+                (val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
+        if (!retries)
+                dev_err(dev, "PCIe clock manager did not leave idle state\n");
+
+        retries = 50;
+        do {
+                usleep_range(1000, 2000);
+                val = readl(artpec6_pcie->phy_base + PHY_STATUS);
+                retries--;
+        } while (retries && !(val & PHY_COSPLLLOCK));
+        if (!retries)
+                dev_err(dev, "PHY PLL did not lock\n");
+}
+
+static void artpec6_pcie_wait_for_phy_a7(struct artpec6_pcie *artpec6_pcie)
+{
+        struct dw_pcie *pci = artpec6_pcie->pci;
+        struct device *dev = pci->dev;
+        u32 val;
+        u16 phy_status_tx, phy_status_rx;
+        unsigned int retries;
+
+        retries = 50;
+        do {
+                usleep_range(1000, 2000);
+                val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
+                retries--;
+        } while (retries &&
+                (val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
+        if (!retries)
+                dev_err(dev, "PCIe clock manager did not leave idle state\n");
+
+        retries = 50;
+        do {
+                usleep_range(1000, 2000);
+                phy_status_tx = readw(artpec6_pcie->phy_base + PHY_TX_ASIC_OUT);
+                phy_status_rx = readw(artpec6_pcie->phy_base + PHY_RX_ASIC_OUT);
+                retries--;
+        } while (retries && ((phy_status_tx & PHY_TX_ASIC_OUT_TX_ACK) ||
+                                (phy_status_rx & PHY_RX_ASIC_OUT_ACK)));
+        if (!retries)
+                dev_err(dev, "PHY did not enter Pn state\n");
+}
+
+static void artpec6_pcie_wait_for_phy(struct artpec6_pcie *artpec6_pcie)
+{
+        switch (artpec6_pcie->variant) {
+        case ARTPEC6:
+                artpec6_pcie_wait_for_phy_a6(artpec6_pcie);
+                break;
+        case ARTPEC7:
+                artpec6_pcie_wait_for_phy_a7(artpec6_pcie);
+                break;
+        }
+}
+
+static void artpec6_pcie_init_phy_a6(struct artpec6_pcie *artpec6_pcie)
+{
+        u32 val;
 
         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
         val |=  PCIECFG_RISRCREN |      /* Receiver term. 50 Ohm */
@@ -116,45 +246,110 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
         val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
         val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
         artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
+}
 
-        retries = 50;
-        do {
-                usleep_range(1000, 2000);
-                val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
-                retries--;
-        } while (retries &&
-                (val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
+static void artpec6_pcie_init_phy_a7(struct artpec6_pcie *artpec6_pcie)
+{
+        struct dw_pcie *pci = artpec6_pcie->pci;
+        u32 val;
+        bool extrefclk;
 
-        retries = 50;
-        do {
-                usleep_range(1000, 2000);
-                val = readl(artpec6_pcie->phy_base + PHY_STATUS);
-                retries--;
-        } while (retries && !(val & PHY_COSPLLLOCK));
+        /* Check if external reference clock is connected */
+        val = artpec6_pcie_readl(artpec6_pcie, PCIESTAT);
+        extrefclk = !!(val & PCIESTAT_EXTREFCLK);
+        dev_dbg(pci->dev, "Using reference clock: %s\n",
+                extrefclk ? "external" : "internal");
 
-        /* Take DW core out of reset */
         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
-        val &= ~PCIECFG_CORE_RESET_REQ;
+        val |=  PCIECFG_RISRCREN |      /* Receiver term. 50 Ohm */
+                PCIECFG_PCLK_ENABLE;
+        if (extrefclk)
+                val |= PCIECFG_REFCLKSEL;
+        else
+                val &= ~PCIECFG_REFCLKSEL;
         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
-        usleep_range(100, 200);
+        usleep_range(10, 20);
 
-        /* setup root complex */
-        dw_pcie_setup_rc(pp);
+        val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
+        val |= NOCCFG_ENABLE_CLK_PCIE;
+        artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
+        usleep_range(20, 30);
+
+        val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
+        val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
+        artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
+}
+
+static void artpec6_pcie_init_phy(struct artpec6_pcie *artpec6_pcie)
+{
+        switch (artpec6_pcie->variant) {
+        case ARTPEC6:
+                artpec6_pcie_init_phy_a6(artpec6_pcie);
+                break;
+        case ARTPEC7:
+                artpec6_pcie_init_phy_a7(artpec6_pcie);
+                break;
+        }
+}
+
+static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie)
+{
+        struct dw_pcie *pci = artpec6_pcie->pci;
+        u32 val;
+
+        if (artpec6_pcie->variant != ARTPEC7)
+                return;
+
+        /*
+         * Increase the N_FTS (Number of Fast Training Sequences)
+         * to be transmitted when transitioning from L0s to L0.
+         */
+        val = dw_pcie_readl_dbi(pci, ACK_F_ASPM_CTRL_OFF);
+        val &= ~ACK_N_FTS_MASK;
+        val |= ACK_N_FTS(180);
+        dw_pcie_writel_dbi(pci, ACK_F_ASPM_CTRL_OFF, val);
+
+        /*
+         * Set the Number of Fast Training Sequences that the core
+         * advertises as its N_FTS during Gen2 or Gen3 link training.
+         */
+        val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+        val &= ~FAST_TRAINING_SEQ_MASK;
+        val |= FAST_TRAINING_SEQ(180);
+        dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+}
+
+static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie)
+{
+        u32 val;
 
-        /* assert LTSSM enable */
         val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
-        val |= PCIECFG_LTSSM_ENABLE;
+        switch (artpec6_pcie->variant) {
+        case ARTPEC6:
+                val |= PCIECFG_CORE_RESET_REQ;
+                break;
+        case ARTPEC7:
+                val &= ~PCIECFG_NOC_RESET;
+                break;
+        }
         artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
+}
 
-        /* check if the link is up or not */
-        if (!dw_pcie_wait_for_link(pci))
-                return 0;
-
-        dev_dbg(pci->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
-                dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
-                dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
+static void artpec6_pcie_deassert_core_reset(struct artpec6_pcie *artpec6_pcie)
+{
+        u32 val;
 
-        return -ETIMEDOUT;
+        val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
+        switch (artpec6_pcie->variant) {
+        case ARTPEC6:
+                val &= ~PCIECFG_CORE_RESET_REQ;
+                break;
+        case ARTPEC7:
+                val |= PCIECFG_NOC_RESET;
+                break;
+        }
+        artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
+        usleep_range(100, 200);
 }
 
 static void artpec6_pcie_enable_interrupts(struct artpec6_pcie *artpec6_pcie)
@@ -171,7 +366,14 @@ static int artpec6_pcie_host_init(struct pcie_port *pp)
         struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
         struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
 
-        artpec6_pcie_establish_link(artpec6_pcie);
+        artpec6_pcie_assert_core_reset(artpec6_pcie);
+        artpec6_pcie_init_phy(artpec6_pcie);
+        artpec6_pcie_deassert_core_reset(artpec6_pcie);
+        artpec6_pcie_wait_for_phy(artpec6_pcie);
+        artpec6_pcie_set_nfts(artpec6_pcie);
+        dw_pcie_setup_rc(pp);
+        artpec6_pcie_establish_link(pci);
+        dw_pcie_wait_for_link(pci);
         artpec6_pcie_enable_interrupts(artpec6_pcie);
 
         return 0;
@@ -227,10 +429,78 @@ static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
         return 0;
 }
 
-static const struct dw_pcie_ops dw_pcie_ops = {
-        .cpu_addr_fixup = artpec6_pcie_cpu_addr_fixup,
+static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep)
+{
+        struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+        struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
+        enum pci_barno bar;
+
+        artpec6_pcie_assert_core_reset(artpec6_pcie);
+        artpec6_pcie_init_phy(artpec6_pcie);
+        artpec6_pcie_deassert_core_reset(artpec6_pcie);
+        artpec6_pcie_wait_for_phy(artpec6_pcie);
+        artpec6_pcie_set_nfts(artpec6_pcie);
+
+        for (bar = BAR_0; bar <= BAR_5; bar++)
+                dw_pcie_ep_reset_bar(pci, bar);
+}
+
+static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
+                                  enum pci_epc_irq_type type, u8 interrupt_num)
+{
+        struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+
+        switch (type) {
+        case PCI_EPC_IRQ_LEGACY:
+                dev_err(pci->dev, "EP cannot trigger legacy IRQs\n");
+                return -EINVAL;
+        case PCI_EPC_IRQ_MSI:
+                return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
+        default:
+                dev_err(pci->dev, "UNKNOWN IRQ type\n");
+        }
+
+        return 0;
+}
+
+static struct dw_pcie_ep_ops pcie_ep_ops = {
+        .ep_init = artpec6_pcie_ep_init,
+        .raise_irq = artpec6_pcie_raise_irq,
 };
 
+static int artpec6_add_pcie_ep(struct artpec6_pcie *artpec6_pcie,
+                               struct platform_device *pdev)
+{
+        int ret;
+        struct dw_pcie_ep *ep;
+        struct resource *res;
+        struct device *dev = &pdev->dev;
+        struct dw_pcie *pci = artpec6_pcie->pci;
+
+        ep = &pci->ep;
+        ep->ops = &pcie_ep_ops;
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
+        pci->dbi_base2 = devm_ioremap(dev, res->start, resource_size(res));
+        if (!pci->dbi_base2)
+                return -ENOMEM;
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
+        if (!res)
+                return -EINVAL;
+
+        ep->phys_base = res->start;
+        ep->addr_size = resource_size(res);
+
+        ret = dw_pcie_ep_init(ep);
+        if (ret) {
+                dev_err(dev, "failed to initialize endpoint\n");
+                return ret;
+        }
+
+        return 0;
+}
+
 static int artpec6_pcie_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
@@ -239,6 +509,18 @@ static int artpec6_pcie_probe(struct platform_device *pdev)
         struct resource *dbi_base;
         struct resource *phy_base;
         int ret;
+        const struct of_device_id *match;
+        const struct artpec_pcie_of_data *data;
+        enum artpec_pcie_variants variant;
+        enum dw_pcie_device_mode mode;
+
+        match = of_match_device(artpec6_pcie_of_match, dev);
+        if (!match)
+                return -EINVAL;
+
+        data = (struct artpec_pcie_of_data *)match->data;
+        variant = (enum artpec_pcie_variants)data->variant;
+        mode = (enum dw_pcie_device_mode)data->mode;
 
         artpec6_pcie = devm_kzalloc(dev, sizeof(*artpec6_pcie), GFP_KERNEL);
         if (!artpec6_pcie)
@@ -252,6 +534,8 @@ static int artpec6_pcie_probe(struct platform_device *pdev)
         pci->ops = &dw_pcie_ops;
 
         artpec6_pcie->pci = pci;
+        artpec6_pcie->variant = variant;
+        artpec6_pcie->mode = mode;
 
         dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
         pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
@@ -271,15 +555,73 @@ static int artpec6_pcie_probe(struct platform_device *pdev)
 
         platform_set_drvdata(pdev, artpec6_pcie);
 
-        ret = artpec6_add_pcie_port(artpec6_pcie, pdev);
-        if (ret < 0)
-                return ret;
+        switch (artpec6_pcie->mode) {
+        case DW_PCIE_RC_TYPE:
+                if (!IS_ENABLED(CONFIG_PCIE_ARTPEC6_HOST))
+                        return -ENODEV;
+
+                ret = artpec6_add_pcie_port(artpec6_pcie, pdev);
+                if (ret < 0)
+                        return ret;
+                break;
+        case DW_PCIE_EP_TYPE: {
+                u32 val;
+
+                if (!IS_ENABLED(CONFIG_PCIE_ARTPEC6_EP))
+                        return -ENODEV;
+
+                val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
+                val &= ~PCIECFG_DEVICE_TYPE_MASK;
+                artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
+                ret = artpec6_add_pcie_ep(artpec6_pcie, pdev);
+                if (ret < 0)
+                        return ret;
+                break;
+        }
+        default:
+                dev_err(dev, "INVALID device type %d\n", artpec6_pcie->mode);
+        }
 
         return 0;
 }
 
+static const struct artpec_pcie_of_data artpec6_pcie_rc_of_data = {
+        .variant = ARTPEC6,
+        .mode = DW_PCIE_RC_TYPE,
+};
+
+static const struct artpec_pcie_of_data artpec6_pcie_ep_of_data = {
+        .variant = ARTPEC6,
+        .mode = DW_PCIE_EP_TYPE,
+};
+
+static const struct artpec_pcie_of_data artpec7_pcie_rc_of_data = {
+        .variant = ARTPEC7,
+        .mode = DW_PCIE_RC_TYPE,
+};
+
+static const struct artpec_pcie_of_data artpec7_pcie_ep_of_data = {
+        .variant = ARTPEC7,
+        .mode = DW_PCIE_EP_TYPE,
+};
+
 static const struct of_device_id artpec6_pcie_of_match[] = {
-        { .compatible = "axis,artpec6-pcie", },
+        {
+                .compatible = "axis,artpec6-pcie",
+                .data = &artpec6_pcie_rc_of_data,
+        },
+        {
+                .compatible = "axis,artpec6-pcie-ep",
+                .data = &artpec6_pcie_ep_of_data,
+        },
+        {
+                .compatible = "axis,artpec7-pcie",
+                .data = &artpec7_pcie_rc_of_data,
+        },
+        {
+                .compatible = "axis,artpec7-pcie-ep",
+                .data = &artpec7_pcie_ep_of_data,
+        },
         {},
 };
 
diff --git a/drivers/pci/dwc/pcie-designware-ep.c b/drivers/pci/dwc/pcie-designware-ep.c
index 2d71a2262a2a..3a6feeff5f5b 100644
--- a/drivers/pci/dwc/pcie-designware-ep.c
+++ b/drivers/pci/dwc/pcie-designware-ep.c
@@ -19,21 +19,24 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
         pci_epc_linkup(epc);
 }
 
-static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
+void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
 {
         u32 reg;
 
         reg = PCI_BASE_ADDRESS_0 + (4 * bar);
+        dw_pcie_dbi_ro_wr_en(pci);
         dw_pcie_writel_dbi2(pci, reg, 0x0);
         dw_pcie_writel_dbi(pci, reg, 0x0);
+        dw_pcie_dbi_ro_wr_dis(pci);
 }
 
-static int dw_pcie_ep_write_header(struct pci_epc *epc,
+static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
                                    struct pci_epf_header *hdr)
 {
         struct dw_pcie_ep *ep = epc_get_drvdata(epc);
         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 
+        dw_pcie_dbi_ro_wr_en(pci);
         dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, hdr->vendorid);
         dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, hdr->deviceid);
         dw_pcie_writeb_dbi(pci, PCI_REVISION_ID, hdr->revid);
@@ -47,6 +50,7 @@ static int dw_pcie_ep_write_header(struct pci_epc *epc,
         dw_pcie_writew_dbi(pci, PCI_SUBSYSTEM_ID, hdr->subsys_id);
         dw_pcie_writeb_dbi(pci, PCI_INTERRUPT_PIN,
                            hdr->interrupt_pin);
+        dw_pcie_dbi_ro_wr_dis(pci);
 
         return 0;
 }
@@ -59,8 +63,7 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
         u32 free_win;
         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 
-        free_win = find_first_zero_bit(&ep->ib_window_map,
-                                       sizeof(ep->ib_window_map));
+        free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
         if (free_win >= ep->num_ib_windows) {
                 dev_err(pci->dev, "no free inbound window\n");
                 return -EINVAL;
@@ -74,7 +77,7 @@ static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
         }
 
         ep->bar_to_atu[bar] = free_win;
-        set_bit(free_win, &ep->ib_window_map);
+        set_bit(free_win, ep->ib_window_map);
 
         return 0;
 }
@@ -85,8 +88,7 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr,
         u32 free_win;
         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 
-        free_win = find_first_zero_bit(&ep->ob_window_map,
-                                       sizeof(ep->ob_window_map));
+        free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows);
         if (free_win >= ep->num_ob_windows) {
                 dev_err(pci->dev, "no free outbound window\n");
                 return -EINVAL;
@@ -95,13 +97,14 @@ static int dw_pcie_ep_outbound_atu(struct dw_pcie_ep *ep, phys_addr_t phys_addr,
         dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
                                   phys_addr, pci_addr, size);
 
-        set_bit(free_win, &ep->ob_window_map);
+        set_bit(free_win, ep->ob_window_map);
         ep->outbound_addr[free_win] = phys_addr;
 
         return 0;
 }
 
-static void dw_pcie_ep_clear_bar(struct pci_epc *epc, enum pci_barno bar)
+static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
+                                 enum pci_barno bar)
 {
         struct dw_pcie_ep *ep = epc_get_drvdata(epc);
         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -110,10 +113,11 @@ static void dw_pcie_ep_clear_bar(struct pci_epc *epc, enum pci_barno bar)
         dw_pcie_ep_reset_bar(pci, bar);
 
         dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
-        clear_bit(atu_index, &ep->ib_window_map);
+        clear_bit(atu_index, ep->ib_window_map);
 }
 
-static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar,
+static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
+                              enum pci_barno bar,
                               dma_addr_t bar_phys, size_t size, int flags)
 {
         int ret;
@@ -131,8 +135,10 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar,
         if (ret)
                 return ret;
 
+        dw_pcie_dbi_ro_wr_en(pci);
         dw_pcie_writel_dbi2(pci, reg, size - 1);
         dw_pcie_writel_dbi(pci, reg, flags);
+        dw_pcie_dbi_ro_wr_dis(pci);
 
         return 0;
 }
@@ -152,7 +158,8 @@ static int dw_pcie_find_index(struct dw_pcie_ep *ep, phys_addr_t addr,
         return -EINVAL;
 }
 
-static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, phys_addr_t addr)
+static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no,
+                                  phys_addr_t addr)
 {
         int ret;
         u32 atu_index;
@@ -164,10 +171,11 @@ static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, phys_addr_t addr)
                 return;
 
         dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND);
-        clear_bit(atu_index, &ep->ob_window_map);
+        clear_bit(atu_index, ep->ob_window_map);
 }
 
-static int dw_pcie_ep_map_addr(struct pci_epc *epc, phys_addr_t addr,
+static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
+                               phys_addr_t addr,
                                u64 pci_addr, size_t size)
 {
         int ret;
@@ -183,39 +191,37 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, phys_addr_t addr,
         return 0;
 }
 
-static int dw_pcie_ep_get_msi(struct pci_epc *epc)
+static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
 {
         int val;
-        u32 lower_addr;
-        u32 upper_addr;
         struct dw_pcie_ep *ep = epc_get_drvdata(epc);
         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 
-        val = dw_pcie_readb_dbi(pci, MSI_MESSAGE_CONTROL);
-        val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
-
-        lower_addr = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_L32);
-        upper_addr = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_U32);
-
-        if (!(lower_addr || upper_addr))
+        val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
+        if (!(val & MSI_CAP_MSI_EN_MASK))
                 return -EINVAL;
 
+        val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
         return val;
 }
 
-static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int)
+static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 encode_int)
 {
         int val;
         struct dw_pcie_ep *ep = epc_get_drvdata(epc);
         struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 
-        val = (encode_int << MSI_CAP_MMC_SHIFT);
+        val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
+        val &= ~MSI_CAP_MMC_MASK;
+        val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;
+        dw_pcie_dbi_ro_wr_en(pci);
         dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
+        dw_pcie_dbi_ro_wr_dis(pci);
 
         return 0;
 }
 
-static int dw_pcie_ep_raise_irq(struct pci_epc *epc,
+static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
                                 enum pci_epc_irq_type type, u8 interrupt_num)
 {
         struct dw_pcie_ep *ep = epc_get_drvdata(epc);
@@ -223,7 +229,7 @@ static int dw_pcie_ep_raise_irq(struct pci_epc *epc,
         if (!ep->ops->raise_irq)
                 return -EINVAL;
 
-        return ep->ops->raise_irq(ep, type, interrupt_num);
+        return ep->ops->raise_irq(ep, func_no, type, interrupt_num);
 }
 
 static void dw_pcie_ep_stop(struct pci_epc *epc)
@@ -261,10 +267,48 @@ static const struct pci_epc_ops epc_ops = {
         .stop                   = dw_pcie_ep_stop,
 };
 
+int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
+                             u8 interrupt_num)
+{
+        struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+        struct pci_epc *epc = ep->epc;
+        u16 msg_ctrl, msg_data;
+        u32 msg_addr_lower, msg_addr_upper;
+        u64 msg_addr;
+        bool has_upper;
+        int ret;
+
+        /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
+        msg_ctrl = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
+        has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
+        msg_addr_lower = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_L32);
+        if (has_upper) {
+                msg_addr_upper = dw_pcie_readl_dbi(pci, MSI_MESSAGE_ADDR_U32);
+                msg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_64);
+        } else {
+                msg_addr_upper = 0;
+                msg_data = dw_pcie_readw_dbi(pci, MSI_MESSAGE_DATA_32);
+        }
+        msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
+        ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
+                                  epc->mem->page_size);
+        if (ret)
+                return ret;
+
+        writel(msg_data | (interrupt_num - 1), ep->msi_mem);
+
+        dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
+
+        return 0;
+}
+
 void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
 {
         struct pci_epc *epc = ep->epc;
 
+        pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
+                              epc->mem->page_size);
+
         pci_epc_mem_exit(epc);
 }
 
@@ -287,12 +331,32 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
                 dev_err(dev, "unable to read *num-ib-windows* property\n");
                 return ret;
         }
+        if (ep->num_ib_windows > MAX_IATU_IN) {
+                dev_err(dev, "invalid *num-ib-windows*\n");
+                return -EINVAL;
+        }
 
         ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
         if (ret < 0) {
                 dev_err(dev, "unable to read *num-ob-windows* property\n");
                 return ret;
         }
+        if (ep->num_ob_windows > MAX_IATU_OUT) {
+                dev_err(dev, "invalid *num-ob-windows*\n");
+                return -EINVAL;
+        }
+
+        ep->ib_window_map = devm_kzalloc(dev, sizeof(long) *
+                                         BITS_TO_LONGS(ep->num_ib_windows),
+                                         GFP_KERNEL);
+        if (!ep->ib_window_map)
+                return -ENOMEM;
+
+        ep->ob_window_map = devm_kzalloc(dev, sizeof(long) *
+                                         BITS_TO_LONGS(ep->num_ob_windows),
+                                         GFP_KERNEL);
+        if (!ep->ob_window_map)
+                return -ENOMEM;
 
         addr = devm_kzalloc(dev, sizeof(phys_addr_t) * ep->num_ob_windows,
                             GFP_KERNEL);
@@ -320,6 +384,13 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
                 return ret;
         }
 
+        ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
+                                             epc->mem->page_size);
+        if (!ep->msi_mem) {
+                dev_err(dev, "Failed to reserve memory for MSI\n");
+                return -ENOMEM;
+        }
+
         ep->epc = epc;
         epc_set_drvdata(epc, ep);
         dw_pcie_setup(pci);
diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index 0fc1d1db72f8..8de2d5c69b1d 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -80,10 +80,19 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
 
 void dw_pcie_msi_init(struct pcie_port *pp)
 {
+        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+        struct device *dev = pci->dev;
+        struct page *page;
         u64 msi_target;
 
-        pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
-        msi_target = virt_to_phys((void *)pp->msi_data);
+        page = alloc_page(GFP_KERNEL);
+        pp->msi_data = dma_map_page(dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
+        if (dma_mapping_error(dev, pp->msi_data)) {
+                dev_err(dev, "failed to map MSI data\n");
+                __free_page(page);
+                return;
+        }
+        msi_target = (u64)pp->msi_data;
 
         /* program the msi_data */
         dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
@@ -184,7 +193,7 @@ static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos)
         if (pp->ops->get_msi_addr)
                 msi_target = pp->ops->get_msi_addr(pp);
         else
-                msi_target = virt_to_phys((void *)pp->msi_data);
+                msi_target = (u64)pp->msi_data;
 
         msg.address_lo = (u32)(msi_target & 0xffffffff);
         msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff);
diff --git a/drivers/pci/dwc/pcie-designware.c b/drivers/pci/dwc/pcie-designware.c
index a3aaabc203e2..1b7282e5b494 100644
--- a/drivers/pci/dwc/pcie-designware.c
+++ b/drivers/pci/dwc/pcie-designware.c
@@ -146,7 +146,7 @@ void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, int type,
         u32 retries, val;
 
         if (pci->ops->cpu_addr_fixup)
-                cpu_addr = pci->ops->cpu_addr_fixup(cpu_addr);
+                cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
 
         if (pci->iatu_unroll_enabled) {
                 dw_pcie_prog_outbound_atu_unroll(pci, index, type, cpu_addr,
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index 948a461c1ac7..11b13864a406 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -11,6 +11,7 @@
 #ifndef _PCIE_DESIGNWARE_H
 #define _PCIE_DESIGNWARE_H
 
+#include <linux/dma-mapping.h>
 #include <linux/irq.h>
 #include <linux/msi.h>
 #include <linux/pci.h>
@@ -97,10 +98,14 @@
 
 #define MSI_MESSAGE_CONTROL             0x52
 #define MSI_CAP_MMC_SHIFT               1
+#define MSI_CAP_MMC_MASK                (7 << MSI_CAP_MMC_SHIFT)
 #define MSI_CAP_MME_SHIFT               4
+#define MSI_CAP_MSI_EN_MASK             0x1
 #define MSI_CAP_MME_MASK                (7 << MSI_CAP_MME_SHIFT)
 #define MSI_MESSAGE_ADDR_L32            0x54
 #define MSI_MESSAGE_ADDR_U32            0x58
+#define MSI_MESSAGE_DATA_32             0x58
+#define MSI_MESSAGE_DATA_64             0x5C
 
 /*
  * Maximum number of MSI IRQs can be 256 per controller. But keep
@@ -110,6 +115,10 @@
 #define MAX_MSI_IRQS                    32
 #define MAX_MSI_CTRLS                   (MAX_MSI_IRQS / 32)
 
+/* Maximum number of inbound/outbound iATUs */
+#define MAX_IATU_IN                     256
+#define MAX_IATU_OUT                    256
+
 struct pcie_port;
 struct dw_pcie;
 struct dw_pcie_ep;
@@ -165,7 +174,7 @@ struct pcie_port {
         const struct dw_pcie_host_ops *ops;
         int                     msi_irq;
         struct irq_domain       *irq_domain;
-        unsigned long           msi_data;
+        dma_addr_t              msi_data;
         DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
 };
 
@@ -177,8 +186,8 @@ enum dw_pcie_as_type {
 
 struct dw_pcie_ep_ops {
         void    (*ep_init)(struct dw_pcie_ep *ep);
-        int     (*raise_irq)(struct dw_pcie_ep *ep, enum pci_epc_irq_type type,
-                             u8 interrupt_num);
+        int     (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
+                             enum pci_epc_irq_type type, u8 interrupt_num);
 };
 
 struct dw_pcie_ep {
@@ -189,14 +198,16 @@ struct dw_pcie_ep {
         size_t                  page_size;
         u8                      bar_to_atu[6];
         phys_addr_t             *outbound_addr;
-        unsigned long           ib_window_map;
-        unsigned long           ob_window_map;
+        unsigned long           *ib_window_map;
+        unsigned long           *ob_window_map;
         u32                     num_ib_windows;
         u32                     num_ob_windows;
+        void __iomem            *msi_mem;
+        phys_addr_t             msi_mem_phys;
 };
 
 struct dw_pcie_ops {
-        u64     (*cpu_addr_fixup)(u64 cpu_addr);
+        u64     (*cpu_addr_fixup)(struct dw_pcie *pcie, u64 cpu_addr);
         u32     (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
                             size_t size);
         void    (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,
@@ -331,6 +342,9 @@ static inline int dw_pcie_host_init(struct pcie_port *pp)
 void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
 int dw_pcie_ep_init(struct dw_pcie_ep *ep);
 void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
+int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
+                             u8 interrupt_num);
+void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
 #else
 static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
 {
@@ -344,5 +358,15 @@ static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
 {
 }
+
+static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
+                                           u8 interrupt_num)
+{
+        return 0;
+}
+
+static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
+{
+}
 #endif
 #endif /* _PCIE_DESIGNWARE_H */
diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
index b01294e899f9..6310c66e265c 100644
--- a/drivers/pci/dwc/pcie-qcom.c
+++ b/drivers/pci/dwc/pcie-qcom.c
@@ -163,7 +163,7 @@ struct qcom_pcie {
         union qcom_pcie_resources res;
         struct phy *phy;
         struct gpio_desc *reset;
-        struct qcom_pcie_ops *ops;
+        const struct qcom_pcie_ops *ops;
 };
 
 #define to_qcom_pcie(x)         dev_get_drvdata((x)->dev)
@@ -1226,7 +1226,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
 
         pcie->pci = pci;
 
-        pcie->ops = (struct qcom_pcie_ops *)of_device_get_match_data(dev);
+        pcie->ops = of_device_get_match_data(dev);
 
         pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_LOW);
         if (IS_ERR(pcie->reset))
diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index f9105c7f20e9..64d8a17f8094 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -93,7 +93,8 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test)
                 goto err;
         }
 
-        ret = pci_epc_map_addr(epc, src_phys_addr, reg->src_addr, reg->size);
+        ret = pci_epc_map_addr(epc, epf->func_no, src_phys_addr, reg->src_addr,
+                               reg->size);
         if (ret) {
                 dev_err(dev, "failed to map source address\n");
                 reg->status = STATUS_SRC_ADDR_INVALID;
@@ -108,7 +109,8 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test)
                 goto err_src_map_addr;
         }
 
-        ret = pci_epc_map_addr(epc, dst_phys_addr, reg->dst_addr, reg->size);
+        ret = pci_epc_map_addr(epc, epf->func_no, dst_phys_addr, reg->dst_addr,
+                               reg->size);
         if (ret) {
                 dev_err(dev, "failed to map destination address\n");
                 reg->status = STATUS_DST_ADDR_INVALID;
@@ -117,13 +119,13 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test)
 
         memcpy(dst_addr, src_addr, reg->size);
 
-        pci_epc_unmap_addr(epc, dst_phys_addr);
+        pci_epc_unmap_addr(epc, epf->func_no, dst_phys_addr);
 
 err_dst_addr:
         pci_epc_mem_free_addr(epc, dst_phys_addr, dst_addr, reg->size);
 
 err_src_map_addr:
-        pci_epc_unmap_addr(epc, src_phys_addr);
+        pci_epc_unmap_addr(epc, epf->func_no, src_phys_addr);
 
 err_src_addr:
         pci_epc_mem_free_addr(epc, src_phys_addr, src_addr, reg->size);
@@ -153,7 +155,8 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test)
                 goto err;
         }
 
-        ret = pci_epc_map_addr(epc, phys_addr, reg->src_addr, reg->size);
+        ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->src_addr,
+                               reg->size);
         if (ret) {
                 dev_err(dev, "failed to map address\n");
                 reg->status = STATUS_SRC_ADDR_INVALID;
@@ -175,7 +178,7 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test)
         kfree(buf);
 
 err_map_addr:
-        pci_epc_unmap_addr(epc, phys_addr);
+        pci_epc_unmap_addr(epc, epf->func_no, phys_addr);
 
 err_addr:
         pci_epc_mem_free_addr(epc, phys_addr, src_addr, reg->size);
@@ -204,7 +207,8 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test)
                 goto err;
         }
 
-        ret = pci_epc_map_addr(epc, phys_addr, reg->dst_addr, reg->size);
+        ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->dst_addr,
+                               reg->size);
         if (ret) {
                 dev_err(dev, "failed to map address\n");
                 reg->status = STATUS_DST_ADDR_INVALID;
@@ -231,7 +235,7 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test)
         kfree(buf);
 
 err_map_addr:
-        pci_epc_unmap_addr(epc, phys_addr);
+        pci_epc_unmap_addr(epc, epf->func_no, phys_addr);
 
 err_addr:
         pci_epc_mem_free_addr(epc, phys_addr, dst_addr, reg->size);
@@ -249,11 +253,11 @@ static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test, u8 irq)
         struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
 
         reg->status |= STATUS_IRQ_RAISED;
-        msi_count = pci_epc_get_msi(epc);
+        msi_count = pci_epc_get_msi(epc, epf->func_no);
         if (irq > msi_count || msi_count <= 0)
-                pci_epc_raise_irq(epc, PCI_EPC_IRQ_LEGACY, 0);
+                pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_LEGACY, 0);
         else
-                pci_epc_raise_irq(epc, PCI_EPC_IRQ_MSI, irq);
+                pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSI, irq);
 }
 
 static void pci_epf_test_cmd_handler(struct work_struct *work)
@@ -280,7 +284,7 @@ static void pci_epf_test_cmd_handler(struct work_struct *work)
 
         if (command & COMMAND_RAISE_LEGACY_IRQ) {
                 reg->status = STATUS_IRQ_RAISED;
-                pci_epc_raise_irq(epc, PCI_EPC_IRQ_LEGACY, 0);
+                pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_LEGACY, 0);
                 goto reset_handler;
         }
 
@@ -315,11 +319,11 @@ static void pci_epf_test_cmd_handler(struct work_struct *work)
         }
 
         if (command & COMMAND_RAISE_MSI_IRQ) {
-                msi_count = pci_epc_get_msi(epc);
+                msi_count = pci_epc_get_msi(epc, epf->func_no);
                 if (irq > msi_count || msi_count <= 0)
                         goto reset_handler;
                 reg->status = STATUS_IRQ_RAISED;
-                pci_epc_raise_irq(epc, PCI_EPC_IRQ_MSI, irq);
+                pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSI, irq);
                 goto reset_handler;
         }
 
@@ -347,7 +351,7 @@ static void pci_epf_test_unbind(struct pci_epf *epf)
         for (bar = BAR_0; bar <= BAR_5; bar++) {
                 if (epf_test->reg[bar]) {
                         pci_epf_free_space(epf, epf_test->reg[bar], bar);
-                        pci_epc_clear_bar(epc, bar);
+                        pci_epc_clear_bar(epc, epf->func_no, bar);
                 }
         }
 }
@@ -369,7 +373,8 @@ static int pci_epf_test_set_bar(struct pci_epf *epf)
 
         for (bar = BAR_0; bar <= BAR_5; bar++) {
                 epf_bar = &epf->bar[bar];
-                ret = pci_epc_set_bar(epc, bar, epf_bar->phys_addr,
+                ret = pci_epc_set_bar(epc, epf->func_no, bar,
+                                      epf_bar->phys_addr,
                                       epf_bar->size, flags);
                 if (ret) {
                         pci_epf_free_space(epf, epf_test->reg[bar], bar);
@@ -422,7 +427,7 @@ static int pci_epf_test_bind(struct pci_epf *epf)
         if (WARN_ON_ONCE(!epc))
                 return -EINVAL;
 
-        ret = pci_epc_write_header(epc, header);
+        ret = pci_epc_write_header(epc, epf->func_no, header);
         if (ret) {
                 dev_err(dev, "configuration header write failed\n");
                 return ret;
@@ -436,7 +441,7 @@ static int pci_epf_test_bind(struct pci_epf *epf)
         if (ret)
                 return ret;
 
-        ret = pci_epc_set_msi(epc, epf->msi_interrupts);
+        ret = pci_epc_set_msi(epc, epf->func_no, epf->msi_interrupts);
         if (ret)
                 return ret;
 
diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-ep-cfs.c
index 9029608c8b1b..018ea3433cb5 100644
--- a/drivers/pci/endpoint/pci-ep-cfs.c
+++ b/drivers/pci/endpoint/pci-ep-cfs.c
@@ -7,18 +7,22 @@
  */
 
 #include <linux/module.h>
+#include <linux/idr.h>
 #include <linux/slab.h>
 
 #include <linux/pci-epc.h>
 #include <linux/pci-epf.h>
 #include <linux/pci-ep-cfs.h>
 
+static DEFINE_IDR(functions_idr);
+static DEFINE_MUTEX(functions_mutex);
 static struct config_group *functions_group;
 static struct config_group *controllers_group;
 
 struct pci_epf_group {
         struct config_group group;
         struct pci_epf *epf;
+        int index;
 };
 
 struct pci_epc_group {
@@ -86,22 +90,23 @@ static int pci_epc_epf_link(struct config_item *epc_item,
 {
         int ret;
         u32 func_no = 0;
-        struct pci_epc *epc;
-        struct pci_epf *epf;
         struct pci_epf_group *epf_group = to_pci_epf_group(epf_item);
         struct pci_epc_group *epc_group = to_pci_epc_group(epc_item);
-
-        epc = epc_group->epc;
-        epf = epf_group->epf;
-        ret = pci_epc_add_epf(epc, epf);
-        if (ret)
-                goto err_add_epf;
+        struct pci_epc *epc = epc_group->epc;
+        struct pci_epf *epf = epf_group->epf;
 
         func_no = find_first_zero_bit(&epc_group->function_num_map,
-                                      sizeof(epc_group->function_num_map));
+                                      BITS_PER_LONG);
+        if (func_no >= BITS_PER_LONG)
+                return -EINVAL;
+
         set_bit(func_no, &epc_group->function_num_map);
         epf->func_no = func_no;
 
+        ret = pci_epc_add_epf(epc, epf);
+        if (ret)
+                goto err_add_epf;
+
         ret = pci_epf_bind(epf);
         if (ret)
                 goto err_epf_bind;
@@ -342,6 +347,9 @@ static void pci_epf_release(struct config_item *item)
 {
         struct pci_epf_group *epf_group = to_pci_epf_group(item);
 
+        mutex_lock(&functions_mutex);
+        idr_remove(&functions_idr, epf_group->index);
+        mutex_unlock(&functions_mutex);
         pci_epf_destroy(epf_group->epf);
         kfree(epf_group);
 }
@@ -361,22 +369,57 @@ static struct config_group *pci_epf_make(struct config_group *group,
 {
         struct pci_epf_group *epf_group;
         struct pci_epf *epf;
+        char *epf_name;
+        int index, err;
 
         epf_group = kzalloc(sizeof(*epf_group), GFP_KERNEL);
         if (!epf_group)
                 return ERR_PTR(-ENOMEM);
 
+        mutex_lock(&functions_mutex);
+        index = idr_alloc(&functions_idr, epf_group, 0, 0, GFP_KERNEL);
+        mutex_unlock(&functions_mutex);
+        if (index < 0) {
+                err = index;
+                goto free_group;
+        }
+
+        epf_group->index = index;
+
         config_group_init_type_name(&epf_group->group, name, &pci_epf_type);
 
-        epf = pci_epf_create(group->cg_item.ci_name);
+        epf_name = kasprintf(GFP_KERNEL, "%s.%d",
+                             group->cg_item.ci_name, epf_group->index);
+        if (!epf_name) {
+                err = -ENOMEM;
+                goto remove_idr;
+        }
+
+        epf = pci_epf_create(epf_name);
         if (IS_ERR(epf)) {
                 pr_err("failed to create endpoint function device\n");
-                return ERR_PTR(-EINVAL);
+                err = -EINVAL;
+                goto free_name;
         }
 
         epf_group->epf = epf;
 
+        kfree(epf_name);
+
         return &epf_group->group;
+
+free_name:
+        kfree(epf_name);
+
+remove_idr:
+        mutex_lock(&functions_mutex);
+        idr_remove(&functions_idr, epf_group->index);
+        mutex_unlock(&functions_mutex);
+
+free_group:
+        kfree(epf_group);
+
+        return ERR_PTR(err);
 }
 
 static void pci_epf_drop(struct config_group *group, struct config_item *item)
diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index 71b72c63fddb..e245bba0ab53 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -7,7 +7,6 @@
  */
 
 #include <linux/device.h>
-#include <linux/dma-mapping.h>
 #include <linux/slab.h>
 #include <linux/module.h>
 #include <linux/of_device.h>
@@ -131,25 +130,26 @@ EXPORT_SYMBOL_GPL(pci_epc_start);
 /**
  * pci_epc_raise_irq() - interrupt the host system
  * @epc: the EPC device which has to interrupt the host
+ * @func_no: the endpoint function number in the EPC device
  * @type: specify the type of interrupt; legacy or MSI
  * @interrupt_num: the MSI interrupt number
  *
  * Invoke to raise an MSI or legacy interrupt
  */
-int pci_epc_raise_irq(struct pci_epc *epc, enum pci_epc_irq_type type,
-                      u8 interrupt_num)
+int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
+                      enum pci_epc_irq_type type, u8 interrupt_num)
 {
         int ret;
         unsigned long flags;
 
-        if (IS_ERR(epc))
+        if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
                 return -EINVAL;
 
         if (!epc->ops->raise_irq)
                 return 0;
 
         spin_lock_irqsave(&epc->lock, flags);
-        ret = epc->ops->raise_irq(epc, type, interrupt_num);
+        ret = epc->ops->raise_irq(epc, func_no, type, interrupt_num);
         spin_unlock_irqrestore(&epc->lock, flags);
 
         return ret;
@@ -159,22 +159,23 @@ EXPORT_SYMBOL_GPL(pci_epc_raise_irq);
 /**
  * pci_epc_get_msi() - get the number of MSI interrupt numbers allocated
  * @epc: the EPC device to which MSI interrupts was requested
+ * @func_no: the endpoint function number in the EPC device
  *
  * Invoke to get the number of MSI interrupts allocated by the RC
  */
-int pci_epc_get_msi(struct pci_epc *epc)
+int pci_epc_get_msi(struct pci_epc *epc, u8 func_no)
 {
         int interrupt;
         unsigned long flags;
 
-        if (IS_ERR(epc))
+        if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
                 return 0;
 
         if (!epc->ops->get_msi)
                 return 0;
 
         spin_lock_irqsave(&epc->lock, flags);
-        interrupt = epc->ops->get_msi(epc);
+        interrupt = epc->ops->get_msi(epc, func_no);
         spin_unlock_irqrestore(&epc->lock, flags);
 
         if (interrupt < 0)
@@ -189,17 +190,18 @@ EXPORT_SYMBOL_GPL(pci_epc_get_msi);
 /**
  * pci_epc_set_msi() - set the number of MSI interrupt numbers required
  * @epc: the EPC device on which MSI has to be configured
+ * @func_no: the endpoint function number in the EPC device
  * @interrupts: number of MSI interrupts required by the EPF
  *
  * Invoke to set the required number of MSI interrupts.
  */
-int pci_epc_set_msi(struct pci_epc *epc, u8 interrupts)
+int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
 {
         int ret;
         u8 encode_int;
         unsigned long flags;
 
-        if (IS_ERR(epc))
+        if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
                 return -EINVAL;
 
         if (!epc->ops->set_msi)
@@ -208,7 +210,7 @@ int pci_epc_set_msi(struct pci_epc *epc, u8 interrupts)
         encode_int = order_base_2(interrupts);
 
         spin_lock_irqsave(&epc->lock, flags);
-        ret = epc->ops->set_msi(epc, encode_int);
+        ret = epc->ops->set_msi(epc, func_no, encode_int);
         spin_unlock_irqrestore(&epc->lock, flags);
 
         return ret;
@@ -218,22 +220,24 @@ EXPORT_SYMBOL_GPL(pci_epc_set_msi);
 /**
  * pci_epc_unmap_addr() - unmap CPU address from PCI address
  * @epc: the EPC device on which address is allocated
+ * @func_no: the endpoint function number in the EPC device
  * @phys_addr: physical address of the local system
  *
  * Invoke to unmap the CPU address from PCI address.
  */
-void pci_epc_unmap_addr(struct pci_epc *epc, phys_addr_t phys_addr)
+void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
+                        phys_addr_t phys_addr)
 {
         unsigned long flags;
 
-        if (IS_ERR(epc))
+        if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
                 return;
 
         if (!epc->ops->unmap_addr)
                 return;
 
         spin_lock_irqsave(&epc->lock, flags);
-        epc->ops->unmap_addr(epc, phys_addr);
+        epc->ops->unmap_addr(epc, func_no, phys_addr);
         spin_unlock_irqrestore(&epc->lock, flags);
 }
 EXPORT_SYMBOL_GPL(pci_epc_unmap_addr);
@@ -241,26 +245,27 @@ EXPORT_SYMBOL_GPL(pci_epc_unmap_addr);
 /**
  * pci_epc_map_addr() - map CPU address to PCI address
  * @epc: the EPC device on which address is allocated
+ * @func_no: the endpoint function number in the EPC device
  * @phys_addr: physical address of the local system
  * @pci_addr: PCI address to which the physical address should be mapped
  * @size: the size of the allocation
  *
  * Invoke to map CPU address with PCI address.
  */
-int pci_epc_map_addr(struct pci_epc *epc, phys_addr_t phys_addr,
-                     u64 pci_addr, size_t size)
+int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
+                     phys_addr_t phys_addr, u64 pci_addr, size_t size)
 {
         int ret;
         unsigned long flags;
 
-        if (IS_ERR(epc))
+        if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
                 return -EINVAL;
 
         if (!epc->ops->map_addr)
                 return 0;
 
         spin_lock_irqsave(&epc->lock, flags);
-        ret = epc->ops->map_addr(epc, phys_addr, pci_addr, size);
+        ret = epc->ops->map_addr(epc, func_no, phys_addr, pci_addr, size);
         spin_unlock_irqrestore(&epc->lock, flags);
 
         return ret;
@@ -270,22 +275,23 @@ EXPORT_SYMBOL_GPL(pci_epc_map_addr);
 /**
  * pci_epc_clear_bar() - reset the BAR
  * @epc: the EPC device for which the BAR has to be cleared
+ * @func_no: the endpoint function number in the EPC device
  * @bar: the BAR number that has to be reset
  *
  * Invoke to reset the BAR of the endpoint device.
  */
-void pci_epc_clear_bar(struct pci_epc *epc, int bar)
+void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, int bar)
 {
         unsigned long flags;
 
-        if (IS_ERR(epc))
+        if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
                 return;
 
         if (!epc->ops->clear_bar)
                 return;
 
         spin_lock_irqsave(&epc->lock, flags);
-        epc->ops->clear_bar(epc, bar);
+        epc->ops->clear_bar(epc, func_no, bar);
         spin_unlock_irqrestore(&epc->lock, flags);
 }
 EXPORT_SYMBOL_GPL(pci_epc_clear_bar);
@@ -293,26 +299,27 @@ EXPORT_SYMBOL_GPL(pci_epc_clear_bar);
 /**
  * pci_epc_set_bar() - configure BAR in order for host to assign PCI addr space
  * @epc: the EPC device on which BAR has to be configured
+ * @func_no: the endpoint function number in the EPC device
  * @bar: the BAR number that has to be configured
  * @size: the size of the addr space
  * @flags: specify memory allocation/io allocation/32bit address/64 bit address
  *
  * Invoke to configure the BAR of the endpoint device.
  */
-int pci_epc_set_bar(struct pci_epc *epc, enum pci_barno bar,
+int pci_epc_set_bar(struct pci_epc *epc, u8 func_no, enum pci_barno bar,
                     dma_addr_t bar_phys, size_t size, int flags)
 {
         int ret;
         unsigned long irq_flags;
 
-        if (IS_ERR(epc))
+        if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
                 return -EINVAL;
 
         if (!epc->ops->set_bar)
                 return 0;
 
         spin_lock_irqsave(&epc->lock, irq_flags);
-        ret = epc->ops->set_bar(epc, bar, bar_phys, size, flags);
+        ret = epc->ops->set_bar(epc, func_no, bar, bar_phys, size, flags);
         spin_unlock_irqrestore(&epc->lock, irq_flags);
 
         return ret;
@@ -322,6 +329,7 @@ EXPORT_SYMBOL_GPL(pci_epc_set_bar);
 /**
  * pci_epc_write_header() - write standard configuration header
  * @epc: the EPC device to which the configuration header should be written
+ * @func_no: the endpoint function number in the EPC device
  * @header: standard configuration header fields
  *
  * Invoke to write the configuration header to the endpoint controller. Every
@@ -329,19 +337,20 @@ EXPORT_SYMBOL_GPL(pci_epc_set_bar);
  * configuration header would be written. The callback function should write
  * the header fields to this dedicated location.
  */
-int pci_epc_write_header(struct pci_epc *epc, struct pci_epf_header *header)
+int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
+                         struct pci_epf_header *header)
 {
         int ret;
         unsigned long flags;
 
-        if (IS_ERR(epc))
+        if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
                 return -EINVAL;
 
         if (!epc->ops->write_header)
                 return 0;
 
         spin_lock_irqsave(&epc->lock, flags);
-        ret = epc->ops->write_header(epc, header);
+        ret = epc->ops->write_header(epc, func_no, header);
         spin_unlock_irqrestore(&epc->lock, flags);
 
         return ret;
@@ -360,7 +369,6 @@ EXPORT_SYMBOL_GPL(pci_epc_write_header);
 int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf)
 {
         unsigned long flags;
-        struct device *dev = epc->dev.parent;
 
         if (epf->epc)
                 return -EBUSY;
@@ -372,12 +380,6 @@ int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf)
                 return -EINVAL;
 
         epf->epc = epc;
-        if (dev->of_node) {
-                of_dma_configure(&epf->dev, dev->of_node);
-        } else {
-                dma_set_coherent_mask(&epf->dev, epc->dev.coherent_dma_mask);
-                epf->dev.dma_mask = epc->dev.dma_mask;
-        }
 
         spin_lock_irqsave(&epc->lock, flags);
         list_add_tail(&epf->list, &epc->pci_epf);
@@ -492,9 +494,7 @@ __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
         INIT_LIST_HEAD(&epc->pci_epf);
 
         device_initialize(&epc->dev);
-        dma_set_coherent_mask(&epc->dev, dev->coherent_dma_mask);
         epc->dev.class = pci_epc_class;
-        epc->dev.dma_mask = dev->dma_mask;
         epc->dev.parent = dev;
         epc->ops = ops;
 
diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c
index 9f282ea632d2..766ce1dca2ec 100644
--- a/drivers/pci/endpoint/pci-epf-core.c
+++ b/drivers/pci/endpoint/pci-epf-core.c
@@ -88,7 +88,7 @@ EXPORT_SYMBOL_GPL(pci_epf_bind);
  */
 void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar)
 {
-        struct device *dev = &epf->dev;
+        struct device *dev = epf->epc->dev.parent;
 
         if (!addr)
                 return;
@@ -111,7 +111,7 @@ EXPORT_SYMBOL_GPL(pci_epf_free_space);
 void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar)
 {
         void *space;
-        struct device *dev = &epf->dev;
+        struct device *dev = epf->epc->dev.parent;
         dma_addr_t phys_addr;
 
         if (size < 128)
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 34ec1d88f961..3b1059190867 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -34,6 +34,8 @@ obj-$(CONFIG_VMD) += vmd.o
 # ARM64 and use internal ifdefs to only build the pieces we need
 # depending on whether ACPI, the DT driver, or both are enabled.
 
+ifdef CONFIG_PCI
 obj-$(CONFIG_ARM64) += pci-thunder-ecam.o
 obj-$(CONFIG_ARM64) += pci-thunder-pem.o
 obj-$(CONFIG_ARM64) += pci-xgene.o
+endif
diff --git a/drivers/pci/host/pci-host-common.c b/drivers/pci/host/pci-host-common.c
index 31f2c231e893..5d028f53fdcd 100644
--- a/drivers/pci/host/pci-host-common.c
+++ b/drivers/pci/host/pci-host-common.c
@@ -13,50 +13,6 @@
 #include <linux/pci-ecam.h>
 #include <linux/platform_device.h>
 
-static int gen_pci_parse_request_of_pci_ranges(struct device *dev,
-                       struct list_head *resources, struct resource **bus_range)
-{
-        int err, res_valid = 0;
-        struct device_node *np = dev->of_node;
-        resource_size_t iobase;
-        struct resource_entry *win, *tmp;
-
-        err = of_pci_get_host_bridge_resources(np, 0, 0xff, resources, &iobase);
-        if (err)
-                return err;
-
-        err = devm_request_pci_bus_resources(dev, resources);
-        if (err)
-                return err;
-
-        resource_list_for_each_entry_safe(win, tmp, resources) {
-                struct resource *res = win->res;
-
-                switch (resource_type(res)) {
-                case IORESOURCE_IO:
-                        err = pci_remap_iospace(res, iobase);
-                        if (err) {
-                                dev_warn(dev, "error %d: failed to map resource %pR\n",
-                                         err, res);
-                                resource_list_destroy_entry(win);
-                        }
-                        break;
-                case IORESOURCE_MEM:
-                        res_valid |= !(res->flags & IORESOURCE_PREFETCH);
-                        break;
-                case IORESOURCE_BUS:
-                        *bus_range = res;
-                        break;
-                }
-        }
-
-        if (res_valid)
-                return 0;
-
-        dev_err(dev, "non-prefetchable memory resource required\n");
-        return -EINVAL;
-}
-
 static void gen_pci_unmap_cfg(void *ptr)
 {
         pci_ecam_free((struct pci_config_window *)ptr);
@@ -71,9 +27,9 @@ static struct pci_config_window *gen_pci_init(struct device *dev,
         struct pci_config_window *cfg;
 
         /* Parse our PCI ranges and request their resources */
-        err = gen_pci_parse_request_of_pci_ranges(dev, resources, &bus_range);
+        err = pci_parse_request_of_pci_ranges(dev, resources, &bus_range);
         if (err)
-                goto err_out;
+                return ERR_PTR(err);
 
         err = of_address_to_resource(dev->of_node, 0, &cfgres);
         if (err) {
@@ -105,7 +61,6 @@ int pci_host_common_probe(struct platform_device *pdev,
         const char *type;
         struct device *dev = &pdev->dev;
         struct device_node *np = dev->of_node;
-        struct pci_bus *bus, *child;
         struct pci_host_bridge *bridge;
         struct pci_config_window *cfg;
         struct list_head resources;
@@ -124,14 +79,13 @@ int pci_host_common_probe(struct platform_device *pdev,
         of_pci_check_probe_only();
 
         /* Parse and map our Configuration Space windows */
-        INIT_LIST_HEAD(&resources);
         cfg = gen_pci_init(dev, &resources, ops);
         if (IS_ERR(cfg))
                 return PTR_ERR(cfg);
 
         /* Do not reassign resources if probe only */
         if (!pci_has_flag(PCI_PROBE_ONLY))
-                pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS);
+                pci_add_flags(PCI_REASSIGN_ALL_BUS);
 
         list_splice_init(&resources, &bridge->windows);
         bridge->dev.parent = dev;
@@ -141,29 +95,11 @@ int pci_host_common_probe(struct platform_device *pdev,
         bridge->map_irq = of_irq_parse_and_map_pci;
         bridge->swizzle_irq = pci_common_swizzle;
 
-        ret = pci_scan_root_bus_bridge(bridge);
+        ret = pci_host_probe(bridge);
         if (ret < 0) {
-                dev_err(dev, "Scanning root bridge failed");
+                pci_free_resource_list(&resources);
                 return ret;
         }
 
-        bus = bridge->bus;
-
-        /*
-         * We insert PCI resources into the iomem_resource and
-         * ioport_resource trees in either pci_bus_claim_resources()
-         * or pci_bus_assign_resources().
-         */
-        if (pci_has_flag(PCI_PROBE_ONLY)) {
-                pci_bus_claim_resources(bus);
-        } else {
-                pci_bus_size_bridges(bus);
-                pci_bus_assign_resources(bus);
-
-                list_for_each_entry(child, &bus->children, node)
-                        pcie_bus_configure_settings(child);
-        }
-
-        pci_bus_add_devices(bus);
         return 0;
 }
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
index 8ff28057ec02..dd9b3bcc41c3 100644
--- a/drivers/pci/host/pci-tegra.c
+++ b/drivers/pci/host/pci-tegra.c
@@ -256,11 +256,10 @@ struct tegra_pcie {
 
         void __iomem *pads;
         void __iomem *afi;
+        void __iomem *cfg;
         int irq;
 
-        struct list_head buses;
-        struct resource *cs;
-
+        struct resource cs;
         struct resource io;
         struct resource pio;
         struct resource mem;
@@ -309,7 +308,6 @@ struct tegra_pcie_port {
 };
 
 struct tegra_pcie_bus {
-        struct vm_struct *area;
         struct list_head list;
         unsigned int nr;
 };
@@ -349,109 +347,26 @@ static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
  *
  * Mapping the whole extended configuration space would require 256 MiB of
  * virtual address space, only a small part of which will actually be used.
- * To work around this, a 1 MiB of virtual addresses are allocated per bus
- * when the bus is first accessed. When the physical range is mapped, the
- * the bus number bits are hidden so that the extended register number bits
- * appear as bits [19:16]. Therefore the virtual mapping looks like this:
- *
- *    [19:16] extended register number
- *    [15:11] device number
- *    [10: 8] function number
- *    [ 7: 0] register number
  *
- * This is achieved by stitching together 16 chunks of 64 KiB of physical
- * address space via the MMU.
+ * To work around this, a 4 KiB region is used to generate the required
+ * configuration transaction with relevant B:D:F and register offset values.
+ * This is achieved by dynamically programming base address and size of
+ * AFI_AXI_BAR used for end point config space mapping to make sure that the
+ * address (access to which generates correct config transaction) falls in
+ * this 4 KiB region.
  */
-static unsigned long tegra_pcie_conf_offset(unsigned int devfn, int where)
+static unsigned int tegra_pcie_conf_offset(u8 bus, unsigned int devfn,
+                                           unsigned int where)
 {
-        return ((where & 0xf00) << 8) | (PCI_SLOT(devfn) << 11) |
-               (PCI_FUNC(devfn) << 8) | (where & 0xfc);
-}
-
-static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie,
-                                                   unsigned int busnr)
-{
-        struct device *dev = pcie->dev;
-        pgprot_t prot = pgprot_noncached(PAGE_KERNEL);
-        phys_addr_t cs = pcie->cs->start;
-        struct tegra_pcie_bus *bus;
-        unsigned int i;
-        int err;
-
-        bus = kzalloc(sizeof(*bus), GFP_KERNEL);
-        if (!bus)
-                return ERR_PTR(-ENOMEM);
-
-        INIT_LIST_HEAD(&bus->list);
-        bus->nr = busnr;
-
-        /* allocate 1 MiB of virtual addresses */
-        bus->area = get_vm_area(SZ_1M, VM_IOREMAP);
-        if (!bus->area) {
-                err = -ENOMEM;
-                goto free;
-        }
-
-        /* map each of the 16 chunks of 64 KiB each */
-        for (i = 0; i < 16; i++) {
-                unsigned long virt = (unsigned long)bus->area->addr +
-                                     i * SZ_64K;
-                phys_addr_t phys = cs + i * SZ_16M + busnr * SZ_64K;
-
-                err = ioremap_page_range(virt, virt + SZ_64K, phys, prot);
-                if (err < 0) {
-                        dev_err(dev, "ioremap_page_range() failed: %d\n", err);
-                        goto unmap;
-                }
-        }
-
-        return bus;
-
-unmap:
-        vunmap(bus->area->addr);
-free:
-        kfree(bus);
-        return ERR_PTR(err);
-}
-
-static int tegra_pcie_add_bus(struct pci_bus *bus)
-{
-        struct pci_host_bridge *host = pci_find_host_bridge(bus);
-        struct tegra_pcie *pcie = pci_host_bridge_priv(host);
-        struct tegra_pcie_bus *b;
-
-        b = tegra_pcie_bus_alloc(pcie, bus->number);
-        if (IS_ERR(b))
-                return PTR_ERR(b);
-
-        list_add_tail(&b->list, &pcie->buses);
-
-        return 0;
-}
-
-static void tegra_pcie_remove_bus(struct pci_bus *child)
-{
-        struct pci_host_bridge *host = pci_find_host_bridge(child);
-        struct tegra_pcie *pcie = pci_host_bridge_priv(host);
-        struct tegra_pcie_bus *bus, *tmp;
-
-        list_for_each_entry_safe(bus, tmp, &pcie->buses, list) {
-                if (bus->nr == child->number) {
-                        vunmap(bus->area->addr);
-                        list_del(&bus->list);
-                        kfree(bus);
-                        break;
-                }
-        }
+        return ((where & 0xf00) << 16) | (bus << 16) | (PCI_SLOT(devfn) << 11) |
+               (PCI_FUNC(devfn) << 8) | (where & 0xff);
 }
 
 static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus,
                                         unsigned int devfn,
                                         int where)
 {
-        struct pci_host_bridge *host = pci_find_host_bridge(bus);
-        struct tegra_pcie *pcie = pci_host_bridge_priv(host);
-        struct device *dev = pcie->dev;
+        struct tegra_pcie *pcie = bus->sysdata;
         void __iomem *addr = NULL;
 
         if (bus->number == 0) {
@@ -465,19 +380,17 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus,
                         }
                 }
         } else {
-                struct tegra_pcie_bus *b;
+                unsigned int offset;
+                u32 base;
 
-                list_for_each_entry(b, &pcie->buses, list)
-                        if (b->nr == bus->number)
-                                addr = (void __iomem *)b->area->addr;
+                offset = tegra_pcie_conf_offset(bus->number, devfn, where);
 
-                if (!addr) {
-                        dev_err(dev, "failed to map cfg. space for bus %u\n",
-                                bus->number);
-                        return NULL;
-                }
+                /* move 4 KiB window to offset within the FPCI region */
+                base = 0xfe100000 + ((offset & ~(SZ_4K - 1)) >> 8);
+                afi_writel(pcie, base, AFI_FPCI_BAR0);
 
-                addr += tegra_pcie_conf_offset(devfn, where);
+                /* move to correct offset within the 4 KiB page */
+                addr = pcie->cfg + (offset & (SZ_4K - 1));
         }
 
         return addr;
@@ -504,8 +417,6 @@ static int tegra_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
 }
 
 static struct pci_ops tegra_pcie_ops = {
-        .add_bus = tegra_pcie_add_bus,
-        .remove_bus = tegra_pcie_remove_bus,
         .map_bus = tegra_pcie_map_bus,
         .read = tegra_pcie_config_read,
         .write = tegra_pcie_config_write,
@@ -648,8 +559,7 @@ static int tegra_pcie_request_resources(struct tegra_pcie *pcie)
 
 static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
 {
-        struct pci_host_bridge *host = pci_find_host_bridge(pdev->bus);
-        struct tegra_pcie *pcie = pci_host_bridge_priv(host);
+        struct tegra_pcie *pcie = pdev->bus->sysdata;
         int irq;
 
         tegra_cpuidle_pcie_irqs_in_use();
@@ -730,12 +640,9 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
         u32 fpci_bar, size, axi_address;
 
         /* Bar 0: type 1 extended configuration space */
-        fpci_bar = 0xfe100000;
-        size = resource_size(pcie->cs);
-        axi_address = pcie->cs->start;
-        afi_writel(pcie, axi_address, AFI_AXI_BAR0_START);
+        size = resource_size(&pcie->cs);
+        afi_writel(pcie, pcie->cs.start, AFI_AXI_BAR0_START);
         afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
-        afi_writel(pcie, fpci_bar, AFI_FPCI_BAR0);
 
         /* Bar 1: downstream IO bar */
         fpci_bar = 0xfdfc0000;
@@ -1340,10 +1247,14 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
                 goto poweroff;
         }
 
-        pcie->cs = devm_request_mem_region(dev, res->start,
-                                           resource_size(res), res->name);
-        if (!pcie->cs) {
-                err = -EADDRNOTAVAIL;
+        pcie->cs = *res;
+
+        /* constrain configuration space to 4 KiB */
+        pcie->cs.end = pcie->cs.start + SZ_4K - 1;
+
+        pcie->cfg = devm_ioremap_resource(dev, &pcie->cs);
+        if (IS_ERR(pcie->cfg)) {
+                err = PTR_ERR(pcie->cfg);
                 goto poweroff;
         }
 
@@ -2332,9 +2243,9 @@ static int tegra_pcie_probe(struct platform_device *pdev)
                 return -ENOMEM;
 
         pcie = pci_host_bridge_priv(host);
+        host->sysdata = pcie;
 
         pcie->soc = of_device_get_match_data(dev);
-        INIT_LIST_HEAD(&pcie->buses);
         INIT_LIST_HEAD(&pcie->ports);
         pcie->dev = dev;
 
@@ -2369,7 +2280,6 @@ static int tegra_pcie_probe(struct platform_device *pdev)
 
         tegra_pcie_enable_ports(pcie);
 
-        pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS);
         host->busnr = pcie->busn.start;
         host->dev.parent = &pdev->dev;
         host->ops = &tegra_pcie_ops;
diff --git a/drivers/pci/host/pci-versatile.c b/drivers/pci/host/pci-versatile.c
index b5b59d058c1b..5b3876f5312b 100644
--- a/drivers/pci/host/pci-versatile.c
+++ b/drivers/pci/host/pci-versatile.c
@@ -194,7 +194,7 @@ static int versatile_pci_probe(struct platform_device *pdev)
         writel(0, versatile_cfg_base[0] + PCI_INTERRUPT_LINE);
 
         pci_add_flags(PCI_ENABLE_PROC_DOMAINS);
-        pci_add_flags(PCI_REASSIGN_ALL_BUS | PCI_REASSIGN_ALL_RSRC);
+        pci_add_flags(PCI_REASSIGN_ALL_BUS);
 
         list_splice_init(&pci_res, &bridge->windows);
         bridge->dev.parent = dev;
diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
index 2fc106d52aff..0a0d7ee6d3c9 100644
--- a/drivers/pci/host/pci-xgene.c
+++ b/drivers/pci/host/pci-xgene.c
@@ -658,7 +658,6 @@ static int xgene_pcie_probe(struct platform_device *pdev)
 
         bus = bridge->bus;
 
-        pci_scan_child_bus(bus);
         pci_assign_unassigned_bus_resources(bus);
         list_for_each_entry(child, &bus->children, node)
                 pcie_bus_configure_settings(child);
diff --git a/drivers/pci/host/pcie-iproc-platform.c b/drivers/pci/host/pcie-iproc-platform.c
index 3e6927c318f2..e764a2a2693c 100644
--- a/drivers/pci/host/pcie-iproc-platform.c
+++ b/drivers/pci/host/pcie-iproc-platform.c
@@ -84,6 +84,13 @@ static int iproc_pcie_pltfm_probe(struct platform_device *pdev)
                 pcie->need_ob_cfg = true;
         }
 
+        /*
+         * DT nodes are not used by all platforms that use the iProc PCIe
+         * core driver. For platforms that require explict inbound mapping
+         * configuration, "dma-ranges" would have been present in DT
+         */
+        pcie->need_ib_cfg = of_property_read_bool(np, "dma-ranges");
+
         /* PHY use is optional */
         pcie->phy = devm_phy_get(dev, "pcie-phy");
         if (IS_ERR(pcie->phy)) {
diff --git a/drivers/pci/host/pcie-iproc.c b/drivers/pci/host/pcie-iproc.c
index 331dab12daee..cbb095481cdc 100644
--- a/drivers/pci/host/pcie-iproc.c
+++ b/drivers/pci/host/pcie-iproc.c
@@ -1370,9 +1370,11 @@ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
                 }
         }
 
-        ret = iproc_pcie_map_dma_ranges(pcie);
-        if (ret && ret != -ENOENT)
-                goto err_power_off_phy;
+        if (pcie->need_ib_cfg) {
+                ret = iproc_pcie_map_dma_ranges(pcie);
+                if (ret && ret != -ENOENT)
+                        goto err_power_off_phy;
+        }
 
 #ifdef CONFIG_ARM
         pcie->sysdata.private_data = pcie;
diff --git a/drivers/pci/host/pcie-iproc.h b/drivers/pci/host/pcie-iproc.h
index 944d546fba2a..d55f56a186cd 100644
--- a/drivers/pci/host/pcie-iproc.h
+++ b/drivers/pci/host/pcie-iproc.h
@@ -66,6 +66,7 @@ struct iproc_msi;
  * @ob: outbound mapping related parameters
  * @ob_map: outbound mapping related parameters specific to the controller
  *
+ * @need_ib_cfg: indicates SW needs to configure the inbound mapping window
  * @ib: inbound mapping related parameters
  * @ib_map: outbound mapping region related parameters
  *
@@ -93,6 +94,7 @@ struct iproc_pcie {
         struct iproc_pcie_ob ob;
         const struct iproc_pcie_ob_map *ob_map;
 
+        bool need_ib_cfg;
         struct iproc_pcie_ib ib;
         const struct iproc_pcie_ib_map *ib_map;
 
diff --git a/drivers/pci/host/pcie-rcar.c b/drivers/pci/host/pcie-rcar.c
index 5efce1f237c5..b4c4aad2cf66 100644
--- a/drivers/pci/host/pcie-rcar.c
+++ b/drivers/pci/host/pcie-rcar.c
@@ -456,7 +456,7 @@ static int rcar_pcie_enable(struct rcar_pcie *pcie)
 
         rcar_pcie_setup(&bridge->windows, pcie);
 
-        pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS);
+        pci_add_flags(PCI_REASSIGN_ALL_BUS);
 
         bridge->dev.parent = dev;
         bridge->sysdata = pcie;
@@ -1120,7 +1120,9 @@ static int rcar_pcie_probe(struct platform_device *pdev)
 
         INIT_LIST_HEAD(&pcie->resources);
 
-        rcar_pcie_parse_request_of_pci_ranges(pcie);
+        err = rcar_pcie_parse_request_of_pci_ranges(pcie);
+        if (err)
+                goto err_free_bridge;
 
         err = rcar_pcie_get_resources(pcie);
         if (err < 0) {
@@ -1175,6 +1177,7 @@ err_pm_disable:
 
 err_free_resource_list:
         pci_free_resource_list(&pcie->resources);
+err_free_bridge:
         pci_free_host_bridge(bridge);
 
         return err;
diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c
index 47498fb2a812..e2198a2feeca 100644
--- a/drivers/pci/hotplug/acpiphp_glue.c
+++ b/drivers/pci/hotplug/acpiphp_glue.c
@@ -797,10 +797,8 @@ void acpiphp_enumerate_slots(struct pci_bus *bus)
 
         handle = adev->handle;
         bridge = kzalloc(sizeof(struct acpiphp_bridge), GFP_KERNEL);
-        if (!bridge) {
-                acpi_handle_err(handle, "No memory for bridge object\n");
+        if (!bridge)
                 return;
-        }
 
         INIT_LIST_HEAD(&bridge->slots);
         kref_init(&bridge->ref);
diff --git a/drivers/pci/hotplug/cpqphp_core.c b/drivers/pci/hotplug/cpqphp_core.c
index 91669ab68ffb..1797e36ec586 100644
--- a/drivers/pci/hotplug/cpqphp_core.c
+++ b/drivers/pci/hotplug/cpqphp_core.c
@@ -821,7 +821,7 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 
         bus = pdev->subordinate;
         if (!bus) {
-                dev_notice(&pdev->dev, "the device is not a bridge, skipping\n");
+                pci_notice(pdev, "the device is not a bridge, skipping\n");
                 rc = -ENODEV;
                 goto err_disable_device;
         }
@@ -869,7 +869,6 @@ static int cpqhpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 
         ctrl = kzalloc(sizeof(struct controller), GFP_KERNEL);
         if (!ctrl) {
-                err("%s : out of memory\n", __func__);
                 rc = -ENOMEM;
                 goto err_disable_device;
         }
diff --git a/drivers/pci/hotplug/cpqphp_pci.c b/drivers/pci/hotplug/cpqphp_pci.c
index 21c9bf20e542..1b2b3f3b648b 100644
--- a/drivers/pci/hotplug/cpqphp_pci.c
+++ b/drivers/pci/hotplug/cpqphp_pci.c
@@ -75,7 +75,9 @@ int cpqhp_configure_device(struct controller *ctrl, struct pci_func *func)
         pci_lock_rescan_remove();
 
         if (func->pci_dev == NULL)
-                func->pci_dev = pci_get_bus_and_slot(func->bus, PCI_DEVFN(func->device, func->function));
+                func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus,
+                                                        PCI_DEVFN(func->device,
+                                                        func->function));
 
         /* No pci device, we need to create it then */
         if (func->pci_dev == NULL) {
@@ -85,7 +87,9 @@ int cpqhp_configure_device(struct controller *ctrl, struct pci_func *func)
                 if (num)
                         pci_bus_add_devices(ctrl->pci_dev->bus);
 
-                func->pci_dev = pci_get_bus_and_slot(func->bus, PCI_DEVFN(func->device, func->function));
+                func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus,
+                                                        PCI_DEVFN(func->device,
+                                                        func->function));
                 if (func->pci_dev == NULL) {
                         dbg("ERROR: pci_dev still null\n");
                         goto out;
@@ -115,7 +119,10 @@ int cpqhp_unconfigure_device(struct pci_func *func)
 
         pci_lock_rescan_remove();
         for (j = 0; j < 8 ; j++) {
-                struct pci_dev *temp = pci_get_bus_and_slot(func->bus, PCI_DEVFN(func->device, j));
+                struct pci_dev *temp = pci_get_domain_bus_and_slot(0,
+                                                        func->bus,
+                                                        PCI_DEVFN(func->device,
+                                                        j));
                 if (temp) {
                         pci_dev_put(temp);
                         pci_stop_and_remove_bus_device(temp);
@@ -305,6 +312,7 @@ int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug)
         int cloop = 0;
         int stop_it;
         int index;
+        u16 devfn;
 
         /* Decide which slots are supported */
 
@@ -402,7 +410,9 @@ int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug)
                         new_slot->switch_save = 0x10;
                         /* In case of unsupported board */
                         new_slot->status = DevError;
-                        new_slot->pci_dev = pci_get_bus_and_slot(new_slot->bus, (new_slot->device << 3) | new_slot->function);
+                        devfn = (new_slot->device << 3) | new_slot->function;
+                        new_slot->pci_dev = pci_get_domain_bus_and_slot(0,
+                                                        new_slot->bus, devfn);
 
                         for (cloop = 0; cloop < 0x20; cloop++) {
                                 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), cloop << 2, (u32 *) &(new_slot->config_space[cloop]));
diff --git a/drivers/pci/hotplug/ibmphp_core.c b/drivers/pci/hotplug/ibmphp_core.c
index e699220a6f37..b81ca3fa0e84 100644
--- a/drivers/pci/hotplug/ibmphp_core.c
+++ b/drivers/pci/hotplug/ibmphp_core.c
@@ -589,10 +589,8 @@ int ibmphp_update_slot_info(struct slot *slot_cur)
         u8 mode;
 
         info = kmalloc(sizeof(struct hotplug_slot_info), GFP_KERNEL);
-        if (!info) {
-                err("out of system memory\n");
+        if (!info)
                 return -ENOMEM;
-        }
 
         info->power_status = SLOT_PWRGD(slot_cur->status);
         info->attention_status = SLOT_ATTN(slot_cur->status,
@@ -693,7 +691,8 @@ static void ibm_unconfigure_device(struct pci_func *func)
         pci_lock_rescan_remove();
 
         for (j = 0; j < 0x08; j++) {
-                temp = pci_get_bus_and_slot(func->busno, (func->device << 3) | j);
+                temp = pci_get_domain_bus_and_slot(0, func->busno,
+                                                   (func->device << 3) | j);
                 if (temp) {
                         pci_stop_and_remove_bus_device(temp);
                         pci_dev_put(temp);
@@ -720,14 +719,12 @@ static u8 bus_structure_fixup(u8 busno)
                 return 1;
 
         bus = kmalloc(sizeof(*bus), GFP_KERNEL);
-        if (!bus) {
-                err("%s - out of memory\n", __func__);
+        if (!bus)
                 return 1;
-        }
+
         dev = kmalloc(sizeof(*dev), GFP_KERNEL);
         if (!dev) {
                 kfree(bus);
-                err("%s - out of memory\n", __func__);
                 return 1;
         }
 
@@ -766,7 +763,7 @@ static int ibm_configure_device(struct pci_func *func)
         if (!(bus_structure_fixup(func->busno)))
                 flag = 1;
         if (func->dev == NULL)
-                func->dev = pci_get_bus_and_slot(func->busno,
+                func->dev = pci_get_domain_bus_and_slot(0, func->busno,
                                 PCI_DEVFN(func->device, func->function));
 
         if (func->dev == NULL) {
@@ -779,7 +776,7 @@ static int ibm_configure_device(struct pci_func *func)
                 if (num)
                         pci_bus_add_devices(bus);
 
-                func->dev = pci_get_bus_and_slot(func->busno,
+                func->dev = pci_get_domain_bus_and_slot(0, func->busno,
                                 PCI_DEVFN(func->device, func->function));
                 if (func->dev == NULL) {
                         err("ERROR... : pci_dev still NULL\n");
@@ -1087,7 +1084,6 @@ static int enable_slot(struct hotplug_slot *hs)
         if (!slot_cur->func) {
                 /* We cannot do update_slot_info here, since no memory for
                  * kmalloc n.e.ways, and update_slot_info allocates some */
-                err("out of system memory\n");
                 rc = -ENOMEM;
                 goto error_power;
         }
@@ -1194,7 +1190,6 @@ int ibmphp_do_disable_slot(struct slot *slot_cur)
                 /* We need this for functions that were there on bootup */
                 slot_cur->func = kzalloc(sizeof(struct pci_func), GFP_KERNEL);
                 if (!slot_cur->func) {
-                        err("out of system memory\n");
                         rc = -ENOMEM;
                         goto error;
                 }
@@ -1292,7 +1287,6 @@ static int __init ibmphp_init(void)
 
         ibmphp_pci_bus = kmalloc(sizeof(*ibmphp_pci_bus), GFP_KERNEL);
         if (!ibmphp_pci_bus) {
-                err("out of memory\n");
                 rc = -ENOMEM;
                 goto exit;
         }
diff --git a/drivers/pci/hotplug/ibmphp_pci.c b/drivers/pci/hotplug/ibmphp_pci.c
index b95d60fa11e9..e22d023f91d1 100644
--- a/drivers/pci/hotplug/ibmphp_pci.c
+++ b/drivers/pci/hotplug/ibmphp_pci.c
@@ -153,10 +153,9 @@ int ibmphp_configure_card(struct pci_func *func, u8 slotno)
                                                 goto error;
                                         }
                                         newfunc = kzalloc(sizeof(*newfunc), GFP_KERNEL);
-                                        if (!newfunc) {
-                                                err("out of system memory\n");
+                                        if (!newfunc)
                                                 return -ENOMEM;
-                                        }
+
                                         newfunc->busno = cur_func->busno;
                                         newfunc->device = device;
                                         cur_func->next = newfunc;
@@ -191,10 +190,9 @@ int ibmphp_configure_card(struct pci_func *func, u8 slotno)
                                         for (i = 0; i < 32; i++) {
                                                 if (func->devices[i]) {
                                                         newfunc = kzalloc(sizeof(*newfunc), GFP_KERNEL);
-                                                        if (!newfunc) {
-                                                                err("out of system memory\n");
+                                                        if (!newfunc)
                                                                 return -ENOMEM;
-                                                        }
+
                                                         newfunc->busno = sec_number;
                                                         newfunc->device = (u8) i;
                                                         for (j = 0; j < 4; j++)
@@ -219,10 +217,9 @@ int ibmphp_configure_card(struct pci_func *func, u8 slotno)
                                         }
 
                                         newfunc = kzalloc(sizeof(*newfunc), GFP_KERNEL);
-                                        if (!newfunc) {
-                                                err("out of system memory\n");
+                                        if (!newfunc)
                                                 return -ENOMEM;
-                                        }
+
                                         newfunc->busno = cur_func->busno;
                                         newfunc->device = device;
                                         for (j = 0; j < 4; j++)
@@ -265,10 +262,9 @@ int ibmphp_configure_card(struct pci_func *func, u8 slotno)
                                                 if (func->devices[i]) {
                                                         debug("inside for loop, device is %x\n", i);
                                                         newfunc = kzalloc(sizeof(*newfunc), GFP_KERNEL);
-                                                        if (!newfunc) {
-                                                                err(" out of system memory\n");
+                                                        if (!newfunc)
                                                                 return -ENOMEM;
-                                                        }
+
                                                         newfunc->busno = sec_number;
                                                         newfunc->device = (u8) i;
                                                         for (j = 0; j < 4; j++)
@@ -391,10 +387,9 @@ static int configure_device(struct pci_func *func)
 
                         io[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
 
-                        if (!io[count]) {
-                                err("out of system memory\n");
+                        if (!io[count])
                                 return -ENOMEM;
-                        }
+
                         io[count]->type = IO;
                         io[count]->busno = func->busno;
                         io[count]->devfunc = PCI_DEVFN(func->device, func->function);
@@ -428,10 +423,9 @@ static int configure_device(struct pci_func *func)
                                 debug("len[count] in PFMEM %x, count %d\n", len[count], count);
 
                                 pfmem[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
-                                if (!pfmem[count]) {
-                                        err("out of system memory\n");
+                                if (!pfmem[count])
                                         return -ENOMEM;
-                                }
+
                                 pfmem[count]->type = PFMEM;
                                 pfmem[count]->busno = func->busno;
                                 pfmem[count]->devfunc = PCI_DEVFN(func->device,
@@ -444,7 +438,6 @@ static int configure_device(struct pci_func *func)
                                 } else {
                                         mem_tmp = kzalloc(sizeof(*mem_tmp), GFP_KERNEL);
                                         if (!mem_tmp) {
-                                                err("out of system memory\n");
                                                 kfree(pfmem[count]);
                                                 return -ENOMEM;
                                         }
@@ -494,10 +487,9 @@ static int configure_device(struct pci_func *func)
                                 debug("len[count] in Mem %x, count %d\n", len[count], count);
 
                                 mem[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
-                                if (!mem[count]) {
-                                        err("out of system memory\n");
+                                if (!mem[count])
                                         return -ENOMEM;
-                                }
+
                                 mem[count]->type = MEM;
                                 mem[count]->busno = func->busno;
                                 mem[count]->devfunc = PCI_DEVFN(func->device,
@@ -660,7 +652,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno)
                         bus_io[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
 
                         if (!bus_io[count]) {
-                                err("out of system memory\n");
                                 retval = -ENOMEM;
                                 goto error;
                         }
@@ -692,7 +683,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno)
 
                                 bus_pfmem[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
                                 if (!bus_pfmem[count]) {
-                                        err("out of system memory\n");
                                         retval = -ENOMEM;
                                         goto error;
                                 }
@@ -708,7 +698,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno)
                                 } else {
                                         mem_tmp = kzalloc(sizeof(*mem_tmp), GFP_KERNEL);
                                         if (!mem_tmp) {
-                                                err("out of system memory\n");
                                                 retval = -ENOMEM;
                                                 goto error;
                                         }
@@ -749,7 +738,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno)
 
                                 bus_mem[count] = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
                                 if (!bus_mem[count]) {
-                                        err("out of system memory\n");
                                         retval = -ENOMEM;
                                         goto error;
                                 }
@@ -820,7 +808,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno)
                 io = kzalloc(sizeof(*io), GFP_KERNEL);
 
                 if (!io) {
-                        err("out of system memory\n");
                         retval = -ENOMEM;
                         goto error;
                 }
@@ -842,7 +829,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno)
                 debug("it wants %x memory behind the bridge\n", amount_needed->mem);
                 mem = kzalloc(sizeof(*mem), GFP_KERNEL);
                 if (!mem) {
-                        err("out of system memory\n");
                         retval = -ENOMEM;
                         goto error;
                 }
@@ -864,7 +850,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno)
                 debug("it wants %x pfmemory behind the bridge\n", amount_needed->pfmem);
                 pfmem = kzalloc(sizeof(*pfmem), GFP_KERNEL);
                 if (!pfmem) {
-                        err("out of system memory\n");
                         retval = -ENOMEM;
                         goto error;
                 }
@@ -879,7 +864,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno)
                 } else {
                         mem_tmp = kzalloc(sizeof(*mem_tmp), GFP_KERNEL);
                         if (!mem_tmp) {
-                                err("out of system memory\n");
                                 retval = -ENOMEM;
                                 goto error;
                         }
@@ -910,7 +894,6 @@ static int configure_bridge(struct pci_func **func_passed, u8 slotno)
                 if (!bus) {
                         bus = kzalloc(sizeof(*bus), GFP_KERNEL);
                         if (!bus) {
-                                err("out of system memory\n");
                                 retval = -ENOMEM;
                                 goto error;
                         }
@@ -1638,10 +1621,9 @@ static int add_new_bus(struct bus_node *bus, struct resource_node *io, struct re
         }
         if (io) {
                 io_range = kzalloc(sizeof(*io_range), GFP_KERNEL);
-                if (!io_range) {
-                        err("out of system memory\n");
+                if (!io_range)
                         return -ENOMEM;
-                }
+
                 io_range->start = io->start;
                 io_range->end = io->end;
                 io_range->rangeno = 1;
@@ -1650,10 +1632,9 @@ static int add_new_bus(struct bus_node *bus, struct resource_node *io, struct re
         }
         if (mem) {
                 mem_range = kzalloc(sizeof(*mem_range), GFP_KERNEL);
-                if (!mem_range) {
-                        err("out of system memory\n");
+                if (!mem_range)
                         return -ENOMEM;
-                }
+
                 mem_range->start = mem->start;
                 mem_range->end = mem->end;
                 mem_range->rangeno = 1;
@@ -1662,10 +1643,9 @@ static int add_new_bus(struct bus_node *bus, struct resource_node *io, struct re
         }
         if (pfmem) {
                 pfmem_range = kzalloc(sizeof(*pfmem_range), GFP_KERNEL);
-                if (!pfmem_range) {
-                        err("out of system memory\n");
+                if (!pfmem_range)
                         return -ENOMEM;
-                }
+
                 pfmem_range->start = pfmem->start;
                 pfmem_range->end = pfmem->end;
                 pfmem_range->rangeno = 1;
diff --git a/drivers/pci/hotplug/ibmphp_res.c b/drivers/pci/hotplug/ibmphp_res.c
index 41851f58b2fd..5e8caf7a4452 100644
--- a/drivers/pci/hotplug/ibmphp_res.c
+++ b/drivers/pci/hotplug/ibmphp_res.c
@@ -42,10 +42,8 @@ static struct bus_node * __init alloc_error_bus(struct ebda_pci_rsrc *curr, u8 b
         }
 
         newbus = kzalloc(sizeof(struct bus_node), GFP_KERNEL);
-        if (!newbus) {
-                err("out of system memory\n");
+        if (!newbus)
                 return NULL;
-        }
 
         if (flag)
                 newbus->busno = busno;
@@ -65,10 +63,9 @@ static struct resource_node * __init alloc_resources(struct ebda_pci_rsrc *curr)
         }
 
         rs = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
-        if (!rs) {
-                err("out of system memory\n");
+        if (!rs)
                 return NULL;
-        }
+
         rs->busno = curr->bus_num;
         rs->devfunc = curr->dev_fun;
         rs->start = curr->start_addr;
@@ -85,10 +82,9 @@ static int __init alloc_bus_range(struct bus_node **new_bus, struct range_node *
 
         if (first_bus) {
                 newbus = kzalloc(sizeof(struct bus_node), GFP_KERNEL);
-                if (!newbus) {
-                        err("out of system memory.\n");
+                if (!newbus)
                         return -ENOMEM;
-                }
+
                 newbus->busno = curr->bus_num;
         } else {
                 newbus = *new_bus;
@@ -109,7 +105,6 @@ static int __init alloc_bus_range(struct bus_node **new_bus, struct range_node *
         if (!newrange) {
                 if (first_bus)
                         kfree(newbus);
-                err("out of system memory\n");
                 return -ENOMEM;
         }
         newrange->start = curr->start_addr;
@@ -1693,10 +1688,9 @@ static int __init once_over(void)
                                 bus_cur->firstPFMemFromMem = pfmem_cur;
 
                                 mem = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
-                                if (!mem) {
-                                        err("out of system memory\n");
+                                if (!mem)
                                         return -ENOMEM;
-                                }
+
                                 mem->type = MEM;
                                 mem->busno = pfmem_cur->busno;
                                 mem->devfunc = pfmem_cur->devfunc;
@@ -1975,10 +1969,9 @@ static int __init update_bridge_ranges(struct bus_node **bus)
 
                                                 if ((start_address) && (start_address <= end_address)) {
                                                         range = kzalloc(sizeof(struct range_node), GFP_KERNEL);
-                                                        if (!range) {
-                                                                err("out of system memory\n");
+                                                        if (!range)
                                                                 return -ENOMEM;
-                                                        }
+
                                                         range->start = start_address;
                                                         range->end = end_address + 0xfff;
 
@@ -2002,7 +1995,6 @@ static int __init update_bridge_ranges(struct bus_node **bus)
                                                                 io = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
                                                                 if (!io) {
                                                                         kfree(range);
-                                                                        err("out of system memory\n");
                                                                         return -ENOMEM;
                                                                 }
                                                                 io->type = IO;
@@ -2024,10 +2016,9 @@ static int __init update_bridge_ranges(struct bus_node **bus)
                                                 if ((start_address) && (start_address <= end_address)) {
 
                                                         range = kzalloc(sizeof(struct range_node), GFP_KERNEL);
-                                                        if (!range) {
-                                                                err("out of system memory\n");
+                                                        if (!range)
                                                                 return -ENOMEM;
-                                                        }
+
                                                         range->start = start_address;
                                                         range->end = end_address + 0xfffff;
 
@@ -2052,7 +2043,6 @@ static int __init update_bridge_ranges(struct bus_node **bus)
                                                                 mem = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
                                                                 if (!mem) {
                                                                         kfree(range);
-                                                                        err("out of system memory\n");
                                                                         return -ENOMEM;
                                                                 }
                                                                 mem->type = MEM;
@@ -2078,10 +2068,9 @@ static int __init update_bridge_ranges(struct bus_node **bus)
                                                 if ((start_address) && (start_address <= end_address)) {
 
                                                         range = kzalloc(sizeof(struct range_node), GFP_KERNEL);
-                                                        if (!range) {
-                                                                err("out of system memory\n");
+                                                        if (!range)
                                                                 return -ENOMEM;
-                                                        }
+
                                                         range->start = start_address;
                                                         range->end = end_address + 0xfffff;
 
@@ -2105,7 +2094,6 @@ static int __init update_bridge_ranges(struct bus_node **bus)
                                                                 pfmem = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
                                                                 if (!pfmem) {
                                                                         kfree(range);
-                                                                        err("out of system memory\n");
                                                                         return -ENOMEM;
                                                                 }
                                                                 pfmem->type = PFMEM;
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index c414d59372e0..18a42f8f5dc5 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -824,16 +824,22 @@ struct controller *pcie_init(struct pcie_device *dev)
         struct pci_dev *pdev = dev->port;
 
         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
-        if (!ctrl) {
-                dev_err(&dev->device, "%s: Out of memory\n", __func__);
+        if (!ctrl)
                 goto abort;
-        }
+
         ctrl->pcie = dev;
         pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
 
         if (pdev->hotplug_user_indicators)
                 slot_cap &= ~(PCI_EXP_SLTCAP_AIP | PCI_EXP_SLTCAP_PIP);
 
+        /*
+         * We assume no Thunderbolt controllers support Command Complete events,
+         * but some controllers falsely claim they do.
+         */
+        if (pdev->is_thunderbolt)
+                slot_cap |= PCI_EXP_SLTCAP_NCCS;
+
         ctrl->slot_cap = slot_cap;
         mutex_init(&ctrl->ctrl_lock);
         init_waitqueue_head(&ctrl->queue);
diff --git a/drivers/pci/hotplug/pciehp_pci.c b/drivers/pci/hotplug/pciehp_pci.c
index fd673a5ab925..3f518dea856d 100644
--- a/drivers/pci/hotplug/pciehp_pci.c
+++ b/drivers/pci/hotplug/pciehp_pci.c
@@ -65,7 +65,6 @@ int pciehp_configure_device(struct slot *p_slot)
 int pciehp_unconfigure_device(struct slot *p_slot)
 {
         int rc = 0;
-        u8 bctl = 0;
         u8 presence = 0;
         struct pci_dev *dev, *temp;
         struct pci_bus *parent = p_slot->ctrl->pcie->port->subordinate;
@@ -87,17 +86,6 @@ int pciehp_unconfigure_device(struct slot *p_slot)
         list_for_each_entry_safe_reverse(dev, temp, &parent->devices,
                                          bus_list) {
                 pci_dev_get(dev);
-                if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE && presence) {
-                        pci_read_config_byte(dev, PCI_BRIDGE_CONTROL, &bctl);
-                        if (bctl & PCI_BRIDGE_CTL_VGA) {
-                                ctrl_err(ctrl,
-                                         "Cannot remove display device %s\n",
-                                         pci_name(dev));
-                                pci_dev_put(dev);
-                                rc = -EINVAL;
-                                break;
-                        }
-                }
                 if (!presence) {
                         pci_dev_set_disconnected(dev, NULL);
                         if (pci_has_subordinate(dev))
diff --git a/drivers/pci/hotplug/pnv_php.c b/drivers/pci/hotplug/pnv_php.c
index 36ef485630da..23da3046f160 100644
--- a/drivers/pci/hotplug/pnv_php.c
+++ b/drivers/pci/hotplug/pnv_php.c
@@ -262,22 +262,18 @@ static int pnv_php_add_devtree(struct pnv_php_slot *php_slot)
         fdt1 = kzalloc(0x10000, GFP_KERNEL);
         if (!fdt1) {
                 ret = -ENOMEM;
-                dev_warn(&php_slot->pdev->dev, "Cannot alloc FDT blob\n");
                 goto out;
         }
 
         ret = pnv_pci_get_device_tree(php_slot->dn->phandle, fdt1, 0x10000);
         if (ret) {
-                dev_warn(&php_slot->pdev->dev, "Error %d getting FDT blob\n",
-                         ret);
+                pci_warn(php_slot->pdev, "Error %d getting FDT blob\n", ret);
                 goto free_fdt1;
         }
 
         fdt = kzalloc(fdt_totalsize(fdt1), GFP_KERNEL);
         if (!fdt) {
                 ret = -ENOMEM;
-                dev_warn(&php_slot->pdev->dev, "Cannot %d bytes memory\n",
-                         fdt_totalsize(fdt1));
                 goto free_fdt1;
         }
 
@@ -286,7 +282,7 @@ static int pnv_php_add_devtree(struct pnv_php_slot *php_slot)
         dt = of_fdt_unflatten_tree(fdt, php_slot->dn, NULL);
         if (!dt) {
                 ret = -EINVAL;
-                dev_warn(&php_slot->pdev->dev, "Cannot unflatten FDT\n");
+                pci_warn(php_slot->pdev, "Cannot unflatten FDT\n");
                 goto free_fdt;
         }
 
@@ -296,7 +292,7 @@ static int pnv_php_add_devtree(struct pnv_php_slot *php_slot)
         ret = pnv_php_populate_changeset(&php_slot->ocs, php_slot->dn);
         if (ret) {
                 pnv_php_reverse_nodes(php_slot->dn);
-                dev_warn(&php_slot->pdev->dev, "Error %d populating changeset\n",
+                pci_warn(php_slot->pdev, "Error %d populating changeset\n",
                          ret);
                 goto free_dt;
         }
@@ -304,8 +300,7 @@ static int pnv_php_add_devtree(struct pnv_php_slot *php_slot)
         php_slot->dn->child = NULL;
         ret = of_changeset_apply(&php_slot->ocs);
         if (ret) {
-                dev_warn(&php_slot->pdev->dev, "Error %d applying changeset\n",
-                         ret);
+                pci_warn(php_slot->pdev, "Error %d applying changeset\n", ret);
                 goto destroy_changeset;
         }
 
@@ -341,14 +336,14 @@ int pnv_php_set_slot_power_state(struct hotplug_slot *slot,
                 if (be64_to_cpu(msg.params[1]) != php_slot->dn->phandle ||
                     be64_to_cpu(msg.params[2]) != state                 ||
                     be64_to_cpu(msg.params[3]) != OPAL_SUCCESS) {
-                        dev_warn(&php_slot->pdev->dev, "Wrong msg (%lld, %lld, %lld)\n",
+                        pci_warn(php_slot->pdev, "Wrong msg (%lld, %lld, %lld)\n",
                                  be64_to_cpu(msg.params[1]),
                                  be64_to_cpu(msg.params[2]),
                                  be64_to_cpu(msg.params[3]));
                         return -ENOMSG;
                 }
         } else if (ret < 0) {
-                dev_warn(&php_slot->pdev->dev, "Error %d powering %s\n",
+                pci_warn(php_slot->pdev, "Error %d powering %s\n",
                          ret, (state == OPAL_PCI_SLOT_POWER_ON) ? "on" : "off");
                 return ret;
         }
@@ -375,7 +370,7 @@ static int pnv_php_get_power_state(struct hotplug_slot *slot, u8 *state)
          */
         ret = pnv_pci_get_power_state(php_slot->id, &power_state);
         if (ret) {
-                dev_warn(&php_slot->pdev->dev, "Error %d getting power status\n",
+                pci_warn(php_slot->pdev, "Error %d getting power status\n",
                          ret);
         } else {
                 *state = power_state;
@@ -401,8 +396,7 @@ static int pnv_php_get_adapter_state(struct hotplug_slot *slot, u8 *state)
                 slot->info->adapter_status = presence;
                 ret = 0;
         } else {
-                dev_warn(&php_slot->pdev->dev, "Error %d getting presence\n",
-                         ret);
+                pci_warn(php_slot->pdev, "Error %d getting presence\n", ret);
         }
 
         return ret;
@@ -625,8 +619,7 @@ static int pnv_php_register_slot(struct pnv_php_slot *php_slot)
         ret = pci_hp_register(&php_slot->slot, php_slot->bus,
                               php_slot->slot_no, php_slot->name);
         if (ret) {
-                dev_warn(&php_slot->pdev->dev, "Error %d registering slot\n",
-                         ret);
+                pci_warn(php_slot->pdev, "Error %d registering slot\n", ret);
                 return ret;
         }
 
@@ -679,7 +672,7 @@ static int pnv_php_enable_msix(struct pnv_php_slot *php_slot)
         /* Enable MSIx */
         ret = pci_enable_msix_exact(pdev, &entry, 1);
         if (ret) {
-                dev_warn(&pdev->dev, "Error %d enabling MSIx\n", ret);
+                pci_warn(pdev, "Error %d enabling MSIx\n", ret);
                 return ret;
         }
 
@@ -723,7 +716,7 @@ static irqreturn_t pnv_php_interrupt(int irq, void *data)
                    (sts & PCI_EXP_SLTSTA_PDC)) {
                 ret = pnv_pci_get_presence_state(php_slot->id, &presence);
                 if (ret) {
-                        dev_warn(&pdev->dev, "PCI slot [%s] error %d getting presence (0x%04x), to retry the operation.\n",
+                        pci_warn(pdev, "PCI slot [%s] error %d getting presence (0x%04x), to retry the operation.\n",
                                  php_slot->name, ret, sts);
                         return IRQ_HANDLED;
                 }
@@ -753,12 +746,12 @@ static irqreturn_t pnv_php_interrupt(int irq, void *data)
          */
         event = kzalloc(sizeof(*event), GFP_ATOMIC);
         if (!event) {
-                dev_warn(&pdev->dev, "PCI slot [%s] missed hotplug event 0x%04x\n",
+                pci_warn(pdev, "PCI slot [%s] missed hotplug event 0x%04x\n",
                          php_slot->name, sts);
                 return IRQ_HANDLED;
         }
 
-        dev_info(&pdev->dev, "PCI slot [%s] %s (IRQ: %d)\n",
+        pci_info(pdev, "PCI slot [%s] %s (IRQ: %d)\n",
                  php_slot->name, added ? "added" : "removed", irq);
         INIT_WORK(&event->work, pnv_php_event_handler);
         event->added = added;
@@ -778,7 +771,7 @@ static void pnv_php_init_irq(struct pnv_php_slot *php_slot, int irq)
         /* Allocate workqueue */
         php_slot->wq = alloc_workqueue("pciehp-%s", 0, 0, php_slot->name);
         if (!php_slot->wq) {
-                dev_warn(&pdev->dev, "Cannot alloc workqueue\n");
+                pci_warn(pdev, "Cannot alloc workqueue\n");
                 pnv_php_disable_irq(php_slot, true);
                 return;
         }
@@ -802,7 +795,7 @@ static void pnv_php_init_irq(struct pnv_php_slot *php_slot, int irq)
                           php_slot->name, php_slot);
         if (ret) {
                 pnv_php_disable_irq(php_slot, true);
-                dev_warn(&pdev->dev, "Error %d enabling IRQ %d\n", ret, irq);
+                pci_warn(pdev, "Error %d enabling IRQ %d\n", ret, irq);
                 return;
         }
 
@@ -838,7 +831,7 @@ static void pnv_php_enable_irq(struct pnv_php_slot *php_slot)
 
         ret = pci_enable_device(pdev);
         if (ret) {
-                dev_warn(&pdev->dev, "Error %d enabling device\n", ret);
+                pci_warn(pdev, "Error %d enabling device\n", ret);
                 return;
         }
 
diff --git a/drivers/pci/hotplug/sgi_hotplug.c b/drivers/pci/hotplug/sgi_hotplug.c
index 42d713578524..78b6bdbb3a39 100644
--- a/drivers/pci/hotplug/sgi_hotplug.c
+++ b/drivers/pci/hotplug/sgi_hotplug.c
@@ -242,18 +242,18 @@ static int sn_slot_enable(struct hotplug_slot *bss_hotplug_slot,
 
 
         if (rc == PCI_SLOT_ALREADY_UP) {
-                dev_dbg(&slot->pci_bus->self->dev, "is already active\n");
+                pci_dbg(slot->pci_bus->self, "is already active\n");
                 return 1; /* return 1 to user */
         }
 
         if (rc == PCI_L1_ERR) {
-                dev_dbg(&slot->pci_bus->self->dev, "L1 failure %d with message: %s",
+                pci_dbg(slot->pci_bus->self, "L1 failure %d with message: %s",
                         resp.resp_sub_errno, resp.resp_l1_msg);
                 return -EPERM;
         }
 
         if (rc) {
-                dev_dbg(&slot->pci_bus->self->dev, "insert failed with error %d sub-error %d\n",
+                pci_dbg(slot->pci_bus->self, "insert failed with error %d sub-error %d\n",
                         rc, resp.resp_sub_errno);
                 return -EIO;
         }
@@ -278,23 +278,23 @@ static int sn_slot_disable(struct hotplug_slot *bss_hotplug_slot,
 
         if ((action == PCI_REQ_SLOT_ELIGIBLE) &&
             (rc == PCI_SLOT_ALREADY_DOWN)) {
-                dev_dbg(&slot->pci_bus->self->dev, "Slot %s already inactive\n", slot->physical_path);
+                pci_dbg(slot->pci_bus->self, "Slot %s already inactive\n", slot->physical_path);
                 return 1; /* return 1 to user */
         }
 
         if ((action == PCI_REQ_SLOT_ELIGIBLE) && (rc == PCI_EMPTY_33MHZ)) {
-                dev_dbg(&slot->pci_bus->self->dev, "Cannot remove last 33MHz card\n");
+                pci_dbg(slot->pci_bus->self, "Cannot remove last 33MHz card\n");
                 return -EPERM;
         }
 
         if ((action == PCI_REQ_SLOT_ELIGIBLE) && (rc == PCI_L1_ERR)) {
-                dev_dbg(&slot->pci_bus->self->dev, "L1 failure %d with message \n%s\n",
+                pci_dbg(slot->pci_bus->self, "L1 failure %d with message \n%s\n",
                         resp.resp_sub_errno, resp.resp_l1_msg);
                 return -EPERM;
         }
 
         if ((action == PCI_REQ_SLOT_ELIGIBLE) && rc) {
-                dev_dbg(&slot->pci_bus->self->dev, "remove failed with error %d sub-error %d\n",
+                pci_dbg(slot->pci_bus->self, "remove failed with error %d sub-error %d\n",
                         rc, resp.resp_sub_errno);
                 return -EIO;
         }
@@ -305,12 +305,12 @@ static int sn_slot_disable(struct hotplug_slot *bss_hotplug_slot,
         if ((action == PCI_REQ_SLOT_DISABLE) && !rc) {
                 pcibus_info = SN_PCIBUS_BUSSOFT_INFO(slot->pci_bus);
                 pcibus_info->pbi_enabled_devices &= ~(1 << device_num);
-                dev_dbg(&slot->pci_bus->self->dev, "remove successful\n");
+                pci_dbg(slot->pci_bus->self, "remove successful\n");
                 return 0;
         }
 
         if ((action == PCI_REQ_SLOT_DISABLE) && rc) {
-                dev_dbg(&slot->pci_bus->self->dev, "remove failed rc = %d\n", rc);
+                pci_dbg(slot->pci_bus->self, "remove failed rc = %d\n", rc);
         }
 
         return rc;
@@ -363,7 +363,7 @@ static int enable_slot(struct hotplug_slot *bss_hotplug_slot)
         num_funcs = pci_scan_slot(slot->pci_bus,
                                   PCI_DEVFN(slot->device_num + 1, 0));
         if (!num_funcs) {
-                dev_dbg(&slot->pci_bus->self->dev, "no device in slot\n");
+                pci_dbg(slot->pci_bus->self, "no device in slot\n");
                 mutex_unlock(&sn_hotplug_mutex);
                 return -ENODEV;
         }
@@ -409,7 +409,7 @@ static int enable_slot(struct hotplug_slot *bss_hotplug_slot)
                 phandle = acpi_device_handle(PCI_CONTROLLER(slot->pci_bus)->companion);
 
                 if (acpi_bus_get_device(phandle, &pdevice)) {
-                        dev_dbg(&slot->pci_bus->self->dev, "no parent device, assuming NULL\n");
+                        pci_dbg(slot->pci_bus->self, "no parent device, assuming NULL\n");
                         pdevice = NULL;
                 }
 
@@ -460,9 +460,9 @@ static int enable_slot(struct hotplug_slot *bss_hotplug_slot)
         mutex_unlock(&sn_hotplug_mutex);
 
         if (rc == 0)
-                dev_dbg(&slot->pci_bus->self->dev, "insert operation successful\n");
+                pci_dbg(slot->pci_bus->self, "insert operation successful\n");
         else
-                dev_dbg(&slot->pci_bus->self->dev, "insert operation failed rc = %d\n", rc);
+                pci_dbg(slot->pci_bus->self, "insert operation failed rc = %d\n", rc);
 
         return rc;
 }
@@ -640,16 +640,16 @@ static int sn_hotplug_slot_register(struct pci_bus *pci_bus)
                 if (rc)
                         goto register_err;
         }
-        dev_dbg(&pci_bus->self->dev, "Registered bus with hotplug\n");
+        pci_dbg(pci_bus->self, "Registered bus with hotplug\n");
         return rc;
 
 register_err:
-        dev_dbg(&pci_bus->self->dev, "bus failed to register with err = %d\n",
+        pci_dbg(pci_bus->self, "bus failed to register with err = %d\n",
                 rc);
 
 alloc_err:
         if (rc == -ENOMEM)
-                dev_dbg(&pci_bus->self->dev, "Memory allocation error\n");
+                pci_dbg(pci_bus->self, "Memory allocation error\n");
 
         /* destroy THIS element */
         if (bss_hotplug_slot)
@@ -682,10 +682,10 @@ static int __init sn_pci_hotplug_init(void)
 
                 rc = sn_pci_bus_valid(pci_bus);
                 if (rc != 1) {
-                        dev_dbg(&pci_bus->self->dev, "not a valid hotplug bus\n");
+                        pci_dbg(pci_bus->self, "not a valid hotplug bus\n");
                         continue;
                 }
-                dev_dbg(&pci_bus->self->dev, "valid hotplug bus\n");
+                pci_dbg(pci_bus->self, "valid hotplug bus\n");
 
                 rc = sn_hotplug_slot_register(pci_bus);
                 if (!rc) {
diff --git a/drivers/pci/hotplug/shpchp.h b/drivers/pci/hotplug/shpchp.h
index 98f867bd570f..c55730b61c9a 100644
--- a/drivers/pci/hotplug/shpchp.h
+++ b/drivers/pci/hotplug/shpchp.h
@@ -48,15 +48,15 @@ do {									\
 #define ctrl_dbg(ctrl, format, arg...)                                  \
         do {                                                            \
                 if (shpchp_debug)                                       \
-                        dev_printk(KERN_DEBUG, &ctrl->pci_dev->dev,     \
+                        pci_printk(KERN_DEBUG, ctrl->pci_dev,           \
                                         format, ## arg);                \
         } while (0)
 #define ctrl_err(ctrl, format, arg...)                                  \
-        dev_err(&ctrl->pci_dev->dev, format, ## arg)
+        pci_err(ctrl->pci_dev, format, ## arg)
 #define ctrl_info(ctrl, format, arg...)                                 \
-        dev_info(&ctrl->pci_dev->dev, format, ## arg)
+        pci_info(ctrl->pci_dev, format, ## arg)
 #define ctrl_warn(ctrl, format, arg...)                                 \
-        dev_warn(&ctrl->pci_dev->dev, format, ## arg)
+        pci_warn(ctrl->pci_dev, format, ## arg)
 
 
 #define SLOT_NAME_SIZE 10
diff --git a/drivers/pci/hotplug/shpchp_core.c b/drivers/pci/hotplug/shpchp_core.c
index f55ea1b68dff..1f0f96908b5a 100644
--- a/drivers/pci/hotplug/shpchp_core.c
+++ b/drivers/pci/hotplug/shpchp_core.c
@@ -291,10 +291,9 @@ static int shpc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                 return -ENODEV;
 
         ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
-        if (!ctrl) {
-                dev_err(&pdev->dev, "%s: Out of memory\n", __func__);
+        if (!ctrl)
                 goto err_out_none;
-        }
+
         INIT_LIST_HEAD(&ctrl->slot_list);
 
         rc = shpc_init(ctrl, pdev);
diff --git a/drivers/pci/hotplug/shpchp_pci.c b/drivers/pci/hotplug/shpchp_pci.c
index c3d3919236be..115701301487 100644
--- a/drivers/pci/hotplug/shpchp_pci.c
+++ b/drivers/pci/hotplug/shpchp_pci.c
@@ -64,7 +64,6 @@ int shpchp_configure_device(struct slot *p_slot)
 int shpchp_unconfigure_device(struct slot *p_slot)
 {
         int rc = 0;
-        u8 bctl = 0;
         struct pci_bus *parent = p_slot->ctrl->pci_dev->subordinate;
         struct pci_dev *dev, *temp;
         struct controller *ctrl = p_slot->ctrl;
@@ -79,17 +78,6 @@ int shpchp_unconfigure_device(struct slot *p_slot)
                         continue;
 
                 pci_dev_get(dev);
-                if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
-                        pci_read_config_byte(dev, PCI_BRIDGE_CONTROL, &bctl);
-                        if (bctl & PCI_BRIDGE_CTL_VGA) {
-                                ctrl_err(ctrl,
-                                         "Cannot remove display device %s\n",
-                                         pci_name(dev));
-                                pci_dev_put(dev);
-                                rc = -EINVAL;
-                                break;
-                        }
-                }
                 pci_stop_and_remove_bus_device(dev);
                 pci_dev_put(dev);
         }
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index c533325e8d86..ec69506bfde2 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -260,19 +260,19 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
                         nres++;
         }
         if (nres != iov->nres) {
-                dev_err(&dev->dev, "not enough MMIO resources for SR-IOV\n");
+                pci_err(dev, "not enough MMIO resources for SR-IOV\n");
                 return -ENOMEM;
         }
 
         bus = pci_iov_virtfn_bus(dev, nr_virtfn - 1);
         if (bus > dev->bus->busn_res.end) {
-                dev_err(&dev->dev, "can't enable %d VFs (bus %02x out of range of %pR)\n",
+                pci_err(dev, "can't enable %d VFs (bus %02x out of range of %pR)\n",
                         nr_virtfn, bus, &dev->bus->busn_res);
                 return -ENOMEM;
         }
 
         if (pci_enable_resources(dev, bars)) {
-                dev_err(&dev->dev, "SR-IOV: IOV BARS not allocated\n");
+                pci_err(dev, "SR-IOV: IOV BARS not allocated\n");
                 return -ENOMEM;
         }
 
@@ -299,7 +299,7 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
 
         rc = pcibios_sriov_enable(dev, initial);
         if (rc) {
-                dev_err(&dev->dev, "failure %d from pcibios_sriov_enable()\n", rc);
+                pci_err(dev, "failure %d from pcibios_sriov_enable()\n", rc);
                 goto err_pcibios;
         }
 
@@ -433,7 +433,7 @@ found:
                 }
                 iov->barsz[i] = resource_size(res);
                 res->end = res->start + resource_size(res) * total - 1;
-                dev_info(&dev->dev, "VF(n) BAR%d space: %pR (contains BAR%d for %d VFs)\n",
+                pci_info(dev, "VF(n) BAR%d space: %pR (contains BAR%d for %d VFs)\n",
                          i, res, i, total);
                 i += bar64;
                 nres++;
diff --git a/drivers/pci/irq.c b/drivers/pci/irq.c
index 10929cd43d5d..2a808e10645f 100644
--- a/drivers/pci/irq.c
+++ b/drivers/pci/irq.c
@@ -16,11 +16,10 @@ static void pci_note_irq_problem(struct pci_dev *pdev, const char *reason)
 {
         struct pci_dev *parent = to_pci_dev(pdev->dev.parent);
 
-        dev_err(&pdev->dev,
-                "Potentially misrouted IRQ (Bridge %s %04x:%04x)\n",
+        pci_err(pdev, "Potentially misrouted IRQ (Bridge %s %04x:%04x)\n",
                 dev_name(&parent->dev), parent->vendor, parent->device);
-        dev_err(&pdev->dev, "%s\n", reason);
-        dev_err(&pdev->dev, "Please report to linux-kernel@vger.kernel.org\n");
+        pci_err(pdev, "%s\n", reason);
+        pci_err(pdev, "Please report to linux-kernel@vger.kernel.org\n");
         WARN_ON(1);
 }
 
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 7f7547d200e4..8b0729c94bb7 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -579,7 +579,7 @@ static int msi_verify_entries(struct pci_dev *dev)
         for_each_pci_msi_entry(entry, dev) {
                 if (!dev->no_64bit_msi || !entry->msg.address_hi)
                         continue;
-                dev_err(&dev->dev, "Device has broken 64-bit MSI but arch"
+                pci_err(dev, "Device has broken 64-bit MSI but arch"
                         " tried to assign one above 4G\n");
                 return -EIO;
         }
@@ -963,7 +963,7 @@ static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
 
         /* Check whether driver already requested for MSI irq */
         if (dev->msi_enabled) {
-                dev_info(&dev->dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
+                pci_info(dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
                 return -EINVAL;
         }
         return msix_capability_init(dev, entries, nvec, affd);
@@ -1033,8 +1033,7 @@ static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
 
         /* Check whether driver already requested MSI-X irqs */
         if (dev->msix_enabled) {
-                dev_info(&dev->dev,
-                         "can't enable MSI (MSI-X already enabled)\n");
+                pci_info(dev, "can't enable MSI (MSI-X already enabled)\n");
                 return -EINVAL;
         }
 
diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index fd721b8140e7..a28355c273ae 100644
--- a/drivers/pci/of.c
+++ b/drivers/pci/of.c
@@ -4,12 +4,14 @@
  *
  * Copyright 2011 IBM Corp.
  */
+#define pr_fmt(fmt)     "PCI: OF: " fmt
 
 #include <linux/irqdomain.h>
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/of.h>
 #include <linux/of_irq.h>
+#include <linux/of_address.h>
 #include <linux/of_pci.h>
 #include "pci.h"
 
@@ -47,8 +49,9 @@ struct device_node * __weak pcibios_get_phb_of_node(struct pci_bus *bus)
         if (WARN_ON(bus->self || bus->parent))
                 return NULL;
 
-        /* Look for a node pointer in either the intermediary device we
-         * create above the root bus or it's own parent. Normally only
+        /*
+         * Look for a node pointer in either the intermediary device we
+         * create above the root bus or its own parent. Normally only
          * the later is populated.
          */
         if (bus->bridge->of_node)
@@ -84,3 +87,561 @@ struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus)
         return NULL;
 #endif
 }
+
+static inline int __of_pci_pci_compare(struct device_node *node,
+                                       unsigned int data)
+{
+        int devfn;
+
+        devfn = of_pci_get_devfn(node);
+        if (devfn < 0)
+                return 0;
+
+        return devfn == data;
+}
+
+struct device_node *of_pci_find_child_device(struct device_node *parent,
+                                             unsigned int devfn)
+{
+        struct device_node *node, *node2;
+
+        for_each_child_of_node(parent, node) {
+                if (__of_pci_pci_compare(node, devfn))
+                        return node;
+                /*
+                 * Some OFs create a parent node "multifunc-device" as
+                 * a fake root for all functions of a multi-function
+                 * device we go down them as well.
+                 */
+                if (!strcmp(node->name, "multifunc-device")) {
+                        for_each_child_of_node(node, node2) {
+                                if (__of_pci_pci_compare(node2, devfn)) {
+                                        of_node_put(node);
+                                        return node2;
+                                }
+                        }
+                }
+        }
+        return NULL;
+}
+EXPORT_SYMBOL_GPL(of_pci_find_child_device);
+
+/**
+ * of_pci_get_devfn() - Get device and function numbers for a device node
+ * @np: device node
+ *
+ * Parses a standard 5-cell PCI resource and returns an 8-bit value that can
+ * be passed to the PCI_SLOT() and PCI_FUNC() macros to extract the device
+ * and function numbers respectively. On error a negative error code is
+ * returned.
+ */
+int of_pci_get_devfn(struct device_node *np)
+{
+        u32 reg[5];
+        int error;
+
+        error = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg));
+        if (error)
+                return error;
+
+        return (reg[0] >> 8) & 0xff;
+}
+EXPORT_SYMBOL_GPL(of_pci_get_devfn);
+
+/**
+ * of_pci_parse_bus_range() - parse the bus-range property of a PCI device
+ * @node: device node
+ * @res: address to a struct resource to return the bus-range
+ *
+ * Returns 0 on success or a negative error-code on failure.
+ */
+int of_pci_parse_bus_range(struct device_node *node, struct resource *res)
+{
+        u32 bus_range[2];
+        int error;
+
+        error = of_property_read_u32_array(node, "bus-range", bus_range,
+                                           ARRAY_SIZE(bus_range));
+        if (error)
+                return error;
+
+        res->name = node->name;
+        res->start = bus_range[0];
+        res->end = bus_range[1];
+        res->flags = IORESOURCE_BUS;
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(of_pci_parse_bus_range);
+
+/**
+ * This function will try to obtain the host bridge domain number by
+ * finding a property called "linux,pci-domain" of the given device node.
+ *
+ * @node: device tree node with the domain information
+ *
+ * Returns the associated domain number from DT in the range [0-0xffff], or
+ * a negative value if the required property is not found.
+ */
+int of_get_pci_domain_nr(struct device_node *node)
+{
+        u32 domain;
+        int error;
+
+        error = of_property_read_u32(node, "linux,pci-domain", &domain);
+        if (error)
+                return error;
+
+        return (u16)domain;
+}
+EXPORT_SYMBOL_GPL(of_get_pci_domain_nr);
+
+/**
+ * This function will try to find the limitation of link speed by finding
+ * a property called "max-link-speed" of the given device node.
+ *
+ * @node: device tree node with the max link speed information
+ *
+ * Returns the associated max link speed from DT, or a negative value if the
+ * required property is not found or is invalid.
+ */
+int of_pci_get_max_link_speed(struct device_node *node)
+{
+        u32 max_link_speed;
+
+        if (of_property_read_u32(node, "max-link-speed", &max_link_speed) ||
+            max_link_speed > 4)
+                return -EINVAL;
+
+        return max_link_speed;
+}
+EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed);
+
+/**
+ * of_pci_check_probe_only - Setup probe only mode if linux,pci-probe-only
+ *                           is present and valid
+ */
+void of_pci_check_probe_only(void)
+{
+        u32 val;
+        int ret;
+
+        ret = of_property_read_u32(of_chosen, "linux,pci-probe-only", &val);
+        if (ret) {
+                if (ret == -ENODATA || ret == -EOVERFLOW)
+                        pr_warn("linux,pci-probe-only without valid value, ignoring\n");
+                return;
+        }
+
+        if (val)
+                pci_add_flags(PCI_PROBE_ONLY);
+        else
+                pci_clear_flags(PCI_PROBE_ONLY);
+
+        pr_info("PROBE_ONLY %sabled\n", val ? "en" : "dis");
+}
+EXPORT_SYMBOL_GPL(of_pci_check_probe_only);
+
+#if defined(CONFIG_OF_ADDRESS)
+/**
+ * of_pci_get_host_bridge_resources - Parse PCI host bridge resources from DT
+ * @dev: device node of the host bridge having the range property
+ * @busno: bus number associated with the bridge root bus
+ * @bus_max: maximum number of buses for this bridge
+ * @resources: list where the range of resources will be added after DT parsing
+ * @io_base: pointer to a variable that will contain on return the physical
+ * address for the start of the I/O range. Can be NULL if the caller doesn't
+ * expect I/O ranges to be present in the device tree.
+ *
+ * It is the caller's job to free the @resources list.
+ *
+ * This function will parse the "ranges" property of a PCI host bridge device
+ * node and setup the resource mapping based on its content. It is expected
+ * that the property conforms with the Power ePAPR document.
+ *
+ * It returns zero if the range parsing has been successful or a standard error
+ * value if it failed.
+ */
+int of_pci_get_host_bridge_resources(struct device_node *dev,
+                        unsigned char busno, unsigned char bus_max,
+                        struct list_head *resources, resource_size_t *io_base)
+{
+        struct resource_entry *window;
+        struct resource *res;
+        struct resource *bus_range;
+        struct of_pci_range range;
+        struct of_pci_range_parser parser;
+        char range_type[4];
+        int err;
+
+        if (io_base)
+                *io_base = (resource_size_t)OF_BAD_ADDR;
+
+        bus_range = kzalloc(sizeof(*bus_range), GFP_KERNEL);
+        if (!bus_range)
+                return -ENOMEM;
+
+        pr_info("host bridge %pOF ranges:\n", dev);
+
+        err = of_pci_parse_bus_range(dev, bus_range);
+        if (err) {
+                bus_range->start = busno;
+                bus_range->end = bus_max;
+                bus_range->flags = IORESOURCE_BUS;
+                pr_info("  No bus range found for %pOF, using %pR\n",
+                        dev, bus_range);
+        } else {
+                if (bus_range->end > bus_range->start + bus_max)
+                        bus_range->end = bus_range->start + bus_max;
+        }
+        pci_add_resource(resources, bus_range);
+
+        /* Check for ranges property */
+        err = of_pci_range_parser_init(&parser, dev);
+        if (err)
+                goto parse_failed;
+
+        pr_debug("Parsing ranges property...\n");
+        for_each_of_pci_range(&parser, &range) {
+                /* Read next ranges element */
+                if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_IO)
+                        snprintf(range_type, 4, " IO");
+                else if ((range.flags & IORESOURCE_TYPE_BITS) == IORESOURCE_MEM)
+                        snprintf(range_type, 4, "MEM");
+                else
+                        snprintf(range_type, 4, "err");
+                pr_info("  %s %#010llx..%#010llx -> %#010llx\n", range_type,
+                        range.cpu_addr, range.cpu_addr + range.size - 1,
+                        range.pci_addr);
+
+                /*
+                 * If we failed translation or got a zero-sized region
+                 * then skip this range
+                 */
+                if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
+                        continue;
+
+                res = kzalloc(sizeof(struct resource), GFP_KERNEL);
+                if (!res) {
+                        err = -ENOMEM;
+                        goto parse_failed;
+                }
+
+                err = of_pci_range_to_resource(&range, dev, res);
+                if (err) {
+                        kfree(res);
+                        continue;
+                }
+
+                if (resource_type(res) == IORESOURCE_IO) {
+                        if (!io_base) {
+                                pr_err("I/O range found for %pOF. Please provide an io_base pointer to save CPU base address\n",
+                                        dev);
+                                err = -EINVAL;
+                                goto conversion_failed;
+                        }
+                        if (*io_base != (resource_size_t)OF_BAD_ADDR)
+                                pr_warn("More than one I/O resource converted for %pOF. CPU base address for old range lost!\n",
+                                        dev);
+                        *io_base = range.cpu_addr;
+                }
+
+                pci_add_resource_offset(resources, res, res->start - range.pci_addr);
+        }
+
+        return 0;
+
+conversion_failed:
+        kfree(res);
+parse_failed:
+        resource_list_for_each_entry(window, resources)
+                kfree(window->res);
+        pci_free_resource_list(resources);
+        return err;
+}
+EXPORT_SYMBOL_GPL(of_pci_get_host_bridge_resources);
+#endif /* CONFIG_OF_ADDRESS */
+
+/**
+ * of_pci_map_rid - Translate a requester ID through a downstream mapping.
+ * @np: root complex device node.
+ * @rid: PCI requester ID to map.
+ * @map_name: property name of the map to use.
+ * @map_mask_name: optional property name of the mask to use.
+ * @target: optional pointer to a target device node.
+ * @id_out: optional pointer to receive the translated ID.
+ *
+ * Given a PCI requester ID, look up the appropriate implementation-defined
+ * platform ID and/or the target device which receives transactions on that
+ * ID, as per the "iommu-map" and "msi-map" bindings. Either of @target or
+ * @id_out may be NULL if only the other is required. If @target points to
+ * a non-NULL device node pointer, only entries targeting that node will be
+ * matched; if it points to a NULL value, it will receive the device node of
+ * the first matching target phandle, with a reference held.
+ *
+ * Return: 0 on success or a standard error code on failure.
+ */
+int of_pci_map_rid(struct device_node *np, u32 rid,
+                   const char *map_name, const char *map_mask_name,
+                   struct device_node **target, u32 *id_out)
+{
+        u32 map_mask, masked_rid;
+        int map_len;
+        const __be32 *map = NULL;
+
+        if (!np || !map_name || (!target && !id_out))
+                return -EINVAL;
+
+        map = of_get_property(np, map_name, &map_len);
+        if (!map) {
+                if (target)
+                        return -ENODEV;
+                /* Otherwise, no map implies no translation */
+                *id_out = rid;
+                return 0;
+        }
+
+        if (!map_len || map_len % (4 * sizeof(*map))) {
+                pr_err("%pOF: Error: Bad %s length: %d\n", np,
+                        map_name, map_len);
+                return -EINVAL;
+        }
+
+        /* The default is to select all bits. */
+        map_mask = 0xffffffff;
+
+        /*
+         * Can be overridden by "{iommu,msi}-map-mask" property.
+         * If of_property_read_u32() fails, the default is used.
+         */
+        if (map_mask_name)
+                of_property_read_u32(np, map_mask_name, &map_mask);
+
+        masked_rid = map_mask & rid;
+        for ( ; map_len > 0; map_len -= 4 * sizeof(*map), map += 4) {
+                struct device_node *phandle_node;
+                u32 rid_base = be32_to_cpup(map + 0);
+                u32 phandle = be32_to_cpup(map + 1);
+                u32 out_base = be32_to_cpup(map + 2);
+                u32 rid_len = be32_to_cpup(map + 3);
+
+                if (rid_base & ~map_mask) {
+                        pr_err("%pOF: Invalid %s translation - %s-mask (0x%x) ignores rid-base (0x%x)\n",
+                                np, map_name, map_name,
+                                map_mask, rid_base);
+                        return -EFAULT;
+                }
+
+                if (masked_rid < rid_base || masked_rid >= rid_base + rid_len)
+                        continue;
+
+                phandle_node = of_find_node_by_phandle(phandle);
+                if (!phandle_node)
+                        return -ENODEV;
+
+                if (target) {
+                        if (*target)
+                                of_node_put(phandle_node);
+                        else
+                                *target = phandle_node;
+
+                        if (*target != phandle_node)
+                                continue;
+                }
+
+                if (id_out)
+                        *id_out = masked_rid - rid_base + out_base;
+
+                pr_debug("%pOF: %s, using mask %08x, rid-base: %08x, out-base: %08x, length: %08x, rid: %08x -> %08x\n",
+                        np, map_name, map_mask, rid_base, out_base,
+                        rid_len, rid, masked_rid - rid_base + out_base);
+                return 0;
+        }
+
+        pr_err("%pOF: Invalid %s translation - no match for rid 0x%x on %pOF\n",
+                np, map_name, rid, target && *target ? *target : NULL);
+        return -EFAULT;
+}
+
+#if IS_ENABLED(CONFIG_OF_IRQ)
+/**
+ * of_irq_parse_pci - Resolve the interrupt for a PCI device
+ * @pdev:       the device whose interrupt is to be resolved
+ * @out_irq:    structure of_irq filled by this function
+ *
+ * This function resolves the PCI interrupt for a given PCI device. If a
+ * device-node exists for a given pci_dev, it will use normal OF tree
+ * walking. If not, it will implement standard swizzling and walk up the
+ * PCI tree until an device-node is found, at which point it will finish
+ * resolving using the OF tree walking.
+ */
+static int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *out_irq)
+{
+        struct device_node *dn, *ppnode;
+        struct pci_dev *ppdev;
+        __be32 laddr[3];
+        u8 pin;
+        int rc;
+
+        /*
+         * Check if we have a device node, if yes, fallback to standard
+         * device tree parsing
+         */
+        dn = pci_device_to_OF_node(pdev);
+        if (dn) {
+                rc = of_irq_parse_one(dn, 0, out_irq);
+                if (!rc)
+                        return rc;
+        }
+
+        /*
+         * Ok, we don't, time to have fun. Let's start by building up an
+         * interrupt spec.  we assume #interrupt-cells is 1, which is standard
+         * for PCI. If you do different, then don't use that routine.
+         */
+        rc = pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pin);
+        if (rc != 0)
+                goto err;
+        /* No pin, exit with no error message. */
+        if (pin == 0)
+                return -ENODEV;
+
+        /* Now we walk up the PCI tree */
+        for (;;) {
+                /* Get the pci_dev of our parent */
+                ppdev = pdev->bus->self;
+
+                /* Ouch, it's a host bridge... */
+                if (ppdev == NULL) {
+                        ppnode = pci_bus_to_OF_node(pdev->bus);
+
+                        /* No node for host bridge ? give up */
+                        if (ppnode == NULL) {
+                                rc = -EINVAL;
+                                goto err;
+                        }
+                } else {
+                        /* We found a P2P bridge, check if it has a node */
+                        ppnode = pci_device_to_OF_node(ppdev);
+                }
+
+                /*
+                 * Ok, we have found a parent with a device-node, hand over to
+                 * the OF parsing code.
+                 * We build a unit address from the linux device to be used for
+                 * resolution. Note that we use the linux bus number which may
+                 * not match your firmware bus numbering.
+                 * Fortunately, in most cases, interrupt-map-mask doesn't
+                 * include the bus number as part of the matching.
+                 * You should still be careful about that though if you intend
+                 * to rely on this function (you ship a firmware that doesn't
+                 * create device nodes for all PCI devices).
+                 */
+                if (ppnode)
+                        break;
+
+                /*
+                 * We can only get here if we hit a P2P bridge with no node;
+                 * let's do standard swizzling and try again
+                 */
+                pin = pci_swizzle_interrupt_pin(pdev, pin);
+                pdev = ppdev;
+        }
+
+        out_irq->np = ppnode;
+        out_irq->args_count = 1;
+        out_irq->args[0] = pin;
+        laddr[0] = cpu_to_be32((pdev->bus->number << 16) | (pdev->devfn << 8));
+        laddr[1] = laddr[2] = cpu_to_be32(0);
+        rc = of_irq_parse_raw(laddr, out_irq);
+        if (rc)
+                goto err;
+        return 0;
+err:
+        if (rc == -ENOENT) {
+                dev_warn(&pdev->dev,
+                        "%s: no interrupt-map found, INTx interrupts not available\n",
+                        __func__);
+                pr_warn_once("%s: possibly some PCI slots don't have level triggered interrupts capability\n",
+                        __func__);
+        } else {
+                dev_err(&pdev->dev, "%s: failed with rc=%d\n", __func__, rc);
+        }
+        return rc;
+}
+
+/**
+ * of_irq_parse_and_map_pci() - Decode a PCI IRQ from the device tree and map to a VIRQ
+ * @dev: The PCI device needing an IRQ
+ * @slot: PCI slot number; passed when used as map_irq callback. Unused
+ * @pin: PCI IRQ pin number; passed when used as map_irq callback. Unused
+ *
+ * @slot and @pin are unused, but included in the function so that this
+ * function can be used directly as the map_irq callback to
+ * pci_assign_irq() and struct pci_host_bridge.map_irq pointer
+ */
+int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        struct of_phandle_args oirq;
+        int ret;
+
+        ret = of_irq_parse_pci(dev, &oirq);
+        if (ret)
+                return 0; /* Proper return code 0 == NO_IRQ */
+
+        return irq_create_of_mapping(&oirq);
+}
+EXPORT_SYMBOL_GPL(of_irq_parse_and_map_pci);
+#endif  /* CONFIG_OF_IRQ */
+
+int pci_parse_request_of_pci_ranges(struct device *dev,
+                                    struct list_head *resources,
+                                    struct resource **bus_range)
+{
+        int err, res_valid = 0;
+        struct device_node *np = dev->of_node;
+        resource_size_t iobase;
+        struct resource_entry *win, *tmp;
+
+        INIT_LIST_HEAD(resources);
+        err = of_pci_get_host_bridge_resources(np, 0, 0xff, resources, &iobase);
+        if (err)
+                return err;
+
+        err = devm_request_pci_bus_resources(dev, resources);
+        if (err)
+                goto out_release_res;
+
+        resource_list_for_each_entry_safe(win, tmp, resources) {
+                struct resource *res = win->res;
+
+                switch (resource_type(res)) {
+                case IORESOURCE_IO:
+                        err = pci_remap_iospace(res, iobase);
+                        if (err) {
+                                dev_warn(dev, "error %d: failed to map resource %pR\n",
+                                         err, res);
+                                resource_list_destroy_entry(win);
+                        }
+                        break;
+                case IORESOURCE_MEM:
+                        res_valid |= !(res->flags & IORESOURCE_PREFETCH);
+                        break;
+                case IORESOURCE_BUS:
+                        if (bus_range)
+                                *bus_range = res;
+                        break;
+                }
+        }
+
+        if (res_valid)
+                return 0;
+
+        dev_err(dev, "non-prefetchable memory resource required\n");
+        err = -EINVAL;
+
+ out_release_res:
+        pci_free_resource_list(resources);
+        return err;
+}
+
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index 3b82bb86a203..78157688dcc9 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -543,7 +543,7 @@ static int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
         }
 
         if (!error)
-                dev_dbg(&dev->dev, "power state changed by ACPI to %s\n",
+                pci_dbg(dev, "power state changed by ACPI to %s\n",
                          acpi_power_state_string(state_conv[state]));
 
         return error;
diff --git a/drivers/pci/pci-stub.c b/drivers/pci/pci-stub.c
index a952007b7608..10d54f939048 100644
--- a/drivers/pci/pci-stub.c
+++ b/drivers/pci/pci-stub.c
@@ -27,7 +27,7 @@ MODULE_PARM_DESC(ids, "Initial PCI IDs to add to the stub driver, format is "
 
 static int pci_stub_probe(struct pci_dev *dev, const struct pci_device_id *id)
 {
-        dev_info(&dev->dev, "claimed by stub\n");
+        pci_info(dev, "claimed by stub\n");
         return 0;
 }
 
diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
index 06c7f0b85cd2..eb6bee8724cc 100644
--- a/drivers/pci/pci-sysfs.c
+++ b/drivers/pci/pci-sysfs.c
@@ -278,6 +278,16 @@ static ssize_t subordinate_bus_number_show(struct device *dev,
 }
 static DEVICE_ATTR_RO(subordinate_bus_number);
 
+static ssize_t ari_enabled_show(struct device *dev,
+                                struct device_attribute *attr,
+                                char *buf)
+{
+        struct pci_dev *pci_dev = to_pci_dev(dev);
+
+        return sprintf(buf, "%u\n", pci_ari_enabled(pci_dev->bus));
+}
+static DEVICE_ATTR_RO(ari_enabled);
+
 static ssize_t modalias_show(struct device *dev, struct device_attribute *attr,
                              char *buf)
 {
@@ -348,7 +358,7 @@ static ssize_t numa_node_store(struct device *dev,
                 return -EINVAL;
 
         add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
-        dev_alert(&pdev->dev, FW_BUG "Overriding NUMA node to %d.  Contact your vendor for updates.",
+        pci_alert(pdev, FW_BUG "Overriding NUMA node to %d.  Contact your vendor for updates.",
                   node);
 
         dev->numa_node = node;
@@ -411,7 +421,7 @@ static ssize_t msi_bus_store(struct device *dev, struct device_attribute *attr,
          */
         if (!subordinate) {
                 pdev->no_msi = !val;
-                dev_info(&pdev->dev, "MSI/MSI-X %s for future drivers\n",
+                pci_info(pdev, "MSI/MSI-X %s for future drivers\n",
                          val ? "allowed" : "disallowed");
                 return count;
         }
@@ -613,7 +623,7 @@ static ssize_t sriov_numvfs_store(struct device *dev,
 
         /* is PF driver loaded w/callback */
         if (!pdev->driver || !pdev->driver->sriov_configure) {
-                dev_info(&pdev->dev, "Driver doesn't support SRIOV configuration via sysfs\n");
+                pci_info(pdev, "Driver doesn't support SRIOV configuration via sysfs\n");
                 ret = -ENOENT;
                 goto exit;
         }
@@ -626,7 +636,7 @@ static ssize_t sriov_numvfs_store(struct device *dev,
 
         /* enable VFs */
         if (pdev->sriov->num_VFs) {
-                dev_warn(&pdev->dev, "%d VFs already enabled. Disable before enabling %d VFs\n",
+                pci_warn(pdev, "%d VFs already enabled. Disable before enabling %d VFs\n",
                          pdev->sriov->num_VFs, num_vfs);
                 ret = -EBUSY;
                 goto exit;
@@ -637,7 +647,7 @@ static ssize_t sriov_numvfs_store(struct device *dev,
                 goto exit;
 
         if (ret != num_vfs)
-                dev_warn(&pdev->dev, "%d VFs requested; only %d enabled\n",
+                pci_warn(pdev, "%d VFs requested; only %d enabled\n",
                          num_vfs, ret);
 
 exit:
@@ -786,6 +796,7 @@ static struct attribute *pci_dev_attrs[] = {
         &dev_attr_devspec.attr,
 #endif
         &dev_attr_driver_override.attr,
+        &dev_attr_ari_enabled.attr,
         NULL,
 };
 
@@ -1216,14 +1227,9 @@ static int pci_mmap_resource(struct kobject *kobj, struct bin_attribute *attr,
         if (res->flags & IORESOURCE_MEM && iomem_is_exclusive(res->start))
                 return -EINVAL;
 
-        if (!pci_mmap_fits(pdev, bar, vma, PCI_MMAP_SYSFS)) {
-                WARN(1, "process \"%s\" tried to map 0x%08lx bytes at page 0x%08lx on %s BAR %d (start 0x%16Lx, size 0x%16Lx)\n",
-                        current->comm, vma->vm_end-vma->vm_start, vma->vm_pgoff,
-                        pci_name(pdev), bar,
-                        (u64)pci_resource_start(pdev, bar),
-                        (u64)pci_resource_len(pdev, bar));
+        if (!pci_mmap_fits(pdev, bar, vma, PCI_MMAP_SYSFS))
                 return -EINVAL;
-        }
+
         mmap_type = res->flags & IORESOURCE_MEM ? pci_mmap_mem : pci_mmap_io;
 
         return pci_mmap_resource_range(pdev, bar, vma, mmap_type, write_combine);
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 50e716b3e2b8..006814babdce 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -157,7 +157,7 @@ void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
          * Make sure the BAR is actually a memory resource, not an IO resource
          */
         if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
-                dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res);
+                pci_warn(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
                 return NULL;
         }
         return ioremap_nocache(res->start, resource_size(res));
@@ -649,7 +649,7 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
          */
         if (state != PCI_D0 && dev->current_state <= PCI_D3cold
             && dev->current_state > state) {
-                dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n",
+                pci_err(dev, "invalid power transition (from state %d to %d)\n",
                         dev->current_state, state);
                 return -EINVAL;
         }
@@ -697,7 +697,7 @@ static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
         pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
         dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
         if (dev->current_state != state && printk_ratelimit())
-                dev_info(&dev->dev, "Refused to change power state, currently in D%d\n",
+                pci_info(dev, "Refused to change power state, currently in D%d\n",
                          dev->current_state);
 
         /*
@@ -971,7 +971,7 @@ pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
         case PM_EVENT_HIBERNATE:
                 return PCI_D3hot;
         default:
-                dev_info(&dev->dev, "unrecognized suspend event %d\n",
+                pci_info(dev, "unrecognized suspend event %d\n",
                          state.event);
                 BUG();
         }
@@ -1014,7 +1014,7 @@ static int pci_save_pcie_state(struct pci_dev *dev)
 
         save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
         if (!save_state) {
-                dev_err(&dev->dev, "buffer not found in %s\n", __func__);
+                pci_err(dev, "buffer not found in %s\n", __func__);
                 return -ENOMEM;
         }
 
@@ -1062,7 +1062,7 @@ static int pci_save_pcix_state(struct pci_dev *dev)
 
         save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
         if (!save_state) {
-                dev_err(&dev->dev, "buffer not found in %s\n", __func__);
+                pci_err(dev, "buffer not found in %s\n", __func__);
                 return -ENOMEM;
         }
 
@@ -1122,7 +1122,7 @@ static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
                 return;
 
         for (;;) {
-                dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
+                pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
                         offset, val, saved_val);
                 pci_write_config_dword(pdev, offset, saved_val);
                 if (retry-- <= 0)
@@ -1359,7 +1359,7 @@ static void pci_enable_bridge(struct pci_dev *dev)
 
         retval = pci_enable_device(dev);
         if (retval)
-                dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
+                pci_err(dev, "Error enabling bridge (%d), continuing\n",
                         retval);
         pci_set_master(dev);
 }
@@ -1864,7 +1864,7 @@ void pci_pme_active(struct pci_dev *dev, bool enable)
                         pme_dev = kmalloc(sizeof(struct pci_pme_device),
                                           GFP_KERNEL);
                         if (!pme_dev) {
-                                dev_warn(&dev->dev, "can't enable PME#\n");
+                                pci_warn(dev, "can't enable PME#\n");
                                 return;
                         }
                         pme_dev->dev = dev;
@@ -1888,7 +1888,7 @@ void pci_pme_active(struct pci_dev *dev, bool enable)
                 }
         }
 
-        dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
+        pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
 }
 EXPORT_SYMBOL(pci_pme_active);
 
@@ -2425,7 +2425,7 @@ void pci_pm_init(struct pci_dev *dev)
         pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
 
         if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
-                dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
+                pci_err(dev, "unsupported PM cap regs version (%u)\n",
                         pmc & PCI_PM_CAP_VER_MASK);
                 return;
         }
@@ -2445,15 +2445,14 @@ void pci_pm_init(struct pci_dev *dev)
                         dev->d2_support = true;
 
                 if (dev->d1_support || dev->d2_support)
-                        dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
+                        pci_printk(KERN_DEBUG, dev, "supports%s%s\n",
                                    dev->d1_support ? " D1" : "",
                                    dev->d2_support ? " D2" : "");
         }
 
         pmc &= PCI_PM_CAP_PME_MASK;
         if (pmc) {
-                dev_printk(KERN_DEBUG, &dev->dev,
-                         "PME# supported from%s%s%s%s%s\n",
+                pci_printk(KERN_DEBUG, dev, "PME# supported from%s%s%s%s%s\n",
                          (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
                          (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
                          (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
@@ -2545,13 +2544,13 @@ static int pci_ea_read(struct pci_dev *dev, int offset)
 
         res = pci_ea_get_resource(dev, bei, prop);
         if (!res) {
-                dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei);
+                pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
                 goto out;
         }
 
         flags = pci_ea_flags(dev, prop);
         if (!flags) {
-                dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop);
+                pci_err(dev, "Unsupported EA properties: %#x\n", prop);
                 goto out;
         }
 
@@ -2601,13 +2600,12 @@ static int pci_ea_read(struct pci_dev *dev, int offset)
         }
 
         if (end < start) {
-                dev_err(&dev->dev, "EA Entry crosses address boundary\n");
+                pci_err(dev, "EA Entry crosses address boundary\n");
                 goto out;
         }
 
         if (ent_size != ent_offset - offset) {
-                dev_err(&dev->dev,
-                        "EA Entry Size (%d) does not match length read (%d)\n",
+                pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
                         ent_size, ent_offset - offset);
                 goto out;
         }
@@ -2618,16 +2616,16 @@ static int pci_ea_read(struct pci_dev *dev, int offset)
         res->flags = flags;
 
         if (bei <= PCI_EA_BEI_BAR5)
-                dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
+                pci_printk(KERN_DEBUG, dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
                            bei, res, prop);
         else if (bei == PCI_EA_BEI_ROM)
-                dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
+                pci_printk(KERN_DEBUG, dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
                            res, prop);
         else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
-                dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
+                pci_printk(KERN_DEBUG, dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
                            bei - PCI_EA_BEI_VF_BAR0, res, prop);
         else
-                dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
+                pci_printk(KERN_DEBUG, dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
                            bei, res, prop);
 
 out:
@@ -2724,13 +2722,11 @@ void pci_allocate_cap_save_buffers(struct pci_dev *dev)
         error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
                                         PCI_EXP_SAVE_REGS * sizeof(u16));
         if (error)
-                dev_err(&dev->dev,
-                        "unable to preallocate PCI Express save buffer\n");
+                pci_err(dev, "unable to preallocate PCI Express save buffer\n");
 
         error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
         if (error)
-                dev_err(&dev->dev,
-                        "unable to preallocate PCI-X save buffer\n");
+                pci_err(dev, "unable to preallocate PCI-X save buffer\n");
 
         pci_allocate_vc_save_buffers(dev);
 }
@@ -3067,6 +3063,81 @@ int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
 }
 
 /**
+ * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
+ * @dev: the PCI device
+ * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
+ *      PCI_EXP_DEVCAP2_ATOMIC_COMP32
+ *      PCI_EXP_DEVCAP2_ATOMIC_COMP64
+ *      PCI_EXP_DEVCAP2_ATOMIC_COMP128
+ *
+ * Return 0 if all upstream bridges support AtomicOp routing, egress
+ * blocking is disabled on all upstream ports, and the root port supports
+ * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
+ * AtomicOp completion), or negative otherwise.
+ */
+int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
+{
+        struct pci_bus *bus = dev->bus;
+        struct pci_dev *bridge;
+        u32 cap, ctl2;
+
+        if (!pci_is_pcie(dev))
+                return -EINVAL;
+
+        /*
+         * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
+         * AtomicOp requesters.  For now, we only support endpoints as
+         * requesters and root ports as completers.  No endpoints as
+         * completers, and no peer-to-peer.
+         */
+
+        switch (pci_pcie_type(dev)) {
+        case PCI_EXP_TYPE_ENDPOINT:
+        case PCI_EXP_TYPE_LEG_END:
+        case PCI_EXP_TYPE_RC_END:
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        while (bus->parent) {
+                bridge = bus->self;
+
+                pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
+
+                switch (pci_pcie_type(bridge)) {
+                /* Ensure switch ports support AtomicOp routing */
+                case PCI_EXP_TYPE_UPSTREAM:
+                case PCI_EXP_TYPE_DOWNSTREAM:
+                        if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
+                                return -EINVAL;
+                        break;
+
+                /* Ensure root port supports all the sizes we care about */
+                case PCI_EXP_TYPE_ROOT_PORT:
+                        if ((cap & cap_mask) != cap_mask)
+                                return -EINVAL;
+                        break;
+                }
+
+                /* Ensure upstream ports don't block AtomicOps on egress */
+                if (!bridge->has_secondary_link) {
+                        pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
+                                                   &ctl2);
+                        if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
+                                return -EINVAL;
+                }
+
+                bus = bus->parent;
+        }
+
+        pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
+                                 PCI_EXP_DEVCTL2_ATOMIC_REQ);
+        return 0;
+}
+EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
+
+/**
  * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
  * @dev: the PCI device
  * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
@@ -3199,7 +3270,7 @@ static int __pci_request_region(struct pci_dev *pdev, int bar,
         return 0;
 
 err_out:
-        dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
+        pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
                  &pdev->resource[bar]);
         return -EBUSY;
 }
@@ -3622,7 +3693,7 @@ static void __pci_set_master(struct pci_dev *dev, bool enable)
         else
                 cmd = old_cmd & ~PCI_COMMAND_MASTER;
         if (cmd != old_cmd) {
-                dev_dbg(&dev->dev, "%s bus mastering\n",
+                pci_dbg(dev, "%s bus mastering\n",
                         enable ? "enabling" : "disabling");
                 pci_write_config_word(dev, PCI_COMMAND, cmd);
         }
@@ -3723,7 +3794,7 @@ int pci_set_cacheline_size(struct pci_dev *dev)
         if (cacheline_size == pci_cache_line_size)
                 return 0;
 
-        dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n",
+        pci_printk(KERN_DEBUG, dev, "cache line size of %d is not supported\n",
                    pci_cache_line_size << 2);
 
         return -EINVAL;
@@ -3752,7 +3823,7 @@ int pci_set_mwi(struct pci_dev *dev)
 
         pci_read_config_word(dev, PCI_COMMAND, &cmd);
         if (!(cmd & PCI_COMMAND_INVALIDATE)) {
-                dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
+                pci_dbg(dev, "enabling Mem-Wr-Inval\n");
                 cmd |= PCI_COMMAND_INVALIDATE;
                 pci_write_config_word(dev, PCI_COMMAND, cmd);
         }
@@ -3948,13 +4019,13 @@ static void pci_flr_wait(struct pci_dev *dev)
         pci_read_config_dword(dev, PCI_COMMAND, &id);
         while (id == ~0) {
                 if (delay > timeout) {
-                        dev_warn(&dev->dev, "not ready %dms after FLR; giving up\n",
+                        pci_warn(dev, "not ready %dms after FLR; giving up\n",
                                  100 + delay - 1);
                         return;
                 }
 
                 if (delay > 1000)
-                        dev_info(&dev->dev, "not ready %dms after FLR; waiting\n",
+                        pci_info(dev, "not ready %dms after FLR; waiting\n",
                                  100 + delay - 1);
 
                 msleep(delay);
@@ -3963,7 +4034,7 @@ static void pci_flr_wait(struct pci_dev *dev)
         }
 
         if (delay > 1000)
-                dev_info(&dev->dev, "ready %dms after FLR\n", 100 + delay - 1);
+                pci_info(dev, "ready %dms after FLR\n", 100 + delay - 1);
 }
 
 /**
@@ -3995,7 +4066,7 @@ static bool pcie_has_flr(struct pci_dev *dev)
 void pcie_flr(struct pci_dev *dev)
 {
         if (!pci_wait_for_pending_transaction(dev))
-                dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
+                pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
 
         pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
         pci_flr_wait(dev);
@@ -4028,7 +4099,7 @@ static int pci_af_flr(struct pci_dev *dev, int probe)
          */
         if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
                                  PCI_AF_STATUS_TP << 8))
-                dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
+                pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
 
         pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
         pci_flr_wait(dev);
@@ -5151,12 +5222,12 @@ void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
                 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
                                               sizeof(long), GFP_KERNEL);
         if (!dev->dma_alias_mask) {
-                dev_warn(&dev->dev, "Unable to allocate DMA alias mask\n");
+                pci_warn(dev, "Unable to allocate DMA alias mask\n");
                 return;
         }
 
         set_bit(devfn, dev->dma_alias_mask);
-        dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n",
+        pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
                  PCI_SLOT(devfn), PCI_FUNC(devfn));
 }
 
@@ -5305,7 +5376,7 @@ static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
                 return;
 
         if (r->flags & IORESOURCE_PCI_FIXED) {
-                dev_info(&dev->dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
+                pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
                          bar, r, (unsigned long long)align);
                 return;
         }
@@ -5342,7 +5413,7 @@ static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
          * devices and we use the second.
          */
 
-        dev_info(&dev->dev, "BAR%d %pR: requesting alignment to %#llx\n",
+        pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
                  bar, r, (unsigned long long)align);
 
         if (resize) {
@@ -5388,13 +5459,11 @@ void pci_reassigndev_resource_alignment(struct pci_dev *dev)
 
         if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
             (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
-                dev_warn(&dev->dev,
-                        "Can't reassign resources to host bridge.\n");
+                pci_warn(dev, "Can't reassign resources to host bridge\n");
                 return;
         }
 
-        dev_info(&dev->dev,
-                "Disabling memory decoding and releasing memory resources.\n");
+        pci_info(dev, "Disabling memory decoding and releasing memory resources\n");
         pci_read_config_word(dev, PCI_COMMAND, &command);
         command &= ~PCI_COMMAND_MEMORY;
         pci_write_config_word(dev, PCI_COMMAND, command);
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index f6b58b32a67c..fcd81911b127 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -38,21 +38,21 @@ int pci_probe_reset_function(struct pci_dev *dev);
  * struct pci_platform_pm_ops - Firmware PM callbacks
  *
  * @is_manageable: returns 'true' if given device is power manageable by the
- *                 platform firmware
+ *                 platform firmware
  *
  * @set_state: invokes the platform firmware to set the device's power state
  *
  * @get_state: queries the platform firmware for a device's current power state
  *
  * @choose_state: returns PCI power state of given device preferred by the
- *                platform; to be used during system-wide transitions from a
- *                sleeping state to the working state and vice versa
+ *                platform; to be used during system-wide transitions from a
+ *                sleeping state to the working state and vice versa
  *
  * @set_wakeup: enables/disables wakeup capability for the device
  *
  * @need_resume: returns 'true' if the given device (which is currently
- *              suspended) needs to be resumed to be configured for system
- *              wakeup.
+ *               suspended) needs to be resumed to be configured for system
+ *               wakeup.
  *
  * If given platform is generally capable of power managing PCI devices, all of
  * these callbacks are mandatory.
@@ -112,7 +112,7 @@ struct pci_vpd_ops {
 
 struct pci_vpd {
         const struct pci_vpd_ops *ops;
-        struct bin_attribute *attr; /* descriptor for sysfs VPD entry */
+        struct bin_attribute *attr;     /* Descriptor for sysfs VPD entry */
         struct mutex    lock;
         unsigned int    len;
         u16             flag;
@@ -199,7 +199,7 @@ extern const struct attribute_group *pci_bus_groups[];
 
 /**
  * pci_match_one_device - Tell if a PCI device structure has a matching
- *                        PCI device id structure
+ *                        PCI device id structure
  * @id: single PCI device id structure to match
  * @dev: the PCI device structure to match against
  *
@@ -231,7 +231,7 @@ struct pci_slot_attribute {
 
 enum pci_bar_type {
         pci_bar_unknown,        /* Standard PCI BAR probe */
-        pci_bar_io,             /* An io port BAR */
+        pci_bar_io,             /* An I/O port BAR */
         pci_bar_mem32,          /* A 32-bit memory BAR */
         pci_bar_mem64,          /* A 64-bit memory BAR */
 };
@@ -255,24 +255,24 @@ void pci_disable_bridge_window(struct pci_dev *dev);
 
 /* Single Root I/O Virtualization */
 struct pci_sriov {
-        int pos;                /* capability position */
-        int nres;               /* number of resources */
-        u32 cap;                /* SR-IOV Capabilities */
-        u16 ctrl;               /* SR-IOV Control */
-        u16 total_VFs;          /* total VFs associated with the PF */
-        u16 initial_VFs;        /* initial VFs associated with the PF */
-        u16 num_VFs;            /* number of VFs available */
-        u16 offset;             /* first VF Routing ID offset */
-        u16 stride;             /* following VF stride */
-        u16 vf_device;          /* VF device ID */
-        u32 pgsz;               /* page size for BAR alignment */
-        u8 link;                /* Function Dependency Link */
-        u8 max_VF_buses;        /* max buses consumed by VFs */
-        u16 driver_max_VFs;     /* max num VFs driver supports */
-        struct pci_dev *dev;    /* lowest numbered PF */
-        struct pci_dev *self;   /* this PF */
-        resource_size_t barsz[PCI_SRIOV_NUM_BARS];      /* VF BAR size */
-        bool drivers_autoprobe; /* auto probing of VFs by driver */
+        int             pos;            /* Capability position */
+        int             nres;           /* Number of resources */
+        u32             cap;            /* SR-IOV Capabilities */
+        u16             ctrl;           /* SR-IOV Control */
+        u16             total_VFs;      /* Total VFs associated with the PF */
+        u16             initial_VFs;    /* Initial VFs associated with the PF */
+        u16             num_VFs;        /* Number of VFs available */
+        u16             offset;         /* First VF Routing ID offset */
+        u16             stride;         /* Following VF stride */
+        u16             vf_device;      /* VF device ID */
+        u32             pgsz;           /* Page size for BAR alignment */
+        u8              link;           /* Function Dependency Link */
+        u8              max_VF_buses;   /* Max buses consumed by VFs */
+        u16             driver_max_VFs; /* Max num VFs driver supports */
+        struct pci_dev  *dev;           /* Lowest numbered PF */
+        struct pci_dev  *self;          /* This PF */
+        resource_size_t barsz[PCI_SRIOV_NUM_BARS];      /* VF BAR size */
+        bool            drivers_autoprobe; /* Auto probing of VFs by driver */
 };
 
 /* pci_dev priv_flags */
@@ -335,13 +335,33 @@ static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
         if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
                 return pci_sriov_resource_alignment(dev, resno);
 #endif
-        if (dev->class >> 8  == PCI_CLASS_BRIDGE_CARDBUS)
+        if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
                 return pci_cardbus_resource_alignment(res);
         return resource_alignment(res);
 }
 
 void pci_enable_acs(struct pci_dev *dev);
 
+#ifdef CONFIG_PCIEASPM
+void pcie_aspm_init_link_state(struct pci_dev *pdev);
+void pcie_aspm_exit_link_state(struct pci_dev *pdev);
+void pcie_aspm_pm_state_change(struct pci_dev *pdev);
+void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
+#else
+static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
+static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
+static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
+static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
+#endif
+
+#ifdef CONFIG_PCIEASPM_DEBUG
+void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
+void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
+#else
+static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { }
+static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { }
+#endif
+
 #ifdef CONFIG_PCIE_PTM
 void pci_ptm_init(struct pci_dev *dev);
 #else
diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig
index 6d75a2eb6ecb..b12e28b3d8f9 100644
--- a/drivers/pci/pcie/Kconfig
+++ b/drivers/pci/pcie/Kconfig
@@ -93,7 +93,7 @@ config PCIE_PME
 
 config PCIE_DPC
         bool "PCIe Downstream Port Containment support"
-        depends on PCIEPORTBUS
+        depends on PCIEPORTBUS && PCIEAER
         default n
         help
           This enables PCI Express Downstream Port Containment (DPC)
diff --git a/drivers/pci/pcie/aer/aer_inject.c b/drivers/pci/pcie/aer/aer_inject.c
index 7e2235484dab..25e1feb962c5 100644
--- a/drivers/pci/pcie/aer/aer_inject.c
+++ b/drivers/pci/pcie/aer/aer_inject.c
@@ -339,14 +339,14 @@ static int aer_inject(struct aer_error_inj *einj)
                 return -ENODEV;
         rpdev = pcie_find_root_port(dev);
         if (!rpdev) {
-                dev_err(&dev->dev, "aer_inject: Root port not found\n");
+                pci_err(dev, "aer_inject: Root port not found\n");
                 ret = -ENODEV;
                 goto out_put;
         }
 
         pos_cap_err = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
         if (!pos_cap_err) {
-                dev_err(&dev->dev, "aer_inject: Device doesn't support AER\n");
+                pci_err(dev, "aer_inject: Device doesn't support AER\n");
                 ret = -EPROTONOSUPPORT;
                 goto out_put;
         }
@@ -357,8 +357,7 @@ static int aer_inject(struct aer_error_inj *einj)
 
         rp_pos_cap_err = pci_find_ext_capability(rpdev, PCI_EXT_CAP_ID_ERR);
         if (!rp_pos_cap_err) {
-                dev_err(&rpdev->dev,
-                        "aer_inject: Root port doesn't support AER\n");
+                pci_err(rpdev, "aer_inject: Root port doesn't support AER\n");
                 ret = -EPROTONOSUPPORT;
                 goto out_put;
         }
@@ -406,16 +405,14 @@ static int aer_inject(struct aer_error_inj *einj)
         if (!aer_mask_override && einj->cor_status &&
             !(einj->cor_status & ~cor_mask)) {
                 ret = -EINVAL;
-                dev_warn(&dev->dev,
-                         "aer_inject: The correctable error(s) is masked by device\n");
+                pci_warn(dev, "aer_inject: The correctable error(s) is masked by device\n");
                 spin_unlock_irqrestore(&inject_lock, flags);
                 goto out_put;
         }
         if (!aer_mask_override && einj->uncor_status &&
             !(einj->uncor_status & ~uncor_mask)) {
                 ret = -EINVAL;
-                dev_warn(&dev->dev,
-                         "aer_inject: The uncorrectable error(s) is masked by device\n");
+                pci_warn(dev, "aer_inject: The uncorrectable error(s) is masked by device\n");
                 spin_unlock_irqrestore(&inject_lock, flags);
                 goto out_put;
         }
@@ -478,7 +475,7 @@ static int aer_inject(struct aer_error_inj *einj)
                          einj->cor_status, einj->uncor_status, pci_name(dev));
                 aer_irq(-1, edev);
         } else {
-                dev_err(&rpdev->dev, "aer_inject: AER device not found\n");
+                pci_err(rpdev, "aer_inject: AER device not found\n");
                 ret = -ENODEV;
         }
 out_put:
diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c
index 3f8c58f897f0..da8331f5684d 100644
--- a/drivers/pci/pcie/aer/aerdrv.c
+++ b/drivers/pci/pcie/aer/aerdrv.c
@@ -323,7 +323,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
         pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, reg32);
 
         pci_reset_bridge_secondary_bus(dev);
-        dev_printk(KERN_DEBUG, &dev->dev, "Root Port link has been reset\n");
+        pci_printk(KERN_DEBUG, dev, "Root Port link has been reset\n");
 
         /* Clear Root Error Status */
         pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &reg32);
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c
index df45383c35f7..109d43fab40e 100644
--- a/drivers/pci/pcie/aer/aerdrv_core.c
+++ b/drivers/pci/pcie/aer/aerdrv_core.c
@@ -223,9 +223,8 @@ static bool find_source_device(struct pci_dev *parent,
         pci_walk_bus(parent->subordinate, find_device_iter, e_info);
 
         if (!e_info->error_dev_num) {
-                dev_printk(KERN_DEBUG, &parent->dev,
-                                "can't find device of ID%04x\n",
-                                e_info->id);
+                pci_printk(KERN_DEBUG, parent, "can't find device of ID%04x\n",
+                           e_info->id);
                 return false;
         }
         return true;
@@ -253,7 +252,7 @@ static int report_error_detected(struct pci_dev *dev, void *data)
                          * of a driver for this device is unaware of
                          * its hw state.
                          */
-                        dev_printk(KERN_DEBUG, &dev->dev, "device has %s\n",
+                        pci_printk(KERN_DEBUG, dev, "device has %s\n",
                                    dev->driver ?
                                    "no AER-aware driver" : "no driver");
                 }
@@ -361,7 +360,7 @@ static pci_ers_result_t broadcast_error_message(struct pci_dev *dev,
 {
         struct aer_broadcast_data result_data;
 
-        dev_printk(KERN_DEBUG, &dev->dev, "broadcast %s message\n", error_mesg);
+        pci_printk(KERN_DEBUG, dev, "broadcast %s message\n", error_mesg);
         result_data.state = state;
         if (cb == report_error_detected)
                 result_data.result = PCI_ERS_RESULT_CAN_RECOVER;
@@ -410,7 +409,7 @@ static pci_ers_result_t broadcast_error_message(struct pci_dev *dev,
 static pci_ers_result_t default_reset_link(struct pci_dev *dev)
 {
         pci_reset_bridge_secondary_bus(dev);
-        dev_printk(KERN_DEBUG, &dev->dev, "downstream link has been reset\n");
+        pci_printk(KERN_DEBUG, dev, "downstream link has been reset\n");
         return PCI_ERS_RESULT_RECOVERED;
 }
 
@@ -462,15 +461,13 @@ static pci_ers_result_t reset_link(struct pci_dev *dev)
         } else if (udev->has_secondary_link) {
                 status = default_reset_link(udev);
         } else {
-                dev_printk(KERN_DEBUG, &dev->dev,
-                        "no link-reset support at upstream device %s\n",
+                pci_printk(KERN_DEBUG, dev, "no link-reset support at upstream device %s\n",
                         pci_name(udev));
                 return PCI_ERS_RESULT_DISCONNECT;
         }
 
         if (status != PCI_ERS_RESULT_RECOVERED) {
-                dev_printk(KERN_DEBUG, &dev->dev,
-                        "link reset at upstream device %s failed\n",
+                pci_printk(KERN_DEBUG, dev, "link reset at upstream device %s failed\n",
                         pci_name(udev));
                 return PCI_ERS_RESULT_DISCONNECT;
         }
@@ -534,12 +531,12 @@ static void do_recovery(struct pci_dev *dev, int severity)
                                 "resume",
                                 report_resume);
 
-        dev_info(&dev->dev, "AER: Device recovery successful\n");
+        pci_info(dev, "AER: Device recovery successful\n");
         return;
 
 failed:
         /* TODO: Should kernel panic here? */
-        dev_info(&dev->dev, "AER: Device recovery failed\n");
+        pci_info(dev, "AER: Device recovery failed\n");
 }
 
 /**
@@ -630,7 +627,8 @@ static void aer_recover_work_func(struct work_struct *work)
                         continue;
                 }
                 cper_print_aer(pdev, entry.severity, entry.regs);
-                do_recovery(pdev, entry.severity);
+                if (entry.severity != AER_CORRECTABLE)
+                        do_recovery(pdev, entry.severity);
                 pci_dev_put(pdev);
         }
 }
@@ -657,7 +655,7 @@ static int get_device_error_info(struct pci_dev *dev, struct aer_err_info *info)
 
         /* The device might not support AER */
         if (!pos)
-                return 1;
+                return 0;
 
         if (info->severity == AER_CORRECTABLE) {
                 pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS,
diff --git a/drivers/pci/pcie/aer/aerdrv_errprint.c b/drivers/pci/pcie/aer/aerdrv_errprint.c
index 1f0456f802af..6a352e638699 100644
--- a/drivers/pci/pcie/aer/aerdrv_errprint.c
+++ b/drivers/pci/pcie/aer/aerdrv_errprint.c
@@ -129,7 +129,7 @@ static const char *aer_agent_string[] = {
 static void __print_tlp_header(struct pci_dev *dev,
                                struct aer_header_log_regs *t)
 {
-        dev_err(&dev->dev, "  TLP Header: %08x %08x %08x %08x\n",
+        pci_err(dev, "  TLP Header: %08x %08x %08x %08x\n",
                 t->dw0, t->dw1, t->dw2, t->dw3);
 }
 
@@ -152,10 +152,10 @@ static void __aer_print_error(struct pci_dev *dev,
                                 aer_uncorrectable_error_string[i] : NULL;
 
                 if (errmsg)
-                        dev_err(&dev->dev, "   [%2d] %-22s%s\n", i, errmsg,
+                        pci_err(dev, "   [%2d] %-22s%s\n", i, errmsg,
                                 info->first_error == i ? " (First)" : "");
                 else
-                        dev_err(&dev->dev, "   [%2d] Unknown Error Bit%s\n",
+                        pci_err(dev, "   [%2d] Unknown Error Bit%s\n",
                                 i, info->first_error == i ? " (First)" : "");
         }
 }
@@ -166,7 +166,7 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
         int id = ((dev->bus->number << 8) | dev->devfn);
 
         if (!info->status) {
-                dev_err(&dev->dev, "PCIe Bus Error: severity=%s, type=Unaccessible, id=%04x(Unregistered Agent ID)\n",
+                pci_err(dev, "PCIe Bus Error: severity=%s, type=Unaccessible, id=%04x(Unregistered Agent ID)\n",
                         aer_error_severity_string[info->severity], id);
                 goto out;
         }
@@ -174,11 +174,11 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
         layer = AER_GET_LAYER_ERROR(info->severity, info->status);
         agent = AER_GET_AGENT(info->severity, info->status);
 
-        dev_err(&dev->dev, "PCIe Bus Error: severity=%s, type=%s, id=%04x(%s)\n",
+        pci_err(dev, "PCIe Bus Error: severity=%s, type=%s, id=%04x(%s)\n",
                 aer_error_severity_string[info->severity],
                 aer_error_layer[layer], id, aer_agent_string[agent]);
 
-        dev_err(&dev->dev, "  device [%04x:%04x] error status/mask=%08x/%08x\n",
+        pci_err(dev, "  device [%04x:%04x] error status/mask=%08x/%08x\n",
                 dev->vendor, dev->device,
                 info->status, info->mask);
 
@@ -189,7 +189,7 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info)
 
 out:
         if (info->id && info->error_dev_num > 1 && info->id == id)
-                dev_err(&dev->dev, "  Error of this Agent(%04x) is reported first\n", id);
+                pci_err(dev, "  Error of this Agent(%04x) is reported first\n", id);
 
         trace_aer_event(dev_name(&dev->dev), (info->status & ~info->mask),
                         info->severity);
@@ -197,7 +197,7 @@ out:
 
 void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info)
 {
-        dev_info(&dev->dev, "AER: %s%s error received: id=%04x\n",
+        pci_info(dev, "AER: %s%s error received: id=%04x\n",
                 info->multi_error_valid ? "Multiple " : "",
                 aer_error_severity_string[info->severity], info->id);
 }
@@ -239,13 +239,13 @@ void cper_print_aer(struct pci_dev *dev, int aer_severity,
         layer = AER_GET_LAYER_ERROR(aer_severity, status);
         agent = AER_GET_AGENT(aer_severity, status);
 
-        dev_err(&dev->dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask);
+        pci_err(dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status, mask);
         cper_print_bits("", status, status_strs, status_strs_size);
-        dev_err(&dev->dev, "aer_layer=%s, aer_agent=%s\n",
+        pci_err(dev, "aer_layer=%s, aer_agent=%s\n",
                 aer_error_layer[layer], aer_agent_string[agent]);
 
         if (aer_severity != AER_CORRECTABLE)
-                dev_err(&dev->dev, "aer_uncor_severity: 0x%08x\n",
+                pci_err(dev, "aer_uncor_severity: 0x%08x\n",
                         aer->uncor_severity);
 
         if (tlp_header_valid)
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 9783e10da3a9..57feef2ecfe7 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -43,18 +43,6 @@
 #define ASPM_STATE_ALL          (ASPM_STATE_L0S | ASPM_STATE_L1 |       \
                                  ASPM_STATE_L1SS)
 
-/*
- * When L1 substates are enabled, the LTR L1.2 threshold is a timing parameter
- * that decides whether L1.1 or L1.2 is entered (Refer PCIe spec for details).
- * Not sure is there is a way to "calculate" this on the fly, but maybe we
- * could turn it into a parameter in future.  This value has been taken from
- * the following files from Intel's coreboot (which is the only code I found
- * to have used this):
- * https://www.coreboot.org/pipermail/coreboot-gerrit/2015-March/021134.html
- * https://review.coreboot.org/#/c/8832/
- */
-#define LTR_L1_2_THRESHOLD_BITS ((1 << 21) | (1 << 23) | (1 << 30))
-
 struct aspm_latency {
         u32 l0s;                        /* L0s latency (nsec) */
         u32 l1;                         /* L1 latency (nsec) */
@@ -278,7 +266,7 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
                 return;
 
         /* Training failed. Restore common clock configurations */
-        dev_err(&parent->dev, "ASPM: Could not configure common clock\n");
+        pci_err(parent, "ASPM: Could not configure common clock\n");
         list_for_each_entry(child, &linkbus->devices, bus_list)
                 pcie_capability_write_word(child, PCI_EXP_LNKCTL,
                                            child_reg[PCI_FUNC(child->devfn)]);
@@ -328,11 +316,36 @@ static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
         case 2:
                 return val * 100;
         }
-        dev_err(&pdev->dev, "%s: Invalid T_PwrOn scale: %u\n",
-                __func__, scale);
+        pci_err(pdev, "%s: Invalid T_PwrOn scale: %u\n", __func__, scale);
         return 0;
 }
 
+static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
+{
+        u64 threshold_ns = threshold_us * 1000;
+
+        /* See PCIe r3.1, sec 7.33.3 and sec 6.18 */
+        if (threshold_ns < 32) {
+                *scale = 0;
+                *value = threshold_ns;
+        } else if (threshold_ns < 1024) {
+                *scale = 1;
+                *value = threshold_ns >> 5;
+        } else if (threshold_ns < 32768) {
+                *scale = 2;
+                *value = threshold_ns >> 10;
+        } else if (threshold_ns < 1048576) {
+                *scale = 3;
+                *value = threshold_ns >> 15;
+        } else if (threshold_ns < 33554432) {
+                *scale = 4;
+                *value = threshold_ns >> 20;
+        } else {
+                *scale = 5;
+                *value = threshold_ns >> 25;
+        }
+}
+
 struct aspm_register_info {
         u32 support:2;
         u32 enabled:2;
@@ -443,6 +456,7 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
                                 struct aspm_register_info *dwreg)
 {
         u32 val1, val2, scale1, scale2;
+        u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
 
         link->l1ss.up_cap_ptr = upreg->l1ss_cap_ptr;
         link->l1ss.dw_cap_ptr = dwreg->l1ss_cap_ptr;
@@ -454,16 +468,7 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
         /* Choose the greater of the two Port Common_Mode_Restore_Times */
         val1 = (upreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
         val2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
-        if (val1 > val2)
-                link->l1ss.ctl1 |= val1 << 8;
-        else
-                link->l1ss.ctl1 |= val2 << 8;
-
-        /*
-         * We currently use LTR L1.2 threshold to be fixed constant picked from
-         * Intel's coreboot.
-         */
-        link->l1ss.ctl1 |= LTR_L1_2_THRESHOLD_BITS;
+        t_common_mode = max(val1, val2);
 
         /* Choose the greater of the two Port T_POWER_ON times */
         val1   = (upreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
@@ -472,10 +477,27 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
         scale2 = (dwreg->l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
 
         if (calc_l1ss_pwron(link->pdev, scale1, val1) >
-            calc_l1ss_pwron(link->downstream, scale2, val2))
+            calc_l1ss_pwron(link->downstream, scale2, val2)) {
                 link->l1ss.ctl2 |= scale1 | (val1 << 3);
-        else
+                t_power_on = calc_l1ss_pwron(link->pdev, scale1, val1);
+        } else {
                 link->l1ss.ctl2 |= scale2 | (val2 << 3);
+                t_power_on = calc_l1ss_pwron(link->downstream, scale2, val2);
+        }
+
+        /*
+         * Set LTR_L1.2_THRESHOLD to the time required to transition the
+         * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
+         * downstream devices report (via LTR) that they can tolerate at
+         * least that much latency.
+         *
+         * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and
+         * Table 5-11.  T(POWER_OFF) is at most 2us and T(L1.2) is at
+         * least 4us.
+         */
+        l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
+        encode_l12_threshold(l1_2_threshold, &scale, &value);
+        link->l1ss.ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
 }
 
 static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
@@ -786,7 +808,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
                  */
                 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
                 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
-                        dev_info(&child->dev, "disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'\n");
+                        pci_info(child, "disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'\n");
                         return -EINVAL;
                 }
         }
@@ -1027,7 +1049,7 @@ static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
          * ignored in this situation.
          */
         if (aspm_disabled) {
-                dev_warn(&pdev->dev, "can't disable ASPM; OS doesn't have ASPM control\n");
+                pci_warn(pdev, "can't disable ASPM; OS doesn't have ASPM control\n");
                 return;
         }
 
diff --git a/drivers/pci/pcie/pcie-dpc.c b/drivers/pci/pcie/pcie-dpc.c
index d1fb5cf9379e..38e40c6c576f 100644
--- a/drivers/pci/pcie/pcie-dpc.c
+++ b/drivers/pci/pcie/pcie-dpc.c
@@ -12,34 +12,15 @@
 #include <linux/pci.h>
 #include <linux/pcieport_if.h>
 #include "../pci.h"
-
-struct rp_pio_header_log_regs {
-        u32 dw0;
-        u32 dw1;
-        u32 dw2;
-        u32 dw3;
-};
-
-struct dpc_rp_pio_regs {
-        u32 status;
-        u32 mask;
-        u32 severity;
-        u32 syserror;
-        u32 exception;
-
-        struct rp_pio_header_log_regs header_log;
-        u32 impspec_log;
-        u32 tlp_prefix_log[4];
-        u32 log_size;
-        u16 first_error;
-};
+#include "aer/aerdrv.h"
 
 struct dpc_dev {
         struct pcie_device      *dev;
         struct work_struct      work;
-        int                     cap_pos;
-        bool                    rp;
+        u16                     cap_pos;
+        bool                    rp_extensions;
         u32                     rp_pio_status;
+        u8                      rp_log_size;
 };
 
 static const char * const rp_pio_error_string[] = {
@@ -69,13 +50,13 @@ static int dpc_wait_rp_inactive(struct dpc_dev *dpc)
         unsigned long timeout = jiffies + HZ;
         struct pci_dev *pdev = dpc->dev->port;
         struct device *dev = &dpc->dev->device;
-        u16 status;
+        u16 cap = dpc->cap_pos, status;
 
-        pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
+        pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
         while (status & PCI_EXP_DPC_RP_BUSY &&
                                         !time_after(jiffies, timeout)) {
                 msleep(10);
-                pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
+                pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
         }
         if (status & PCI_EXP_DPC_RP_BUSY) {
                 dev_warn(dev, "DPC root port still busy\n");
@@ -101,11 +82,12 @@ static void dpc_wait_link_inactive(struct dpc_dev *dpc)
                 dev_warn(dev, "Link state not disabled for DPC event\n");
 }
 
-static void interrupt_event_handler(struct work_struct *work)
+static void dpc_work(struct work_struct *work)
 {
         struct dpc_dev *dpc = container_of(work, struct dpc_dev, work);
         struct pci_dev *dev, *temp, *pdev = dpc->dev->port;
         struct pci_bus *parent = pdev->subordinate;
+        u16 cap = dpc->cap_pos, ctl;
 
         pci_lock_rescan_remove();
         list_for_each_entry_safe_reverse(dev, temp, &parent->devices,
@@ -121,159 +103,127 @@ static void interrupt_event_handler(struct work_struct *work)
         pci_unlock_rescan_remove();
 
         dpc_wait_link_inactive(dpc);
-        if (dpc->rp && dpc_wait_rp_inactive(dpc))
+        if (dpc->rp_extensions && dpc_wait_rp_inactive(dpc))
                 return;
-        if (dpc->rp && dpc->rp_pio_status) {
-                pci_write_config_dword(pdev,
-                                      dpc->cap_pos + PCI_EXP_DPC_RP_PIO_STATUS,
-                                      dpc->rp_pio_status);
+        if (dpc->rp_extensions && dpc->rp_pio_status) {
+                pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS,
+                                       dpc->rp_pio_status);
                 dpc->rp_pio_status = 0;
         }
 
-        pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS,
+        pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
                 PCI_EXP_DPC_STATUS_TRIGGER | PCI_EXP_DPC_STATUS_INTERRUPT);
-}
 
-static void dpc_rp_pio_print_tlp_header(struct device *dev,
-                                        struct rp_pio_header_log_regs *t)
-{
-        dev_err(dev, "TLP Header: %#010x %#010x %#010x %#010x\n",
-                t->dw0, t->dw1, t->dw2, t->dw3);
+        pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl);
+        pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL,
+                              ctl | PCI_EXP_DPC_CTL_INT_EN);
 }
 
-static void dpc_rp_pio_print_error(struct dpc_dev *dpc,
-                                   struct dpc_rp_pio_regs *rp_pio)
+static void dpc_process_rp_pio_error(struct dpc_dev *dpc)
 {
         struct device *dev = &dpc->dev->device;
+        struct pci_dev *pdev = dpc->dev->port;
+        u16 cap = dpc->cap_pos, dpc_status, first_error;
+        u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix;
         int i;
-        u32 status;
 
+        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
+        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);
         dev_err(dev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
-                rp_pio->status, rp_pio->mask);
+                status, mask);
+
+        dpc->rp_pio_status = status;
 
+        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);
+        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);
+        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);
         dev_err(dev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
-                rp_pio->severity, rp_pio->syserror, rp_pio->exception);
+                sev, syserr, exc);
 
-        status = (rp_pio->status & ~rp_pio->mask);
+        /* Get First Error Pointer */
+        pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);
+        first_error = (dpc_status & 0x1f00) >> 8;
 
+        status &= ~mask;
         for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
-                if (!(status & (1 << i)))
-                        continue;
-
-                dev_err(dev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
-                        rp_pio->first_error == i ? " (First)" : "");
+                if (status & (1 << i))
+                        dev_err(dev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
+                                first_error == i ? " (First)" : "");
         }
 
-        dpc_rp_pio_print_tlp_header(dev, &rp_pio->header_log);
-        if (rp_pio->log_size == 4)
+        if (dpc->rp_log_size < 4)
                 return;
-        dev_err(dev, "RP PIO ImpSpec Log %#010x\n", rp_pio->impspec_log);
+        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
+                              &dw0);
+        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
+                              &dw1);
+        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
+                              &dw2);
+        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
+                              &dw3);
+        dev_err(dev, "TLP Header: %#010x %#010x %#010x %#010x\n",
+                dw0, dw1, dw2, dw3);
 
-        for (i = 0; i < rp_pio->log_size - 5; i++)
-                dev_err(dev, "TLP Prefix Header: dw%d, %#010x\n", i,
-                        rp_pio->tlp_prefix_log[i]);
+        if (dpc->rp_log_size < 5)
+                return;
+        pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);
+        dev_err(dev, "RP PIO ImpSpec Log %#010x\n", log);
+
+        for (i = 0; i < dpc->rp_log_size - 5; i++) {
+                pci_read_config_dword(pdev,
+                        cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix);
+                dev_err(dev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix);
+        }
 }
 
-static void dpc_rp_pio_get_info(struct dpc_dev *dpc,
-                                struct dpc_rp_pio_regs *rp_pio)
+static irqreturn_t dpc_irq(int irq, void *context)
 {
+        struct dpc_dev *dpc = (struct dpc_dev *)context;
         struct pci_dev *pdev = dpc->dev->port;
         struct device *dev = &dpc->dev->device;
-        int i;
-        u16 cap;
-        u16 status;
-
-        pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_STATUS,
-                              &rp_pio->status);
-        pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_MASK,
-                              &rp_pio->mask);
-
-        pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_SEVERITY,
-                              &rp_pio->severity);
-        pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_SYSERROR,
-                              &rp_pio->syserror);
-        pci_read_config_dword(pdev, dpc->cap_pos + PCI_EXP_DPC_RP_PIO_EXCEPTION,
-                              &rp_pio->exception);
+        u16 cap = dpc->cap_pos, ctl, status, source, reason, ext_reason;
 
-        /* Get First Error Pointer */
-        pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
-        rp_pio->first_error = (status & 0x1f00) >> 8;
+        pci_read_config_word(pdev, cap + PCI_EXP_DPC_CTL, &ctl);
 
-        pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap);
-        rp_pio->log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
-        if (rp_pio->log_size < 4 || rp_pio->log_size > 9) {
-                dev_err(dev, "RP PIO log size %u is invalid\n",
-                        rp_pio->log_size);
-                return;
-        }
-
-        pci_read_config_dword(pdev,
-                              dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
-                              &rp_pio->header_log.dw0);
-        pci_read_config_dword(pdev,
-                              dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
-                              &rp_pio->header_log.dw1);
-        pci_read_config_dword(pdev,
-                              dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
-                              &rp_pio->header_log.dw2);
-        pci_read_config_dword(pdev,
-                              dpc->cap_pos + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
-                              &rp_pio->header_log.dw3);
-        if (rp_pio->log_size == 4)
-                return;
-
-        pci_read_config_dword(pdev,
-                              dpc->cap_pos + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG,
-                              &rp_pio->impspec_log);
-        for (i = 0; i < rp_pio->log_size - 5; i++)
-                pci_read_config_dword(pdev,
-                        dpc->cap_pos + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG,
-                        &rp_pio->tlp_prefix_log[i]);
-}
+        if (!(ctl & PCI_EXP_DPC_CTL_INT_EN) || ctl == (u16)(~0))
+                return IRQ_NONE;
 
-static void dpc_process_rp_pio_error(struct dpc_dev *dpc)
-{
-        struct dpc_rp_pio_regs rp_pio_regs;
+        pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
 
-        dpc_rp_pio_get_info(dpc, &rp_pio_regs);
-        dpc_rp_pio_print_error(dpc, &rp_pio_regs);
+        if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT))
+                return IRQ_NONE;
 
-        dpc->rp_pio_status = rp_pio_regs.status;
-}
+        if (!(status & PCI_EXP_DPC_STATUS_TRIGGER)) {
+                pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
+                                      PCI_EXP_DPC_STATUS_INTERRUPT);
+                return IRQ_HANDLED;
+        }
 
-static irqreturn_t dpc_irq(int irq, void *context)
-{
-        struct dpc_dev *dpc = (struct dpc_dev *)context;
-        struct pci_dev *pdev = dpc->dev->port;
-        struct device *dev = &dpc->dev->device;
-        u16 status, source;
+        pci_write_config_word(pdev, cap + PCI_EXP_DPC_CTL,
+                              ctl & ~PCI_EXP_DPC_CTL_INT_EN);
 
-        pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
-        pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_SOURCE_ID,
+        pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID,
                              &source);
-        if (!status || status == (u16)(~0))
-                return IRQ_NONE;
 
         dev_info(dev, "DPC containment event, status:%#06x source:%#06x\n",
                 status, source);
 
-        if (status & PCI_EXP_DPC_STATUS_TRIGGER) {
-                u16 reason = (status >> 1) & 0x3;
-                u16 ext_reason = (status >> 5) & 0x3;
-
-                dev_warn(dev, "DPC %s detected, remove downstream devices\n",
-                         (reason == 0) ? "unmasked uncorrectable error" :
-                         (reason == 1) ? "ERR_NONFATAL" :
-                         (reason == 2) ? "ERR_FATAL" :
-                         (ext_reason == 0) ? "RP PIO error" :
-                         (ext_reason == 1) ? "software trigger" :
-                                             "reserved error");
-                /* show RP PIO error detail information */
-                if (reason == 3 && ext_reason == 0)
-                        dpc_process_rp_pio_error(dpc);
-
-                schedule_work(&dpc->work);
-        }
+        reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1;
+        ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5;
+
+        dev_warn(dev, "DPC %s detected, remove downstream devices\n",
+                 (reason == 0) ? "unmasked uncorrectable error" :
+                 (reason == 1) ? "ERR_NONFATAL" :
+                 (reason == 2) ? "ERR_FATAL" :
+                 (ext_reason == 0) ? "RP PIO error" :
+                 (ext_reason == 1) ? "software trigger" :
+                                     "reserved error");
+        /* show RP PIO error detail information */
+        if (dpc->rp_extensions && reason == 3 && ext_reason == 0)
+                dpc_process_rp_pio_error(dpc);
+
+        schedule_work(&dpc->work);
+
         return IRQ_HANDLED;
 }
 
@@ -286,13 +236,16 @@ static int dpc_probe(struct pcie_device *dev)
         int status;
         u16 ctl, cap;
 
+        if (pcie_aer_get_firmware_first(pdev))
+                return -ENOTSUPP;
+
         dpc = devm_kzalloc(device, sizeof(*dpc), GFP_KERNEL);
         if (!dpc)
                 return -ENOMEM;
 
         dpc->cap_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
         dpc->dev = dev;
-        INIT_WORK(&dpc->work, interrupt_event_handler);
+        INIT_WORK(&dpc->work, dpc_work);
         set_service_data(dev, dpc);
 
         status = devm_request_irq(device, dev->irq, dpc_irq, IRQF_SHARED,
@@ -306,15 +259,23 @@ static int dpc_probe(struct pcie_device *dev)
         pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap);
         pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl);
 
-        dpc->rp = (cap & PCI_EXP_DPC_CAP_RP_EXT);
+        dpc->rp_extensions = (cap & PCI_EXP_DPC_CAP_RP_EXT);
+        if (dpc->rp_extensions) {
+                dpc->rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
+                if (dpc->rp_log_size < 4 || dpc->rp_log_size > 9) {
+                        dev_err(device, "RP PIO log size %u is invalid\n",
+                                dpc->rp_log_size);
+                        dpc->rp_log_size = 0;
+                }
+        }
 
         ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_NONFATAL | PCI_EXP_DPC_CTL_INT_EN;
         pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
 
         dev_info(device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
-                cap & 0xf, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
+                cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
                 FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
-                FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), (cap >> 8) & 0xf,
+                FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), dpc->rp_log_size,
                 FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE));
         return status;
 }
diff --git a/drivers/pci/pcie/pme.c b/drivers/pci/pcie/pme.c
index 55bdef4fb558..5480f54f7612 100644
--- a/drivers/pci/pcie/pme.c
+++ b/drivers/pci/pcie/pme.c
@@ -195,14 +195,14 @@ static void pcie_pme_handle_request(struct pci_dev *port, u16 req_id)
                  * assuming that the PME was reported by a PCIe-PCI bridge that
                  * used devfn different from zero.
                  */
-                dev_dbg(&port->dev, "PME interrupt generated for non-existent device %02x:%02x.%d\n",
+                pci_dbg(port, "PME interrupt generated for non-existent device %02x:%02x.%d\n",
                         busnr, PCI_SLOT(devfn), PCI_FUNC(devfn));
                 found = pcie_pme_from_pci_bridge(bus, 0);
         }
 
  out:
         if (!found)
-                dev_dbg(&port->dev, "Spurious native PME interrupt!\n");
+                pci_dbg(port, "Spurious native PME interrupt!\n");
 }
 
 /**
@@ -342,7 +342,7 @@ static int pcie_pme_probe(struct pcie_device *srv)
                 return ret;
         }
 
-        dev_info(&port->dev, "Signaling PME with IRQ %d\n", srv->irq);
+        pci_info(port, "Signaling PME with IRQ %d\n", srv->irq);
 
         pcie_pme_mark_devices(port);
         pcie_pme_interrupt_enable(port, true);
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index a59210350c44..ef3bad4ad010 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -216,9 +216,9 @@ static int get_port_device_capability(struct pci_dev *dev)
                 return 0;
 
         cap_mask = PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP
-                        | PCIE_PORT_SERVICE_VC | PCIE_PORT_SERVICE_DPC;
+                        | PCIE_PORT_SERVICE_VC;
         if (pci_aer_available())
-                cap_mask |= PCIE_PORT_SERVICE_AER;
+                cap_mask |= PCIE_PORT_SERVICE_AER | PCIE_PORT_SERVICE_DPC;
 
         if (pcie_ports_auto)
                 pcie_port_platform_notify(dev, &cap_mask);
diff --git a/drivers/pci/pcie/ptm.c b/drivers/pci/pcie/ptm.c
index 1071b8c6208c..98cfa30f3fae 100644
--- a/drivers/pci/pcie/ptm.c
+++ b/drivers/pci/pcie/ptm.c
@@ -25,7 +25,7 @@ static void pci_ptm_info(struct pci_dev *dev)
                          dev->ptm_granularity);
                 break;
         }
-        dev_info(&dev->dev, "PTM enabled%s, %s granularity\n",
+        pci_info(dev, "PTM enabled%s, %s granularity\n",
                  dev->ptm_root ? " (root)" : "", clock_desc);
 }
 
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 3ea2d610d607..ef5377438a1e 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -70,8 +70,8 @@ static int find_anything(struct device *dev, void *data)
 }
 
 /*
- * Some device drivers need know if pci is initiated.
- * Basically, we think pci is not initiated when there
+ * Some device drivers need know if PCI is initiated.
+ * Basically, we think PCI is not initiated when there
  * is no device to be found on the pci_bus_type.
  */
 int no_pci_devices(void)
@@ -117,12 +117,16 @@ static u64 pci_size(u64 base, u64 maxbase, u64 mask)
         if (!size)
                 return 0;
 
-        /* Get the lowest of them to find the decode size, and
-           from that the extent.  */
+        /*
+         * Get the lowest of them to find the decode size, and from that
+         * the extent.
+         */
         size = (size & ~(size-1)) - 1;
 
-        /* base == maxbase can be valid only if the BAR has
-           already been programmed with all 1s.  */
+        /*
+         * base == maxbase can be valid only if the BAR has already been
+         * programmed with all 1s.
+         */
         if (base == maxbase && ((base | size) & mask) != mask)
                 return 0;
 
@@ -165,7 +169,7 @@ static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
 #define PCI_COMMAND_DECODE_ENABLE       (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
 
 /**
- * pci_read_base - read a PCI BAR
+ * pci_read_base - Read a PCI BAR
  * @dev: the PCI device
  * @type: type of the BAR
  * @res: resource buffer to be filled in
@@ -254,7 +258,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
 
         sz64 = pci_size(l64, sz64, mask64);
         if (!sz64) {
-                dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
+                pci_info(dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
                          pos);
                 goto fail;
         }
@@ -265,7 +269,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
                         res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
                         res->start = 0;
                         res->end = 0;
-                        dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
+                        pci_err(dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
                                 pos, (unsigned long long)sz64);
                         goto out;
                 }
@@ -275,7 +279,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
                         res->flags |= IORESOURCE_UNSET;
                         res->start = 0;
                         res->end = sz64;
-                        dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
+                        pci_info(dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
                                  pos, (unsigned long long)l64);
                         goto out;
                 }
@@ -302,7 +306,7 @@ int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
                 res->flags |= IORESOURCE_UNSET;
                 res->start = 0;
                 res->end = region.end - region.start;
-                dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
+                pci_info(dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
                          pos, (unsigned long long)region.start);
         }
 
@@ -313,7 +317,7 @@ fail:
         res->flags = 0;
 out:
         if (res->flags)
-                dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
+                pci_printk(KERN_DEBUG, dev, "reg 0x%x: %pR\n", pos, res);
 
         return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
 }
@@ -376,7 +380,7 @@ static void pci_read_bridge_io(struct pci_bus *child)
                 region.start = base;
                 region.end = limit + io_granularity - 1;
                 pcibios_bus_to_resource(dev->bus, res, &region);
-                dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
+                pci_printk(KERN_DEBUG, dev, "  bridge window %pR\n", res);
         }
 }
 
@@ -398,7 +402,7 @@ static void pci_read_bridge_mmio(struct pci_bus *child)
                 region.start = base;
                 region.end = limit + 0xfffff;
                 pcibios_bus_to_resource(dev->bus, res, &region);
-                dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
+                pci_printk(KERN_DEBUG, dev, "  bridge window %pR\n", res);
         }
 }
 
@@ -438,7 +442,7 @@ static void pci_read_bridge_mmio_pref(struct pci_bus *child)
         limit = (pci_bus_addr_t) limit64;
 
         if (base != base64) {
-                dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
+                pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
                         (unsigned long long) base64);
                 return;
         }
@@ -451,7 +455,7 @@ static void pci_read_bridge_mmio_pref(struct pci_bus *child)
                 region.start = base;
                 region.end = limit + 0xfffff;
                 pcibios_bus_to_resource(dev->bus, res, &region);
-                dev_printk(KERN_DEBUG, &dev->dev, "  bridge window %pR\n", res);
+                pci_printk(KERN_DEBUG, dev, "  bridge window %pR\n", res);
         }
 }
 
@@ -464,7 +468,7 @@ void pci_read_bridge_bases(struct pci_bus *child)
         if (pci_is_root_bus(child))     /* It's a host bus, nothing to read */
                 return;
 
-        dev_info(&dev->dev, "PCI bridge to %pR%s\n",
+        pci_info(dev, "PCI bridge to %pR%s\n",
                  &child->busn_res,
                  dev->transparent ? " (subtractive decode)" : "");
 
@@ -481,7 +485,7 @@ void pci_read_bridge_bases(struct pci_bus *child)
                         if (res && res->flags) {
                                 pci_bus_add_resource(child, res,
                                                      PCI_SUBTRACTIVE_DECODE);
-                                dev_printk(KERN_DEBUG, &dev->dev,
+                                pci_printk(KERN_DEBUG, dev,
                                            "  bridge window %pR (subtractive decode)\n",
                                            res);
                         }
@@ -765,7 +769,7 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)
 
         bridge->bus = bus;
 
-        /* temporarily move resources off the list */
+        /* Temporarily move resources off the list */
         list_splice_init(&bridge->windows, &resources);
         bus->sysdata = bridge->sysdata;
         bus->msi = bridge->msi;
@@ -777,7 +781,7 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)
 
         b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
         if (b) {
-                /* If we already got to this bus through a different bridge, ignore it */
+                /* Ignore it if we already got here via a different bridge */
                 dev_dbg(&b->dev, "bus already known\n");
                 err = -EEXIST;
                 goto free;
@@ -870,9 +874,7 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
         int i;
         int ret;
 
-        /*
-         * Allocate a new bus, and inherit stuff from the parent..
-         */
+        /* Allocate a new bus and inherit stuff from the parent */
         child = pci_alloc_bus(parent);
         if (!child)
                 return NULL;
@@ -883,16 +885,14 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
         child->sysdata = parent->sysdata;
         child->bus_flags = parent->bus_flags;
 
-        /* initialize some portions of the bus device, but don't register it
-         * now as the parent is not properly set up yet.
+        /*
+         * Initialize some portions of the bus device, but don't register
+         * it now as the parent is not properly set up yet.
          */
         child->dev.class = &pcibus_class;
         dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
 
-        /*
-         * Set up the primary, secondary and subordinate
-         * bus numbers.
-         */
+        /* Set up the primary, secondary and subordinate bus numbers */
         child->number = child->busn_res.start = busnr;
         child->primary = parent->busn_res.start;
         child->busn_res.end = 0xff;
@@ -908,7 +908,7 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
         pci_set_bus_of_node(child);
         pci_set_bus_speed(child);
 
-        /* Set up default resource pointers and names.. */
+        /* Set up default resource pointers and names */
         for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
                 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
                 child->resource[i]->name = child->name;
@@ -1006,11 +1006,11 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
         secondary = (buses >> 8) & 0xFF;
         subordinate = (buses >> 16) & 0xFF;
 
-        dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
+        pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
                 secondary, subordinate, pass);
 
         if (!primary && (primary != bus->number) && secondary && subordinate) {
-                dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
+                pci_warn(dev, "Primary bus is hard wired to 0\n");
                 primary = bus->number;
         }
 
@@ -1018,13 +1018,15 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
         if (!pass &&
             (primary != bus->number || secondary <= bus->number ||
              secondary > subordinate)) {
-                dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
+                pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
                          secondary, subordinate);
                 broken = 1;
         }
 
-        /* Disable MasterAbortMode during probing to avoid reporting
-           of bus errors (in some architectures) */
+        /*
+         * Disable Master-Abort Mode during probing to avoid reporting of
+         * bus errors in some architectures.
+         */
         pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
         pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
                               bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
@@ -1034,18 +1036,19 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
         if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
             !is_cardbus && !broken) {
                 unsigned int cmax;
+
                 /*
-                 * Bus already configured by firmware, process it in the first
-                 * pass and just note the configuration.
+                 * Bus already configured by firmware, process it in the
+                 * first pass and just note the configuration.
                  */
                 if (pass)
                         goto out;
 
                 /*
-                 * The bus might already exist for two reasons: Either we are
-                 * rescanning the bus or the bus is reachable through more than
-                 * one bridge. The second case can happen with the i450NX
-                 * chipset.
+                 * The bus might already exist for two reasons: Either we
+                 * are rescanning the bus or the bus is reachable through
+                 * more than one bridge. The second case can happen with
+                 * the i450NX chipset.
                  */
                 child = pci_find_bus(pci_domain_nr(bus), secondary);
                 if (!child) {
@@ -1059,24 +1062,29 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
 
                 cmax = pci_scan_child_bus(child);
                 if (cmax > subordinate)
-                        dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
+                        pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
                                  subordinate, cmax);
-                /* subordinate should equal child->busn_res.end */
+
+                /* Subordinate should equal child->busn_res.end */
                 if (subordinate > max)
                         max = subordinate;
         } else {
+
                 /*
                  * We need to assign a number to this bus which we always
                  * do in the second pass.
                  */
                 if (!pass) {
                         if (pcibios_assign_all_busses() || broken || is_cardbus)
-                                /* Temporarily disable forwarding of the
-                                   configuration cycles on all bridges in
-                                   this bus segment to avoid possible
-                                   conflicts in the second pass between two
-                                   bridges programmed with overlapping
-                                   bus ranges. */
+
+                                /*
+                                 * Temporarily disable forwarding of the
+                                 * configuration cycles on all bridges in
+                                 * this bus segment to avoid possible
+                                 * conflicts in the second pass between two
+                                 * bridges programmed with overlapping bus
+                                 * ranges.
+                                 */
                                 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
                                                        buses & ~0xffffff);
                         goto out;
@@ -1085,9 +1093,11 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
                 /* Clear errors */
                 pci_write_config_word(dev, PCI_STATUS, 0xffff);
 
-                /* Prevent assigning a bus number that already exists.
-                 * This can happen when a bridge is hot-plugged, so in
-                 * this case we only re-scan this bus. */
+                /*
+                 * Prevent assigning a bus number that already exists.
+                 * This can happen when a bridge is hot-plugged, so in this
+                 * case we only re-scan this bus.
+                 */
                 child = pci_find_bus(pci_domain_nr(bus), max+1);
                 if (!child) {
                         child = pci_add_new_bus(bus, dev, max+1);
@@ -1114,19 +1124,18 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
                         buses |= CARDBUS_LATENCY_TIMER << 24;
                 }
 
-                /*
-                 * We need to blast all three values with a single write.
-                 */
+                /* We need to blast all three values with a single write */
                 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
 
                 if (!is_cardbus) {
                         child->bridge_ctl = bctl;
                         max = pci_scan_child_bus_extend(child, available_buses);
                 } else {
+
                         /*
-                         * For CardBus bridges, we leave 4 bus numbers
-                         * as cards with a PCI-to-PCI bridge can be
-                         * inserted later.
+                         * For CardBus bridges, we leave 4 bus numbers as
+                         * cards with a PCI-to-PCI bridge can be inserted
+                         * later.
                          */
                         for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
                                 struct pci_bus *parent = bus;
@@ -1142,10 +1151,11 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
                                         parent = parent->parent;
                                 }
                                 if (j) {
+
                                         /*
-                                         * Often, there are two cardbus bridges
-                                         * -- try to leave one valid bus number
-                                         * for each one.
+                                         * Often, there are two CardBus
+                                         * bridges -- try to leave one
+                                         * valid bus number for each one.
                                          */
                                         i /= 2;
                                         break;
@@ -1153,9 +1163,8 @@ static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
                         }
                         max += i;
                 }
-                /*
-                 * Set the subordinate bus number to its real value.
-                 */
+
+                /* Set subordinate bus number to its real value */
                 pci_bus_update_busn_res_end(child, max);
                 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
         }
@@ -1296,7 +1305,7 @@ static void set_pcie_thunderbolt(struct pci_dev *dev)
 }
 
 /**
- * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
+ * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
  * @dev: PCI device
  *
  * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
@@ -1333,7 +1342,7 @@ static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
 }
 
 /**
- * pci_cfg_space_size - get the configuration space size of the PCI device.
+ * pci_cfg_space_size - Get the configuration space size of the PCI device
  * @dev: PCI device
  *
  * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
@@ -1399,7 +1408,7 @@ static void pci_msi_setup_pci_dev(struct pci_dev *dev)
 }
 
 /**
- * pci_intx_mask_broken - test PCI_COMMAND_INTX_DISABLE writability
+ * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
  * @dev: PCI device
  *
  * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev.  Check this
@@ -1427,11 +1436,11 @@ static int pci_intx_mask_broken(struct pci_dev *dev)
 }
 
 /**
- * pci_setup_device - fill in class and map information of a device
+ * pci_setup_device - Fill in class and map information of a device
  * @dev: the device structure to fill
  *
  * Initialize the device structure with information about the device's
- * vendor,class,memory and IO-space addresses,IRQ lines etc.
+ * vendor,class,memory and IO-space addresses, IRQ lines etc.
  * Called at initialisation of the PCI subsystem and by CardBus services.
  * Returns 0 on success and negative if unknown type of device (not normal,
  * bridge or CardBus).
@@ -1457,8 +1466,11 @@ int pci_setup_device(struct pci_dev *dev)
         set_pcie_port_type(dev);
 
         pci_dev_assign_slot(dev);
-        /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
-           set this higher, assuming the system even supports it.  */
+
+        /*
+         * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
+         * set this higher, assuming the system even supports it.
+         */
         dev->dma_mask = 0xffffffff;
 
         dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
@@ -1469,13 +1481,13 @@ int pci_setup_device(struct pci_dev *dev)
         dev->revision = class & 0xff;
         dev->class = class >> 8;                    /* upper 3 bytes */
 
-        dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
+        pci_printk(KERN_DEBUG, dev, "[%04x:%04x] type %02x class %#08x\n",
                    dev->vendor, dev->device, dev->hdr_type, dev->class);
 
-        /* need to have dev->class ready */
+        /* Need to have dev->class ready */
         dev->cfg_size = pci_cfg_space_size(dev);
 
-        /* need to have dev->cfg_size ready */
+        /* Need to have dev->cfg_size ready */
         set_pcie_thunderbolt(dev);
 
         /* "Unknown power state" */
@@ -1483,13 +1495,14 @@ int pci_setup_device(struct pci_dev *dev)
 
         /* Early fixups, before probing the BARs */
         pci_fixup_device(pci_fixup_early, dev);
-        /* device class may be changed after fixup */
+
+        /* Device class may be changed after fixup */
         class = dev->class >> 8;
 
         if (dev->non_compliant_bars) {
                 pci_read_config_word(dev, PCI_COMMAND, &cmd);
                 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
-                        dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
+                        pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
                         cmd &= ~PCI_COMMAND_IO;
                         cmd &= ~PCI_COMMAND_MEMORY;
                         pci_write_config_word(dev, PCI_COMMAND, cmd);
@@ -1522,14 +1535,14 @@ int pci_setup_device(struct pci_dev *dev)
                                 res = &dev->resource[0];
                                 res->flags = LEGACY_IO_RESOURCE;
                                 pcibios_bus_to_resource(dev->bus, res, &region);
-                                dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
+                                pci_info(dev, "legacy IDE quirk: reg 0x10: %pR\n",
                                          res);
                                 region.start = 0x3F6;
                                 region.end = 0x3F6;
                                 res = &dev->resource[1];
                                 res->flags = LEGACY_IO_RESOURCE;
                                 pcibios_bus_to_resource(dev->bus, res, &region);
-                                dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
+                                pci_info(dev, "legacy IDE quirk: reg 0x14: %pR\n",
                                          res);
                         }
                         if ((progif & 4) == 0) {
@@ -1538,14 +1551,14 @@ int pci_setup_device(struct pci_dev *dev)
                                 res = &dev->resource[2];
                                 res->flags = LEGACY_IO_RESOURCE;
                                 pcibios_bus_to_resource(dev->bus, res, &region);
-                                dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
+                                pci_info(dev, "legacy IDE quirk: reg 0x18: %pR\n",
                                          res);
                                 region.start = 0x376;
                                 region.end = 0x376;
                                 res = &dev->resource[3];
                                 res->flags = LEGACY_IO_RESOURCE;
                                 pcibios_bus_to_resource(dev->bus, res, &region);
-                                dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
+                                pci_info(dev, "legacy IDE quirk: reg 0x1c: %pR\n",
                                          res);
                         }
                 }
@@ -1554,9 +1567,12 @@ int pci_setup_device(struct pci_dev *dev)
         case PCI_HEADER_TYPE_BRIDGE:                /* bridge header */
                 if (class != PCI_CLASS_BRIDGE_PCI)
                         goto bad;
-                /* The PCI-to-PCI bridge spec requires that subtractive
-                   decoding (i.e. transparent) bridge must have programming
-                   interface code of 0x01. */
+
+                /*
+                 * The PCI-to-PCI bridge spec requires that subtractive
+                 * decoding (i.e. transparent) bridge must have programming
+                 * interface code of 0x01.
+                 */
                 pci_read_irq(dev);
                 dev->transparent = ((dev->class & 0xff) == 1);
                 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
@@ -1578,12 +1594,12 @@ int pci_setup_device(struct pci_dev *dev)
                 break;
 
         default:                                    /* unknown header */
-                dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
+                pci_err(dev, "unknown header type %02x, ignoring device\n",
                         dev->hdr_type);
                 return -EIO;
 
         bad:
-                dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
+                pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
                         dev->class, dev->hdr_type);
                 dev->class = PCI_CLASS_NOT_DEFINED << 8;
         }
@@ -1607,7 +1623,7 @@ static void pci_configure_mps(struct pci_dev *dev)
                 return;
 
         if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
-                dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
+                pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
                          mps, pci_name(bridge), p_mps);
                 return;
         }
@@ -1621,12 +1637,12 @@ static void pci_configure_mps(struct pci_dev *dev)
 
         rc = pcie_set_mps(dev, p_mps);
         if (rc) {
-                dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
+                pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
                          p_mps);
                 return;
         }
 
-        dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
+        pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
                  p_mps, mps, 128 << dev->pcie_mpss);
 }
 
@@ -1646,8 +1662,7 @@ static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
                 hpp = &pci_default_type0;
 
         if (hpp->revision > 1) {
-                dev_warn(&dev->dev,
-                         "PCI settings rev %d not supported; using defaults\n",
+                pci_warn(dev, "PCI settings rev %d not supported; using defaults\n",
                          hpp->revision);
                 hpp = &pci_default_type0;
         }
@@ -1685,7 +1700,7 @@ static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
         if (!pos)
                 return;
 
-        dev_warn(&dev->dev, "PCI-X settings not supported\n");
+        pci_warn(dev, "PCI-X settings not supported\n");
 }
 
 static bool pcie_root_rcb_set(struct pci_dev *dev)
@@ -1715,7 +1730,7 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
                 return;
 
         if (hpp->revision > 1) {
-                dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
+                pci_warn(dev, "PCIe settings rev %d not supported\n",
                          hpp->revision);
                 return;
         }
@@ -1773,6 +1788,7 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
         /* Initialize Advanced Error Capabilities and Control Register */
         pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
         reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
+
         /* Don't enable ECRC generation or checking if unsupported */
         if (!(reg32 & PCI_ERR_CAP_ECRC_GENC))
                 reg32 &= ~PCI_ERR_CAP_ECRC_GENE;
@@ -1819,7 +1835,7 @@ int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
          */
         if (host->no_ext_tags) {
                 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
-                        dev_info(&dev->dev, "disabling Extended Tags\n");
+                        pci_info(dev, "disabling Extended Tags\n");
                         pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
                                                    PCI_EXP_DEVCTL_EXT_TAG);
                 }
@@ -1827,7 +1843,7 @@ int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
         }
 
         if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
-                dev_info(&dev->dev, "enabling Extended Tags\n");
+                pci_info(dev, "enabling Extended Tags\n");
                 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
                                          PCI_EXP_DEVCTL_EXT_TAG);
         }
@@ -1872,10 +1888,42 @@ static void pci_configure_relaxed_ordering(struct pci_dev *dev)
         if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
                 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
                                            PCI_EXP_DEVCTL_RELAX_EN);
-                dev_info(&dev->dev, "Disable Relaxed Ordering because the Root Port didn't support it\n");
+                pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
         }
 }
 
+static void pci_configure_ltr(struct pci_dev *dev)
+{
+#ifdef CONFIG_PCIEASPM
+        u32 cap;
+        struct pci_dev *bridge;
+
+        if (!pci_is_pcie(dev))
+                return;
+
+        pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
+        if (!(cap & PCI_EXP_DEVCAP2_LTR))
+                return;
+
+        /*
+         * Software must not enable LTR in an Endpoint unless the Root
+         * Complex and all intermediate Switches indicate support for LTR.
+         * PCIe r3.1, sec 6.18.
+         */
+        if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
+                dev->ltr_path = 1;
+        else {
+                bridge = pci_upstream_bridge(dev);
+                if (bridge && bridge->ltr_path)
+                        dev->ltr_path = 1;
+        }
+
+        if (dev->ltr_path)
+                pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
+                                         PCI_EXP_DEVCTL2_LTR_EN);
+#endif
+}
+
 static void pci_configure_device(struct pci_dev *dev)
 {
         struct hotplug_params hpp;
@@ -1884,6 +1932,7 @@ static void pci_configure_device(struct pci_dev *dev)
         pci_configure_mps(dev);
         pci_configure_extended_tags(dev, NULL);
         pci_configure_relaxed_ordering(dev);
+        pci_configure_ltr(dev);
 
         memset(&hpp, 0, sizeof(hpp));
         ret = pci_get_hp_params(dev, &hpp);
@@ -1903,10 +1952,11 @@ static void pci_release_capabilities(struct pci_dev *dev)
 }
 
 /**
- * pci_release_dev - free a pci device structure when all users of it are finished.
+ * pci_release_dev - Free a PCI device structure when all users of it are
+ *                   finished
  * @dev: device that's been disconnected
  *
- * Will be called only by the device core when all users of this pci device are
+ * Will be called only by the device core when all users of this PCI device are
  * done.
  */
 static void pci_release_dev(struct device *dev)
@@ -1994,7 +2044,7 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
         if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
                 return false;
 
-        /* some broken boards return 0 or ~0 if a slot is empty: */
+        /* Some broken boards return 0 or ~0 if a slot is empty: */
         if (*l == 0xffffffff || *l == 0x00000000 ||
             *l == 0x0000ffff || *l == 0xffff0000)
                 return false;
@@ -2007,8 +2057,8 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
 
 /*
- * Read the config data for a PCI device, sanity-check it
- * and fill in the dev structure...
+ * Read the config data for a PCI device, sanity-check it,
+ * and fill in the dev structure.
  */
 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
 {
@@ -2074,7 +2124,7 @@ static void pci_init_capabilities(struct pci_dev *dev)
 }
 
 /*
- * This is the equivalent of pci_host_bridge_msi_domain that acts on
+ * This is the equivalent of pci_host_bridge_msi_domain() that acts on
  * devices. Firmware interfaces that can select the MSI domain on a
  * per-device basis should be called from here.
  */
@@ -2083,7 +2133,7 @@ static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
         struct irq_domain *d;
 
         /*
-         * If a domain has been set through the pcibios_add_device
+         * If a domain has been set through the pcibios_add_device()
          * callback, then this is the one (platform code knows best).
          */
         d = dev_get_msi_domain(&dev->dev);
@@ -2137,10 +2187,10 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
         /* Fix up broken headers */
         pci_fixup_device(pci_fixup_header, dev);
 
-        /* moved out from quirk header fixup code */
+        /* Moved out from quirk header fixup code */
         pci_reassigndev_resource_alignment(dev);
 
-        /* Clear the state_saved flag. */
+        /* Clear the state_saved flag */
         dev->state_saved = false;
 
         /* Initialize various capabilities */
@@ -2157,7 +2207,7 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
         ret = pcibios_add_device(dev);
         WARN_ON(ret < 0);
 
-        /* Setup MSI irq domain */
+        /* Set up MSI IRQ domain */
         pci_set_msi_domain(dev);
 
         /* Notifier could use PCI capabilities */
@@ -2216,29 +2266,34 @@ static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
 
 static int only_one_child(struct pci_bus *bus)
 {
-        struct pci_dev *parent = bus->self;
+        struct pci_dev *bridge = bus->self;
 
-        if (!parent || !pci_is_pcie(parent))
+        /*
+         * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
+         * we scan for all possible devices, not just Device 0.
+         */
+        if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
                 return 0;
-        if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
-                return 1;
 
         /*
-         * PCIe downstream ports are bridges that normally lead to only a
-         * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all
-         * possible devices, not just device 0.  See PCIe spec r3.0,
-         * sec 7.3.1.
+         * A PCIe Downstream Port normally leads to a Link with only Device
+         * 0 on it (PCIe spec r3.1, sec 7.3.1).  As an optimization, scan
+         * only for Device 0 in that situation.
+         *
+         * Checking has_secondary_link is a hack to identify Downstream
+         * Ports because sometimes Switches are configured such that the
+         * PCIe Port Type labels are backwards.
          */
-        if (parent->has_secondary_link &&
-            !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
+        if (bridge && pci_is_pcie(bridge) && bridge->has_secondary_link)
                 return 1;
+
         return 0;
 }
 
 /**
- * pci_scan_slot - scan a PCI slot on a bus for devices.
+ * pci_scan_slot - Scan a PCI slot on a bus for devices
  * @bus: PCI bus to scan
- * @devfn: slot number to scan (must have zero function.)
+ * @devfn: slot number to scan (must have zero function)
  *
  * Scan a PCI slot on the specified PCI bus for devices, adding
  * discovered devices to the @bus->devices list.  New devices
@@ -2269,7 +2324,7 @@ int pci_scan_slot(struct pci_bus *bus, int devfn)
                 }
         }
 
-        /* only one slot has pcie device */
+        /* Only one slot has PCIe device */
         if (bus->self && nr)
                 pcie_aspm_init_link_state(bus->self);
 
@@ -2318,7 +2373,9 @@ static void pcie_write_mps(struct pci_dev *dev, int mps)
 
                 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
                     dev->bus->self)
-                        /* For "Performance", the assumption is made that
+
+                        /*
+                         * For "Performance", the assumption is made that
                          * downstream communication will never be larger than
                          * the MRRS.  So, the MPS only needs to be configured
                          * for the upstream communication.  This being the case,
@@ -2335,27 +2392,30 @@ static void pcie_write_mps(struct pci_dev *dev, int mps)
 
         rc = pcie_set_mps(dev, mps);
         if (rc)
-                dev_err(&dev->dev, "Failed attempting to set the MPS\n");
+                pci_err(dev, "Failed attempting to set the MPS\n");
 }
 
 static void pcie_write_mrrs(struct pci_dev *dev)
 {
         int rc, mrrs;
 
-        /* In the "safe" case, do not configure the MRRS.  There appear to be
+        /*
+         * In the "safe" case, do not configure the MRRS.  There appear to be
          * issues with setting MRRS to 0 on a number of devices.
          */
         if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
                 return;
 
-        /* For Max performance, the MRRS must be set to the largest supported
+        /*
+         * For max performance, the MRRS must be set to the largest supported
          * value.  However, it cannot be configured larger than the MPS the
          * device or the bus can support.  This should already be properly
-         * configured by a prior call to pcie_write_mps.
+         * configured by a prior call to pcie_write_mps().
          */
         mrrs = pcie_get_mps(dev);
 
-        /* MRRS is a R/W register.  Invalid values can be written, but a
+        /*
+         * MRRS is a R/W register.  Invalid values can be written, but a
          * subsequent read will verify if the value is acceptable or not.
          * If the MRRS value provided is not acceptable (e.g., too large),
          * shrink the value until it is acceptable to the HW.
@@ -2365,12 +2425,12 @@ static void pcie_write_mrrs(struct pci_dev *dev)
                 if (!rc)
                         break;
 
-                dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
+                pci_warn(dev, "Failed attempting to set the MRRS\n");
                 mrrs /= 2;
         }
 
         if (mrrs < 128)
-                dev_err(&dev->dev, "MRRS was unable to be configured with a safe value.  If problems are experienced, try running with pci=pcie_bus_safe\n");
+                pci_err(dev, "MRRS was unable to be configured with a safe value.  If problems are experienced, try running with pci=pcie_bus_safe\n");
 }
 
 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
@@ -2390,14 +2450,15 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
         pcie_write_mps(dev, mps);
         pcie_write_mrrs(dev);
 
-        dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
+        pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
                  pcie_get_mps(dev), 128 << dev->pcie_mpss,
                  orig_mps, pcie_get_readrq(dev));
 
         return 0;
 }
 
-/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
+/*
+ * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
  * parents then children fashion.  If this changes, then this code will not
  * work as designed.
  */
@@ -2411,7 +2472,8 @@ void pcie_bus_configure_settings(struct pci_bus *bus)
         if (!pci_is_pcie(bus->self))
                 return;
 
-        /* FIXME - Peer to peer DMA is possible, though the endpoint would need
+        /*
+         * FIXME - Peer to peer DMA is possible, though the endpoint would need
          * to be aware of the MPS of the destination.  To work around this,
          * simply force the MPS of the entire system to the smallest possible.
          */
@@ -2465,7 +2527,7 @@ static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
         for (devfn = 0; devfn < 0x100; devfn += 8)
                 pci_scan_slot(bus, devfn);
 
-        /* Reserve buses for SR-IOV capability. */
+        /* Reserve buses for SR-IOV capability */
         used_buses = pci_iov_bus_range(bus);
         max += used_buses;
 
@@ -2507,6 +2569,7 @@ static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
                 unsigned int buses = 0;
 
                 if (!hotplug_bridges && normal_bridges == 1) {
+
                         /*
                          * There is only one bridge on the bus (upstream
                          * port) so it gets all available buses which it
@@ -2515,6 +2578,7 @@ static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
                          */
                         buses = available_buses;
                 } else if (dev->is_hotplug_bridge) {
+
                         /*
                          * Distribute the extra buses between hotplug
                          * bridges if any.
@@ -2573,8 +2637,8 @@ unsigned int pci_scan_child_bus(struct pci_bus *bus)
 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
 
 /**
- * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
- * @bridge: Host bridge to set up.
+ * pcibios_root_bridge_prepare - Platform-specific host bridge setup
+ * @bridge: Host bridge to set up
  *
  * Default empty implementation.  Replace with an architecture-specific setup
  * routine, if necessary.
@@ -2621,6 +2685,39 @@ err_out:
 }
 EXPORT_SYMBOL_GPL(pci_create_root_bus);
 
+int pci_host_probe(struct pci_host_bridge *bridge)
+{
+        struct pci_bus *bus, *child;
+        int ret;
+
+        ret = pci_scan_root_bus_bridge(bridge);
+        if (ret < 0) {
+                dev_err(bridge->dev.parent, "Scanning root bridge failed");
+                return ret;
+        }
+
+        bus = bridge->bus;
+
+        /*
+         * We insert PCI resources into the iomem_resource and
+         * ioport_resource trees in either pci_bus_claim_resources()
+         * or pci_bus_assign_resources().
+         */
+        if (pci_has_flag(PCI_PROBE_ONLY)) {
+                pci_bus_claim_resources(bus);
+        } else {
+                pci_bus_size_bridges(bus);
+                pci_bus_assign_resources(bus);
+
+                list_for_each_entry(child, &bus->children, node)
+                        pcie_bus_configure_settings(child);
+        }
+
+        pci_bus_add_devices(bus);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(pci_host_probe);
+
 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
 {
         struct resource *res = &b->busn_res;
@@ -2777,7 +2874,7 @@ struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
 EXPORT_SYMBOL(pci_scan_bus);
 
 /**
- * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
+ * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
  * @bridge: PCI bridge for the bus to scan
  *
  * Scan a PCI bus and child buses for new devices, add them,
@@ -2802,11 +2899,11 @@ unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
 }
 
 /**
- * pci_rescan_bus - scan a PCI bus for devices.
+ * pci_rescan_bus - Scan a PCI bus for devices
  * @bus: PCI bus to scan
  *
- * Scan a PCI bus and child buses for new devices, adds them,
- * and enables them.
+ * Scan a PCI bus and child buses for new devices, add them,
+ * and enable them.
  *
  * Returns the max number of subordinate bus discovered.
  */
@@ -2875,7 +2972,7 @@ int pci_hp_add_bridge(struct pci_dev *dev)
                         break;
         }
         if (busnr-- > end) {
-                dev_err(&dev->dev, "No bus number available for hot-added bridge\n");
+                pci_err(dev, "No bus number available for hot-added bridge\n");
                 return -1;
         }
 
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 10684b17d0bd..fc734014206f 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -19,7 +19,6 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/acpi.h>
-#include <linux/kallsyms.h>
 #include <linux/dmi.h>
 #include <linux/pci-aspm.h>
 #include <linux/ioport.h>
@@ -66,7 +65,7 @@ static void quirk_passive_release(struct pci_dev *dev)
         while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
                 pci_read_config_byte(d, 0x82, &dlc);
                 if (!(dlc & 1<<1)) {
-                        dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
+                        pci_info(d, "PIIX3: Enabling Passive Release\n");
                         dlc |= 1<<1;
                         pci_write_config_byte(d, 0x82, dlc);
                 }
@@ -86,7 +85,7 @@ static void quirk_isa_dma_hangs(struct pci_dev *dev)
 {
         if (!isa_dma_bridge_buggy) {
                 isa_dma_bridge_buggy = 1;
-                dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
+                pci_info(dev, "Activating ISA DMA hang workarounds\n");
         }
 }
         /*
@@ -115,7 +114,7 @@ static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
         pm1a = inw(pmbase);
 
         if (pm1a & 0x10) {
-                dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
+                pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
                 outw(0x10, pmbase);
         }
 }
@@ -127,7 +126,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk
 static void quirk_nopcipci(struct pci_dev *dev)
 {
         if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
-                dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
+                pci_info(dev, "Disabling direct PCI/PCI transfers\n");
                 pci_pci_problems |= PCIPCI_FAIL;
         }
 }
@@ -140,7 +139,7 @@ static void quirk_nopciamd(struct pci_dev *dev)
         pci_read_config_byte(dev, 0x08, &rev);
         if (rev == 0x13) {
                 /* Erratum 24 */
-                dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
+                pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
                 pci_pci_problems |= PCIAGP_FAIL;
         }
 }
@@ -152,7 +151,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,	PCI_DEVICE_ID_AMD_8151_0,	quirk_nopci
 static void quirk_triton(struct pci_dev *dev)
 {
         if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
-                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
+                pci_info(dev, "Limiting direct PCI/PCI transfers\n");
                 pci_pci_problems |= PCIPCI_TRITON;
         }
 }
@@ -212,7 +211,7 @@ static void quirk_vialatency(struct pci_dev *dev)
         busarb &= ~(1<<5);
         busarb |= (1<<4);
         pci_write_config_byte(dev, 0x76, busarb);
-        dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
+        pci_info(dev, "Applying VIA southbridge workaround\n");
 exit:
         pci_dev_put(p);
 }
@@ -230,7 +229,7 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8361,		quirk_viala
 static void quirk_viaetbf(struct pci_dev *dev)
 {
         if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
-                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
+                pci_info(dev, "Limiting direct PCI/PCI transfers\n");
                 pci_pci_problems |= PCIPCI_VIAETBF;
         }
 }
@@ -239,7 +238,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C597_0,	quirk_via
 static void quirk_vsfx(struct pci_dev *dev)
 {
         if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
-                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
+                pci_info(dev, "Limiting direct PCI/PCI transfers\n");
                 pci_pci_problems |= PCIPCI_VSFX;
         }
 }
@@ -254,7 +253,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_82C576,	quirk_vsfx)
 static void quirk_alimagik(struct pci_dev *dev)
 {
         if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
-                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
+                pci_info(dev, "Limiting direct PCI/PCI transfers\n");
                 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
         }
 }
@@ -268,7 +267,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL,	PCI_DEVICE_ID_AL_M1651,		quirk_alimagi
 static void quirk_natoma(struct pci_dev *dev)
 {
         if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
-                dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
+                pci_info(dev, "Limiting direct PCI/PCI transfers\n");
                 pci_pci_problems |= PCIPCI_NATOMA;
         }
 }
@@ -313,7 +312,7 @@ static void quirk_extend_bar_to_page(struct pci_dev *dev)
                         r->end = PAGE_SIZE - 1;
                         r->start = 0;
                         r->flags |= IORESOURCE_UNSET;
-                        dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n",
+                        pci_info(dev, "expanded BAR %d to page size: %pR\n",
                                  i, r);
                 }
         }
@@ -360,7 +359,7 @@ static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
         bus_region.end = region + size - 1;
         pcibios_bus_to_resource(dev->bus, res, &bus_region);
 
-        dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
+        pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
                  name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
 }
 
@@ -381,7 +380,7 @@ static void quirk_cs5536_vsa(struct pci_dev *dev)
                 quirk_io(dev, 0,   8, name);    /* SMB */
                 quirk_io(dev, 1, 256, name);    /* GPIO */
                 quirk_io(dev, 2,  64, name);    /* MFGPT */
-                dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n",
+                pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
                          name);
         }
 }
@@ -409,7 +408,7 @@ static void quirk_io_region(struct pci_dev *dev, int port,
         pcibios_bus_to_resource(dev->bus, res, &bus_region);
 
         if (!pci_claim_resource(dev, nr))
-                dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
+                pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
 }
 
 /*
@@ -418,7 +417,7 @@ static void quirk_io_region(struct pci_dev *dev, int port,
  */
 static void quirk_ati_exploding_mce(struct pci_dev *dev)
 {
-        dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
+        pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
         /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
         request_region(0x3b0, 0x0C, "RadeonIGP");
         request_region(0x3d3, 0x01, "RadeonIGP");
@@ -441,7 +440,7 @@ static void quirk_amd_nl_class(struct pci_dev *pdev)
 
         /* Use "USB Device (not host controller)" class */
         pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
-        dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
+        pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
                  class, pdev->class);
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
@@ -488,8 +487,7 @@ static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int p
          * let's get enough confirmation reports first.
          */
         base &= -size;
-        dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base,
-                 base + size - 1);
+        pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
 }
 
 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
@@ -514,8 +512,7 @@ static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int
          * reserve it, but let's get enough confirmation reports first.
          */
         base &= -size;
-        dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base,
-                 base + size - 1);
+        pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
 }
 
 /*
@@ -644,7 +641,7 @@ static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const cha
         base &= ~(size-1);
 
         /* Just print it out for now. We should reserve it after more debugging */
-        dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
+        pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
 }
 
 static void quirk_ich6_lpc(struct pci_dev *dev)
@@ -679,7 +676,7 @@ static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const cha
         mask |= 3;
 
         /* Just print it out for now. We should reserve it after more debugging */
-        dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
+        pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
 }
 
 /* ICH7-10 has the same common LPC generic IO decode registers */
@@ -758,7 +755,7 @@ static void quirk_xio2000a(struct pci_dev *dev)
         struct pci_dev *pdev;
         u16 command;
 
-        dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
+        pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
         list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
                 pci_read_config_word(pdev, PCI_COMMAND, &command);
                 if (command & PCI_COMMAND_FAST_BACK)
@@ -788,7 +785,7 @@ static void quirk_via_ioapic(struct pci_dev *dev)
         else
                 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
 
-        dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
+        pci_info(dev, "%sbling VIA external APIC routing\n",
                tmp == 0 ? "Disa" : "Ena");
 
         /* Offset 0x58: External APIC IRQ output control */
@@ -810,7 +807,7 @@ static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
 
         pci_read_config_byte(dev, 0x5B, &misc_control2);
         if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
-                dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
+                pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
                 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
         }
 }
@@ -829,8 +826,8 @@ DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA,	PCI_DEVICE_ID_VIA_8237,		quirk
 static void quirk_amd_ioapic(struct pci_dev *dev)
 {
         if (dev->revision >= 0x02) {
-                dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
-                dev_warn(&dev->dev, "        : booting with the \"noapic\" option\n");
+                pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
+                pci_warn(dev, "        : booting with the \"noapic\" option\n");
         }
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_VIPER_7410,   quirk_amd_ioapic);
@@ -854,7 +851,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_lin
 static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
 {
         if (dev->subordinate && dev->revision <= 0x12) {
-                dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
+                pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
                          dev->revision);
                 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
         }
@@ -962,7 +959,7 @@ static void quirk_via_vlink(struct pci_dev *dev)
 
         pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
         if (new_irq != irq) {
-                dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
+                pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
                         irq, new_irq);
                 udelay(15);     /* unknown if delay really needed */
                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
@@ -1011,7 +1008,7 @@ static void quirk_amd_ordering(struct pci_dev *dev)
         pci_read_config_dword(dev, 0x4C, &pcic);
         if ((pcic & 6) != 6) {
                 pcic |= 6;
-                dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
+                pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
                 pci_write_config_dword(dev, 0x4C, pcic);
                 pci_read_config_dword(dev, 0x84, &pcic);
                 pcic |= (1 << 23);      /* Required in this mode */
@@ -1064,7 +1061,7 @@ static void quirk_mediagx_master(struct pci_dev *dev)
         pci_read_config_byte(dev, 0x41, &reg);
         if (reg & 2) {
                 reg &= ~2;
-                dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
+                pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
                          reg);
                 pci_write_config_byte(dev, 0x41, reg);
         }
@@ -1087,7 +1084,7 @@ static void quirk_disable_pxb(struct pci_dev *pdev)
         if (config & (1<<6)) {
                 config &= ~(1<<6);
                 pci_write_config_word(pdev, 0x40, config);
-                dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
+                pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
         }
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82454NX,    quirk_disable_pxb);
@@ -1107,7 +1104,7 @@ static void quirk_amd_ide_mode(struct pci_dev *pdev)
                 pci_write_config_byte(pdev, 0x40, tmp);
 
                 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
-                dev_info(&pdev->dev, "set SATA to AHCI mode\n");
+                pci_info(pdev, "set SATA to AHCI mode\n");
         }
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
@@ -1145,7 +1142,7 @@ static void quirk_ide_samemode(struct pci_dev *pdev)
         pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
 
         if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
-                dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
+                pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
                 prog &= ~5;
                 pdev->class &= ~5;
                 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
@@ -1356,10 +1353,10 @@ static void asus_hides_smbus_lpc(struct pci_dev *dev)
                 pci_write_config_word(dev, 0xF2, val & (~0x8));
                 pci_read_config_word(dev, 0xF2, &val);
                 if (val & 0x8)
-                        dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
+                        pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
                                  val);
                 else
-                        dev_info(&dev->dev, "Enabled i801 SMBus device\n");
+                        pci_info(dev, "Enabled i801 SMBus device\n");
         }
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82801AA_0,  asus_hides_smbus_lpc);
@@ -1411,7 +1408,7 @@ static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
                 return;
         iounmap(asus_rcba_base);
         asus_rcba_base = NULL;
-        dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
+        pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
 }
 
 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
@@ -1433,7 +1430,7 @@ static void quirk_sis_96x_smbus(struct pci_dev *dev)
         u8 val = 0;
         pci_read_config_byte(dev, 0x77, &val);
         if (val & 0x10) {
-                dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
+                pci_info(dev, "Enabling SiS 96x SMBus\n");
                 pci_write_config_byte(dev, 0x77, val & ~0x10);
         }
 }
@@ -1505,10 +1502,10 @@ static void asus_hides_ac97_lpc(struct pci_dev *dev)
                 pci_write_config_byte(dev, 0x50, val & (~0xc0));
                 pci_read_config_byte(dev, 0x50, &val);
                 if (val & 0xc0)
-                        dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
+                        pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
                                  val);
                 else
-                        dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
+                        pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
         }
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA,     PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
@@ -1599,7 +1596,7 @@ static void quirk_jmicron_async_suspend(struct pci_dev *dev)
 {
         if (dev->multifunction) {
                 device_disable_async_suspend(&dev->dev);
-                dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
+                pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
         }
 }
 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
@@ -1636,8 +1633,8 @@ static void quirk_pcie_mch(struct pci_dev *pdev)
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_E7520_MCH,  quirk_pcie_mch);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_E7320_MCH,  quirk_pcie_mch);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_E7525_MCH,  quirk_pcie_mch);
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI,   0x1610, quirk_pcie_mch);
 
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
 
 /*
  * It's possible for the MSI to get corrupted if shpc and acpi
@@ -1646,7 +1643,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI,	0x1610,	quirk_pcie_mch);
 static void quirk_pcie_pxh(struct pci_dev *dev)
 {
         dev->no_msi = 1;
-        dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
+        pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHD_0,     quirk_pcie_pxh);
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_PXHD_1,     quirk_pcie_pxh);
@@ -1692,7 +1689,7 @@ static void quirk_radeon_pm(struct pci_dev *dev)
             dev->subsystem_device == 0x00e2) {
                 if (dev->d3_delay < 20) {
                         dev->d3_delay = 20;
-                        dev_info(&dev->dev, "extending delay after power-on from D3 to %d msec\n",
+                        pci_info(dev, "extending delay after power-on from D3 to %d msec\n",
                                  dev->d3_delay);
                 }
         }
@@ -1736,7 +1733,7 @@ static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
                 return;
 
         dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
-        dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
+        pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
                  dev->vendor, dev->device);
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_80333_0,    quirk_reroute_to_boot_interrupts_intel);
@@ -1779,7 +1776,7 @@ static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
         pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
         pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
 
-        dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
+        pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
                  dev->vendor, dev->device);
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_ESB_10,      quirk_disable_intel_boot_interrupt);
@@ -1812,7 +1809,7 @@ static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
 
         pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
 
-        dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
+        pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
                  dev->vendor, dev->device);
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB,        quirk_disable_broadcom_boot_interrupt);
@@ -1845,7 +1842,7 @@ static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
         pci_config_dword &= ~AMD_813X_NOIOAMODE;
         pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
 
-        dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
+        pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
                  dev->vendor, dev->device);
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_8131_BRIDGE,  quirk_disable_amd_813x_boot_interrupt);
@@ -1864,12 +1861,12 @@ static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
 
         pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
         if (!pci_config_word) {
-                dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n",
+                pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
                          dev->vendor, dev->device);
                 return;
         }
         pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
-        dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
+        pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
                  dev->vendor, dev->device);
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS,      quirk_disable_amd_8111_boot_interrupt);
@@ -1913,7 +1910,7 @@ static void quirk_plx_pci9050(struct pci_dev *dev)
                 if (pci_resource_len(dev, bar) == 0x80 &&
                     (pci_resource_start(dev, bar) & 0x80)) {
                         struct resource *r = &dev->resource[bar];
-                        dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
+                        pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
                                  bar);
                         r->flags |= IORESOURCE_UNSET;
                         r->start = 0;
@@ -1960,7 +1957,7 @@ static void quirk_netmos(struct pci_dev *dev)
         case PCI_DEVICE_ID_NETMOS_9845:
         case PCI_DEVICE_ID_NETMOS_9855:
                 if (num_parallel) {
-                        dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
+                        pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
                                 dev->device, num_parallel, num_serial);
                         dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
                             (dev->class & 0xff);
@@ -2046,13 +2043,13 @@ static void quirk_e100_interrupt(struct pci_dev *dev)
         /* Convert from PCI bus to resource space.  */
         csr = ioremap(pci_resource_start(dev, 0), 8);
         if (!csr) {
-                dev_warn(&dev->dev, "Can't map e100 registers\n");
+                pci_warn(dev, "Can't map e100 registers\n");
                 return;
         }
 
         cmd_hi = readb(csr + 3);
         if (cmd_hi == 0) {
-                dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n");
+                pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
                 writeb(1, csr + 3);
         }
 
@@ -2067,7 +2064,7 @@ DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
  */
 static void quirk_disable_aspm_l0s(struct pci_dev *dev)
 {
-        dev_info(&dev->dev, "Disabling L0s\n");
+        pci_info(dev, "Disabling L0s\n");
         pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
@@ -2097,7 +2094,7 @@ static void fixup_rev1_53c810(struct pci_dev *dev)
                 return;
 
         dev->class = PCI_CLASS_STORAGE_SCSI << 8;
-        dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
+        pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
                  class, dev->class);
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
@@ -2110,7 +2107,7 @@ static void quirk_p64h2_1k_io(struct pci_dev *dev)
         pci_read_config_word(dev, 0x40, &en1k);
 
         if (en1k & 0x200) {
-                dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
+                pci_info(dev, "Enable I/O Space to 1KB granularity\n");
                 dev->io_window_1k = 1;
         }
 }
@@ -2126,7 +2123,7 @@ static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
         if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
                 if (!(b & 0x20)) {
                         pci_write_config_byte(dev, 0xf41, b | 0x20);
-                        dev_info(&dev->dev, "Linking AER extended capability\n");
+                        pci_info(dev, "Linking AER extended capability\n");
                 }
         }
 }
@@ -2164,7 +2161,7 @@ static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
                         /* Turn off PCI Bus Parking */
                         pci_write_config_byte(dev, 0x76, b ^ 0x40);
 
-                        dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n");
+                        pci_info(dev, "Disabling VIA CX700 PCI parking\n");
                 }
         }
 
@@ -2179,7 +2176,7 @@ static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
                         /* Disable "Read FIFO Timer" */
                         pci_write_config_byte(dev, 0x77, 0x0);
 
-                        dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n");
+                        pci_info(dev, "Disabling VIA CX700 PCI caching\n");
                 }
         }
 }
@@ -2196,7 +2193,7 @@ static void quirk_blacklist_vpd(struct pci_dev *dev)
 {
         if (dev->vpd) {
                 dev->vpd->len = 0;
-                dev_warn(&dev->dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
+                pci_warn(dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
         }
 }
 
@@ -2312,7 +2309,7 @@ static void quirk_unhide_mch_dev6(struct pci_dev *dev)
         u8 reg;
 
         if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
-                dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
+                pci_info(dev, "Enabling MCH 'Overflow' Device\n");
                 pci_write_config_byte(dev, 0xF4, reg | 0x02);
         }
 }
@@ -2351,7 +2348,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
 static void quirk_disable_all_msi(struct pci_dev *dev)
 {
         pci_no_msi();
-        dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
+        pci_warn(dev, "MSI quirk detected; MSI disabled\n");
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
@@ -2366,7 +2363,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
 static void quirk_disable_msi(struct pci_dev *dev)
 {
         if (dev->subordinate) {
-                dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
+                pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
                 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
         }
 }
@@ -2406,7 +2403,7 @@ static int msi_ht_cap_enabled(struct pci_dev *dev)
 
                 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
                                          &flags) == 0) {
-                        dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
+                        pci_info(dev, "Found %s HT MSI Mapping\n",
                                 flags & HT_MSI_FLAGS_ENABLE ?
                                 "enabled" : "disabled");
                         return (flags & HT_MSI_FLAGS_ENABLE) != 0;
@@ -2422,7 +2419,7 @@ static int msi_ht_cap_enabled(struct pci_dev *dev)
 static void quirk_msi_ht_cap(struct pci_dev *dev)
 {
         if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
-                dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
+                pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
                 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
         }
 }
@@ -2446,7 +2443,7 @@ static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
         if (!pdev)
                 return;
         if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
-                dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
+                pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
                 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
         }
         pci_dev_put(pdev);
@@ -2465,7 +2462,7 @@ static void ht_enable_msi_mapping(struct pci_dev *dev)
 
                 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
                                          &flags) == 0) {
-                        dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
+                        pci_info(dev, "Enabling HT MSI Mapping\n");
 
                         pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
                                               flags | HT_MSI_FLAGS_ENABLE);
@@ -2492,7 +2489,7 @@ static void nvenet_msi_disable(struct pci_dev *dev)
         if (board_name &&
             (strstr(board_name, "P5N32-SLI PREMIUM") ||
              strstr(board_name, "P5N32-E SLI"))) {
-                dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n");
+                pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
                 dev->no_msi = 1;
         }
 }
@@ -2669,7 +2666,7 @@ static void ht_disable_msi_mapping(struct pci_dev *dev)
 
                 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
                                          &flags) == 0) {
-                        dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
+                        pci_info(dev, "Disabling HT MSI Mapping\n");
 
                         pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
                                               flags & ~HT_MSI_FLAGS_ENABLE);
@@ -2699,9 +2696,10 @@ static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
          * HT MSI mapping should be disabled on devices that are below
          * a non-Hypertransport host bridge. Locate the host bridge...
          */
-        host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
+        host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
+                                                  PCI_DEVFN(0, 0));
         if (host_bridge == NULL) {
-                dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
+                pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
                 return;
         }
 
@@ -2770,7 +2768,7 @@ static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
 {
         /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
         if (dev->revision < 0x18) {
-                dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
+                pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
                 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
         }
 }
@@ -2899,8 +2897,8 @@ static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
         pci_write_config_byte(dev, 0x8E, write_enable);
         pci_write_config_byte(dev, 0x8D, write_target);
 
-        dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
-        dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
+        pci_notice(dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
+        pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
@@ -2935,7 +2933,7 @@ static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
                 pci_write_config_byte(dev, 0xe1, 0x32);
                 pci_write_config_byte(dev, 0xfc, 0x00);
 
-                dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
+                pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
         }
 
         pci_read_config_byte(dev, 0xCB, &disable);
@@ -2948,8 +2946,8 @@ static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
         pci_write_config_byte(dev, 0xCB, disable | 0x02);
         pci_write_config_byte(dev, 0xCA, write_enable);
 
-        dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
-        dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
+        pci_notice(dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
+        pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
 
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
@@ -2990,7 +2988,7 @@ static void fixup_ti816x_class(struct pci_dev *dev)
 
         /* TI 816x devices do not have class code set when in PCIe boot mode */
         dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
-        dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n",
+        pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
                  class, dev->class);
 }
 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
@@ -3032,7 +3030,7 @@ static void quirk_intel_mc_errata(struct pci_dev *dev)
          */
         err = pci_read_config_word(dev, 0x48, &rcc);
         if (err) {
-                dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n");
+                pci_err(dev, "Error attempting to read the read completion coalescing register\n");
                 return;
         }
 
@@ -3043,7 +3041,7 @@ static void quirk_intel_mc_errata(struct pci_dev *dev)
 
         err = pci_write_config_word(dev, 0x48, rcc);
         if (err) {
-                dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n");
+                pci_err(dev, "Error attempting to write the read completion coalescing register\n");
                 return;
         }
 
@@ -3108,7 +3106,7 @@ static ktime_t fixup_debug_start(struct pci_dev *dev,
 {
         ktime_t calltime = 0;
 
-        dev_dbg(&dev->dev, "calling %pF\n", fn);
+        pci_dbg(dev, "calling %pF\n", fn);
         if (initcall_debug) {
                 pr_debug("calling  %pF @ %i for %s\n",
                          fn, task_pid_nr(current), dev_name(&dev->dev));
@@ -3150,13 +3148,13 @@ static void disable_igfx_irq(struct pci_dev *dev)
 {
         void __iomem *regs = pci_iomap(dev, 0, 0);
         if (regs == NULL) {
-                dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
+                pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
                 return;
         }
 
         /* Check if any interrupt line is still enabled */
         if (readl(regs + I915_DEIER_REG) != 0) {
-                dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
+                pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
 
                 writel(0, regs + I915_DEIER_REG);
         }
@@ -3215,6 +3213,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
                         quirk_broken_intx_masking);
 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
                         quirk_broken_intx_masking);
+DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */
+                        quirk_broken_intx_masking);
 
 /*
  * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
@@ -3317,13 +3317,13 @@ static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
 
         /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
         if (pci_enable_device_mem(pdev)) {
-                dev_warn(&pdev->dev, "Can't enable device memory\n");
+                pci_warn(pdev, "Can't enable device memory\n");
                 return;
         }
 
         fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
         if (!fw_ver) {
-                dev_warn(&pdev->dev, "Can't map ConnectX-4 initialization segment\n");
+                pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
                 goto out;
         }
 
@@ -3335,7 +3335,7 @@ static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
         fw_subminor = fw_sub_min & 0xffff;
         if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
             fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
-                dev_warn(&pdev->dev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
+                pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
                          fw_major, fw_minor, fw_subminor, pdev->device ==
                          PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
                 pdev->broken_intx_masking = 1;
@@ -3473,7 +3473,7 @@ static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
             || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
             || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
                 return;
-        dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n");
+        pci_info(dev, "quirk: cutting power to thunderbolt controller...\n");
 
         /* magic sequence */
         acpi_execute_simple_method(SXIO, NULL, 1);
@@ -3524,7 +3524,7 @@ static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
                         nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
                     || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
                 goto out;
-        dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
+        pci_info(dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
         device_pm_wait_for_dev(&dev->dev, &nhi->dev);
 out:
         pci_dev_put(nhi);
@@ -3740,7 +3740,7 @@ static int reset_ivb_igd(struct pci_dev *dev, int probe)
                         goto reset_complete;
                 msleep(10);
         } while (time_before(jiffies, timeout));
-        dev_warn(&dev->dev, "timeout during reset\n");
+        pci_warn(dev, "timeout during reset\n");
 
 reset_complete:
         iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
@@ -3879,6 +3879,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
                          quirk_dma_func1_alias);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
                          quirk_dma_func1_alias);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
+                         quirk_dma_func1_alias);
 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
                          quirk_dma_func1_alias);
@@ -4012,7 +4014,7 @@ static void quirk_tw686x_class(struct pci_dev *pdev)
 
         /* Use "Multimedia controller" class */
         pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
-        dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
+        pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
                  class, pdev->class);
 }
 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
@@ -4032,7 +4034,7 @@ DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
 static void quirk_relaxedordering_disable(struct pci_dev *dev)
 {
         dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
-        dev_info(&dev->dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
+        pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
 }
 
 /*
@@ -4141,11 +4143,11 @@ static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
         struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
 
         if (!root_port) {
-                dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n");
+                pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
                 return;
         }
 
-        dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
+        pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
                  dev_name(&pdev->dev));
         pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
                                            PCI_EXP_DEVCTL_RELAX_EN |
@@ -4339,7 +4341,7 @@ static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
         u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
         int ret = acs_flags & ~flags ? 0 : 1;
 
-        dev_info(&dev->dev, "Using QCOM ACS Quirk (%d)\n", ret);
+        pci_info(dev, "Using QCOM ACS Quirk (%d)\n", ret);
 
         return ret;
 }
@@ -4591,7 +4593,7 @@ static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
         if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
                 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
                 if (updcr & INTEL_UPDCR_REG_MASK) {
-                        dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
+                        pci_info(dev, "Disabling UPDCR peer decodes\n");
                         updcr &= ~INTEL_UPDCR_REG_MASK;
                         writel(updcr, rcba_mem + INTEL_UPDCR_REG);
                 }
@@ -4618,7 +4620,7 @@ static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
          */
         pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
         if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
-                dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
+                pci_info(dev, "Enabling MPC IRBNCE\n");
                 mpc |= INTEL_MPC_REG_IRBNCE;
                 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
         }
@@ -4630,7 +4632,7 @@ static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
                 return -ENOTTY;
 
         if (pci_quirk_enable_intel_lpc_acs(dev)) {
-                dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
+                pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
                 return 0;
         }
 
@@ -4638,7 +4640,7 @@ static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
 
         dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
 
-        dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
+        pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
 
         return 0;
 }
@@ -4665,7 +4667,7 @@ static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
 
         pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
 
-        dev_info(&dev->dev, "Intel SPT PCH root port ACS workaround enabled\n");
+        pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
 
         return 0;
 }
@@ -4800,7 +4802,7 @@ static void quirk_no_ext_tags(struct pci_dev *pdev)
                 return;
 
         bridge->no_ext_tags = 1;
-        dev_info(&pdev->dev, "disabling Extended Tags (this device can't handle them)\n");
+        pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
 
         pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
 }
@@ -4815,7 +4817,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
  */
 static void quirk_no_ats(struct pci_dev *pdev)
 {
-        dev_info(&pdev->dev, "disabling ATS (broken on this device)\n");
+        pci_info(pdev, "disabling ATS (broken on this device)\n");
         pdev->ats_cap = 0;
 }
 
diff --git a/drivers/pci/rom.c b/drivers/pci/rom.c
index 9ba3fa841eb0..374a33443be9 100644
--- a/drivers/pci/rom.c
+++ b/drivers/pci/rom.c
@@ -93,15 +93,15 @@ size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size)
                 void __iomem *pds;
                 /* Standard PCI ROMs start out with these bytes 55 AA */
                 if (readw(image) != 0xAA55) {
-                        dev_err(&pdev->dev, "Invalid PCI ROM header signature: expecting 0xaa55, got %#06x\n",
-                                readw(image));
+                        pci_info(pdev, "Invalid PCI ROM header signature: expecting 0xaa55, got %#06x\n",
+                                 readw(image));
                         break;
                 }
                 /* get the PCI data structure and check its "PCIR" signature */
                 pds = image + readw(image + 24);
                 if (readl(pds) != 0x52494350) {
-                        dev_err(&pdev->dev, "Invalid PCI ROM data signature: expecting 0x52494350, got %#010x\n",
-                                readl(pds));
+                        pci_info(pdev, "Invalid PCI ROM data signature: expecting 0x52494350, got %#010x\n",
+                                 readl(pds));
                         break;
                 }
                 last_image = readb(pds + 21) & 0x80;
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 0a26648f1712..3cce29a069e6 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -68,10 +68,8 @@ static int add_to_list(struct list_head *head,
         struct pci_dev_resource *tmp;
 
         tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
-        if (!tmp) {
-                pr_warn("add_to_list: kmalloc() failed!\n");
+        if (!tmp)
                 return -ENOMEM;
-        }
 
         tmp->res = res;
         tmp->dev = dev;
@@ -153,7 +151,7 @@ static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
 
                 r_align = pci_resource_alignment(dev, r);
                 if (!r_align) {
-                        dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
+                        pci_warn(dev, "BAR %d: %pR has bogus alignment\n",
                                  i, r);
                         continue;
                 }
@@ -261,7 +259,7 @@ static void reassign_resources_sorted(struct list_head *realloc_head,
                                  (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
                         if (pci_reassign_resource(add_res->dev, idx,
                                                   add_size, align))
-                                dev_printk(KERN_DEBUG, &add_res->dev->dev,
+                                pci_printk(KERN_DEBUG, add_res->dev,
                                            "failed to add %llx res[%d]=%pR\n",
                                            (unsigned long long)add_size,
                                            idx, res);
@@ -520,7 +518,7 @@ void pci_setup_cardbus(struct pci_bus *bus)
         struct resource *res;
         struct pci_bus_region region;
 
-        dev_info(&bridge->dev, "CardBus bridge to %pR\n",
+        pci_info(bridge, "CardBus bridge to %pR\n",
                  &bus->busn_res);
 
         res = bus->resource[0];
@@ -530,7 +528,7 @@ void pci_setup_cardbus(struct pci_bus *bus)
                  * The IO resource is allocated a range twice as large as it
                  * would normally need.  This allows us to set both IO regs.
                  */
-                dev_info(&bridge->dev, "  bridge window %pR\n", res);
+                pci_info(bridge, "  bridge window %pR\n", res);
                 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
                                         region.start);
                 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
@@ -540,7 +538,7 @@ void pci_setup_cardbus(struct pci_bus *bus)
         res = bus->resource[1];
         pcibios_resource_to_bus(bridge->bus, &region, res);
         if (res->flags & IORESOURCE_IO) {
-                dev_info(&bridge->dev, "  bridge window %pR\n", res);
+                pci_info(bridge, "  bridge window %pR\n", res);
                 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
                                         region.start);
                 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
@@ -550,7 +548,7 @@ void pci_setup_cardbus(struct pci_bus *bus)
         res = bus->resource[2];
         pcibios_resource_to_bus(bridge->bus, &region, res);
         if (res->flags & IORESOURCE_MEM) {
-                dev_info(&bridge->dev, "  bridge window %pR\n", res);
+                pci_info(bridge, "  bridge window %pR\n", res);
                 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
                                         region.start);
                 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
@@ -560,7 +558,7 @@ void pci_setup_cardbus(struct pci_bus *bus)
         res = bus->resource[3];
         pcibios_resource_to_bus(bridge->bus, &region, res);
         if (res->flags & IORESOURCE_MEM) {
-                dev_info(&bridge->dev, "  bridge window %pR\n", res);
+                pci_info(bridge, "  bridge window %pR\n", res);
                 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
                                         region.start);
                 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
@@ -603,7 +601,7 @@ static void pci_setup_bridge_io(struct pci_dev *bridge)
                 l = ((u16) io_limit_lo << 8) | io_base_lo;
                 /* Set up upper 16 bits of I/O base/limit. */
                 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
-                dev_info(&bridge->dev, "  bridge window %pR\n", res);
+                pci_info(bridge, "  bridge window %pR\n", res);
         } else {
                 /* Clear upper 16 bits of I/O base/limit. */
                 io_upper16 = 0;
@@ -629,7 +627,7 @@ static void pci_setup_bridge_mmio(struct pci_dev *bridge)
         if (res->flags & IORESOURCE_MEM) {
                 l = (region.start >> 16) & 0xfff0;
                 l |= region.end & 0xfff00000;
-                dev_info(&bridge->dev, "  bridge window %pR\n", res);
+                pci_info(bridge, "  bridge window %pR\n", res);
         } else {
                 l = 0x0000fff0;
         }
@@ -658,7 +656,7 @@ static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
                         bu = upper_32_bits(region.start);
                         lu = upper_32_bits(region.end);
                 }
-                dev_info(&bridge->dev, "  bridge window %pR\n", res);
+                pci_info(bridge, "  bridge window %pR\n", res);
         } else {
                 l = 0x0000fff0;
         }
@@ -673,7 +671,7 @@ static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
 {
         struct pci_dev *bridge = bus->self;
 
-        dev_info(&bridge->dev, "PCI bridge to %pR\n",
+        pci_info(bridge, "PCI bridge to %pR\n",
                  &bus->busn_res);
 
         if (type & IORESOURCE_IO)
@@ -945,7 +943,7 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
                         resource_size(b_res), min_align);
         if (!size0 && !size1) {
                 if (b_res->start || b_res->end)
-                        dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n",
+                        pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
                                  b_res, &bus->busn_res);
                 b_res->flags = 0;
                 return;
@@ -957,7 +955,7 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
         if (size1 > size0 && realloc_head) {
                 add_to_list(realloc_head, bus->self, b_res, size1-size0,
                             min_align);
-                dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx\n",
+                pci_printk(KERN_DEBUG, bus->self, "bridge window %pR to %pR add_size %llx\n",
                            b_res, &bus->busn_res,
                            (unsigned long long)size1-size0);
         }
@@ -1062,7 +1060,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
                         if (order < 0)
                                 order = 0;
                         if (order >= ARRAY_SIZE(aligns)) {
-                                dev_warn(&dev->dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
+                                pci_warn(dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
                                          i, r, (unsigned long long) align);
                                 r->flags = 0;
                                 continue;
@@ -1094,7 +1092,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
                                 resource_size(b_res), add_align);
         if (!size0 && !size1) {
                 if (b_res->start || b_res->end)
-                        dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n",
+                        pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
                                  b_res, &bus->busn_res);
                 b_res->flags = 0;
                 return 0;
@@ -1104,7 +1102,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
         b_res->flags |= IORESOURCE_STARTALIGN;
         if (size1 > size0 && realloc_head) {
                 add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
-                dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx add_align %llx\n",
+                pci_printk(KERN_DEBUG, bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n",
                            b_res, &bus->busn_res,
                            (unsigned long long) (size1 - size0),
                            (unsigned long long) add_align);
@@ -1408,7 +1406,7 @@ void __pci_bus_assign_resources(const struct pci_bus *bus,
                         break;
 
                 default:
-                        dev_info(&dev->dev, "not setting up bridge for bus %04x:%02x\n",
+                        pci_info(dev, "not setting up bridge for bus %04x:%02x\n",
                                  pci_domain_nr(b), b->number);
                         break;
                 }
@@ -1514,7 +1512,7 @@ static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
                 break;
 
         default:
-                dev_info(&bridge->dev, "not setting up bridge for bus %04x:%02x\n",
+                pci_info(bridge, "not setting up bridge for bus %04x:%02x\n",
                          pci_domain_nr(b), b->number);
                 break;
         }
@@ -1572,7 +1570,7 @@ static void pci_bridge_release_resources(struct pci_bus *bus,
         release_child_resources(r);
         if (!release_resource(r)) {
                 type = old_flags = r->flags & PCI_RES_TYPE_MASK;
-                dev_printk(KERN_DEBUG, &dev->dev, "resource %d %pR released\n",
+                pci_printk(KERN_DEBUG, dev, "resource %d %pR released\n",
                                         PCI_BRIDGE_RESOURCES + idx, r);
                 /* keep the old size */
                 r->end = resource_size(r) - 1;
@@ -1875,7 +1873,7 @@ static void extend_bridge_window(struct pci_dev *bridge, struct resource *res,
                 return;
 
         dev_res->add_size = available - resource_size(res);
-        dev_dbg(&bridge->dev, "bridge window %pR extended by %pa\n", res,
+        pci_dbg(bridge, "bridge window %pR extended by %pa\n", res,
                 &dev_res->add_size);
 }
 
@@ -2086,7 +2084,7 @@ again:
 enable_all:
         retval = pci_reenable_device(bridge);
         if (retval)
-                dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval);
+                pci_err(bridge, "Error reenabling bridge (%d)\n", retval);
         pci_set_master(bridge);
 }
 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
@@ -2120,7 +2118,7 @@ int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
                         if (ret)
                                 goto cleanup;
 
-                        dev_info(&bridge->dev, "BAR %d: releasing %pR\n",
+                        pci_info(bridge, "BAR %d: releasing %pR\n",
                                  i, res);
 
                         if (res->parent)
diff --git a/drivers/pci/setup-irq.c b/drivers/pci/setup-irq.c
index 9c8d81b3cf82..5ad4ee7d7b1e 100644
--- a/drivers/pci/setup-irq.c
+++ b/drivers/pci/setup-irq.c
@@ -26,7 +26,7 @@ void pci_assign_irq(struct pci_dev *dev)
         struct pci_host_bridge *hbrg = pci_find_host_bridge(dev->bus);
 
         if (!(hbrg->map_irq)) {
-                dev_dbg(&dev->dev, "runtime IRQ mapping not provided by arch\n");
+                pci_dbg(dev, "runtime IRQ mapping not provided by arch\n");
                 return;
         }
 
@@ -56,7 +56,7 @@ void pci_assign_irq(struct pci_dev *dev)
         }
         dev->irq = irq;
 
-        dev_dbg(&dev->dev, "assign IRQ: got %d\n", dev->irq);
+        pci_dbg(dev, "assign IRQ: got %d\n", dev->irq);
 
         /* Always tell the device, so the driver knows what is
            the real IRQ to use; the device does not use it. */
diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
index e815111f3f81..369d48d6c6f1 100644
--- a/drivers/pci/setup-res.c
+++ b/drivers/pci/setup-res.c
@@ -103,7 +103,7 @@ static void pci_std_update_resource(struct pci_dev *dev, int resno)
         pci_read_config_dword(dev, reg, &check);
 
         if ((new ^ check) & mask) {
-                dev_err(&dev->dev, "BAR %d: error updating (%#08x != %#08x)\n",
+                pci_err(dev, "BAR %d: error updating (%#08x != %#08x)\n",
                         resno, new, check);
         }
 
@@ -112,7 +112,7 @@ static void pci_std_update_resource(struct pci_dev *dev, int resno)
                 pci_write_config_dword(dev, reg + 4, new);
                 pci_read_config_dword(dev, reg + 4, &check);
                 if (check != new) {
-                        dev_err(&dev->dev, "BAR %d: error updating (high %#08x != %#08x)\n",
+                        pci_err(dev, "BAR %d: error updating (high %#08x != %#08x)\n",
                                 resno, new, check);
                 }
         }
@@ -137,7 +137,7 @@ int pci_claim_resource(struct pci_dev *dev, int resource)
         struct resource *root, *conflict;
 
         if (res->flags & IORESOURCE_UNSET) {
-                dev_info(&dev->dev, "can't claim BAR %d %pR: no address assigned\n",
+                pci_info(dev, "can't claim BAR %d %pR: no address assigned\n",
                          resource, res);
                 return -EINVAL;
         }
@@ -152,7 +152,7 @@ int pci_claim_resource(struct pci_dev *dev, int resource)
 
         root = pci_find_parent_resource(dev, res);
         if (!root) {
-                dev_info(&dev->dev, "can't claim BAR %d %pR: no compatible bridge window\n",
+                pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n",
                          resource, res);
                 res->flags |= IORESOURCE_UNSET;
                 return -EINVAL;
@@ -160,7 +160,7 @@ int pci_claim_resource(struct pci_dev *dev, int resource)
 
         conflict = request_resource_conflict(root, res);
         if (conflict) {
-                dev_info(&dev->dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
+                pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
                          resource, res, conflict->name, conflict);
                 res->flags |= IORESOURCE_UNSET;
                 return -EBUSY;
@@ -172,7 +172,7 @@ EXPORT_SYMBOL(pci_claim_resource);
 
 void pci_disable_bridge_window(struct pci_dev *dev)
 {
-        dev_info(&dev->dev, "disabling bridge mem windows\n");
+        pci_info(dev, "disabling bridge mem windows\n");
 
         /* MMIO Base/Limit */
         pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
@@ -221,11 +221,11 @@ static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
                         root = &iomem_resource;
         }
 
-        dev_info(&dev->dev, "BAR %d: trying firmware assignment %pR\n",
+        pci_info(dev, "BAR %d: trying firmware assignment %pR\n",
                  resno, res);
         conflict = request_resource_conflict(root, res);
         if (conflict) {
-                dev_info(&dev->dev, "BAR %d: %pR conflicts with %s %pR\n",
+                pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n",
                          resno, res, conflict->name, conflict);
                 res->start = start;
                 res->end = end;
@@ -324,7 +324,7 @@ int pci_assign_resource(struct pci_dev *dev, int resno)
         res->flags |= IORESOURCE_UNSET;
         align = pci_resource_alignment(dev, res);
         if (!align) {
-                dev_info(&dev->dev, "BAR %d: can't assign %pR (bogus alignment)\n",
+                pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n",
                          resno, res);
                 return -EINVAL;
         }
@@ -338,19 +338,18 @@ int pci_assign_resource(struct pci_dev *dev, int resno)
          * working, which is better than just leaving it disabled.
          */
         if (ret < 0) {
-                dev_info(&dev->dev, "BAR %d: no space for %pR\n", resno, res);
+                pci_info(dev, "BAR %d: no space for %pR\n", resno, res);
                 ret = pci_revert_fw_address(res, dev, resno, size);
         }
 
         if (ret < 0) {
-                dev_info(&dev->dev, "BAR %d: failed to assign %pR\n", resno,
-                         res);
+                pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res);
                 return ret;
         }
 
         res->flags &= ~IORESOURCE_UNSET;
         res->flags &= ~IORESOURCE_STARTALIGN;
-        dev_info(&dev->dev, "BAR %d: assigned %pR\n", resno, res);
+        pci_info(dev, "BAR %d: assigned %pR\n", resno, res);
         if (resno < PCI_BRIDGE_RESOURCES)
                 pci_update_resource(dev, resno);
 
@@ -372,7 +371,7 @@ int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsiz
         flags = res->flags;
         res->flags |= IORESOURCE_UNSET;
         if (!res->parent) {
-                dev_info(&dev->dev, "BAR %d: can't reassign an unassigned resource %pR\n",
+                pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n",
                          resno, res);
                 return -EINVAL;
         }
@@ -382,14 +381,14 @@ int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsiz
         ret = _pci_assign_resource(dev, resno, new_size, min_align);
         if (ret) {
                 res->flags = flags;
-                dev_info(&dev->dev, "BAR %d: %pR (failed to expand by %#llx)\n",
+                pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n",
                          resno, res, (unsigned long long) addsize);
                 return ret;
         }
 
         res->flags &= ~IORESOURCE_UNSET;
         res->flags &= ~IORESOURCE_STARTALIGN;
-        dev_info(&dev->dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
+        pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
                  resno, res, (unsigned long long) addsize);
         if (resno < PCI_BRIDGE_RESOURCES)
                 pci_update_resource(dev, resno);
@@ -401,7 +400,7 @@ void pci_release_resource(struct pci_dev *dev, int resno)
 {
         struct resource *res = dev->resource + resno;
 
-        dev_info(&dev->dev, "BAR %d: releasing %pR\n", resno, res);
+        pci_info(dev, "BAR %d: releasing %pR\n", resno, res);
         release_resource(res);
         res->end = resource_size(res) - 1;
         res->start = 0;
@@ -477,13 +476,13 @@ int pci_enable_resources(struct pci_dev *dev, int mask)
                         continue;
 
                 if (r->flags & IORESOURCE_UNSET) {
-                        dev_err(&dev->dev, "can't enable device: BAR %d %pR not assigned\n",
+                        pci_err(dev, "can't enable device: BAR %d %pR not assigned\n",
                                 i, r);
                         return -EINVAL;
                 }
 
                 if (!r->parent) {
-                        dev_err(&dev->dev, "can't enable device: BAR %d %pR not claimed\n",
+                        pci_err(dev, "can't enable device: BAR %d %pR not claimed\n",
                                 i, r);
                         return -EINVAL;
                 }
@@ -495,8 +494,7 @@ int pci_enable_resources(struct pci_dev *dev, int mask)
         }
 
         if (cmd != old_cmd) {
-                dev_info(&dev->dev, "enabling device (%04x -> %04x)\n",
-                         old_cmd, cmd);
+                pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
                 pci_write_config_word(dev, PCI_COMMAND, cmd);
         }
         return 0;
diff --git a/drivers/pci/switch/switchtec.c b/drivers/pci/switch/switchtec.c
index 5c4c459cf092..4096c42771a2 100644
--- a/drivers/pci/switch/switchtec.c
+++ b/drivers/pci/switch/switchtec.c
@@ -698,6 +698,7 @@ static const struct event_reg {
         EV_GLB(SWITCHTEC_IOCTL_EVENT_CLI_MRPC_COMP_ASYNC,
                cli_mrpc_comp_async_hdr),
         EV_GLB(SWITCHTEC_IOCTL_EVENT_GPIO_INT, gpio_interrupt_hdr),
+        EV_GLB(SWITCHTEC_IOCTL_EVENT_GFMS, gfms_event_hdr),
         EV_PAR(SWITCHTEC_IOCTL_EVENT_PART_RESET, part_reset_hdr),
         EV_PAR(SWITCHTEC_IOCTL_EVENT_MRPC_COMP, mrpc_comp_hdr),
         EV_PAR(SWITCHTEC_IOCTL_EVENT_MRPC_COMP_ASYNC, mrpc_comp_async_hdr),
@@ -1343,6 +1344,8 @@ static const struct pci_device_id switchtec_pci_tbl[] = {
         SWITCHTEC_PCI_DEVICE(0x8534),  //PFX 64xG3
         SWITCHTEC_PCI_DEVICE(0x8535),  //PFX 80xG3
         SWITCHTEC_PCI_DEVICE(0x8536),  //PFX 96xG3
+        SWITCHTEC_PCI_DEVICE(0x8541),  //PSX 24xG3
+        SWITCHTEC_PCI_DEVICE(0x8542),  //PSX 32xG3
         SWITCHTEC_PCI_DEVICE(0x8543),  //PSX 48xG3
         SWITCHTEC_PCI_DEVICE(0x8544),  //PSX 64xG3
         SWITCHTEC_PCI_DEVICE(0x8545),  //PSX 80xG3
diff --git a/drivers/pci/syscall.c b/drivers/pci/syscall.c
index 83efa001c2e7..e725f99b5479 100644
--- a/drivers/pci/syscall.c
+++ b/drivers/pci/syscall.c
@@ -28,7 +28,7 @@ SYSCALL_DEFINE5(pciconfig_read, unsigned long, bus, unsigned long, dfn,
                 return -EPERM;
 
         err = -ENODEV;
-        dev = pci_get_bus_and_slot(bus, dfn);
+        dev = pci_get_domain_bus_and_slot(0, bus, dfn);
         if (!dev)
                 goto error;
 
@@ -96,7 +96,7 @@ SYSCALL_DEFINE5(pciconfig_write, unsigned long, bus, unsigned long, dfn,
         if (!capable(CAP_SYS_ADMIN))
                 return -EPERM;
 
-        dev = pci_get_bus_and_slot(bus, dfn);
+        dev = pci_get_domain_bus_and_slot(0, bus, dfn);
         if (!dev)
                 return -ENODEV;
 
diff --git a/drivers/pci/vc.c b/drivers/pci/vc.c
index 825c4bddb5fd..5acd9c02683a 100644
--- a/drivers/pci/vc.c
+++ b/drivers/pci/vc.c
@@ -54,7 +54,7 @@ static void pci_vc_load_arb_table(struct pci_dev *dev, int pos)
                                  PCI_VC_PORT_STATUS_TABLE))
                 return;
 
-        dev_err(&dev->dev, "VC arbitration table failed to load\n");
+        pci_err(dev, "VC arbitration table failed to load\n");
 }
 
 /**
@@ -82,7 +82,7 @@ static void pci_vc_load_port_arb_table(struct pci_dev *dev, int pos, int res)
         if (pci_wait_for_pending(dev, status_pos, PCI_VC_RES_STATUS_TABLE))
                 return;
 
-        dev_err(&dev->dev, "VC%d port arbitration table failed to load\n", res);
+        pci_err(dev, "VC%d port arbitration table failed to load\n", res);
 }
 
 /**
@@ -158,11 +158,11 @@ enable:
         pci_write_config_dword(dev, ctrl_pos, ctrl);
 
         if (!pci_wait_for_pending(dev, status_pos, PCI_VC_RES_STATUS_NEGO))
-                dev_err(&dev->dev, "VC%d negotiation stuck pending\n", id);
+                pci_err(dev, "VC%d negotiation stuck pending\n", id);
 
         if (link && !pci_wait_for_pending(link, status_pos2,
                                           PCI_VC_RES_STATUS_NEGO))
-                dev_err(&link->dev, "VC%d negotiation stuck pending\n", id);
+                pci_err(link, "VC%d negotiation stuck pending\n", id);
 }
 
 /**
@@ -192,8 +192,7 @@ static int pci_vc_do_save_buffer(struct pci_dev *dev, int pos,
         /* Sanity check buffer size for save/restore */
         if (buf && save_state->cap.size !=
             pci_vc_do_save_buffer(dev, pos, NULL, save)) {
-                dev_err(&dev->dev,
-                        "VC save buffer size does not match @0x%x\n", pos);
+                pci_err(dev, "VC save buffer size does not match @0x%x\n", pos);
                 return -ENOMEM;
         }
 
@@ -363,14 +362,14 @@ int pci_save_vc_state(struct pci_dev *dev)
 
                 save_state = pci_find_saved_ext_cap(dev, vc_caps[i].id);
                 if (!save_state) {
-                        dev_err(&dev->dev, "%s buffer not found in %s\n",
+                        pci_err(dev, "%s buffer not found in %s\n",
                                 vc_caps[i].name, __func__);
                         return -ENOMEM;
                 }
 
                 ret = pci_vc_do_save_buffer(dev, pos, save_state, true);
                 if (ret) {
-                        dev_err(&dev->dev, "%s save unsuccessful %s\n",
+                        pci_err(dev, "%s save unsuccessful %s\n",
                                 vc_caps[i].name, __func__);
                         return ret;
                 }
@@ -423,8 +422,7 @@ void pci_allocate_vc_save_buffers(struct pci_dev *dev)
 
                 len = pci_vc_do_save_buffer(dev, pos, NULL, false);
                 if (pci_add_ext_cap_save_buffer(dev, vc_caps[i].id, len))
-                        dev_err(&dev->dev,
-                                "unable to preallocate %s save buffer\n",
+                        pci_err(dev, "unable to preallocate %s save buffer\n",
                                 vc_caps[i].name);
         }
 }
diff --git a/drivers/pci/xen-pcifront.c b/drivers/pci/xen-pcifront.c
index 82fe8526ac90..8785014f656e 100644
--- a/drivers/pci/xen-pcifront.c
+++ b/drivers/pci/xen-pcifront.c
@@ -262,8 +262,8 @@ static int pci_frontend_enable_msix(struct pci_dev *dev,
         struct msi_desc *entry;
 
         if (nvec > SH_INFO_MAX_VEC) {
-                dev_err(&dev->dev, "too much vector for pci frontend: %x."
-                                   " Increase SH_INFO_MAX_VEC.\n", nvec);
+                pci_err(dev, "too many vectors (0x%x) for PCI frontend:"
+                                   " Increase SH_INFO_MAX_VEC\n", nvec);
                 return -EINVAL;
         }
 
@@ -282,7 +282,7 @@ static int pci_frontend_enable_msix(struct pci_dev *dev,
                         /* we get the result */
                         for (i = 0; i < nvec; i++) {
                                 if (op.msix_entries[i].vector <= 0) {
-                                        dev_warn(&dev->dev, "MSI-X entry %d is invalid: %d!\n",
+                                        pci_warn(dev, "MSI-X entry %d is invalid: %d!\n",
                                                 i, op.msix_entries[i].vector);
                                         err = -EINVAL;
                                         vector[i] = -1;
@@ -296,7 +296,7 @@ static int pci_frontend_enable_msix(struct pci_dev *dev,
                         err = op.value;
                 }
         } else {
-                dev_err(&dev->dev, "enable msix get err %x\n", err);
+                pci_err(dev, "enable msix get err %x\n", err);
         }
         return err;
 }
@@ -317,7 +317,7 @@ static void pci_frontend_disable_msix(struct pci_dev *dev)
 
         /* What should do for error ? */
         if (err)
-                dev_err(&dev->dev, "pci_disable_msix get err %x\n", err);
+                pci_err(dev, "pci_disable_msix get err %x\n", err);
 }
 
 static int pci_frontend_enable_msi(struct pci_dev *dev, int vector[])
@@ -336,13 +336,13 @@ static int pci_frontend_enable_msi(struct pci_dev *dev, int vector[])
         if (likely(!err)) {
                 vector[0] = op.value;
                 if (op.value <= 0) {
-                        dev_warn(&dev->dev, "MSI entry is invalid: %d!\n",
+                        pci_warn(dev, "MSI entry is invalid: %d!\n",
                                 op.value);
                         err = -EINVAL;
                         vector[0] = -1;
                 }
         } else {
-                dev_err(&dev->dev, "pci frontend enable msi failed for dev "
+                pci_err(dev, "pci frontend enable msi failed for dev "
                                     "%x:%x\n", op.bus, op.devfn);
                 err = -EINVAL;
         }
@@ -561,7 +561,7 @@ static void free_root_bus_devs(struct pci_bus *bus)
         while (!list_empty(&bus->devices)) {
                 dev = container_of(bus->devices.next, struct pci_dev,
                                    bus_list);
-                dev_dbg(&dev->dev, "removing device\n");
+                pci_dbg(dev, "removing device\n");
                 pci_stop_and_remove_bus_device(dev);
         }
 }
@@ -596,6 +596,7 @@ static pci_ers_result_t pcifront_common_process(int cmd,
         struct pci_driver *pdrv;
         int bus = pdev->sh_info->aer_op.bus;
         int devfn = pdev->sh_info->aer_op.devfn;
+        int domain = pdev->sh_info->aer_op.domain;
         struct pci_dev *pcidev;
         int flag = 0;
 
@@ -604,7 +605,7 @@ static pci_ers_result_t pcifront_common_process(int cmd,
                 cmd, bus, devfn);
         result = PCI_ERS_RESULT_NONE;
 
-        pcidev = pci_get_bus_and_slot(bus, devfn);
+        pcidev = pci_get_domain_bus_and_slot(domain, bus, devfn);
         if (!pcidev || !pcidev->driver) {
                 dev_err(&pdev->xdev->dev, "device or AER driver is NULL\n");
                 pci_dev_put(pcidev);
@@ -614,8 +615,7 @@ static pci_ers_result_t pcifront_common_process(int cmd,
 
         if (pdrv) {
                 if (pdrv->err_handler && pdrv->err_handler->error_detected) {
-                        dev_dbg(&pcidev->dev,
-                                "trying to call AER service\n");
+                        pci_dbg(pcidev, "trying to call AER service\n");
                         if (pcidev) {
                                 flag = 1;
                                 switch (cmd) {
diff --git a/drivers/sbus/char/openprom.c b/drivers/sbus/char/openprom.c
index 2c2e6a3b4c7e..7b31f19ade83 100644
--- a/drivers/sbus/char/openprom.c
+++ b/drivers/sbus/char/openprom.c
@@ -251,8 +251,9 @@ static int oprompci2node(void __user *argp, struct device_node *dp, struct openp
                 struct pci_dev *pdev;
                 struct device_node *dp;
 
-                pdev = pci_get_bus_and_slot (((int *) op->oprom_array)[0],
-                                      ((int *) op->oprom_array)[1]);
+                pdev = pci_get_domain_bus_and_slot(0,
+                                                ((int *) op->oprom_array)[0],
+                                                ((int *) op->oprom_array)[1]);
 
                 dp = pci_device_to_OF_node(pdev);
                 data->current_node = dp;
diff --git a/drivers/video/console/vgacon.c b/drivers/video/console/vgacon.c
index 445b1dc5d441..a17ba1465815 100644
--- a/drivers/video/console/vgacon.c
+++ b/drivers/video/console/vgacon.c
@@ -422,7 +422,10 @@ static const char *vgacon_startup(void)
                 vga_video_port_val = VGA_CRT_DM;
                 if ((screen_info.orig_video_ega_bx & 0xff) != 0x10) {
                         static struct resource ega_console_resource =
-                            { .name = "ega", .start = 0x3B0, .end = 0x3BF };
+                            { .name     = "ega",
+                              .flags    = IORESOURCE_IO,
+                              .start    = 0x3B0,
+                              .end      = 0x3BF };
                         vga_video_type = VIDEO_TYPE_EGAM;
                         vga_vram_size = 0x8000;
                         display_desc = "EGA+";
@@ -430,9 +433,15 @@ static const char *vgacon_startup(void)
                                          &ega_console_resource);
                 } else {
                         static struct resource mda1_console_resource =
-                            { .name = "mda", .start = 0x3B0, .end = 0x3BB };
+                            { .name     = "mda",
+                              .flags    = IORESOURCE_IO,
+                              .start    = 0x3B0,
+                              .end      = 0x3BB };
                         static struct resource mda2_console_resource =
-                            { .name = "mda", .start = 0x3BF, .end = 0x3BF };
+                            { .name     = "mda",
+                              .flags    = IORESOURCE_IO,
+                              .start    = 0x3BF,
+                              .end      = 0x3BF };
                         vga_video_type = VIDEO_TYPE_MDA;
                         vga_vram_size = 0x2000;
                         display_desc = "*MDA";
@@ -454,15 +463,21 @@ static const char *vgacon_startup(void)
                         vga_vram_size = 0x8000;
 
                         if (!screen_info.orig_video_isVGA) {
-                                static struct resource ega_console_resource
-                                    = { .name = "ega", .start = 0x3C0, .end = 0x3DF };
+                                static struct resource ega_console_resource =
+                                    { .name     = "ega",
+                                      .flags    = IORESOURCE_IO,
+                                      .start    = 0x3C0,
+                                      .end      = 0x3DF };
                                 vga_video_type = VIDEO_TYPE_EGAC;
                                 display_desc = "EGA";
                                 request_resource(&ioport_resource,
                                                  &ega_console_resource);
                         } else {
-                                static struct resource vga_console_resource
-                                    = { .name = "vga+", .start = 0x3C0, .end = 0x3DF };
+                                static struct resource vga_console_resource =
+                                    { .name     = "vga+",
+                                      .flags    = IORESOURCE_IO,
+                                      .start    = 0x3C0,
+                                      .end      = 0x3DF };
                                 vga_video_type = VIDEO_TYPE_VGAC;
                                 display_desc = "VGA+";
                                 request_resource(&ioport_resource,
@@ -494,7 +509,10 @@ static const char *vgacon_startup(void)
                         }
                 } else {
                         static struct resource cga_console_resource =
-                            { .name = "cga", .start = 0x3D4, .end = 0x3D5 };
+                            { .name     = "cga",
+                              .flags    = IORESOURCE_IO,
+                              .start    = 0x3D4,
+                              .end      = 0x3D5 };
                         vga_video_type = VIDEO_TYPE_CGA;
                         vga_vram_size = 0x2000;
                         display_desc = "*CGA";
diff --git a/drivers/video/fbdev/intelfb/intelfbhw.c b/drivers/video/fbdev/intelfb/intelfbhw.c
index 83fec573cceb..57aff7450bce 100644
--- a/drivers/video/fbdev/intelfb/intelfbhw.c
+++ b/drivers/video/fbdev/intelfb/intelfbhw.c
@@ -181,7 +181,9 @@ int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
                 return 1;
 
         /* Find the bridge device.  It is always 0:0.0 */
-        if (!(bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)))) {
+        bridge_dev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 0,
+                                                 PCI_DEVFN(0, 0));
+        if (!bridge_dev) {
                 ERR_MSG("cannot find bridge device\n");
                 return 1;
         }
diff --git a/drivers/video/fbdev/nvidia/nv_hw.c b/drivers/video/fbdev/nvidia/nv_hw.c
index 81c80ac3c76f..8335da4ca30e 100644
--- a/drivers/video/fbdev/nvidia/nv_hw.c
+++ b/drivers/video/fbdev/nvidia/nv_hw.c
@@ -683,10 +683,11 @@ static void nForceUpdateArbitrationSettings(unsigned VClk,
         nv10_sim_state sim_data;
         unsigned int M, N, P, pll, MClk, NVClk, memctrl;
         struct pci_dev *dev;
+        int domain = pci_domain_nr(par->pci_dev->bus);
 
         if ((par->Chipset & 0x0FF0) == 0x01A0) {
                 unsigned int uMClkPostDiv;
-                dev = pci_get_bus_and_slot(0, 3);
+                dev = pci_get_domain_bus_and_slot(domain, 0, 3);
                 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
                 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
 
@@ -694,7 +695,7 @@ static void nForceUpdateArbitrationSettings(unsigned VClk,
                         uMClkPostDiv = 4;
                 MClk = 400000 / uMClkPostDiv;
         } else {
-                dev = pci_get_bus_and_slot(0, 5);
+                dev = pci_get_domain_bus_and_slot(domain, 0, 5);
                 pci_read_config_dword(dev, 0x4c, &MClk);
                 MClk /= 1000;
         }
@@ -707,13 +708,13 @@ static void nForceUpdateArbitrationSettings(unsigned VClk,
         sim_data.pix_bpp = (char)pixelDepth;
         sim_data.enable_video = 0;
         sim_data.enable_mp = 0;
-        dev = pci_get_bus_and_slot(0, 1);
+        dev = pci_get_domain_bus_and_slot(domain, 0, 1);
         pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
         pci_dev_put(dev);
         sim_data.memory_type = (sim_data.memory_type >> 12) & 1;
         sim_data.memory_width = 64;
 
-        dev = pci_get_bus_and_slot(0, 3);
+        dev = pci_get_domain_bus_and_slot(domain, 0, 3);
         pci_read_config_dword(dev, 0, &memctrl);
         pci_dev_put(dev);
         memctrl >>= 16;
@@ -721,7 +722,7 @@ static void nForceUpdateArbitrationSettings(unsigned VClk,
         if ((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) {
                 u32 dimm[3];
 
-                dev = pci_get_bus_and_slot(0, 2);
+                dev = pci_get_domain_bus_and_slot(domain, 0, 2);
                 pci_read_config_dword(dev, 0x40, &dimm[0]);
                 dimm[0] = (dimm[0] >> 8) & 0x4f;
                 pci_read_config_dword(dev, 0x44, &dimm[1]);
diff --git a/drivers/video/fbdev/nvidia/nv_setup.c b/drivers/video/fbdev/nvidia/nv_setup.c
index 2f2e162134fa..b17acd290360 100644
--- a/drivers/video/fbdev/nvidia/nv_setup.c
+++ b/drivers/video/fbdev/nvidia/nv_setup.c
@@ -264,7 +264,8 @@ static void nv10GetConfig(struct nvidia_par *par)
         }
 #endif
 
-        dev = pci_get_bus_and_slot(0, 1);
+        dev = pci_get_domain_bus_and_slot(pci_domain_nr(par->pci_dev->bus),
+                                          0, 1);
         if ((par->Chipset & 0xffff) == 0x01a0) {
                 u32 amt;
 
diff --git a/drivers/video/fbdev/riva/fbdev.c b/drivers/video/fbdev/riva/fbdev.c
index 1ea78bb911fb..ff8282374f37 100644
--- a/drivers/video/fbdev/riva/fbdev.c
+++ b/drivers/video/fbdev/riva/fbdev.c
@@ -780,7 +780,7 @@ static int riva_load_video_mode(struct fb_info *info)
         else
                 newmode.misc_output |= 0x80;    
 
-        rc = CalcStateExt(&par->riva, &newmode.ext, bpp, width,
+        rc = CalcStateExt(&par->riva, &newmode.ext, par->pdev, bpp, width,
                           hDisplaySize, height, dotClock);
         if (rc)
                 goto out;
diff --git a/drivers/video/fbdev/riva/nv_driver.c b/drivers/video/fbdev/riva/nv_driver.c
index f3694cf17e58..a3d9c66973ad 100644
--- a/drivers/video/fbdev/riva/nv_driver.c
+++ b/drivers/video/fbdev/riva/nv_driver.c
@@ -159,6 +159,7 @@ unsigned long riva_get_memlen(struct riva_par *par)
         unsigned int chipset = par->Chipset;
         struct pci_dev* dev;
         u32 amt;
+        int domain = pci_domain_nr(par->pdev->bus);
 
         switch (chip->Architecture) {
         case NV_ARCH_03:
@@ -226,12 +227,12 @@ unsigned long riva_get_memlen(struct riva_par *par)
         case NV_ARCH_30:
                 if(chipset == NV_CHIP_IGEFORCE2) {
 
-                        dev = pci_get_bus_and_slot(0, 1);
+                        dev = pci_get_domain_bus_and_slot(domain, 0, 1);
                         pci_read_config_dword(dev, 0x7C, &amt);
                         pci_dev_put(dev);
                         memlen = (((amt >> 6) & 31) + 1) * 1024;
                 } else if (chipset == NV_CHIP_0x01F0) {
-                        dev = pci_get_bus_and_slot(0, 1);
+                        dev = pci_get_domain_bus_and_slot(domain, 0, 1);
                         pci_read_config_dword(dev, 0x84, &amt);
                         pci_dev_put(dev);
                         memlen = (((amt >> 4) & 127) + 1) * 1024;
@@ -417,6 +418,6 @@ riva_common_setup(struct riva_par *par)
         }
         par->riva.flatPanel = (par->FlatPanel > 0) ? TRUE : FALSE;
 
-        RivaGetConfig(&par->riva, par->Chipset);
+        RivaGetConfig(&par->riva, par->pdev, par->Chipset);
 }
 
diff --git a/drivers/video/fbdev/riva/riva_hw.c b/drivers/video/fbdev/riva/riva_hw.c
index 8bdf37f3013b..0601c13f2105 100644
--- a/drivers/video/fbdev/riva/riva_hw.c
+++ b/drivers/video/fbdev/riva/riva_hw.c
@@ -1108,7 +1108,8 @@ static void nForceUpdateArbitrationSettings
     unsigned      pixelDepth,
     unsigned     *burst,
     unsigned     *lwm,
-    RIVA_HW_INST *chip
+    RIVA_HW_INST *chip,
+    struct pci_dev *pdev
 )
 {
     nv10_fifo_info fifo_data;
@@ -1116,8 +1117,9 @@ static void nForceUpdateArbitrationSettings
     unsigned int M, N, P, pll, MClk, NVClk;
     unsigned int uMClkPostDiv;
     struct pci_dev *dev;
+    int domain = pci_domain_nr(pdev->bus);
 
-    dev = pci_get_bus_and_slot(0, 3);
+    dev = pci_get_domain_bus_and_slot(domain, 0, 3);
     pci_read_config_dword(dev, 0x6C, &uMClkPostDiv);
     pci_dev_put(dev);
     uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf;
@@ -1132,7 +1134,7 @@ static void nForceUpdateArbitrationSettings
     sim_data.enable_video   = 0;
     sim_data.enable_mp      = 0;
 
-    dev = pci_get_bus_and_slot(0, 1);
+    dev = pci_get_domain_bus_and_slot(domain, 0, 1);
     pci_read_config_dword(dev, 0x7C, &sim_data.memory_type);
     pci_dev_put(dev);
     sim_data.memory_type    = (sim_data.memory_type >> 12) & 1;
@@ -1234,6 +1236,7 @@ int CalcStateExt
 (
     RIVA_HW_INST  *chip,
     RIVA_HW_STATE *state,
+    struct pci_dev *pdev,
     int            bpp,
     int            width,
     int            hDisplaySize,
@@ -1300,7 +1303,7 @@ int CalcStateExt
                                           pixelDepth * 8,
                                          &(state->arbitration0),
                                          &(state->arbitration1),
-                                          chip);
+                                          chip, pdev);
             } else {
                 nv10UpdateArbitrationSettings(VClk, 
                                           pixelDepth * 8, 
@@ -2102,10 +2105,12 @@ static void nv4GetConfig
 static void nv10GetConfig
 (
     RIVA_HW_INST *chip,
+    struct pci_dev *pdev,
     unsigned int chipset
 )
 {
     struct pci_dev* dev;
+    int domain = pci_domain_nr(pdev->bus);
     u32 amt;
 
 #ifdef __BIG_ENDIAN
@@ -2118,12 +2123,12 @@ static void nv10GetConfig
      * Fill in chip configuration.
      */
     if(chipset == NV_CHIP_IGEFORCE2) {
-        dev = pci_get_bus_and_slot(0, 1);
+        dev = pci_get_domain_bus_and_slot(domain, 0, 1);
         pci_read_config_dword(dev, 0x7C, &amt);
         pci_dev_put(dev);
         chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
     } else if(chipset == NV_CHIP_0x01F0) {
-        dev = pci_get_bus_and_slot(0, 1);
+        dev = pci_get_domain_bus_and_slot(domain, 0, 1);
         pci_read_config_dword(dev, 0x84, &amt);
         pci_dev_put(dev);
         chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
@@ -2224,6 +2229,7 @@ static void nv10GetConfig
 int RivaGetConfig
 (
     RIVA_HW_INST *chip,
+    struct pci_dev *pdev,
     unsigned int chipset
 )
 {
@@ -2245,7 +2251,7 @@ int RivaGetConfig
         case NV_ARCH_10:
         case NV_ARCH_20:
         case NV_ARCH_30:
-            nv10GetConfig(chip, chipset);
+            nv10GetConfig(chip, pdev, chipset);
             break;
         default:
             return (-1);
diff --git a/drivers/video/fbdev/riva/riva_hw.h b/drivers/video/fbdev/riva/riva_hw.h
index c2769f73e0b2..5e7b35466b00 100644
--- a/drivers/video/fbdev/riva/riva_hw.h
+++ b/drivers/video/fbdev/riva/riva_hw.h
@@ -536,6 +536,7 @@ extern int CalcStateExt
 (
     RIVA_HW_INST  *chip,
     RIVA_HW_STATE *state,
+    struct pci_dev *pdev,
     int            bpp,
     int            width,
     int            hDisplaySize,
@@ -546,7 +547,7 @@ extern int CalcStateExt
 /*
  * External routines.
  */
-int RivaGetConfig(RIVA_HW_INST *, unsigned int);
+int RivaGetConfig(RIVA_HW_INST *chip, struct pci_dev *pdev, unsigned int c);
 /*
  * FIFO Free Count. Should attempt to yield processor if RIVA is busy.
  */
diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h
index bf588a05d0d0..88865e0ebf4d 100644
--- a/include/linux/of_pci.h
+++ b/include/linux/of_pci.h
@@ -9,8 +9,7 @@ struct pci_dev;
 struct of_phandle_args;
 struct device_node;
 
-#ifdef CONFIG_OF_PCI
-int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *out_irq);
+#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_PCI)
 struct device_node *of_pci_find_child_device(struct device_node *parent,
                                              unsigned int devfn);
 int of_pci_get_devfn(struct device_node *np);
@@ -23,11 +22,6 @@ int of_pci_map_rid(struct device_node *np, u32 rid,
                    const char *map_name, const char *map_mask_name,
                    struct device_node **target, u32 *id_out);
 #else
-static inline int of_irq_parse_pci(const struct pci_dev *pdev, struct of_phandle_args *out_irq)
-{
-        return 0;
-}
-
 static inline struct device_node *of_pci_find_child_device(struct device_node *parent,
                                              unsigned int devfn)
 {
diff --git a/include/linux/pci-aspm.h b/include/linux/pci-aspm.h
index 3cc06b059017..df28af5cef21 100644
--- a/include/linux/pci-aspm.h
+++ b/include/linux/pci-aspm.h
@@ -24,43 +24,12 @@
 #define PCIE_LINK_STATE_CLKPM   4
 
 #ifdef CONFIG_PCIEASPM
-void pcie_aspm_init_link_state(struct pci_dev *pdev);
-void pcie_aspm_exit_link_state(struct pci_dev *pdev);
-void pcie_aspm_pm_state_change(struct pci_dev *pdev);
-void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
 void pci_disable_link_state(struct pci_dev *pdev, int state);
 void pci_disable_link_state_locked(struct pci_dev *pdev, int state);
 void pcie_no_aspm(void);
 #else
-static inline void pcie_aspm_init_link_state(struct pci_dev *pdev)
-{
-}
-static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev)
-{
-}
-static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev)
-{
-}
-static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
-{
-}
-static inline void pci_disable_link_state(struct pci_dev *pdev, int state)
-{
-}
-static inline void pcie_no_aspm(void)
-{
-}
+static inline void pci_disable_link_state(struct pci_dev *pdev, int state) { }
+static inline void pcie_no_aspm(void) { }
 #endif
 
-#ifdef CONFIG_PCIEASPM_DEBUG /* this depends on CONFIG_PCIEASPM */
-void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
-void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
-#else
-static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
-{
-}
-static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
-{
-}
-#endif
 #endif /* LINUX_ASPM_H */
diff --git a/include/linux/pci-dma-compat.h b/include/linux/pci-dma-compat.h
index d1f9fdade1e0..0dd1a3f7b309 100644
--- a/include/linux/pci-dma-compat.h
+++ b/include/linux/pci-dma-compat.h
@@ -17,91 +17,90 @@ static inline void *
 pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
                      dma_addr_t *dma_handle)
 {
-        return dma_alloc_coherent(hwdev == NULL ? NULL : &hwdev->dev, size, dma_handle, GFP_ATOMIC);
+        return dma_alloc_coherent(&hwdev->dev, size, dma_handle, GFP_ATOMIC);
 }
 
 static inline void *
 pci_zalloc_consistent(struct pci_dev *hwdev, size_t size,
                       dma_addr_t *dma_handle)
 {
-        return dma_zalloc_coherent(hwdev == NULL ? NULL : &hwdev->dev,
-                                   size, dma_handle, GFP_ATOMIC);
+        return dma_zalloc_coherent(&hwdev->dev, size, dma_handle, GFP_ATOMIC);
 }
 
 static inline void
 pci_free_consistent(struct pci_dev *hwdev, size_t size,
                     void *vaddr, dma_addr_t dma_handle)
 {
-        dma_free_coherent(hwdev == NULL ? NULL : &hwdev->dev, size, vaddr, dma_handle);
+        dma_free_coherent(&hwdev->dev, size, vaddr, dma_handle);
 }
 
 static inline dma_addr_t
 pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction)
 {
-        return dma_map_single(hwdev == NULL ? NULL : &hwdev->dev, ptr, size, (enum dma_data_direction)direction);
+        return dma_map_single(&hwdev->dev, ptr, size, (enum dma_data_direction)direction);
 }
 
 static inline void
 pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
                  size_t size, int direction)
 {
-        dma_unmap_single(hwdev == NULL ? NULL : &hwdev->dev, dma_addr, size, (enum dma_data_direction)direction);
+        dma_unmap_single(&hwdev->dev, dma_addr, size, (enum dma_data_direction)direction);
 }
 
 static inline dma_addr_t
 pci_map_page(struct pci_dev *hwdev, struct page *page,
              unsigned long offset, size_t size, int direction)
 {
-        return dma_map_page(hwdev == NULL ? NULL : &hwdev->dev, page, offset, size, (enum dma_data_direction)direction);
+        return dma_map_page(&hwdev->dev, page, offset, size, (enum dma_data_direction)direction);
 }
 
 static inline void
 pci_unmap_page(struct pci_dev *hwdev, dma_addr_t dma_address,
                size_t size, int direction)
 {
-        dma_unmap_page(hwdev == NULL ? NULL : &hwdev->dev, dma_address, size, (enum dma_data_direction)direction);
+        dma_unmap_page(&hwdev->dev, dma_address, size, (enum dma_data_direction)direction);
 }
 
 static inline int
 pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
            int nents, int direction)
 {
-        return dma_map_sg(hwdev == NULL ? NULL : &hwdev->dev, sg, nents, (enum dma_data_direction)direction);
+        return dma_map_sg(&hwdev->dev, sg, nents, (enum dma_data_direction)direction);
 }
 
 static inline void
 pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
              int nents, int direction)
 {
-        dma_unmap_sg(hwdev == NULL ? NULL : &hwdev->dev, sg, nents, (enum dma_data_direction)direction);
+        dma_unmap_sg(&hwdev->dev, sg, nents, (enum dma_data_direction)direction);
 }
 
 static inline void
 pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t dma_handle,
                     size_t size, int direction)
 {
-        dma_sync_single_for_cpu(hwdev == NULL ? NULL : &hwdev->dev, dma_handle, size, (enum dma_data_direction)direction);
+        dma_sync_single_for_cpu(&hwdev->dev, dma_handle, size, (enum dma_data_direction)direction);
 }
 
 static inline void
 pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t dma_handle,
                     size_t size, int direction)
 {
-        dma_sync_single_for_device(hwdev == NULL ? NULL : &hwdev->dev, dma_handle, size, (enum dma_data_direction)direction);
+        dma_sync_single_for_device(&hwdev->dev, dma_handle, size, (enum dma_data_direction)direction);
 }
 
 static inline void
 pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sg,
                 int nelems, int direction)
 {
-        dma_sync_sg_for_cpu(hwdev == NULL ? NULL : &hwdev->dev, sg, nelems, (enum dma_data_direction)direction);
+        dma_sync_sg_for_cpu(&hwdev->dev, sg, nelems, (enum dma_data_direction)direction);
 }
 
 static inline void
 pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sg,
                 int nelems, int direction)
 {
-        dma_sync_sg_for_device(hwdev == NULL ? NULL : &hwdev->dev, sg, nelems, (enum dma_data_direction)direction);
+        dma_sync_sg_for_device(&hwdev->dev, sg, nelems, (enum dma_data_direction)direction);
 }
 
 static inline int
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index 573730d490a7..a1a5e5df0f66 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -36,17 +36,20 @@ enum pci_epc_irq_type {
  * @owner: the module owner containing the ops
  */
 struct pci_epc_ops {
-        int     (*write_header)(struct pci_epc *pci_epc,
+        int     (*write_header)(struct pci_epc *epc, u8 func_no,
                                 struct pci_epf_header *hdr);
-        int     (*set_bar)(struct pci_epc *epc, enum pci_barno bar,
+        int     (*set_bar)(struct pci_epc *epc, u8 func_no,
+                           enum pci_barno bar,
                            dma_addr_t bar_phys, size_t size, int flags);
-        void    (*clear_bar)(struct pci_epc *epc, enum pci_barno bar);
-        int     (*map_addr)(struct pci_epc *epc, phys_addr_t addr,
-                            u64 pci_addr, size_t size);
-        void    (*unmap_addr)(struct pci_epc *epc, phys_addr_t addr);
-        int     (*set_msi)(struct pci_epc *epc, u8 interrupts);
-        int     (*get_msi)(struct pci_epc *epc);
-        int     (*raise_irq)(struct pci_epc *pci_epc,
+        void    (*clear_bar)(struct pci_epc *epc, u8 func_no,
+                             enum pci_barno bar);
+        int     (*map_addr)(struct pci_epc *epc, u8 func_no,
+                            phys_addr_t addr, u64 pci_addr, size_t size);
+        void    (*unmap_addr)(struct pci_epc *epc, u8 func_no,
+                              phys_addr_t addr);
+        int     (*set_msi)(struct pci_epc *epc, u8 func_no, u8 interrupts);
+        int     (*get_msi)(struct pci_epc *epc, u8 func_no);
+        int     (*raise_irq)(struct pci_epc *epc, u8 func_no,
                              enum pci_epc_irq_type type, u8 interrupt_num);
         int     (*start)(struct pci_epc *epc);
         void    (*stop)(struct pci_epc *epc);
@@ -121,17 +124,21 @@ void pci_epc_destroy(struct pci_epc *epc);
 int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf);
 void pci_epc_linkup(struct pci_epc *epc);
 void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf);
-int pci_epc_write_header(struct pci_epc *epc, struct pci_epf_header *hdr);
-int pci_epc_set_bar(struct pci_epc *epc, enum pci_barno bar,
+int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
+                         struct pci_epf_header *hdr);
+int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
+                    enum pci_barno bar,
                     dma_addr_t bar_phys, size_t size, int flags);
-void pci_epc_clear_bar(struct pci_epc *epc, int bar);
-int pci_epc_map_addr(struct pci_epc *epc, phys_addr_t phys_addr,
+void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no, int bar);
+int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
+                     phys_addr_t phys_addr,
                      u64 pci_addr, size_t size);
-void pci_epc_unmap_addr(struct pci_epc *epc, phys_addr_t phys_addr);
-int pci_epc_set_msi(struct pci_epc *epc, u8 interrupts);
-int pci_epc_get_msi(struct pci_epc *epc);
-int pci_epc_raise_irq(struct pci_epc *epc, enum pci_epc_irq_type type,
-                      u8 interrupt_num);
+void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
+                        phys_addr_t phys_addr);
+int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts);
+int pci_epc_get_msi(struct pci_epc *epc, u8 func_no);
+int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
+                      enum pci_epc_irq_type type, u8 interrupt_num);
 int pci_epc_start(struct pci_epc *epc);
 void pci_epc_stop(struct pci_epc *epc);
 struct pci_epc *pci_epc_get(const char *epc_name);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index c170c9250c8b..43dcecd6533d 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -48,17 +48,17 @@
  * In the interest of not exposing interfaces to user-space unnecessarily,
  * the following kernel-only defines are being added here.
  */
-#define PCI_DEVID(bus, devfn)  ((((u16)(bus)) << 8) | (devfn))
+#define PCI_DEVID(bus, devfn)   ((((u16)(bus)) << 8) | (devfn))
 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
 
 /* pci_slot represents a physical slot */
 struct pci_slot {
-        struct pci_bus *bus;            /* The bus this slot is on */
-        struct list_head list;          /* node in list of slots on this bus */
-        struct hotplug_slot *hotplug;   /* Hotplug info (migrate over time) */
-        unsigned char number;           /* PCI_SLOT(pci_dev->devfn) */
-        struct kobject kobj;
+        struct pci_bus          *bus;           /* Bus this slot is on */
+        struct list_head        list;           /* Node in list of slots */
+        struct hotplug_slot     *hotplug;       /* Hotplug info (move here) */
+        unsigned char           number;         /* PCI_SLOT(pci_dev->devfn) */
+        struct kobject          kobj;
 };
 
 static inline const char *pci_slot_name(const struct pci_slot *slot)
@@ -72,9 +72,7 @@ enum pci_mmap_state {
         pci_mmap_mem
 };
 
-/*
- *  For PCI devices, the region numbers are assigned this way:
- */
+/* For PCI devices, the region numbers are assigned this way: */
 enum {
         /* #0-5: standard PCI resources */
         PCI_STD_RESOURCES,
@@ -83,23 +81,23 @@ enum {
         /* #6: expansion ROM resource */
         PCI_ROM_RESOURCE,
 
-        /* device specific resources */
+        /* Device-specific resources */
 #ifdef CONFIG_PCI_IOV
         PCI_IOV_RESOURCES,
         PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
 #endif
 
-        /* resources assigned to buses behind the bridge */
+        /* Resources assigned to buses behind the bridge */
 #define PCI_BRIDGE_RESOURCE_NUM 4
 
         PCI_BRIDGE_RESOURCES,
         PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
                                   PCI_BRIDGE_RESOURCE_NUM - 1,
 
-        /* total resources associated with a PCI device */
+        /* Total resources associated with a PCI device */
         PCI_NUM_RESOURCES,
 
-        /* preserve this for compatibility */
+        /* Preserve this for compatibility */
         DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
 };
 
@@ -152,9 +150,10 @@ static inline const char *pci_power_name(pci_power_t state)
 #define PCI_PM_D3COLD_WAIT      100
 #define PCI_PM_BUS_WAIT         50
 
-/** The pci_channel state describes connectivity between the CPU and
- *  the pci device.  If some PCI bus between here and the pci device
- *  has crashed or locked up, this info is reflected here.
+/**
+ * The pci_channel state describes connectivity between the CPU and
+ * the PCI device.  If some PCI bus between here and the PCI device
+ * has crashed or locked up, this info is reflected here.
  */
 typedef unsigned int __bitwise pci_channel_state_t;
 
@@ -184,9 +183,7 @@ enum pcie_reset_state {
 
 typedef unsigned short __bitwise pci_dev_flags_t;
 enum pci_dev_flags {
-        /* INTX_DISABLE in PCI_COMMAND register disables MSI
-         * generation too.
-         */
+        /* INTX_DISABLE in PCI_COMMAND register disables MSI too */
         PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
         /* Device configuration is irrevocably lost if disabled into D3 */
         PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
@@ -202,7 +199,7 @@ enum pci_dev_flags {
         PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
         /* Get VPD from function 0 VPD */
         PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
-        /* a non-root bridge where translation occurs, stop alias search here */
+        /* A non-root bridge where translation occurs, stop alias search here */
         PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
         /* Do not use FLR even if device advertises PCI_AF_CAP */
         PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
@@ -222,17 +219,17 @@ enum pci_bus_flags {
         PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
 };
 
-/* These values come from the PCI Express Spec */
+/* Values from Link Status register, PCIe r3.1, sec 7.8.8 */
 enum pcie_link_width {
         PCIE_LNK_WIDTH_RESRV    = 0x00,
         PCIE_LNK_X1             = 0x01,
         PCIE_LNK_X2             = 0x02,
         PCIE_LNK_X4             = 0x04,
         PCIE_LNK_X8             = 0x08,
-        PCIE_LNK_X12            = 0x0C,
+        PCIE_LNK_X12            = 0x0c,
         PCIE_LNK_X16            = 0x10,
         PCIE_LNK_X32            = 0x20,
-        PCIE_LNK_WIDTH_UNKNOWN  = 0xFF,
+        PCIE_LNK_WIDTH_UNKNOWN  = 0xff,
 };
 
 /* Based on the PCI Hotplug Spec, but some values are made up by us */
@@ -263,15 +260,15 @@ enum pci_bus_speed {
 };
 
 struct pci_cap_saved_data {
-        u16 cap_nr;
-        bool cap_extended;
-        unsigned int size;
-        u32 data[0];
+        u16             cap_nr;
+        bool            cap_extended;
+        unsigned int    size;
+        u32             data[0];
 };
 
 struct pci_cap_saved_state {
-        struct hlist_node next;
-        struct pci_cap_saved_data cap;
+        struct hlist_node               next;
+        struct pci_cap_saved_data       cap;
 };
 
 struct irq_affinity;
@@ -280,19 +277,17 @@ struct pci_vpd;
 struct pci_sriov;
 struct pci_ats;
 
-/*
- * The pci_dev structure is used to describe PCI devices.
- */
+/* The pci_dev structure describes PCI devices */
 struct pci_dev {
-        struct list_head bus_list;      /* node in per-bus list */
-        struct pci_bus  *bus;           /* bus this device is on */
-        struct pci_bus  *subordinate;   /* bus this device bridges to */
+        struct list_head bus_list;      /* Node in per-bus list */
+        struct pci_bus  *bus;           /* Bus this device is on */
+        struct pci_bus  *subordinate;   /* Bus this device bridges to */
 
-        void            *sysdata;       /* hook for sys-specific extension */
-        struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
+        void            *sysdata;       /* Hook for sys-specific extension */
+        struct proc_dir_entry *procent; /* Device entry in /proc/bus/pci */
         struct pci_slot *slot;          /* Physical slot this device is in */
 
-        unsigned int    devfn;          /* encoded device & function index */
+        unsigned int    devfn;          /* Encoded device & function index */
         unsigned short  vendor;
         unsigned short  device;
         unsigned short  subsystem_vendor;
@@ -307,12 +302,12 @@ struct pci_dev {
         u8              msi_cap;        /* MSI capability offset */
         u8              msix_cap;       /* MSI-X capability offset */
         u8              pcie_mpss:3;    /* PCIe Max Payload Size Supported */
-        u8              rom_base_reg;   /* which config register controls the ROM */
-        u8              pin;            /* which interrupt pin this device uses */
-        u16             pcie_flags_reg; /* cached PCIe Capabilities Register */
-        unsigned long   *dma_alias_mask;/* mask of enabled devfn aliases */
+        u8              rom_base_reg;   /* Config register controlling ROM */
+        u8              pin;            /* Interrupt pin this device uses */
+        u16             pcie_flags_reg; /* Cached PCIe Capabilities Register */
+        unsigned long   *dma_alias_mask;/* Mask of enabled devfn aliases */
 
-        struct pci_driver *driver;      /* which driver has allocated this device */
+        struct pci_driver *driver;      /* Driver bound to this device */
         u64             dma_mask;       /* Mask of the bits of bus address this
                                            device implements.  Normally this is
                                            0xffffffff.  You only need to change
@@ -321,9 +316,9 @@ struct pci_dev {
 
         struct device_dma_parameters dma_parms;
 
-        pci_power_t     current_state;  /* Current operating state. In ACPI-speak,
-                                           this is D0-D3, D0 being fully functional,
-                                           and D3 being off. */
+        pci_power_t     current_state;  /* Current operating state. In ACPI,
+                                           this is D0-D3, D0 being fully
+                                           functional, and D3 being off. */
         u8              pm_cap;         /* PM capability offset */
         unsigned int    pme_support:5;  /* Bitmask of states from which PME#
                                            can be generated */
@@ -334,10 +329,10 @@ struct pci_dev {
         unsigned int    no_d3cold:1;    /* D3cold is forbidden */
         unsigned int    bridge_d3:1;    /* Allow D3 for bridge */
         unsigned int    d3cold_allowed:1;       /* D3cold is allowed by user */
-        unsigned int    mmio_always_on:1;       /* disallow turning off io/mem
-                                                   decoding during bar sizing */
+        unsigned int    mmio_always_on:1;       /* Disallow turning off io/mem
+                                                   decoding during BAR sizing */
         unsigned int    wakeup_prepared:1;
-        unsigned int    runtime_d3cold:1;       /* whether go through runtime
+        unsigned int    runtime_d3cold:1;       /* Whether go through runtime
                                                    D3cold, not set for devices
                                                    powered on/off by the
                                                    corresponding bridge */
@@ -350,12 +345,14 @@ struct pci_dev {
 
 #ifdef CONFIG_PCIEASPM
         struct pcie_link_state  *link_state;    /* ASPM link state */
+        unsigned int    ltr_path:1;     /* Latency Tolerance Reporting
+                                           supported from root to here */
 #endif
 
-        pci_channel_state_t error_state;        /* current connectivity state */
-        struct  device  dev;            /* Generic device interface */
+        pci_channel_state_t error_state;        /* Current connectivity state */
+        struct device   dev;                    /* Generic device interface */
 
-        int             cfg_size;       /* Size of configuration space */
+        int             cfg_size;               /* Size of config space */
 
         /*
          * Instead of touching interrupt line and base address registers
@@ -364,47 +361,47 @@ struct pci_dev {
         unsigned int    irq;
         struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
 
-        bool match_driver;              /* Skip attaching driver */
-        /* These fields are used by common fixups */
-        unsigned int    transparent:1;  /* Subtractive decode PCI bridge */
-        unsigned int    multifunction:1;/* Part of multi-function device */
-        /* keep track of device state */
+        bool            match_driver;           /* Skip attaching driver */
+
+        unsigned int    transparent:1;          /* Subtractive decode bridge */
+        unsigned int    multifunction:1;        /* Multi-function device */
+
         unsigned int    is_added:1;
-        unsigned int    is_busmaster:1; /* device is busmaster */
-        unsigned int    no_msi:1;       /* device may not use msi */
-        unsigned int    no_64bit_msi:1; /* device may only use 32-bit MSIs */
-        unsigned int    block_cfg_access:1;     /* config space access is blocked */
-        unsigned int    broken_parity_status:1; /* Device generates false positive parity */
-        unsigned int    irq_reroute_variant:2;  /* device needs IRQ rerouting variant */
+        unsigned int    is_busmaster:1;         /* Is busmaster */
+        unsigned int    no_msi:1;               /* May not use MSI */
+        unsigned int    no_64bit_msi:1;         /* May only use 32-bit MSIs */
+        unsigned int    block_cfg_access:1;     /* Config space access blocked */
+        unsigned int    broken_parity_status:1; /* Generates false positive parity */
+        unsigned int    irq_reroute_variant:2;  /* Needs IRQ rerouting variant */
         unsigned int    msi_enabled:1;
         unsigned int    msix_enabled:1;
-        unsigned int    ari_enabled:1;  /* ARI forwarding */
-        unsigned int    ats_enabled:1;  /* Address Translation Service */
+        unsigned int    ari_enabled:1;          /* ARI forwarding */
+        unsigned int    ats_enabled:1;          /* Address Translation Svc */
         unsigned int    pasid_enabled:1;        /* Process Address Space ID */
         unsigned int    pri_enabled:1;          /* Page Request Interface */
         unsigned int    is_managed:1;
-        unsigned int    needs_freset:1; /* Dev requires fundamental reset */
+        unsigned int    needs_freset:1;         /* Requires fundamental reset */
         unsigned int    state_saved:1;
         unsigned int    is_physfn:1;
         unsigned int    is_virtfn:1;
         unsigned int    reset_fn:1;
-        unsigned int    is_hotplug_bridge:1;
-        unsigned int    is_thunderbolt:1; /* Thunderbolt controller */
-        unsigned int    __aer_firmware_first_valid:1;
+        unsigned int    is_hotplug_bridge:1;
+        unsigned int    is_thunderbolt:1;       /* Thunderbolt controller */
+        unsigned int    __aer_firmware_first_valid:1;
         unsigned int    __aer_firmware_first:1;
-        unsigned int    broken_intx_masking:1; /* INTx masking can't be used */
-        unsigned int    io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
+        unsigned int    broken_intx_masking:1;  /* INTx masking can't be used */
+        unsigned int    io_window_1k:1;         /* Intel bridge 1K I/O windows */
         unsigned int    irq_managed:1;
         unsigned int    has_secondary_link:1;
-        unsigned int    non_compliant_bars:1;   /* broken BARs; ignore them */
-        unsigned int    is_probed:1;            /* device probing in progress */
+        unsigned int    non_compliant_bars:1;   /* Broken BARs; ignore them */
+        unsigned int    is_probed:1;            /* Device probing in progress */
         pci_dev_flags_t dev_flags;
         atomic_t        enable_cnt;     /* pci_enable_device has been called */
 
-        u32             saved_config_space[16]; /* config space saved at suspend time */
+        u32             saved_config_space[16]; /* Config space saved at suspend time */
         struct hlist_head saved_cap_space;
-        struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
-        int rom_attr_enabled;           /* has display of the rom attribute been enabled? */
+        struct bin_attribute *rom_attr;         /* Attribute descriptor for sysfs ROM entry */
+        int             rom_attr_enabled;       /* Display of ROM attribute enabled? */
         struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
         struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
 
@@ -419,12 +416,12 @@ struct pci_dev {
         struct pci_vpd *vpd;
 #ifdef CONFIG_PCI_ATS
         union {
-                struct pci_sriov *sriov;        /* SR-IOV capability related */
-                struct pci_dev *physfn; /* the PF this VF is associated with */
+                struct pci_sriov        *sriov;         /* PF: SR-IOV info */
+                struct pci_dev          *physfn;        /* VF: related PF */
         };
         u16             ats_cap;        /* ATS Capability offset */
         u8              ats_stu;        /* ATS Smallest Translation Unit */
-        atomic_t        ats_ref_cnt;    /* number of VFs with ATS enabled */
+        atomic_t        ats_ref_cnt;    /* Number of VFs with ATS enabled */
 #endif
 #ifdef CONFIG_PCI_PRI
         u32             pri_reqs_alloc; /* Number of PRI requests allocated */
@@ -432,11 +429,11 @@ struct pci_dev {
 #ifdef CONFIG_PCI_PASID
         u16             pasid_features;
 #endif
-        phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
-        size_t romlen; /* Length of ROM if it's not from the BAR */
-        char *driver_override; /* Driver name to force a match */
+        phys_addr_t     rom;            /* Physical address if not from BAR */
+        size_t          romlen;         /* Length if not from BAR */
+        char            *driver_override; /* Driver name to force a match */
 
-        unsigned long priv_flags; /* Private flags for the pci driver */
+        unsigned long   priv_flags;     /* Private flags for the PCI driver */
 };
 
 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
@@ -459,26 +456,26 @@ static inline int pci_channel_offline(struct pci_dev *pdev)
 }
 
 struct pci_host_bridge {
-        struct device dev;
-        struct pci_bus *bus;            /* root bus */
-        struct pci_ops *ops;
-        void *sysdata;
-        int busnr;
+        struct device   dev;
+        struct pci_bus  *bus;           /* Root bus */
+        struct pci_ops  *ops;
+        void            *sysdata;
+        int             busnr;
         struct list_head windows;       /* resource_entry */
-        u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* platform IRQ swizzler */
+        u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* Platform IRQ swizzler */
         int (*map_irq)(const struct pci_dev *, u8, u8);
         void (*release_fn)(struct pci_host_bridge *);
-        void *release_data;
+        void            *release_data;
         struct msi_controller *msi;
-        unsigned int ignore_reset_delay:1;      /* for entire hierarchy */
-        unsigned int no_ext_tags:1;             /* no Extended Tags */
+        unsigned int    ignore_reset_delay:1;   /* For entire hierarchy */
+        unsigned int    no_ext_tags:1;          /* No Extended Tags */
         /* Resource alignment requirements */
         resource_size_t (*align_resource)(struct pci_dev *dev,
                         const struct resource *res,
                         resource_size_t start,
                         resource_size_t size,
                         resource_size_t align);
-        unsigned long private[0] ____cacheline_aligned;
+        unsigned long   private[0] ____cacheline_aligned;
 };
 
 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
@@ -500,8 +497,8 @@ void pci_free_host_bridge(struct pci_host_bridge *bridge);
 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
 
 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
-                     void (*release_fn)(struct pci_host_bridge *),
-                     void *release_data);
+                                 void (*release_fn)(struct pci_host_bridge *),
+                                 void *release_data);
 
 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
 
@@ -521,32 +518,32 @@ int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
 #define PCI_SUBTRACTIVE_DECODE  0x1
 
 struct pci_bus_resource {
-        struct list_head list;
-        struct resource *res;
-        unsigned int flags;
+        struct list_head        list;
+        struct resource         *res;
+        unsigned int            flags;
 };
 
 #define PCI_REGION_FLAG_MASK    0x0fU   /* These bits of resource flags tell us the PCI region flags */
 
 struct pci_bus {
-        struct list_head node;          /* node in list of buses */
-        struct pci_bus  *parent;        /* parent bus this bridge is on */
-        struct list_head children;      /* list of child buses */
-        struct list_head devices;       /* list of devices on this bus */
-        struct pci_dev  *self;          /* bridge device as seen by parent */
-        struct list_head slots;         /* list of slots on this bus;
+        struct list_head node;          /* Node in list of buses */
+        struct pci_bus  *parent;        /* Parent bus this bridge is on */
+        struct list_head children;      /* List of child buses */
+        struct list_head devices;       /* List of devices on this bus */
+        struct pci_dev  *self;          /* Bridge device as seen by parent */
+        struct list_head slots;         /* List of slots on this bus;
                                            protected by pci_slot_mutex */
         struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
-        struct list_head resources;     /* address space routed to this bus */
-        struct resource busn_res;       /* bus numbers routed to this bus */
+        struct list_head resources;     /* Address space routed to this bus */
+        struct resource busn_res;       /* Bus numbers routed to this bus */
 
-        struct pci_ops  *ops;           /* configuration access functions */
+        struct pci_ops  *ops;           /* Configuration access functions */
         struct msi_controller *msi;     /* MSI controller */
-        void            *sysdata;       /* hook for sys-specific extension */
-        struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
+        void            *sysdata;       /* Hook for sys-specific extension */
+        struct proc_dir_entry *procdir; /* Directory entry in /proc/bus/pci */
 
-        unsigned char   number;         /* bus number */
-        unsigned char   primary;        /* number of primary bridge */
+        unsigned char   number;         /* Bus number */
+        unsigned char   primary;        /* Number of primary bridge */
         unsigned char   max_bus_speed;  /* enum pci_bus_speed */
         unsigned char   cur_bus_speed;  /* enum pci_bus_speed */
 #ifdef CONFIG_PCI_DOMAINS_GENERIC
@@ -555,12 +552,12 @@ struct pci_bus {
 
         char            name[48];
 
-        unsigned short  bridge_ctl;     /* manage NO_ISA/FBB/et al behaviors */
-        pci_bus_flags_t bus_flags;      /* inherited by child buses */
+        unsigned short  bridge_ctl;     /* Manage NO_ISA/FBB/et al behaviors */
+        pci_bus_flags_t bus_flags;      /* Inherited by child buses */
         struct device           *bridge;
         struct device           dev;
-        struct bin_attribute    *legacy_io; /* legacy I/O for this bus */
-        struct bin_attribute    *legacy_mem; /* legacy mem */
+        struct bin_attribute    *legacy_io;     /* Legacy I/O for this bus */
+        struct bin_attribute    *legacy_mem;    /* Legacy mem */
         unsigned int            is_added:1;
 };
 
@@ -617,9 +614,7 @@ static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
 #endif
 
-/*
- * Error values that may be returned by PCI functions.
- */
+/* Error values that may be returned by PCI functions */
 #define PCIBIOS_SUCCESSFUL              0x00
 #define PCIBIOS_FUNC_NOT_SUPPORTED      0x81
 #define PCIBIOS_BAD_VENDOR_ID           0x83
@@ -628,9 +623,7 @@ static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false;
 #define PCIBIOS_SET_FAILED              0x88
 #define PCIBIOS_BUFFER_TOO_SMALL        0x89
 
-/*
- * Translate above to generic errno for passing back through non-PCI code.
- */
+/* Translate above to generic errno for passing back through non-PCI code */
 static inline int pcibios_err_to_errno(int err)
 {
         if (err <= PCIBIOS_SUCCESSFUL)
@@ -680,13 +673,13 @@ typedef u32 pci_bus_addr_t;
 #endif
 
 struct pci_bus_region {
-        pci_bus_addr_t start;
-        pci_bus_addr_t end;
+        pci_bus_addr_t  start;
+        pci_bus_addr_t  end;
 };
 
 struct pci_dynids {
-        spinlock_t lock;            /* protects list, index */
-        struct list_head list;      /* for IDs added at runtime */
+        spinlock_t              lock;   /* Protects list, index */
+        struct list_head        list;   /* For IDs added at runtime */
 };
 
 
@@ -700,13 +693,13 @@ struct pci_dynids {
 typedef unsigned int __bitwise pci_ers_result_t;
 
 enum pci_ers_result {
-        /* no result/none/not supported in device driver */
+        /* No result/none/not supported in device driver */
         PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
 
         /* Device driver can recover without slot reset */
         PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
 
-        /* Device driver wants slot to be reset. */
+        /* Device driver wants slot to be reset */
         PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
 
         /* Device has completely failed, is unrecoverable */
@@ -742,27 +735,27 @@ struct pci_error_handlers {
 
 struct module;
 struct pci_driver {
-        struct list_head node;
-        const char *name;
-        const struct pci_device_id *id_table;   /* must be non-NULL for probe to be called */
-        int  (*probe)  (struct pci_dev *dev, const struct pci_device_id *id);   /* New device inserted */
-        void (*remove) (struct pci_dev *dev);   /* Device removed (NULL if not a hot-plug capable driver) */
-        int  (*suspend) (struct pci_dev *dev, pm_message_t state);      /* Device suspended */
-        int  (*suspend_late) (struct pci_dev *dev, pm_message_t state);
-        int  (*resume_early) (struct pci_dev *dev);
-        int  (*resume) (struct pci_dev *dev);                   /* Device woken up */
+        struct list_head        node;
+        const char              *name;
+        const struct pci_device_id *id_table;   /* Must be non-NULL for probe to be called */
+        int  (*probe)(struct pci_dev *dev, const struct pci_device_id *id);     /* New device inserted */
+        void (*remove)(struct pci_dev *dev);    /* Device removed (NULL if not a hot-plug capable driver) */
+        int  (*suspend)(struct pci_dev *dev, pm_message_t state);       /* Device suspended */
+        int  (*suspend_late)(struct pci_dev *dev, pm_message_t state);
+        int  (*resume_early)(struct pci_dev *dev);
+        int  (*resume) (struct pci_dev *dev);   /* Device woken up */
         void (*shutdown) (struct pci_dev *dev);
-        int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
+        int  (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* On PF */
         const struct pci_error_handlers *err_handler;
         const struct attribute_group **groups;
         struct device_driver    driver;
-        struct pci_dynids dynids;
+        struct pci_dynids       dynids;
 };
 
 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
 
 /**
- * PCI_DEVICE - macro used to describe a specific pci device
+ * PCI_DEVICE - macro used to describe a specific PCI device
  * @vend: the 16 bit PCI Vendor ID
  * @dev: the 16 bit PCI Device ID
  *
@@ -775,7 +768,7 @@ struct pci_driver {
         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
 
 /**
- * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
+ * PCI_DEVICE_SUB - macro used to describe a specific PCI device with subsystem
  * @vend: the 16 bit PCI Vendor ID
  * @dev: the 16 bit PCI Device ID
  * @subvend: the 16 bit PCI Subvendor ID
@@ -789,7 +782,7 @@ struct pci_driver {
         .subvendor = (subvend), .subdevice = (subdev)
 
 /**
- * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
+ * PCI_DEVICE_CLASS - macro used to describe a specific PCI device class
  * @dev_class: the class, subclass, prog-if triple for this device
  * @dev_class_mask: the class mask for this device
  *
@@ -803,7 +796,7 @@ struct pci_driver {
         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
 
 /**
- * PCI_VDEVICE - macro used to describe a specific pci device in short form
+ * PCI_VDEVICE - macro used to describe a specific PCI device in short form
  * @vend: the vendor name
  * @dev: the 16 bit PCI Device ID
  *
@@ -812,22 +805,21 @@ struct pci_driver {
  * to PCI_ANY_ID. The macro allows the next field to follow as the device
  * private data.
  */
-
 #define PCI_VDEVICE(vend, dev) \
         .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
 
 enum {
-        PCI_REASSIGN_ALL_RSRC   = 0x00000001,   /* ignore firmware setup */
-        PCI_REASSIGN_ALL_BUS    = 0x00000002,   /* reassign all bus numbers */
-        PCI_PROBE_ONLY          = 0x00000004,   /* use existing setup */
-        PCI_CAN_SKIP_ISA_ALIGN  = 0x00000008,   /* don't do ISA alignment */
-        PCI_ENABLE_PROC_DOMAINS = 0x00000010,   /* enable domains in /proc */
+        PCI_REASSIGN_ALL_RSRC   = 0x00000001,   /* Ignore firmware setup */
+        PCI_REASSIGN_ALL_BUS    = 0x00000002,   /* Reassign all bus numbers */
+        PCI_PROBE_ONLY          = 0x00000004,   /* Use existing setup */
+        PCI_CAN_SKIP_ISA_ALIGN  = 0x00000008,   /* Don't do ISA alignment */
+        PCI_ENABLE_PROC_DOMAINS = 0x00000010,   /* Enable domains in /proc */
         PCI_COMPAT_DOMAIN_0     = 0x00000020,   /* ... except domain 0 */
-        PCI_SCAN_ALL_PCIE_DEVS  = 0x00000040,   /* scan all, not just dev 0 */
+        PCI_SCAN_ALL_PCIE_DEVS  = 0x00000040,   /* Scan all, not just dev 0 */
 };
 
-/* these external functions are only available when PCI support is enabled */
+/* These external functions are only available when PCI support is enabled */
 #ifdef CONFIG_PCI
 
 extern unsigned int pci_flags;
@@ -840,11 +832,11 @@ static inline int pci_has_flag(int flag) { return pci_flags & flag; }
 void pcie_bus_configure_settings(struct pci_bus *bus);
 
 enum pcie_bus_config_types {
-        PCIE_BUS_TUNE_OFF,      /* don't touch MPS at all */
-        PCIE_BUS_DEFAULT,       /* ensure MPS matches upstream bridge */
-        PCIE_BUS_SAFE,          /* use largest MPS boot-time devices support */
-        PCIE_BUS_PERFORMANCE,   /* use MPS and MRRS for best performance */
-        PCIE_BUS_PEER2PEER,     /* set MPS = 128 for all devices */
+        PCIE_BUS_TUNE_OFF,      /* Don't touch MPS at all */
+        PCIE_BUS_DEFAULT,       /* Ensure MPS matches upstream bridge */
+        PCIE_BUS_SAFE,          /* Use largest MPS boot-time devices support */
+        PCIE_BUS_PERFORMANCE,   /* Use MPS and MRRS for best performance */
+        PCIE_BUS_PEER2PEER,     /* Set MPS = 128 for all devices */
 };
 
 extern enum pcie_bus_config_types pcie_bus_config;
@@ -853,7 +845,7 @@ extern struct bus_type pci_bus_type;
 
 /* Do NOT directly access these two variables, unless you are arch-specific PCI
  * code, or PCI core code. */
-extern struct list_head pci_root_buses; /* list of all known PCI buses */
+extern struct list_head pci_root_buses; /* List of all known PCI buses */
 /* Some device drivers need know if PCI is initiated */
 int no_pci_devices(void);
 
@@ -887,12 +879,13 @@ struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
                                     struct pci_ops *ops, void *sysdata,
                                     struct list_head *resources);
+int pci_host_probe(struct pci_host_bridge *bridge);
 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
 void pci_bus_release_busn_res(struct pci_bus *b);
 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
-                                             struct pci_ops *ops, void *sysdata,
-                                             struct list_head *resources);
+                                  struct pci_ops *ops, void *sysdata,
+                                  struct list_head *resources);
 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
                                 int busnr);
@@ -949,10 +942,10 @@ int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
 
 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
-                                struct pci_dev *from);
+                               struct pci_dev *from);
 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
-                                unsigned int ss_vendor, unsigned int ss_device,
-                                struct pci_dev *from);
+                               unsigned int ss_vendor, unsigned int ss_device,
+                               struct pci_dev *from);
 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
                                             unsigned int devfn);
@@ -1028,7 +1021,7 @@ static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
         return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
 }
 
-/* user-space driven config access */
+/* User-space driven config access */
 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
@@ -1170,7 +1163,7 @@ unsigned int pci_rescan_bus(struct pci_bus *bus);
 void pci_lock_rescan_remove(void);
 void pci_unlock_rescan_remove(void);
 
-/* Vital product data routines */
+/* Vital Product Data routines */
 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
@@ -1255,9 +1248,7 @@ static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
                                        const char *mod_name);
 
-/*
- * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
- */
+/* pci_register_driver() must be a macro so KBUILD_MODNAME can be expanded */
 #define pci_register_driver(driver)             \
         __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
 
@@ -1272,8 +1263,7 @@ void pci_unregister_driver(struct pci_driver *dev);
  * use this macro once, and calling it replaces module_init() and module_exit()
  */
 #define module_pci_driver(__pci_driver) \
-        module_driver(__pci_driver, pci_register_driver, \
-                       pci_unregister_driver)
+        module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
 
 /**
  * builtin_pci_driver() - Helper macro for registering a PCI driver
@@ -1312,10 +1302,10 @@ resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
                       unsigned int command_bits, u32 flags);
 
-#define PCI_IRQ_LEGACY          (1 << 0) /* allow legacy interrupts */
-#define PCI_IRQ_MSI             (1 << 1) /* allow MSI interrupts */
-#define PCI_IRQ_MSIX            (1 << 2) /* allow MSI-X interrupts */
-#define PCI_IRQ_AFFINITY        (1 << 3) /* auto-assign affinity */
+#define PCI_IRQ_LEGACY          (1 << 0) /* Allow legacy interrupts */
+#define PCI_IRQ_MSI             (1 << 1) /* Allow MSI interrupts */
+#define PCI_IRQ_MSIX            (1 << 2) /* Allow MSI-X interrupts */
+#define PCI_IRQ_AFFINITY        (1 << 3) /* Auto-assign affinity */
 #define PCI_IRQ_ALL_TYPES \
         (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
 
@@ -1334,8 +1324,8 @@ int pci_set_vga_state(struct pci_dev *pdev, bool decode,
 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
 
 struct msix_entry {
-        u32     vector; /* kernel uses to write allocated vector */
-        u16     entry;  /* driver uses to specify entry, OS writes */
+        u32     vector; /* Kernel uses to write allocated vector */
+        u16     entry;  /* Driver uses to specify entry, OS writes */
 };
 
 #ifdef CONFIG_PCI_MSI
@@ -1375,10 +1365,10 @@ static inline int pci_msi_enabled(void) { return 0; }
 static inline int pci_enable_msi(struct pci_dev *dev)
 { return -ENOSYS; }
 static inline int pci_enable_msix_range(struct pci_dev *dev,
-                      struct msix_entry *entries, int minvec, int maxvec)
+                        struct msix_entry *entries, int minvec, int maxvec)
 { return -ENOSYS; }
 static inline int pci_enable_msix_exact(struct pci_dev *dev,
-                      struct msix_entry *entries, int nvec)
+                        struct msix_entry *entries, int nvec)
 { return -ENOSYS; }
 
 static inline int
@@ -1543,9 +1533,9 @@ static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
 #endif
 
-/* some architectures require additional setup to direct VGA traffic */
+/* Some architectures require additional setup to direct VGA traffic */
 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
-                      unsigned int command_bits, u32 flags);
+                                    unsigned int command_bits, u32 flags);
 void pci_register_set_vga_state(arch_set_vga_state_t func);
 
 static inline int
@@ -1584,10 +1574,9 @@ static inline void pci_clear_flags(int flags) { }
 static inline int pci_has_flag(int flag) { return 0; }
 
 /*
- *  If the system does not have PCI, clearly these return errors.  Define
- *  these as simple inline functions to avoid hair in drivers.
+ * If the system does not have PCI, clearly these return errors.  Define
+ * these as simple inline functions to avoid hair in drivers.
  */
-
 #define _PCI_NOP(o, s, t) \
         static inline int pci_##o##_config_##s(struct pci_dev *dev, \
                                                 int where, t val) \
@@ -1686,6 +1675,13 @@ static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
 #define dev_is_pf(d) (false)
 static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
 { return false; }
+static inline int pci_irqd_intx_xlate(struct irq_domain *d,
+                                      struct device_node *node,
+                                      const u32 *intspec,
+                                      unsigned int intsize,
+                                      unsigned long *out_hwirq,
+                                      unsigned int *out_type)
+{ return -EINVAL; }
 #endif /* CONFIG_PCI */
 
 /* Include architecture-dependent settings and functions */
@@ -1726,8 +1722,10 @@ int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
 #define pci_root_bus_fwnode(bus)        NULL
 #endif
 
-/* these helpers provide future and backwards compatibility
- * for accessing popular PCI BAR info */
+/*
+ * These helpers provide future and backwards compatibility
+ * for accessing popular PCI BAR info
+ */
 #define pci_resource_start(dev, bar)    ((dev)->resource[(bar)].start)
 #define pci_resource_end(dev, bar)      ((dev)->resource[(bar)].end)
 #define pci_resource_flags(dev, bar)    ((dev)->resource[(bar)].flags)
@@ -1739,7 +1737,8 @@ int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
          (pci_resource_end((dev), (bar)) -              \
           pci_resource_start((dev), (bar)) + 1))
 
-/* Similar to the helpers above, these manipulate per-pci_dev
+/*
+ * Similar to the helpers above, these manipulate per-pci_dev
  * driver-specific data.  They are really just a wrapper around
  * the generic device structure functions of these calls.
  */
@@ -1753,16 +1752,14 @@ static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
         dev_set_drvdata(&pdev->dev, data);
 }
 
-/* If you want to know what to call your pci_dev, ask this function.
- * Again, it's a wrapper around the generic device.
- */
 static inline const char *pci_name(const struct pci_dev *pdev)
 {
         return dev_name(&pdev->dev);
 }
 
 
-/* Some archs don't want to expose struct resource to userland as-is
+/*
+ * Some archs don't want to expose struct resource to userland as-is
  * in sysfs and /proc
  */
 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
@@ -1781,16 +1778,16 @@ static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
 
 
 /*
- *  The world is not perfect and supplies us with broken PCI devices.
- *  For at least a part of these bugs we need a work-around, so both
- *  generic (drivers/pci/quirks.c) and per-architecture code can define
- *  fixup hooks to be called for particular buggy devices.
+ * The world is not perfect and supplies us with broken PCI devices.
+ * For at least a part of these bugs we need a work-around, so both
+ * generic (drivers/pci/quirks.c) and per-architecture code can define
+ * fixup hooks to be called for particular buggy devices.
  */
 
 struct pci_fixup {
-        u16 vendor;             /* You can use PCI_ANY_ID here of course */
-        u16 device;             /* You can use PCI_ANY_ID here of course */
-        u32 class;              /* You can use PCI_ANY_ID here too */
+        u16 vendor;                     /* Or PCI_ANY_ID */
+        u16 device;                     /* Or PCI_ANY_ID */
+        u32 class;                      /* Or PCI_ANY_ID */
         unsigned int class_shift;       /* should be 0, 8, 16 */
         void (*hook)(struct pci_dev *dev);
 };
@@ -1832,23 +1829,19 @@ enum pci_fixup_pass {
 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class,           \
                                          class_shift, hook)             \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
-                resume##hook, vendor, device, class,    \
-                class_shift, hook)
+                resume##hook, vendor, device, class, class_shift, hook)
 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class,     \
                                          class_shift, hook)             \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
-                resume_early##hook, vendor, device,     \
-                class, class_shift, hook)
+                resume_early##hook, vendor, device, class, class_shift, hook)
 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class,          \
                                          class_shift, hook)             \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
-                suspend##hook, vendor, device, class,   \
-                class_shift, hook)
+                suspend##hook, vendor, device, class, class_shift, hook)
 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class,     \
                                          class_shift, hook)             \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late,              \
-                suspend_late##hook, vendor, device,     \
-                class, class_shift, hook)
+                suspend_late##hook, vendor, device, class, class_shift, hook)
 
 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook)                   \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early,                     \
@@ -1864,20 +1857,16 @@ enum pci_fixup_pass {
                 hook, vendor, device, PCI_ANY_ID, 0, hook)
 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook)                  \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume,                    \
-                resume##hook, vendor, device,           \
-                PCI_ANY_ID, 0, hook)
+                resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook)            \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early,              \
-                resume_early##hook, vendor, device,     \
-                PCI_ANY_ID, 0, hook)
+                resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook)                 \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend,                   \
-                suspend##hook, vendor, device,          \
-                PCI_ANY_ID, 0, hook)
+                suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook)            \
         DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late,              \
-                suspend_late##hook, vendor, device,     \
-                PCI_ANY_ID, 0, hook)
+                suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
 
 #ifdef CONFIG_PCI_QUIRKS
 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
@@ -2061,6 +2050,7 @@ void pci_request_acs(void);
 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
 bool pci_acs_path_enabled(struct pci_dev *start,
                           struct pci_dev *end, u16 acs_flags);
+int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
 
 #define PCI_VPD_LRDT                    0x80    /* Large Resource Data Type */
 #define PCI_VPD_LRDT_ID(x)              ((x) | PCI_VPD_LRDT)
@@ -2112,7 +2102,7 @@ static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
  */
 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
 {
-    return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
+        return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
 }
 
 /**
@@ -2182,6 +2172,9 @@ void pci_release_of_node(struct pci_dev *dev);
 void pci_set_bus_of_node(struct pci_bus *bus);
 void pci_release_bus_of_node(struct pci_bus *bus);
 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
+int pci_parse_request_of_pci_ranges(struct device *dev,
+                                    struct list_head *resources,
+                                    struct resource **bus_range);
 
 /* Arch may override this (weak) */
 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
@@ -2197,7 +2190,7 @@ static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
         return bus ? bus->dev.of_node : NULL;
 }
 
-#else /* CONFIG_OF */
+#else   /* CONFIG_OF */
 static inline void pci_set_of_node(struct pci_dev *dev) { }
 static inline void pci_release_of_node(struct pci_dev *dev) { }
 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
@@ -2206,6 +2199,12 @@ static inline struct device_node *
 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
 static inline struct irq_domain *
 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
+static inline int pci_parse_request_of_pci_ranges(struct device *dev,
+                                                  struct list_head *resources,
+                                                  struct resource **bus_range)
+{
+        return -EINVAL;
+}
 #endif  /* CONFIG_OF */
 
 #ifdef CONFIG_ACPI
@@ -2231,7 +2230,7 @@ int pci_for_each_dma_alias(struct pci_dev *pdev,
                            int (*fn)(struct pci_dev *pdev,
                                      u16 alias, void *data), void *data);
 
-/* helper functions for operation of device flag */
+/* Helper functions for operation of device flag */
 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
 {
         pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
@@ -2278,7 +2277,19 @@ static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
         return false;
 }
 
-/* provide the legacy pci_dma_* API */
+/* Provide the legacy pci_dma_* API */
 #include <linux/pci-dma-compat.h>
 
+#define pci_printk(level, pdev, fmt, arg...) \
+        dev_printk(level, &(pdev)->dev, fmt, ##arg)
+
+#define pci_emerg(pdev, fmt, arg...)    dev_emerg(&(pdev)->dev, fmt, ##arg)
+#define pci_alert(pdev, fmt, arg...)    dev_alert(&(pdev)->dev, fmt, ##arg)
+#define pci_crit(pdev, fmt, arg...)     dev_crit(&(pdev)->dev, fmt, ##arg)
+#define pci_err(pdev, fmt, arg...)      dev_err(&(pdev)->dev, fmt, ##arg)
+#define pci_warn(pdev, fmt, arg...)     dev_warn(&(pdev)->dev, fmt, ##arg)
+#define pci_notice(pdev, fmt, arg...)   dev_notice(&(pdev)->dev, fmt, ##arg)
+#define pci_info(pdev, fmt, arg...)     dev_info(&(pdev)->dev, fmt, ##arg)
+#define pci_dbg(pdev, fmt, arg...)      dev_dbg(&(pdev)->dev, fmt, ##arg)
+
 #endif /* LINUX_PCI_H */
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index ab20dc5db423..eb13e84e1fef 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2381,6 +2381,8 @@
 
 #define PCI_VENDOR_ID_LENOVO            0x17aa
 
+#define PCI_VENDOR_ID_CDNS              0x17cd
+
 #define PCI_VENDOR_ID_ARECA             0x17d3
 #define PCI_DEVICE_ID_ARECA_1110        0x1110
 #define PCI_DEVICE_ID_ARECA_1120        0x1120
diff --git a/include/linux/switchtec.h b/include/linux/switchtec.h
index 09d73d0d1aa8..42d121174fe2 100644
--- a/include/linux/switchtec.h
+++ b/include/linux/switchtec.h
@@ -100,6 +100,9 @@ struct sw_event_regs {
         u32 gpio_interrupt_hdr;
         u32 gpio_interrupt_data;
         u32 reserved16[4];
+        u32 gfms_event_hdr;
+        u32 gfms_event_data;
+        u32 reserved17[4];
 } __packed;
 
 enum {
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 70c2b2ade048..0c79eac5e9b8 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -622,15 +622,19 @@
  * safely.
  */
 #define PCI_EXP_DEVCAP2         36      /* Device Capabilities 2 */
+#define  PCI_EXP_DEVCAP2_COMP_TMOUT_DIS 0x00000010 /* Completion Timeout Disable supported */
 #define  PCI_EXP_DEVCAP2_ARI            0x00000020 /* Alternative Routing-ID */
 #define  PCI_EXP_DEVCAP2_ATOMIC_ROUTE   0x00000040 /* Atomic Op routing */
-#define PCI_EXP_DEVCAP2_ATOMIC_COMP64   0x00000100 /* Atomic 64-bit compare */
+#define  PCI_EXP_DEVCAP2_ATOMIC_COMP32  0x00000080 /* 32b AtomicOp completion */
+#define  PCI_EXP_DEVCAP2_ATOMIC_COMP64  0x00000100 /* 64b AtomicOp completion */
+#define  PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200 /* 128b AtomicOp completion */
 #define  PCI_EXP_DEVCAP2_LTR            0x00000800 /* Latency tolerance reporting */
 #define  PCI_EXP_DEVCAP2_OBFF_MASK      0x000c0000 /* OBFF support mechanism */
 #define  PCI_EXP_DEVCAP2_OBFF_MSG       0x00040000 /* New message signaling */
 #define  PCI_EXP_DEVCAP2_OBFF_WAKE      0x00080000 /* Re-use WAKE# for OBFF */
 #define PCI_EXP_DEVCTL2         40      /* Device Control 2 */
 #define  PCI_EXP_DEVCTL2_COMP_TIMEOUT   0x000f  /* Completion Timeout Value */
+#define  PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010  /* Completion Timeout Disable */
 #define  PCI_EXP_DEVCTL2_ARI            0x0020  /* Alternative Routing-ID */
 #define PCI_EXP_DEVCTL2_ATOMIC_REQ      0x0040  /* Set Atomic requests */
 #define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */
@@ -966,26 +970,28 @@
 
 /* Downstream Port Containment */
 #define PCI_EXP_DPC_CAP                 4       /* DPC Capability */
-#define PCI_EXP_DPC_IRQ                 0x1f    /* DPC Interrupt Message Number */
-#define  PCI_EXP_DPC_CAP_RP_EXT         0x20    /* Root Port Extensions for DPC */
-#define  PCI_EXP_DPC_CAP_POISONED_TLP   0x40    /* Poisoned TLP Egress Blocking Supported */
-#define  PCI_EXP_DPC_CAP_SW_TRIGGER     0x80    /* Software Triggering Supported */
-#define  PCI_EXP_DPC_RP_PIO_LOG_SIZE    0xF00   /* RP PIO log size */
+#define PCI_EXP_DPC_IRQ                 0x001F  /* Interrupt Message Number */
+#define  PCI_EXP_DPC_CAP_RP_EXT         0x0020  /* Root Port Extensions */
+#define  PCI_EXP_DPC_CAP_POISONED_TLP   0x0040  /* Poisoned TLP Egress Blocking Supported */
+#define  PCI_EXP_DPC_CAP_SW_TRIGGER     0x0080  /* Software Triggering Supported */
+#define  PCI_EXP_DPC_RP_PIO_LOG_SIZE    0x0F00  /* RP PIO Log Size */
 #define  PCI_EXP_DPC_CAP_DL_ACTIVE      0x1000  /* ERR_COR signal on DL_Active supported */
 
 #define PCI_EXP_DPC_CTL                 6       /* DPC control */
-#define  PCI_EXP_DPC_CTL_EN_NONFATAL    0x02    /* Enable trigger on ERR_NONFATAL message */
-#define  PCI_EXP_DPC_CTL_INT_EN         0x08    /* DPC Interrupt Enable */
+#define  PCI_EXP_DPC_CTL_EN_NONFATAL    0x0002  /* Enable trigger on ERR_NONFATAL message */
+#define  PCI_EXP_DPC_CTL_INT_EN         0x0008  /* DPC Interrupt Enable */
 
 #define PCI_EXP_DPC_STATUS              8       /* DPC Status */
-#define  PCI_EXP_DPC_STATUS_TRIGGER     0x01    /* Trigger Status */
-#define  PCI_EXP_DPC_STATUS_INTERRUPT   0x08    /* Interrupt Status */
-#define  PCI_EXP_DPC_RP_BUSY            0x10    /* Root Port Busy */
+#define  PCI_EXP_DPC_STATUS_TRIGGER         0x0001 /* Trigger Status */
+#define  PCI_EXP_DPC_STATUS_TRIGGER_RSN     0x0006 /* Trigger Reason */
+#define  PCI_EXP_DPC_STATUS_INTERRUPT       0x0008 /* Interrupt Status */
+#define  PCI_EXP_DPC_RP_BUSY                0x0010 /* Root Port Busy */
+#define  PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */
 
 #define PCI_EXP_DPC_SOURCE_ID           10      /* DPC Source Identifier */
 
 #define PCI_EXP_DPC_RP_PIO_STATUS        0x0C   /* RP PIO Status */
-#define PCI_EXP_DPC_RP_PIO_MASK          0x10   /* RP PIO MASK */
+#define PCI_EXP_DPC_RP_PIO_MASK          0x10   /* RP PIO Mask */
 #define PCI_EXP_DPC_RP_PIO_SEVERITY      0x14   /* RP PIO Severity */
 #define PCI_EXP_DPC_RP_PIO_SYSERROR      0x18   /* RP PIO SysError */
 #define PCI_EXP_DPC_RP_PIO_EXCEPTION     0x1C   /* RP PIO Exception */
diff --git a/include/uapi/linux/switchtec_ioctl.h b/include/uapi/linux/switchtec_ioctl.h
index 75df44373034..4f4daf8db954 100644
--- a/include/uapi/linux/switchtec_ioctl.h
+++ b/include/uapi/linux/switchtec_ioctl.h
@@ -88,7 +88,8 @@ struct switchtec_ioctl_event_summary {
 #define SWITCHTEC_IOCTL_EVENT_FORCE_SPEED               26
 #define SWITCHTEC_IOCTL_EVENT_CREDIT_TIMEOUT            27
 #define SWITCHTEC_IOCTL_EVENT_LINK_STATE                28
-#define SWITCHTEC_IOCTL_MAX_EVENTS                      29
+#define SWITCHTEC_IOCTL_EVENT_GFMS                      29
+#define SWITCHTEC_IOCTL_MAX_EVENTS                      30
 
 #define SWITCHTEC_IOCTL_EVENT_LOCAL_PART_IDX -1
 #define SWITCHTEC_IOCTL_EVENT_IDX_ALL -2
diff --git a/kernel/resource.c b/kernel/resource.c
index 54ba6de3757c..8c527d83ca76 100644
--- a/kernel/resource.c
+++ b/kernel/resource.c
@@ -1022,6 +1022,7 @@ static void __init __reserve_region_with_split(struct resource *root,
         struct resource *conflict;
         struct resource *res = alloc_resource(GFP_ATOMIC);
         struct resource *next_res = NULL;
+        int type = resource_type(root);
 
         if (!res)
                 return;
@@ -1029,7 +1030,7 @@ static void __init __reserve_region_with_split(struct resource *root,
         res->name = name;
         res->start = start;
         res->end = end;
-        res->flags = IORESOURCE_BUSY;
+        res->flags = type | IORESOURCE_BUSY;
         res->desc = IORES_DESC_NONE;
 
         while (1) {
@@ -1064,7 +1065,7 @@ static void __init __reserve_region_with_split(struct resource *root,
                                 next_res->name = name;
                                 next_res->start = conflict->end + 1;
                                 next_res->end = end;
-                                next_res->flags = IORESOURCE_BUSY;
+                                next_res->flags = type | IORESOURCE_BUSY;
                                 next_res->desc = IORES_DESC_NONE;
                         }
                 } else {
@@ -1478,7 +1479,7 @@ void __devm_release_region(struct device *dev, struct resource *parent,
 EXPORT_SYMBOL(__devm_release_region);
 
 /*
- * Called from init/main.c to reserve IO ports.
+ * Reserve I/O ports or memory based on "reserve=" kernel parameter.
  */
 #define MAXRESERVE 4
 static int __init reserve_setup(char *str)
@@ -1489,26 +1490,38 @@ static int __init reserve_setup(char *str)
         for (;;) {
                 unsigned int io_start, io_num;
                 int x = reserved;
+                struct resource *parent;
 
-                if (get_option (&str, &io_start) != 2)
+                if (get_option(&str, &io_start) != 2)
                         break;
-                if (get_option (&str, &io_num)   == 0)
+                if (get_option(&str, &io_num) == 0)
                         break;
                 if (x < MAXRESERVE) {
                         struct resource *res = reserve + x;
+
+                        /*
+                         * If the region starts below 0x10000, we assume it's
+                         * I/O port space; otherwise assume it's memory.
+                         */
+                        if (io_start < 0x10000) {
+                                res->flags = IORESOURCE_IO;
+                                parent = &ioport_resource;
+                        } else {
+                                res->flags = IORESOURCE_MEM;
+                                parent = &iomem_resource;
+                        }
                         res->name = "reserved";
                         res->start = io_start;
                         res->end = io_start + io_num - 1;
-                        res->flags = IORESOURCE_BUSY;
+                        res->flags |= IORESOURCE_BUSY;
                         res->desc = IORES_DESC_NONE;
                         res->child = NULL;
-                        if (request_resource(res->start >= 0x10000 ? &iomem_resource : &ioport_resource, res) == 0)
+                        if (request_resource(parent, res) == 0)
                                 reserved = x+1;
                 }
         }
         return 1;
 }
-
 __setup("reserve=", reserve_setup);
 
 /*