5 files changed, 333 insertions, 50 deletions
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index e6e90e80519a..f31bceb69c0d 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -1,8 +1,7 @@
 menu "SOC (System On Chip) specific Drivers"
 source "drivers/soc/bcm/Kconfig"
-source "drivers/soc/fsl/qbman/Kconfig"
+source "drivers/soc/fsl/Kconfig"
-source "drivers/soc/fsl/qe/Kconfig"
 source "drivers/soc/mediatek/Kconfig"
 source "drivers/soc/qcom/Kconfig"
 source "drivers/soc/rockchip/Kconfig"
diff --git a/drivers/soc/fsl/Kconfig b/drivers/soc/fsl/Kconfig
new file mode 100644
index 000000000000..7a9fb9baa66d
--- /dev/null
+++ b/drivers/soc/fsl/Kconfig
@@ -0,0 +1,18 @@
+#
+# Freescale SOC drivers
+#
+source "drivers/soc/fsl/qbman/Kconfig"
+source "drivers/soc/fsl/qe/Kconfig"
+config FSL_GUTS
+        bool
+        select SOC_BUS
+        help
+          The global utilities block controls power management, I/O device
+          enabling, power-onreset(POR) configuration monitoring, alternate
+          function selection for multiplexed signals,and clock control.
+          This driver is to manage and access global utilities block.
+          Initially only reading SVR and registering soc device are supported.
+          Other guts accesses, such as reading RCW, should eventually be moved
+          into this driver as well.
diff --git a/drivers/soc/fsl/Makefile b/drivers/soc/fsl/Makefile
index 75e1f5334821..44b3bebef24a 100644
--- a/drivers/soc/fsl/Makefile
+++ b/drivers/soc/fsl/Makefile
@@ -5,3 +5,4 @@
 obj-$(CONFIG_FSL_DPAA)                 += qbman/
 obj-$(CONFIG_QUICC_ENGINE)              += qe/
 obj-$(CONFIG_CPM)                       += qe/
+obj-$(CONFIG_FSL_GUTS)                  += guts.o
diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c
new file mode 100644
index 000000000000..0ac88263c2d7
--- /dev/null
+++ b/drivers/soc/fsl/guts.c
@@ -0,0 +1,236 @@
+/*
+ * Freescale QorIQ Platforms GUTS Driver
+ *
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/of_fdt.h>
+#include <linux/sys_soc.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/fsl/guts.h>
+struct guts {
+        struct ccsr_guts __iomem *regs;
+        bool little_endian;
+};
+struct fsl_soc_die_attr {
+        char    *die;
+        u32     svr;
+        u32     mask;
+};
+static struct guts *guts;
+static struct soc_device_attribute soc_dev_attr;
+static struct soc_device *soc_dev;
+/* SoC die attribute definition for QorIQ platform */
+static const struct fsl_soc_die_attr fsl_soc_die[] = {
+        /*
+         * Power Architecture-based SoCs T Series
+         */
+        /* Die: T4240, SoC: T4240/T4160/T4080 */
+        { .die          = "T4240",
+          .svr          = 0x82400000,
+          .mask         = 0xfff00000,
+        },
+        /* Die: T1040, SoC: T1040/T1020/T1042/T1022 */
+        { .die          = "T1040",
+          .svr          = 0x85200000,
+          .mask         = 0xfff00000,
+        },
+        /* Die: T2080, SoC: T2080/T2081 */
+        { .die          = "T2080",
+          .svr          = 0x85300000,
+          .mask         = 0xfff00000,
+        },
+        /* Die: T1024, SoC: T1024/T1014/T1023/T1013 */
+        { .die          = "T1024",
+          .svr          = 0x85400000,
+          .mask         = 0xfff00000,
+        },
+        /*
+         * ARM-based SoCs LS Series
+         */
+        /* Die: LS1043A, SoC: LS1043A/LS1023A */
+        { .die          = "LS1043A",
+          .svr          = 0x87920000,
+          .mask         = 0xffff0000,
+        },
+        /* Die: LS2080A, SoC: LS2080A/LS2040A/LS2085A */
+        { .die          = "LS2080A",
+          .svr          = 0x87010000,
+          .mask         = 0xff3f0000,
+        },
+        /* Die: LS1088A, SoC: LS1088A/LS1048A/LS1084A/LS1044A */
+        { .die          = "LS1088A",
+          .svr          = 0x87030000,
+          .mask         = 0xff3f0000,
+        },
+        /* Die: LS1012A, SoC: LS1012A */
+        { .die          = "LS1012A",
+          .svr          = 0x87040000,
+          .mask         = 0xffff0000,
+        },
+        /* Die: LS1046A, SoC: LS1046A/LS1026A */
+        { .die          = "LS1046A",
+          .svr          = 0x87070000,
+          .mask         = 0xffff0000,
+        },
+        /* Die: LS2088A, SoC: LS2088A/LS2048A/LS2084A/LS2044A */
+        { .die          = "LS2088A",
+          .svr          = 0x87090000,
+          .mask         = 0xff3f0000,
+        },
+        /* Die: LS1021A, SoC: LS1021A/LS1020A/LS1022A */
+        { .die          = "LS1021A",
+          .svr          = 0x87000000,
+          .mask         = 0xfff70000,
+        },
+        { },
+};
+static const struct fsl_soc_die_attr *fsl_soc_die_match(
+        u32 svr, const struct fsl_soc_die_attr *matches)
+{
+        while (matches->svr) {
+                if (matches->svr == (svr & matches->mask))
+                        return matches;
+                matches++;
+        };
+        return NULL;
+}
+u32 fsl_guts_get_svr(void)
+{
+        u32 svr = 0;
+        if (!guts || !guts->regs)
+                return svr;
+        if (guts->little_endian)
+                svr = ioread32(&guts->regs->svr);
+        else
+                svr = ioread32be(&guts->regs->svr);
+        return svr;
+}
+EXPORT_SYMBOL(fsl_guts_get_svr);
+static int fsl_guts_probe(struct platform_device *pdev)
+{
+        struct device_node *np = pdev->dev.of_node;
+        struct device *dev = &pdev->dev;
+        struct resource *res;
+        const struct fsl_soc_die_attr *soc_die;
+        const char *machine;
+        u32 svr;
+        /* Initialize guts */
+        guts = devm_kzalloc(dev, sizeof(*guts), GFP_KERNEL);
+        if (!guts)
+                return -ENOMEM;
+        guts->little_endian = of_property_read_bool(np, "little-endian");
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        guts->regs = devm_ioremap_resource(dev, res);
+        if (IS_ERR(guts->regs))
+                return PTR_ERR(guts->regs);
+        /* Register soc device */
+        machine = of_flat_dt_get_machine_name();
+        if (machine)
+                soc_dev_attr.machine = devm_kstrdup(dev, machine, GFP_KERNEL);
+        svr = fsl_guts_get_svr();
+        soc_die = fsl_soc_die_match(svr, fsl_soc_die);
+        if (soc_die) {
+                soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL,
+                                                     "QorIQ %s", soc_die->die);
+        } else {
+                soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL, "QorIQ");
+        }
+        soc_dev_attr.soc_id = devm_kasprintf(dev, GFP_KERNEL,
+                                             "svr:0x%08x", svr);
+        soc_dev_attr.revision = devm_kasprintf(dev, GFP_KERNEL, "%d.%d",
+                                               (svr >>  4) & 0xf, svr & 0xf);
+        soc_dev = soc_device_register(&soc_dev_attr);
+        if (IS_ERR(soc_dev))
+                return PTR_ERR(soc_dev);
+        pr_info("Machine: %s\n", soc_dev_attr.machine);
+        pr_info("SoC family: %s\n", soc_dev_attr.family);
+        pr_info("SoC ID: %s, Revision: %s\n",
+                soc_dev_attr.soc_id, soc_dev_attr.revision);
+        return 0;
+}
+static int fsl_guts_remove(struct platform_device *dev)
+{
+        soc_device_unregister(soc_dev);
+        return 0;
+}
+/*
+ * Table for matching compatible strings, for device tree
+ * guts node, for Freescale QorIQ SOCs.
+ */
+static const struct of_device_id fsl_guts_of_match[] = {
+        { .compatible = "fsl,qoriq-device-config-1.0", },
+        { .compatible = "fsl,qoriq-device-config-2.0", },
+        { .compatible = "fsl,p1010-guts", },
+        { .compatible = "fsl,p1020-guts", },
+        { .compatible = "fsl,p1021-guts", },
+        { .compatible = "fsl,p1022-guts", },
+        { .compatible = "fsl,p1023-guts", },
+        { .compatible = "fsl,p2020-guts", },
+        { .compatible = "fsl,bsc9131-guts", },
+        { .compatible = "fsl,bsc9132-guts", },
+        { .compatible = "fsl,mpc8536-guts", },
+        { .compatible = "fsl,mpc8544-guts", },
+        { .compatible = "fsl,mpc8548-guts", },
+        { .compatible = "fsl,mpc8568-guts", },
+        { .compatible = "fsl,mpc8569-guts", },
+        { .compatible = "fsl,mpc8572-guts", },
+        { .compatible = "fsl,ls1021a-dcfg", },
+        { .compatible = "fsl,ls1043a-dcfg", },
+        { .compatible = "fsl,ls2080a-dcfg", },
+        {}
+};
+MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
+static struct platform_driver fsl_guts_driver = {
+        .driver = {
+                .name = "fsl-guts",
+                .of_match_table = fsl_guts_of_match,
+        },
+        .probe = fsl_guts_probe,
+        .remove = fsl_guts_remove,
+};
+static int __init fsl_guts_init(void)
+{
+        return platform_driver_register(&fsl_guts_driver);
+}
+core_initcall(fsl_guts_init);
+static void __exit fsl_guts_exit(void)
+{
+        platform_driver_unregister(&fsl_guts_driver);
+}
+module_exit(fsl_guts_exit);
diff --git a/include/linux/fsl/guts.h b/include/linux/fsl/guts.h
index 649e9171a9b3..3efa3b861d44 100644
--- a/include/linux/fsl/guts.h
+++ b/include/linux/fsl/guts.h
@@ -29,83 +29,112 @@
 * #ifdefs.
 */
 struct ccsr_guts {
-        __be32  porpllsr;       /* 0x.0000 - POR PLL Ratio Status Register */
+        u32     porpllsr;       /* 0x.0000 - POR PLL Ratio Status Register */
-        __be32  porbmsr;        /* 0x.0004 - POR Boot Mode Status Register */
+        u32     porbmsr;        /* 0x.0004 - POR Boot Mode Status Register */
-        __be32  porimpscr;      /* 0x.0008 - POR I/O Impedance Status and Control Register */
+        u32     porimpscr;      /* 0x.0008 - POR I/O Impedance Status and
-        __be32  pordevsr;       /* 0x.000c - POR I/O Device Status Register */
+                                 *           Control Register
-        __be32  pordbgmsr;      /* 0x.0010 - POR Debug Mode Status Register */
+                                 */
-        __be32  pordevsr2;      /* 0x.0014 - POR device status register 2 */
+        u32     pordevsr;       /* 0x.000c - POR I/O Device Status Register */
+        u32     pordbgmsr;      /* 0x.0010 - POR Debug Mode Status Register */
+        u32     pordevsr2;      /* 0x.0014 - POR device status register 2 */
        u8      res018[0x20 - 0x18];
-        __be32  porcir;         /* 0x.0020 - POR Configuration Information Register */
+        u32     porcir;         /* 0x.0020 - POR Configuration Information
+                                 *           Register
+                                 */
        u8      res024[0x30 - 0x24];
-        __be32  gpiocr;         /* 0x.0030 - GPIO Control Register */
+        u32     gpiocr;         /* 0x.0030 - GPIO Control Register */
        u8      res034[0x40 - 0x34];
-        __be32  gpoutdr;        /* 0x.0040 - General-Purpose Output Data Register */
+        u32     gpoutdr;        /* 0x.0040 - General-Purpose Output Data
+                                 *           Register
+                                 */
        u8      res044[0x50 - 0x44];
-        __be32  gpindr;         /* 0x.0050 - General-Purpose Input Data Register */
+        u32     gpindr;         /* 0x.0050 - General-Purpose Input Data
+                                 *           Register
+                                 */
        u8      res054[0x60 - 0x54];
-        __be32  pmuxcr;         /* 0x.0060 - Alternate Function Signal Multiplex Control */
+        u32     pmuxcr;         /* 0x.0060 - Alternate Function Signal
-        __be32  pmuxcr2;        /* 0x.0064 - Alternate function signal multiplex control 2 */
+                                 *           Multiplex Control
-        __be32  dmuxcr;         /* 0x.0068 - DMA Mux Control Register */
+                                 */
+        u32     pmuxcr2;        /* 0x.0064 - Alternate function signal
+                                 *           multiplex control 2
+                                 */
+        u32     dmuxcr;         /* 0x.0068 - DMA Mux Control Register */
        u8      res06c[0x70 - 0x6c];
-        __be32  devdisr;        /* 0x.0070 - Device Disable Control */
+        u32     devdisr;        /* 0x.0070 - Device Disable Control */
 #define CCSR_GUTS_DEVDISR_TB1   0x00001000
 #define CCSR_GUTS_DEVDISR_TB0   0x00004000
-        __be32  devdisr2;       /* 0x.0074 - Device Disable Control 2 */
+        u32     devdisr2;       /* 0x.0074 - Device Disable Control 2 */
        u8      res078[0x7c - 0x78];
-        __be32  pmjcr;          /* 0x.007c - 4 Power Management Jog Control Register */
+        u32     pmjcr;          /* 0x.007c - 4 Power Management Jog Control
-        __be32  powmgtcsr;      /* 0x.0080 - Power Management Status and Control Register */
+                                 *           Register
-        __be32  pmrccr;         /* 0x.0084 - Power Management Reset Counter Configuration Register */
+                                 */
-        __be32  pmpdccr;        /* 0x.0088 - Power Management Power Down Counter Configuration Register */
+        u32     powmgtcsr;      /* 0x.0080 - Power Management Status and
-        __be32  pmcdr;          /* 0x.008c - 4Power management clock disable register */
+                                 *           Control Register
-        __be32  mcpsumr;        /* 0x.0090 - Machine Check Summary Register */
+                                 */
-        __be32  rstrscr;        /* 0x.0094 - Reset Request Status and Control Register */
+        u32     pmrccr;         /* 0x.0084 - Power Management Reset Counter
-        __be32  ectrstcr;       /* 0x.0098 - Exception reset control register */
+                                 *           Configuration Register
-        __be32  autorstsr;      /* 0x.009c - Automatic reset status register */
+                                 */
-        __be32  pvr;            /* 0x.00a0 - Processor Version Register */
+        u32     pmpdccr;        /* 0x.0088 - Power Management Power Down Counter
-        __be32  svr;            /* 0x.00a4 - System Version Register */
+                                 *           Configuration Register
+                                 */
+        u32     pmcdr;          /* 0x.008c - 4Power management clock disable
+                                 *           register
+                                 */
+        u32     mcpsumr;        /* 0x.0090 - Machine Check Summary Register */
+        u32     rstrscr;        /* 0x.0094 - Reset Request Status and
+                                 *           Control Register
+                                 */
+        u32     ectrstcr;       /* 0x.0098 - Exception reset control register */
+        u32     autorstsr;      /* 0x.009c - Automatic reset status register */
+        u32     pvr;            /* 0x.00a0 - Processor Version Register */
+        u32     svr;            /* 0x.00a4 - System Version Register */
        u8      res0a8[0xb0 - 0xa8];
-        __be32  rstcr;          /* 0x.00b0 - Reset Control Register */
+        u32     rstcr;          /* 0x.00b0 - Reset Control Register */
        u8      res0b4[0xc0 - 0xb4];
-        __be32  iovselsr;       /* 0x.00c0 - I/O voltage select status register
+        u32     iovselsr;       /* 0x.00c0 - I/O voltage select status register
                                             Called 'elbcvselcr' on 86xx SOCs */
        u8      res0c4[0x100 - 0xc4];
-        __be32  rcwsr[16];      /* 0x.0100 - Reset Control Word Status registers
+        u32     rcwsr[16];      /* 0x.0100 - Reset Control Word Status registers
                                             There are 16 registers */
        u8      res140[0x224 - 0x140];
-        __be32  iodelay1;       /* 0x.0224 - IO delay control register 1 */
+        u32     iodelay1;       /* 0x.0224 - IO delay control register 1 */
-        __be32  iodelay2;       /* 0x.0228 - IO delay control register 2 */
+        u32     iodelay2;       /* 0x.0228 - IO delay control register 2 */
        u8      res22c[0x604 - 0x22c];
-        __be32  pamubypenr;     /* 0x.604 - PAMU bypass enable register */
+        u32     pamubypenr;     /* 0x.604 - PAMU bypass enable register */
        u8      res608[0x800 - 0x608];
-        __be32  clkdvdr;        /* 0x.0800 - Clock Divide Register */
+        u32     clkdvdr;        /* 0x.0800 - Clock Divide Register */
        u8      res804[0x900 - 0x804];
-        __be32  ircr;           /* 0x.0900 - Infrared Control Register */
+        u32     ircr;           /* 0x.0900 - Infrared Control Register */
        u8      res904[0x908 - 0x904];
-        __be32  dmacr;          /* 0x.0908 - DMA Control Register */
+        u32     dmacr;          /* 0x.0908 - DMA Control Register */
        u8      res90c[0x914 - 0x90c];
-        __be32  elbccr;         /* 0x.0914 - eLBC Control Register */
+        u32     elbccr;         /* 0x.0914 - eLBC Control Register */
        u8      res918[0xb20 - 0x918];
-        __be32  ddr1clkdr;      /* 0x.0b20 - DDR1 Clock Disable Register */
+        u32     ddr1clkdr;      /* 0x.0b20 - DDR1 Clock Disable Register */
-        __be32  ddr2clkdr;      /* 0x.0b24 - DDR2 Clock Disable Register */
+        u32     ddr2clkdr;      /* 0x.0b24 - DDR2 Clock Disable Register */
-        __be32  ddrclkdr;       /* 0x.0b28 - DDR Clock Disable Register */
+        u32     ddrclkdr;       /* 0x.0b28 - DDR Clock Disable Register */
        u8      resb2c[0xe00 - 0xb2c];
-        __be32  clkocr;         /* 0x.0e00 - Clock Out Select Register */
+        u32     clkocr;         /* 0x.0e00 - Clock Out Select Register */
        u8      rese04[0xe10 - 0xe04];
-        __be32  ddrdllcr;       /* 0x.0e10 - DDR DLL Control Register */
+        u32     ddrdllcr;       /* 0x.0e10 - DDR DLL Control Register */
        u8      rese14[0xe20 - 0xe14];
-        __be32  lbcdllcr;       /* 0x.0e20 - LBC DLL Control Register */
+        u32     lbcdllcr;       /* 0x.0e20 - LBC DLL Control Register */
-        __be32  cpfor;          /* 0x.0e24 - L2 charge pump fuse override register */
+        u32     cpfor;          /* 0x.0e24 - L2 charge pump fuse override
+                                 *           register
+                                 */
        u8      rese28[0xf04 - 0xe28];
-        __be32  srds1cr0;       /* 0x.0f04 - SerDes1 Control Register 0 */
+        u32     srds1cr0;       /* 0x.0f04 - SerDes1 Control Register 0 */
-        __be32  srds1cr1;       /* 0x.0f08 - SerDes1 Control Register 0 */
+        u32     srds1cr1;       /* 0x.0f08 - SerDes1 Control Register 0 */
        u8      resf0c[0xf2c - 0xf0c];
-        __be32  itcr;           /* 0x.0f2c - Internal transaction control register */
+        u32     itcr;           /* 0x.0f2c - Internal transaction control
+                                 *           register
+                                 */
        u8      resf30[0xf40 - 0xf30];
-        __be32  srds2cr0;       /* 0x.0f40 - SerDes2 Control Register 0 */
+        u32     srds2cr0;       /* 0x.0f40 - SerDes2 Control Register 0 */
-        __be32  srds2cr1;       /* 0x.0f44 - SerDes2 Control Register 0 */
+        u32     srds2cr1;       /* 0x.0f44 - SerDes2 Control Register 0 */
 } __attribute__ ((packed));
+u32 fsl_guts_get_svr(void);
 /* Alternate function signal multiplex control */
 #define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))

diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index e6e90e80519a..f31bceb69c0d 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig
@@ -1,8 +1,7 @@
1	menu "SOC (System On Chip) specific Drivers"	1	menu "SOC (System On Chip) specific Drivers"
2		2
3	source "drivers/soc/bcm/Kconfig"	3	source "drivers/soc/bcm/Kconfig"
4	source "drivers/soc/fsl/qbman/Kconfig"	4	source "drivers/soc/fsl/Kconfig"
5	source "drivers/soc/fsl/qe/Kconfig"
6	source "drivers/soc/mediatek/Kconfig"	5	source "drivers/soc/mediatek/Kconfig"
7	source "drivers/soc/qcom/Kconfig"	6	source "drivers/soc/qcom/Kconfig"
8	source "drivers/soc/rockchip/Kconfig"	7	source "drivers/soc/rockchip/Kconfig"


diff --git a/drivers/soc/fsl/Kconfig b/drivers/soc/fsl/Kconfig new file mode 100644 index 000000000000..7a9fb9baa66d --- /dev/null +++ b/drivers/soc/fsl/Kconfig
@@ -0,0 +1,18 @@
		1	#
		2	# Freescale SOC drivers
		3	#
		4
		5	source "drivers/soc/fsl/qbman/Kconfig"
		6	source "drivers/soc/fsl/qe/Kconfig"
		7
		8	config FSL_GUTS
		9	bool
		10	select SOC_BUS
		11	help
		12	The global utilities block controls power management, I/O device
		13	enabling, power-onreset(POR) configuration monitoring, alternate
		14	function selection for multiplexed signals,and clock control.
		15	This driver is to manage and access global utilities block.
		16	Initially only reading SVR and registering soc device are supported.
		17	Other guts accesses, such as reading RCW, should eventually be moved
		18	into this driver as well.


diff --git a/drivers/soc/fsl/Makefile b/drivers/soc/fsl/Makefile index 75e1f5334821..44b3bebef24a 100644 --- a/drivers/soc/fsl/Makefile +++ b/drivers/soc/fsl/Makefile
@@ -5,3 +5,4 @@
5	obj-$(CONFIG_FSL_DPAA) += qbman/	5	obj-$(CONFIG_FSL_DPAA) += qbman/
6	obj-$(CONFIG_QUICC_ENGINE) += qe/	6	obj-$(CONFIG_QUICC_ENGINE) += qe/
7	obj-$(CONFIG_CPM) += qe/	7	obj-$(CONFIG_CPM) += qe/
		8	obj-$(CONFIG_FSL_GUTS) += guts.o


diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c new file mode 100644 index 000000000000..0ac88263c2d7 --- /dev/null +++ b/drivers/soc/fsl/guts.c
@@ -0,0 +1,236 @@
		1	/*
		2	* Freescale QorIQ Platforms GUTS Driver
		3	*
		4	* Copyright (C) 2016 Freescale Semiconductor, Inc.
		5	*
		6	* This program is free software; you can redistribute it and/or modify
		7	* it under the terms of the GNU General Public License as published by
		8	* the Free Software Foundation; either version 2 of the License, or
		9	* (at your option) any later version.
		10	*/
		11
		12	#include <linux/io.h>
		13	#include <linux/slab.h>
		14	#include <linux/module.h>
		15	#include <linux/of_fdt.h>
		16	#include <linux/sys_soc.h>
		17	#include <linux/of_address.h>
		18	#include <linux/platform_device.h>
		19	#include <linux/fsl/guts.h>
		20
		21	struct guts {
		22	struct ccsr_guts __iomem *regs;
		23	bool little_endian;
		24	};
		25
		26	struct fsl_soc_die_attr {
		27	char *die;
		28	u32 svr;
		29	u32 mask;
		30	};
		31
		32	static struct guts *guts;
		33	static struct soc_device_attribute soc_dev_attr;
		34	static struct soc_device *soc_dev;
		35
		36
		37	/* SoC die attribute definition for QorIQ platform */
		38	static const struct fsl_soc_die_attr fsl_soc_die[] = {
		39	/*
		40	* Power Architecture-based SoCs T Series
		41	*/
		42
		43	/* Die: T4240, SoC: T4240/T4160/T4080 */
		44	{ .die = "T4240",
		45	.svr = 0x82400000,
		46	.mask = 0xfff00000,
		47	},
		48	/* Die: T1040, SoC: T1040/T1020/T1042/T1022 */
		49	{ .die = "T1040",
		50	.svr = 0x85200000,
		51	.mask = 0xfff00000,
		52	},
		53	/* Die: T2080, SoC: T2080/T2081 */
		54	{ .die = "T2080",
		55	.svr = 0x85300000,
		56	.mask = 0xfff00000,
		57	},
		58	/* Die: T1024, SoC: T1024/T1014/T1023/T1013 */
		59	{ .die = "T1024",
		60	.svr = 0x85400000,
		61	.mask = 0xfff00000,
		62	},
		63
		64	/*
		65	* ARM-based SoCs LS Series
		66	*/
		67
		68	/* Die: LS1043A, SoC: LS1043A/LS1023A */
		69	{ .die = "LS1043A",
		70	.svr = 0x87920000,
		71	.mask = 0xffff0000,
		72	},
		73	/* Die: LS2080A, SoC: LS2080A/LS2040A/LS2085A */
		74	{ .die = "LS2080A",
		75	.svr = 0x87010000,
		76	.mask = 0xff3f0000,
		77	},
		78	/* Die: LS1088A, SoC: LS1088A/LS1048A/LS1084A/LS1044A */
		79	{ .die = "LS1088A",
		80	.svr = 0x87030000,
		81	.mask = 0xff3f0000,
		82	},
		83	/* Die: LS1012A, SoC: LS1012A */
		84	{ .die = "LS1012A",
		85	.svr = 0x87040000,
		86	.mask = 0xffff0000,
		87	},
		88	/* Die: LS1046A, SoC: LS1046A/LS1026A */
		89	{ .die = "LS1046A",
		90	.svr = 0x87070000,
		91	.mask = 0xffff0000,
		92	},
		93	/* Die: LS2088A, SoC: LS2088A/LS2048A/LS2084A/LS2044A */
		94	{ .die = "LS2088A",
		95	.svr = 0x87090000,
		96	.mask = 0xff3f0000,
		97	},
		98	/* Die: LS1021A, SoC: LS1021A/LS1020A/LS1022A */
		99	{ .die = "LS1021A",
		100	.svr = 0x87000000,
		101	.mask = 0xfff70000,
		102	},
		103	{ },
		104	};
		105
		106	static const struct fsl_soc_die_attr *fsl_soc_die_match(
		107	u32 svr, const struct fsl_soc_die_attr *matches)
		108	{
		109	while (matches->svr) {
		110	if (matches->svr == (svr & matches->mask))
		111	return matches;
		112	matches++;
		113	};
		114	return NULL;
		115	}
		116
		117	u32 fsl_guts_get_svr(void)
		118	{
		119	u32 svr = 0;
		120
		121	if (!guts \|\| !guts->regs)
		122	return svr;
		123
		124	if (guts->little_endian)
		125	svr = ioread32(&guts->regs->svr);
		126	else
		127	svr = ioread32be(&guts->regs->svr);
		128
		129	return svr;
		130	}
		131	EXPORT_SYMBOL(fsl_guts_get_svr);
		132
		133	static int fsl_guts_probe(struct platform_device *pdev)
		134	{
		135	struct device_node *np = pdev->dev.of_node;
		136	struct device *dev = &pdev->dev;
		137	struct resource *res;
		138	const struct fsl_soc_die_attr *soc_die;
		139	const char *machine;
		140	u32 svr;
		141
		142	/* Initialize guts */
		143	guts = devm_kzalloc(dev, sizeof(*guts), GFP_KERNEL);
		144	if (!guts)
		145	return -ENOMEM;
		146
		147	guts->little_endian = of_property_read_bool(np, "little-endian");
		148
		149	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		150	guts->regs = devm_ioremap_resource(dev, res);
		151	if (IS_ERR(guts->regs))
		152	return PTR_ERR(guts->regs);
		153
		154	/* Register soc device */
		155	machine = of_flat_dt_get_machine_name();
		156	if (machine)
		157	soc_dev_attr.machine = devm_kstrdup(dev, machine, GFP_KERNEL);
		158
		159	svr = fsl_guts_get_svr();
		160	soc_die = fsl_soc_die_match(svr, fsl_soc_die);
		161	if (soc_die) {
		162	soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL,
		163	"QorIQ %s", soc_die->die);
		164	} else {
		165	soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL, "QorIQ");
		166	}
		167	soc_dev_attr.soc_id = devm_kasprintf(dev, GFP_KERNEL,
		168	"svr:0x%08x", svr);
		169	soc_dev_attr.revision = devm_kasprintf(dev, GFP_KERNEL, "%d.%d",
		170	(svr >> 4) & 0xf, svr & 0xf);
		171
		172	soc_dev = soc_device_register(&soc_dev_attr);
		173	if (IS_ERR(soc_dev))
		174	return PTR_ERR(soc_dev);
		175
		176	pr_info("Machine: %s\n", soc_dev_attr.machine);
		177	pr_info("SoC family: %s\n", soc_dev_attr.family);
		178	pr_info("SoC ID: %s, Revision: %s\n",
		179	soc_dev_attr.soc_id, soc_dev_attr.revision);
		180	return 0;
		181	}
		182
		183	static int fsl_guts_remove(struct platform_device *dev)
		184	{
		185	soc_device_unregister(soc_dev);
		186	return 0;
		187	}
		188
		189	/*
		190	* Table for matching compatible strings, for device tree
		191	* guts node, for Freescale QorIQ SOCs.
		192	*/
		193	static const struct of_device_id fsl_guts_of_match[] = {
		194	{ .compatible = "fsl,qoriq-device-config-1.0", },
		195	{ .compatible = "fsl,qoriq-device-config-2.0", },
		196	{ .compatible = "fsl,p1010-guts", },
		197	{ .compatible = "fsl,p1020-guts", },
		198	{ .compatible = "fsl,p1021-guts", },
		199	{ .compatible = "fsl,p1022-guts", },
		200	{ .compatible = "fsl,p1023-guts", },
		201	{ .compatible = "fsl,p2020-guts", },
		202	{ .compatible = "fsl,bsc9131-guts", },
		203	{ .compatible = "fsl,bsc9132-guts", },
		204	{ .compatible = "fsl,mpc8536-guts", },
		205	{ .compatible = "fsl,mpc8544-guts", },
		206	{ .compatible = "fsl,mpc8548-guts", },
		207	{ .compatible = "fsl,mpc8568-guts", },
		208	{ .compatible = "fsl,mpc8569-guts", },
		209	{ .compatible = "fsl,mpc8572-guts", },
		210	{ .compatible = "fsl,ls1021a-dcfg", },
		211	{ .compatible = "fsl,ls1043a-dcfg", },
		212	{ .compatible = "fsl,ls2080a-dcfg", },
		213	{}
		214	};
		215	MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
		216
		217	static struct platform_driver fsl_guts_driver = {
		218	.driver = {
		219	.name = "fsl-guts",
		220	.of_match_table = fsl_guts_of_match,
		221	},
		222	.probe = fsl_guts_probe,
		223	.remove = fsl_guts_remove,
		224	};
		225
		226	static int __init fsl_guts_init(void)
		227	{
		228	return platform_driver_register(&fsl_guts_driver);
		229	}
		230	core_initcall(fsl_guts_init);
		231
		232	static void __exit fsl_guts_exit(void)
		233	{
		234	platform_driver_unregister(&fsl_guts_driver);
		235	}
		236	module_exit(fsl_guts_exit);


diff --git a/include/linux/fsl/guts.h b/include/linux/fsl/guts.h index 649e9171a9b3..3efa3b861d44 100644 --- a/include/linux/fsl/guts.h +++ b/include/linux/fsl/guts.h
@@ -29,83 +29,112 @@
29	* #ifdefs.	29	* #ifdefs.
30	*/	30	*/
31	struct ccsr_guts {	31	struct ccsr_guts {
32	__be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */	32	u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
33	__be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */	33	u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
34	__be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */	34	u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and
35	__be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */	35	* Control Register
36	__be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */	36	*/
37	__be32 pordevsr2; /* 0x.0014 - POR device status register 2 */	37	u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
		38	u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
		39	u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
38	u8 res018[0x20 - 0x18];	40	u8 res018[0x20 - 0x18];
39	__be32 porcir; /* 0x.0020 - POR Configuration Information Register */	41	u32 porcir; /* 0x.0020 - POR Configuration Information
		42	* Register
		43	*/
40	u8 res024[0x30 - 0x24];	44	u8 res024[0x30 - 0x24];
41	__be32 gpiocr; /* 0x.0030 - GPIO Control Register */	45	u32 gpiocr; /* 0x.0030 - GPIO Control Register */
42	u8 res034[0x40 - 0x34];	46	u8 res034[0x40 - 0x34];
43	__be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */	47	u32 gpoutdr; /* 0x.0040 - General-Purpose Output Data
		48	* Register
		49	*/
44	u8 res044[0x50 - 0x44];	50	u8 res044[0x50 - 0x44];
45	__be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */	51	u32 gpindr; /* 0x.0050 - General-Purpose Input Data
		52	* Register
		53	*/
46	u8 res054[0x60 - 0x54];	54	u8 res054[0x60 - 0x54];
47	__be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */	55	u32 pmuxcr; /* 0x.0060 - Alternate Function Signal
48	__be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */	56	* Multiplex Control
49	__be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */	57	*/
		58	u32 pmuxcr2; /* 0x.0064 - Alternate function signal
		59	* multiplex control 2
		60	*/
		61	u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
50	u8 res06c[0x70 - 0x6c];	62	u8 res06c[0x70 - 0x6c];
51	__be32 devdisr; /* 0x.0070 - Device Disable Control */	63	u32 devdisr; /* 0x.0070 - Device Disable Control */
52	#define CCSR_GUTS_DEVDISR_TB1 0x00001000	64	#define CCSR_GUTS_DEVDISR_TB1 0x00001000
53	#define CCSR_GUTS_DEVDISR_TB0 0x00004000	65	#define CCSR_GUTS_DEVDISR_TB0 0x00004000
54	__be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */	66	u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
55	u8 res078[0x7c - 0x78];	67	u8 res078[0x7c - 0x78];
56	__be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */	68	u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control
57	__be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */	69	* Register
58	__be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */	70	*/
59	__be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */	71	u32 powmgtcsr; /* 0x.0080 - Power Management Status and
60	__be32 pmcdr; /* 0x.008c - 4Power management clock disable register */	72	* Control Register
61	__be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */	73	*/
62	__be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */	74	u32 pmrccr; /* 0x.0084 - Power Management Reset Counter
63	__be32 ectrstcr; /* 0x.0098 - Exception reset control register */	75	* Configuration Register
64	__be32 autorstsr; /* 0x.009c - Automatic reset status register */	76	*/
65	__be32 pvr; /* 0x.00a0 - Processor Version Register */	77	u32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter
66	__be32 svr; /* 0x.00a4 - System Version Register */	78	* Configuration Register
		79	*/
		80	u32 pmcdr; /* 0x.008c - 4Power management clock disable
		81	* register
		82	*/
		83	u32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
		84	u32 rstrscr; /* 0x.0094 - Reset Request Status and
		85	* Control Register
		86	*/
		87	u32 ectrstcr; /* 0x.0098 - Exception reset control register */
		88	u32 autorstsr; /* 0x.009c - Automatic reset status register */
		89	u32 pvr; /* 0x.00a0 - Processor Version Register */
		90	u32 svr; /* 0x.00a4 - System Version Register */
67	u8 res0a8[0xb0 - 0xa8];	91	u8 res0a8[0xb0 - 0xa8];
68	__be32 rstcr; /* 0x.00b0 - Reset Control Register */	92	u32 rstcr; /* 0x.00b0 - Reset Control Register */
69	u8 res0b4[0xc0 - 0xb4];	93	u8 res0b4[0xc0 - 0xb4];
70	__be32 iovselsr; /* 0x.00c0 - I/O voltage select status register	94	u32 iovselsr; /* 0x.00c0 - I/O voltage select status register
71	Called 'elbcvselcr' on 86xx SOCs */	95	Called 'elbcvselcr' on 86xx SOCs */
72	u8 res0c4[0x100 - 0xc4];	96	u8 res0c4[0x100 - 0xc4];
73	__be32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers	97	u32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
74	There are 16 registers */	98	There are 16 registers */
75	u8 res140[0x224 - 0x140];	99	u8 res140[0x224 - 0x140];
76	__be32 iodelay1; /* 0x.0224 - IO delay control register 1 */	100	u32 iodelay1; /* 0x.0224 - IO delay control register 1 */
77	__be32 iodelay2; /* 0x.0228 - IO delay control register 2 */	101	u32 iodelay2; /* 0x.0228 - IO delay control register 2 */
78	u8 res22c[0x604 - 0x22c];	102	u8 res22c[0x604 - 0x22c];
79	__be32 pamubypenr; /* 0x.604 - PAMU bypass enable register */	103	u32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
80	u8 res608[0x800 - 0x608];	104	u8 res608[0x800 - 0x608];
81	__be32 clkdvdr; /* 0x.0800 - Clock Divide Register */	105	u32 clkdvdr; /* 0x.0800 - Clock Divide Register */
82	u8 res804[0x900 - 0x804];	106	u8 res804[0x900 - 0x804];
83	__be32 ircr; /* 0x.0900 - Infrared Control Register */	107	u32 ircr; /* 0x.0900 - Infrared Control Register */
84	u8 res904[0x908 - 0x904];	108	u8 res904[0x908 - 0x904];
85	__be32 dmacr; /* 0x.0908 - DMA Control Register */	109	u32 dmacr; /* 0x.0908 - DMA Control Register */
86	u8 res90c[0x914 - 0x90c];	110	u8 res90c[0x914 - 0x90c];
87	__be32 elbccr; /* 0x.0914 - eLBC Control Register */	111	u32 elbccr; /* 0x.0914 - eLBC Control Register */
88	u8 res918[0xb20 - 0x918];	112	u8 res918[0xb20 - 0x918];
89	__be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */	113	u32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
90	__be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */	114	u32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
91	__be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */	115	u32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
92	u8 resb2c[0xe00 - 0xb2c];	116	u8 resb2c[0xe00 - 0xb2c];
93	__be32 clkocr; /* 0x.0e00 - Clock Out Select Register */	117	u32 clkocr; /* 0x.0e00 - Clock Out Select Register */
94	u8 rese04[0xe10 - 0xe04];	118	u8 rese04[0xe10 - 0xe04];
95	__be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */	119	u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
96	u8 rese14[0xe20 - 0xe14];	120	u8 rese14[0xe20 - 0xe14];
97	__be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */	121	u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
98	__be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */	122	u32 cpfor; /* 0x.0e24 - L2 charge pump fuse override
		123	* register
		124	*/
99	u8 rese28[0xf04 - 0xe28];	125	u8 rese28[0xf04 - 0xe28];
100	__be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */	126	u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
101	__be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */	127	u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
102	u8 resf0c[0xf2c - 0xf0c];	128	u8 resf0c[0xf2c - 0xf0c];
103	__be32 itcr; /* 0x.0f2c - Internal transaction control register */	129	u32 itcr; /* 0x.0f2c - Internal transaction control
		130	* register
		131	*/
104	u8 resf30[0xf40 - 0xf30];	132	u8 resf30[0xf40 - 0xf30];
105	__be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */	133	u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
106	__be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */	134	u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
107	} __attribute__ ((packed));	135	} __attribute__ ((packed));
108		136
		137	u32 fsl_guts_get_svr(void);
109		138
110	/* Alternate function signal multiplex control */	139	/* Alternate function signal multiplex control */
111	#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))	140	#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))