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-rw-r--r--Documentation/devicetree/bindings/ata/ahci-platform.txt1
-rw-r--r--Documentation/devicetree/bindings/ata/imx-sata.txt1
-rw-r--r--Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt36
-rw-r--r--drivers/ata/Kconfig16
-rw-r--r--drivers/ata/Makefile1
-rw-r--r--drivers/ata/ahci.h1
-rw-r--r--drivers/ata/ahci_imx.c371
-rw-r--r--drivers/ata/ahci_tegra.c359
-rw-r--r--drivers/ata/libahci_platform.c24
-rw-r--r--drivers/ata/libata-core.c46
-rw-r--r--drivers/ata/libata-transport.c4
-rw-r--r--drivers/ata/libata.h2
-rw-r--r--drivers/ata/pata_arasan_cf.c6
-rw-r--r--drivers/ata/pata_bk3710.c8
-rw-r--r--drivers/ata/pata_falcon.c8
-rw-r--r--drivers/ata/pata_gayle.c219
-rw-r--r--drivers/ata/pata_it821x.c6
-rw-r--r--drivers/ata/pata_macio.c12
-rw-r--r--drivers/ata/pata_mpc52xx.c1
-rw-r--r--drivers/ata/pata_samsung_cf.c4
-rw-r--r--drivers/ata/sata_dwc_460ex.c1
-rw-r--r--include/linux/libata.h1
-rw-r--r--include/linux/mfd/syscon/imx6q-iomuxc-gpr.h2
23 files changed, 995 insertions, 135 deletions
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index c760ecb81381..f4006d3c9fdf 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -30,6 +30,7 @@ compatible:
30Optional properties: 30Optional properties:
31- dma-coherent : Present if dma operations are coherent 31- dma-coherent : Present if dma operations are coherent
32- clocks : a list of phandle + clock specifier pairs 32- clocks : a list of phandle + clock specifier pairs
33- resets : a list of phandle + reset specifier pairs
33- target-supply : regulator for SATA target power 34- target-supply : regulator for SATA target power
34- phys : reference to the SATA PHY node 35- phys : reference to the SATA PHY node
35- phy-names : must be "sata-phy" 36- phy-names : must be "sata-phy"
diff --git a/Documentation/devicetree/bindings/ata/imx-sata.txt b/Documentation/devicetree/bindings/ata/imx-sata.txt
index a3d14719e478..781f88751762 100644
--- a/Documentation/devicetree/bindings/ata/imx-sata.txt
+++ b/Documentation/devicetree/bindings/ata/imx-sata.txt
@@ -7,6 +7,7 @@ Required properties:
7- compatible : should be one of the following: 7- compatible : should be one of the following:
8 - "fsl,imx53-ahci" for i.MX53 SATA controller 8 - "fsl,imx53-ahci" for i.MX53 SATA controller
9 - "fsl,imx6q-ahci" for i.MX6Q SATA controller 9 - "fsl,imx6q-ahci" for i.MX6Q SATA controller
10 - "fsl,imx6qp-ahci" for i.MX6QP SATA controller
10- interrupts : interrupt mapping for SATA IRQ 11- interrupts : interrupt mapping for SATA IRQ
11- reg : registers mapping 12- reg : registers mapping
12- clocks : list of clock specifiers, must contain an entry for each 13- clocks : list of clock specifiers, must contain an entry for each
diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
index 66c83c3e8915..12ab2f723eb0 100644
--- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
+++ b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt
@@ -1,9 +1,10 @@
1Tegra124 SoC SATA AHCI controller 1Tegra SoC SATA AHCI controller
2 2
3Required properties : 3Required properties :
4- compatible : For Tegra124, must contain "nvidia,tegra124-ahci". Otherwise, 4- compatible : Must be one of:
5 must contain '"nvidia,<chip>-ahci", "nvidia,tegra124-ahci"', where <chip> 5 - Tegra124 : "nvidia,tegra124-ahci"
6 is tegra132. 6 - Tegra132 : "nvidia,tegra132-ahci", "nvidia,tegra124-ahci"
7 - Tegra210 : "nvidia,tegra210-ahci"
7- reg : Should contain 2 entries: 8- reg : Should contain 2 entries:
8 - AHCI register set (SATA BAR5) 9 - AHCI register set (SATA BAR5)
9 - SATA register set 10 - SATA register set
@@ -13,8 +14,6 @@ Required properties :
13- clock-names : Must include the following entries: 14- clock-names : Must include the following entries:
14 - sata 15 - sata
15 - sata-oob 16 - sata-oob
16 - cml1
17 - pll_e
18- resets : Must contain an entry for each entry in reset-names. 17- resets : Must contain an entry for each entry in reset-names.
19 See ../reset/reset.txt for details. 18 See ../reset/reset.txt for details.
20- reset-names : Must include the following entries: 19- reset-names : Must include the following entries:
@@ -24,9 +23,22 @@ Required properties :
24- phys : Must contain an entry for each entry in phy-names. 23- phys : Must contain an entry for each entry in phy-names.
25 See ../phy/phy-bindings.txt for details. 24 See ../phy/phy-bindings.txt for details.
26- phy-names : Must include the following entries: 25- phy-names : Must include the following entries:
27 - sata-phy : XUSB PADCTL SATA PHY 26 - For Tegra124 and Tegra132:
28- hvdd-supply : Defines the SATA HVDD regulator 27 - sata-phy : XUSB PADCTL SATA PHY
29- vddio-supply : Defines the SATA VDDIO regulator 28- For Tegra124 and Tegra132:
30- avdd-supply : Defines the SATA AVDD regulator 29 - hvdd-supply : Defines the SATA HVDD regulator
31- target-5v-supply : Defines the SATA 5V power regulator 30 - vddio-supply : Defines the SATA VDDIO regulator
32- target-12v-supply : Defines the SATA 12V power regulator 31 - avdd-supply : Defines the SATA AVDD regulator
32 - target-5v-supply : Defines the SATA 5V power regulator
33 - target-12v-supply : Defines the SATA 12V power regulator
34
35Optional properties:
36- reg :
37 - AUX register set
38- clock-names :
39 - cml1 :
40 cml1 clock should be defined here if the PHY driver
41 doesn't manage them. If it does, they should not be.
42- phy-names :
43 - For T210:
44 - sata-phy
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 4582fa27cf37..2b16e7c8fff3 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -211,10 +211,10 @@ config AHCI_SUNXI
211 If unsure, say N. 211 If unsure, say N.
212 212
213config AHCI_TEGRA 213config AHCI_TEGRA
214 tristate "NVIDIA Tegra124 AHCI SATA support" 214 tristate "NVIDIA Tegra AHCI SATA support"
215 depends on ARCH_TEGRA 215 depends on ARCH_TEGRA
216 help 216 help
217 This option enables support for the NVIDIA Tegra124 SoC's 217 This option enables support for the NVIDIA Tegra SoC's
218 onboard AHCI SATA. 218 onboard AHCI SATA.
219 219
220 If unsure, say N. 220 If unsure, say N.
@@ -954,6 +954,18 @@ config PATA_FALCON
954 954
955 If unsure, say N. 955 If unsure, say N.
956 956
957config PATA_GAYLE
958 tristate "Amiga Gayle PATA support"
959 depends on M68K && AMIGA
960 help
961 This option enables support for the on-board IDE
962 interfaces on some Amiga models (A600, A1200,
963 A4000 and A4000T) and also for IDE interfaces on
964 the Zorro expansion bus (M-Tech E-Matrix 530
965 expansion card).
966
967 If unsure, say N.
968
957config PATA_ISAPNP 969config PATA_ISAPNP
958 tristate "ISA Plug and Play PATA support" 970 tristate "ISA Plug and Play PATA support"
959 depends on ISAPNP 971 depends on ISAPNP
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 6dae8c985e8e..d21cdd83f7ab 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -97,6 +97,7 @@ obj-$(CONFIG_PATA_WINBOND) += pata_sl82c105.o
97# SFF PIO only 97# SFF PIO only
98obj-$(CONFIG_PATA_CMD640_PCI) += pata_cmd640.o 98obj-$(CONFIG_PATA_CMD640_PCI) += pata_cmd640.o
99obj-$(CONFIG_PATA_FALCON) += pata_falcon.o 99obj-$(CONFIG_PATA_FALCON) += pata_falcon.o
100obj-$(CONFIG_PATA_GAYLE) += pata_gayle.o
100obj-$(CONFIG_PATA_ISAPNP) += pata_isapnp.o 101obj-$(CONFIG_PATA_ISAPNP) += pata_isapnp.o
101obj-$(CONFIG_PATA_IXP4XX_CF) += pata_ixp4xx_cf.o 102obj-$(CONFIG_PATA_IXP4XX_CF) += pata_ixp4xx_cf.o
102obj-$(CONFIG_PATA_MPIIX) += pata_mpiix.o 103obj-$(CONFIG_PATA_MPIIX) += pata_mpiix.o
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index a9d996e17d75..4356ef1d28a8 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -350,6 +350,7 @@ struct ahci_host_priv {
350 u32 em_msg_type; /* EM message type */ 350 u32 em_msg_type; /* EM message type */
351 bool got_runtime_pm; /* Did we do pm_runtime_get? */ 351 bool got_runtime_pm; /* Did we do pm_runtime_get? */
352 struct clk *clks[AHCI_MAX_CLKS]; /* Optional */ 352 struct clk *clks[AHCI_MAX_CLKS]; /* Optional */
353 struct reset_control *rsts; /* Optional */
353 struct regulator **target_pwrs; /* Optional */ 354 struct regulator **target_pwrs; /* Optional */
354 /* 355 /*
355 * If platform uses PHYs. There is a 1:1 relation between the port number and 356 * If platform uses PHYs. There is a 1:1 relation between the port number and
diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c
index a58bcc069c54..6822e2f33f7e 100644
--- a/drivers/ata/ahci_imx.c
+++ b/drivers/ata/ahci_imx.c
@@ -23,6 +23,7 @@
23#include <linux/regmap.h> 23#include <linux/regmap.h>
24#include <linux/ahci_platform.h> 24#include <linux/ahci_platform.h>
25#include <linux/of_device.h> 25#include <linux/of_device.h>
26#include <linux/of_gpio.h>
26#include <linux/mfd/syscon.h> 27#include <linux/mfd/syscon.h>
27#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 28#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
28#include <linux/libata.h> 29#include <linux/libata.h>
@@ -53,11 +54,49 @@ enum {
53 /* Clock Reset Register */ 54 /* Clock Reset Register */
54 IMX_CLOCK_RESET = 0x7f3f, 55 IMX_CLOCK_RESET = 0x7f3f,
55 IMX_CLOCK_RESET_RESET = 1 << 0, 56 IMX_CLOCK_RESET_RESET = 1 << 0,
57 /* IMX8QM HSIO AHCI definitions */
58 IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET = 0x03,
59 IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET = 0x09,
60 IMX8QM_SATA_PHY_IMPED_RATIO_85OHM = 0x6c,
61 IMX8QM_LPCG_PHYX2_OFFSET = 0x00000,
62 IMX8QM_CSR_PHYX2_OFFSET = 0x90000,
63 IMX8QM_CSR_PHYX1_OFFSET = 0xa0000,
64 IMX8QM_CSR_PHYX_STTS0_OFFSET = 0x4,
65 IMX8QM_CSR_PCIEA_OFFSET = 0xb0000,
66 IMX8QM_CSR_PCIEB_OFFSET = 0xc0000,
67 IMX8QM_CSR_SATA_OFFSET = 0xd0000,
68 IMX8QM_CSR_PCIE_CTRL2_OFFSET = 0x8,
69 IMX8QM_CSR_MISC_OFFSET = 0xe0000,
70
71 IMX8QM_LPCG_PHYX2_PCLK0_MASK = (0x3 << 16),
72 IMX8QM_LPCG_PHYX2_PCLK1_MASK = (0x3 << 20),
73 IMX8QM_PHY_APB_RSTN_0 = BIT(0),
74 IMX8QM_PHY_MODE_SATA = BIT(19),
75 IMX8QM_PHY_MODE_MASK = (0xf << 17),
76 IMX8QM_PHY_PIPE_RSTN_0 = BIT(24),
77 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0 = BIT(25),
78 IMX8QM_PHY_PIPE_RSTN_1 = BIT(26),
79 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1 = BIT(27),
80 IMX8QM_STTS0_LANE0_TX_PLL_LOCK = BIT(4),
81 IMX8QM_MISC_IOB_RXENA = BIT(0),
82 IMX8QM_MISC_IOB_TXENA = BIT(1),
83 IMX8QM_MISC_PHYX1_EPCS_SEL = BIT(12),
84 IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 = BIT(24),
85 IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 = BIT(25),
86 IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 = BIT(28),
87 IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0 = BIT(29),
88 IMX8QM_SATA_CTRL_RESET_N = BIT(12),
89 IMX8QM_SATA_CTRL_EPCS_PHYRESET_N = BIT(7),
90 IMX8QM_CTRL_BUTTON_RST_N = BIT(21),
91 IMX8QM_CTRL_POWER_UP_RST_N = BIT(23),
92 IMX8QM_CTRL_LTSSM_ENABLE = BIT(4),
56}; 93};
57 94
58enum ahci_imx_type { 95enum ahci_imx_type {
59 AHCI_IMX53, 96 AHCI_IMX53,
60 AHCI_IMX6Q, 97 AHCI_IMX6Q,
98 AHCI_IMX6QP,
99 AHCI_IMX8QM,
61}; 100};
62 101
63struct imx_ahci_priv { 102struct imx_ahci_priv {
@@ -66,10 +105,18 @@ struct imx_ahci_priv {
66 struct clk *sata_clk; 105 struct clk *sata_clk;
67 struct clk *sata_ref_clk; 106 struct clk *sata_ref_clk;
68 struct clk *ahb_clk; 107 struct clk *ahb_clk;
108 struct clk *epcs_tx_clk;
109 struct clk *epcs_rx_clk;
110 struct clk *phy_apbclk;
111 struct clk *phy_pclk0;
112 struct clk *phy_pclk1;
113 void __iomem *phy_base;
114 int clkreq_gpio;
69 struct regmap *gpr; 115 struct regmap *gpr;
70 bool no_device; 116 bool no_device;
71 bool first_time; 117 bool first_time;
72 u32 phy_params; 118 u32 phy_params;
119 u32 imped_ratio;
73}; 120};
74 121
75static int ahci_imx_hotplug; 122static int ahci_imx_hotplug;
@@ -188,11 +235,26 @@ static int imx_phy_reg_read(u16 *val, void __iomem *mmio)
188 235
189static int imx_sata_phy_reset(struct ahci_host_priv *hpriv) 236static int imx_sata_phy_reset(struct ahci_host_priv *hpriv)
190{ 237{
238 struct imx_ahci_priv *imxpriv = hpriv->plat_data;
191 void __iomem *mmio = hpriv->mmio; 239 void __iomem *mmio = hpriv->mmio;
192 int timeout = 10; 240 int timeout = 10;
193 u16 val; 241 u16 val;
194 int ret; 242 int ret;
195 243
244 if (imxpriv->type == AHCI_IMX6QP) {
245 /* 6qp adds the sata reset mechanism, use it for 6qp sata */
246 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
247 IMX6Q_GPR5_SATA_SW_PD, 0);
248
249 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
250 IMX6Q_GPR5_SATA_SW_RST, 0);
251 udelay(50);
252 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
253 IMX6Q_GPR5_SATA_SW_RST,
254 IMX6Q_GPR5_SATA_SW_RST);
255 return 0;
256 }
257
196 /* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */ 258 /* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */
197 ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio); 259 ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio);
198 if (ret) 260 if (ret)
@@ -391,6 +453,207 @@ static struct attribute *fsl_sata_ahci_attrs[] = {
391}; 453};
392ATTRIBUTE_GROUPS(fsl_sata_ahci); 454ATTRIBUTE_GROUPS(fsl_sata_ahci);
393 455
456static int imx8_sata_enable(struct ahci_host_priv *hpriv)
457{
458 u32 val, reg;
459 int i, ret;
460 struct imx_ahci_priv *imxpriv = hpriv->plat_data;
461 struct device *dev = &imxpriv->ahci_pdev->dev;
462
463 /* configure the hsio for sata */
464 ret = clk_prepare_enable(imxpriv->phy_pclk0);
465 if (ret < 0) {
466 dev_err(dev, "can't enable phy_pclk0.\n");
467 return ret;
468 }
469 ret = clk_prepare_enable(imxpriv->phy_pclk1);
470 if (ret < 0) {
471 dev_err(dev, "can't enable phy_pclk1.\n");
472 goto disable_phy_pclk0;
473 }
474 ret = clk_prepare_enable(imxpriv->epcs_tx_clk);
475 if (ret < 0) {
476 dev_err(dev, "can't enable epcs_tx_clk.\n");
477 goto disable_phy_pclk1;
478 }
479 ret = clk_prepare_enable(imxpriv->epcs_rx_clk);
480 if (ret < 0) {
481 dev_err(dev, "can't enable epcs_rx_clk.\n");
482 goto disable_epcs_tx_clk;
483 }
484 ret = clk_prepare_enable(imxpriv->phy_apbclk);
485 if (ret < 0) {
486 dev_err(dev, "can't enable phy_apbclk.\n");
487 goto disable_epcs_rx_clk;
488 }
489 /* Configure PHYx2 PIPE_RSTN */
490 regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEA_OFFSET +
491 IMX8QM_CSR_PCIE_CTRL2_OFFSET, &val);
492 if ((val & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
493 /* The link of the PCIEA of HSIO is down */
494 regmap_update_bits(imxpriv->gpr,
495 IMX8QM_CSR_PHYX2_OFFSET,
496 IMX8QM_PHY_PIPE_RSTN_0 |
497 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0,
498 IMX8QM_PHY_PIPE_RSTN_0 |
499 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0);
500 }
501 regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEB_OFFSET +
502 IMX8QM_CSR_PCIE_CTRL2_OFFSET, &reg);
503 if ((reg & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
504 /* The link of the PCIEB of HSIO is down */
505 regmap_update_bits(imxpriv->gpr,
506 IMX8QM_CSR_PHYX2_OFFSET,
507 IMX8QM_PHY_PIPE_RSTN_1 |
508 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1,
509 IMX8QM_PHY_PIPE_RSTN_1 |
510 IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1);
511 }
512 if (((reg | val) & IMX8QM_CTRL_LTSSM_ENABLE) == 0) {
513 /* The links of both PCIA and PCIEB of HSIO are down */
514 regmap_update_bits(imxpriv->gpr,
515 IMX8QM_LPCG_PHYX2_OFFSET,
516 IMX8QM_LPCG_PHYX2_PCLK0_MASK |
517 IMX8QM_LPCG_PHYX2_PCLK1_MASK,
518 0);
519 }
520
521 /* set PWR_RST and BT_RST of csr_pciea */
522 val = IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET;
523 regmap_update_bits(imxpriv->gpr,
524 val,
525 IMX8QM_CTRL_BUTTON_RST_N,
526 IMX8QM_CTRL_BUTTON_RST_N);
527 regmap_update_bits(imxpriv->gpr,
528 val,
529 IMX8QM_CTRL_POWER_UP_RST_N,
530 IMX8QM_CTRL_POWER_UP_RST_N);
531
532 /* PHYX1_MODE to SATA */
533 regmap_update_bits(imxpriv->gpr,
534 IMX8QM_CSR_PHYX1_OFFSET,
535 IMX8QM_PHY_MODE_MASK,
536 IMX8QM_PHY_MODE_SATA);
537
538 /*
539 * BIT0 RXENA 1, BIT1 TXENA 0
540 * BIT12 PHY_X1_EPCS_SEL 1.
541 */
542 regmap_update_bits(imxpriv->gpr,
543 IMX8QM_CSR_MISC_OFFSET,
544 IMX8QM_MISC_IOB_RXENA,
545 IMX8QM_MISC_IOB_RXENA);
546 regmap_update_bits(imxpriv->gpr,
547 IMX8QM_CSR_MISC_OFFSET,
548 IMX8QM_MISC_IOB_TXENA,
549 0);
550 regmap_update_bits(imxpriv->gpr,
551 IMX8QM_CSR_MISC_OFFSET,
552 IMX8QM_MISC_PHYX1_EPCS_SEL,
553 IMX8QM_MISC_PHYX1_EPCS_SEL);
554 /*
555 * It is possible, for PCIe and SATA are sharing
556 * the same clock source, HPLL or external oscillator.
557 * When PCIe is in low power modes (L1.X or L2 etc),
558 * the clock source can be turned off. In this case,
559 * if this clock source is required to be toggling by
560 * SATA, then SATA functions will be abnormal.
561 * Set the override here to avoid it.
562 */
563 regmap_update_bits(imxpriv->gpr,
564 IMX8QM_CSR_MISC_OFFSET,
565 IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 |
566 IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 |
567 IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
568 IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0,
569 IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 |
570 IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 |
571 IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 |
572 IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0);
573
574 /* clear PHY RST, then set it */
575 regmap_update_bits(imxpriv->gpr,
576 IMX8QM_CSR_SATA_OFFSET,
577 IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
578 0);
579
580 regmap_update_bits(imxpriv->gpr,
581 IMX8QM_CSR_SATA_OFFSET,
582 IMX8QM_SATA_CTRL_EPCS_PHYRESET_N,
583 IMX8QM_SATA_CTRL_EPCS_PHYRESET_N);
584
585 /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */
586 regmap_update_bits(imxpriv->gpr,
587 IMX8QM_CSR_SATA_OFFSET,
588 IMX8QM_SATA_CTRL_RESET_N,
589 IMX8QM_SATA_CTRL_RESET_N);
590 udelay(1);
591 regmap_update_bits(imxpriv->gpr,
592 IMX8QM_CSR_SATA_OFFSET,
593 IMX8QM_SATA_CTRL_RESET_N,
594 0);
595 regmap_update_bits(imxpriv->gpr,
596 IMX8QM_CSR_SATA_OFFSET,
597 IMX8QM_SATA_CTRL_RESET_N,
598 IMX8QM_SATA_CTRL_RESET_N);
599
600 /* APB reset */
601 regmap_update_bits(imxpriv->gpr,
602 IMX8QM_CSR_PHYX1_OFFSET,
603 IMX8QM_PHY_APB_RSTN_0,
604 IMX8QM_PHY_APB_RSTN_0);
605
606 for (i = 0; i < 100; i++) {
607 reg = IMX8QM_CSR_PHYX1_OFFSET +
608 IMX8QM_CSR_PHYX_STTS0_OFFSET;
609 regmap_read(imxpriv->gpr, reg, &val);
610 val &= IMX8QM_STTS0_LANE0_TX_PLL_LOCK;
611 if (val == IMX8QM_STTS0_LANE0_TX_PLL_LOCK)
612 break;
613 udelay(1);
614 }
615
616 if (val != IMX8QM_STTS0_LANE0_TX_PLL_LOCK) {
617 dev_err(dev, "TX PLL of the PHY is not locked\n");
618 ret = -ENODEV;
619 } else {
620 writeb(imxpriv->imped_ratio, imxpriv->phy_base +
621 IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET);
622 writeb(imxpriv->imped_ratio, imxpriv->phy_base +
623 IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET);
624 reg = readb(imxpriv->phy_base +
625 IMX8QM_SATA_PHY_RX_IMPED_RATIO_OFFSET);
626 if (unlikely(reg != imxpriv->imped_ratio))
627 dev_info(dev, "Can't set PHY RX impedance ratio.\n");
628 reg = readb(imxpriv->phy_base +
629 IMX8QM_SATA_PHY_TX_IMPED_RATIO_OFFSET);
630 if (unlikely(reg != imxpriv->imped_ratio))
631 dev_info(dev, "Can't set PHY TX impedance ratio.\n");
632 usleep_range(50, 100);
633
634 /*
635 * To reduce the power consumption, gate off
636 * the PHY clks
637 */
638 clk_disable_unprepare(imxpriv->phy_apbclk);
639 clk_disable_unprepare(imxpriv->phy_pclk1);
640 clk_disable_unprepare(imxpriv->phy_pclk0);
641 return ret;
642 }
643
644 clk_disable_unprepare(imxpriv->phy_apbclk);
645disable_epcs_rx_clk:
646 clk_disable_unprepare(imxpriv->epcs_rx_clk);
647disable_epcs_tx_clk:
648 clk_disable_unprepare(imxpriv->epcs_tx_clk);
649disable_phy_pclk1:
650 clk_disable_unprepare(imxpriv->phy_pclk1);
651disable_phy_pclk0:
652 clk_disable_unprepare(imxpriv->phy_pclk0);
653
654 return ret;
655}
656
394static int imx_sata_enable(struct ahci_host_priv *hpriv) 657static int imx_sata_enable(struct ahci_host_priv *hpriv)
395{ 658{
396 struct imx_ahci_priv *imxpriv = hpriv->plat_data; 659 struct imx_ahci_priv *imxpriv = hpriv->plat_data;
@@ -408,7 +671,7 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv)
408 if (ret < 0) 671 if (ret < 0)
409 goto disable_regulator; 672 goto disable_regulator;
410 673
411 if (imxpriv->type == AHCI_IMX6Q) { 674 if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
412 /* 675 /*
413 * set PHY Paremeters, two steps to configure the GPR13, 676 * set PHY Paremeters, two steps to configure the GPR13,
414 * one write for rest of parameters, mask of first write 677 * one write for rest of parameters, mask of first write
@@ -438,6 +701,8 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv)
438 dev_err(dev, "failed to reset phy: %d\n", ret); 701 dev_err(dev, "failed to reset phy: %d\n", ret);
439 goto disable_clk; 702 goto disable_clk;
440 } 703 }
704 } else if (imxpriv->type == AHCI_IMX8QM) {
705 ret = imx8_sata_enable(hpriv);
441 } 706 }
442 707
443 usleep_range(1000, 2000); 708 usleep_range(1000, 2000);
@@ -459,10 +724,29 @@ static void imx_sata_disable(struct ahci_host_priv *hpriv)
459 if (imxpriv->no_device) 724 if (imxpriv->no_device)
460 return; 725 return;
461 726
462 if (imxpriv->type == AHCI_IMX6Q) { 727 switch (imxpriv->type) {
728 case AHCI_IMX6QP:
729 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR5,
730 IMX6Q_GPR5_SATA_SW_PD,
731 IMX6Q_GPR5_SATA_SW_PD);
463 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13, 732 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
464 IMX6Q_GPR13_SATA_MPLL_CLK_EN, 733 IMX6Q_GPR13_SATA_MPLL_CLK_EN,
465 !IMX6Q_GPR13_SATA_MPLL_CLK_EN); 734 !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
735 break;
736
737 case AHCI_IMX6Q:
738 regmap_update_bits(imxpriv->gpr, IOMUXC_GPR13,
739 IMX6Q_GPR13_SATA_MPLL_CLK_EN,
740 !IMX6Q_GPR13_SATA_MPLL_CLK_EN);
741 break;
742
743 case AHCI_IMX8QM:
744 clk_disable_unprepare(imxpriv->epcs_rx_clk);
745 clk_disable_unprepare(imxpriv->epcs_tx_clk);
746 break;
747
748 default:
749 break;
466 } 750 }
467 751
468 clk_disable_unprepare(imxpriv->sata_ref_clk); 752 clk_disable_unprepare(imxpriv->sata_ref_clk);
@@ -513,7 +797,7 @@ static int ahci_imx_softreset(struct ata_link *link, unsigned int *class,
513 797
514 if (imxpriv->type == AHCI_IMX53) 798 if (imxpriv->type == AHCI_IMX53)
515 ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline); 799 ret = ahci_pmp_retry_srst_ops.softreset(link, class, deadline);
516 else if (imxpriv->type == AHCI_IMX6Q) 800 else
517 ret = ahci_ops.softreset(link, class, deadline); 801 ret = ahci_ops.softreset(link, class, deadline);
518 802
519 return ret; 803 return ret;
@@ -536,6 +820,8 @@ static const struct ata_port_info ahci_imx_port_info = {
536static const struct of_device_id imx_ahci_of_match[] = { 820static const struct of_device_id imx_ahci_of_match[] = {
537 { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 }, 821 { .compatible = "fsl,imx53-ahci", .data = (void *)AHCI_IMX53 },
538 { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q }, 822 { .compatible = "fsl,imx6q-ahci", .data = (void *)AHCI_IMX6Q },
823 { .compatible = "fsl,imx6qp-ahci", .data = (void *)AHCI_IMX6QP },
824 { .compatible = "fsl,imx8qm-ahci", .data = (void *)AHCI_IMX8QM },
539 {}, 825 {},
540}; 826};
541MODULE_DEVICE_TABLE(of, imx_ahci_of_match); 827MODULE_DEVICE_TABLE(of, imx_ahci_of_match);
@@ -703,6 +989,79 @@ static struct scsi_host_template ahci_platform_sht = {
703 AHCI_SHT(DRV_NAME), 989 AHCI_SHT(DRV_NAME),
704}; 990};
705 991
992static int imx8_sata_probe(struct device *dev, struct imx_ahci_priv *imxpriv)
993{
994 int ret;
995 struct resource *phy_res;
996 struct platform_device *pdev = imxpriv->ahci_pdev;
997 struct device_node *np = dev->of_node;
998
999 if (of_property_read_u32(np, "fsl,phy-imp", &imxpriv->imped_ratio))
1000 imxpriv->imped_ratio = IMX8QM_SATA_PHY_IMPED_RATIO_85OHM;
1001 phy_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
1002 if (phy_res) {
1003 imxpriv->phy_base = devm_ioremap(dev, phy_res->start,
1004 resource_size(phy_res));
1005 if (!imxpriv->phy_base) {
1006 dev_err(dev, "error with ioremap\n");
1007 return -ENOMEM;
1008 }
1009 } else {
1010 dev_err(dev, "missing *phy* reg region.\n");
1011 return -ENOMEM;
1012 }
1013 imxpriv->gpr =
1014 syscon_regmap_lookup_by_phandle(np, "hsio");
1015 if (IS_ERR(imxpriv->gpr)) {
1016 dev_err(dev, "unable to find gpr registers\n");
1017 return PTR_ERR(imxpriv->gpr);
1018 }
1019
1020 imxpriv->epcs_tx_clk = devm_clk_get(dev, "epcs_tx");
1021 if (IS_ERR(imxpriv->epcs_tx_clk)) {
1022 dev_err(dev, "can't get epcs_tx_clk clock.\n");
1023 return PTR_ERR(imxpriv->epcs_tx_clk);
1024 }
1025 imxpriv->epcs_rx_clk = devm_clk_get(dev, "epcs_rx");
1026 if (IS_ERR(imxpriv->epcs_rx_clk)) {
1027 dev_err(dev, "can't get epcs_rx_clk clock.\n");
1028 return PTR_ERR(imxpriv->epcs_rx_clk);
1029 }
1030 imxpriv->phy_pclk0 = devm_clk_get(dev, "phy_pclk0");
1031 if (IS_ERR(imxpriv->phy_pclk0)) {
1032 dev_err(dev, "can't get phy_pclk0 clock.\n");
1033 return PTR_ERR(imxpriv->phy_pclk0);
1034 }
1035 imxpriv->phy_pclk1 = devm_clk_get(dev, "phy_pclk1");
1036 if (IS_ERR(imxpriv->phy_pclk1)) {
1037 dev_err(dev, "can't get phy_pclk1 clock.\n");
1038 return PTR_ERR(imxpriv->phy_pclk1);
1039 }
1040 imxpriv->phy_apbclk = devm_clk_get(dev, "phy_apbclk");
1041 if (IS_ERR(imxpriv->phy_apbclk)) {
1042 dev_err(dev, "can't get phy_apbclk clock.\n");
1043 return PTR_ERR(imxpriv->phy_apbclk);
1044 }
1045
1046 /* Fetch GPIO, then enable the external OSC */
1047 imxpriv->clkreq_gpio = of_get_named_gpio(np, "clkreq-gpio", 0);
1048 if (gpio_is_valid(imxpriv->clkreq_gpio)) {
1049 ret = devm_gpio_request_one(dev, imxpriv->clkreq_gpio,
1050 GPIOF_OUT_INIT_LOW,
1051 "SATA CLKREQ");
1052 if (ret == -EBUSY) {
1053 dev_info(dev, "clkreq had been initialized.\n");
1054 } else if (ret) {
1055 dev_err(dev, "%d unable to get clkreq.\n", ret);
1056 return ret;
1057 }
1058 } else if (imxpriv->clkreq_gpio == -EPROBE_DEFER) {
1059 return imxpriv->clkreq_gpio;
1060 }
1061
1062 return 0;
1063}
1064
706static int imx_ahci_probe(struct platform_device *pdev) 1065static int imx_ahci_probe(struct platform_device *pdev)
707{ 1066{
708 struct device *dev = &pdev->dev; 1067 struct device *dev = &pdev->dev;
@@ -743,7 +1102,7 @@ static int imx_ahci_probe(struct platform_device *pdev)
743 return PTR_ERR(imxpriv->ahb_clk); 1102 return PTR_ERR(imxpriv->ahb_clk);
744 } 1103 }
745 1104
746 if (imxpriv->type == AHCI_IMX6Q) { 1105 if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
747 u32 reg_value; 1106 u32 reg_value;
748 1107
749 imxpriv->gpr = syscon_regmap_lookup_by_compatible( 1108 imxpriv->gpr = syscon_regmap_lookup_by_compatible(
@@ -762,6 +1121,10 @@ static int imx_ahci_probe(struct platform_device *pdev)
762 IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F | 1121 IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F |
763 IMX6Q_GPR13_SATA_SPD_MODE_3P0G | 1122 IMX6Q_GPR13_SATA_SPD_MODE_3P0G |
764 reg_value; 1123 reg_value;
1124 } else if (imxpriv->type == AHCI_IMX8QM) {
1125 ret = imx8_sata_probe(dev, imxpriv);
1126 if (ret)
1127 return ret;
765 } 1128 }
766 1129
767 hpriv = ahci_platform_get_resources(pdev); 1130 hpriv = ahci_platform_get_resources(pdev);
diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c
index 3a62eb246d80..64d848409fe2 100644
--- a/drivers/ata/ahci_tegra.c
+++ b/drivers/ata/ahci_tegra.c
@@ -34,7 +34,8 @@
34#define DRV_NAME "tegra-ahci" 34#define DRV_NAME "tegra-ahci"
35 35
36#define SATA_CONFIGURATION_0 0x180 36#define SATA_CONFIGURATION_0 0x180
37#define SATA_CONFIGURATION_EN_FPCI BIT(0) 37#define SATA_CONFIGURATION_0_EN_FPCI BIT(0)
38#define SATA_CONFIGURATION_0_CLK_OVERRIDE BIT(31)
38 39
39#define SCFG_OFFSET 0x1000 40#define SCFG_OFFSET 0x1000
40 41
@@ -45,17 +46,55 @@
45#define T_SATA0_CFG_1_SERR BIT(8) 46#define T_SATA0_CFG_1_SERR BIT(8)
46 47
47#define T_SATA0_CFG_9 0x24 48#define T_SATA0_CFG_9 0x24
48#define T_SATA0_CFG_9_BASE_ADDRESS_SHIFT 13 49#define T_SATA0_CFG_9_BASE_ADDRESS 0x40020000
49 50
50#define SATA_FPCI_BAR5 0x94 51#define SATA_FPCI_BAR5 0x94
51#define SATA_FPCI_BAR5_START_SHIFT 4 52#define SATA_FPCI_BAR5_START_MASK (0xfffffff << 4)
53#define SATA_FPCI_BAR5_START (0x0040020 << 4)
54#define SATA_FPCI_BAR5_ACCESS_TYPE (0x1)
52 55
53#define SATA_INTR_MASK 0x188 56#define SATA_INTR_MASK 0x188
54#define SATA_INTR_MASK_IP_INT_MASK BIT(16) 57#define SATA_INTR_MASK_IP_INT_MASK BIT(16)
55 58
59#define T_SATA0_CFG_35 0x94
60#define T_SATA0_CFG_35_IDP_INDEX_MASK (0x7ff << 2)
61#define T_SATA0_CFG_35_IDP_INDEX (0x2a << 2)
62
63#define T_SATA0_AHCI_IDP1 0x98
64#define T_SATA0_AHCI_IDP1_DATA (0x400040)
65
66#define T_SATA0_CFG_PHY_1 0x12c
67#define T_SATA0_CFG_PHY_1_PADS_IDDQ_EN BIT(23)
68#define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN BIT(22)
69
70#define T_SATA0_NVOOB 0x114
71#define T_SATA0_NVOOB_COMMA_CNT_MASK (0xff << 16)
72#define T_SATA0_NVOOB_COMMA_CNT (0x07 << 16)
73#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (0x3 << 24)
74#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE (0x1 << 24)
75#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (0x3 << 26)
76#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH (0x3 << 26)
77
78#define T_SATA_CFG_PHY_0 0x120
79#define T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD BIT(11)
80#define T_SATA_CFG_PHY_0_MASK_SQUELCH BIT(24)
81
82#define T_SATA0_CFG2NVOOB_2 0x134
83#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK (0x1ff << 18)
84#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW (0xc << 18)
85
56#define T_SATA0_AHCI_HBA_CAP_BKDR 0x300 86#define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
87#define T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP BIT(13)
88#define T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP BIT(14)
89#define T_SATA0_AHCI_HBA_CAP_BKDR_SALP BIT(26)
90#define T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM BIT(17)
91#define T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ BIT(30)
57 92
58#define T_SATA0_BKDOOR_CC 0x4a4 93#define T_SATA0_BKDOOR_CC 0x4a4
94#define T_SATA0_BKDOOR_CC_CLASS_CODE_MASK (0xffff << 16)
95#define T_SATA0_BKDOOR_CC_CLASS_CODE (0x0106 << 16)
96#define T_SATA0_BKDOOR_CC_PROG_IF_MASK (0xff << 8)
97#define T_SATA0_BKDOOR_CC_PROG_IF (0x01 << 8)
59 98
60#define T_SATA0_CFG_SATA 0x54c 99#define T_SATA0_CFG_SATA 0x54c
61#define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12) 100#define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN BIT(12)
@@ -82,6 +121,27 @@
82#define T_SATA0_CHX_PHY_CTRL11 0x6d0 121#define T_SATA0_CHX_PHY_CTRL11 0x6d0
83#define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16) 122#define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16)
84 123
124#define T_SATA0_CHX_PHY_CTRL17_0 0x6e8
125#define T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1 0x55010000
126#define T_SATA0_CHX_PHY_CTRL18_0 0x6ec
127#define T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2 0x55010000
128#define T_SATA0_CHX_PHY_CTRL20_0 0x6f4
129#define T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1 0x1
130#define T_SATA0_CHX_PHY_CTRL21_0 0x6f8
131#define T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2 0x1
132
133/* AUX Registers */
134#define SATA_AUX_MISC_CNTL_1_0 0x8
135#define SATA_AUX_MISC_CNTL_1_0_DEVSLP_OVERRIDE BIT(17)
136#define SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT BIT(13)
137#define SATA_AUX_MISC_CNTL_1_0_DESO_SUPPORT BIT(15)
138
139#define SATA_AUX_RX_STAT_INT_0 0xc
140#define SATA_AUX_RX_STAT_INT_0_SATA_DEVSLP BIT(7)
141
142#define SATA_AUX_SPARE_CFG0_0 0x18
143#define SATA_AUX_SPARE_CFG0_0_MDAT_TIMER_AFTER_PG_VALID BIT(14)
144
85#define FUSE_SATA_CALIB 0x124 145#define FUSE_SATA_CALIB 0x124
86#define FUSE_SATA_CALIB_MASK 0x3 146#define FUSE_SATA_CALIB_MASK 0x3
87 147
@@ -99,23 +159,92 @@ static const struct sata_pad_calibration tegra124_pad_calibration[] = {
99 {0x14, 0x0e, 0x1a, 0x0e}, 159 {0x14, 0x0e, 0x1a, 0x0e},
100}; 160};
101 161
162struct tegra_ahci_ops {
163 int (*init)(struct ahci_host_priv *hpriv);
164};
165
166struct tegra_ahci_soc {
167 const char *const *supply_names;
168 u32 num_supplies;
169 bool supports_devslp;
170 const struct tegra_ahci_ops *ops;
171};
172
102struct tegra_ahci_priv { 173struct tegra_ahci_priv {
103 struct platform_device *pdev; 174 struct platform_device *pdev;
104 void __iomem *sata_regs; 175 void __iomem *sata_regs;
176 void __iomem *sata_aux_regs;
105 struct reset_control *sata_rst; 177 struct reset_control *sata_rst;
106 struct reset_control *sata_oob_rst; 178 struct reset_control *sata_oob_rst;
107 struct reset_control *sata_cold_rst; 179 struct reset_control *sata_cold_rst;
108 /* Needs special handling, cannot use ahci_platform */ 180 /* Needs special handling, cannot use ahci_platform */
109 struct clk *sata_clk; 181 struct clk *sata_clk;
110 struct regulator_bulk_data supplies[5]; 182 struct regulator_bulk_data *supplies;
183 const struct tegra_ahci_soc *soc;
111}; 184};
112 185
186static void tegra_ahci_handle_quirks(struct ahci_host_priv *hpriv)
187{
188 struct tegra_ahci_priv *tegra = hpriv->plat_data;
189 u32 val;
190
191 if (tegra->sata_aux_regs && !tegra->soc->supports_devslp) {
192 val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
193 val &= ~SATA_AUX_MISC_CNTL_1_0_SDS_SUPPORT;
194 writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0);
195 }
196}
197
198static int tegra124_ahci_init(struct ahci_host_priv *hpriv)
199{
200 struct tegra_ahci_priv *tegra = hpriv->plat_data;
201 struct sata_pad_calibration calib;
202 int ret;
203 u32 val;
204
205 /* Pad calibration */
206 ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val);
207 if (ret)
208 return ret;
209
210 calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK];
211
212 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
213
214 val = readl(tegra->sata_regs +
215 SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
216 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
217 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
218 val |= calib.gen1_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
219 val |= calib.gen1_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
220 writel(val, tegra->sata_regs + SCFG_OFFSET +
221 T_SATA0_CHX_PHY_CTRL1_GEN1);
222
223 val = readl(tegra->sata_regs +
224 SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
225 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
226 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
227 val |= calib.gen2_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
228 val |= calib.gen2_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
229 writel(val, tegra->sata_regs + SCFG_OFFSET +
230 T_SATA0_CHX_PHY_CTRL1_GEN2);
231
232 writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ,
233 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);
234 writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1,
235 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);
236
237 writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);
238
239 return 0;
240}
241
113static int tegra_ahci_power_on(struct ahci_host_priv *hpriv) 242static int tegra_ahci_power_on(struct ahci_host_priv *hpriv)
114{ 243{
115 struct tegra_ahci_priv *tegra = hpriv->plat_data; 244 struct tegra_ahci_priv *tegra = hpriv->plat_data;
116 int ret; 245 int ret;
117 246
118 ret = regulator_bulk_enable(ARRAY_SIZE(tegra->supplies), 247 ret = regulator_bulk_enable(tegra->soc->num_supplies,
119 tegra->supplies); 248 tegra->supplies);
120 if (ret) 249 if (ret)
121 return ret; 250 return ret;
@@ -144,7 +273,7 @@ disable_power:
144 tegra_powergate_power_off(TEGRA_POWERGATE_SATA); 273 tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
145 274
146disable_regulators: 275disable_regulators:
147 regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies); 276 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
148 277
149 return ret; 278 return ret;
150} 279}
@@ -162,15 +291,14 @@ static void tegra_ahci_power_off(struct ahci_host_priv *hpriv)
162 clk_disable_unprepare(tegra->sata_clk); 291 clk_disable_unprepare(tegra->sata_clk);
163 tegra_powergate_power_off(TEGRA_POWERGATE_SATA); 292 tegra_powergate_power_off(TEGRA_POWERGATE_SATA);
164 293
165 regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies); 294 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
166} 295}
167 296
168static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv) 297static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
169{ 298{
170 struct tegra_ahci_priv *tegra = hpriv->plat_data; 299 struct tegra_ahci_priv *tegra = hpriv->plat_data;
171 int ret; 300 int ret;
172 unsigned int val; 301 u32 val;
173 struct sata_pad_calibration calib;
174 302
175 ret = tegra_ahci_power_on(hpriv); 303 ret = tegra_ahci_power_on(hpriv);
176 if (ret) { 304 if (ret) {
@@ -179,78 +307,115 @@ static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv)
179 return ret; 307 return ret;
180 } 308 }
181 309
310 /*
311 * Program the following SATA IPFS registers to allow SW accesses to
312 * SATA's MMIO register range.
313 */
314 val = readl(tegra->sata_regs + SATA_FPCI_BAR5);
315 val &= ~(SATA_FPCI_BAR5_START_MASK | SATA_FPCI_BAR5_ACCESS_TYPE);
316 val |= SATA_FPCI_BAR5_START | SATA_FPCI_BAR5_ACCESS_TYPE;
317 writel(val, tegra->sata_regs + SATA_FPCI_BAR5);
318
319 /* Program the following SATA IPFS register to enable the SATA */
182 val = readl(tegra->sata_regs + SATA_CONFIGURATION_0); 320 val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
183 val |= SATA_CONFIGURATION_EN_FPCI; 321 val |= SATA_CONFIGURATION_0_EN_FPCI;
184 writel(val, tegra->sata_regs + SATA_CONFIGURATION_0); 322 writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
185 323
186 /* Pad calibration */ 324 /* Electrical settings for better link stability */
187 325 val = T_SATA0_CHX_PHY_CTRL17_0_RX_EQ_CTRL_L_GEN1;
188 ret = tegra_fuse_readl(FUSE_SATA_CALIB, &val); 326 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL17_0);
189 if (ret) { 327 val = T_SATA0_CHX_PHY_CTRL18_0_RX_EQ_CTRL_L_GEN2;
190 dev_err(&tegra->pdev->dev, 328 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL18_0);
191 "failed to read calibration fuse: %d\n", ret); 329 val = T_SATA0_CHX_PHY_CTRL20_0_RX_EQ_CTRL_H_GEN1;
192 return ret; 330 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL20_0);
193 } 331 val = T_SATA0_CHX_PHY_CTRL21_0_RX_EQ_CTRL_H_GEN2;
194 332 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL21_0);
195 calib = tegra124_pad_calibration[val & FUSE_SATA_CALIB_MASK]; 333
196 334 /* For SQUELCH Filter & Gen3 drive getting detected as Gen1 drive */
197 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); 335
198 336 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
199 val = readl(tegra->sata_regs + 337 val |= T_SATA_CFG_PHY_0_MASK_SQUELCH;
200 SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1); 338 val &= ~T_SATA_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD;
201 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK; 339 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0);
202 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK; 340
203 val |= calib.gen1_tx_amp << 341 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
204 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT; 342 val &= ~(T_SATA0_NVOOB_COMMA_CNT_MASK |
205 val |= calib.gen1_tx_peak << 343 T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK |
206 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT; 344 T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK);
207 writel(val, tegra->sata_regs + SCFG_OFFSET + 345 val |= (T_SATA0_NVOOB_COMMA_CNT |
208 T_SATA0_CHX_PHY_CTRL1_GEN1); 346 T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH |
209 347 T_SATA0_NVOOB_SQUELCH_FILTER_MODE);
210 val = readl(tegra->sata_regs + 348 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB);
211 SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2); 349
212 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK; 350 /*
213 val &= ~T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK; 351 * Change CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW from 83.3 ns to 58.8ns
214 val |= calib.gen2_tx_amp << 352 */
215 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT; 353 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
216 val |= calib.gen2_tx_peak << 354 val &= ~T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK;
217 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT; 355 val |= T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW;
218 writel(val, tegra->sata_regs + SCFG_OFFSET + 356 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
219 T_SATA0_CHX_PHY_CTRL1_GEN2); 357
220 358 if (tegra->soc->ops && tegra->soc->ops->init)
221 writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ, 359 tegra->soc->ops->init(hpriv);
222 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11); 360
223 writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1, 361 /*
224 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2); 362 * Program the following SATA configuration registers to
225 363 * initialize SATA
226 writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); 364 */
227 365 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
228 /* Program controller device ID */ 366 val |= (T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE |
367 T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR);
368 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);
369 val = T_SATA0_CFG_9_BASE_ADDRESS;
370 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
229 371
372 /* Program Class Code and Programming interface for SATA */
230 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); 373 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
231 val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN; 374 val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
232 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); 375 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
233 376
234 writel(0x01060100, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC); 377 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
378 val &=
379 ~(T_SATA0_BKDOOR_CC_CLASS_CODE_MASK |
380 T_SATA0_BKDOOR_CC_PROG_IF_MASK);
381 val |= T_SATA0_BKDOOR_CC_CLASS_CODE | T_SATA0_BKDOOR_CC_PROG_IF;
382 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);
235 383
236 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); 384 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
237 val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN; 385 val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
238 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); 386 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);
239 387
240 /* Enable IO & memory access, bus master mode */ 388 /* Enabling LPM capabilities through Backdoor Programming */
241 389 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
242 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1); 390 val |= (T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP |
243 val |= T_SATA0_CFG_1_IO_SPACE | T_SATA0_CFG_1_MEMORY_SPACE | 391 T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP |
244 T_SATA0_CFG_1_BUS_MASTER | T_SATA0_CFG_1_SERR; 392 T_SATA0_AHCI_HBA_CAP_BKDR_SALP |
245 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1); 393 T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM);
246 394 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
247 /* Program SATA MMIO */ 395
248 396 /* SATA Second Level Clock Gating configuration
249 writel(0x10000 << SATA_FPCI_BAR5_START_SHIFT, 397 * Enabling Gating of Tx/Rx clocks and driving Pad IDDQ and Lane
250 tegra->sata_regs + SATA_FPCI_BAR5); 398 * IDDQ Signals
399 */
400 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
401 val &= ~T_SATA0_CFG_35_IDP_INDEX_MASK;
402 val |= T_SATA0_CFG_35_IDP_INDEX;
403 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_35);
404
405 val = T_SATA0_AHCI_IDP1_DATA;
406 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_AHCI_IDP1);
407
408 val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
409 val |= (T_SATA0_CFG_PHY_1_PADS_IDDQ_EN |
410 T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN);
411 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_PHY_1);
412
413 /* Enabling IPFS Clock Gating */
414 val = readl(tegra->sata_regs + SATA_CONFIGURATION_0);
415 val &= ~SATA_CONFIGURATION_0_CLK_OVERRIDE;
416 writel(val, tegra->sata_regs + SATA_CONFIGURATION_0);
251 417
252 writel(0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT, 418 tegra_ahci_handle_quirks(hpriv);
253 tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);
254 419
255 /* Unmask SATA interrupts */ 420 /* Unmask SATA interrupts */
256 421
@@ -279,14 +444,40 @@ static struct ata_port_operations ahci_tegra_port_ops = {
279}; 444};
280 445
281static const struct ata_port_info ahci_tegra_port_info = { 446static const struct ata_port_info ahci_tegra_port_info = {
282 .flags = AHCI_FLAG_COMMON, 447 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
283 .pio_mask = ATA_PIO4, 448 .pio_mask = ATA_PIO4,
284 .udma_mask = ATA_UDMA6, 449 .udma_mask = ATA_UDMA6,
285 .port_ops = &ahci_tegra_port_ops, 450 .port_ops = &ahci_tegra_port_ops,
286}; 451};
287 452
453static const char *const tegra124_supply_names[] = {
454 "avdd", "hvdd", "vddio", "target-5v", "target-12v"
455};
456
457static const struct tegra_ahci_ops tegra124_ahci_ops = {
458 .init = tegra124_ahci_init,
459};
460
461static const struct tegra_ahci_soc tegra124_ahci_soc = {
462 .supply_names = tegra124_supply_names,
463 .num_supplies = ARRAY_SIZE(tegra124_supply_names),
464 .supports_devslp = false,
465 .ops = &tegra124_ahci_ops,
466};
467
468static const struct tegra_ahci_soc tegra210_ahci_soc = {
469 .supports_devslp = false,
470};
471
288static const struct of_device_id tegra_ahci_of_match[] = { 472static const struct of_device_id tegra_ahci_of_match[] = {
289 { .compatible = "nvidia,tegra124-ahci" }, 473 {
474 .compatible = "nvidia,tegra124-ahci",
475 .data = &tegra124_ahci_soc
476 },
477 {
478 .compatible = "nvidia,tegra210-ahci",
479 .data = &tegra210_ahci_soc
480 },
290 {} 481 {}
291}; 482};
292MODULE_DEVICE_TABLE(of, tegra_ahci_of_match); 483MODULE_DEVICE_TABLE(of, tegra_ahci_of_match);
@@ -301,6 +492,7 @@ static int tegra_ahci_probe(struct platform_device *pdev)
301 struct tegra_ahci_priv *tegra; 492 struct tegra_ahci_priv *tegra;
302 struct resource *res; 493 struct resource *res;
303 int ret; 494 int ret;
495 unsigned int i;
304 496
305 hpriv = ahci_platform_get_resources(pdev); 497 hpriv = ahci_platform_get_resources(pdev);
306 if (IS_ERR(hpriv)) 498 if (IS_ERR(hpriv))
@@ -313,12 +505,23 @@ static int tegra_ahci_probe(struct platform_device *pdev)
313 hpriv->plat_data = tegra; 505 hpriv->plat_data = tegra;
314 506
315 tegra->pdev = pdev; 507 tegra->pdev = pdev;
508 tegra->soc = of_device_get_match_data(&pdev->dev);
316 509
317 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 510 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
318 tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res); 511 tegra->sata_regs = devm_ioremap_resource(&pdev->dev, res);
319 if (IS_ERR(tegra->sata_regs)) 512 if (IS_ERR(tegra->sata_regs))
320 return PTR_ERR(tegra->sata_regs); 513 return PTR_ERR(tegra->sata_regs);
321 514
515 /*
516 * AUX registers is optional.
517 */
518 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
519 if (res) {
520 tegra->sata_aux_regs = devm_ioremap_resource(&pdev->dev, res);
521 if (IS_ERR(tegra->sata_aux_regs))
522 return PTR_ERR(tegra->sata_aux_regs);
523 }
524
322 tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata"); 525 tegra->sata_rst = devm_reset_control_get(&pdev->dev, "sata");
323 if (IS_ERR(tegra->sata_rst)) { 526 if (IS_ERR(tegra->sata_rst)) {
324 dev_err(&pdev->dev, "Failed to get sata reset\n"); 527 dev_err(&pdev->dev, "Failed to get sata reset\n");
@@ -343,13 +546,17 @@ static int tegra_ahci_probe(struct platform_device *pdev)
343 return PTR_ERR(tegra->sata_clk); 546 return PTR_ERR(tegra->sata_clk);
344 } 547 }
345 548
346 tegra->supplies[0].supply = "avdd"; 549 tegra->supplies = devm_kcalloc(&pdev->dev,
347 tegra->supplies[1].supply = "hvdd"; 550 tegra->soc->num_supplies,
348 tegra->supplies[2].supply = "vddio"; 551 sizeof(*tegra->supplies), GFP_KERNEL);
349 tegra->supplies[3].supply = "target-5v"; 552 if (!tegra->supplies)
350 tegra->supplies[4].supply = "target-12v"; 553 return -ENOMEM;
554
555 for (i = 0; i < tegra->soc->num_supplies; i++)
556 tegra->supplies[i].supply = tegra->soc->supply_names[i];
351 557
352 ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(tegra->supplies), 558 ret = devm_regulator_bulk_get(&pdev->dev,
559 tegra->soc->num_supplies,
353 tegra->supplies); 560 tegra->supplies);
354 if (ret) { 561 if (ret) {
355 dev_err(&pdev->dev, "Failed to get regulators\n"); 562 dev_err(&pdev->dev, "Failed to get regulators\n");
@@ -385,5 +592,5 @@ static struct platform_driver tegra_ahci_driver = {
385module_platform_driver(tegra_ahci_driver); 592module_platform_driver(tegra_ahci_driver);
386 593
387MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>"); 594MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
388MODULE_DESCRIPTION("Tegra124 AHCI SATA driver"); 595MODULE_DESCRIPTION("Tegra AHCI SATA driver");
389MODULE_LICENSE("GPL v2"); 596MODULE_LICENSE("GPL v2");
diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c
index 30cc8f1a31e1..46a762442dc5 100644
--- a/drivers/ata/libahci_platform.c
+++ b/drivers/ata/libahci_platform.c
@@ -25,6 +25,7 @@
25#include <linux/phy/phy.h> 25#include <linux/phy/phy.h>
26#include <linux/pm_runtime.h> 26#include <linux/pm_runtime.h>
27#include <linux/of_platform.h> 27#include <linux/of_platform.h>
28#include <linux/reset.h>
28#include "ahci.h" 29#include "ahci.h"
29 30
30static void ahci_host_stop(struct ata_host *host); 31static void ahci_host_stop(struct ata_host *host);
@@ -195,7 +196,8 @@ EXPORT_SYMBOL_GPL(ahci_platform_disable_regulators);
195 * following order: 196 * following order:
196 * 1) Regulator 197 * 1) Regulator
197 * 2) Clocks (through ahci_platform_enable_clks) 198 * 2) Clocks (through ahci_platform_enable_clks)
198 * 3) Phys 199 * 3) Resets
200 * 4) Phys
199 * 201 *
200 * If resource enabling fails at any point the previous enabled resources 202 * If resource enabling fails at any point the previous enabled resources
201 * are disabled in reverse order. 203 * are disabled in reverse order.
@@ -215,12 +217,19 @@ int ahci_platform_enable_resources(struct ahci_host_priv *hpriv)
215 if (rc) 217 if (rc)
216 goto disable_regulator; 218 goto disable_regulator;
217 219
218 rc = ahci_platform_enable_phys(hpriv); 220 rc = reset_control_deassert(hpriv->rsts);
219 if (rc) 221 if (rc)
220 goto disable_clks; 222 goto disable_clks;
221 223
224 rc = ahci_platform_enable_phys(hpriv);
225 if (rc)
226 goto disable_resets;
227
222 return 0; 228 return 0;
223 229
230disable_resets:
231 reset_control_assert(hpriv->rsts);
232
224disable_clks: 233disable_clks:
225 ahci_platform_disable_clks(hpriv); 234 ahci_platform_disable_clks(hpriv);
226 235
@@ -239,12 +248,15 @@ EXPORT_SYMBOL_GPL(ahci_platform_enable_resources);
239 * following order: 248 * following order:
240 * 1) Phys 249 * 1) Phys
241 * 2) Clocks (through ahci_platform_disable_clks) 250 * 2) Clocks (through ahci_platform_disable_clks)
242 * 3) Regulator 251 * 3) Resets
252 * 4) Regulator
243 */ 253 */
244void ahci_platform_disable_resources(struct ahci_host_priv *hpriv) 254void ahci_platform_disable_resources(struct ahci_host_priv *hpriv)
245{ 255{
246 ahci_platform_disable_phys(hpriv); 256 ahci_platform_disable_phys(hpriv);
247 257
258 reset_control_assert(hpriv->rsts);
259
248 ahci_platform_disable_clks(hpriv); 260 ahci_platform_disable_clks(hpriv);
249 261
250 ahci_platform_disable_regulators(hpriv); 262 ahci_platform_disable_regulators(hpriv);
@@ -393,6 +405,12 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev)
393 hpriv->clks[i] = clk; 405 hpriv->clks[i] = clk;
394 } 406 }
395 407
408 hpriv->rsts = devm_reset_control_array_get_optional_shared(dev);
409 if (IS_ERR(hpriv->rsts)) {
410 rc = PTR_ERR(hpriv->rsts);
411 goto err_out;
412 }
413
396 hpriv->nports = child_nodes = of_get_child_count(dev->of_node); 414 hpriv->nports = child_nodes = of_get_child_count(dev->of_node);
397 415
398 /* 416 /*
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 728ed4764678..8bc71ca61e7f 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -6026,7 +6026,7 @@ struct ata_port *ata_port_alloc(struct ata_host *host)
6026 return ap; 6026 return ap;
6027} 6027}
6028 6028
6029static void ata_host_release(struct device *gendev, void *res) 6029static void ata_devres_release(struct device *gendev, void *res)
6030{ 6030{
6031 struct ata_host *host = dev_get_drvdata(gendev); 6031 struct ata_host *host = dev_get_drvdata(gendev);
6032 int i; 6032 int i;
@@ -6040,13 +6040,36 @@ static void ata_host_release(struct device *gendev, void *res)
6040 if (ap->scsi_host) 6040 if (ap->scsi_host)
6041 scsi_host_put(ap->scsi_host); 6041 scsi_host_put(ap->scsi_host);
6042 6042
6043 }
6044
6045 dev_set_drvdata(gendev, NULL);
6046 ata_host_put(host);
6047}
6048
6049static void ata_host_release(struct kref *kref)
6050{
6051 struct ata_host *host = container_of(kref, struct ata_host, kref);
6052 int i;
6053
6054 for (i = 0; i < host->n_ports; i++) {
6055 struct ata_port *ap = host->ports[i];
6056
6043 kfree(ap->pmp_link); 6057 kfree(ap->pmp_link);
6044 kfree(ap->slave_link); 6058 kfree(ap->slave_link);
6045 kfree(ap); 6059 kfree(ap);
6046 host->ports[i] = NULL; 6060 host->ports[i] = NULL;
6047 } 6061 }
6062 kfree(host);
6063}
6048 6064
6049 dev_set_drvdata(gendev, NULL); 6065void ata_host_get(struct ata_host *host)
6066{
6067 kref_get(&host->kref);
6068}
6069
6070void ata_host_put(struct ata_host *host)
6071{
6072 kref_put(&host->kref, ata_host_release);
6050} 6073}
6051 6074
6052/** 6075/**
@@ -6074,26 +6097,31 @@ struct ata_host *ata_host_alloc(struct device *dev, int max_ports)
6074 struct ata_host *host; 6097 struct ata_host *host;
6075 size_t sz; 6098 size_t sz;
6076 int i; 6099 int i;
6100 void *dr;
6077 6101
6078 DPRINTK("ENTER\n"); 6102 DPRINTK("ENTER\n");
6079 6103
6080 if (!devres_open_group(dev, NULL, GFP_KERNEL))
6081 return NULL;
6082
6083 /* alloc a container for our list of ATA ports (buses) */ 6104 /* alloc a container for our list of ATA ports (buses) */
6084 sz = sizeof(struct ata_host) + (max_ports + 1) * sizeof(void *); 6105 sz = sizeof(struct ata_host) + (max_ports + 1) * sizeof(void *);
6085 /* alloc a container for our list of ATA ports (buses) */ 6106 host = kzalloc(sz, GFP_KERNEL);
6086 host = devres_alloc(ata_host_release, sz, GFP_KERNEL);
6087 if (!host) 6107 if (!host)
6108 return NULL;
6109
6110 if (!devres_open_group(dev, NULL, GFP_KERNEL))
6111 goto err_free;
6112
6113 dr = devres_alloc(ata_devres_release, 0, GFP_KERNEL);
6114 if (!dr)
6088 goto err_out; 6115 goto err_out;
6089 6116
6090 devres_add(dev, host); 6117 devres_add(dev, dr);
6091 dev_set_drvdata(dev, host); 6118 dev_set_drvdata(dev, host);
6092 6119
6093 spin_lock_init(&host->lock); 6120 spin_lock_init(&host->lock);
6094 mutex_init(&host->eh_mutex); 6121 mutex_init(&host->eh_mutex);
6095 host->dev = dev; 6122 host->dev = dev;
6096 host->n_ports = max_ports; 6123 host->n_ports = max_ports;
6124 kref_init(&host->kref);
6097 6125
6098 /* allocate ports bound to this host */ 6126 /* allocate ports bound to this host */
6099 for (i = 0; i < max_ports; i++) { 6127 for (i = 0; i < max_ports; i++) {
@@ -6112,6 +6140,8 @@ struct ata_host *ata_host_alloc(struct device *dev, int max_ports)
6112 6140
6113 err_out: 6141 err_out:
6114 devres_release_group(dev, NULL); 6142 devres_release_group(dev, NULL);
6143 err_free:
6144 kfree(host);
6115 return NULL; 6145 return NULL;
6116} 6146}
6117 6147
diff --git a/drivers/ata/libata-transport.c b/drivers/ata/libata-transport.c
index 19e6e539a061..a0b0b4d986f2 100644
--- a/drivers/ata/libata-transport.c
+++ b/drivers/ata/libata-transport.c
@@ -224,6 +224,8 @@ static DECLARE_TRANSPORT_CLASS(ata_port_class,
224 224
225static void ata_tport_release(struct device *dev) 225static void ata_tport_release(struct device *dev)
226{ 226{
227 struct ata_port *ap = tdev_to_port(dev);
228 ata_host_put(ap->host);
227} 229}
228 230
229/** 231/**
@@ -284,6 +286,7 @@ int ata_tport_add(struct device *parent,
284 dev->type = &ata_port_type; 286 dev->type = &ata_port_type;
285 287
286 dev->parent = parent; 288 dev->parent = parent;
289 ata_host_get(ap->host);
287 dev->release = ata_tport_release; 290 dev->release = ata_tport_release;
288 dev_set_name(dev, "ata%d", ap->print_id); 291 dev_set_name(dev, "ata%d", ap->print_id);
289 transport_setup_device(dev); 292 transport_setup_device(dev);
@@ -314,6 +317,7 @@ int ata_tport_add(struct device *parent,
314 tport_err: 317 tport_err:
315 transport_destroy_device(dev); 318 transport_destroy_device(dev);
316 put_device(dev); 319 put_device(dev);
320 ata_host_put(ap->host);
317 return error; 321 return error;
318} 322}
319 323
diff --git a/drivers/ata/libata.h b/drivers/ata/libata.h
index f953cb4bb1ba..9e21c49cf6be 100644
--- a/drivers/ata/libata.h
+++ b/drivers/ata/libata.h
@@ -100,6 +100,8 @@ extern int ata_port_probe(struct ata_port *ap);
100extern void __ata_port_probe(struct ata_port *ap); 100extern void __ata_port_probe(struct ata_port *ap);
101extern unsigned int ata_read_log_page(struct ata_device *dev, u8 log, 101extern unsigned int ata_read_log_page(struct ata_device *dev, u8 log,
102 u8 page, void *buf, unsigned int sectors); 102 u8 page, void *buf, unsigned int sectors);
103extern void ata_host_get(struct ata_host *host);
104extern void ata_host_put(struct ata_host *host);
103 105
104#define to_ata_port(d) container_of(d, struct ata_port, tdev) 106#define to_ata_port(d) container_of(d, struct ata_port, tdev)
105 107
diff --git a/drivers/ata/pata_arasan_cf.c b/drivers/ata/pata_arasan_cf.c
index b4d54771c9fe..ebecab8c3f36 100644
--- a/drivers/ata/pata_arasan_cf.c
+++ b/drivers/ata/pata_arasan_cf.c
@@ -796,7 +796,7 @@ static int arasan_cf_probe(struct platform_device *pdev)
796 struct resource *res; 796 struct resource *res;
797 u32 quirk; 797 u32 quirk;
798 irq_handler_t irq_handler = NULL; 798 irq_handler_t irq_handler = NULL;
799 int ret = 0; 799 int ret;
800 800
801 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 801 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
802 if (!res) 802 if (!res)
@@ -809,10 +809,8 @@ static int arasan_cf_probe(struct platform_device *pdev)
809 } 809 }
810 810
811 acdev = devm_kzalloc(&pdev->dev, sizeof(*acdev), GFP_KERNEL); 811 acdev = devm_kzalloc(&pdev->dev, sizeof(*acdev), GFP_KERNEL);
812 if (!acdev) { 812 if (!acdev)
813 dev_warn(&pdev->dev, "kzalloc fail\n");
814 return -ENOMEM; 813 return -ENOMEM;
815 }
816 814
817 if (pdata) 815 if (pdata)
818 quirk = pdata->quirk; 816 quirk = pdata->quirk;
diff --git a/drivers/ata/pata_bk3710.c b/drivers/ata/pata_bk3710.c
index 6c3bd5fae3e4..fad95cfecced 100644
--- a/drivers/ata/pata_bk3710.c
+++ b/drivers/ata/pata_bk3710.c
@@ -1,3 +1,5 @@
1// SPDX-License-Identifier: GPL-2.0
2
1/* 3/*
2 * Palmchip BK3710 PATA controller driver 4 * Palmchip BK3710 PATA controller driver
3 * 5 *
@@ -8,10 +10,6 @@
8 * 10 *
9 * Copyright (C) 2006 Texas Instruments. 11 * Copyright (C) 2006 Texas Instruments.
10 * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com> 12 * Copyright (C) 2007 MontaVista Software, Inc., <source@mvista.com>
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
14 * for more details.
15 */ 13 */
16 14
17#include <linux/ata.h> 15#include <linux/ata.h>
@@ -379,4 +377,4 @@ static int __init pata_bk3710_init(void)
379} 377}
380 378
381module_init(pata_bk3710_init); 379module_init(pata_bk3710_init);
382MODULE_LICENSE("GPL"); 380MODULE_LICENSE("GPL v2");
diff --git a/drivers/ata/pata_falcon.c b/drivers/ata/pata_falcon.c
index 5b0c57d1c59f..41e0d6a6cd05 100644
--- a/drivers/ata/pata_falcon.c
+++ b/drivers/ata/pata_falcon.c
@@ -1,3 +1,5 @@
1// SPDX-License-Identifier: GPL-2.0
2
1/* 3/*
2 * Atari Falcon PATA controller driver 4 * Atari Falcon PATA controller driver
3 * 5 *
@@ -7,10 +9,6 @@
7 * Based on falconide.c: 9 * Based on falconide.c:
8 * 10 *
9 * Created 12 Jul 1997 by Geert Uytterhoeven 11 * Created 12 Jul 1997 by Geert Uytterhoeven
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */ 12 */
15 13
16#include <linux/kernel.h> 14#include <linux/kernel.h>
@@ -180,5 +178,5 @@ module_init(pata_falcon_init_one);
180 178
181MODULE_AUTHOR("Bartlomiej Zolnierkiewicz"); 179MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
182MODULE_DESCRIPTION("low-level driver for Atari Falcon PATA"); 180MODULE_DESCRIPTION("low-level driver for Atari Falcon PATA");
183MODULE_LICENSE("GPL"); 181MODULE_LICENSE("GPL v2");
184MODULE_VERSION(DRV_VERSION); 182MODULE_VERSION(DRV_VERSION);
diff --git a/drivers/ata/pata_gayle.c b/drivers/ata/pata_gayle.c
new file mode 100644
index 000000000000..65bc9f3042ce
--- /dev/null
+++ b/drivers/ata/pata_gayle.c
@@ -0,0 +1,219 @@
1// SPDX-License-Identifier: GPL-2.0
2
3/*
4 * Amiga Gayle PATA controller driver
5 *
6 * Copyright (c) 2018 Samsung Electronics Co., Ltd.
7 * http://www.samsung.com
8 *
9 * Based on gayle.c:
10 *
11 * Created 12 Jul 1997 by Geert Uytterhoeven
12 */
13
14#include <linux/ata.h>
15#include <linux/blkdev.h>
16#include <linux/delay.h>
17#include <linux/interrupt.h>
18#include <linux/kernel.h>
19#include <linux/libata.h>
20#include <linux/mm.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/zorro.h>
24#include <scsi/scsi_cmnd.h>
25#include <scsi/scsi_host.h>
26
27#include <asm/amigahw.h>
28#include <asm/amigaints.h>
29#include <asm/amigayle.h>
30#include <asm/ide.h>
31#include <asm/setup.h>
32
33#define DRV_NAME "pata_gayle"
34#define DRV_VERSION "0.1.0"
35
36#define GAYLE_CONTROL 0x101a
37
38static struct scsi_host_template pata_gayle_sht = {
39 ATA_PIO_SHT(DRV_NAME),
40};
41
42/* FIXME: is this needed? */
43static unsigned int pata_gayle_data_xfer(struct ata_queued_cmd *qc,
44 unsigned char *buf,
45 unsigned int buflen, int rw)
46{
47 struct ata_device *dev = qc->dev;
48 struct ata_port *ap = dev->link->ap;
49 void __iomem *data_addr = ap->ioaddr.data_addr;
50 unsigned int words = buflen >> 1;
51
52 /* Transfer multiple of 2 bytes */
53 if (rw == READ)
54 raw_insw((u16 *)data_addr, (u16 *)buf, words);
55 else
56 raw_outsw((u16 *)data_addr, (u16 *)buf, words);
57
58 /* Transfer trailing byte, if any. */
59 if (unlikely(buflen & 0x01)) {
60 unsigned char pad[2] = { };
61
62 /* Point buf to the tail of buffer */
63 buf += buflen - 1;
64
65 if (rw == READ) {
66 raw_insw((u16 *)data_addr, (u16 *)pad, 1);
67 *buf = pad[0];
68 } else {
69 pad[0] = *buf;
70 raw_outsw((u16 *)data_addr, (u16 *)pad, 1);
71 }
72 words++;
73 }
74
75 return words << 1;
76}
77
78/*
79 * Provide our own set_mode() as we don't want to change anything that has
80 * already been configured..
81 */
82static int pata_gayle_set_mode(struct ata_link *link,
83 struct ata_device **unused)
84{
85 struct ata_device *dev;
86
87 ata_for_each_dev(dev, link, ENABLED) {
88 /* We don't really care */
89 dev->pio_mode = dev->xfer_mode = XFER_PIO_0;
90 dev->xfer_shift = ATA_SHIFT_PIO;
91 dev->flags |= ATA_DFLAG_PIO;
92 ata_dev_info(dev, "configured for PIO\n");
93 }
94 return 0;
95}
96
97static bool pata_gayle_irq_check(struct ata_port *ap)
98{
99 u8 ch;
100
101 ch = z_readb((unsigned long)ap->private_data);
102
103 return !!(ch & GAYLE_IRQ_IDE);
104}
105
106static void pata_gayle_irq_clear(struct ata_port *ap)
107{
108 (void)z_readb((unsigned long)ap->ioaddr.status_addr);
109 z_writeb(0x7c, (unsigned long)ap->private_data);
110}
111
112static struct ata_port_operations pata_gayle_a1200_ops = {
113 .inherits = &ata_sff_port_ops,
114 .sff_data_xfer = pata_gayle_data_xfer,
115 .sff_irq_check = pata_gayle_irq_check,
116 .sff_irq_clear = pata_gayle_irq_clear,
117 .cable_detect = ata_cable_unknown,
118 .set_mode = pata_gayle_set_mode,
119};
120
121static struct ata_port_operations pata_gayle_a4000_ops = {
122 .inherits = &ata_sff_port_ops,
123 .sff_data_xfer = pata_gayle_data_xfer,
124 .cable_detect = ata_cable_unknown,
125 .set_mode = pata_gayle_set_mode,
126};
127
128static int __init pata_gayle_init_one(struct platform_device *pdev)
129{
130 struct resource *res;
131 struct gayle_ide_platform_data *pdata;
132 struct ata_host *host;
133 struct ata_port *ap;
134 void __iomem *base;
135 int ret;
136
137 pdata = dev_get_platdata(&pdev->dev);
138
139 dev_info(&pdev->dev, "Amiga Gayle IDE controller (A%u style)\n",
140 pdata->explicit_ack ? 1200 : 4000);
141
142 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
143 if (!res)
144 return -ENODEV;
145
146 if (!devm_request_mem_region(&pdev->dev, res->start,
147 resource_size(res), DRV_NAME)) {
148 pr_err(DRV_NAME ": resources busy\n");
149 return -EBUSY;
150 }
151
152 /* allocate host */
153 host = ata_host_alloc(&pdev->dev, 1);
154 if (!host)
155 return -ENOMEM;
156
157 ap = host->ports[0];
158
159 if (pdata->explicit_ack)
160 ap->ops = &pata_gayle_a1200_ops;
161 else
162 ap->ops = &pata_gayle_a4000_ops;
163
164 ap->pio_mask = ATA_PIO4;
165 ap->flags |= ATA_FLAG_SLAVE_POSS | ATA_FLAG_NO_IORDY;
166
167 base = ZTWO_VADDR(pdata->base);
168 ap->ioaddr.data_addr = base;
169 ap->ioaddr.error_addr = base + 2 + 1 * 4;
170 ap->ioaddr.feature_addr = base + 2 + 1 * 4;
171 ap->ioaddr.nsect_addr = base + 2 + 2 * 4;
172 ap->ioaddr.lbal_addr = base + 2 + 3 * 4;
173 ap->ioaddr.lbam_addr = base + 2 + 4 * 4;
174 ap->ioaddr.lbah_addr = base + 2 + 5 * 4;
175 ap->ioaddr.device_addr = base + 2 + 6 * 4;
176 ap->ioaddr.status_addr = base + 2 + 7 * 4;
177 ap->ioaddr.command_addr = base + 2 + 7 * 4;
178
179 ap->ioaddr.altstatus_addr = base + GAYLE_CONTROL;
180 ap->ioaddr.ctl_addr = base + GAYLE_CONTROL;
181
182 ap->private_data = (void *)ZTWO_VADDR(pdata->irqport);
183
184 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", pdata->base,
185 pdata->base + GAYLE_CONTROL);
186
187 ret = ata_host_activate(host, IRQ_AMIGA_PORTS, ata_sff_interrupt,
188 IRQF_SHARED, &pata_gayle_sht);
189 if (ret)
190 return ret;
191
192 platform_set_drvdata(pdev, host);
193
194 return 0;
195}
196
197static int __exit pata_gayle_remove_one(struct platform_device *pdev)
198{
199 struct ata_host *host = platform_get_drvdata(pdev);
200
201 ata_host_detach(host);
202
203 return 0;
204}
205
206static struct platform_driver pata_gayle_driver = {
207 .remove = __exit_p(pata_gayle_remove_one),
208 .driver = {
209 .name = "amiga-gayle-ide",
210 },
211};
212
213module_platform_driver_probe(pata_gayle_driver, pata_gayle_init_one);
214
215MODULE_AUTHOR("Bartlomiej Zolnierkiewicz");
216MODULE_DESCRIPTION("low-level driver for Amiga Gayle PATA");
217MODULE_LICENSE("GPL v2");
218MODULE_ALIAS("platform:amiga-gayle-ide");
219MODULE_VERSION(DRV_VERSION);
diff --git a/drivers/ata/pata_it821x.c b/drivers/ata/pata_it821x.c
index 8468b300193b..9bac79edbc2c 100644
--- a/drivers/ata/pata_it821x.c
+++ b/drivers/ata/pata_it821x.c
@@ -658,10 +658,10 @@ static u8 *it821x_firmware_command(struct ata_port *ap, u8 cmd, int len)
658 u8 status; 658 u8 status;
659 int n = 0; 659 int n = 0;
660 u16 *buf = kmalloc(len, GFP_KERNEL); 660 u16 *buf = kmalloc(len, GFP_KERNEL);
661 if (buf == NULL) { 661
662 printk(KERN_ERR "it821x_firmware_command: Out of memory\n"); 662 if (!buf)
663 return NULL; 663 return NULL;
664 } 664
665 /* This isn't quite a normal ATA command as we are talking to the 665 /* This isn't quite a normal ATA command as we are talking to the
666 firmware not the drives */ 666 firmware not the drives */
667 ap->ctl |= ATA_NIEN; 667 ap->ctl |= ATA_NIEN;
diff --git a/drivers/ata/pata_macio.c b/drivers/ata/pata_macio.c
index 0adcb40d2794..9588e685d994 100644
--- a/drivers/ata/pata_macio.c
+++ b/drivers/ata/pata_macio.c
@@ -1131,11 +1131,9 @@ static int pata_macio_attach(struct macio_dev *mdev,
1131 /* Allocate and init private data structure */ 1131 /* Allocate and init private data structure */
1132 priv = devm_kzalloc(&mdev->ofdev.dev, 1132 priv = devm_kzalloc(&mdev->ofdev.dev,
1133 sizeof(struct pata_macio_priv), GFP_KERNEL); 1133 sizeof(struct pata_macio_priv), GFP_KERNEL);
1134 if (priv == NULL) { 1134 if (!priv)
1135 dev_err(&mdev->ofdev.dev,
1136 "Failed to allocate private memory\n");
1137 return -ENOMEM; 1135 return -ENOMEM;
1138 } 1136
1139 priv->node = of_node_get(mdev->ofdev.dev.of_node); 1137 priv->node = of_node_get(mdev->ofdev.dev.of_node);
1140 priv->mdev = mdev; 1138 priv->mdev = mdev;
1141 priv->dev = &mdev->ofdev.dev; 1139 priv->dev = &mdev->ofdev.dev;
@@ -1277,11 +1275,9 @@ static int pata_macio_pci_attach(struct pci_dev *pdev,
1277 /* Allocate and init private data structure */ 1275 /* Allocate and init private data structure */
1278 priv = devm_kzalloc(&pdev->dev, 1276 priv = devm_kzalloc(&pdev->dev,
1279 sizeof(struct pata_macio_priv), GFP_KERNEL); 1277 sizeof(struct pata_macio_priv), GFP_KERNEL);
1280 if (priv == NULL) { 1278 if (!priv)
1281 dev_err(&pdev->dev,
1282 "Failed to allocate private memory\n");
1283 return -ENOMEM; 1279 return -ENOMEM;
1284 } 1280
1285 priv->node = of_node_get(np); 1281 priv->node = of_node_get(np);
1286 priv->pdev = pdev; 1282 priv->pdev = pdev;
1287 priv->dev = &pdev->dev; 1283 priv->dev = &pdev->dev;
diff --git a/drivers/ata/pata_mpc52xx.c b/drivers/ata/pata_mpc52xx.c
index 9730125530f6..f1d352d5f128 100644
--- a/drivers/ata/pata_mpc52xx.c
+++ b/drivers/ata/pata_mpc52xx.c
@@ -738,7 +738,6 @@ static int mpc52xx_ata_probe(struct platform_device *op)
738 /* Prepare our private structure */ 738 /* Prepare our private structure */
739 priv = devm_kzalloc(&op->dev, sizeof(*priv), GFP_ATOMIC); 739 priv = devm_kzalloc(&op->dev, sizeof(*priv), GFP_ATOMIC);
740 if (!priv) { 740 if (!priv) {
741 dev_err(&op->dev, "error allocating private structure\n");
742 rv = -ENOMEM; 741 rv = -ENOMEM;
743 goto err1; 742 goto err1;
744 } 743 }
diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c
index 50801c40b029..bb96dc35950d 100644
--- a/drivers/ata/pata_samsung_cf.c
+++ b/drivers/ata/pata_samsung_cf.c
@@ -505,10 +505,8 @@ static int __init pata_s3c_probe(struct platform_device *pdev)
505 cpu_type = platform_get_device_id(pdev)->driver_data; 505 cpu_type = platform_get_device_id(pdev)->driver_data;
506 506
507 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 507 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
508 if (!info) { 508 if (!info)
509 dev_err(dev, "failed to allocate memory for device data\n");
510 return -ENOMEM; 509 return -ENOMEM;
511 }
512 510
513 info->irq = platform_get_irq(pdev, 0); 511 info->irq = platform_get_irq(pdev, 0);
514 512
diff --git a/drivers/ata/sata_dwc_460ex.c b/drivers/ata/sata_dwc_460ex.c
index 6af4ec3c88c3..ce3d6674ef80 100644
--- a/drivers/ata/sata_dwc_460ex.c
+++ b/drivers/ata/sata_dwc_460ex.c
@@ -901,7 +901,6 @@ static int sata_dwc_port_start(struct ata_port *ap)
901 /* Allocate Port Struct */ 901 /* Allocate Port Struct */
902 hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL); 902 hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL);
903 if (!hsdevp) { 903 if (!hsdevp) {
904 dev_err(ap->dev, "%s: kmalloc failed for hsdevp\n", __func__);
905 err = -ENOMEM; 904 err = -ENOMEM;
906 goto CLEANUP; 905 goto CLEANUP;
907 } 906 }
diff --git a/include/linux/libata.h b/include/linux/libata.h
index ed9826b21c5e..1795fecdea17 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -617,6 +617,7 @@ struct ata_host {
617 void *private_data; 617 void *private_data;
618 struct ata_port_operations *ops; 618 struct ata_port_operations *ops;
619 unsigned long flags; 619 unsigned long flags;
620 struct kref kref;
620 621
621 struct mutex eh_mutex; 622 struct mutex eh_mutex;
622 struct task_struct *eh_owner; 623 struct task_struct *eh_owner;
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
index c8e0164c5423..e06f5f79eaef 100644
--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -243,6 +243,8 @@
243#define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0) 243#define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0)
244 244
245#define IMX6Q_GPR5_L2_CLK_STOP BIT(8) 245#define IMX6Q_GPR5_L2_CLK_STOP BIT(8)
246#define IMX6Q_GPR5_SATA_SW_PD BIT(10)
247#define IMX6Q_GPR5_SATA_SW_RST BIT(11)
246 248
247#define IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK (0xf << 0) 249#define IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK (0xf << 0)
248#define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK (0xf << 4) 250#define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK (0xf << 4)
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-10 23:05:00 -0500