diff options
-rw-r--r-- | drivers/mtd/nand/denali.c | 42 |
1 files changed, 3 insertions, 39 deletions
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 4e6d03d7a031..65cf7cccedbe 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c | |||
@@ -84,7 +84,6 @@ static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd) | |||
84 | #define SPARE_ACCESS 0x41 | 84 | #define SPARE_ACCESS 0x41 |
85 | #define MAIN_ACCESS 0x42 | 85 | #define MAIN_ACCESS 0x42 |
86 | #define MAIN_SPARE_ACCESS 0x43 | 86 | #define MAIN_SPARE_ACCESS 0x43 |
87 | #define PIPELINE_ACCESS 0x2000 | ||
88 | 87 | ||
89 | #define DENALI_READ 0 | 88 | #define DENALI_READ 0 |
90 | #define DENALI_WRITE 0x100 | 89 | #define DENALI_WRITE 0x100 |
@@ -683,15 +682,7 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, | |||
683 | int access_type, int op) | 682 | int access_type, int op) |
684 | { | 683 | { |
685 | int status = PASS; | 684 | int status = PASS; |
686 | uint32_t page_count = 1; | 685 | uint32_t addr, cmd; |
687 | uint32_t addr, cmd, irq_status, irq_mask; | ||
688 | |||
689 | if (op == DENALI_READ) | ||
690 | irq_mask = INTR__LOAD_COMP; | ||
691 | else if (op == DENALI_WRITE) | ||
692 | irq_mask = 0; | ||
693 | else | ||
694 | BUG(); | ||
695 | 686 | ||
696 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); | 687 | setup_ecc_for_xfer(denali, ecc_en, transfer_spare); |
697 | 688 | ||
@@ -714,35 +705,8 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, | |||
714 | cmd = MODE_10 | addr; | 705 | cmd = MODE_10 | addr; |
715 | index_addr(denali, cmd, access_type); | 706 | index_addr(denali, cmd, access_type); |
716 | 707 | ||
717 | /* | 708 | cmd = MODE_01 | addr; |
718 | * page 33 of the NAND controller spec indicates we should not | 709 | iowrite32(cmd, denali->flash_mem); |
719 | * use the pipeline commands in Spare area only mode. | ||
720 | * So we don't. | ||
721 | */ | ||
722 | if (access_type == SPARE_ACCESS) { | ||
723 | cmd = MODE_01 | addr; | ||
724 | iowrite32(cmd, denali->flash_mem); | ||
725 | } else { | ||
726 | index_addr(denali, cmd, | ||
727 | PIPELINE_ACCESS | op | page_count); | ||
728 | |||
729 | /* | ||
730 | * wait for command to be accepted | ||
731 | * can always use status0 bit as the | ||
732 | * mask is identical for each bank. | ||
733 | */ | ||
734 | irq_status = wait_for_irq(denali, irq_mask); | ||
735 | |||
736 | if (irq_status == 0) { | ||
737 | dev_err(denali->dev, | ||
738 | "cmd, page, addr on timeout (0x%x, 0x%x, 0x%x)\n", | ||
739 | cmd, denali->page, addr); | ||
740 | status = FAIL; | ||
741 | } else { | ||
742 | cmd = MODE_01 | addr; | ||
743 | iowrite32(cmd, denali->flash_mem); | ||
744 | } | ||
745 | } | ||
746 | } | 710 | } |
747 | return status; | 711 | return status; |
748 | } | 712 | } |