2 files changed, 23 insertions, 13 deletions

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 3091ae5975a3..7e9ab1fa090c 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -84,16 +84,26 @@
 
 #endif  /* CONFIG_BROKEN_GAS_INST */
 
-#define REG_PSTATE_PAN_IMM              sys_reg(0, 0, 4, 0, 4)
-#define REG_PSTATE_UAO_IMM              sys_reg(0, 0, 4, 0, 3)
-#define REG_PSTATE_SSBS_IMM             sys_reg(0, 3, 4, 0, 1)
-
-#define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \
-                                      (!!x)<<8 | 0x1f)
-#define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \
-                                      (!!x)<<8 | 0x1f)
-#define SET_PSTATE_SSBS(x) __emit_inst(0xd5000000 | REG_PSTATE_SSBS_IMM | \
-                                       (!!x)<<8 | 0x1f)
+/*
+ * Instructions for modifying PSTATE fields.
+ * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
+ * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions
+ * for accessing PSTATE fields have the following encoding:
+ *      Op0 = 0, CRn = 4
+ *      Op1, Op2 encodes the PSTATE field modified and defines the constraints.
+ *      CRm = Imm4 for the instruction.
+ *      Rt = 0x1f
+ */
+#define pstate_field(op1, op2)          ((op1) << Op1_shift | (op2) << Op2_shift)
+#define PSTATE_Imm_shift                CRm_shift
+
+#define PSTATE_PAN                      pstate_field(0, 4)
+#define PSTATE_UAO                      pstate_field(0, 3)
+#define PSTATE_SSBS                     pstate_field(3, 1)
+
+#define SET_PSTATE_PAN(x)               __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift))
+#define SET_PSTATE_UAO(x)               __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift))
+#define SET_PSTATE_SSBS(x)              __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift))
 
 #define SYS_DC_ISW                      sys_insn(1, 0, 7, 6, 2)
 #define SYS_DC_CSW                      sys_insn(1, 0, 7, 10, 2)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 35796ca1db50..f15e2fb97011 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1045,7 +1045,7 @@ static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
         if (user_mode(regs))
                 return 1;
 
-        if (instr & BIT(CRm_shift))
+        if (instr & BIT(PSTATE_Imm_shift))
                 regs->pstate |= PSR_SSBS_BIT;
         else
                 regs->pstate &= ~PSR_SSBS_BIT;
@@ -1055,8 +1055,8 @@ static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
 }
 
 static struct undef_hook ssbs_emulation_hook = {
-        .instr_mask     = ~(1U << CRm_shift),
-        .instr_val      = 0xd500001f | REG_PSTATE_SSBS_IMM,
+        .instr_mask     = ~(1U << PSTATE_Imm_shift),
+        .instr_val      = 0xd500401f | PSTATE_SSBS,
         .fn             = ssbs_emulation_handler,
 };