205 files changed, 6399 insertions, 3427 deletions

diff --git a/Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt b/Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt
new file mode 100644
index 000000000000..0a2df4338332
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt
@@ -0,0 +1,31 @@
+Lantiq XWAY SoC FPI BUS binding
+============================
+
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible                    : Should be one of
+                                        "lantiq,xrx200-fpi"
+- reg                           : The address and length of the XBAR
+                                  configuration register.
+                                  Address and length of the FPI bus itself.
+- lantiq,rcu                    : A phandle to the RCU syscon
+- lantiq,offset-endianness      : Offset of the endianness configuration
+                                  register
+
+-------------------------------------------------------------------------------
+Example for the FPI on the xrx200 SoCs:
+        fpi@10000000 {
+                compatible = "lantiq,xrx200-fpi";
+                ranges = <0x0 0x10000000 0xf000000>;
+                reg =   <0x1f400000 0x1000>,
+                        <0x10000000 0xf000000>;
+                lantiq,rcu = <&rcu0>;
+                lantiq,offset-endianness = <0x4c>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                gptu@e100a00 {
+                        ......
+                };
+        };
diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
new file mode 100644
index 000000000000..a0c19bd1ce66
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt
@@ -0,0 +1,36 @@
+Lantiq XWAY SoC GPHY binding
+============================
+
+This binding describes a software-defined ethernet PHY, provided by the RCU
+module on newer Lantiq XWAY SoCs (xRX200 and newer).
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible            : Should be one of
+                                "lantiq,xrx200a1x-gphy"
+                                "lantiq,xrx200a2x-gphy"
+                                "lantiq,xrx300-gphy"
+                                "lantiq,xrx330-gphy"
+- reg                   : Addrress of the GPHY FW load address register
+- resets                : Must reference the RCU GPHY reset bit
+- reset-names           : One entry, value must be "gphy" or optional "gphy2"
+- clocks                : A reference to the (PMU) GPHY clock gate
+
+Optional properties:
+- lantiq,gphy-mode      : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
+                          <dt-bindings/mips/lantiq_xway_gphy.h>
+
+
+-------------------------------------------------------------------------------
+Example for the GPHys on the xRX200 SoCs:
+
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+        gphy0: gphy@20 {
+                compatible = "lantiq,xrx200a2x-gphy";
+                reg = <0x20 0x4>;
+
+                resets = <&reset0 31 30>, <&reset1 7 7>;
+                reset-names = "gphy", "gphy2";
+                clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
+                lantiq,gphy-mode = <GPHY_MODE_GE>;
+        };
diff --git a/Documentation/devicetree/bindings/mips/lantiq/rcu.txt b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
new file mode 100644
index 000000000000..a086f1e1cdd7
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/lantiq/rcu.txt
@@ -0,0 +1,89 @@
+Lantiq XWAY SoC RCU binding
+===========================
+
+This binding describes the RCU (reset controller unit) multifunction device,
+where each sub-device has it's own set of registers.
+
+The RCU register range is used for multiple purposes. Mostly one device
+uses one or multiple register exclusively, but for some registers some
+bits are for one driver and some other bits are for a different driver.
+With this patch all accesses to the RCU registers will go through
+syscon.
+
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible    : The first and second values must be:
+                  "lantiq,xrx200-rcu", "simple-mfd", "syscon"
+- reg           : The address and length of the system control registers
+
+
+-------------------------------------------------------------------------------
+Example of the RCU bindings on a xRX200 SoC:
+        rcu0: rcu@203000 {
+                compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon";
+                reg = <0x203000 0x100>;
+                ranges = <0x0 0x203000 0x100>;
+                big-endian;
+
+                gphy0: gphy@20 {
+                        compatible = "lantiq,xrx200a2x-gphy";
+                        reg = <0x20 0x4>;
+
+                        resets = <&reset0 31 30>, <&reset1 7 7>;
+                        reset-names = "gphy", "gphy2";
+                        lantiq,gphy-mode = <GPHY_MODE_GE>;
+                };
+
+                gphy1: gphy@68 {
+                        compatible = "lantiq,xrx200a2x-gphy";
+                        reg = <0x68 0x4>;
+
+                        resets = <&reset0 29 28>, <&reset1 6 6>;
+                        reset-names = "gphy", "gphy2";
+                        lantiq,gphy-mode = <GPHY_MODE_GE>;
+                };
+
+                reset0: reset-controller@10 {
+                        compatible = "lantiq,xrx200-reset";
+                        reg = <0x10 4>, <0x14 4>;
+
+                        #reset-cells = <2>;
+                };
+
+                reset1: reset-controller@48 {
+                        compatible = "lantiq,xrx200-reset";
+                        reg = <0x48 4>, <0x24 4>;
+
+                        #reset-cells = <2>;
+                };
+
+                usb_phy0: usb2-phy@18 {
+                        compatible = "lantiq,xrx200-usb2-phy";
+                        reg = <0x18 4>, <0x38 4>;
+                        status = "disabled";
+
+                        resets = <&reset1 4 4>, <&reset0 4 4>;
+                        reset-names = "phy", "ctrl";
+                        #phy-cells = <0>;
+                };
+
+                usb_phy1: usb2-phy@34 {
+                        compatible = "lantiq,xrx200-usb2-phy";
+                        reg = <0x34 4>, <0x3C 4>;
+                        status = "disabled";
+
+                        resets = <&reset1 5 4>, <&reset0 4 4>;
+                        reset-names = "phy", "ctrl";
+                        #phy-cells = <0>;
+                };
+
+                reboot@10 {
+                        compatible = "syscon-reboot";
+                        reg = <0x10 4>;
+
+                        regmap = <&rcu0>;
+                        offset = <0x10>;
+                        mask = <0x40000000>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/mips/ni.txt b/Documentation/devicetree/bindings/mips/ni.txt
new file mode 100644
index 000000000000..722bf2d62da9
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/ni.txt
@@ -0,0 +1,7 @@
+National Instruments MIPS platforms
+
+required root node properties:
+        - compatible: must be "ni,169445"
+
+CPU Nodes
+        - compatible: must be "mti,mips14KEc"
diff --git a/Documentation/devicetree/bindings/mips/ralink.txt b/Documentation/devicetree/bindings/mips/ralink.txt
index b35a8d04f8b6..a16e8d7fe56c 100644
--- a/Documentation/devicetree/bindings/mips/ralink.txt
+++ b/Documentation/devicetree/bindings/mips/ralink.txt
@@ -15,3 +15,4 @@ value must be one of the following values:
   ralink,rt5350-soc
   ralink,mt7620a-soc
   ralink,mt7620n-soc
+  ralink,mt7628a-soc
diff --git a/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
new file mode 100644
index 000000000000..643948b6b576
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt
@@ -0,0 +1,40 @@
+Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
+===========================================
+
+This binding describes the USB PHY hardware provided by the RCU module on the
+Lantiq XWAY SoCs.
+
+This node has to be a sub node of the Lantiq RCU block.
+
+-------------------------------------------------------------------------------
+Required properties (controller (parent) node):
+- compatible    : Should be one of
+                        "lantiq,ase-usb2-phy"
+                        "lantiq,danube-usb2-phy"
+                        "lantiq,xrx100-usb2-phy"
+                        "lantiq,xrx200-usb2-phy"
+                        "lantiq,xrx300-usb2-phy"
+- reg           : Defines the following sets of registers in the parent
+                  syscon device
+                        - Offset of the USB PHY configuration register
+                        - Offset of the USB Analog configuration
+                          register (only for xrx200 and xrx200)
+- clocks        : References to the (PMU) "phy" clk gate.
+- clock-names   : Must be "phy"
+- resets        : References to the RCU USB configuration reset bits.
+- reset-names   : Must be one of the following:
+                        "phy" (optional)
+                        "ctrl" (shared)
+
+-------------------------------------------------------------------------------
+Example for the USB PHYs on an xRX200 SoC:
+        usb_phy0: usb2-phy@18 {
+                compatible = "lantiq,xrx200-usb2-phy";
+                reg = <0x18 4>, <0x38 4>;
+
+                clocks = <&pmu PMU_GATE_USB0_PHY>;
+                clock-names = "phy";
+                resets = <&reset1 4 4>, <&reset0 4 4>;
+                reset-names = "phy", "ctrl";
+                #phy-cells = <0>;
+        };
diff --git a/Documentation/devicetree/bindings/reset/lantiq,reset.txt b/Documentation/devicetree/bindings/reset/lantiq,reset.txt
new file mode 100644
index 000000000000..c6aef36b7d15
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/lantiq,reset.txt
@@ -0,0 +1,30 @@
+Lantiq XWAY SoC RCU reset controller binding
+============================================
+
+This binding describes a reset-controller found on the RCU module on Lantiq
+XWAY SoCs.
+
+This node has to be a sub node of the Lantiq RCU block.
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible            : Should be one of
+                                "lantiq,danube-reset"
+                                "lantiq,xrx200-reset"
+- reg                   : Defines the following sets of registers in the parent
+                          syscon device
+                        - Offset of the reset set register
+                        - Offset of the reset status register
+- #reset-cells          : Specifies the number of cells needed to encode the
+                          reset line, should be 2.
+                          The first cell takes the reset set bit and the
+                          second cell takes the status bit.
+
+-------------------------------------------------------------------------------
+Example for the reset-controllers on the xRX200 SoCs:
+        reset0: reset-controller@10 {
+                compatible = "lantiq,xrx200-reset";
+                reg <0x10 0x04>, <0x14 0x04>;
+
+                #reset-cells = <2>;
+        };
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 69183f0fbc78..1ea1fd4232ab 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -361,6 +361,7 @@ variscite	Variscite Ltd.
 via     VIA Technologies, Inc.
 virtio  Virtual I/O Device Specification, developed by the OASIS consortium
 vivante Vivante Corporation
+vocore VoCore Studio
 voipac  Voipac Technologies s.r.o.
 wd      Western Digital Corp.
 wetek   WeTek Electronics, limited.
diff --git a/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt b/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt
new file mode 100644
index 000000000000..18d4d8302702
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt
@@ -0,0 +1,24 @@
+Lantiq WTD watchdog binding
+============================
+
+This describes the binding of the Lantiq watchdog driver.
+
+-------------------------------------------------------------------------------
+Required properties:
+- compatible            : Should be one of
+                                "lantiq,wdt"
+                                "lantiq,xrx100-wdt"
+                                "lantiq,xrx200-wdt", "lantiq,xrx100-wdt"
+                                "lantiq,falcon-wdt"
+- reg                   : Address of the watchdog block
+- lantiq,rcu            : A phandle to the RCU syscon (required for
+                          "lantiq,falcon-wdt" and "lantiq,xrx100-wdt")
+
+-------------------------------------------------------------------------------
+Example for the watchdog on the xRX200 SoCs:
+                watchdog@803f0 {
+                        compatible = "lantiq,xrx200-wdt", "lantiq,xrx100-wdt";
+                        reg = <0x803f0 0x10>;
+
+                        lantiq,rcu = <&rcu0>;
+                };
diff --git a/MAINTAINERS b/MAINTAINERS
index 4b914dd27bae..ef65785cdff2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7717,6 +7717,7 @@ M:	John Crispin <john@phrozen.org>
 L:      linux-mips@linux-mips.org
 S:      Maintained
 F:      arch/mips/lantiq
+F:      drivers/soc/lantiq
 
 LAPB module
 L:      linux-x25@vger.kernel.org
@@ -8982,6 +8983,7 @@ M:	Paul Burton <paul.burton@imgtec.com>
 L:      linux-mips@linux-mips.org
 S:      Supported
 F:      arch/mips/generic/
+F:      arch/mips/tools/generic-board-config.sh
 
 MIPS/LOONGSON1 ARCHITECTURE
 M:      Keguang Zhang <keguang.zhang@gmail.com>
@@ -8992,6 +8994,13 @@ F:	arch/mips/include/asm/mach-loongson32/
 F:      drivers/*/*loongson1*
 F:      drivers/*/*/*loongson1*
 
+MIPS RINT INSTRUCTION EMULATION
+M:      Aleksandar Markovic <aleksandar.markovic@imgtec.com>
+L:      linux-mips@linux-mips.org
+S:      Supported
+F:      arch/mips/math-emu/sp_rint.c
+F:      arch/mips/math-emu/dp_rint.c
+
 MIROSOUND PCM20 FM RADIO RECEIVER DRIVER
 M:      Hans Verkuil <hverkuil@xs4all.nl>
 L:      linux-media@vger.kernel.org
@@ -9869,6 +9878,12 @@ F:	drivers/regulator/twl-regulator.c
 F:      drivers/regulator/twl6030-regulator.c
 F:      include/linux/i2c-omap.h
 
+ONION OMEGA2+ BOARD
+M:      Harvey Hunt <harveyhuntnexus@gmail.com>
+L:      linux-mips@linux-mips.org
+S:      Maintained
+F:      arch/mips/boot/dts/ralink/omega2p.dts
+
 OMFS FILESYSTEM
 M:      Bob Copeland <me@bobcopeland.com>
 L:      linux-karma-devel@lists.sourceforge.net
@@ -14390,6 +14405,12 @@ L:	netdev@vger.kernel.org
 S:      Maintained
 F:      drivers/net/vmxnet3/
 
+VOCORE VOCORE2 BOARD
+M:      Harvey Hunt <harveyhuntnexus@gmail.com>
+L:      linux-mips@linux-mips.org
+S:      Maintained
+F:      arch/mips/boot/dts/ralink/vocore2.dts
+
 VOLTAGE AND CURRENT REGULATOR FRAMEWORK
 M:      Liam Girdwood <lgirdwood@gmail.com>
 M:      Mark Brown <broonie@kernel.org>
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 48d91d5be4e9..cb7fcc4216fd 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1627,14 +1627,6 @@ config CPU_R5500
           NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
           instruction set.
 
-config CPU_R6000
-        bool "R6000"
-        depends on SYS_HAS_CPU_R6000
-        select CPU_SUPPORTS_32BIT_KERNEL
-        help
-          MIPS Technologies R6000 and R6000A series processors.  Note these
-          processors are extremely rare and the support for them is incomplete.
-
 config CPU_NEVADA
         bool "RM52xx"
         depends on SYS_HAS_CPU_NEVADA
@@ -1950,9 +1942,6 @@ config SYS_HAS_CPU_R5432
 config SYS_HAS_CPU_R5500
         bool
 
-config SYS_HAS_CPU_R6000
-        bool
-
 config SYS_HAS_CPU_NEVADA
         bool
 
@@ -2180,7 +2169,7 @@ config PAGE_SIZE_32KB
 
 config PAGE_SIZE_64KB
         bool "64kB"
-        depends on !CPU_R3000 && !CPU_TX39XX && !CPU_R6000
+        depends on !CPU_R3000 && !CPU_TX39XX
         help
           Using 64kB page size will result in higher performance kernel at
           the price of higher memory consumption.  This option is available on
@@ -2248,11 +2237,11 @@ config CPU_HAS_PREFETCH
 
 config CPU_GENERIC_DUMP_TLB
         bool
-        default y if !(CPU_R3000 || CPU_R6000 || CPU_R8000 || CPU_TX39XX)
+        default y if !(CPU_R3000 || CPU_R8000 || CPU_TX39XX)
 
 config CPU_R4K_FPU
         bool
-        default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || CPU_CAVIUM_OCTEON)
+        default y if !(CPU_R3000 || CPU_TX39XX)
 
 config CPU_R4K_CACHE_TLB
         bool
@@ -2260,6 +2249,7 @@ config CPU_R4K_CACHE_TLB
 
 config MIPS_MT_SMP
         bool "MIPS MT SMP support (1 TC on each available VPE)"
+        default y
         depends on SYS_SUPPORTS_MULTITHREADING && !CPU_MIPSR6 && !CPU_MICROMIPS
         select CPU_MIPSR2_IRQ_VI
         select CPU_MIPSR2_IRQ_EI
@@ -2376,7 +2366,6 @@ config MIPS_CPS
         bool "MIPS Coherent Processing System support"
         depends on SYS_SUPPORTS_MIPS_CPS
         select MIPS_CM
-        select MIPS_CPC
         select MIPS_CPS_PM if HOTPLUG_CPU
         select SMP
         select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
@@ -2393,11 +2382,11 @@ config MIPS_CPS
 
 config MIPS_CPS_PM
         depends on MIPS_CPS
-        select MIPS_CPC
         bool
 
 config MIPS_CM
         bool
+        select MIPS_CPC
 
 config MIPS_CPC
         bool
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index bc2708c9ada4..a96d97a806c9 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -151,7 +151,6 @@ cflags-y += -fno-stack-check
 #
 cflags-$(CONFIG_CPU_R3000)      += -march=r3000
 cflags-$(CONFIG_CPU_TX39XX)     += -march=r3900
-cflags-$(CONFIG_CPU_R6000)      += -march=r6000 -Wa,--trap
 cflags-$(CONFIG_CPU_R4300)      += -march=r4300 -Wa,--trap
 cflags-$(CONFIG_CPU_VR41XX)     += -march=r4100 -Wa,--trap
 cflags-$(CONFIG_CPU_R4X00)      += -march=r4600 -Wa,--trap
@@ -291,7 +290,8 @@ KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)
 
 bootvars-y      = VMLINUX_LOAD_ADDRESS=$(load-y) \
                   VMLINUX_ENTRY_ADDRESS=$(entry-y) \
-                  PLATFORM="$(platform-y)"
+                  PLATFORM="$(platform-y)" \
+                  ITS_INPUTS="$(its-y)"
 ifdef CONFIG_32BIT
 bootvars-y      += ADDR_BITS=32
 endif
@@ -299,6 +299,10 @@ ifdef CONFIG_64BIT
 bootvars-y      += ADDR_BITS=64
 endif
 
+# This is required to get dwarf unwinding tables into .debug_frame
+# instead of .eh_frame so we don't discard them.
+KBUILD_CFLAGS += -fno-asynchronous-unwind-tables
+
 LDFLAGS                 += -m $(ld-emul)
 
 ifdef CONFIG_MIPS
@@ -500,8 +504,14 @@ $(eval $(call gen_generic_defconfigs,micro32,r2,eb el))
 .PHONY: $(generic_defconfigs)
 $(generic_defconfigs):
         $(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh \
-                -m -O $(objtree) $(srctree)/arch/$(ARCH)/configs/generic_defconfig $^ \
-                $(foreach board,$(BOARDS),$(generic_config_dir)/board-$(board).config)
+                -m -O $(objtree) $(srctree)/arch/$(ARCH)/configs/generic_defconfig $^ | \
+                grep -Ev '^#'
+        $(Q)cp $(KCONFIG_CONFIG) $(objtree)/.config.$@
+        $(Q)$(MAKE) -f $(srctree)/Makefile olddefconfig \
+                KCONFIG_CONFIG=$(objtree)/.config.$@ >/dev/null
+        $(Q)$(CONFIG_SHELL) $(srctree)/arch/$(ARCH)/tools/generic-board-config.sh \
+                $(srctree) $(objtree) $(objtree)/.config.$@ $(KCONFIG_CONFIG) \
+                "$(origin BOARDS)" $(BOARDS)
         $(Q)$(MAKE) -f $(srctree)/Makefile olddefconfig
 
 #
@@ -510,6 +520,19 @@ $(generic_defconfigs):
 $(generic_config_dir)/%.config: ;
 
 #
+# Prevent direct use of generic_defconfig, which is intended to be used as the
+# basis of the various ISA-specific targets generated above.
+#
+.PHONY: generic_defconfig
+generic_defconfig:
+        $(Q)echo "generic_defconfig is not intended for direct use, but should instead be"
+        $(Q)echo "used via an ISA-specific target from the following list:"
+        $(Q)echo
+        $(Q)for cfg in $(generic_defconfigs); do echo "  $${cfg}"; done
+        $(Q)echo
+        $(Q)false
+
+#
 # Legacy defconfig compatibility - these targets used to be real defconfigs but
 # now that the boards have been converted to use the generic kernel they are
 # wrappers around the generic rules above.
diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c
index 83831002c832..da7663770425 100644
--- a/arch/mips/alchemy/devboards/db1200.c
+++ b/arch/mips/alchemy/devboards/db1200.c
@@ -344,28 +344,32 @@ static struct platform_device db1200_ide_dev = {
 
 /* SD carddetects:  they're supposed to be edge-triggered, but ack
  * doesn't seem to work (CPLD Rev 2).  Instead, the screaming one
- * is disabled and its counterpart enabled.  The 500ms timeout is
- * because the carddetect isn't debounced in hardware.
+ * is disabled and its counterpart enabled.  The 200ms timeout is
+ * because the carddetect usually triggers twice, after debounce.
  */
 static irqreturn_t db1200_mmc_cd(int irq, void *ptr)
 {
-        void(*mmc_cd)(struct mmc_host *, unsigned long);
+        disable_irq_nosync(irq);
+        return IRQ_WAKE_THREAD;
+}
 
-        if (irq == DB1200_SD0_INSERT_INT) {
-                disable_irq_nosync(DB1200_SD0_INSERT_INT);
-                enable_irq(DB1200_SD0_EJECT_INT);
-        } else {
-                disable_irq_nosync(DB1200_SD0_EJECT_INT);
-                enable_irq(DB1200_SD0_INSERT_INT);
-        }
+static irqreturn_t db1200_mmc_cdfn(int irq, void *ptr)
+{
+        void (*mmc_cd)(struct mmc_host *, unsigned long);
 
         /* link against CONFIG_MMC=m */
         mmc_cd = symbol_get(mmc_detect_change);
         if (mmc_cd) {
-                mmc_cd(ptr, msecs_to_jiffies(500));
+                mmc_cd(ptr, msecs_to_jiffies(200));
                 symbol_put(mmc_detect_change);
         }
 
+        msleep(100);    /* debounce */
+        if (irq == DB1200_SD0_INSERT_INT)
+                enable_irq(DB1200_SD0_EJECT_INT);
+        else
+                enable_irq(DB1200_SD0_INSERT_INT);
+
         return IRQ_HANDLED;
 }
 
@@ -374,13 +378,13 @@ static int db1200_mmc_cd_setup(void *mmc_host, int en)
         int ret;
 
         if (en) {
-                ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
-                                  0, "sd_insert", mmc_host);
+                ret = request_threaded_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
+                                db1200_mmc_cdfn, 0, "sd_insert", mmc_host);
                 if (ret)
                         goto out;
 
-                ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
-                                  0, "sd_eject", mmc_host);
+                ret = request_threaded_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
+                                db1200_mmc_cdfn, 0, "sd_eject", mmc_host);
                 if (ret) {
                         free_irq(DB1200_SD0_INSERT_INT, mmc_host);
                         goto out;
@@ -436,23 +440,27 @@ static struct led_classdev db1200_mmc_led = {
 
 static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr)
 {
-        void(*mmc_cd)(struct mmc_host *, unsigned long);
+        disable_irq_nosync(irq);
+        return IRQ_WAKE_THREAD;
+}
 
-        if (irq == PB1200_SD1_INSERT_INT) {
-                disable_irq_nosync(PB1200_SD1_INSERT_INT);
-                enable_irq(PB1200_SD1_EJECT_INT);
-        } else {
-                disable_irq_nosync(PB1200_SD1_EJECT_INT);
-                enable_irq(PB1200_SD1_INSERT_INT);
-        }
+static irqreturn_t pb1200_mmc1_cdfn(int irq, void *ptr)
+{
+        void (*mmc_cd)(struct mmc_host *, unsigned long);
 
         /* link against CONFIG_MMC=m */
         mmc_cd = symbol_get(mmc_detect_change);
         if (mmc_cd) {
-                mmc_cd(ptr, msecs_to_jiffies(500));
+                mmc_cd(ptr, msecs_to_jiffies(200));
                 symbol_put(mmc_detect_change);
         }
 
+        msleep(100);    /* debounce */
+        if (irq == PB1200_SD1_INSERT_INT)
+                enable_irq(PB1200_SD1_EJECT_INT);
+        else
+                enable_irq(PB1200_SD1_INSERT_INT);
+
         return IRQ_HANDLED;
 }
 
@@ -461,13 +469,13 @@ static int pb1200_mmc1_cd_setup(void *mmc_host, int en)
         int ret;
 
         if (en) {
-                ret = request_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd, 0,
-                                  "sd1_insert", mmc_host);
+                ret = request_threaded_irq(PB1200_SD1_INSERT_INT, pb1200_mmc1_cd,
+                                pb1200_mmc1_cdfn, 0, "sd1_insert", mmc_host);
                 if (ret)
                         goto out;
 
-                ret = request_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd, 0,
-                                  "sd1_eject", mmc_host);
+                ret = request_threaded_irq(PB1200_SD1_EJECT_INT, pb1200_mmc1_cd,
+                                pb1200_mmc1_cdfn, 0, "sd1_eject", mmc_host);
                 if (ret) {
                         free_irq(PB1200_SD1_INSERT_INT, mmc_host);
                         goto out;
diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c
index 3e7fbdbdb3c4..cd1ae29f95a3 100644
--- a/arch/mips/alchemy/devboards/db1300.c
+++ b/arch/mips/alchemy/devboards/db1300.c
@@ -450,24 +450,27 @@ static struct platform_device db1300_ide_dev = {
 
 static irqreturn_t db1300_mmc_cd(int irq, void *ptr)
 {
-        void(*mmc_cd)(struct mmc_host *, unsigned long);
+        disable_irq_nosync(irq);
+        return IRQ_WAKE_THREAD;
+}
 
-        /* disable the one currently screaming. No other way to shut it up */
-        if (irq == DB1300_SD1_INSERT_INT) {
-                disable_irq_nosync(DB1300_SD1_INSERT_INT);
-                enable_irq(DB1300_SD1_EJECT_INT);
-        } else {
-                disable_irq_nosync(DB1300_SD1_EJECT_INT);
-                enable_irq(DB1300_SD1_INSERT_INT);
-        }
+static irqreturn_t db1300_mmc_cdfn(int irq, void *ptr)
+{
+        void (*mmc_cd)(struct mmc_host *, unsigned long);
 
         /* link against CONFIG_MMC=m.  We can only be called once MMC core has
          * initialized the controller, so symbol_get() should always succeed.
          */
         mmc_cd = symbol_get(mmc_detect_change);
-        mmc_cd(ptr, msecs_to_jiffies(500));
+        mmc_cd(ptr, msecs_to_jiffies(200));
         symbol_put(mmc_detect_change);
 
+        msleep(100);    /* debounce */
+        if (irq == DB1300_SD1_INSERT_INT)
+                enable_irq(DB1300_SD1_EJECT_INT);
+        else
+                enable_irq(DB1300_SD1_INSERT_INT);
+
         return IRQ_HANDLED;
 }
 
@@ -487,13 +490,13 @@ static int db1300_mmc_cd_setup(void *mmc_host, int en)
         int ret;
 
         if (en) {
-                ret = request_irq(DB1300_SD1_INSERT_INT, db1300_mmc_cd, 0,
-                                  "sd_insert", mmc_host);
+                ret = request_threaded_irq(DB1300_SD1_INSERT_INT, db1300_mmc_cd,
+                                db1300_mmc_cdfn, 0, "sd_insert", mmc_host);
                 if (ret)
                         goto out;
 
-                ret = request_irq(DB1300_SD1_EJECT_INT, db1300_mmc_cd, 0,
-                                  "sd_eject", mmc_host);
+                ret = request_threaded_irq(DB1300_SD1_EJECT_INT, db1300_mmc_cd,
+                                db1300_mmc_cdfn, 0, "sd_eject", mmc_host);
                 if (ret) {
                         free_irq(DB1300_SD1_INSERT_INT, mmc_host);
                         goto out;
diff --git a/arch/mips/alchemy/devboards/db1xxx.c b/arch/mips/alchemy/devboards/db1xxx.c
index 2d47f951121a..c9ad28995cd2 100644
--- a/arch/mips/alchemy/devboards/db1xxx.c
+++ b/arch/mips/alchemy/devboards/db1xxx.c
@@ -2,6 +2,7 @@
  * Alchemy DB/PB1xxx board support.
  */
 
+#include <asm/prom.h>
 #include <asm/mach-au1x00/au1000.h>
 #include <asm/mach-db1x00/bcsr.h>
 
@@ -97,6 +98,7 @@ arch_initcall(db1xxx_arch_init);
 
 static int __init db1xxx_dev_init(void)
 {
+        mips_set_machine_name(board_type_str());
         switch (BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI))) {
         case BCSR_WHOAMI_DB1000:
         case BCSR_WHOAMI_DB1500:
diff --git a/arch/mips/ar7/clock.c b/arch/mips/ar7/clock.c
index dda422a0f36c..0137656107a9 100644
--- a/arch/mips/ar7/clock.c
+++ b/arch/mips/ar7/clock.c
@@ -430,6 +430,9 @@ EXPORT_SYMBOL(clk_disable);
 
 unsigned long clk_get_rate(struct clk *clk)
 {
+        if (!clk)
+                return 0;
+
         return clk->rate;
 }
 EXPORT_SYMBOL(clk_get_rate);
diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index fa845953f736..6b1000b6a6a6 100644
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -487,17 +487,16 @@ static void __init ath79_clocks_init_dt_ng(struct device_node *np)
 {
         struct clk *ref_clk;
         void __iomem *pll_base;
-        const char *dnfn = of_node_full_name(np);
 
         ref_clk = of_clk_get(np, 0);
         if (IS_ERR(ref_clk)) {
-                pr_err("%s: of_clk_get failed\n", dnfn);
+                pr_err("%pOF: of_clk_get failed\n", np);
                 goto err;
         }
 
         pll_base = of_iomap(np, 0);
         if (!pll_base) {
-                pr_err("%s: can't map pll registers\n", dnfn);
+                pr_err("%pOF: can't map pll registers\n", np);
                 goto err_clk;
         }
 
@@ -506,12 +505,12 @@ static void __init ath79_clocks_init_dt_ng(struct device_node *np)
         else if (of_device_is_compatible(np, "qca,ar9330-pll"))
                 ar9330_clk_init(ref_clk, pll_base);
         else {
-                pr_err("%s: could not find any appropriate clk_init()\n", dnfn);
+                pr_err("%pOF: could not find any appropriate clk_init()\n", np);
                 goto err_iounmap;
         }
 
         if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
-                pr_err("%s: could not register clk provider\n", dnfn);
+                pr_err("%pOF: could not register clk provider\n", np);
                 goto err_iounmap;
         }
 
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index 73626040e4d6..19577f771c1f 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -339,6 +339,9 @@ EXPORT_SYMBOL(clk_disable);
 
 unsigned long clk_get_rate(struct clk *clk)
 {
+        if (!clk)
+                return 0;
+
         return clk->rate;
 }
 
diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
index 145b5ce8eb7e..1bd5c4f00d19 100644
--- a/arch/mips/boot/Makefile
+++ b/arch/mips/boot/Makefile
@@ -118,6 +118,12 @@ ifeq ($(ADDR_BITS),64)
         itb_addr_cells = 2
 endif
 
+quiet_cmd_its_cat = CAT     $@
+      cmd_its_cat = cat $^ >$@
+
+$(obj)/vmlinux.its.S: $(addprefix $(srctree)/arch/mips/$(PLATFORM)/,$(ITS_INPUTS))
+        $(call if_changed,its_cat)
+
 quiet_cmd_cpp_its_S = ITS     $@
       cmd_cpp_its_S = $(CPP) $(cpp_flags) -P -C -o $@ $< \
                         -DKERNEL_NAME="\"Linux $(KERNELRELEASE)\"" \
@@ -128,19 +134,19 @@ quiet_cmd_cpp_its_S = ITS     $@
                         -DADDR_BITS=$(ADDR_BITS) \
                         -DADDR_CELLS=$(itb_addr_cells)
 
-$(obj)/vmlinux.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S $(VMLINUX) FORCE
+$(obj)/vmlinux.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
         $(call if_changed_dep,cpp_its_S,none,vmlinux.bin)
 
-$(obj)/vmlinux.gz.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S $(VMLINUX) FORCE
+$(obj)/vmlinux.gz.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
         $(call if_changed_dep,cpp_its_S,gzip,vmlinux.bin.gz)
 
-$(obj)/vmlinux.bz2.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S $(VMLINUX)  FORCE
+$(obj)/vmlinux.bz2.its: $(obj)/vmlinux.its.S $(VMLINUX)  FORCE
         $(call if_changed_dep,cpp_its_S,bzip2,vmlinux.bin.bz2)
 
-$(obj)/vmlinux.lzma.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S $(VMLINUX) FORCE
+$(obj)/vmlinux.lzma.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
         $(call if_changed_dep,cpp_its_S,lzma,vmlinux.bin.lzma)
 
-$(obj)/vmlinux.lzo.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S $(VMLINUX) FORCE
+$(obj)/vmlinux.lzo.its: $(obj)/vmlinux.its.S $(VMLINUX) FORCE
         $(call if_changed_dep,cpp_its_S,lzo,vmlinux.bin.lzo)
 
 quiet_cmd_itb-image = ITB     $@
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index b9db49203e0c..cbac26ce063e 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -5,6 +5,7 @@ dts-dirs	+= ingenic
 dts-dirs        += lantiq
 dts-dirs        += mti
 dts-dirs        += netlogic
+dts-dirs        += ni
 dts-dirs        += pic32
 dts-dirs        += qca
 dts-dirs        += ralink
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index fd138d9978c1..6c381844929c 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -1,6 +1,7 @@
 /dts-v1/;
 
 #include "jz4780.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         compatible = "img,ci20", "ingenic,jz4780";
@@ -21,6 +22,13 @@
                 reg = <0x0 0x10000000
                        0x30000000 0x30000000>;
         };
+
+        eth0_power: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "eth0_power";
+                gpio = <&gpb 25 GPIO_ACTIVE_LOW>;
+                enable-active-high;
+        };
 };
 
 &ext {
@@ -123,6 +131,29 @@
                         };
                 };
         };
+
+        dm9000@6 {
+                compatible = "davicom,dm9000";
+                davicom,no-eeprom;
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&pins_nemc_cs6>;
+
+                reg = <6 0 1   /* addr */
+                       6 2 1>; /* data */
+
+                ingenic,nemc-tAS = <15>;
+                ingenic,nemc-tAH = <10>;
+                ingenic,nemc-tBP = <20>;
+                ingenic,nemc-tAW = <50>;
+                ingenic,nemc-tSTRV = <100>;
+
+                reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>;
+                vcc-supply = <&eth0_power>;
+
+                interrupt-parent = <&gpe>;
+                interrupts = <19 4>;
+        };
 };
 
 &bch {
@@ -165,4 +196,10 @@
                 groups = "nemc-cs1";
                 bias-disable;
         };
+
+        pins_nemc_cs6: nemc-cs6 {
+                function = "nemc-cs6";
+                groups = "nemc-cs6";
+                bias-disable;
+        };
 };
diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi
index 4853ef67b3ab..e906134ecaef 100644
--- a/arch/mips/boot/dts/ingenic/jz4780.dtsi
+++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi
@@ -44,6 +44,17 @@
                 #clock-cells = <1>;
         };
 
+        rtc_dev: rtc@10003000 {
+                compatible = "ingenic,jz4780-rtc";
+                reg = <0x10003000 0x4c>;
+
+                interrupt-parent = <&intc>;
+                interrupts = <32>;
+
+                clocks = <&cgu JZ4780_CLK_RTCLK>;
+                clock-names = "rtc";
+        };
+
         pinctrl: pin-controller@10010000 {
                 compatible = "ingenic,jz4780-pinctrl";
                 reg = <0x10010000 0x600>;
diff --git a/arch/mips/boot/dts/ni/169445.dts b/arch/mips/boot/dts/ni/169445.dts
new file mode 100644
index 000000000000..5389ef46c480
--- /dev/null
+++ b/arch/mips/boot/dts/ni/169445.dts
@@ -0,0 +1,100 @@
+/dts-v1/;
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "ni,169445";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "mti,mips14KEc";
+                        clocks = <&baseclk>;
+                        reg = <0>;
+                };
+        };
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x10000000>;
+        };
+
+        baseclk: baseclock {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <50000000>;
+        };
+
+        cpu_intc: interrupt-controller {
+                #address-cells = <0>;
+                compatible = "mti,cpu-interrupt-controller";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+
+        ahb@1f300000 {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0x0 0x1f300000 0x80FFF>;
+
+                gpio1: gpio@10 {
+                        compatible = "ni,169445-nand-gpio";
+                        reg = <0x10 0x4>;
+                        reg-names = "dat";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpio2: gpio@14 {
+                        compatible = "ni,169445-nand-gpio";
+                        reg = <0x14 0x4>;
+                        reg-names = "dat";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        no-output;
+                };
+
+                nand@0 {
+                        compatible = "gpio-control-nand";
+                        nand-on-flash-bbt;
+                        nand-ecc-mode = "soft_bch";
+                        nand-ecc-step-size = <512>;
+                        nand-ecc-strength = <4>;
+                        reg = <0x0 4>;
+                        gpios = <&gpio2 0 0>, /* rdy */
+                                <&gpio1 1 0>, /* nce */
+                                <&gpio1 2 0>, /* ale */
+                                <&gpio1 3 0>, /* cle */
+                                <&gpio1 4 0>; /* nwp */
+                };
+
+                serial@80000 {
+                        compatible = "ns16550a";
+                        reg = <0x80000 0x1000>;
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <6>;
+                        clocks = <&baseclk>;
+                        reg-shift = <0>;
+                };
+
+                ethernet@40000 {
+                        compatible = "snps,dwmac-4.10a";
+                        interrupt-parent = <&cpu_intc>;
+                        interrupts = <5>;
+                        interrupt-names = "macirq";
+                        reg = <0x40000 0x2000>;
+                        clock-names = "stmmaceth", "pclk";
+                        clocks = <&baseclk>, <&baseclk>;
+
+                        phy-mode = "rgmii";
+
+                        fixed-link {
+                                speed = <1000>;
+                                full-duplex;
+                        };
+                };
+        };
+};
diff --git a/arch/mips/boot/dts/ni/Makefile b/arch/mips/boot/dts/ni/Makefile
new file mode 100644
index 000000000000..66cfdffc51c2
--- /dev/null
+++ b/arch/mips/boot/dts/ni/Makefile
@@ -0,0 +1,7 @@
+dtb-$(CONFIG_FIT_IMAGE_FDT_NI169445)    += 169445.dtb
+
+# Force kbuild to make empty built-in.o if necessary
+obj-                                    += dummy.o
+
+always                                  := $(dtb-y)
+clean-files                             := *.dtb *.dtb.S
diff --git a/arch/mips/boot/dts/ralink/Makefile b/arch/mips/boot/dts/ralink/Makefile
index 2a7225954bf6..55e2937b61f3 100644
--- a/arch/mips/boot/dts/ralink/Makefile
+++ b/arch/mips/boot/dts/ralink/Makefile
@@ -2,6 +2,8 @@ dtb-$(CONFIG_DTB_RT2880_EVAL)	+= rt2880_eval.dtb
 dtb-$(CONFIG_DTB_RT305X_EVAL)   += rt3052_eval.dtb
 dtb-$(CONFIG_DTB_RT3883_EVAL)   += rt3883_eval.dtb
 dtb-$(CONFIG_DTB_MT7620A_EVAL)  += mt7620a_eval.dtb
+dtb-$(CONFIG_DTB_OMEGA2P)       += omega2p.dtb
+dtb-$(CONFIG_DTB_VOCORE2)       += vocore2.dtb
 
 obj-y                           += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
 
diff --git a/arch/mips/boot/dts/ralink/mt7628a.dtsi b/arch/mips/boot/dts/ralink/mt7628a.dtsi
new file mode 100644
index 000000000000..9ff7e8faaecc
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/mt7628a.dtsi
@@ -0,0 +1,126 @@
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        compatible = "ralink,mt7628a-soc";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "mti,mips24KEc";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+        };
+
+        resetc: reset-controller {
+                compatible = "ralink,rt2880-reset";
+                #reset-cells = <1>;
+        };
+
+        cpuintc: interrupt-controller {
+                #address-cells = <0>;
+                #interrupt-cells = <1>;
+                interrupt-controller;
+                compatible = "mti,cpu-interrupt-controller";
+        };
+
+        palmbus@10000000 {
+                compatible = "palmbus";
+                reg = <0x10000000 0x200000>;
+                ranges = <0x0 0x10000000 0x1FFFFF>;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                sysc: system-controller@0 {
+                        compatible = "ralink,mt7620a-sysc", "syscon";
+                        reg = <0x0 0x100>;
+                };
+
+                intc: interrupt-controller@200 {
+                        compatible = "ralink,rt2880-intc";
+                        reg = <0x200 0x100>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+
+                        resets = <&resetc 9>;
+                        reset-names = "intc";
+
+                        interrupt-parent = <&cpuintc>;
+                        interrupts = <2>;
+
+                        ralink,intc-registers = <0x9c 0xa0
+                                                 0x6c 0xa4
+                                                 0x80 0x78>;
+                };
+
+                memory-controller@300 {
+                        compatible = "ralink,mt7620a-memc";
+                        reg = <0x300 0x100>;
+                };
+
+                uart0: uartlite@c00 {
+                        compatible = "ns16550a";
+                        reg = <0xc00 0x100>;
+
+                        resets = <&resetc 12>;
+                        reset-names = "uart0";
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <20>;
+
+                        reg-shift = <2>;
+                };
+
+                uart1: uart1@d00 {
+                        compatible = "ns16550a";
+                        reg = <0xd00 0x100>;
+
+                        resets = <&resetc 19>;
+                        reset-names = "uart1";
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <21>;
+
+                        reg-shift = <2>;
+                };
+
+                uart2: uart2@e00 {
+                        compatible = "ns16550a";
+                        reg = <0xe00 0x100>;
+
+                        resets = <&resetc 20>;
+                        reset-names = "uart2";
+
+                        interrupt-parent = <&intc>;
+                        interrupts = <22>;
+
+                        reg-shift = <2>;
+                };
+        };
+
+        usb_phy: usb-phy@10120000 {
+                compatible = "mediatek,mt7628-usbphy";
+                reg = <0x10120000 0x1000>;
+
+                #phy-cells = <0>;
+
+                ralink,sysctl = <&sysc>;
+                resets = <&resetc 22 &resetc 25>;
+                reset-names = "host", "device";
+        };
+
+        ehci@101c0000 {
+                compatible = "generic-ehci";
+                reg = <0x101c0000 0x1000>;
+
+                phys = <&usb_phy>;
+                phy-names = "usb";
+
+                interrupt-parent = <&intc>;
+                interrupts = <18>;
+        };
+};
diff --git a/arch/mips/boot/dts/ralink/omega2p.dts b/arch/mips/boot/dts/ralink/omega2p.dts
new file mode 100644
index 000000000000..5884fd48f59a
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/omega2p.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+/include/ "mt7628a.dtsi"
+
+/ {
+        compatible = "onion,omega2+", "ralink,mt7688a-soc", "ralink,mt7628a-soc";
+        model = "Onion Omega2+";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x8000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+};
diff --git a/arch/mips/boot/dts/ralink/vocore2.dts b/arch/mips/boot/dts/ralink/vocore2.dts
new file mode 100644
index 000000000000..fa8a5f8f236a
--- /dev/null
+++ b/arch/mips/boot/dts/ralink/vocore2.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+#include "mt7628a.dtsi"
+
+/ {
+        compatible = "vocore,vocore2", "ralink,mt7628a-soc";
+        model = "VoCore2";
+
+        memory@0 {
+                device_type = "memory";
+                reg = <0x0 0x8000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS2,115200";
+                stdout-path = &uart2;
+        };
+};
diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile
index b6d6e841a984..50b427879465 100644
--- a/arch/mips/cavium-octeon/executive/Makefile
+++ b/arch/mips/cavium-octeon/executive/Makefile
@@ -16,4 +16,4 @@ obj-y += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \
         cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \
         cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o
 
-obj-y += cvmx-helper-errata.o cvmx-helper-jtag.o
+obj-y += cvmx-helper-errata.o cvmx-helper-jtag.o cvmx-boot-vector.o
diff --git a/arch/mips/cavium-octeon/executive/cvmx-boot-vector.c b/arch/mips/cavium-octeon/executive/cvmx-boot-vector.c
new file mode 100644
index 000000000000..b7019d21808e
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-boot-vector.c
@@ -0,0 +1,167 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004-2017 Cavium, Inc.
+ */
+
+
+/*
+  We install this program at the bootvector:
+------------------------------------
+        .set noreorder
+        .set nomacro
+        .set noat
+reset_vector:
+        dmtc0   $k0, $31, 0     # Save $k0 to DESAVE
+        dmtc0   $k1, $31, 3     # Save $k1 to KScratch2
+
+        mfc0    $k0, $12, 0     # Status
+        mfc0    $k1, $15, 1     # Ebase
+
+        ori     $k0, 0x84       # Enable 64-bit addressing, set
+                                # ERL (should already be set)
+        andi    $k1, 0x3ff      # mask out core ID
+
+        mtc0    $k0, $12, 0     # Status
+        sll     $k1, 5
+
+        lui     $k0, 0xbfc0
+        cache   17, 0($0)       # Core-14345, clear L1 Dcache virtual
+                                # tags if the core hit an NMI
+
+        ld      $k0, 0x78($k0)  # k0 <- (bfc00078) pointer to the reset vector
+        synci   0($0)           # Invalidate ICache to get coherent
+                                # view of target code.
+
+        daddu   $k0, $k0, $k1
+        nop
+
+        ld      $k0, 0($k0)     # k0 <- core specific target address
+        dmfc0   $k1, $31, 3     # Restore $k1 from KScratch2
+
+        beqz    $k0, wait_loop  # Spin in wait loop
+        nop
+
+        jr      $k0
+        nop
+
+        nop                     # NOPs needed here to fill delay slots
+        nop                     # on endian reversal of previous instructions
+
+wait_loop:
+        wait
+        nop
+
+        b       wait_loop
+        nop
+
+        nop
+        nop
+------------------------------------
+
+0000000000000000 <reset_vector>:
+   0:   40baf800        dmtc0   k0,c0_desave
+   4:   40bbf803        dmtc0   k1,c0_kscratch2
+
+   8:   401a6000        mfc0    k0,c0_status
+   c:   401b7801        mfc0    k1,c0_ebase
+
+  10:   375a0084        ori     k0,k0,0x84
+  14:   337b03ff        andi    k1,k1,0x3ff
+
+  18:   409a6000        mtc0    k0,c0_status
+  1c:   001bd940        sll     k1,k1,0x5
+
+  20:   3c1abfc0        lui     k0,0xbfc0
+  24:   bc110000        cache   0x11,0(zero)
+
+  28:   df5a0078        ld      k0,120(k0)
+  2c:   041f0000        synci   0(zero)
+
+  30:   035bd02d        daddu   k0,k0,k1
+  34:   00000000        nop
+
+  38:   df5a0000        ld      k0,0(k0)
+  3c:   403bf803        dmfc0   k1,c0_kscratch2
+
+  40:   13400005        beqz    k0,58 <wait_loop>
+  44:   00000000        nop
+
+  48:   03400008        jr      k0
+  4c:   00000000        nop
+
+  50:   00000000        nop
+  54:   00000000        nop
+
+0000000000000058 <wait_loop>:
+  58:   42000020        wait
+  5c:   00000000        nop
+
+  60:   1000fffd        b       58 <wait_loop>
+  64:   00000000        nop
+
+  68:   00000000        nop
+  6c:   00000000        nop
+
+ */
+
+#include <asm/octeon/cvmx-boot-vector.h>
+
+static unsigned long long _cvmx_bootvector_data[16] = {
+        0x40baf80040bbf803ull,  /* patch low order 8-bits if no KScratch*/
+        0x401a6000401b7801ull,
+        0x375a0084337b03ffull,
+        0x409a6000001bd940ull,
+        0x3c1abfc0bc110000ull,
+        0xdf5a0078041f0000ull,
+        0x035bd02d00000000ull,
+        0xdf5a0000403bf803ull,  /* patch low order 8-bits if no KScratch*/
+        0x1340000500000000ull,
+        0x0340000800000000ull,
+        0x0000000000000000ull,
+        0x4200002000000000ull,
+        0x1000fffd00000000ull,
+        0x0000000000000000ull,
+        OCTEON_BOOT_MOVEABLE_MAGIC1,
+        0 /* To be filled in with address of vector block*/
+};
+
+/* 2^10 CPUs */
+#define VECTOR_TABLE_SIZE (1024 * sizeof(struct cvmx_boot_vector_element))
+
+static void cvmx_boot_vector_init(void *mem)
+{
+        uint64_t kseg0_mem;
+        int i;
+
+        memset(mem, 0, VECTOR_TABLE_SIZE);
+        kseg0_mem = cvmx_ptr_to_phys(mem) | 0x8000000000000000ull;
+
+        for (i = 0; i < 15; i++) {
+                uint64_t v = _cvmx_bootvector_data[i];
+
+                if (OCTEON_IS_OCTEON1PLUS() && (i == 0 || i == 7))
+                        v &= 0xffffffff00000000ull; /* KScratch not availble. */
+                cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8);
+                cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, v);
+        }
+        cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, 15 * 8);
+        cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, kseg0_mem);
+        cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000);
+}
+
+/**
+ * Get a pointer to the per-core table of reset vector pointers
+ *
+ */
+struct cvmx_boot_vector_element *cvmx_boot_vector_get(void)
+{
+        struct cvmx_boot_vector_element *ret;
+
+        ret = cvmx_bootmem_alloc_named_range_once(VECTOR_TABLE_SIZE, 0,
+                (1ull << 32) - 1, 8, "__boot_vector1__", cvmx_boot_vector_init);
+        return ret;
+}
+EXPORT_SYMBOL(cvmx_boot_vector_get);
diff --git a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
index 8d54d774933c..94d97ebfa036 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
@@ -44,6 +44,55 @@ static struct cvmx_bootmem_desc *cvmx_bootmem_desc;
 
 /* See header file for descriptions of functions */
 
+/**
+ * This macro returns the size of a member of a structure.
+ * Logically it is the same as "sizeof(s::field)" in C++, but
+ * C lacks the "::" operator.
+ */
+#define SIZEOF_FIELD(s, field) sizeof(((s *)NULL)->field)
+
+/**
+ * This macro returns a member of the
+ * cvmx_bootmem_named_block_desc_t structure. These members can't
+ * be directly addressed as they might be in memory not directly
+ * reachable. In the case where bootmem is compiled with
+ * LINUX_HOST, the structure itself might be located on a remote
+ * Octeon. The argument "field" is the member name of the
+ * cvmx_bootmem_named_block_desc_t to read. Regardless of the type
+ * of the field, the return type is always a uint64_t. The "addr"
+ * parameter is the physical address of the structure.
+ */
+#define CVMX_BOOTMEM_NAMED_GET_FIELD(addr, field)                       \
+        __cvmx_bootmem_desc_get(addr,                                   \
+                offsetof(struct cvmx_bootmem_named_block_desc, field),  \
+                SIZEOF_FIELD(struct cvmx_bootmem_named_block_desc, field))
+
+/**
+ * This function is the implementation of the get macros defined
+ * for individual structure members. The argument are generated
+ * by the macros inorder to read only the needed memory.
+ *
+ * @param base   64bit physical address of the complete structure
+ * @param offset Offset from the beginning of the structure to the member being
+ *               accessed.
+ * @param size   Size of the structure member.
+ *
+ * @return Value of the structure member promoted into a uint64_t.
+ */
+static inline uint64_t __cvmx_bootmem_desc_get(uint64_t base, int offset,
+                                               int size)
+{
+        base = (1ull << 63) | (base + offset);
+        switch (size) {
+        case 4:
+                return cvmx_read64_uint32(base);
+        case 8:
+                return cvmx_read64_uint64(base);
+        default:
+                return 0;
+        }
+}
+
 /*
  * Wrapper functions are provided for reading/writing the size and
  * next block values as these may not be directly addressible (in 32
@@ -98,6 +147,42 @@ void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment)
         return cvmx_bootmem_alloc_range(size, alignment, 0, 0);
 }
 
+void *cvmx_bootmem_alloc_named_range_once(uint64_t size, uint64_t min_addr,
+                                          uint64_t max_addr, uint64_t align,
+                                          char *name,
+                                          void (*init) (void *))
+{
+        int64_t addr;
+        void *ptr;
+        uint64_t named_block_desc_addr;
+
+        named_block_desc_addr = (uint64_t)
+                cvmx_bootmem_phy_named_block_find(name,
+                                                  (uint32_t)CVMX_BOOTMEM_FLAG_NO_LOCKING);
+
+        if (named_block_desc_addr) {
+                addr = CVMX_BOOTMEM_NAMED_GET_FIELD(named_block_desc_addr,
+                                                    base_addr);
+                return cvmx_phys_to_ptr(addr);
+        }
+
+        addr = cvmx_bootmem_phy_named_block_alloc(size, min_addr, max_addr,
+                                                  align, name,
+                                                  (uint32_t)CVMX_BOOTMEM_FLAG_NO_LOCKING);
+
+        if (addr < 0)
+                return NULL;
+        ptr = cvmx_phys_to_ptr(addr);
+
+        if (init)
+                init(ptr);
+        else
+                memset(ptr, 0, size);
+
+        return ptr;
+}
+EXPORT_SYMBOL(cvmx_bootmem_alloc_named_range_once);
+
 void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
                                      uint64_t max_addr, uint64_t align,
                                      char *name)
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index c1eb1ff7c800..5b3a3f6a9ad3 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -2963,3 +2963,12 @@ void octeon_fixup_irqs(void)
 }
 
 #endif /* CONFIG_HOTPLUG_CPU */
+
+struct irq_domain *octeon_irq_get_block_domain(int node, uint8_t block)
+{
+        struct octeon_ciu3_info *ciu3_info;
+
+        ciu3_info = octeon_ciu3_info_per_node[node & CVMX_NODE_MASK];
+        return ciu3_info->domain[block];
+}
+EXPORT_SYMBOL(octeon_irq_get_block_domain);
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index 3de786545ded..75e7c8625659 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -205,7 +205,7 @@ int plat_post_relocation(long offset)
  * Firmware CPU startup hook
  *
  */
-static void octeon_boot_secondary(int cpu, struct task_struct *idle)
+static int octeon_boot_secondary(int cpu, struct task_struct *idle)
 {
         int count;
 
@@ -223,8 +223,12 @@ static void octeon_boot_secondary(int cpu, struct task_struct *idle)
                 udelay(1);
                 count--;
         }
-        if (count == 0)
+        if (count == 0) {
                 pr_err("Secondary boot timeout\n");
+                return -ETIMEDOUT;
+        }
+
+        return 0;
 }
 
 /**
@@ -408,7 +412,7 @@ late_initcall(register_cavium_notifier);
 
 #endif  /* CONFIG_HOTPLUG_CPU */
 
-struct plat_smp_ops octeon_smp_ops = {
+const struct plat_smp_ops octeon_smp_ops = {
         .send_ipi_single        = octeon_send_ipi_single,
         .send_ipi_mask          = octeon_send_ipi_mask,
         .init_secondary         = octeon_init_secondary,
@@ -485,7 +489,7 @@ static void octeon_78xx_send_ipi_mask(const struct cpumask *mask,
                 octeon_78xx_send_ipi_single(cpu, action);
 }
 
-static struct plat_smp_ops octeon_78xx_smp_ops = {
+static const struct plat_smp_ops octeon_78xx_smp_ops = {
         .send_ipi_single        = octeon_78xx_send_ipi_single,
         .send_ipi_mask          = octeon_78xx_send_ipi_mask,
         .init_secondary         = octeon_init_secondary,
@@ -501,7 +505,7 @@ static struct plat_smp_ops octeon_78xx_smp_ops = {
 
 void __init octeon_setup_smp(void)
 {
-        struct plat_smp_ops *ops;
+        const struct plat_smp_ops *ops;
 
         if (octeon_has_feature(OCTEON_FEATURE_CIU3))
                 ops = &octeon_78xx_smp_ops;
diff --git a/arch/mips/configs/cavium_octeon_defconfig b/arch/mips/configs/cavium_octeon_defconfig
index e5b18f1a31a0..490b12af103c 100644
--- a/arch/mips/configs/cavium_octeon_defconfig
+++ b/arch/mips/configs/cavium_octeon_defconfig
@@ -60,11 +60,8 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
 CONFIG_SATA_AHCI=y
 CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_AHCI_OCTEON=y
 CONFIG_PATA_OCTEON_CF=y
-CONFIG_SATA_SIL=y
 CONFIG_NETDEVICES=y
-CONFIG_MII=y
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_NET_VENDOR_ADAPTEC is not set
 # CONFIG_NET_VENDOR_ALTEON is not set
@@ -121,22 +118,30 @@ CONFIG_SPI=y
 CONFIG_SPI_OCTEON=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
-CONFIG_USB=m
-CONFIG_USB_EHCI_HCD=m
-CONFIG_USB_EHCI_HCD_PLATFORM=m
-CONFIG_USB_OHCI_HCD=m
-CONFIG_USB_OHCI_HCD_PLATFORM=m
+CONFIG_USB=y
+# CONFIG_USB_PCI is not set
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_DWC3=y
 CONFIG_MMC=y
 # CONFIG_PWRSEQ_EMMC is not set
 # CONFIG_PWRSEQ_SIMPLE is not set
-# CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_CAVIUM_OCTEON=y
+CONFIG_EDAC=y
+CONFIG_EDAC_OCTEON_PC=y
+CONFIG_EDAC_OCTEON_L2C=y
+CONFIG_EDAC_OCTEON_LMC=y
+CONFIG_EDAC_OCTEON_PCI=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_DS1307=y
 CONFIG_STAGING=y
 CONFIG_OCTEON_ETHERNET=y
-CONFIG_OCTEON_USB=m
 # CONFIG_IOMMU_SUPPORT is not set
+CONFIG_RAS=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_EXT4_FS_SECURITY=y
diff --git a/arch/mips/configs/ci20_defconfig b/arch/mips/configs/ci20_defconfig
index b42cfa7865f9..5ea3104a3aca 100644
--- a/arch/mips/configs/ci20_defconfig
+++ b/arch/mips/configs/ci20_defconfig
@@ -91,6 +91,7 @@ CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_I2C=y
 CONFIG_I2C_JZ4780=y
 CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_INGENIC=y
 # CONFIG_HWMON is not set
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_DEBUG=y
@@ -99,6 +100,8 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
 # CONFIG_HID is not set
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_JZ4740=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_MEMORY=y
 # CONFIG_DNOTIFY is not set
diff --git a/arch/mips/configs/generic/board-ni169445.config b/arch/mips/configs/generic/board-ni169445.config
new file mode 100644
index 000000000000..f72223b366ca
--- /dev/null
+++ b/arch/mips/configs/generic/board-ni169445.config
@@ -0,0 +1,30 @@
+# require CONFIG_CPU_MIPS32_R2=y
+# require CONFIG_CPU_LITTLE_ENDIAN=y
+
+CONFIG_FIT_IMAGE_FDT_NI169445=y
+
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CMDLINE_PARTS=y
+
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_BCH=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_GPIO=y
+CONFIG_MTD_NAND_IDS=y
+
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BLOCK=y
+
+CONFIG_NETDEVICES=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_DWMAC_GENERIC=y
diff --git a/arch/mips/configs/generic/board-sead-3.config b/arch/mips/configs/generic/board-sead-3.config
index 3b5e1ac579eb..df49a592dbb5 100644
--- a/arch/mips/configs/generic/board-sead-3.config
+++ b/arch/mips/configs/generic/board-sead-3.config
@@ -1,3 +1,5 @@
+# require CONFIG_32BIT=y
+
 CONFIG_LEGACY_BOARD_SEAD3=y
 
 CONFIG_AUXDISPLAY=y
diff --git a/arch/mips/configs/generic_defconfig b/arch/mips/configs/generic_defconfig
index 91aacf2ef26d..26b1cd5ffbf5 100644
--- a/arch/mips/configs/generic_defconfig
+++ b/arch/mips/configs/generic_defconfig
@@ -3,7 +3,7 @@ CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_MIPS_CPS=y
 CONFIG_CPU_HAS_MSA=y
 CONFIG_HIGHMEM=y
-CONFIG_NR_CPUS=2
+CONFIG_NR_CPUS=16
 CONFIG_MIPS_O32_FP64_SUPPORT=y
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ_IDLE=y
@@ -61,7 +61,6 @@ CONFIG_HID_KENSINGTON=y
 CONFIG_HID_LOGITECH=y
 CONFIG_HID_MICROSOFT=y
 CONFIG_HID_MONTEREY=y
-# CONFIG_USB_SUPPORT is not set
 # CONFIG_MIPS_PLATFORM_DEVICES is not set
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT4_FS=y
diff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig
index b1911816337c..55438fc9991e 100644
--- a/arch/mips/configs/gpr_defconfig
+++ b/arch/mips/configs/gpr_defconfig
@@ -111,12 +111,8 @@ CONFIG_ATALK=m
 CONFIG_DEV_APPLETALK=m
 CONFIG_IPDDP=m
 CONFIG_IPDDP_ENCAP=y
-CONFIG_IPDDP_DECAP=y
 CONFIG_X25=m
 CONFIG_LAPB=m
-CONFIG_ECONET=m
-CONFIG_ECONET_AUNUDP=y
-CONFIG_ECONET_NATIVE=y
 CONFIG_WAN_ROUTER=m
 CONFIG_NET_SCHED=y
 CONFIG_NET_SCH_CBQ=m
diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig
index 1ec8ed8d05d1..02be95c1b712 100644
--- a/arch/mips/configs/lemote2f_defconfig
+++ b/arch/mips/configs/lemote2f_defconfig
@@ -37,7 +37,6 @@ CONFIG_PM=y
 CONFIG_HIBERNATION=y
 CONFIG_PM_STD_PARTITION="/dev/hda3"
 CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEBUG=y
 CONFIG_CPU_FREQ_STAT=y
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_FREQ_GOV_POWERSAVE=m
diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig
index 078ecac071ab..396408404487 100644
--- a/arch/mips/configs/malta_defconfig
+++ b/arch/mips/configs/malta_defconfig
@@ -2,7 +2,6 @@ CONFIG_MIPS_MALTA=y
 CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_CPU_MIPS32_R2=y
 CONFIG_PAGE_SIZE_16KB=y
-CONFIG_MIPS_MT_SMP=y
 CONFIG_NR_CPUS=8
 CONFIG_HZ_100=y
 CONFIG_SYSVIPC=y
diff --git a/arch/mips/configs/malta_kvm_defconfig b/arch/mips/configs/malta_kvm_defconfig
index 80ecd94ed126..5691673a3327 100644
--- a/arch/mips/configs/malta_kvm_defconfig
+++ b/arch/mips/configs/malta_kvm_defconfig
@@ -2,7 +2,6 @@ CONFIG_MIPS_MALTA=y
 CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_CPU_MIPS32_R2=y
 CONFIG_PAGE_SIZE_16KB=y
-CONFIG_MIPS_MT_SMP=y
 CONFIG_NR_CPUS=8
 CONFIG_HZ_100=y
 CONFIG_SYSVIPC=y
diff --git a/arch/mips/configs/malta_kvm_guest_defconfig b/arch/mips/configs/malta_kvm_guest_defconfig
index 35ad1f8d1a79..e9cadb37d684 100644
--- a/arch/mips/configs/malta_kvm_guest_defconfig
+++ b/arch/mips/configs/malta_kvm_guest_defconfig
@@ -3,6 +3,7 @@ CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_CPU_MIPS32_R2=y
 CONFIG_KVM_GUEST=y
 CONFIG_PAGE_SIZE_16KB=y
+# CONFIG_MIPS_MT_SMP is not set
 CONFIG_HZ_100=y
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ=y
diff --git a/arch/mips/configs/maltasmvp_defconfig b/arch/mips/configs/maltasmvp_defconfig
index 55b68b981b05..d8c8f5fb8918 100644
--- a/arch/mips/configs/maltasmvp_defconfig
+++ b/arch/mips/configs/maltasmvp_defconfig
@@ -2,7 +2,6 @@ CONFIG_MIPS_MALTA=y
 CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_CPU_MIPS32_R2=y
 CONFIG_PAGE_SIZE_16KB=y
-CONFIG_MIPS_MT_SMP=y
 CONFIG_SCHED_SMT=y
 CONFIG_MIPS_CPS=y
 CONFIG_NR_CPUS=8
diff --git a/arch/mips/configs/maltasmvp_eva_defconfig b/arch/mips/configs/maltasmvp_eva_defconfig
index 5ca590cf1635..04827bc9f87f 100644
--- a/arch/mips/configs/maltasmvp_eva_defconfig
+++ b/arch/mips/configs/maltasmvp_eva_defconfig
@@ -3,7 +3,6 @@ CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_CPU_MIPS32_R2=y
 CONFIG_CPU_MIPS32_3_5_FEATURES=y
 CONFIG_PAGE_SIZE_16KB=y
-CONFIG_MIPS_MT_SMP=y
 CONFIG_SCHED_SMT=y
 CONFIG_MIPS_CPS=y
 CONFIG_NR_CPUS=8
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
index 4011f1869e72..c3d0d0a6e044 100644
--- a/arch/mips/configs/mtx1_defconfig
+++ b/arch/mips/configs/mtx1_defconfig
@@ -146,12 +146,8 @@ CONFIG_ATALK=m
 CONFIG_DEV_APPLETALK=m
 CONFIG_IPDDP=m
 CONFIG_IPDDP_ENCAP=y
-CONFIG_IPDDP_DECAP=y
 CONFIG_X25=m
 CONFIG_LAPB=m
-CONFIG_ECONET=m
-CONFIG_ECONET_AUNUDP=y
-CONFIG_ECONET_NATIVE=y
 CONFIG_WAN_ROUTER=m
 CONFIG_NET_SCHED=y
 CONFIG_NET_SCH_CBQ=m
diff --git a/arch/mips/configs/nlm_xlp_defconfig b/arch/mips/configs/nlm_xlp_defconfig
index 5720ce23e9aa..7357248b3d7a 100644
--- a/arch/mips/configs/nlm_xlp_defconfig
+++ b/arch/mips/configs/nlm_xlp_defconfig
@@ -259,7 +259,6 @@ CONFIG_ATALK=m
 CONFIG_DEV_APPLETALK=m
 CONFIG_IPDDP=m
 CONFIG_IPDDP_ENCAP=y
-CONFIG_IPDDP_DECAP=y
 CONFIG_X25=m
 CONFIG_LAPB=m
 CONFIG_WAN_ROUTER=m
diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig
index fea56c535d92..1e18fd7de209 100644
--- a/arch/mips/configs/nlm_xlr_defconfig
+++ b/arch/mips/configs/nlm_xlr_defconfig
@@ -240,12 +240,8 @@ CONFIG_ATALK=m
 CONFIG_DEV_APPLETALK=m
 CONFIG_IPDDP=m
 CONFIG_IPDDP_ENCAP=y
-CONFIG_IPDDP_DECAP=y
 CONFIG_X25=m
 CONFIG_LAPB=m
-CONFIG_ECONET=m
-CONFIG_ECONET_AUNUDP=y
-CONFIG_ECONET_NATIVE=y
 CONFIG_WAN_ROUTER=m
 CONFIG_PHONET=m
 CONFIG_IEEE802154=m
diff --git a/arch/mips/configs/omega2p_defconfig b/arch/mips/configs/omega2p_defconfig
new file mode 100644
index 000000000000..e2731c3cc7e7
--- /dev/null
+++ b/arch/mips/configs/omega2p_defconfig
@@ -0,0 +1,129 @@
+CONFIG_RALINK=y
+CONFIG_SOC_MT7620=y
+CONFIG_DTB_OMEGA2P=y
+CONFIG_CPU_MIPS32_R2=y
+# CONFIG_COMPACTION is not set
+CONFIG_HZ_100=y
+CONFIG_PREEMPT=y
+# CONFIG_SECCOMP is not set
+CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+CONFIG_MEMCG=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_ALLOW_DEV_COREDUMP is not set
+CONFIG_NETDEVICES=y
+# CONFIG_ETHERNET is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_LEGACY_PTY_COUNT=2
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_MMC=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_MEMORY=y
+CONFIG_PHY_RALINK_USB=y
+# CONFIG_DNOTIFY is not set
+CONFIG_PROC_KCORE=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+CONFIG_CONFIGFS_FS=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_PANIC_TIMEOUT=10
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_STACKTRACE=y
+# CONFIG_FTRACE is not set
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRC16=y
+CONFIG_XZ_DEC=y
diff --git a/arch/mips/configs/pistachio_defconfig b/arch/mips/configs/pistachio_defconfig
index 3598d58aac30..b22a3cf149b6 100644
--- a/arch/mips/configs/pistachio_defconfig
+++ b/arch/mips/configs/pistachio_defconfig
@@ -47,6 +47,8 @@ CONFIG_IP_ADVANCED_ROUTER=y
 CONFIG_IP_MULTIPLE_TABLES=y
 CONFIG_IP_ROUTE_MULTIPATH=y
 CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_MROUTE=y
 CONFIG_IP_PIMSM_V1=y
 CONFIG_IP_PIMSM_V2=y
@@ -292,7 +294,8 @@ CONFIG_SQUASHFS_LZO=y
 CONFIG_PSTORE=y
 CONFIG_PSTORE_CONSOLE=y
 CONFIG_PSTORE_RAM=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=m
 CONFIG_NLS_ASCII=m
diff --git a/arch/mips/configs/vocore2_defconfig b/arch/mips/configs/vocore2_defconfig
new file mode 100644
index 000000000000..9121e4194a63
--- /dev/null
+++ b/arch/mips/configs/vocore2_defconfig
@@ -0,0 +1,129 @@
+CONFIG_RALINK=y
+CONFIG_SOC_MT7620=y
+CONFIG_DTB_VOCORE2=y
+CONFIG_CPU_MIPS32_R2=y
+# CONFIG_COMPACTION is not set
+CONFIG_HZ_100=y
+CONFIG_PREEMPT=y
+# CONFIG_SECCOMP is not set
+CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+CONFIG_MEMCG=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_ALLOW_DEV_COREDUMP is not set
+CONFIG_NETDEVICES=y
+# CONFIG_ETHERNET is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_LEGACY_PTY_COUNT=2
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_MMC=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_MEMORY=y
+CONFIG_PHY_RALINK_USB=y
+# CONFIG_DNOTIFY is not set
+CONFIG_PROC_KCORE=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+CONFIG_CONFIGFS_FS=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_PANIC_TIMEOUT=10
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_STACKTRACE=y
+# CONFIG_FTRACE is not set
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRC16=y
+CONFIG_XZ_DEC=y
diff --git a/arch/mips/fw/arc/init.c b/arch/mips/fw/arc/init.c
index 629b24db0d3a..008555969534 100644
--- a/arch/mips/fw/arc/init.c
+++ b/arch/mips/fw/arc/init.c
@@ -51,7 +51,7 @@ void __init prom_init(void)
 #endif
 #ifdef CONFIG_SGI_IP27
         {
-                extern struct plat_smp_ops ip27_smp_ops;
+                extern const struct plat_smp_ops ip27_smp_ops;
 
                 register_smp_ops(&ip27_smp_ops);
         }
diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
index 51ffbbaddee2..e0436aaf7f38 100644
--- a/arch/mips/generic/Kconfig
+++ b/arch/mips/generic/Kconfig
@@ -36,4 +36,10 @@ config FIT_IMAGE_FDT_BOSTON
           enable this if you wish to boot on a MIPS Boston board, as it is
           expected by the bootloader.
 
+config FIT_IMAGE_FDT_NI169445
+        bool "Include FDT for NI 169445"
+        help
+          Enable this to include the FDT for the 169445 platform from
+          National Instruments in the FIT kernel image.
+
 endif
diff --git a/arch/mips/generic/Platform b/arch/mips/generic/Platform
index 9a30d69e2281..f5312dfa8184 100644
--- a/arch/mips/generic/Platform
+++ b/arch/mips/generic/Platform
@@ -12,3 +12,7 @@ platform-$(CONFIG_MIPS_GENERIC)	+= generic/
 cflags-$(CONFIG_MIPS_GENERIC)   += -I$(srctree)/arch/mips/include/asm/mach-generic
 load-$(CONFIG_MIPS_GENERIC)     += 0xffffffff80100000
 all-$(CONFIG_MIPS_GENERIC)      := vmlinux.gz.itb
+
+its-y                                   := vmlinux.its.S
+its-$(CONFIG_FIT_IMAGE_FDT_BOSTON)      += board-boston.its.S
+its-$(CONFIG_FIT_IMAGE_FDT_NI169445)    += board-ni169445.its.S
diff --git a/arch/mips/generic/board-boston.its.S b/arch/mips/generic/board-boston.its.S
new file mode 100644
index 000000000000..a7f51f97b910
--- /dev/null
+++ b/arch/mips/generic/board-boston.its.S
@@ -0,0 +1,22 @@
+/ {
+        images {
+                fdt@boston {
+                        description = "img,boston Device Tree";
+                        data = /incbin/("boot/dts/img/boston.dtb");
+                        type = "flat_dt";
+                        arch = "mips";
+                        compression = "none";
+                        hash@0 {
+                                algo = "sha1";
+                        };
+                };
+        };
+
+        configurations {
+                conf@boston {
+                        description = "Boston Linux kernel";
+                        kernel = "kernel@0";
+                        fdt = "fdt@boston";
+                };
+        };
+};
diff --git a/arch/mips/generic/board-ni169445.its.S b/arch/mips/generic/board-ni169445.its.S
new file mode 100644
index 000000000000..d12e12fe90be
--- /dev/null
+++ b/arch/mips/generic/board-ni169445.its.S
@@ -0,0 +1,22 @@
+{
+        images {
+                fdt@ni169445 {
+                        description = "NI 169445 device tree";
+                        data = /incbin/("boot/dts/ni/169445.dtb");
+                        type = "flat_dt";
+                        arch = "mips";
+                        compression = "none";
+                        hash@0 {
+                                algo = "sha1";
+                        };
+                };
+        };
+
+        configurations {
+                conf@ni169445 {
+                        description = "NI 169445 Linux Kernel";
+                        kernel = "kernel@0";
+                        fdt = "fdt@ni169445";
+                };
+        };
+};
diff --git a/arch/mips/generic/init.c b/arch/mips/generic/init.c
index 3f32b376d30e..15a7fb8e2a2e 100644
--- a/arch/mips/generic/init.c
+++ b/arch/mips/generic/init.c
@@ -16,6 +16,7 @@
 #include <linux/of_fdt.h>
 #include <linux/of_platform.h>
 
+#include <asm/bootinfo.h>
 #include <asm/fw/fw.h>
 #include <asm/irq_cpu.h>
 #include <asm/machine.h>
@@ -88,6 +89,8 @@ void __init *plat_get_fdt(void)
         return (void *)fdt;
 }
 
+#ifdef CONFIG_RELOCATABLE
+
 void __init plat_fdt_relocated(void *new_location)
 {
         /*
@@ -101,6 +104,8 @@ void __init plat_fdt_relocated(void *new_location)
                 fw_arg1 = (unsigned long)new_location;
 }
 
+#endif /* CONFIG_RELOCATABLE */
+
 void __init plat_mem_setup(void)
 {
         if (mach && mach->fixup_fdt)
diff --git a/arch/mips/generic/irq.c b/arch/mips/generic/irq.c
index 14064bdd91dd..5322d09dd51b 100644
--- a/arch/mips/generic/irq.c
+++ b/arch/mips/generic/irq.c
@@ -12,10 +12,11 @@
 #include <linux/clk-provider.h>
 #include <linux/clocksource.h>
 #include <linux/init.h>
-#include <linux/irqchip/mips-gic.h>
 #include <linux/types.h>
 
 #include <asm/irq.h>
+#include <asm/mips-cps.h>
+#include <asm/time.h>
 
 int get_c0_fdc_int(void)
 {
@@ -23,7 +24,7 @@ int get_c0_fdc_int(void)
 
         if (cpu_has_veic)
                 panic("Unimplemented!");
-        else if (gic_present)
+        else if (mips_gic_present())
                 mips_cpu_fdc_irq = gic_get_c0_fdc_int();
         else if (cp0_fdc_irq >= 0)
                 mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
@@ -39,7 +40,7 @@ int get_c0_perfcount_int(void)
 
         if (cpu_has_veic)
                 panic("Unimplemented!");
-        else if (gic_present)
+        else if (mips_gic_present())
                 mips_cpu_perf_irq = gic_get_c0_perfcount_int();
         else if (cp0_perfcount_irq >= 0)
                 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
@@ -55,7 +56,7 @@ unsigned int get_c0_compare_int(void)
 
         if (cpu_has_veic)
                 panic("Unimplemented!");
-        else if (gic_present)
+        else if (mips_gic_present())
                 mips_cpu_timer_irq = gic_get_c0_compare_int();
         else
                 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
diff --git a/arch/mips/generic/vmlinux.its.S b/arch/mips/generic/vmlinux.its.S
index 3390e2f80b80..f67fbf1c8541 100644
--- a/arch/mips/generic/vmlinux.its.S
+++ b/arch/mips/generic/vmlinux.its.S
@@ -29,28 +29,3 @@
                 };
         };
 };
-
-#ifdef CONFIG_FIT_IMAGE_FDT_BOSTON
-/ {
-        images {
-                fdt@boston {
-                        description = "img,boston Device Tree";
-                        data = /incbin/("boot/dts/img/boston.dtb");
-                        type = "flat_dt";
-                        arch = "mips";
-                        compression = "none";
-                        hash@0 {
-                                algo = "sha1";
-                        };
-                };
-        };
-
-        configurations {
-                conf@boston {
-                        description = "Boston Linux kernel";
-                        kernel = "kernel@0";
-                        fdt = "fdt@boston";
-                };
-        };
-};
-#endif /* CONFIG_FIT_IMAGE_FDT_BOSTON */
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index 859cf7048347..81fae23ce7cd 100644
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -55,6 +55,7 @@
                 .type   symbol, @function;              \
                 .ent    symbol, 0;                      \
 symbol:         .frame  sp, 0, ra;                      \
+                .cfi_startproc;                         \
                 .insn
 
 /*
@@ -66,12 +67,14 @@ symbol:		.frame	sp, 0, ra;			\
                 .type   symbol, @function;              \
                 .ent    symbol, 0;                      \
 symbol:         .frame  sp, framesize, rpc;             \
+                .cfi_startproc;                         \
                 .insn
 
 /*
  * END - mark end of function
  */
 #define END(function)                                   \
+                .cfi_endproc;                           \
                 .end    function;                       \
                 .size   function, .-function
 
diff --git a/arch/mips/include/asm/bmips.h b/arch/mips/include/asm/bmips.h
index a92aee7b977a..b3e2975f83d3 100644
--- a/arch/mips/include/asm/bmips.h
+++ b/arch/mips/include/asm/bmips.h
@@ -48,8 +48,8 @@
 #include <asm/r4kcache.h>
 #include <asm/smp-ops.h>
 
-extern struct plat_smp_ops bmips43xx_smp_ops;
-extern struct plat_smp_ops bmips5000_smp_ops;
+extern const struct plat_smp_ops bmips43xx_smp_ops;
+extern const struct plat_smp_ops bmips5000_smp_ops;
 
 static inline int register_bmips_smp_ops(void)
 {
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index cd6efb07c980..a41059d47d31 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -15,6 +15,8 @@
 #include <linux/cache.h>
 #include <linux/types.h>
 
+#include <asm/mipsregs.h>
+
 /*
  * Descriptor for a cache
  */
@@ -77,17 +79,10 @@ struct cpuinfo_mips {
         struct cache_desc       tcache; /* Tertiary/split secondary cache */
         int                     srsets; /* Shadow register sets */
         int                     package;/* physical package number */
-        int                     core;   /* physical core number */
+        unsigned int            globalnumber;
 #ifdef CONFIG_64BIT
         int                     vmbits; /* Virtual memory size in bits */
 #endif
-#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
-        /*
-         * There is not necessarily a 1:1 mapping of VPE num to CPU number
-         * in particular on multi-core systems.
-         */
-        int                     vpe_id;  /* Virtual Processor number */
-#endif
         void                    *data;  /* Additional data */
         unsigned int            watch_reg_count;   /* Number that exist */
         unsigned int            watch_reg_use_cnt; /* Usable by ptrace */
@@ -144,11 +139,52 @@ struct proc_cpuinfo_notifier_args {
         unsigned long n;
 };
 
-#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
-# define cpu_vpe_id(cpuinfo)    ((cpuinfo)->vpe_id)
-#else
-# define cpu_vpe_id(cpuinfo)    ({ (void)cpuinfo; 0; })
-#endif
+static inline unsigned int cpu_cluster(struct cpuinfo_mips *cpuinfo)
+{
+        /* Optimisation for systems where multiple clusters aren't used */
+        if (!IS_ENABLED(CONFIG_CPU_MIPSR6))
+                return 0;
+
+        return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CLUSTER) >>
+                MIPS_GLOBALNUMBER_CLUSTER_SHF;
+}
+
+static inline unsigned int cpu_core(struct cpuinfo_mips *cpuinfo)
+{
+        return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CORE) >>
+                MIPS_GLOBALNUMBER_CORE_SHF;
+}
+
+static inline unsigned int cpu_vpe_id(struct cpuinfo_mips *cpuinfo)
+{
+        /* Optimisation for systems where VP(E)s aren't used */
+        if (!IS_ENABLED(CONFIG_MIPS_MT_SMP) && !IS_ENABLED(CONFIG_CPU_MIPSR6))
+                return 0;
+
+        return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_VP) >>
+                MIPS_GLOBALNUMBER_VP_SHF;
+}
+
+extern void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster);
+extern void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core);
+extern void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe);
+
+static inline bool cpus_are_siblings(int cpua, int cpub)
+{
+        struct cpuinfo_mips *infoa = &cpu_data[cpua];
+        struct cpuinfo_mips *infob = &cpu_data[cpub];
+        unsigned int gnuma, gnumb;
+
+        if (infoa->package != infob->package)
+                return false;
+
+        gnuma = infoa->globalnumber & ~MIPS_GLOBALNUMBER_VP;
+        gnumb = infob->globalnumber & ~MIPS_GLOBALNUMBER_VP;
+        if (gnuma != gnumb)
+                return false;
+
+        return true;
+}
 
 static inline unsigned long cpu_asid_inc(void)
 {
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index 175fe565f4e1..a45af3de075d 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -151,11 +151,6 @@ static inline int __pure __get_cpu_type(const int cpu_type)
         case CPU_R5500:
 #endif
 
-#ifdef CONFIG_SYS_HAS_CPU_R6000
-        case CPU_R6000:
-        case CPU_R6000A:
-#endif
-
 #ifdef CONFIG_SYS_HAS_CPU_NEVADA
         case CPU_NEVADA:
 #endif
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index d0c152b989f8..ece9b84f3bcb 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -286,11 +286,6 @@ enum cpu_type_enum {
         CPU_R3081, CPU_R3081E,
 
         /*
-         * R6000 class processors
-         */
-        CPU_R6000, CPU_R6000A,
-
-        /*
          * R4000 class processors
          */
         CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
diff --git a/arch/mips/include/asm/floppy.h b/arch/mips/include/asm/floppy.h
index d75aed36480a..021d09ae5670 100644
--- a/arch/mips/include/asm/floppy.h
+++ b/arch/mips/include/asm/floppy.h
@@ -10,11 +10,11 @@
 #ifndef _ASM_FLOPPY_H
 #define _ASM_FLOPPY_H
 
-#include <linux/dma-mapping.h>
+#include <asm/io.h>
 
 static inline void fd_cacheflush(char * addr, long size)
 {
-        dma_cache_sync(NULL, addr, size, DMA_BIDIRECTIONAL);
+        dma_cache_wback_inv((unsigned long)addr, size);
 }
 
 #define MAX_BUFFER_SECTORS 24
diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h
index c05369e0b8d6..b36097d3cbf4 100644
--- a/arch/mips/include/asm/fpu_emulator.h
+++ b/arch/mips/include/asm/fpu_emulator.h
@@ -36,6 +36,7 @@ struct mips_fpu_emulator_stats {
         unsigned long emulated;
         unsigned long loads;
         unsigned long stores;
+        unsigned long branches;
         unsigned long cp1ops;
         unsigned long cp1xops;
         unsigned long errors;
@@ -45,6 +46,121 @@ struct mips_fpu_emulator_stats {
         unsigned long ieee754_zerodiv;
         unsigned long ieee754_invalidop;
         unsigned long ds_emul;
+
+        unsigned long abs_s;
+        unsigned long abs_d;
+        unsigned long add_s;
+        unsigned long add_d;
+        unsigned long bc1eqz;
+        unsigned long bc1nez;
+        unsigned long ceil_w_s;
+        unsigned long ceil_w_d;
+        unsigned long ceil_l_s;
+        unsigned long ceil_l_d;
+        unsigned long class_s;
+        unsigned long class_d;
+        unsigned long cmp_af_s;
+        unsigned long cmp_af_d;
+        unsigned long cmp_eq_s;
+        unsigned long cmp_eq_d;
+        unsigned long cmp_le_s;
+        unsigned long cmp_le_d;
+        unsigned long cmp_lt_s;
+        unsigned long cmp_lt_d;
+        unsigned long cmp_ne_s;
+        unsigned long cmp_ne_d;
+        unsigned long cmp_or_s;
+        unsigned long cmp_or_d;
+        unsigned long cmp_ueq_s;
+        unsigned long cmp_ueq_d;
+        unsigned long cmp_ule_s;
+        unsigned long cmp_ule_d;
+        unsigned long cmp_ult_s;
+        unsigned long cmp_ult_d;
+        unsigned long cmp_un_s;
+        unsigned long cmp_un_d;
+        unsigned long cmp_une_s;
+        unsigned long cmp_une_d;
+        unsigned long cmp_saf_s;
+        unsigned long cmp_saf_d;
+        unsigned long cmp_seq_s;
+        unsigned long cmp_seq_d;
+        unsigned long cmp_sle_s;
+        unsigned long cmp_sle_d;
+        unsigned long cmp_slt_s;
+        unsigned long cmp_slt_d;
+        unsigned long cmp_sne_s;
+        unsigned long cmp_sne_d;
+        unsigned long cmp_sor_s;
+        unsigned long cmp_sor_d;
+        unsigned long cmp_sueq_s;
+        unsigned long cmp_sueq_d;
+        unsigned long cmp_sule_s;
+        unsigned long cmp_sule_d;
+        unsigned long cmp_sult_s;
+        unsigned long cmp_sult_d;
+        unsigned long cmp_sun_s;
+        unsigned long cmp_sun_d;
+        unsigned long cmp_sune_s;
+        unsigned long cmp_sune_d;
+        unsigned long cvt_d_l;
+        unsigned long cvt_d_s;
+        unsigned long cvt_d_w;
+        unsigned long cvt_l_s;
+        unsigned long cvt_l_d;
+        unsigned long cvt_s_d;
+        unsigned long cvt_s_l;
+        unsigned long cvt_s_w;
+        unsigned long cvt_w_s;
+        unsigned long cvt_w_d;
+        unsigned long div_s;
+        unsigned long div_d;
+        unsigned long floor_w_s;
+        unsigned long floor_w_d;
+        unsigned long floor_l_s;
+        unsigned long floor_l_d;
+        unsigned long maddf_s;
+        unsigned long maddf_d;
+        unsigned long max_s;
+        unsigned long max_d;
+        unsigned long maxa_s;
+        unsigned long maxa_d;
+        unsigned long min_s;
+        unsigned long min_d;
+        unsigned long mina_s;
+        unsigned long mina_d;
+        unsigned long mov_s;
+        unsigned long mov_d;
+        unsigned long msubf_s;
+        unsigned long msubf_d;
+        unsigned long mul_s;
+        unsigned long mul_d;
+        unsigned long neg_s;
+        unsigned long neg_d;
+        unsigned long recip_s;
+        unsigned long recip_d;
+        unsigned long rint_s;
+        unsigned long rint_d;
+        unsigned long round_w_s;
+        unsigned long round_w_d;
+        unsigned long round_l_s;
+        unsigned long round_l_d;
+        unsigned long rsqrt_s;
+        unsigned long rsqrt_d;
+        unsigned long sel_s;
+        unsigned long sel_d;
+        unsigned long seleqz_s;
+        unsigned long seleqz_d;
+        unsigned long selnez_s;
+        unsigned long selnez_d;
+        unsigned long sqrt_s;
+        unsigned long sqrt_d;
+        unsigned long sub_s;
+        unsigned long sub_d;
+        unsigned long trunc_w_s;
+        unsigned long trunc_w_d;
+        unsigned long trunc_l_s;
+        unsigned long trunc_l_d;
 };
 
 DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats);
@@ -62,7 +178,7 @@ do {									\
 
 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
                                     struct mips_fpu_struct *ctx, int has_fpu,
-                                    void *__user *fault_addr);
+                                    void __user **fault_addr);
 void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
                      struct task_struct *tsk);
 int process_fpemu_return(int sig, void __user *fault_addr,
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index ecabc00c1e66..0cbf3af37eca 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -632,4 +632,6 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
  */
 #define xlate_dev_kmem_ptr(p)   p
 
+void __ioread64_copy(void *to, const void __iomem *from, size_t count);
+
 #endif /* _ASM_IO_H */
diff --git a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
index bace5b9ae4df..f439cf9cf9d1 100644
--- a/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-au1x00/cpu-feature-overrides.h
@@ -8,12 +8,16 @@
 #define __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H
 
 #define cpu_has_tlb                     1
+#define cpu_has_ftlb                    0
 #define cpu_has_tlbinv                  0
 #define cpu_has_segments                0
 #define cpu_has_eva                     0
 #define cpu_has_htw                     0
+#define cpu_has_ldpte                   0
 #define cpu_has_rixiex                  0
 #define cpu_has_maar                    0
+#define cpu_has_rw_llb                  0
+#define cpu_has_3kex                    0
 #define cpu_has_4kex                    1
 #define cpu_has_3k_cache                0
 #define cpu_has_4k_cache                1
@@ -30,6 +34,12 @@
 #define cpu_has_mcheck                  1
 #define cpu_has_ejtag                   1
 #define cpu_has_llsc                    1
+#define cpu_has_guestctl0ext            0
+#define cpu_has_guestctl1               0
+#define cpu_has_guestctl2               0
+#define cpu_has_guestid                 0
+#define cpu_has_drg                     0
+#define cpu_has_bp_ghist                0
 #define cpu_has_mips16                  0
 #define cpu_has_mips16e2                0
 #define cpu_has_mdmx                    0
@@ -37,17 +47,23 @@
 #define cpu_has_smartmips               0
 #define cpu_has_rixi                    0
 #define cpu_has_mmips                   0
+#define cpu_has_lpa                     0
+#define cpu_has_mhv                     0
 #define cpu_has_vtag_icache             0
 #define cpu_has_dc_aliases              0
 #define cpu_has_ic_fills_f_dc           1
 #define cpu_has_pindexed_dcache         0
 #define cpu_has_mips32r1                1
 #define cpu_has_mips32r2                0
+#define cpu_has_mips32r6                0
 #define cpu_has_mips64r1                0
 #define cpu_has_mips64r2                0
+#define cpu_has_mips64r6                0
 #define cpu_has_dsp                     0
 #define cpu_has_dsp2                    0
+#define cpu_has_dsp3                    0
 #define cpu_has_mipsmt                  0
+#define cpu_has_vp                      0
 #define cpu_has_userlocal               0
 #define cpu_has_nofpuex                 0
 #define cpu_has_64bits                  0
@@ -58,9 +74,19 @@
 
 #define cpu_dcache_line_size()          32
 #define cpu_icache_line_size()          32
+#define cpu_scache_line_size()          0
 
 #define cpu_has_perf_cntr_intr_bit      0
 #define cpu_has_vz                      0
 #define cpu_has_msa                     0
+#define cpu_has_fre                     0
+#define cpu_has_cdmm                    0
+#define cpu_has_small_pages             0
+#define cpu_has_nan_legacy              1
+#define cpu_has_nan_2008                1
+#define cpu_has_ebase_wg                0
+#define cpu_has_badinstr                0
+#define cpu_has_badinstrp               0
+#define cpu_has_contextconfig           0
 
 #endif /* __ASM_MACH_AU1X00_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 5035f09c5427..24080af570f9 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -710,7 +710,7 @@
 /* Broadcom 6345 ENET DMA definitions */
 #define ENETDMA_6345_CHANCFG_REG        (0x00)
 
-#define ENETDMA_6345_MAXBURST_REG       (0x40)
+#define ENETDMA_6345_MAXBURST_REG       (0x04)
 
 #define ENETDMA_6345_RSTART_REG         (0x08)
 
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index bd8b9bbe1771..a4f798629c3d 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -46,9 +46,9 @@
 #define cpu_has_64bits          1
 #define cpu_has_octeon_cache    1
 #define cpu_has_saa             octeon_has_saa()
-#define cpu_has_mips32r1        0
-#define cpu_has_mips32r2        0
-#define cpu_has_mips64r1        0
+#define cpu_has_mips32r1        1
+#define cpu_has_mips32r2        1
+#define cpu_has_mips64r1        1
 #define cpu_has_mips64r2        1
 #define cpu_has_dsp             0
 #define cpu_has_dsp2            0
diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
index defd135e7ac8..3fb7a0e09494 100644
--- a/arch/mips/include/asm/mach-ip27/topology.h
+++ b/arch/mips/include/asm/mach-ip27/topology.h
@@ -23,7 +23,6 @@ struct cpuinfo_ip27 {
 extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS];
 
 #define cpu_to_node(cpu)        (sn_cpu_info[(cpu)].p_nodeid)
-#define parent_node(node)       (node)
 #define cpumask_of_node(node)   ((node) == -1 ?                         \
                                  cpu_all_mask :                         \
                                  &hub_data(node)->h_cpus)
diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
index 8064d7a4b33d..d750f93232e4 100644
--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
@@ -46,8 +46,6 @@ extern struct clk *clk_get_ppe(void);
 
 /* find out what bootsource we have */
 extern unsigned char ltq_boot_select(void);
-/* find out what caused the last cpu reset */
-extern int ltq_reset_cause(void);
 /* find out the soc type */
 extern int ltq_soc_type(void);
 
diff --git a/arch/mips/include/asm/mach-loongson64/loongson.h b/arch/mips/include/asm/mach-loongson64/loongson.h
index c68c0cc879c6..d0ae5d55413b 100644
--- a/arch/mips/include/asm/mach-loongson64/loongson.h
+++ b/arch/mips/include/asm/mach-loongson64/loongson.h
@@ -26,7 +26,7 @@ extern void mach_prepare_shutdown(void);
 /* environment arguments from bootloader */
 extern u32 cpu_clock_freq;
 extern u32 memsize, highmemsize;
-extern struct plat_smp_ops loongson3_smp_ops;
+extern const struct plat_smp_ops loongson3_smp_ops;
 
 /* loongson-specific command line, env and memory initialization */
 extern void __init prom_init_memory(void);
diff --git a/arch/mips/include/asm/mach-loongson64/topology.h b/arch/mips/include/asm/mach-loongson64/topology.h
index 0d8f3b55bdbc..bcb885615fca 100644
--- a/arch/mips/include/asm/mach-loongson64/topology.h
+++ b/arch/mips/include/asm/mach-loongson64/topology.h
@@ -4,7 +4,6 @@
 #ifdef CONFIG_NUMA
 
 #define cpu_to_node(cpu)        (cpu_logical_map(cpu) >> 2)
-#define parent_node(node)       (node)
 #define cpumask_of_node(node)   (&__node_data[(node)]->cpumask)
 
 struct pci_bus;
diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h
index 987ff580466b..817698abf2eb 100644
--- a/arch/mips/include/asm/mips-boards/maltaint.h
+++ b/arch/mips/include/asm/mips-boards/maltaint.h
@@ -10,8 +10,6 @@
 #ifndef _MIPS_MALTAINT_H
 #define _MIPS_MALTAINT_H
 
-#include <linux/irqchip/mips-gic.h>
-
 /*
  * Interrupts 0..15 are used for Malta ISA compatible interrupts
  */
@@ -62,7 +60,4 @@
 #define MSC01E_INT_PERFCTR      10
 #define MSC01E_INT_CPUCTR       11
 
-/* GIC external interrupts */
-#define GIC_INT_I8259A          GIC_SHARED_TO_HWIRQ(3)
-
 #endif /* !(_MIPS_MALTAINT_H) */
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
index cfdbab015769..f6231b91b724 100644
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -8,16 +8,18 @@
  * option) any later version.
  */
 
+#ifndef __MIPS_ASM_MIPS_CPS_H__
+# error Please include asm/mips-cps.h rather than asm/mips-cm.h
+#endif
+
 #ifndef __MIPS_ASM_MIPS_CM_H__
 #define __MIPS_ASM_MIPS_CM_H__
 
 #include <linux/bitops.h>
 #include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/types.h>
 
 /* The base address of the CM GCR block */
-extern void __iomem *mips_cm_base;
+extern void __iomem *mips_gcr_base;
 
 /* The base address of the CM L2-only sync region */
 extern void __iomem *mips_cm_l2sync_base;
@@ -80,7 +82,7 @@ static inline int mips_cm_probe(void)
 static inline bool mips_cm_present(void)
 {
 #ifdef CONFIG_MIPS_CM
-        return mips_cm_base != NULL;
+        return mips_gcr_base != NULL;
 #else
         return false;
 #endif
@@ -112,321 +114,219 @@ static inline bool mips_cm_has_l2sync(void)
 /* Size of the L2-only sync region */
 #define MIPS_CM_L2SYNC_SIZE     0x1000
 
-/* Macros to ease the creation of register access functions */
-#define BUILD_CM_R_(name, off)                                  \
-static inline unsigned long __iomem *addr_gcr_##name(void)      \
-{                                                               \
-        return (unsigned long __iomem *)(mips_cm_base + (off)); \
-}                                                               \
-                                                                \
-static inline u32 read32_gcr_##name(void)                       \
-{                                                               \
-        return __raw_readl(addr_gcr_##name());                  \
-}                                                               \
-                                                                \
-static inline u64 read64_gcr_##name(void)                       \
-{                                                               \
-        void __iomem *addr = addr_gcr_##name();                 \
-        u64 ret;                                                \
-                                                                \
-        if (mips_cm_is64) {                                     \
-                ret = __raw_readq(addr);                        \
-        } else {                                                \
-                ret = __raw_readl(addr);                        \
-                ret |= (u64)__raw_readl(addr + 0x4) << 32;      \
-        }                                                       \
-                                                                \
-        return ret;                                             \
-}                                                               \
-                                                                \
-static inline unsigned long read_gcr_##name(void)               \
-{                                                               \
-        if (mips_cm_is64)                                       \
-                return read64_gcr_##name();                     \
-        else                                                    \
-                return read32_gcr_##name();                     \
-}
-
-#define BUILD_CM__W(name, off)                                  \
-static inline void write32_gcr_##name(u32 value)                \
-{                                                               \
-        __raw_writel(value, addr_gcr_##name());                 \
-}                                                               \
-                                                                \
-static inline void write64_gcr_##name(u64 value)                \
-{                                                               \
-        __raw_writeq(value, addr_gcr_##name());                 \
-}                                                               \
-                                                                \
-static inline void write_gcr_##name(unsigned long value)        \
-{                                                               \
-        if (mips_cm_is64)                                       \
-                write64_gcr_##name(value);                      \
-        else                                                    \
-                write32_gcr_##name(value);                      \
-}
-
-#define BUILD_CM_RW(name, off)                                  \
-        BUILD_CM_R_(name, off)                                  \
-        BUILD_CM__W(name, off)
-
-#define BUILD_CM_Cx_R_(name, off)                               \
-        BUILD_CM_R_(cl_##name, MIPS_CM_CLCB_OFS + (off))        \
-        BUILD_CM_R_(co_##name, MIPS_CM_COCB_OFS + (off))
-
-#define BUILD_CM_Cx__W(name, off)                               \
-        BUILD_CM__W(cl_##name, MIPS_CM_CLCB_OFS + (off))        \
-        BUILD_CM__W(co_##name, MIPS_CM_COCB_OFS + (off))
-
-#define BUILD_CM_Cx_RW(name, off)                               \
-        BUILD_CM_Cx_R_(name, off)                               \
-        BUILD_CM_Cx__W(name, off)
-
-/* GCB register accessor functions */
-BUILD_CM_R_(config,             MIPS_CM_GCB_OFS + 0x00)
-BUILD_CM_RW(base,               MIPS_CM_GCB_OFS + 0x08)
-BUILD_CM_RW(access,             MIPS_CM_GCB_OFS + 0x20)
-BUILD_CM_R_(rev,                MIPS_CM_GCB_OFS + 0x30)
-BUILD_CM_RW(err_control,        MIPS_CM_GCB_OFS + 0x38)
-BUILD_CM_RW(error_mask,         MIPS_CM_GCB_OFS + 0x40)
-BUILD_CM_RW(error_cause,        MIPS_CM_GCB_OFS + 0x48)
-BUILD_CM_RW(error_addr,         MIPS_CM_GCB_OFS + 0x50)
-BUILD_CM_RW(error_mult,         MIPS_CM_GCB_OFS + 0x58)
-BUILD_CM_RW(l2_only_sync_base,  MIPS_CM_GCB_OFS + 0x70)
-BUILD_CM_RW(gic_base,           MIPS_CM_GCB_OFS + 0x80)
-BUILD_CM_RW(cpc_base,           MIPS_CM_GCB_OFS + 0x88)
-BUILD_CM_RW(reg0_base,          MIPS_CM_GCB_OFS + 0x90)
-BUILD_CM_RW(reg0_mask,          MIPS_CM_GCB_OFS + 0x98)
-BUILD_CM_RW(reg1_base,          MIPS_CM_GCB_OFS + 0xa0)
-BUILD_CM_RW(reg1_mask,          MIPS_CM_GCB_OFS + 0xa8)
-BUILD_CM_RW(reg2_base,          MIPS_CM_GCB_OFS + 0xb0)
-BUILD_CM_RW(reg2_mask,          MIPS_CM_GCB_OFS + 0xb8)
-BUILD_CM_RW(reg3_base,          MIPS_CM_GCB_OFS + 0xc0)
-BUILD_CM_RW(reg3_mask,          MIPS_CM_GCB_OFS + 0xc8)
-BUILD_CM_R_(gic_status,         MIPS_CM_GCB_OFS + 0xd0)
-BUILD_CM_R_(cpc_status,         MIPS_CM_GCB_OFS + 0xf0)
-BUILD_CM_RW(l2_config,          MIPS_CM_GCB_OFS + 0x130)
-BUILD_CM_RW(sys_config2,        MIPS_CM_GCB_OFS + 0x150)
-BUILD_CM_RW(l2_pft_control,     MIPS_CM_GCB_OFS + 0x300)
-BUILD_CM_RW(l2_pft_control_b,   MIPS_CM_GCB_OFS + 0x308)
-BUILD_CM_RW(bev_base,           MIPS_CM_GCB_OFS + 0x680)
-
-/* Core Local & Core Other register accessor functions */
-BUILD_CM_Cx_RW(reset_release,   0x00)
-BUILD_CM_Cx_RW(coherence,       0x08)
-BUILD_CM_Cx_R_(config,          0x10)
-BUILD_CM_Cx_RW(other,           0x18)
-BUILD_CM_Cx_RW(reset_base,      0x20)
-BUILD_CM_Cx_R_(id,              0x28)
-BUILD_CM_Cx_RW(reset_ext_base,  0x30)
-BUILD_CM_Cx_R_(tcid_0_priority, 0x40)
-BUILD_CM_Cx_R_(tcid_1_priority, 0x48)
-BUILD_CM_Cx_R_(tcid_2_priority, 0x50)
-BUILD_CM_Cx_R_(tcid_3_priority, 0x58)
-BUILD_CM_Cx_R_(tcid_4_priority, 0x60)
-BUILD_CM_Cx_R_(tcid_5_priority, 0x68)
-BUILD_CM_Cx_R_(tcid_6_priority, 0x70)
-BUILD_CM_Cx_R_(tcid_7_priority, 0x78)
-BUILD_CM_Cx_R_(tcid_8_priority, 0x80)
-
-/* GCR_CONFIG register fields */
-#define CM_GCR_CONFIG_NUMIOCU_SHF               8
-#define CM_GCR_CONFIG_NUMIOCU_MSK               (_ULCAST_(0xf) << 8)
-#define CM_GCR_CONFIG_PCORES_SHF                0
-#define CM_GCR_CONFIG_PCORES_MSK                (_ULCAST_(0xff) << 0)
-
-/* GCR_BASE register fields */
-#define CM_GCR_BASE_GCRBASE_SHF                 15
-#define CM_GCR_BASE_GCRBASE_MSK                 (_ULCAST_(0x1ffff) << 15)
-#define CM_GCR_BASE_CMDEFTGT_SHF                0
-#define CM_GCR_BASE_CMDEFTGT_MSK                (_ULCAST_(0x3) << 0)
+#define GCR_ACCESSOR_RO(sz, off, name)                                  \
+        CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_GCB_OFS + off, name)           \
+        CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
+
+#define GCR_ACCESSOR_RW(sz, off, name)                                  \
+        CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_GCB_OFS + off, name)           \
+        CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, redir_##name)
+
+#define GCR_CX_ACCESSOR_RO(sz, off, name)                               \
+        CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name)     \
+        CPS_ACCESSOR_RO(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
+
+#define GCR_CX_ACCESSOR_RW(sz, off, name)                               \
+        CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_CLCB_OFS + off, cl_##name)     \
+        CPS_ACCESSOR_RW(gcr, sz, MIPS_CM_COCB_OFS + off, co_##name)
+
+/* GCR_CONFIG - Information about the system */
+GCR_ACCESSOR_RO(64, 0x000, config)
+#define CM_GCR_CONFIG_CLUSTER_COH_CAPABLE       BIT_ULL(43)
+#define CM_GCR_CONFIG_CLUSTER_ID                GENMASK_ULL(39, 32)
+#define CM_GCR_CONFIG_NUM_CLUSTERS              GENMASK(29, 23)
+#define CM_GCR_CONFIG_NUMIOCU                   GENMASK(15, 8)
+#define CM_GCR_CONFIG_PCORES                    GENMASK(7, 0)
+
+/* GCR_BASE - Base address of the Global Configuration Registers (GCRs) */
+GCR_ACCESSOR_RW(64, 0x008, base)
+#define CM_GCR_BASE_GCRBASE                     GENMASK_ULL(47, 15)
+#define CM_GCR_BASE_CMDEFTGT                    GENMASK(1, 0)
 #define  CM_GCR_BASE_CMDEFTGT_DISABLED          0
 #define  CM_GCR_BASE_CMDEFTGT_MEM               1
 #define  CM_GCR_BASE_CMDEFTGT_IOCU0             2
 #define  CM_GCR_BASE_CMDEFTGT_IOCU1             3
 
-/* GCR_RESET_EXT_BASE register fields */
-#define CM_GCR_RESET_EXT_BASE_EVARESET          BIT(31)
-#define CM_GCR_RESET_EXT_BASE_UEB               BIT(30)
-
-/* GCR_ACCESS register fields */
-#define CM_GCR_ACCESS_ACCESSEN_SHF              0
-#define CM_GCR_ACCESS_ACCESSEN_MSK              (_ULCAST_(0xff) << 0)
+/* GCR_ACCESS - Controls core/IOCU access to GCRs */
+GCR_ACCESSOR_RW(32, 0x020, access)
+#define CM_GCR_ACCESS_ACCESSEN                  GENMASK(7, 0)
 
-/* GCR_REV register fields */
-#define CM_GCR_REV_MAJOR_SHF                    8
-#define CM_GCR_REV_MAJOR_MSK                    (_ULCAST_(0xff) << 8)
-#define CM_GCR_REV_MINOR_SHF                    0
-#define CM_GCR_REV_MINOR_MSK                    (_ULCAST_(0xff) << 0)
+/* GCR_REV - Indicates the Coherence Manager revision */
+GCR_ACCESSOR_RO(32, 0x030, rev)
+#define CM_GCR_REV_MAJOR                        GENMASK(15, 8)
+#define CM_GCR_REV_MINOR                        GENMASK(7, 0)
 
 #define CM_ENCODE_REV(major, minor) \
-                (((major) << CM_GCR_REV_MAJOR_SHF) | \
-                 ((minor) << CM_GCR_REV_MINOR_SHF))
+                (((major) << __ffs(CM_GCR_REV_MAJOR)) | \
+                 ((minor) << __ffs(CM_GCR_REV_MINOR)))
 
 #define CM_REV_CM2                              CM_ENCODE_REV(6, 0)
 #define CM_REV_CM2_5                            CM_ENCODE_REV(7, 0)
 #define CM_REV_CM3                              CM_ENCODE_REV(8, 0)
-
-/* GCR_ERR_CONTROL register fields */
-#define CM_GCR_ERR_CONTROL_L2_ECC_EN_SHF        1
-#define CM_GCR_ERR_CONTROL_L2_ECC_EN_MSK        (_ULCAST_(0x1) << 1)
-#define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT_SHF   0
-#define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT_MSK   (_ULCAST_(0x1) << 0)
-
-/* GCR_ERROR_CAUSE register fields */
-#define CM_GCR_ERROR_CAUSE_ERRTYPE_SHF          27
-#define CM_GCR_ERROR_CAUSE_ERRTYPE_MSK          (_ULCAST_(0x1f) << 27)
-#define CM3_GCR_ERROR_CAUSE_ERRTYPE_SHF         58
-#define CM3_GCR_ERROR_CAUSE_ERRTYPE_MSK         GENMASK_ULL(63, 58)
-#define CM_GCR_ERROR_CAUSE_ERRINFO_SHF          0
-#define CM_GCR_ERROR_CAUSE_ERRINGO_MSK          (_ULCAST_(0x7ffffff) << 0)
-
-/* GCR_ERROR_MULT register fields */
-#define CM_GCR_ERROR_MULT_ERR2ND_SHF            0
-#define CM_GCR_ERROR_MULT_ERR2ND_MSK            (_ULCAST_(0x1f) << 0)
-
-/* GCR_L2_ONLY_SYNC_BASE register fields */
-#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_SHF   12
-#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK   (_ULCAST_(0xfffff) << 12)
-#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_SHF     0
-#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK     (_ULCAST_(0x1) << 0)
-
-/* GCR_GIC_BASE register fields */
-#define CM_GCR_GIC_BASE_GICBASE_SHF             17
-#define CM_GCR_GIC_BASE_GICBASE_MSK             (_ULCAST_(0x7fff) << 17)
-#define CM_GCR_GIC_BASE_GICEN_SHF               0
-#define CM_GCR_GIC_BASE_GICEN_MSK               (_ULCAST_(0x1) << 0)
-
-/* GCR_CPC_BASE register fields */
-#define CM_GCR_CPC_BASE_CPCBASE_SHF             15
-#define CM_GCR_CPC_BASE_CPCBASE_MSK             (_ULCAST_(0x1ffff) << 15)
-#define CM_GCR_CPC_BASE_CPCEN_SHF               0
-#define CM_GCR_CPC_BASE_CPCEN_MSK               (_ULCAST_(0x1) << 0)
-
-/* GCR_GIC_STATUS register fields */
-#define CM_GCR_GIC_STATUS_GICEX_SHF             0
-#define CM_GCR_GIC_STATUS_GICEX_MSK             (_ULCAST_(0x1) << 0)
-
-/* GCR_REGn_BASE register fields */
-#define CM_GCR_REGn_BASE_BASEADDR_SHF           16
-#define CM_GCR_REGn_BASE_BASEADDR_MSK           (_ULCAST_(0xffff) << 16)
-
-/* GCR_REGn_MASK register fields */
-#define CM_GCR_REGn_MASK_ADDRMASK_SHF           16
-#define CM_GCR_REGn_MASK_ADDRMASK_MSK           (_ULCAST_(0xffff) << 16)
-#define CM_GCR_REGn_MASK_CCAOVR_SHF             5
-#define CM_GCR_REGn_MASK_CCAOVR_MSK             (_ULCAST_(0x3) << 5)
-#define CM_GCR_REGn_MASK_CCAOVREN_SHF           4
-#define CM_GCR_REGn_MASK_CCAOVREN_MSK           (_ULCAST_(0x1) << 4)
-#define CM_GCR_REGn_MASK_DROPL2_SHF             2
-#define CM_GCR_REGn_MASK_DROPL2_MSK             (_ULCAST_(0x1) << 2)
-#define CM_GCR_REGn_MASK_CMTGT_SHF              0
-#define CM_GCR_REGn_MASK_CMTGT_MSK              (_ULCAST_(0x3) << 0)
-#define  CM_GCR_REGn_MASK_CMTGT_DISABLED        (_ULCAST_(0x0) << 0)
-#define  CM_GCR_REGn_MASK_CMTGT_MEM             (_ULCAST_(0x1) << 0)
-#define  CM_GCR_REGn_MASK_CMTGT_IOCU0           (_ULCAST_(0x2) << 0)
-#define  CM_GCR_REGn_MASK_CMTGT_IOCU1           (_ULCAST_(0x3) << 0)
-
-/* GCR_GIC_STATUS register fields */
-#define CM_GCR_GIC_STATUS_EX_SHF                0
-#define CM_GCR_GIC_STATUS_EX_MSK                (_ULCAST_(0x1) << 0)
-
-/* GCR_CPC_STATUS register fields */
-#define CM_GCR_CPC_STATUS_EX_SHF                0
-#define CM_GCR_CPC_STATUS_EX_MSK                (_ULCAST_(0x1) << 0)
-
-/* GCR_L2_CONFIG register fields */
-#define CM_GCR_L2_CONFIG_BYPASS_SHF             20
-#define CM_GCR_L2_CONFIG_BYPASS_MSK             (_ULCAST_(0x1) << 20)
-#define CM_GCR_L2_CONFIG_SET_SIZE_SHF           12
-#define CM_GCR_L2_CONFIG_SET_SIZE_MSK           (_ULCAST_(0xf) << 12)
-#define CM_GCR_L2_CONFIG_LINE_SIZE_SHF          8
-#define CM_GCR_L2_CONFIG_LINE_SIZE_MSK          (_ULCAST_(0xf) << 8)
-#define CM_GCR_L2_CONFIG_ASSOC_SHF              0
-#define CM_GCR_L2_CONFIG_ASSOC_MSK              (_ULCAST_(0xff) << 0)
-
-/* GCR_SYS_CONFIG2 register fields */
-#define CM_GCR_SYS_CONFIG2_MAXVPW_SHF           0
-#define CM_GCR_SYS_CONFIG2_MAXVPW_MSK           (_ULCAST_(0xf) << 0)
-
-/* GCR_L2_PFT_CONTROL register fields */
-#define CM_GCR_L2_PFT_CONTROL_PAGEMASK_SHF      12
-#define CM_GCR_L2_PFT_CONTROL_PAGEMASK_MSK      (_ULCAST_(0xfffff) << 12)
-#define CM_GCR_L2_PFT_CONTROL_PFTEN_SHF         8
-#define CM_GCR_L2_PFT_CONTROL_PFTEN_MSK         (_ULCAST_(0x1) << 8)
-#define CM_GCR_L2_PFT_CONTROL_NPFT_SHF          0
-#define CM_GCR_L2_PFT_CONTROL_NPFT_MSK          (_ULCAST_(0xff) << 0)
-
-/* GCR_L2_PFT_CONTROL_B register fields */
-#define CM_GCR_L2_PFT_CONTROL_B_CEN_SHF         8
-#define CM_GCR_L2_PFT_CONTROL_B_CEN_MSK         (_ULCAST_(0x1) << 8)
-#define CM_GCR_L2_PFT_CONTROL_B_PORTID_SHF      0
-#define CM_GCR_L2_PFT_CONTROL_B_PORTID_MSK      (_ULCAST_(0xff) << 0)
-
-/* GCR_Cx_COHERENCE register fields */
-#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_SHF     0
-#define CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK     (_ULCAST_(0xff) << 0)
-#define CM3_GCR_Cx_COHERENCE_COHEN_MSK          (_ULCAST_(0x1) << 0)
-
-/* GCR_Cx_CONFIG register fields */
-#define CM_GCR_Cx_CONFIG_IOCUTYPE_SHF           10
-#define CM_GCR_Cx_CONFIG_IOCUTYPE_MSK           (_ULCAST_(0x3) << 10)
-#define CM_GCR_Cx_CONFIG_PVPE_SHF               0
-#define CM_GCR_Cx_CONFIG_PVPE_MSK               (_ULCAST_(0x3ff) << 0)
-
-/* GCR_Cx_OTHER register fields */
-#define CM_GCR_Cx_OTHER_CORENUM_SHF             16
-#define CM_GCR_Cx_OTHER_CORENUM_MSK             (_ULCAST_(0xffff) << 16)
-#define CM3_GCR_Cx_OTHER_CORE_SHF               8
-#define CM3_GCR_Cx_OTHER_CORE_MSK               (_ULCAST_(0x3f) << 8)
-#define CM3_GCR_Cx_OTHER_VP_SHF                 0
-#define CM3_GCR_Cx_OTHER_VP_MSK                 (_ULCAST_(0x7) << 0)
-
-/* GCR_Cx_RESET_BASE register fields */
-#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_SHF     12
-#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE_MSK     (_ULCAST_(0xfffff) << 12)
-
-/* GCR_Cx_RESET_EXT_BASE register fields */
-#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_SHF   31
-#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET_MSK   (_ULCAST_(0x1) << 31)
-#define CM_GCR_Cx_RESET_EXT_BASE_UEB_SHF        30
-#define CM_GCR_Cx_RESET_EXT_BASE_UEB_MSK        (_ULCAST_(0x1) << 30)
-#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_SHF 20
-#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK_MSK (_ULCAST_(0xff) << 20)
-#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_SHF   1
-#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA_MSK   (_ULCAST_(0x7f) << 1)
-#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_SHF    0
-#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT_MSK    (_ULCAST_(0x1) << 0)
-
-/**
- * mips_cm_numcores - return the number of cores present in the system
- *
- * Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or
- * zero if no Coherence Manager is present.
- */
-static inline unsigned mips_cm_numcores(void)
-{
-        if (!mips_cm_present())
-                return 0;
-
-        return ((read_gcr_config() & CM_GCR_CONFIG_PCORES_MSK)
-                >> CM_GCR_CONFIG_PCORES_SHF) + 1;
-}
-
-/**
- * mips_cm_numiocu - return the number of IOCUs present in the system
- *
- * Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero
- * if no Coherence Manager is present.
- */
-static inline unsigned mips_cm_numiocu(void)
-{
-        if (!mips_cm_present())
-                return 0;
-
-        return (read_gcr_config() & CM_GCR_CONFIG_NUMIOCU_MSK)
-                >> CM_GCR_CONFIG_NUMIOCU_SHF;
-}
+#define CM_REV_CM3_5                            CM_ENCODE_REV(9, 0)
+
+/* GCR_ERR_CONTROL - Control error checking logic */
+GCR_ACCESSOR_RW(32, 0x038, err_control)
+#define CM_GCR_ERR_CONTROL_L2_ECC_EN            BIT(1)
+#define CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT       BIT(0)
+
+/* GCR_ERR_MASK - Control which errors are reported as interrupts */
+GCR_ACCESSOR_RW(64, 0x040, error_mask)
+
+/* GCR_ERR_CAUSE - Indicates the type of error that occurred */
+GCR_ACCESSOR_RW(64, 0x048, error_cause)
+#define CM_GCR_ERROR_CAUSE_ERRTYPE              GENMASK(31, 27)
+#define CM3_GCR_ERROR_CAUSE_ERRTYPE             GENMASK_ULL(63, 58)
+#define CM_GCR_ERROR_CAUSE_ERRINFO              GENMASK(26, 0)
+
+/* GCR_ERR_ADDR - Indicates the address associated with an error */
+GCR_ACCESSOR_RW(64, 0x050, error_addr)
+
+/* GCR_ERR_MULT - Indicates when multiple errors have occurred */
+GCR_ACCESSOR_RW(64, 0x058, error_mult)
+#define CM_GCR_ERROR_MULT_ERR2ND                GENMASK(4, 0)
+
+/* GCR_L2_ONLY_SYNC_BASE - Base address of the L2 cache-only sync region */
+GCR_ACCESSOR_RW(64, 0x070, l2_only_sync_base)
+#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE       GENMASK(31, 12)
+#define CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN         BIT(0)
+
+/* GCR_GIC_BASE - Base address of the Global Interrupt Controller (GIC) */
+GCR_ACCESSOR_RW(64, 0x080, gic_base)
+#define CM_GCR_GIC_BASE_GICBASE                 GENMASK(31, 17)
+#define CM_GCR_GIC_BASE_GICEN                   BIT(0)
+
+/* GCR_CPC_BASE - Base address of the Cluster Power Controller (CPC) */
+GCR_ACCESSOR_RW(64, 0x088, cpc_base)
+#define CM_GCR_CPC_BASE_CPCBASE                 GENMASK(31, 15)
+#define CM_GCR_CPC_BASE_CPCEN                   BIT(0)
+
+/* GCR_REGn_BASE - Base addresses of CM address regions */
+GCR_ACCESSOR_RW(64, 0x090, reg0_base)
+GCR_ACCESSOR_RW(64, 0x0a0, reg1_base)
+GCR_ACCESSOR_RW(64, 0x0b0, reg2_base)
+GCR_ACCESSOR_RW(64, 0x0c0, reg3_base)
+#define CM_GCR_REGn_BASE_BASEADDR               GENMASK(31, 16)
+
+/* GCR_REGn_MASK - Size & destination of CM address regions */
+GCR_ACCESSOR_RW(64, 0x098, reg0_mask)
+GCR_ACCESSOR_RW(64, 0x0a8, reg1_mask)
+GCR_ACCESSOR_RW(64, 0x0b8, reg2_mask)
+GCR_ACCESSOR_RW(64, 0x0c8, reg3_mask)
+#define CM_GCR_REGn_MASK_ADDRMASK               GENMASK(31, 16)
+#define CM_GCR_REGn_MASK_CCAOVR                 GENMASK(7, 5)
+#define CM_GCR_REGn_MASK_CCAOVREN               BIT(4)
+#define CM_GCR_REGn_MASK_DROPL2                 BIT(2)
+#define CM_GCR_REGn_MASK_CMTGT                  GENMASK(1, 0)
+#define  CM_GCR_REGn_MASK_CMTGT_DISABLED        0x0
+#define  CM_GCR_REGn_MASK_CMTGT_MEM             0x1
+#define  CM_GCR_REGn_MASK_CMTGT_IOCU0           0x2
+#define  CM_GCR_REGn_MASK_CMTGT_IOCU1           0x3
+
+/* GCR_GIC_STATUS - Indicates presence of a Global Interrupt Controller (GIC) */
+GCR_ACCESSOR_RO(32, 0x0d0, gic_status)
+#define CM_GCR_GIC_STATUS_EX                    BIT(0)
+
+/* GCR_CPC_STATUS - Indicates presence of a Cluster Power Controller (CPC) */
+GCR_ACCESSOR_RO(32, 0x0f0, cpc_status)
+#define CM_GCR_CPC_STATUS_EX                    BIT(0)
+
+/* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */
+GCR_ACCESSOR_RW(32, 0x130, l2_config)
+#define CM_GCR_L2_CONFIG_BYPASS                 BIT(20)
+#define CM_GCR_L2_CONFIG_SET_SIZE               GENMASK(15, 12)
+#define CM_GCR_L2_CONFIG_LINE_SIZE              GENMASK(11, 8)
+#define CM_GCR_L2_CONFIG_ASSOC                  GENMASK(7, 0)
+
+/* GCR_SYS_CONFIG2 - Further information about the system */
+GCR_ACCESSOR_RO(32, 0x150, sys_config2)
+#define CM_GCR_SYS_CONFIG2_MAXVPW               GENMASK(3, 0)
+
+/* GCR_L2_PFT_CONTROL - Controls hardware L2 prefetching */
+GCR_ACCESSOR_RW(32, 0x300, l2_pft_control)
+#define CM_GCR_L2_PFT_CONTROL_PAGEMASK          GENMASK(31, 12)
+#define CM_GCR_L2_PFT_CONTROL_PFTEN             BIT(8)
+#define CM_GCR_L2_PFT_CONTROL_NPFT              GENMASK(7, 0)
+
+/* GCR_L2_PFT_CONTROL_B - Controls hardware L2 prefetching */
+GCR_ACCESSOR_RW(32, 0x308, l2_pft_control_b)
+#define CM_GCR_L2_PFT_CONTROL_B_CEN             BIT(8)
+#define CM_GCR_L2_PFT_CONTROL_B_PORTID          GENMASK(7, 0)
+
+/* GCR_L2SM_COP - L2 cache op state machine control */
+GCR_ACCESSOR_RW(32, 0x620, l2sm_cop)
+#define CM_GCR_L2SM_COP_PRESENT                 BIT(31)
+#define CM_GCR_L2SM_COP_RESULT                  GENMASK(8, 6)
+#define  CM_GCR_L2SM_COP_RESULT_DONTCARE        0
+#define  CM_GCR_L2SM_COP_RESULT_DONE_OK         1
+#define  CM_GCR_L2SM_COP_RESULT_DONE_ERROR      2
+#define  CM_GCR_L2SM_COP_RESULT_ABORT_OK        3
+#define  CM_GCR_L2SM_COP_RESULT_ABORT_ERROR     4
+#define CM_GCR_L2SM_COP_RUNNING                 BIT(5)
+#define CM_GCR_L2SM_COP_TYPE                    GENMASK(4, 2)
+#define  CM_GCR_L2SM_COP_TYPE_IDX_WBINV         0
+#define  CM_GCR_L2SM_COP_TYPE_IDX_STORETAG      1
+#define  CM_GCR_L2SM_COP_TYPE_IDX_STORETAGDATA  2
+#define  CM_GCR_L2SM_COP_TYPE_HIT_INV           4
+#define  CM_GCR_L2SM_COP_TYPE_HIT_WBINV         5
+#define  CM_GCR_L2SM_COP_TYPE_HIT_WB            6
+#define  CM_GCR_L2SM_COP_TYPE_FETCHLOCK         7
+#define CM_GCR_L2SM_COP_CMD                     GENMASK(1, 0)
+#define  CM_GCR_L2SM_COP_CMD_START              1       /* only when idle */
+#define  CM_GCR_L2SM_COP_CMD_ABORT              3       /* only when running */
+
+/* GCR_L2SM_TAG_ADDR_COP - L2 cache op state machine address control */
+GCR_ACCESSOR_RW(64, 0x628, l2sm_tag_addr_cop)
+#define CM_GCR_L2SM_TAG_ADDR_COP_NUM_LINES      GENMASK_ULL(63, 48)
+#define CM_GCR_L2SM_TAG_ADDR_COP_START_TAG      GENMASK_ULL(47, 6)
+
+/* GCR_BEV_BASE - Controls the location of the BEV for powered up cores */
+GCR_ACCESSOR_RW(64, 0x680, bev_base)
+
+/* GCR_Cx_RESET_RELEASE - Controls core reset for CM 1.x */
+GCR_CX_ACCESSOR_RW(32, 0x000, reset_release)
+
+/* GCR_Cx_COHERENCE - Controls core coherence */
+GCR_CX_ACCESSOR_RW(32, 0x008, coherence)
+#define CM_GCR_Cx_COHERENCE_COHDOMAINEN         GENMASK(7, 0)
+#define CM3_GCR_Cx_COHERENCE_COHEN              BIT(0)
+
+/* GCR_Cx_CONFIG - Information about a core's configuration */
+GCR_CX_ACCESSOR_RO(32, 0x010, config)
+#define CM_GCR_Cx_CONFIG_IOCUTYPE               GENMASK(11, 10)
+#define CM_GCR_Cx_CONFIG_PVPE                   GENMASK(9, 0)
+
+/* GCR_Cx_OTHER - Configure the core-other/redirect GCR block */
+GCR_CX_ACCESSOR_RW(32, 0x018, other)
+#define CM_GCR_Cx_OTHER_CORENUM                 GENMASK(31, 16) /* CM < 3 */
+#define CM_GCR_Cx_OTHER_CLUSTER_EN              BIT(31)         /* CM >= 3.5 */
+#define CM_GCR_Cx_OTHER_GIC_EN                  BIT(30)         /* CM >= 3.5 */
+#define CM_GCR_Cx_OTHER_BLOCK                   GENMASK(25, 24) /* CM >= 3.5 */
+#define  CM_GCR_Cx_OTHER_BLOCK_LOCAL            0
+#define  CM_GCR_Cx_OTHER_BLOCK_GLOBAL           1
+#define  CM_GCR_Cx_OTHER_BLOCK_USER             2
+#define  CM_GCR_Cx_OTHER_BLOCK_GLOBAL_HIGH      3
+#define CM_GCR_Cx_OTHER_CLUSTER                 GENMASK(21, 16) /* CM >= 3.5 */
+#define CM3_GCR_Cx_OTHER_CORE                   GENMASK(13, 8)  /* CM >= 3 */
+#define  CM_GCR_Cx_OTHER_CORE_CM                32
+#define CM3_GCR_Cx_OTHER_VP                     GENMASK(2, 0)   /* CM >= 3 */
+
+/* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */
+GCR_CX_ACCESSOR_RW(32, 0x020, reset_base)
+#define CM_GCR_Cx_RESET_BASE_BEVEXCBASE         GENMASK(31, 12)
+
+/* GCR_Cx_ID - Identify the current core */
+GCR_CX_ACCESSOR_RO(32, 0x028, id)
+#define CM_GCR_Cx_ID_CLUSTER                    GENMASK(15, 8)
+#define CM_GCR_Cx_ID_CORE                       GENMASK(7, 0)
+
+/* GCR_Cx_RESET_EXT_BASE - Configure behaviour when cores reset or power up */
+GCR_CX_ACCESSOR_RW(32, 0x030, reset_ext_base)
+#define CM_GCR_Cx_RESET_EXT_BASE_EVARESET       BIT(31)
+#define CM_GCR_Cx_RESET_EXT_BASE_UEB            BIT(30)
+#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCMASK     GENMASK(27, 20)
+#define CM_GCR_Cx_RESET_EXT_BASE_BEVEXCPA       GENMASK(7, 1)
+#define CM_GCR_Cx_RESET_EXT_BASE_PRESENT        BIT(0)
 
 /**
  * mips_cm_l2sync - perform an L2-only sync operation
@@ -469,7 +369,7 @@ static inline unsigned int mips_cm_max_vp_width(void)
         uint32_t cfg;
 
         if (mips_cm_revision() >= CM_REV_CM3)
-                return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW_MSK;
+                return read_gcr_sys_config2() & CM_GCR_SYS_CONFIG2_MAXVPW;
 
         if (mips_cm_present()) {
                 /*
@@ -477,8 +377,8 @@ static inline unsigned int mips_cm_max_vp_width(void)
                  * number of VP(E)s, and if that ever changes then this will
                  * need revisiting.
                  */
-                cfg = read_gcr_cl_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
-                return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
+                cfg = read_gcr_cl_config() & CM_GCR_Cx_CONFIG_PVPE;
+                return (cfg >> __ffs(CM_GCR_Cx_CONFIG_PVPE)) + 1;
         }
 
         if (IS_ENABLED(CONFIG_SMP))
@@ -499,7 +399,7 @@ static inline unsigned int mips_cm_max_vp_width(void)
  */
 static inline unsigned int mips_cm_vp_id(unsigned int cpu)
 {
-        unsigned int core = cpu_data[cpu].core;
+        unsigned int core = cpu_core(&cpu_data[cpu]);
         unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);
 
         return (core * mips_cm_max_vp_width()) + vp;
@@ -508,29 +408,56 @@ static inline unsigned int mips_cm_vp_id(unsigned int cpu)
 #ifdef CONFIG_MIPS_CM
 
 /**
- * mips_cm_lock_other - lock access to another core
+ * mips_cm_lock_other - lock access to redirect/other region
+ * @cluster: the other cluster to be accessed
  * @core: the other core to be accessed
  * @vp: the VP within the other core to be accessed
+ * @block: the register block to be accessed
  *
- * Call before operating upon a core via the 'other' register region in
- * order to prevent the region being moved during access. Must be followed
- * by a call to mips_cm_unlock_other.
+ * Configure the redirect/other region for the local core/VP (depending upon
+ * the CM revision) to target the specified @cluster, @core, @vp & register
+ * @block. Must be called before using the redirect/other region, and followed
+ * by a call to mips_cm_unlock_other() when access to the redirect/other region
+ * is complete.
+ *
+ * This function acquires a spinlock such that code between it &
+ * mips_cm_unlock_other() calls cannot be pre-empted by anything which may
+ * reconfigure the redirect/other region, and cannot be interfered with by
+ * another VP in the core. As such calls to this function should not be nested.
  */
-extern void mips_cm_lock_other(unsigned int core, unsigned int vp);
+extern void mips_cm_lock_other(unsigned int cluster, unsigned int core,
+                               unsigned int vp, unsigned int block);
 
 /**
- * mips_cm_unlock_other - unlock access to another core
+ * mips_cm_unlock_other - unlock access to redirect/other region
  *
- * Call after operating upon another core via the 'other' register region.
- * Must be called after mips_cm_lock_other.
+ * Must be called after mips_cm_lock_other() once all required access to the
+ * redirect/other region has been completed.
  */
 extern void mips_cm_unlock_other(void);
 
 #else /* !CONFIG_MIPS_CM */
 
-static inline void mips_cm_lock_other(unsigned int core, unsigned int vp) { }
+static inline void mips_cm_lock_other(unsigned int cluster, unsigned int core,
+                                      unsigned int vp, unsigned int block) { }
 static inline void mips_cm_unlock_other(void) { }
 
 #endif /* !CONFIG_MIPS_CM */
 
+/**
+ * mips_cm_lock_other_cpu - lock access to redirect/other region
+ * @cpu: the other CPU whose register we want to access
+ *
+ * Configure the redirect/other region for the local core/VP (depending upon
+ * the CM revision) to target the specified @cpu & register @block. This is
+ * equivalent to calling mips_cm_lock_other() but accepts a Linux CPU number
+ * for convenience.
+ */
+static inline void mips_cm_lock_other_cpu(unsigned int cpu, unsigned int block)
+{
+        struct cpuinfo_mips *d = &cpu_data[cpu];
+
+        mips_cm_lock_other(cpu_cluster(d), cpu_core(d), cpu_vpe_id(d), block);
+}
+
 #endif /* __MIPS_ASM_MIPS_CM_H__ */
diff --git a/arch/mips/include/asm/mips-cpc.h b/arch/mips/include/asm/mips-cpc.h
index 8c519f9827a3..f885051a8378 100644
--- a/arch/mips/include/asm/mips-cpc.h
+++ b/arch/mips/include/asm/mips-cpc.h
@@ -8,11 +8,15 @@
  * option) any later version.
  */
 
+#ifndef __MIPS_ASM_MIPS_CPS_H__
+# error Please include asm/mips-cps.h rather than asm/mips-cpc.h
+#endif
+
 #ifndef __MIPS_ASM_MIPS_CPC_H__
 #define __MIPS_ASM_MIPS_CPC_H__
 
-#include <linux/io.h>
-#include <linux/types.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
 
 /* The base address of the CPC registers */
 extern void __iomem *mips_cpc_base;
@@ -61,89 +65,92 @@ static inline bool mips_cpc_present(void)
 #define MIPS_CPC_CLCB_OFS       0x2000
 #define MIPS_CPC_COCB_OFS       0x4000
 
-/* Macros to ease the creation of register access functions */
-#define BUILD_CPC_R_(name, off)                                 \
-static inline u32 *addr_cpc_##name(void)                        \
-{                                                               \
-        return (u32 *)(mips_cpc_base + (off));                  \
-}                                                               \
-                                                                \
-static inline u32 read_cpc_##name(void)                         \
-{                                                               \
-        return __raw_readl(mips_cpc_base + (off));              \
-}
-
-#define BUILD_CPC__W(name, off) \
-static inline void write_cpc_##name(u32 value)                  \
-{                                                               \
-        __raw_writel(value, mips_cpc_base + (off));             \
-}
-
-#define BUILD_CPC_RW(name, off)                                 \
-        BUILD_CPC_R_(name, off)                                 \
-        BUILD_CPC__W(name, off)
-
-#define BUILD_CPC_Cx_R_(name, off)                              \
-        BUILD_CPC_R_(cl_##name, MIPS_CPC_CLCB_OFS + (off))      \
-        BUILD_CPC_R_(co_##name, MIPS_CPC_COCB_OFS + (off))
-
-#define BUILD_CPC_Cx__W(name, off)                              \
-        BUILD_CPC__W(cl_##name, MIPS_CPC_CLCB_OFS + (off))      \
-        BUILD_CPC__W(co_##name, MIPS_CPC_COCB_OFS + (off))
-
-#define BUILD_CPC_Cx_RW(name, off)                              \
-        BUILD_CPC_Cx_R_(name, off)                              \
-        BUILD_CPC_Cx__W(name, off)
-
-/* GCB register accessor functions */
-BUILD_CPC_RW(access,            MIPS_CPC_GCB_OFS + 0x00)
-BUILD_CPC_RW(seqdel,            MIPS_CPC_GCB_OFS + 0x08)
-BUILD_CPC_RW(rail,              MIPS_CPC_GCB_OFS + 0x10)
-BUILD_CPC_RW(resetlen,          MIPS_CPC_GCB_OFS + 0x18)
-BUILD_CPC_R_(revision,          MIPS_CPC_GCB_OFS + 0x20)
-
-/* Core Local & Core Other accessor functions */
-BUILD_CPC_Cx_RW(cmd,            0x00)
-BUILD_CPC_Cx_RW(stat_conf,      0x08)
-BUILD_CPC_Cx_RW(other,          0x10)
-BUILD_CPC_Cx_RW(vp_stop,        0x20)
-BUILD_CPC_Cx_RW(vp_run,         0x28)
-BUILD_CPC_Cx_RW(vp_running,     0x30)
-
-/* CPC_Cx_CMD register fields */
-#define CPC_Cx_CMD_SHF                          0
-#define CPC_Cx_CMD_MSK                          (_ULCAST_(0xf) << 0)
-#define  CPC_Cx_CMD_CLOCKOFF                    (_ULCAST_(0x1) << 0)
-#define  CPC_Cx_CMD_PWRDOWN                     (_ULCAST_(0x2) << 0)
-#define  CPC_Cx_CMD_PWRUP                       (_ULCAST_(0x3) << 0)
-#define  CPC_Cx_CMD_RESET                       (_ULCAST_(0x4) << 0)
-
-/* CPC_Cx_STAT_CONF register fields */
-#define CPC_Cx_STAT_CONF_PWRUPE_SHF             23
-#define CPC_Cx_STAT_CONF_PWRUPE_MSK             (_ULCAST_(0x1) << 23)
-#define CPC_Cx_STAT_CONF_SEQSTATE_SHF           19
-#define CPC_Cx_STAT_CONF_SEQSTATE_MSK           (_ULCAST_(0xf) << 19)
-#define  CPC_Cx_STAT_CONF_SEQSTATE_D0           (_ULCAST_(0x0) << 19)
-#define  CPC_Cx_STAT_CONF_SEQSTATE_U0           (_ULCAST_(0x1) << 19)
-#define  CPC_Cx_STAT_CONF_SEQSTATE_U1           (_ULCAST_(0x2) << 19)
-#define  CPC_Cx_STAT_CONF_SEQSTATE_U2           (_ULCAST_(0x3) << 19)
-#define  CPC_Cx_STAT_CONF_SEQSTATE_U3           (_ULCAST_(0x4) << 19)
-#define  CPC_Cx_STAT_CONF_SEQSTATE_U4           (_ULCAST_(0x5) << 19)
-#define  CPC_Cx_STAT_CONF_SEQSTATE_U5           (_ULCAST_(0x6) << 19)
-#define  CPC_Cx_STAT_CONF_SEQSTATE_U6           (_ULCAST_(0x7) << 19)
-#define  CPC_Cx_STAT_CONF_SEQSTATE_D1           (_ULCAST_(0x8) << 19)
-#define  CPC_Cx_STAT_CONF_SEQSTATE_D3           (_ULCAST_(0x9) << 19)
-#define  CPC_Cx_STAT_CONF_SEQSTATE_D2           (_ULCAST_(0xa) << 19)
-#define CPC_Cx_STAT_CONF_CLKGAT_IMPL_SHF        17
-#define CPC_Cx_STAT_CONF_CLKGAT_IMPL_MSK        (_ULCAST_(0x1) << 17)
-#define CPC_Cx_STAT_CONF_PWRDN_IMPL_SHF         16
-#define CPC_Cx_STAT_CONF_PWRDN_IMPL_MSK         (_ULCAST_(0x1) << 16)
-#define CPC_Cx_STAT_CONF_EJTAG_PROBE_SHF        15
-#define CPC_Cx_STAT_CONF_EJTAG_PROBE_MSK        (_ULCAST_(0x1) << 15)
-
-/* CPC_Cx_OTHER register fields */
-#define CPC_Cx_OTHER_CORENUM_SHF                16
-#define CPC_Cx_OTHER_CORENUM_MSK                (_ULCAST_(0xff) << 16)
+#define CPC_ACCESSOR_RO(sz, off, name)                                  \
+        CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_GCB_OFS + off, name)          \
+        CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_COCB_OFS + off, redir_##name)
+
+#define CPC_ACCESSOR_RW(sz, off, name)                                  \
+        CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_GCB_OFS + off, name)          \
+        CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_COCB_OFS + off, redir_##name)
+
+#define CPC_CX_ACCESSOR_RO(sz, off, name)                               \
+        CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_CLCB_OFS + off, cl_##name)    \
+        CPS_ACCESSOR_RO(cpc, sz, MIPS_CPC_COCB_OFS + off, co_##name)
+
+#define CPC_CX_ACCESSOR_RW(sz, off, name)                               \
+        CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_CLCB_OFS + off, cl_##name)    \
+        CPS_ACCESSOR_RW(cpc, sz, MIPS_CPC_COCB_OFS + off, co_##name)
+
+/* CPC_ACCESS - Control core/IOCU access to CPC registers prior to CM 3 */
+CPC_ACCESSOR_RW(32, 0x000, access)
+
+/* CPC_SEQDEL - Configure delays between command sequencer steps */
+CPC_ACCESSOR_RW(32, 0x008, seqdel)
+
+/* CPC_RAIL - Configure the delay from rail power-up to stability */
+CPC_ACCESSOR_RW(32, 0x010, rail)
+
+/* CPC_RESETLEN - Configure the length of reset sequences */
+CPC_ACCESSOR_RW(32, 0x018, resetlen)
+
+/* CPC_REVISION - Indicates the revisison of the CPC */
+CPC_ACCESSOR_RO(32, 0x020, revision)
+
+/* CPC_PWRUP_CTL - Control power to the Coherence Manager (CM) */
+CPC_ACCESSOR_RW(32, 0x030, pwrup_ctl)
+#define CPC_PWRUP_CTL_CM_PWRUP                  BIT(0)
+
+/* CPC_CONFIG - Mirrors GCR_CONFIG */
+CPC_ACCESSOR_RW(64, 0x138, config)
+
+/* CPC_SYS_CONFIG - Control cluster endianness */
+CPC_ACCESSOR_RW(32, 0x140, sys_config)
+#define CPC_SYS_CONFIG_BE_IMMEDIATE             BIT(2)
+#define CPC_SYS_CONFIG_BE_STATUS                BIT(1)
+#define CPC_SYS_CONFIG_BE                       BIT(0)
+
+/* CPC_Cx_CMD - Instruct the CPC to take action on a core */
+CPC_CX_ACCESSOR_RW(32, 0x000, cmd)
+#define CPC_Cx_CMD                              GENMASK(3, 0)
+#define  CPC_Cx_CMD_CLOCKOFF                    0x1
+#define  CPC_Cx_CMD_PWRDOWN                     0x2
+#define  CPC_Cx_CMD_PWRUP                       0x3
+#define  CPC_Cx_CMD_RESET                       0x4
+
+/* CPC_Cx_STAT_CONF - Indicates core configuration & state */
+CPC_CX_ACCESSOR_RW(32, 0x008, stat_conf)
+#define CPC_Cx_STAT_CONF_PWRUPE                 BIT(23)
+#define CPC_Cx_STAT_CONF_SEQSTATE               GENMASK(22, 19)
+#define  CPC_Cx_STAT_CONF_SEQSTATE_D0           0x0
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U0           0x1
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U1           0x2
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U2           0x3
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U3           0x4
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U4           0x5
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U5           0x6
+#define  CPC_Cx_STAT_CONF_SEQSTATE_U6           0x7
+#define  CPC_Cx_STAT_CONF_SEQSTATE_D1           0x8
+#define  CPC_Cx_STAT_CONF_SEQSTATE_D3           0x9
+#define  CPC_Cx_STAT_CONF_SEQSTATE_D2           0xa
+#define CPC_Cx_STAT_CONF_CLKGAT_IMPL            BIT(17)
+#define CPC_Cx_STAT_CONF_PWRDN_IMPL             BIT(16)
+#define CPC_Cx_STAT_CONF_EJTAG_PROBE            BIT(15)
+
+/* CPC_Cx_OTHER - Configure the core-other register block prior to CM 3 */
+CPC_CX_ACCESSOR_RW(32, 0x010, other)
+#define CPC_Cx_OTHER_CORENUM                    GENMASK(23, 16)
+
+/* CPC_Cx_VP_STOP - Stop Virtual Processors (VPs) within a core from running */
+CPC_CX_ACCESSOR_RW(32, 0x020, vp_stop)
+
+/* CPC_Cx_VP_START - Start Virtual Processors (VPs) within a core running */
+CPC_CX_ACCESSOR_RW(32, 0x028, vp_run)
+
+/* CPC_Cx_VP_RUNNING - Indicate which Virtual Processors (VPs) are running */
+CPC_CX_ACCESSOR_RW(32, 0x030, vp_running)
+
+/* CPC_Cx_CONFIG - Mirrors GCR_Cx_CONFIG */
+CPC_CX_ACCESSOR_RW(32, 0x090, config)
 
 #ifdef CONFIG_MIPS_CPC
 
diff --git a/arch/mips/include/asm/mips-cps.h b/arch/mips/include/asm/mips-cps.h
new file mode 100644
index 000000000000..bf02b5070a98
--- /dev/null
+++ b/arch/mips/include/asm/mips-cps.h
@@ -0,0 +1,240 @@
+/*
+ * Copyright (C) 2017 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MIPS_ASM_MIPS_CPS_H__
+#define __MIPS_ASM_MIPS_CPS_H__
+
+#include <linux/io.h>
+#include <linux/types.h>
+
+extern unsigned long __cps_access_bad_size(void)
+        __compiletime_error("Bad size for CPS accessor");
+
+#define CPS_ACCESSOR_A(unit, off, name)                                 \
+static inline void *addr_##unit##_##name(void)                          \
+{                                                                       \
+        return mips_##unit##_base + (off);                              \
+}
+
+#define CPS_ACCESSOR_R(unit, sz, name)                                  \
+static inline uint##sz##_t read_##unit##_##name(void)                   \
+{                                                                       \
+        uint64_t val64;                                                 \
+                                                                        \
+        switch (sz) {                                                   \
+        case 32:                                                        \
+                return __raw_readl(addr_##unit##_##name());             \
+                                                                        \
+        case 64:                                                        \
+                if (mips_cm_is64)                                       \
+                        return __raw_readq(addr_##unit##_##name());     \
+                                                                        \
+                val64 = __raw_readl(addr_##unit##_##name() + 4);        \
+                val64 <<= 32;                                           \
+                val64 |= __raw_readl(addr_##unit##_##name());           \
+                return val64;                                           \
+                                                                        \
+        default:                                                        \
+                return __cps_access_bad_size();                         \
+        }                                                               \
+}
+
+#define CPS_ACCESSOR_W(unit, sz, name)                                  \
+static inline void write_##unit##_##name(uint##sz##_t val)              \
+{                                                                       \
+        switch (sz) {                                                   \
+        case 32:                                                        \
+                __raw_writel(val, addr_##unit##_##name());              \
+                break;                                                  \
+                                                                        \
+        case 64:                                                        \
+                if (mips_cm_is64) {                                     \
+                        __raw_writeq(val, addr_##unit##_##name());      \
+                        break;                                          \
+                }                                                       \
+                                                                        \
+                __raw_writel((uint64_t)val >> 32,                       \
+                             addr_##unit##_##name() + 4);               \
+                __raw_writel(val, addr_##unit##_##name());              \
+                break;                                                  \
+                                                                        \
+        default:                                                        \
+                __cps_access_bad_size();                                \
+                break;                                                  \
+        }                                                               \
+}
+
+#define CPS_ACCESSOR_M(unit, sz, name)                                  \
+static inline void change_##unit##_##name(uint##sz##_t mask,            \
+                                          uint##sz##_t val)             \
+{                                                                       \
+        uint##sz##_t reg_val = read_##unit##_##name();                  \
+        reg_val &= ~mask;                                               \
+        reg_val |= val;                                                 \
+        write_##unit##_##name(reg_val);                                 \
+}                                                                       \
+                                                                        \
+static inline void set_##unit##_##name(uint##sz##_t val)                \
+{                                                                       \
+        change_##unit##_##name(val, val);                               \
+}                                                                       \
+                                                                        \
+static inline void clear_##unit##_##name(uint##sz##_t val)              \
+{                                                                       \
+        change_##unit##_##name(val, 0);                                 \
+}
+
+#define CPS_ACCESSOR_RO(unit, sz, off, name)                            \
+        CPS_ACCESSOR_A(unit, off, name)                                 \
+        CPS_ACCESSOR_R(unit, sz, name)
+
+#define CPS_ACCESSOR_WO(unit, sz, off, name)                            \
+        CPS_ACCESSOR_A(unit, off, name)                                 \
+        CPS_ACCESSOR_W(unit, sz, name)
+
+#define CPS_ACCESSOR_RW(unit, sz, off, name)                            \
+        CPS_ACCESSOR_A(unit, off, name)                                 \
+        CPS_ACCESSOR_R(unit, sz, name)                                  \
+        CPS_ACCESSOR_W(unit, sz, name)                                  \
+        CPS_ACCESSOR_M(unit, sz, name)
+
+#include <asm/mips-cm.h>
+#include <asm/mips-cpc.h>
+#include <asm/mips-gic.h>
+
+/**
+ * mips_cps_numclusters - return the number of clusters present in the system
+ *
+ * Returns the number of clusters in the system.
+ */
+static inline unsigned int mips_cps_numclusters(void)
+{
+        unsigned int num_clusters;
+
+        if (mips_cm_revision() < CM_REV_CM3_5)
+                return 1;
+
+        num_clusters = read_gcr_config() & CM_GCR_CONFIG_NUM_CLUSTERS;
+        num_clusters >>= __ffs(CM_GCR_CONFIG_NUM_CLUSTERS);
+        return num_clusters;
+}
+
+/**
+ * mips_cps_cluster_config - return (GCR|CPC)_CONFIG from a cluster
+ * @cluster: the ID of the cluster whose config we want
+ *
+ * Read the value of GCR_CONFIG (or its CPC_CONFIG mirror) from a @cluster.
+ *
+ * Returns the value of GCR_CONFIG.
+ */
+static inline uint64_t mips_cps_cluster_config(unsigned int cluster)
+{
+        uint64_t config;
+
+        if (mips_cm_revision() < CM_REV_CM3_5) {
+                /*
+                 * Prior to CM 3.5 we don't have the notion of multiple
+                 * clusters so we can trivially read the GCR_CONFIG register
+                 * within this cluster.
+                 */
+                WARN_ON(cluster != 0);
+                config = read_gcr_config();
+        } else {
+                /*
+                 * From CM 3.5 onwards we read the CPC_CONFIG mirror of
+                 * GCR_CONFIG via the redirect region, since the CPC is always
+                 * powered up allowing us not to need to power up the CM.
+                 */
+                mips_cm_lock_other(cluster, 0, 0, CM_GCR_Cx_OTHER_BLOCK_GLOBAL);
+                config = read_cpc_redir_config();
+                mips_cm_unlock_other();
+        }
+
+        return config;
+}
+
+/**
+ * mips_cps_numcores - return the number of cores present in a cluster
+ * @cluster: the ID of the cluster whose core count we want
+ *
+ * Returns the value of the PCORES field of the GCR_CONFIG register plus 1, or
+ * zero if no Coherence Manager is present.
+ */
+static inline unsigned int mips_cps_numcores(unsigned int cluster)
+{
+        if (!mips_cm_present())
+                return 0;
+
+        /* Add one before masking to handle 0xff indicating no cores */
+        return (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;
+}
+
+/**
+ * mips_cps_numiocu - return the number of IOCUs present in a cluster
+ * @cluster: the ID of the cluster whose IOCU count we want
+ *
+ * Returns the value of the NUMIOCU field of the GCR_CONFIG register, or zero
+ * if no Coherence Manager is present.
+ */
+static inline unsigned int mips_cps_numiocu(unsigned int cluster)
+{
+        unsigned int num_iocu;
+
+        if (!mips_cm_present())
+                return 0;
+
+        num_iocu = mips_cps_cluster_config(cluster) & CM_GCR_CONFIG_NUMIOCU;
+        num_iocu >>= __ffs(CM_GCR_CONFIG_NUMIOCU);
+        return num_iocu;
+}
+
+/**
+ * mips_cps_numvps - return the number of VPs (threads) supported by a core
+ * @cluster: the ID of the cluster containing the core we want to examine
+ * @core: the ID of the core whose VP count we want
+ *
+ * Returns the number of Virtual Processors (VPs, ie. hardware threads) that
+ * are supported by the given @core in the given @cluster. If the core or the
+ * kernel do not support hardware mutlti-threading this returns 1.
+ */
+static inline unsigned int mips_cps_numvps(unsigned int cluster, unsigned int core)
+{
+        unsigned int cfg;
+
+        if (!mips_cm_present())
+                return 1;
+
+        if ((!IS_ENABLED(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
+                && (!IS_ENABLED(CONFIG_CPU_MIPSR6) || !cpu_has_vp))
+                return 1;
+
+        mips_cm_lock_other(cluster, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
+
+        if (mips_cm_revision() < CM_REV_CM3_5) {
+                /*
+                 * Prior to CM 3.5 we can only have one cluster & don't have
+                 * CPC_Cx_CONFIG, so we read GCR_Cx_CONFIG.
+                 */
+                cfg = read_gcr_co_config();
+        } else {
+                /*
+                 * From CM 3.5 onwards we read CPC_Cx_CONFIG because the CPC is
+                 * always powered, which allows us to not worry about powering
+                 * up the cluster's CM here.
+                 */
+                cfg = read_cpc_co_config();
+        }
+
+        mips_cm_unlock_other();
+
+        return (cfg + 1) & CM_GCR_Cx_CONFIG_PVPE;
+}
+
+#endif /* __MIPS_ASM_MIPS_CPS_H__ */
diff --git a/arch/mips/include/asm/mips-gic.h b/arch/mips/include/asm/mips-gic.h
new file mode 100644
index 000000000000..a2badf572632
--- /dev/null
+++ b/arch/mips/include/asm/mips-gic.h
@@ -0,0 +1,347 @@
+/*
+ * Copyright (C) 2017 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MIPS_ASM_MIPS_CPS_H__
+# error Please include asm/mips-cps.h rather than asm/mips-gic.h
+#endif
+
+#ifndef __MIPS_ASM_MIPS_GIC_H__
+#define __MIPS_ASM_MIPS_GIC_H__
+
+#include <linux/bitops.h>
+
+/* The base address of the GIC registers */
+extern void __iomem *mips_gic_base;
+
+/* Offsets from the GIC base address to various control blocks */
+#define MIPS_GIC_SHARED_OFS     0x00000
+#define MIPS_GIC_SHARED_SZ      0x08000
+#define MIPS_GIC_LOCAL_OFS      0x08000
+#define MIPS_GIC_LOCAL_SZ       0x04000
+#define MIPS_GIC_REDIR_OFS      0x0c000
+#define MIPS_GIC_REDIR_SZ       0x04000
+#define MIPS_GIC_USER_OFS       0x10000
+#define MIPS_GIC_USER_SZ        0x10000
+
+/* For read-only shared registers */
+#define GIC_ACCESSOR_RO(sz, off, name)                                  \
+        CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
+
+/* For read-write shared registers */
+#define GIC_ACCESSOR_RW(sz, off, name)                                  \
+        CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_SHARED_OFS + off, name)
+
+/* For read-only local registers */
+#define GIC_VX_ACCESSOR_RO(sz, off, name)                               \
+        CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name)   \
+        CPS_ACCESSOR_RO(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
+
+/* For read-write local registers */
+#define GIC_VX_ACCESSOR_RW(sz, off, name)                               \
+        CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_LOCAL_OFS + off, vl_##name)   \
+        CPS_ACCESSOR_RW(gic, sz, MIPS_GIC_REDIR_OFS + off, vo_##name)
+
+/* For read-only shared per-interrupt registers */
+#define GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name)                 \
+static inline void __iomem *addr_gic_##name(unsigned int intr)          \
+{                                                                       \
+        return mips_gic_base + (off) + (intr * (stride));               \
+}                                                                       \
+                                                                        \
+static inline unsigned int read_gic_##name(unsigned int intr)           \
+{                                                                       \
+        BUILD_BUG_ON(sz != 32);                                         \
+        return __raw_readl(addr_gic_##name(intr));                      \
+}
+
+/* For read-write shared per-interrupt registers */
+#define GIC_ACCESSOR_RW_INTR_REG(sz, off, stride, name)                 \
+        GIC_ACCESSOR_RO_INTR_REG(sz, off, stride, name)                 \
+                                                                        \
+static inline void write_gic_##name(unsigned int intr,                  \
+                                    unsigned int val)                   \
+{                                                                       \
+        BUILD_BUG_ON(sz != 32);                                         \
+        __raw_writel(val, addr_gic_##name(intr));                       \
+}
+
+/* For read-only local per-interrupt registers */
+#define GIC_VX_ACCESSOR_RO_INTR_REG(sz, off, stride, name)              \
+        GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off,          \
+                                 stride, vl_##name)                     \
+        GIC_ACCESSOR_RO_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off,          \
+                                 stride, vo_##name)
+
+/* For read-write local per-interrupt registers */
+#define GIC_VX_ACCESSOR_RW_INTR_REG(sz, off, stride, name)              \
+        GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_LOCAL_OFS + off,          \
+                                 stride, vl_##name)                     \
+        GIC_ACCESSOR_RW_INTR_REG(sz, MIPS_GIC_REDIR_OFS + off,          \
+                                 stride, vo_##name)
+
+/* For read-only shared bit-per-interrupt registers */
+#define GIC_ACCESSOR_RO_INTR_BIT(off, name)                             \
+static inline void __iomem *addr_gic_##name(void)                       \
+{                                                                       \
+        return mips_gic_base + (off);                                   \
+}                                                                       \
+                                                                        \
+static inline unsigned int read_gic_##name(unsigned int intr)           \
+{                                                                       \
+        void __iomem *addr = addr_gic_##name();                         \
+        unsigned int val;                                               \
+                                                                        \
+        if (mips_cm_is64) {                                             \
+                addr += (intr / 64) * sizeof(uint64_t);                 \
+                val = __raw_readq(addr) >> intr % 64;                   \
+        } else {                                                        \
+                addr += (intr / 32) * sizeof(uint32_t);                 \
+                val = __raw_readl(addr) >> intr % 32;                   \
+        }                                                               \
+                                                                        \
+        return val & 0x1;                                               \
+}
+
+/* For read-write shared bit-per-interrupt registers */
+#define GIC_ACCESSOR_RW_INTR_BIT(off, name)                             \
+        GIC_ACCESSOR_RO_INTR_BIT(off, name)                             \
+                                                                        \
+static inline void write_gic_##name(unsigned int intr)                  \
+{                                                                       \
+        void __iomem *addr = addr_gic_##name();                         \
+                                                                        \
+        if (mips_cm_is64) {                                             \
+                addr += (intr / 64) * sizeof(uint64_t);                 \
+                __raw_writeq(BIT(intr % 64), addr);                     \
+        } else {                                                        \
+                addr += (intr / 32) * sizeof(uint32_t);                 \
+                __raw_writel(BIT(intr % 32), addr);                     \
+        }                                                               \
+}                                                                       \
+                                                                        \
+static inline void change_gic_##name(unsigned int intr,                 \
+                                     unsigned int val)                  \
+{                                                                       \
+        void __iomem *addr = addr_gic_##name();                         \
+                                                                        \
+        if (mips_cm_is64) {                                             \
+                uint64_t _val;                                          \
+                                                                        \
+                addr += (intr / 64) * sizeof(uint64_t);                 \
+                _val = __raw_readq(addr);                               \
+                _val &= ~BIT_ULL(intr % 64);                            \
+                _val |= (uint64_t)val << (intr % 64);                   \
+                __raw_writeq(_val, addr);                               \
+        } else {                                                        \
+                uint32_t _val;                                          \
+                                                                        \
+                addr += (intr / 32) * sizeof(uint32_t);                 \
+                _val = __raw_readl(addr);                               \
+                _val &= ~BIT(intr % 32);                                \
+                _val |= val << (intr % 32);                             \
+                __raw_writel(_val, addr);                               \
+        }                                                               \
+}
+
+/* For read-only local bit-per-interrupt registers */
+#define GIC_VX_ACCESSOR_RO_INTR_BIT(sz, off, name)                      \
+        GIC_ACCESSOR_RO_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off,          \
+                                 vl_##name)                             \
+        GIC_ACCESSOR_RO_INTR_BIT(sz, MIPS_GIC_REDIR_OFS + off,          \
+                                 vo_##name)
+
+/* For read-write local bit-per-interrupt registers */
+#define GIC_VX_ACCESSOR_RW_INTR_BIT(sz, off, name)                      \
+        GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_LOCAL_OFS + off,          \
+                                 vl_##name)                             \
+        GIC_ACCESSOR_RW_INTR_BIT(sz, MIPS_GIC_REDIR_OFS + off,          \
+                                 vo_##name)
+
+/* GIC_SH_CONFIG - Information about the GIC configuration */
+GIC_ACCESSOR_RW(32, 0x000, config)
+#define GIC_CONFIG_COUNTSTOP            BIT(28)
+#define GIC_CONFIG_COUNTBITS            GENMASK(27, 24)
+#define GIC_CONFIG_NUMINTERRUPTS        GENMASK(23, 16)
+#define GIC_CONFIG_PVPS                 GENMASK(6, 0)
+
+/* GIC_SH_COUNTER - Shared global counter value */
+GIC_ACCESSOR_RW(64, 0x010, counter)
+GIC_ACCESSOR_RW(32, 0x010, counter_32l)
+GIC_ACCESSOR_RW(32, 0x014, counter_32h)
+
+/* GIC_SH_POL_* - Configures interrupt polarity */
+GIC_ACCESSOR_RW_INTR_BIT(0x100, pol)
+#define GIC_POL_ACTIVE_LOW              0       /* when level triggered */
+#define GIC_POL_ACTIVE_HIGH             1       /* when level triggered */
+#define GIC_POL_FALLING_EDGE            0       /* when single-edge triggered */
+#define GIC_POL_RISING_EDGE             1       /* when single-edge triggered */
+
+/* GIC_SH_TRIG_* - Configures interrupts to be edge or level triggered */
+GIC_ACCESSOR_RW_INTR_BIT(0x180, trig)
+#define GIC_TRIG_LEVEL                  0
+#define GIC_TRIG_EDGE                   1
+
+/* GIC_SH_DUAL_* - Configures whether interrupts trigger on both edges */
+GIC_ACCESSOR_RW_INTR_BIT(0x200, dual)
+#define GIC_DUAL_SINGLE                 0       /* when edge-triggered */
+#define GIC_DUAL_DUAL                   1       /* when edge-triggered */
+
+/* GIC_SH_WEDGE - Write an 'edge', ie. trigger an interrupt */
+GIC_ACCESSOR_RW(32, 0x280, wedge)
+#define GIC_WEDGE_RW                    BIT(31)
+#define GIC_WEDGE_INTR                  GENMASK(7, 0)
+
+/* GIC_SH_RMASK_* - Reset/clear shared interrupt mask bits */
+GIC_ACCESSOR_RW_INTR_BIT(0x300, rmask)
+
+/* GIC_SH_SMASK_* - Set shared interrupt mask bits */
+GIC_ACCESSOR_RW_INTR_BIT(0x380, smask)
+
+/* GIC_SH_MASK_* - Read the current shared interrupt mask */
+GIC_ACCESSOR_RO_INTR_BIT(0x400, mask)
+
+/* GIC_SH_PEND_* - Read currently pending shared interrupts */
+GIC_ACCESSOR_RO_INTR_BIT(0x480, pend)
+
+/* GIC_SH_MAPx_PIN - Map shared interrupts to a particular CPU pin */
+GIC_ACCESSOR_RW_INTR_REG(32, 0x500, 0x4, map_pin)
+#define GIC_MAP_PIN_MAP_TO_PIN          BIT(31)
+#define GIC_MAP_PIN_MAP_TO_NMI          BIT(30)
+#define GIC_MAP_PIN_MAP                 GENMASK(5, 0)
+
+/* GIC_SH_MAPx_VP - Map shared interrupts to a particular Virtual Processor */
+GIC_ACCESSOR_RW_INTR_REG(32, 0x2000, 0x20, map_vp)
+
+/* GIC_Vx_CTL - VP-level interrupt control */
+GIC_VX_ACCESSOR_RW(32, 0x000, ctl)
+#define GIC_VX_CTL_FDC_ROUTABLE         BIT(4)
+#define GIC_VX_CTL_SWINT_ROUTABLE       BIT(3)
+#define GIC_VX_CTL_PERFCNT_ROUTABLE     BIT(2)
+#define GIC_VX_CTL_TIMER_ROUTABLE       BIT(1)
+#define GIC_VX_CTL_EIC                  BIT(0)
+
+/* GIC_Vx_PEND - Read currently pending local interrupts */
+GIC_VX_ACCESSOR_RO(32, 0x004, pend)
+
+/* GIC_Vx_MASK - Read the current local interrupt mask */
+GIC_VX_ACCESSOR_RO(32, 0x008, mask)
+
+/* GIC_Vx_RMASK - Reset/clear local interrupt mask bits */
+GIC_VX_ACCESSOR_RW(32, 0x00c, rmask)
+
+/* GIC_Vx_SMASK - Set local interrupt mask bits */
+GIC_VX_ACCESSOR_RW(32, 0x010, smask)
+
+/* GIC_Vx_*_MAP - Route local interrupts to the desired pins */
+GIC_VX_ACCESSOR_RW_INTR_REG(32, 0x040, 0x4, map)
+
+/* GIC_Vx_WD_MAP - Route the local watchdog timer interrupt */
+GIC_VX_ACCESSOR_RW(32, 0x040, wd_map)
+
+/* GIC_Vx_COMPARE_MAP - Route the local count/compare interrupt */
+GIC_VX_ACCESSOR_RW(32, 0x044, compare_map)
+
+/* GIC_Vx_TIMER_MAP - Route the local CPU timer (cp0 count/compare) interrupt */
+GIC_VX_ACCESSOR_RW(32, 0x048, timer_map)
+
+/* GIC_Vx_FDC_MAP - Route the local fast debug channel interrupt */
+GIC_VX_ACCESSOR_RW(32, 0x04c, fdc_map)
+
+/* GIC_Vx_PERFCTR_MAP - Route the local performance counter interrupt */
+GIC_VX_ACCESSOR_RW(32, 0x050, perfctr_map)
+
+/* GIC_Vx_SWINT0_MAP - Route the local software interrupt 0 */
+GIC_VX_ACCESSOR_RW(32, 0x054, swint0_map)
+
+/* GIC_Vx_SWINT1_MAP - Route the local software interrupt 1 */
+GIC_VX_ACCESSOR_RW(32, 0x058, swint1_map)
+
+/* GIC_Vx_OTHER - Configure access to other Virtual Processor registers */
+GIC_VX_ACCESSOR_RW(32, 0x080, other)
+#define GIC_VX_OTHER_VPNUM              GENMASK(5, 0)
+
+/* GIC_Vx_IDENT - Retrieve the local Virtual Processor's ID */
+GIC_VX_ACCESSOR_RO(32, 0x088, ident)
+#define GIC_VX_IDENT_VPNUM              GENMASK(5, 0)
+
+/* GIC_Vx_COMPARE - Value to compare with GIC_SH_COUNTER */
+GIC_VX_ACCESSOR_RW(64, 0x0a0, compare)
+
+/* GIC_Vx_EIC_SHADOW_SET_BASE - Set shadow register set for each interrupt */
+GIC_VX_ACCESSOR_RW_INTR_REG(32, 0x100, 0x4, eic_shadow_set)
+
+/**
+ * enum mips_gic_local_interrupt - GIC local interrupts
+ * @GIC_LOCAL_INT_WD: GIC watchdog timer interrupt
+ * @GIC_LOCAL_INT_COMPARE: GIC count/compare interrupt
+ * @GIC_LOCAL_INT_TIMER: CP0 count/compare interrupt
+ * @GIC_LOCAL_INT_PERFCTR: Performance counter interrupt
+ * @GIC_LOCAL_INT_SWINT0: Software interrupt 0
+ * @GIC_LOCAL_INT_SWINT1: Software interrupt 1
+ * @GIC_LOCAL_INT_FDC: Fast debug channel interrupt
+ * @GIC_NUM_LOCAL_INTRS: The number of local interrupts
+ *
+ * Enumerates interrupts provided by the GIC that are local to a VP.
+ */
+enum mips_gic_local_interrupt {
+        GIC_LOCAL_INT_WD,
+        GIC_LOCAL_INT_COMPARE,
+        GIC_LOCAL_INT_TIMER,
+        GIC_LOCAL_INT_PERFCTR,
+        GIC_LOCAL_INT_SWINT0,
+        GIC_LOCAL_INT_SWINT1,
+        GIC_LOCAL_INT_FDC,
+        GIC_NUM_LOCAL_INTRS
+};
+
+/**
+ * mips_gic_present() - Determine whether a GIC is present
+ *
+ * Determines whether a MIPS Global Interrupt Controller (GIC) is present in
+ * the system that the kernel is running on.
+ *
+ * Return true if a GIC is present, else false.
+ */
+static inline bool mips_gic_present(void)
+{
+        return IS_ENABLED(CONFIG_MIPS_GIC) && mips_gic_base;
+}
+
+/**
+ * gic_get_c0_compare_int() - Return cp0 count/compare interrupt virq
+ *
+ * Determine the virq number to use for the coprocessor 0 count/compare
+ * interrupt, which may be routed via the GIC.
+ *
+ * Returns the virq number or a negative error number.
+ */
+extern int gic_get_c0_compare_int(void);
+
+/**
+ * gic_get_c0_perfcount_int() - Return performance counter interrupt virq
+ *
+ * Determine the virq number to use for CPU performance counter interrupts,
+ * which may be routed via the GIC.
+ *
+ * Returns the virq number or a negative error number.
+ */
+extern int gic_get_c0_perfcount_int(void);
+
+/**
+ * gic_get_c0_fdc_int() - Return fast debug channel interrupt virq
+ *
+ * Determine the virq number to use for fast debug channel (FDC) interrupts,
+ * which may be routed via the GIC.
+ *
+ * Returns the virq number or a negative error number.
+ */
+extern int gic_get_c0_fdc_int(void);
+
+#endif /* __MIPS_ASM_MIPS_CPS_H__ */
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index dbb0eceda2c6..e4ed1bc9a734 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -48,6 +48,7 @@
 #define CP0_ENTRYLO0 $2
 #define CP0_ENTRYLO1 $3
 #define CP0_CONF $3
+#define CP0_GLOBALNUMBER $3, 1
 #define CP0_CONTEXT $4
 #define CP0_PAGEMASK $5
 #define CP0_SEGCTL0 $5, 2
@@ -148,6 +149,16 @@
 #define MIPS_ENTRYLO_RI         (_ULCAST_(1) << (BITS_PER_LONG - 1))
 
 /*
+ * MIPSr6+ GlobalNumber register definitions
+ */
+#define MIPS_GLOBALNUMBER_VP_SHF        0
+#define MIPS_GLOBALNUMBER_VP            (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
+#define MIPS_GLOBALNUMBER_CORE_SHF      8
+#define MIPS_GLOBALNUMBER_CORE          (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
+#define MIPS_GLOBALNUMBER_CLUSTER_SHF   16
+#define MIPS_GLOBALNUMBER_CLUSTER       (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
+
+/*
  * Values for PageMask register
  */
 #ifdef CONFIG_CPU_VR41XX
@@ -1446,6 +1457,8 @@ do {									\
 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
 
+#define read_c0_globalnumber()  __read_32bit_c0_register($3, 1)
+
 #define read_c0_context()       __read_ulong_c0_register($4, 0)
 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
 
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index e51add184717..06552a965cf4 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -114,8 +114,6 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "R5432 "
 #elif defined CONFIG_CPU_R5500
 #define MODULE_PROC_FAMILY "R5500 "
-#elif defined CONFIG_CPU_R6000
-#define MODULE_PROC_FAMILY "R6000 "
 #elif defined CONFIG_CPU_NEVADA
 #define MODULE_PROC_FAMILY "NEVADA "
 #elif defined CONFIG_CPU_R8000
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
index e0717d10e650..a6e6cbebe046 100644
--- a/arch/mips/include/asm/netlogic/common.h
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -84,7 +84,7 @@ nlm_set_nmi_handler(void *handler)
  */
 void nlm_init_boot_cpu(void);
 unsigned int nlm_get_cpu_frequency(void);
-extern struct plat_smp_ops nlm_smp_ops;
+extern const struct plat_smp_ops nlm_smp_ops;
 extern char nlm_reset_entry[], nlm_reset_entry_end[];
 
 /* SWIOTLB */
diff --git a/arch/mips/include/asm/octeon/cvmx-boot-vector.h b/arch/mips/include/asm/octeon/cvmx-boot-vector.h
new file mode 100644
index 000000000000..8db08241d53c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-boot-vector.h
@@ -0,0 +1,53 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003-2017 Cavium, Inc.
+ */
+
+#ifndef __CVMX_BOOT_VECTOR_H__
+#define __CVMX_BOOT_VECTOR_H__
+
+#include <asm/octeon/octeon.h>
+
+/*
+ * The boot vector table is made up of an array of 1024 elements of
+ * struct cvmx_boot_vector_element.  There is one entry for each
+ * possible MIPS CPUNum, indexed by the CPUNum.
+ *
+ * Once cvmx_boot_vector_get() returns a non-NULL value (indicating
+ * success), NMI to a core will cause execution to transfer to the
+ * target_ptr location for that core's entry in the vector table.
+ *
+ * The struct cvmx_boot_vector_element fields app0, app1, and app2 can
+ * be used by the application that has set the target_ptr in any
+ * application specific manner, they are not touched by the vectoring
+ * code.
+ *
+ * The boot vector code clobbers the CP0_DESAVE register, and on
+ * OCTEON II and later CPUs also clobbers CP0_KScratch2.  All GP
+ * registers are preserved, except on pre-OCTEON II CPUs, where k1 is
+ * clobbered.
+ *
+ */
+
+
+/*
+ * Applications install the boot bus code in cvmx-boot-vector.c, which
+ * uses this magic:
+ */
+#define OCTEON_BOOT_MOVEABLE_MAGIC1 0xdb00110ad358eacdull
+
+struct cvmx_boot_vector_element {
+        /* kseg0 or xkphys address of target code. */
+        uint64_t target_ptr;
+        /* Three application specific arguments. */
+        uint64_t app0;
+        uint64_t app1;
+        uint64_t app2;
+};
+
+struct cvmx_boot_vector_element *cvmx_boot_vector_get(void);
+
+#endif /* __CVMX_BOOT_VECTOR_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h
index 374562507d0b..72d2e403a6e4 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootmem.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h
@@ -255,6 +255,34 @@ extern void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
                                             uint64_t max_addr, uint64_t align,
                                             char *name);
 
+/**
+ * Allocate if needed a block of memory from a specific range of the
+ * free list that was passed to the application by the bootloader, and
+ * assign it a name in the global named block table.  (part of the
+ * cvmx_bootmem_descriptor_t structure) Named blocks can later be
+ * freed.  If the requested name block is already allocated, return
+ * the pointer to block of memory.  If request cannot be satisfied
+ * within the address range specified, NULL is returned
+ *
+ * @param size   Size in bytes of block to allocate
+ * @param min_addr  minimum address of range
+ * @param max_addr  maximum address of range
+ * @param align  Alignment of memory to be allocated. (must be a power of 2)
+ * @param name   name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
+ * @param init   Initialization function
+ *
+ * The initialization function is optional, if omitted the named block
+ * is initialized to all zeros when it is created, i.e. once.
+ *
+ * @return pointer to block of memory, NULL on error
+ */
+void *cvmx_bootmem_alloc_named_range_once(uint64_t size,
+                                          uint64_t min_addr,
+                                          uint64_t max_addr,
+                                          uint64_t align,
+                                          char *name,
+                                          void (*init) (void *));
+
 extern int cvmx_bootmem_free_named(char *name);
 
 /**
diff --git a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
index 0dd0e40c96d4..6e61792d9248 100644
--- a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
@@ -128,6 +128,7 @@ static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset)
         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
         case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
                 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
         case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
         case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
@@ -143,6 +144,10 @@ static inline uint64_t CVMX_CIU_PP_POKEX(unsigned long offset)
                 return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
                 return CVMX_ADD_IO_SEG(0x0001070100100200ull) + (offset) * 8;
+        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001010000030000ull) + (offset) * 8;
         }
         return CVMX_ADD_IO_SEG(0x0001070000000580ull) + (offset) * 8;
 }
@@ -180,6 +185,7 @@ static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset)
         case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
         case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
         case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
                 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
         case OCTEON_CN31XX & OCTEON_FAMILY_MASK:
         case OCTEON_CN50XX & OCTEON_FAMILY_MASK:
@@ -195,6 +201,10 @@ static inline uint64_t CVMX_CIU_WDOGX(unsigned long offset)
                 return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
         case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
                 return CVMX_ADD_IO_SEG(0x0001070100100000ull) + (offset) * 8;
+        case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+        case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+                return CVMX_ADD_IO_SEG(0x0001010000020000ull) + (offset) * 8;
         }
         return CVMX_ADD_IO_SEG(0x0001070000000500ull) + (offset) * 8;
 }
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index e638735cc3ac..205ab2ce10f8 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -357,6 +357,34 @@ static inline unsigned int cvmx_get_local_core_num(void)
         return cvmx_get_core_num() & ((1 << CVMX_NODE_NO_SHIFT) - 1);
 }
 
+#define CVMX_NODE_BITS         (2)     /* Number of bits to define a node */
+#define CVMX_MAX_NODES         (1 << CVMX_NODE_BITS)
+#define CVMX_NODE_IO_SHIFT     (36)
+#define CVMX_NODE_MEM_SHIFT    (40)
+#define CVMX_NODE_IO_MASK      ((uint64_t)CVMX_NODE_MASK << CVMX_NODE_IO_SHIFT)
+
+static inline void cvmx_write_csr_node(uint64_t node, uint64_t csr_addr,
+                                       uint64_t val)
+{
+        uint64_t composite_csr_addr, node_addr;
+
+        node_addr = (node & CVMX_NODE_MASK) << CVMX_NODE_IO_SHIFT;
+        composite_csr_addr = (csr_addr & ~CVMX_NODE_IO_MASK) | node_addr;
+
+        cvmx_write64_uint64(composite_csr_addr, val);
+        if (((csr_addr >> 40) & 0x7ffff) == (0x118))
+                cvmx_read64_uint64(CVMX_MIO_BOOT_BIST_STAT | node_addr);
+}
+
+static inline uint64_t cvmx_read_csr_node(uint64_t node, uint64_t csr_addr)
+{
+        uint64_t node_addr;
+
+        node_addr = (csr_addr & ~CVMX_NODE_IO_MASK) |
+                    (node & CVMX_NODE_MASK) << CVMX_NODE_IO_SHIFT;
+        return cvmx_read_csr(node_addr);
+}
+
 /**
  * Returns the number of bits set in the provided value.
  * Simple wrapper for POP instruction.
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index 07c0516ef4d5..c99c4b6a79f4 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -362,4 +362,6 @@ extern void octeon_fixup_irqs(void);
 
 extern struct semaphore octeon_bootbus_sem;
 
+struct irq_domain *octeon_irq_get_block_domain(int node, uint8_t block);
+
 #endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h
index db7c322f057f..53b2cb8e5966 100644
--- a/arch/mips/include/asm/smp-ops.h
+++ b/arch/mips/include/asm/smp-ops.h
@@ -13,7 +13,7 @@
 
 #include <linux/errno.h>
 
-#include <asm/mips-cm.h>
+#include <asm/mips-cps.h>
 
 #ifdef CONFIG_SMP
 
@@ -26,7 +26,7 @@ struct plat_smp_ops {
         void (*send_ipi_mask)(const struct cpumask *mask, unsigned int action);
         void (*init_secondary)(void);
         void (*smp_finish)(void);
-        void (*boot_secondary)(int cpu, struct task_struct *idle);
+        int (*boot_secondary)(int cpu, struct task_struct *idle);
         void (*smp_setup)(void);
         void (*prepare_cpus)(unsigned int max_cpus);
 #ifdef CONFIG_HOTPLUG_CPU
@@ -35,11 +35,11 @@ struct plat_smp_ops {
 #endif
 };
 
-extern void register_smp_ops(struct plat_smp_ops *ops);
+extern void register_smp_ops(const struct plat_smp_ops *ops);
 
 static inline void plat_smp_setup(void)
 {
-        extern struct plat_smp_ops *mp_ops;     /* private */
+        extern const struct plat_smp_ops *mp_ops;       /* private */
 
         mp_ops->smp_setup();
 }
@@ -57,7 +57,7 @@ static inline void plat_smp_setup(void)
         /* UP, nothing to do ...  */
 }
 
-static inline void register_smp_ops(struct plat_smp_ops *ops)
+static inline void register_smp_ops(const struct plat_smp_ops *ops)
 {
 }
 
@@ -66,7 +66,7 @@ static inline void register_smp_ops(struct plat_smp_ops *ops)
 static inline int register_up_smp_ops(void)
 {
 #ifdef CONFIG_SMP_UP
-        extern struct plat_smp_ops up_smp_ops;
+        extern const struct plat_smp_ops up_smp_ops;
 
         register_smp_ops(&up_smp_ops);
 
@@ -79,7 +79,7 @@ static inline int register_up_smp_ops(void)
 static inline int register_cmp_smp_ops(void)
 {
 #ifdef CONFIG_MIPS_CMP
-        extern struct plat_smp_ops cmp_smp_ops;
+        extern const struct plat_smp_ops cmp_smp_ops;
 
         if (!mips_cm_present())
                 return -ENODEV;
@@ -95,7 +95,7 @@ static inline int register_cmp_smp_ops(void)
 static inline int register_vsmp_smp_ops(void)
 {
 #ifdef CONFIG_MIPS_MT_SMP
-        extern struct plat_smp_ops vsmp_smp_ops;
+        extern const struct plat_smp_ops vsmp_smp_ops;
 
         register_smp_ops(&vsmp_smp_ops);
 
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index bab3d41e5987..9e494f8d9c03 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -58,7 +58,7 @@ extern void calculate_cpu_foreign_map(void);
  */
 static inline void smp_send_reschedule(int cpu)
 {
-        extern struct plat_smp_ops *mp_ops;     /* private */
+        extern const struct plat_smp_ops *mp_ops;       /* private */
 
         mp_ops->send_ipi_single(cpu, SMP_RESCHEDULE_YOURSELF);
 }
@@ -66,14 +66,14 @@ static inline void smp_send_reschedule(int cpu)
 #ifdef CONFIG_HOTPLUG_CPU
 static inline int __cpu_disable(void)
 {
-        extern struct plat_smp_ops *mp_ops;     /* private */
+        extern const struct plat_smp_ops *mp_ops;       /* private */
 
         return mp_ops->cpu_disable();
 }
 
 static inline void __cpu_die(unsigned int cpu)
 {
-        extern struct plat_smp_ops *mp_ops;     /* private */
+        extern const struct plat_smp_ops *mp_ops;       /* private */
 
         mp_ops->cpu_die(cpu);
 }
@@ -97,14 +97,14 @@ int mips_smp_ipi_free(const struct cpumask *mask);
 
 static inline void arch_send_call_function_single_ipi(int cpu)
 {
-        extern struct plat_smp_ops *mp_ops;     /* private */
+        extern const struct plat_smp_ops *mp_ops;       /* private */
 
         mp_ops->send_ipi_mask(cpumask_of(cpu), SMP_CALL_FUNCTION);
 }
 
 static inline void arch_send_call_function_ipi_mask(const struct cpumask *mask)
 {
-        extern struct plat_smp_ops *mp_ops;     /* private */
+        extern const struct plat_smp_ops *mp_ops;       /* private */
 
         mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION);
 }
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index eaa5a4d7d5e5..5d3563c55e0c 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -19,20 +19,43 @@
 #include <asm/asm-offsets.h>
 #include <asm/thread_info.h>
 
+/* Make the addition of cfi info a little easier. */
+        .macro cfi_rel_offset reg offset=0 docfi=0
+        .if \docfi
+        .cfi_rel_offset \reg, \offset
+        .endif
+        .endm
+
+        .macro cfi_st reg offset=0 docfi=0
+        LONG_S  \reg, \offset(sp)
+        cfi_rel_offset \reg, \offset, \docfi
+        .endm
+
+        .macro cfi_restore reg offset=0 docfi=0
+        .if \docfi
+        .cfi_restore \reg
+        .endif
+        .endm
+
+        .macro cfi_ld reg offset=0 docfi=0
+        LONG_L  \reg, \offset(sp)
+        cfi_restore \reg \offset \docfi
+        .endm
+
 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 #define STATMASK 0x3f
 #else
 #define STATMASK 0x1f
 #endif
 
-                .macro  SAVE_AT
+                .macro  SAVE_AT docfi=0
                 .set    push
                 .set    noat
-                LONG_S  $1, PT_R1(sp)
+                cfi_st  $1, PT_R1, \docfi
                 .set    pop
                 .endm
 
-                .macro  SAVE_TEMP
+                .macro  SAVE_TEMP docfi=0
 #ifdef CONFIG_CPU_HAS_SMARTMIPS
                 mflhxu  v1
                 LONG_S  v1, PT_LO(sp)
@@ -44,20 +67,20 @@
                 mfhi    v1
 #endif
 #ifdef CONFIG_32BIT
-                LONG_S  $8, PT_R8(sp)
-                LONG_S  $9, PT_R9(sp)
+                cfi_st  $8, PT_R8, \docfi
+                cfi_st  $9, PT_R9, \docfi
 #endif
-                LONG_S  $10, PT_R10(sp)
-                LONG_S  $11, PT_R11(sp)
-                LONG_S  $12, PT_R12(sp)
+                cfi_st  $10, PT_R10, \docfi
+                cfi_st  $11, PT_R11, \docfi
+                cfi_st  $12, PT_R12, \docfi
 #if !defined(CONFIG_CPU_HAS_SMARTMIPS) && !defined(CONFIG_CPU_MIPSR6)
                 LONG_S  v1, PT_HI(sp)
                 mflo    v1
 #endif
-                LONG_S  $13, PT_R13(sp)
-                LONG_S  $14, PT_R14(sp)
-                LONG_S  $15, PT_R15(sp)
-                LONG_S  $24, PT_R24(sp)
+                cfi_st  $13, PT_R13, \docfi
+                cfi_st  $14, PT_R14, \docfi
+                cfi_st  $15, PT_R15, \docfi
+                cfi_st  $24, PT_R24, \docfi
 #if !defined(CONFIG_CPU_HAS_SMARTMIPS) && !defined(CONFIG_CPU_MIPSR6)
                 LONG_S  v1, PT_LO(sp)
 #endif
@@ -71,20 +94,28 @@
 #endif
                 .endm
 
-                .macro  SAVE_STATIC
-                LONG_S  $16, PT_R16(sp)
-                LONG_S  $17, PT_R17(sp)
-                LONG_S  $18, PT_R18(sp)
-                LONG_S  $19, PT_R19(sp)
-                LONG_S  $20, PT_R20(sp)
-                LONG_S  $21, PT_R21(sp)
-                LONG_S  $22, PT_R22(sp)
-                LONG_S  $23, PT_R23(sp)
-                LONG_S  $30, PT_R30(sp)
+                .macro  SAVE_STATIC docfi=0
+                cfi_st  $16, PT_R16, \docfi
+                cfi_st  $17, PT_R17, \docfi
+                cfi_st  $18, PT_R18, \docfi
+                cfi_st  $19, PT_R19, \docfi
+                cfi_st  $20, PT_R20, \docfi
+                cfi_st  $21, PT_R21, \docfi
+                cfi_st  $22, PT_R22, \docfi
+                cfi_st  $23, PT_R23, \docfi
+                cfi_st  $30, PT_R30, \docfi
                 .endm
 
+/*
+ * get_saved_sp returns the SP for the current CPU by looking in the
+ * kernelsp array for it.  If tosp is set, it stores the current sp in
+ * k0 and loads the new value in sp.  If not, it clobbers k0 and
+ * stores the new value in k1, leaving sp unaffected.
+ */
 #ifdef CONFIG_SMP
-                .macro  get_saved_sp    /* SMP variation */
+
+                /* SMP variation */
+                .macro  get_saved_sp docfi=0 tosp=0
                 ASM_CPUID_MFC0  k0, ASM_SMP_CPUID_REG
 #if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
                 lui     k1, %hi(kernelsp)
@@ -97,7 +128,15 @@
 #endif
                 LONG_SRL        k0, SMP_CPUID_PTRSHIFT
                 LONG_ADDU       k1, k0
+                .if \tosp
+                move    k0, sp
+                .if \docfi
+                .cfi_register sp, k0
+                .endif
+                LONG_L  sp, %lo(kernelsp)(k1)
+                .else
                 LONG_L  k1, %lo(kernelsp)(k1)
+                .endif
                 .endm
 
                 .macro  set_saved_sp stackp temp temp2
@@ -106,7 +145,8 @@
                 LONG_S  \stackp, kernelsp(\temp)
                 .endm
 #else /* !CONFIG_SMP */
-                .macro  get_saved_sp    /* Uniprocessor variation */
+                /* Uniprocessor variation */
+                .macro  get_saved_sp docfi=0 tosp=0
 #ifdef CONFIG_CPU_JUMP_WORKAROUNDS
                 /*
                  * Clear BTB (branch target buffer), forbid RAS (return address
@@ -135,7 +175,15 @@
                 daddiu  k1, %hi(kernelsp)
                 dsll    k1, k1, 16
 #endif
+                .if \tosp
+                move    k0, sp
+                .if \docfi
+                .cfi_register sp, k0
+                .endif
+                LONG_L  sp, %lo(kernelsp)(k1)
+                .else
                 LONG_L  k1, %lo(kernelsp)(k1)
+                .endif
                 .endm
 
                 .macro  set_saved_sp stackp temp temp2
@@ -143,7 +191,7 @@
                 .endm
 #endif
 
-                .macro  SAVE_SOME
+                .macro  SAVE_SOME docfi=0
                 .set    push
                 .set    noat
                 .set    reorder
@@ -151,7 +199,6 @@
                 sll     k0, 3           /* extract cu0 bit */
                 .set    noreorder
                 bltz    k0, 8f
-                 move   k1, sp
 #ifdef CONFIG_EVA
                 /*
                  * Flush interAptiv's Return Prediction Stack (RPS) by writing
@@ -178,20 +225,26 @@
                 MTC0    k0, CP0_ENTRYHI
 #endif
                 .set    reorder
+                 move   k0, sp
+                .if \docfi
+                .cfi_register sp, k0
+                .endif
                 /* Called from user mode, new stack. */
-                get_saved_sp
-#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
-8:              move    k0, sp
-                PTR_SUBU sp, k1, PT_SIZE
-#else
-                .set    at=k0
-8:              PTR_SUBU k1, PT_SIZE
+                get_saved_sp docfi=\docfi tosp=1
+8:
+#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
+                .set    at=k1
+#endif
+                PTR_SUBU sp, PT_SIZE
+#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
                 .set    noat
-                move    k0, sp
-                move    sp, k1
 #endif
-                LONG_S  k0, PT_R29(sp)
-                LONG_S  $3, PT_R3(sp)
+                .if \docfi
+                .cfi_def_cfa sp,0
+                .endif
+                cfi_st  k0, PT_R29, \docfi
+                cfi_rel_offset  sp, PT_R29, \docfi
+                cfi_st  v1, PT_R3, \docfi
                 /*
                  * You might think that you don't need to save $0,
                  * but the FPU emulator and gdb remote debug stub
@@ -199,23 +252,26 @@
                  */
                 LONG_S  $0, PT_R0(sp)
                 mfc0    v1, CP0_STATUS
-                LONG_S  $2, PT_R2(sp)
+                cfi_st  v0, PT_R2, \docfi
                 LONG_S  v1, PT_STATUS(sp)
-                LONG_S  $4, PT_R4(sp)
+                cfi_st  $4, PT_R4, \docfi
                 mfc0    v1, CP0_CAUSE
-                LONG_S  $5, PT_R5(sp)
+                cfi_st  $5, PT_R5, \docfi
                 LONG_S  v1, PT_CAUSE(sp)
-                LONG_S  $6, PT_R6(sp)
-                MFC0    v1, CP0_EPC
-                LONG_S  $7, PT_R7(sp)
+                cfi_st  $6, PT_R6, \docfi
+                cfi_st  ra, PT_R31, \docfi
+                MFC0    ra, CP0_EPC
+                cfi_st  $7, PT_R7, \docfi
 #ifdef CONFIG_64BIT
-                LONG_S  $8, PT_R8(sp)
-                LONG_S  $9, PT_R9(sp)
+                cfi_st  $8, PT_R8, \docfi
+                cfi_st  $9, PT_R9, \docfi
 #endif
-                LONG_S  v1, PT_EPC(sp)
-                LONG_S  $25, PT_R25(sp)
-                LONG_S  $28, PT_R28(sp)
-                LONG_S  $31, PT_R31(sp)
+                LONG_S  ra, PT_EPC(sp)
+                .if \docfi
+                .cfi_rel_offset ra, PT_EPC
+                .endif
+                cfi_st  $25, PT_R25, \docfi
+                cfi_st  $28, PT_R28, \docfi
 
                 /* Set thread_info if we're coming from user mode */
                 mfc0    k0, CP0_STATUS
@@ -232,21 +288,21 @@
                 .set    pop
                 .endm
 
-                .macro  SAVE_ALL
-                SAVE_SOME
-                SAVE_AT
-                SAVE_TEMP
-                SAVE_STATIC
+                .macro  SAVE_ALL docfi=0
+                SAVE_SOME \docfi
+                SAVE_AT \docfi
+                SAVE_TEMP \docfi
+                SAVE_STATIC \docfi
                 .endm
 
-                .macro  RESTORE_AT
+                .macro  RESTORE_AT docfi=0
                 .set    push
                 .set    noat
-                LONG_L  $1,  PT_R1(sp)
+                cfi_ld  $1, PT_R1, \docfi
                 .set    pop
                 .endm
 
-                .macro  RESTORE_TEMP
+                .macro  RESTORE_TEMP docfi=0
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
                 /* Restore the Octeon multiplier state */
                 jal     octeon_mult_restore
@@ -265,33 +321,37 @@
                 mthi    $24
 #endif
 #ifdef CONFIG_32BIT
-                LONG_L  $8, PT_R8(sp)
-                LONG_L  $9, PT_R9(sp)
+                cfi_ld  $8, PT_R8, \docfi
+                cfi_ld  $9, PT_R9, \docfi
 #endif
-                LONG_L  $10, PT_R10(sp)
-                LONG_L  $11, PT_R11(sp)
-                LONG_L  $12, PT_R12(sp)
-                LONG_L  $13, PT_R13(sp)
-                LONG_L  $14, PT_R14(sp)
-                LONG_L  $15, PT_R15(sp)
-                LONG_L  $24, PT_R24(sp)
+                cfi_ld  $10, PT_R10, \docfi
+                cfi_ld  $11, PT_R11, \docfi
+                cfi_ld  $12, PT_R12, \docfi
+                cfi_ld  $13, PT_R13, \docfi
+                cfi_ld  $14, PT_R14, \docfi
+                cfi_ld  $15, PT_R15, \docfi
+                cfi_ld  $24, PT_R24, \docfi
                 .endm
 
-                .macro  RESTORE_STATIC
-                LONG_L  $16, PT_R16(sp)
-                LONG_L  $17, PT_R17(sp)
-                LONG_L  $18, PT_R18(sp)
-                LONG_L  $19, PT_R19(sp)
-                LONG_L  $20, PT_R20(sp)
-                LONG_L  $21, PT_R21(sp)
-                LONG_L  $22, PT_R22(sp)
-                LONG_L  $23, PT_R23(sp)
-                LONG_L  $30, PT_R30(sp)
+                .macro  RESTORE_STATIC docfi=0
+                cfi_ld  $16, PT_R16, \docfi
+                cfi_ld  $17, PT_R17, \docfi
+                cfi_ld  $18, PT_R18, \docfi
+                cfi_ld  $19, PT_R19, \docfi
+                cfi_ld  $20, PT_R20, \docfi
+                cfi_ld  $21, PT_R21, \docfi
+                cfi_ld  $22, PT_R22, \docfi
+                cfi_ld  $23, PT_R23, \docfi
+                cfi_ld  $30, PT_R30, \docfi
+                .endm
+
+                .macro  RESTORE_SP docfi=0
+                cfi_ld  sp, PT_R29, \docfi
                 .endm
 
 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 
-                .macro  RESTORE_SOME
+                .macro  RESTORE_SOME docfi=0
                 .set    push
                 .set    reorder
                 .set    noat
@@ -306,30 +366,30 @@
                 and     v0, v1
                 or      v0, a0
                 mtc0    v0, CP0_STATUS
-                LONG_L  $31, PT_R31(sp)
-                LONG_L  $28, PT_R28(sp)
-                LONG_L  $25, PT_R25(sp)
-                LONG_L  $7,  PT_R7(sp)
-                LONG_L  $6,  PT_R6(sp)
-                LONG_L  $5,  PT_R5(sp)
-                LONG_L  $4,  PT_R4(sp)
-                LONG_L  $3,  PT_R3(sp)
-                LONG_L  $2,  PT_R2(sp)
+                cfi_ld  $31, PT_R31, \docfi
+                cfi_ld  $28, PT_R28, \docfi
+                cfi_ld  $25, PT_R25, \docfi
+                cfi_ld  $7,  PT_R7, \docfi
+                cfi_ld  $6,  PT_R6, \docfi
+                cfi_ld  $5,  PT_R5, \docfi
+                cfi_ld  $4,  PT_R4, \docfi
+                cfi_ld  $3,  PT_R3, \docfi
+                cfi_ld  $2,  PT_R2, \docfi
                 .set    pop
                 .endm
 
-                .macro  RESTORE_SP_AND_RET
+                .macro  RESTORE_SP_AND_RET docfi=0
                 .set    push
                 .set    noreorder
                 LONG_L  k0, PT_EPC(sp)
-                LONG_L  sp, PT_R29(sp)
+                RESTORE_SP \docfi
                 jr      k0
                  rfe
                 .set    pop
                 .endm
 
 #else
-                .macro  RESTORE_SOME
+                .macro  RESTORE_SOME docfi=0
                 .set    push
                 .set    reorder
                 .set    noat
@@ -346,24 +406,24 @@
                 mtc0    v0, CP0_STATUS
                 LONG_L  v1, PT_EPC(sp)
                 MTC0    v1, CP0_EPC
-                LONG_L  $31, PT_R31(sp)
-                LONG_L  $28, PT_R28(sp)
-                LONG_L  $25, PT_R25(sp)
+                cfi_ld  $31, PT_R31, \docfi
+                cfi_ld  $28, PT_R28, \docfi
+                cfi_ld  $25, PT_R25, \docfi
 #ifdef CONFIG_64BIT
-                LONG_L  $8, PT_R8(sp)
-                LONG_L  $9, PT_R9(sp)
+                cfi_ld  $8, PT_R8, \docfi
+                cfi_ld  $9, PT_R9, \docfi
 #endif
-                LONG_L  $7,  PT_R7(sp)
-                LONG_L  $6,  PT_R6(sp)
-                LONG_L  $5,  PT_R5(sp)
-                LONG_L  $4,  PT_R4(sp)
-                LONG_L  $3,  PT_R3(sp)
-                LONG_L  $2,  PT_R2(sp)
+                cfi_ld  $7,  PT_R7, \docfi
+                cfi_ld  $6,  PT_R6, \docfi
+                cfi_ld  $5,  PT_R5, \docfi
+                cfi_ld  $4,  PT_R4, \docfi
+                cfi_ld  $3,  PT_R3, \docfi
+                cfi_ld  $2,  PT_R2, \docfi
                 .set    pop
                 .endm
 
-                .macro  RESTORE_SP_AND_RET
-                LONG_L  sp, PT_R29(sp)
+                .macro  RESTORE_SP_AND_RET docfi=0
+                RESTORE_SP \docfi
 #ifdef CONFIG_CPU_MIPSR6
                 eretnc
 #else
@@ -375,16 +435,12 @@
 
 #endif
 
-                .macro  RESTORE_SP
-                LONG_L  sp, PT_R29(sp)
-                .endm
-
-                .macro  RESTORE_ALL
-                RESTORE_TEMP
-                RESTORE_STATIC
-                RESTORE_AT
-                RESTORE_SOME
-                RESTORE_SP
+                .macro  RESTORE_ALL docfi=0
+                RESTORE_TEMP \docfi
+                RESTORE_STATIC \docfi
+                RESTORE_AT \docfi
+                RESTORE_SOME \docfi
+                RESTORE_SP \docfi
                 .endm
 
 /*
diff --git a/arch/mips/include/asm/stacktrace.h b/arch/mips/include/asm/stacktrace.h
index 780ee2c2a2ac..10c4e9c84448 100644
--- a/arch/mips/include/asm/stacktrace.h
+++ b/arch/mips/include/asm/stacktrace.h
@@ -2,6 +2,8 @@
 #define _ASM_STACKTRACE_H
 
 #include <asm/ptrace.h>
+#include <asm/asm.h>
+#include <linux/stringify.h>
 
 #ifdef CONFIG_KALLSYMS
 extern int raw_show_trace;
@@ -20,6 +22,14 @@ static inline unsigned long unwind_stack(struct task_struct *task,
 }
 #endif
 
+#define STR_PTR_LA    __stringify(PTR_LA)
+#define STR_LONG_S    __stringify(LONG_S)
+#define STR_LONG_L    __stringify(LONG_L)
+#define STR_LONGSIZE  __stringify(LONGSIZE)
+
+#define STORE_ONE_REG(r) \
+    STR_LONG_S   " $" __stringify(r)",("STR_LONGSIZE"*"__stringify(r)")(%1)\n\t"
+
 static __always_inline void prepare_frametrace(struct pt_regs *regs)
 {
 #ifndef CONFIG_KALLSYMS
@@ -32,21 +42,47 @@ static __always_inline void prepare_frametrace(struct pt_regs *regs)
         __asm__ __volatile__(
                 ".set push\n\t"
                 ".set noat\n\t"
-#ifdef CONFIG_64BIT
-                "1: dla $1, 1b\n\t"
-                "sd $1, %0\n\t"
-                "sd $29, %1\n\t"
-                "sd $31, %2\n\t"
-#else
-                "1: la $1, 1b\n\t"
-                "sw $1, %0\n\t"
-                "sw $29, %1\n\t"
-                "sw $31, %2\n\t"
-#endif
+                /* Store $1 so we can use it */
+                STR_LONG_S " $1,"STR_LONGSIZE"(%1)\n\t"
+                /* Store the PC */
+                "1: " STR_PTR_LA " $1, 1b\n\t"
+                STR_LONG_S " $1,%0\n\t"
+                STORE_ONE_REG(2)
+                STORE_ONE_REG(3)
+                STORE_ONE_REG(4)
+                STORE_ONE_REG(5)
+                STORE_ONE_REG(6)
+                STORE_ONE_REG(7)
+                STORE_ONE_REG(8)
+                STORE_ONE_REG(9)
+                STORE_ONE_REG(10)
+                STORE_ONE_REG(11)
+                STORE_ONE_REG(12)
+                STORE_ONE_REG(13)
+                STORE_ONE_REG(14)
+                STORE_ONE_REG(15)
+                STORE_ONE_REG(16)
+                STORE_ONE_REG(17)
+                STORE_ONE_REG(18)
+                STORE_ONE_REG(19)
+                STORE_ONE_REG(20)
+                STORE_ONE_REG(21)
+                STORE_ONE_REG(22)
+                STORE_ONE_REG(23)
+                STORE_ONE_REG(24)
+                STORE_ONE_REG(25)
+                STORE_ONE_REG(26)
+                STORE_ONE_REG(27)
+                STORE_ONE_REG(28)
+                STORE_ONE_REG(29)
+                STORE_ONE_REG(30)
+                STORE_ONE_REG(31)
+                /* Restore $1 */
+                STR_LONG_L " $1,"STR_LONGSIZE"(%1)\n\t"
                 ".set pop\n\t"
-                : "=m" (regs->cp0_epc),
-                "=m" (regs->regs[29]), "=m" (regs->regs[31])
-                : : "memory");
+                : "=m" (regs->cp0_epc)
+                : "r" (regs->regs)
+                : "memory");
 }
 
 #endif /* _ASM_STACKTRACE_H */
diff --git a/arch/mips/include/asm/topology.h b/arch/mips/include/asm/topology.h
index 7afda4150a59..0673d2d0f2e6 100644
--- a/arch/mips/include/asm/topology.h
+++ b/arch/mips/include/asm/topology.h
@@ -13,7 +13,7 @@
 
 #ifdef CONFIG_SMP
 #define topology_physical_package_id(cpu)       (cpu_data[cpu].package)
-#define topology_core_id(cpu)                   (cpu_data[cpu].core)
+#define topology_core_id(cpu)                   (cpu_core(&cpu_data[cpu]))
 #define topology_core_cpumask(cpu)              (&cpu_core_map[cpu])
 #define topology_sibling_cpumask(cpu)           (&cpu_sibling_map[cpu])
 #endif
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index d61897535926..6abea5183d7c 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -981,7 +981,7 @@ struct mm16_r3_format {		/* Load from global pointer format */
 struct mm16_r5_format {         /* Load/store from stack pointer format */
         __BITFIELD_FIELD(unsigned int opcode : 6,
         __BITFIELD_FIELD(unsigned int rt : 5,
-        __BITFIELD_FIELD(signed int simmediate : 5,
+        __BITFIELD_FIELD(unsigned int imm : 5,
         __BITFIELD_FIELD(unsigned int : 16, /* Ignored */
         ;))))
 };
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 46c0581256f1..07f0f4a4b562 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -35,11 +35,15 @@ obj-$(CONFIG_MODULES)		+= module.o
 obj-$(CONFIG_FTRACE_SYSCALLS)   += ftrace.o
 obj-$(CONFIG_FUNCTION_TRACER)   += mcount.o ftrace.o
 
-obj-$(CONFIG_CPU_R4K_FPU)       += r4k_fpu.o r4k_switch.o
-obj-$(CONFIG_CPU_R3000)         += r2300_fpu.o r2300_switch.o
-obj-$(CONFIG_CPU_R6000)         += r6000_fpu.o r4k_switch.o
-obj-$(CONFIG_CPU_TX39XX)        += r2300_fpu.o r2300_switch.o
-obj-$(CONFIG_CPU_CAVIUM_OCTEON) += r4k_fpu.o octeon_switch.o
+sw-y                            := r4k_switch.o
+sw-$(CONFIG_CPU_R3000)          := r2300_switch.o
+sw-$(CONFIG_CPU_TX39XX)         := r2300_switch.o
+sw-$(CONFIG_CPU_CAVIUM_OCTEON)  := octeon_switch.o
+obj-y                           += $(sw-y)
+
+obj-$(CONFIG_CPU_R4K_FPU)       += r4k_fpu.o
+obj-$(CONFIG_CPU_R3000)         += r2300_fpu.o
+obj-$(CONFIG_CPU_TX39XX)        += r2300_fpu.o
 
 obj-$(CONFIG_SMP)               += smp.o
 obj-$(CONFIG_SMP_UP)            += smp-up.o
diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S
index b849fe6aad94..d173b49f212d 100644
--- a/arch/mips/kernel/cps-vec.S
+++ b/arch/mips/kernel/cps-vec.S
@@ -327,8 +327,8 @@ LEAF(mips_cps_get_bootcfg)
          * to handle contiguous VP numbering, but no such systems yet
          * exist.
          */
-        mfc0    t9, $3, 1
-        andi    t9, t9, 0xff
+        mfc0    t9, CP0_GLOBALNUMBER
+        andi    t9, t9, MIPS_GLOBALNUMBER_VP
 #elif defined(CONFIG_MIPS_MT_SMP)
         has_mt  ta2, 1f
 
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index d08afc7dc507..cf3fd549e16d 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -326,7 +326,7 @@ static int __init fpu_disable(char *s)
 
 __setup("nofpu", fpu_disable);
 
-int mips_dsp_disabled;
+static int mips_dsp_disabled;
 
 static int __init dsp_disable(char *s)
 {
@@ -919,9 +919,12 @@ static void decode_configs(struct cpuinfo_mips *c)
 
 #ifndef CONFIG_MIPS_CPS
         if (cpu_has_mips_r2_r6) {
-                c->core = get_ebase_cpunum();
+                unsigned int core;
+
+                core = get_ebase_cpunum();
                 if (cpu_has_mipsmt)
-                        c->core >>= fls(core_nvpes()) - 1;
+                        core >>= fls(core_nvpes()) - 1;
+                cpu_set_core(c, core);
         }
 #endif
 }
@@ -1394,24 +1397,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
                 c->tlbsize = 48;
                 break;
-        case PRID_IMP_R6000:
-                c->cputype = CPU_R6000;
-                __cpu_name[cpu] = "R6000";
-                set_isa(c, MIPS_CPU_ISA_II);
-                c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
-                c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
-                             MIPS_CPU_LLSC;
-                c->tlbsize = 32;
-                break;
-        case PRID_IMP_R6000A:
-                c->cputype = CPU_R6000A;
-                __cpu_name[cpu] = "R6000A";
-                set_isa(c, MIPS_CPU_ISA_II);
-                c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
-                c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
-                             MIPS_CPU_LLSC;
-                c->tlbsize = 32;
-                break;
         case PRID_IMP_RM7000:
                 c->cputype = CPU_RM7000;
                 __cpu_name[cpu] = "RM7000";
@@ -2113,3 +2098,35 @@ void cpu_report(void)
         if (cpu_has_msa)
                 pr_info("MSA revision is: %08x\n", c->msa_id);
 }
+
+void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
+{
+        /* Ensure the core number fits in the field */
+        WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
+                           MIPS_GLOBALNUMBER_CLUSTER_SHF));
+
+        cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
+        cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
+}
+
+void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
+{
+        /* Ensure the core number fits in the field */
+        WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
+
+        cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
+        cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
+}
+
+void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
+{
+        /* Ensure the VP(E) ID fits in the field */
+        WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
+
+        /* Ensure we're not using VP(E)s without support */
+        WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
+                !IS_ENABLED(CONFIG_CPU_MIPSR6));
+
+        cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
+        cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;
+}
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index ae810da4d499..37b9383eacd3 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -150,6 +150,7 @@ LEAF(__r4k_wait)
         .align  5
 BUILD_ROLLBACK_PROLOGUE handle_int
 NESTED(handle_int, PT_SIZE, sp)
+        .cfi_signal_frame
 #ifdef CONFIG_TRACE_IRQFLAGS
         /*
          * Check to see if the interrupted code has just disabled
@@ -181,7 +182,7 @@ NESTED(handle_int, PT_SIZE, sp)
 1:
         .set pop
 #endif
-        SAVE_ALL
+        SAVE_ALL docfi=1
         CLI
         TRACE_IRQS_OFF
 
@@ -269,8 +270,8 @@ NESTED(except_vec_ejtag_debug, 0, sp)
  */
 BUILD_ROLLBACK_PROLOGUE except_vec_vi
 NESTED(except_vec_vi, 0, sp)
-        SAVE_SOME
-        SAVE_AT
+        SAVE_SOME docfi=1
+        SAVE_AT docfi=1
         .set    push
         .set    noreorder
         PTR_LA  v1, except_vec_vi_handler
@@ -396,6 +397,7 @@ NESTED(except_vec_nmi, 0, sp)
         __FINIT
 
 NESTED(nmi_handler, PT_SIZE, sp)
+        .cfi_signal_frame
         .set    push
         .set    noat
         /*
@@ -478,6 +480,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
         .macro  __BUILD_HANDLER exception handler clear verbose ext
         .align  5
         NESTED(handle_\exception, PT_SIZE, sp)
+        .cfi_signal_frame
         .set    noat
         SAVE_ALL
         FEXPORT(handle_\exception\ext)
@@ -485,8 +488,8 @@ NESTED(nmi_handler, PT_SIZE, sp)
         .set    at
         __BUILD_\verbose \exception
         move    a0, sp
-        PTR_LA  ra, ret_from_exception
-        j       do_\handler
+        jal     do_\handler
+        j       ret_from_exception
         END(handle_\exception)
         .endm
 
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 60ab4c44d305..7c246b69c545 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -11,6 +11,7 @@
  * as published by the Free Software Foundation; either version
  * 2 of the License, or (at your option) any later version.
  */
+#include <linux/cpu.h>
 #include <linux/export.h>
 #include <linux/init.h>
 #include <linux/irqflags.h>
diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c
index cb0c57f860d4..e91c8c4e2eb5 100644
--- a/arch/mips/kernel/mips-cm.c
+++ b/arch/mips/kernel/mips-cm.c
@@ -12,10 +12,10 @@
 #include <linux/percpu.h>
 #include <linux/spinlock.h>
 
-#include <asm/mips-cm.h>
+#include <asm/mips-cps.h>
 #include <asm/mipsregs.h>
 
-void __iomem *mips_cm_base;
+void __iomem *mips_gcr_base;
 void __iomem *mips_cm_l2sync_base;
 int mips_cm_is64;
 
@@ -167,8 +167,8 @@ phys_addr_t __mips_cm_l2sync_phys_base(void)
          * current location.
          */
         base_reg = read_gcr_l2_only_sync_base();
-        if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK)
-                return base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK;
+        if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN)
+                return base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE;
 
         /* Default to following the CM */
         return mips_cm_phys_base() + MIPS_CM_GCR_SIZE;
@@ -183,19 +183,19 @@ static void mips_cm_probe_l2sync(void)
         phys_addr_t addr;
 
         /* L2-only sync was introduced with CM major revision 6 */
-        major_rev = (read_gcr_rev() & CM_GCR_REV_MAJOR_MSK) >>
-                CM_GCR_REV_MAJOR_SHF;
+        major_rev = (read_gcr_rev() & CM_GCR_REV_MAJOR) >>
+                __ffs(CM_GCR_REV_MAJOR);
         if (major_rev < 6)
                 return;
 
         /* Find a location for the L2 sync region */
         addr = mips_cm_l2sync_phys_base();
-        BUG_ON((addr & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE_MSK) != addr);
+        BUG_ON((addr & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE) != addr);
         if (!addr)
                 return;
 
         /* Set the region base address & enable it */
-        write_gcr_l2_only_sync_base(addr | CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN_MSK);
+        write_gcr_l2_only_sync_base(addr | CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN);
 
         /* Map the region */
         mips_cm_l2sync_base = ioremap_nocache(addr, MIPS_CM_L2SYNC_SIZE);
@@ -211,41 +211,39 @@ int mips_cm_probe(void)
          * No need to probe again if we have already been
          * here before.
          */
-        if (mips_cm_base)
+        if (mips_gcr_base)
                 return 0;
 
         addr = mips_cm_phys_base();
-        BUG_ON((addr & CM_GCR_BASE_GCRBASE_MSK) != addr);
+        BUG_ON((addr & CM_GCR_BASE_GCRBASE) != addr);
         if (!addr)
                 return -ENODEV;
 
-        mips_cm_base = ioremap_nocache(addr, MIPS_CM_GCR_SIZE);
-        if (!mips_cm_base)
+        mips_gcr_base = ioremap_nocache(addr, MIPS_CM_GCR_SIZE);
+        if (!mips_gcr_base)
                 return -ENXIO;
 
         /* sanity check that we're looking at a CM */
         base_reg = read_gcr_base();
-        if ((base_reg & CM_GCR_BASE_GCRBASE_MSK) != addr) {
+        if ((base_reg & CM_GCR_BASE_GCRBASE) != addr) {
                 pr_err("GCRs appear to have been moved (expected them at 0x%08lx)!\n",
                        (unsigned long)addr);
-                mips_cm_base = NULL;
+                mips_gcr_base = NULL;
                 return -ENODEV;
         }
 
         /* set default target to memory */
-        base_reg &= ~CM_GCR_BASE_CMDEFTGT_MSK;
-        base_reg |= CM_GCR_BASE_CMDEFTGT_MEM;
-        write_gcr_base(base_reg);
+        change_gcr_base(CM_GCR_BASE_CMDEFTGT, CM_GCR_BASE_CMDEFTGT_MEM);
 
         /* disable CM regions */
-        write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
-        write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
-        write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
-        write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
-        write_gcr_reg2_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
-        write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
-        write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
-        write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
+        write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR);
+        write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK);
+        write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR);
+        write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK);
+        write_gcr_reg2_base(CM_GCR_REGn_BASE_BASEADDR);
+        write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK);
+        write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR);
+        write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK);
 
         /* probe for an L2-only sync region */
         mips_cm_probe_l2sync();
@@ -259,16 +257,27 @@ int mips_cm_probe(void)
         return 0;
 }
 
-void mips_cm_lock_other(unsigned int core, unsigned int vp)
+void mips_cm_lock_other(unsigned int cluster, unsigned int core,
+                        unsigned int vp, unsigned int block)
 {
-        unsigned curr_core;
+        unsigned int curr_core, cm_rev;
         u32 val;
 
+        cm_rev = mips_cm_revision();
         preempt_disable();
 
-        if (mips_cm_revision() >= CM_REV_CM3) {
-                val = core << CM3_GCR_Cx_OTHER_CORE_SHF;
-                val |= vp << CM3_GCR_Cx_OTHER_VP_SHF;
+        if (cm_rev >= CM_REV_CM3) {
+                val = core << __ffs(CM3_GCR_Cx_OTHER_CORE);
+                val |= vp << __ffs(CM3_GCR_Cx_OTHER_VP);
+
+                if (cm_rev >= CM_REV_CM3_5) {
+                        val |= CM_GCR_Cx_OTHER_CLUSTER_EN;
+                        val |= cluster << __ffs(CM_GCR_Cx_OTHER_CLUSTER);
+                        val |= block << __ffs(CM_GCR_Cx_OTHER_BLOCK);
+                } else {
+                        WARN_ON(cluster != 0);
+                        WARN_ON(block != CM_GCR_Cx_OTHER_BLOCK_LOCAL);
+                }
 
                 /*
                  * We need to disable interrupts in SMP systems in order to
@@ -282,18 +291,20 @@ void mips_cm_lock_other(unsigned int core, unsigned int vp)
                 spin_lock_irqsave(this_cpu_ptr(&cm_core_lock),
                                   *this_cpu_ptr(&cm_core_lock_flags));
         } else {
+                WARN_ON(cluster != 0);
                 WARN_ON(vp != 0);
+                WARN_ON(block != CM_GCR_Cx_OTHER_BLOCK_LOCAL);
 
                 /*
                  * We only have a GCR_CL_OTHER per core in systems with
                  * CM 2.5 & older, so have to ensure other VP(E)s don't
                  * race with us.
                  */
-                curr_core = current_cpu_data.core;
+                curr_core = cpu_core(&current_cpu_data);
                 spin_lock_irqsave(&per_cpu(cm_core_lock, curr_core),
                                   per_cpu(cm_core_lock_flags, curr_core));
 
-                val = core << CM_GCR_Cx_OTHER_CORENUM_SHF;
+                val = core << __ffs(CM_GCR_Cx_OTHER_CORENUM);
         }
 
         write_gcr_cl_other(val);
@@ -310,7 +321,7 @@ void mips_cm_unlock_other(void)
         unsigned int curr_core;
 
         if (mips_cm_revision() < CM_REV_CM3) {
-                curr_core = current_cpu_data.core;
+                curr_core = cpu_core(&current_cpu_data);
                 spin_unlock_irqrestore(&per_cpu(cm_core_lock, curr_core),
                                        per_cpu(cm_core_lock_flags, curr_core));
         } else {
@@ -332,13 +343,13 @@ void mips_cm_error_report(void)
                 return;
 
         revision = mips_cm_revision();
+        cm_error = read_gcr_error_cause();
+        cm_addr = read_gcr_error_addr();
+        cm_other = read_gcr_error_mult();
 
         if (revision < CM_REV_CM3) { /* CM2 */
-                cm_error = read_gcr_error_cause();
-                cm_addr = read_gcr_error_addr();
-                cm_other = read_gcr_error_mult();
-                cause = cm_error >> CM_GCR_ERROR_CAUSE_ERRTYPE_SHF;
-                ocause = cm_other >> CM_GCR_ERROR_MULT_ERR2ND_SHF;
+                cause = cm_error >> __ffs(CM_GCR_ERROR_CAUSE_ERRTYPE);
+                ocause = cm_other >> __ffs(CM_GCR_ERROR_MULT_ERR2ND);
 
                 if (!cause)
                         return;
@@ -380,11 +391,8 @@ void mips_cm_error_report(void)
                 ulong core_id_bits, vp_id_bits, cmd_bits, cmd_group_bits;
                 ulong cm3_cca_bits, mcp_bits, cm3_tr_bits, sched_bit;
 
-                cm_error = read64_gcr_error_cause();
-                cm_addr = read64_gcr_error_addr();
-                cm_other = read64_gcr_error_mult();
-                cause = cm_error >> CM3_GCR_ERROR_CAUSE_ERRTYPE_SHF;
-                ocause = cm_other >> CM_GCR_ERROR_MULT_ERR2ND_SHF;
+                cause = cm_error >> __ffs64(CM3_GCR_ERROR_CAUSE_ERRTYPE);
+                ocause = cm_other >> __ffs(CM_GCR_ERROR_MULT_ERR2ND);
 
                 if (!cause)
                         return;
diff --git a/arch/mips/kernel/mips-cpc.c b/arch/mips/kernel/mips-cpc.c
index a4964c334cab..f66b05ebf637 100644
--- a/arch/mips/kernel/mips-cpc.c
+++ b/arch/mips/kernel/mips-cpc.c
@@ -12,8 +12,7 @@
 #include <linux/percpu.h>
 #include <linux/spinlock.h>
 
-#include <asm/mips-cm.h>
-#include <asm/mips-cpc.h>
+#include <asm/mips-cps.h>
 
 void __iomem *mips_cpc_base;
 
@@ -40,13 +39,13 @@ static phys_addr_t mips_cpc_phys_base(void)
         if (!mips_cm_present())
                 return 0;
 
-        if (!(read_gcr_cpc_status() & CM_GCR_CPC_STATUS_EX_MSK))
+        if (!(read_gcr_cpc_status() & CM_GCR_CPC_STATUS_EX))
                 return 0;
 
         /* If the CPC is already enabled, leave it so */
         cpc_base = read_gcr_cpc_base();
-        if (cpc_base & CM_GCR_CPC_BASE_CPCEN_MSK)
-                return cpc_base & CM_GCR_CPC_BASE_CPCBASE_MSK;
+        if (cpc_base & CM_GCR_CPC_BASE_CPCEN)
+                return cpc_base & CM_GCR_CPC_BASE_CPCBASE;
 
         /* Otherwise, use the default address */
         cpc_base = mips_cpc_default_phys_base();
@@ -54,7 +53,7 @@ static phys_addr_t mips_cpc_phys_base(void)
                 return cpc_base;
 
         /* Enable the CPC, mapped at the default address */
-        write_gcr_cpc_base(cpc_base | CM_GCR_CPC_BASE_CPCEN_MSK);
+        write_gcr_cpc_base(cpc_base | CM_GCR_CPC_BASE_CPCEN);
         return cpc_base;
 }
 
@@ -86,10 +85,10 @@ void mips_cpc_lock_other(unsigned int core)
                 return;
 
         preempt_disable();
-        curr_core = current_cpu_data.core;
+        curr_core = cpu_core(&current_cpu_data);
         spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core),
                           per_cpu(cpc_core_lock_flags, curr_core));
-        write_cpc_cl_other(core << CPC_Cx_OTHER_CORENUM_SHF);
+        write_cpc_cl_other(core << __ffs(CPC_Cx_OTHER_CORENUM));
 
         /*
          * Ensure the core-other region reflects the appropriate core &
@@ -106,7 +105,7 @@ void mips_cpc_unlock_other(void)
                 /* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */
                 return;
 
-        curr_core = current_cpu_data.core;
+        curr_core = cpu_core(&current_cpu_data);
         spin_unlock_irqrestore(&per_cpu(cpc_core_lock, curr_core),
                                per_cpu(cpc_core_lock_flags, curr_core));
         preempt_enable();
diff --git a/arch/mips/kernel/mips-r2-to-r6-emul.c b/arch/mips/kernel/mips-r2-to-r6-emul.c
index ae64c8f56a8c..eb18b186e858 100644
--- a/arch/mips/kernel/mips-r2-to-r6-emul.c
+++ b/arch/mips/kernel/mips-r2-to-r6-emul.c
@@ -46,9 +46,11 @@
 #define LL      "ll "
 #define SC      "sc "
 
-DEFINE_PER_CPU(struct mips_r2_emulator_stats, mipsr2emustats);
-DEFINE_PER_CPU(struct mips_r2_emulator_stats, mipsr2bdemustats);
-DEFINE_PER_CPU(struct mips_r2br_emulator_stats, mipsr2bremustats);
+#ifdef CONFIG_DEBUG_FS
+static DEFINE_PER_CPU(struct mips_r2_emulator_stats, mipsr2emustats);
+static DEFINE_PER_CPU(struct mips_r2_emulator_stats, mipsr2bdemustats);
+static DEFINE_PER_CPU(struct mips_r2br_emulator_stats, mipsr2bremustats);
+#endif
 
 extern const unsigned int fpucondbit[8];
 
@@ -600,7 +602,7 @@ static int ddivu_func(struct pt_regs *regs, u32 ir)
 }
 
 /* R6 removed instructions for the SPECIAL opcode */
-static struct r2_decoder_table spec_op_table[] = {
+static const struct r2_decoder_table spec_op_table[] = {
         { 0xfc1ff83f, 0x00000008, jr_func },
         { 0xfc00ffff, 0x00000018, mult_func },
         { 0xfc00ffff, 0x00000019, multu_func },
@@ -867,7 +869,7 @@ static int dclo_func(struct pt_regs *regs, u32 ir)
 }
 
 /* R6 removed instructions for the SPECIAL2 opcode */
-static struct r2_decoder_table spec2_op_table[] = {
+static const struct r2_decoder_table spec2_op_table[] = {
         { 0xfc00ffff, 0x70000000, madd_func },
         { 0xfc00ffff, 0x70000001, maddu_func },
         { 0xfc0007ff, 0x70000002, mul_func },
@@ -881,9 +883,9 @@ static struct r2_decoder_table spec2_op_table[] = {
 };
 
 static inline int mipsr2_find_op_func(struct pt_regs *regs, u32 inst,
-                                      struct r2_decoder_table *table)
+                                      const struct r2_decoder_table *table)
 {
-        struct r2_decoder_table *p;
+        const struct r2_decoder_table *p;
         int err;
 
         for (p = table; p->func; p++) {
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
index 3375745b9198..e42113fe2762 100644
--- a/arch/mips/kernel/octeon_switch.S
+++ b/arch/mips/kernel/octeon_switch.S
@@ -10,12 +10,13 @@
  * Copyright (C) 2000 MIPS Technologies, Inc.
  *    written by Carsten Langgaard, carstenl@mips.com
  */
+#include <asm/asm.h>
+#include <asm/export.h>
+#include <asm/asm-offsets.h>
+#include <asm/mipsregs.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
 
-#define USE_ALTERNATE_RESUME_IMPL 1
-        .set push
-        .set arch=mips64r2
-#include "r4k_switch.S"
-        .set pop
 /*
  * task_struct *resume(task_struct *prev, task_struct *next,
  *                     struct thread_info *next_ti)
diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c
index d99416094ba9..4655017f2377 100644
--- a/arch/mips/kernel/pm-cps.c
+++ b/arch/mips/kernel/pm-cps.c
@@ -17,8 +17,7 @@
 #include <asm/cacheflush.h>
 #include <asm/cacheops.h>
 #include <asm/idle.h>
-#include <asm/mips-cm.h>
-#include <asm/mips-cpc.h>
+#include <asm/mips-cps.h>
 #include <asm/mipsmtregs.h>
 #include <asm/pm.h>
 #include <asm/pm-cps.h>
@@ -49,7 +48,7 @@ static DEFINE_PER_CPU_READ_MOSTLY(cps_nc_entry_fn[CPS_PM_STATE_COUNT],
                                   nc_asm_enter);
 
 /* Bitmap indicating which states are supported by the system */
-DECLARE_BITMAP(state_support, CPS_PM_STATE_COUNT);
+static DECLARE_BITMAP(state_support, CPS_PM_STATE_COUNT);
 
 /*
  * Indicates the number of coupled VPEs ready to operate in a non-coherent
@@ -114,7 +113,7 @@ static void coupled_barrier(atomic_t *a, unsigned online)
 int cps_pm_enter_state(enum cps_pm_state state)
 {
         unsigned cpu = smp_processor_id();
-        unsigned core = current_cpu_data.core;
+        unsigned core = cpu_core(&current_cpu_data);
         unsigned online, left;
         cpumask_t *coupled_mask = this_cpu_ptr(&online_coupled);
         u32 *core_ready_count, *nc_core_ready_count;
@@ -486,7 +485,7 @@ static void *cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
                 * defined by the interAptiv & proAptiv SUMs as ensuring that the
                 *  operation resulting from the preceding store is complete.
                 */
-                uasm_i_addiu(&p, t0, zero, 1 << cpu_data[cpu].core);
+                uasm_i_addiu(&p, t0, zero, 1 << cpu_core(&cpu_data[cpu]));
                 uasm_i_sw(&p, t0, 0, r_pcohctl);
                 uasm_i_lw(&p, t0, 0, r_pcohctl);
 
@@ -569,8 +568,8 @@ static void *cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
          * rest will just be performing a rather unusual nop.
          */
         uasm_i_addiu(&p, t0, zero, mips_cm_revision() < CM_REV_CM3
-                                ? CM_GCR_Cx_COHERENCE_COHDOMAINEN_MSK
-                                : CM3_GCR_Cx_COHERENCE_COHEN_MSK);
+                                ? CM_GCR_Cx_COHERENCE_COHDOMAINEN
+                                : CM3_GCR_Cx_COHERENCE_COHEN);
 
         uasm_i_sw(&p, t0, 0, r_pcohctl);
         uasm_i_lw(&p, t0, 0, r_pcohctl);
@@ -640,7 +639,7 @@ out_err:
 static int cps_pm_online_cpu(unsigned int cpu)
 {
         enum cps_pm_state state;
-        unsigned core = cpu_data[cpu].core;
+        unsigned core = cpu_core(&cpu_data[cpu]);
         void *entry_fn, *core_rc;
 
         for (state = CPS_PM_NC_WAIT; state < CPS_PM_STATE_COUNT; state++) {
@@ -692,7 +691,7 @@ static int __init cps_pm_init(void)
         /* Detect whether a CPC is present */
         if (mips_cpc_present()) {
                 /* Detect whether clock gating is implemented */
-                if (read_cpc_cl_stat_conf() & CPC_Cx_STAT_CONF_CLKGAT_IMPL_MSK)
+                if (read_cpc_cl_stat_conf() & CPC_Cx_STAT_CONF_CLKGAT_IMPL)
                         set_bit(CPS_PM_CLOCK_GATED, state_support);
                 else
                         pr_warn("pm-cps: CPC does not support clock gating\n");
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 70604c753aa4..bd9bf528f19b 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -134,13 +134,13 @@ static int show_cpuinfo(struct seq_file *m, void *v)
         seq_printf(m, "kscratch registers\t: %d\n",
                       hweight8(cpu_data[n].kscratch_mask));
         seq_printf(m, "package\t\t\t: %d\n", cpu_data[n].package);
-        seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
+        seq_printf(m, "core\t\t\t: %d\n", cpu_core(&cpu_data[n]));
 
 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
         if (cpu_has_mipsmt)
-                seq_printf(m, "VPE\t\t\t: %d\n", cpu_data[n].vpe_id);
+                seq_printf(m, "VPE\t\t\t: %d\n", cpu_vpe_id(&cpu_data[n]));
         else if (cpu_has_vp)
-                seq_printf(m, "VP\t\t\t: %d\n", cpu_data[n].vpe_id);
+                seq_printf(m, "VP\t\t\t: %d\n", cpu_vpe_id(&cpu_data[n]));
 #endif
 
         sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 5351e1f3950d..c5ff6bfe2825 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -208,13 +208,13 @@ static inline int is_ra_save_ins(union mips_instruction *ip, int *poff)
          *
          * microMIPS is way more fun...
          */
-        if (mm_insn_16bit(ip->halfword[1])) {
+        if (mm_insn_16bit(ip->word >> 16)) {
                 switch (ip->mm16_r5_format.opcode) {
                 case mm_swsp16_op:
                         if (ip->mm16_r5_format.rt != 31)
                                 return 0;
 
-                        *poff = ip->mm16_r5_format.simmediate;
+                        *poff = ip->mm16_r5_format.imm;
                         *poff = (*poff << 2) / sizeof(ulong);
                         return 1;
 
@@ -287,7 +287,7 @@ static inline int is_jump_ins(union mips_instruction *ip)
          *
          * microMIPS is kind of more fun...
          */
-        if (mm_insn_16bit(ip->halfword[1])) {
+        if (mm_insn_16bit(ip->word >> 16)) {
                 if ((ip->mm16_r5_format.opcode == mm_pool16c_op &&
                     (ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op))
                         return 1;
@@ -313,9 +313,11 @@ static inline int is_jump_ins(union mips_instruction *ip)
 #endif
 }
 
-static inline int is_sp_move_ins(union mips_instruction *ip)
+static inline int is_sp_move_ins(union mips_instruction *ip, int *frame_size)
 {
 #ifdef CONFIG_CPU_MICROMIPS
+        unsigned short tmp;
+
         /*
          * addiusp -imm
          * addius5 sp,-imm
@@ -324,21 +326,40 @@ static inline int is_sp_move_ins(union mips_instruction *ip)
          *
          * microMIPS is not more fun...
          */
-        if (mm_insn_16bit(ip->halfword[1])) {
-                return (ip->mm16_r3_format.opcode == mm_pool16d_op &&
-                        ip->mm16_r3_format.simmediate && mm_addiusp_func) ||
-                       (ip->mm16_r5_format.opcode == mm_pool16d_op &&
-                        ip->mm16_r5_format.rt == 29);
+        if (mm_insn_16bit(ip->word >> 16)) {
+                if (ip->mm16_r3_format.opcode == mm_pool16d_op &&
+                    ip->mm16_r3_format.simmediate & mm_addiusp_func) {
+                        tmp = ip->mm_b0_format.simmediate >> 1;
+                        tmp = ((tmp & 0x1ff) ^ 0x100) - 0x100;
+                        if ((tmp + 2) < 4) /* 0x0,0x1,0x1fe,0x1ff are special */
+                                tmp ^= 0x100;
+                        *frame_size = -(signed short)(tmp << 2);
+                        return 1;
+                }
+                if (ip->mm16_r5_format.opcode == mm_pool16d_op &&
+                    ip->mm16_r5_format.rt == 29) {
+                        tmp = ip->mm16_r5_format.imm >> 1;
+                        *frame_size = -(signed short)(tmp & 0xf);
+                        return 1;
+                }
+                return 0;
         }
 
-        return ip->mm_i_format.opcode == mm_addiu32_op &&
-               ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29;
+        if (ip->mm_i_format.opcode == mm_addiu32_op &&
+            ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29) {
+                *frame_size = -ip->i_format.simmediate;
+                return 1;
+        }
 #else
         /* addiu/daddiu sp,sp,-imm */
         if (ip->i_format.rs != 29 || ip->i_format.rt != 29)
                 return 0;
-        if (ip->i_format.opcode == addiu_op || ip->i_format.opcode == daddiu_op)
+
+        if (ip->i_format.opcode == addiu_op ||
+            ip->i_format.opcode == daddiu_op) {
+                *frame_size = -ip->i_format.simmediate;
                 return 1;
+        }
 #endif
         return 0;
 }
@@ -348,7 +369,9 @@ static int get_frame_info(struct mips_frame_info *info)
         bool is_mmips = IS_ENABLED(CONFIG_CPU_MICROMIPS);
         union mips_instruction insn, *ip, *ip_end;
         const unsigned int max_insns = 128;
+        unsigned int last_insn_size = 0;
         unsigned int i;
+        bool saw_jump = false;
 
         info->pc_offset = -1;
         info->frame_size = 0;
@@ -359,47 +382,44 @@ static int get_frame_info(struct mips_frame_info *info)
 
         ip_end = (void *)ip + info->func_size;
 
-        for (i = 0; i < max_insns && ip < ip_end; i++, ip++) {
+        for (i = 0; i < max_insns && ip < ip_end; i++) {
+                ip = (void *)ip + last_insn_size;
                 if (is_mmips && mm_insn_16bit(ip->halfword[0])) {
-                        insn.halfword[0] = 0;
-                        insn.halfword[1] = ip->halfword[0];
+                        insn.word = ip->halfword[0] << 16;
+                        last_insn_size = 2;
                 } else if (is_mmips) {
-                        insn.halfword[0] = ip->halfword[1];
-                        insn.halfword[1] = ip->halfword[0];
+                        insn.word = ip->halfword[0] << 16 | ip->halfword[1];
+                        last_insn_size = 4;
                 } else {
                         insn.word = ip->word;
+                        last_insn_size = 4;
                 }
 
-                if (is_jump_ins(&insn))
-                        break;
-
                 if (!info->frame_size) {
-                        if (is_sp_move_ins(&insn))
-                        {
-#ifdef CONFIG_CPU_MICROMIPS
-                                if (mm_insn_16bit(ip->halfword[0]))
-                                {
-                                        unsigned short tmp;
-
-                                        if (ip->halfword[0] & mm_addiusp_func)
-                                        {
-                                                tmp = (((ip->halfword[0] >> 1) & 0x1ff) << 2);
-                                                info->frame_size = -(signed short)(tmp | ((tmp & 0x100) ? 0xfe00 : 0));
-                                        } else {
-                                                tmp = (ip->halfword[0] >> 1);
-                                                info->frame_size = -(signed short)(tmp & 0xf);
-                                        }
-                                        ip = (void *) &ip->halfword[1];
-                                        ip--;
-                                } else
-#endif
-                                info->frame_size = - ip->i_format.simmediate;
-                        }
+                        is_sp_move_ins(&insn, &info->frame_size);
+                        continue;
+                } else if (!saw_jump && is_jump_ins(ip)) {
+                        /*
+                         * If we see a jump instruction, we are finished
+                         * with the frame save.
+                         *
+                         * Some functions can have a shortcut return at
+                         * the beginning of the function, so don't start
+                         * looking for jump instruction until we see the
+                         * frame setup.
+                         *
+                         * The RA save instruction can get put into the
+                         * delay slot of the jump instruction, so look
+                         * at the next instruction, too.
+                         */
+                        saw_jump = true;
                         continue;
                 }
                 if (info->pc_offset == -1 &&
                     is_ra_save_ins(&insn, &info->pc_offset))
                         break;
+                if (saw_jump)
+                        break;
         }
         if (info->frame_size && info->pc_offset >= 0) /* nested */
                 return 0;
diff --git a/arch/mips/kernel/r2300_fpu.S b/arch/mips/kernel/r2300_fpu.S
index 918f2f6d3861..3062ba66c563 100644
--- a/arch/mips/kernel/r2300_fpu.S
+++ b/arch/mips/kernel/r2300_fpu.S
@@ -12,7 +12,9 @@
  * Copyright (c) 1998 Harald Koerfgen
  */
 #include <asm/asm.h>
+#include <asm/asmmacro.h>
 #include <asm/errno.h>
+#include <asm/export.h>
 #include <asm/fpregdef.h>
 #include <asm/mipsregs.h>
 #include <asm/asm-offsets.h>
@@ -31,9 +33,85 @@
         PTR     9b+4,bad_stack;                                 \
         .previous
 
-        .set    noreorder
         .set    mips1
 
+/*
+ * Save a thread's fp context.
+ */
+LEAF(_save_fp)
+EXPORT_SYMBOL(_save_fp)
+        fpu_save_single a0, t1                  # clobbers t1
+        jr      ra
+        END(_save_fp)
+
+/*
+ * Restore a thread's fp context.
+ */
+LEAF(_restore_fp)
+        fpu_restore_single a0, t1               # clobbers t1
+        jr      ra
+        END(_restore_fp)
+
+/*
+ * Load the FPU with signalling NANS.  This bit pattern we're using has
+ * the property that no matter whether considered as single or as double
+ * precision represents signaling NANS.
+ *
+ * The value to initialize fcr31 to comes in $a0.
+ */
+
+        .set push
+        SET_HARDFLOAT
+
+LEAF(_init_fpu)
+        mfc0    t0, CP0_STATUS
+        li      t1, ST0_CU1
+        or      t0, t1
+        mtc0    t0, CP0_STATUS
+
+        ctc1    a0, fcr31
+
+        li      t0, -1
+
+        mtc1    t0, $f0
+        mtc1    t0, $f1
+        mtc1    t0, $f2
+        mtc1    t0, $f3
+        mtc1    t0, $f4
+        mtc1    t0, $f5
+        mtc1    t0, $f6
+        mtc1    t0, $f7
+        mtc1    t0, $f8
+        mtc1    t0, $f9
+        mtc1    t0, $f10
+        mtc1    t0, $f11
+        mtc1    t0, $f12
+        mtc1    t0, $f13
+        mtc1    t0, $f14
+        mtc1    t0, $f15
+        mtc1    t0, $f16
+        mtc1    t0, $f17
+        mtc1    t0, $f18
+        mtc1    t0, $f19
+        mtc1    t0, $f20
+        mtc1    t0, $f21
+        mtc1    t0, $f22
+        mtc1    t0, $f23
+        mtc1    t0, $f24
+        mtc1    t0, $f25
+        mtc1    t0, $f26
+        mtc1    t0, $f27
+        mtc1    t0, $f28
+        mtc1    t0, $f29
+        mtc1    t0, $f30
+        mtc1    t0, $f31
+        jr      ra
+        END(_init_fpu)
+
+        .set pop
+
+        .set    noreorder
+
 /**
  * _save_fp_context() - save FP context from the FPU
  * @a0 - pointer to fpregs field of sigcontext
diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S
index 1049eeafd97d..e57703b1de50 100644
--- a/arch/mips/kernel/r2300_switch.S
+++ b/arch/mips/kernel/r2300_switch.S
@@ -26,12 +26,6 @@
         .align  5
 
 /*
- * Offset to the current process status flags, the first 32 bytes of the
- * stack are not used.
- */
-#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
-
-/*
  * task_struct *resume(task_struct *prev, task_struct *next,
  *                     struct thread_info *next_ti)
  */
@@ -68,78 +62,3 @@ LEAF(resume)
         move    v0, a0
         jr      ra
         END(resume)
-
-/*
- * Save a thread's fp context.
- */
-LEAF(_save_fp)
-EXPORT_SYMBOL(_save_fp)
-        fpu_save_single a0, t1                  # clobbers t1
-        jr      ra
-        END(_save_fp)
-
-/*
- * Restore a thread's fp context.
- */
-LEAF(_restore_fp)
-        fpu_restore_single a0, t1               # clobbers t1
-        jr      ra
-        END(_restore_fp)
-
-/*
- * Load the FPU with signalling NANS.  This bit pattern we're using has
- * the property that no matter whether considered as single or as double
- * precision represents signaling NANS.
- *
- * The value to initialize fcr31 to comes in $a0.
- */
-
-        .set push
-        SET_HARDFLOAT
-
-LEAF(_init_fpu)
-        mfc0    t0, CP0_STATUS
-        li      t1, ST0_CU1
-        or      t0, t1
-        mtc0    t0, CP0_STATUS
-
-        ctc1    a0, fcr31
-
-        li      t0, -1
-
-        mtc1    t0, $f0
-        mtc1    t0, $f1
-        mtc1    t0, $f2
-        mtc1    t0, $f3
-        mtc1    t0, $f4
-        mtc1    t0, $f5
-        mtc1    t0, $f6
-        mtc1    t0, $f7
-        mtc1    t0, $f8
-        mtc1    t0, $f9
-        mtc1    t0, $f10
-        mtc1    t0, $f11
-        mtc1    t0, $f12
-        mtc1    t0, $f13
-        mtc1    t0, $f14
-        mtc1    t0, $f15
-        mtc1    t0, $f16
-        mtc1    t0, $f17
-        mtc1    t0, $f18
-        mtc1    t0, $f19
-        mtc1    t0, $f20
-        mtc1    t0, $f21
-        mtc1    t0, $f22
-        mtc1    t0, $f23
-        mtc1    t0, $f24
-        mtc1    t0, $f25
-        mtc1    t0, $f26
-        mtc1    t0, $f27
-        mtc1    t0, $f28
-        mtc1    t0, $f29
-        mtc1    t0, $f30
-        mtc1    t0, $f31
-        jr      ra
-        END(_init_fpu)
-
-        .set pop
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index 56d86b09c917..0a83b1708b3c 100644
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -15,6 +15,7 @@
 #include <asm/asm.h>
 #include <asm/asmmacro.h>
 #include <asm/errno.h>
+#include <asm/export.h>
 #include <asm/fpregdef.h>
 #include <asm/mipsregs.h>
 #include <asm/asm-offsets.h>
@@ -34,6 +35,201 @@
         .previous
         .endm
 
+/*
+ * Save a thread's fp context.
+ */
+LEAF(_save_fp)
+EXPORT_SYMBOL(_save_fp)
+#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
+                defined(CONFIG_CPU_MIPS32_R6)
+        mfc0    t0, CP0_STATUS
+#endif
+        fpu_save_double a0 t0 t1                # clobbers t1
+        jr      ra
+        END(_save_fp)
+
+/*
+ * Restore a thread's fp context.
+ */
+LEAF(_restore_fp)
+#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
+                defined(CONFIG_CPU_MIPS32_R6)
+        mfc0    t0, CP0_STATUS
+#endif
+        fpu_restore_double a0 t0 t1             # clobbers t1
+        jr      ra
+        END(_restore_fp)
+
+#ifdef CONFIG_CPU_HAS_MSA
+
+/*
+ * Save a thread's MSA vector context.
+ */
+LEAF(_save_msa)
+EXPORT_SYMBOL(_save_msa)
+        msa_save_all    a0
+        jr      ra
+        END(_save_msa)
+
+/*
+ * Restore a thread's MSA vector context.
+ */
+LEAF(_restore_msa)
+        msa_restore_all a0
+        jr      ra
+        END(_restore_msa)
+
+LEAF(_init_msa_upper)
+        msa_init_all_upper
+        jr      ra
+        END(_init_msa_upper)
+
+#endif
+
+/*
+ * Load the FPU with signalling NANS.  This bit pattern we're using has
+ * the property that no matter whether considered as single or as double
+ * precision represents signaling NANS.
+ *
+ * The value to initialize fcr31 to comes in $a0.
+ */
+
+        .set push
+        SET_HARDFLOAT
+
+LEAF(_init_fpu)
+        mfc0    t0, CP0_STATUS
+        li      t1, ST0_CU1
+        or      t0, t1
+        mtc0    t0, CP0_STATUS
+        enable_fpu_hazard
+
+        ctc1    a0, fcr31
+
+        li      t1, -1                          # SNaN
+
+#ifdef CONFIG_64BIT
+        sll     t0, t0, 5
+        bgez    t0, 1f                          # 16 / 32 register mode?
+
+        dmtc1   t1, $f1
+        dmtc1   t1, $f3
+        dmtc1   t1, $f5
+        dmtc1   t1, $f7
+        dmtc1   t1, $f9
+        dmtc1   t1, $f11
+        dmtc1   t1, $f13
+        dmtc1   t1, $f15
+        dmtc1   t1, $f17
+        dmtc1   t1, $f19
+        dmtc1   t1, $f21
+        dmtc1   t1, $f23
+        dmtc1   t1, $f25
+        dmtc1   t1, $f27
+        dmtc1   t1, $f29
+        dmtc1   t1, $f31
+1:
+#endif
+
+#ifdef CONFIG_CPU_MIPS32
+        mtc1    t1, $f0
+        mtc1    t1, $f1
+        mtc1    t1, $f2
+        mtc1    t1, $f3
+        mtc1    t1, $f4
+        mtc1    t1, $f5
+        mtc1    t1, $f6
+        mtc1    t1, $f7
+        mtc1    t1, $f8
+        mtc1    t1, $f9
+        mtc1    t1, $f10
+        mtc1    t1, $f11
+        mtc1    t1, $f12
+        mtc1    t1, $f13
+        mtc1    t1, $f14
+        mtc1    t1, $f15
+        mtc1    t1, $f16
+        mtc1    t1, $f17
+        mtc1    t1, $f18
+        mtc1    t1, $f19
+        mtc1    t1, $f20
+        mtc1    t1, $f21
+        mtc1    t1, $f22
+        mtc1    t1, $f23
+        mtc1    t1, $f24
+        mtc1    t1, $f25
+        mtc1    t1, $f26
+        mtc1    t1, $f27
+        mtc1    t1, $f28
+        mtc1    t1, $f29
+        mtc1    t1, $f30
+        mtc1    t1, $f31
+
+#if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS32_R6)
+        .set    push
+        .set    MIPS_ISA_LEVEL_RAW
+        .set    fp=64
+        sll     t0, t0, 5                       # is Status.FR set?
+        bgez    t0, 1f                          # no: skip setting upper 32b
+
+        mthc1   t1, $f0
+        mthc1   t1, $f1
+        mthc1   t1, $f2
+        mthc1   t1, $f3
+        mthc1   t1, $f4
+        mthc1   t1, $f5
+        mthc1   t1, $f6
+        mthc1   t1, $f7
+        mthc1   t1, $f8
+        mthc1   t1, $f9
+        mthc1   t1, $f10
+        mthc1   t1, $f11
+        mthc1   t1, $f12
+        mthc1   t1, $f13
+        mthc1   t1, $f14
+        mthc1   t1, $f15
+        mthc1   t1, $f16
+        mthc1   t1, $f17
+        mthc1   t1, $f18
+        mthc1   t1, $f19
+        mthc1   t1, $f20
+        mthc1   t1, $f21
+        mthc1   t1, $f22
+        mthc1   t1, $f23
+        mthc1   t1, $f24
+        mthc1   t1, $f25
+        mthc1   t1, $f26
+        mthc1   t1, $f27
+        mthc1   t1, $f28
+        mthc1   t1, $f29
+        mthc1   t1, $f30
+        mthc1   t1, $f31
+1:      .set    pop
+#endif /* CONFIG_CPU_MIPS32_R2 || CONFIG_CPU_MIPS32_R6 */
+#else
+        .set    MIPS_ISA_ARCH_LEVEL_RAW
+        dmtc1   t1, $f0
+        dmtc1   t1, $f2
+        dmtc1   t1, $f4
+        dmtc1   t1, $f6
+        dmtc1   t1, $f8
+        dmtc1   t1, $f10
+        dmtc1   t1, $f12
+        dmtc1   t1, $f14
+        dmtc1   t1, $f16
+        dmtc1   t1, $f18
+        dmtc1   t1, $f20
+        dmtc1   t1, $f22
+        dmtc1   t1, $f24
+        dmtc1   t1, $f26
+        dmtc1   t1, $f28
+        dmtc1   t1, $f30
+#endif
+        jr      ra
+        END(_init_fpu)
+
+        .set pop        /* SET_HARDFLOAT */
+
         .set    noreorder
 
 /**
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 7b386d54fd65..17cf9341c1cf 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -12,8 +12,6 @@
  */
 #include <asm/asm.h>
 #include <asm/cachectl.h>
-#include <asm/export.h>
-#include <asm/fpregdef.h>
 #include <asm/mipsregs.h>
 #include <asm/asm-offsets.h>
 #include <asm/regdef.h>
@@ -22,10 +20,6 @@
 
 #include <asm/asmmacro.h>
 
-/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
-#undef fp
-
-#ifndef USE_ALTERNATE_RESUME_IMPL
 /*
  * task_struct *resume(task_struct *prev, task_struct *next,
  *                     struct thread_info *next_ti)
@@ -63,200 +57,3 @@
         move    v0, a0
         jr      ra
         END(resume)
-
-#endif /* USE_ALTERNATE_RESUME_IMPL */
-
-/*
- * Save a thread's fp context.
- */
-LEAF(_save_fp)
-EXPORT_SYMBOL(_save_fp)
-#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
-                defined(CONFIG_CPU_MIPS32_R6)
-        mfc0    t0, CP0_STATUS
-#endif
-        fpu_save_double a0 t0 t1                # clobbers t1
-        jr      ra
-        END(_save_fp)
-
-/*
- * Restore a thread's fp context.
- */
-LEAF(_restore_fp)
-#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \
-                defined(CONFIG_CPU_MIPS32_R6)
-        mfc0    t0, CP0_STATUS
-#endif
-        fpu_restore_double a0 t0 t1             # clobbers t1
-        jr      ra
-        END(_restore_fp)
-
-#ifdef CONFIG_CPU_HAS_MSA
-
-/*
- * Save a thread's MSA vector context.
- */
-LEAF(_save_msa)
-EXPORT_SYMBOL(_save_msa)
-        msa_save_all    a0
-        jr      ra
-        END(_save_msa)
-
-/*
- * Restore a thread's MSA vector context.
- */
-LEAF(_restore_msa)
-        msa_restore_all a0
-        jr      ra
-        END(_restore_msa)
-
-LEAF(_init_msa_upper)
-        msa_init_all_upper
-        jr      ra
-        END(_init_msa_upper)
-
-#endif
-
-/*
- * Load the FPU with signalling NANS.  This bit pattern we're using has
- * the property that no matter whether considered as single or as double
- * precision represents signaling NANS.
- *
- * The value to initialize fcr31 to comes in $a0.
- */
-
-        .set push
-        SET_HARDFLOAT
-
-LEAF(_init_fpu)
-        mfc0    t0, CP0_STATUS
-        li      t1, ST0_CU1
-        or      t0, t1
-        mtc0    t0, CP0_STATUS
-        enable_fpu_hazard
-
-        ctc1    a0, fcr31
-
-        li      t1, -1                          # SNaN
-
-#ifdef CONFIG_64BIT
-        sll     t0, t0, 5
-        bgez    t0, 1f                          # 16 / 32 register mode?
-
-        dmtc1   t1, $f1
-        dmtc1   t1, $f3
-        dmtc1   t1, $f5
-        dmtc1   t1, $f7
-        dmtc1   t1, $f9
-        dmtc1   t1, $f11
-        dmtc1   t1, $f13
-        dmtc1   t1, $f15
-        dmtc1   t1, $f17
-        dmtc1   t1, $f19
-        dmtc1   t1, $f21
-        dmtc1   t1, $f23
-        dmtc1   t1, $f25
-        dmtc1   t1, $f27
-        dmtc1   t1, $f29
-        dmtc1   t1, $f31
-1:
-#endif
-
-#ifdef CONFIG_CPU_MIPS32
-        mtc1    t1, $f0
-        mtc1    t1, $f1
-        mtc1    t1, $f2
-        mtc1    t1, $f3
-        mtc1    t1, $f4
-        mtc1    t1, $f5
-        mtc1    t1, $f6
-        mtc1    t1, $f7
-        mtc1    t1, $f8
-        mtc1    t1, $f9
-        mtc1    t1, $f10
-        mtc1    t1, $f11
-        mtc1    t1, $f12
-        mtc1    t1, $f13
-        mtc1    t1, $f14
-        mtc1    t1, $f15
-        mtc1    t1, $f16
-        mtc1    t1, $f17
-        mtc1    t1, $f18
-        mtc1    t1, $f19
-        mtc1    t1, $f20
-        mtc1    t1, $f21
-        mtc1    t1, $f22
-        mtc1    t1, $f23
-        mtc1    t1, $f24
-        mtc1    t1, $f25
-        mtc1    t1, $f26
-        mtc1    t1, $f27
-        mtc1    t1, $f28
-        mtc1    t1, $f29
-        mtc1    t1, $f30
-        mtc1    t1, $f31
-
-#if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS32_R6)
-        .set    push
-        .set    MIPS_ISA_LEVEL_RAW
-        .set    fp=64
-        sll     t0, t0, 5                       # is Status.FR set?
-        bgez    t0, 1f                          # no: skip setting upper 32b
-
-        mthc1   t1, $f0
-        mthc1   t1, $f1
-        mthc1   t1, $f2
-        mthc1   t1, $f3
-        mthc1   t1, $f4
-        mthc1   t1, $f5
-        mthc1   t1, $f6
-        mthc1   t1, $f7
-        mthc1   t1, $f8
-        mthc1   t1, $f9
-        mthc1   t1, $f10
-        mthc1   t1, $f11
-        mthc1   t1, $f12
-        mthc1   t1, $f13
-        mthc1   t1, $f14
-        mthc1   t1, $f15
-        mthc1   t1, $f16
-        mthc1   t1, $f17
-        mthc1   t1, $f18
-        mthc1   t1, $f19
-        mthc1   t1, $f20
-        mthc1   t1, $f21
-        mthc1   t1, $f22
-        mthc1   t1, $f23
-        mthc1   t1, $f24
-        mthc1   t1, $f25
-        mthc1   t1, $f26
-        mthc1   t1, $f27
-        mthc1   t1, $f28
-        mthc1   t1, $f29
-        mthc1   t1, $f30
-        mthc1   t1, $f31
-1:      .set    pop
-#endif /* CONFIG_CPU_MIPS32_R2 || CONFIG_CPU_MIPS32_R6 */
-#else
-        .set    MIPS_ISA_ARCH_LEVEL_RAW
-        dmtc1   t1, $f0
-        dmtc1   t1, $f2
-        dmtc1   t1, $f4
-        dmtc1   t1, $f6
-        dmtc1   t1, $f8
-        dmtc1   t1, $f10
-        dmtc1   t1, $f12
-        dmtc1   t1, $f14
-        dmtc1   t1, $f16
-        dmtc1   t1, $f18
-        dmtc1   t1, $f20
-        dmtc1   t1, $f22
-        dmtc1   t1, $f24
-        dmtc1   t1, $f26
-        dmtc1   t1, $f28
-        dmtc1   t1, $f30
-#endif
-        jr      ra
-        END(_init_fpu)
-
-        .set pop        /* SET_HARDFLOAT */
diff --git a/arch/mips/kernel/r6000_fpu.S b/arch/mips/kernel/r6000_fpu.S
deleted file mode 100644
index 9cc7bfab3419..000000000000
--- a/arch/mips/kernel/r6000_fpu.S
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * r6000_fpu.S: Save/restore floating point context for signal handlers.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996 by Ralf Baechle
- *
- * Multi-arch abstraction and asm macros for easier reading:
- * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
- */
-#include <asm/asm.h>
-#include <asm/fpregdef.h>
-#include <asm/mipsregs.h>
-#include <asm/asm-offsets.h>
-#include <asm/regdef.h>
-
-        .set    noreorder
-        .set    mips2
-        .set    push
-        SET_HARDFLOAT
-
-/**
- * _save_fp_context() - save FP context from the FPU
- * @a0 - pointer to fpregs field of sigcontext
- * @a1 - pointer to fpc_csr field of sigcontext
- *
- * Save FP context, including the 32 FP data registers and the FP
- * control & status register, from the FPU to signal context.
- */
-        LEAF(_save_fp_context)
-        mfc0    t0,CP0_STATUS
-        sll     t0,t0,2
-        bgez    t0,1f
-         nop
-
-        cfc1    t1,fcr31
-        /* Store the 16 double precision registers */
-        sdc1    $f0,0(a0)
-        sdc1    $f2,16(a0)
-        sdc1    $f4,32(a0)
-        sdc1    $f6,48(a0)
-        sdc1    $f8,64(a0)
-        sdc1    $f10,80(a0)
-        sdc1    $f12,96(a0)
-        sdc1    $f14,112(a0)
-        sdc1    $f16,128(a0)
-        sdc1    $f18,144(a0)
-        sdc1    $f20,160(a0)
-        sdc1    $f22,176(a0)
-        sdc1    $f24,192(a0)
-        sdc1    $f26,208(a0)
-        sdc1    $f28,224(a0)
-        sdc1    $f30,240(a0)
-        jr      ra
-         sw     t0,(a1)
-1:      jr      ra
-         nop
-        END(_save_fp_context)
-
-/**
- * _restore_fp_context() - restore FP context to the FPU
- * @a0 - pointer to fpregs field of sigcontext
- * @a1 - pointer to fpc_csr field of sigcontext
- *
- * Restore FP context, including the 32 FP data registers and the FP
- * control & status register, from signal context to the FPU.
- */
-        LEAF(_restore_fp_context)
-        mfc0    t0,CP0_STATUS
-        sll     t0,t0,2
-
-        bgez    t0,1f
-         lw     t0,(a1)
-        /* Restore the 16 double precision registers */
-        ldc1    $f0,0(a0)
-        ldc1    $f2,16(a0)
-        ldc1    $f4,32(a0)
-        ldc1    $f6,48(a0)
-        ldc1    $f8,64(a0)
-        ldc1    $f10,80(a0)
-        ldc1    $f12,96(a0)
-        ldc1    $f14,112(a0)
-        ldc1    $f16,128(a0)
-        ldc1    $f18,144(a0)
-        ldc1    $f20,160(a0)
-        ldc1    $f22,176(a0)
-        ldc1    $f24,192(a0)
-        ldc1    $f26,208(a0)
-        ldc1    $f28,224(a0)
-        ldc1    $f30,240(a0)
-        jr      ra
-         ctc1   t0,fcr31
-1:      jr      ra
-         nop
-        END(_restore_fp_context)
-
-        .set pop        /* SET_HARDFLOAT */
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 1b070a76fcdd..406072e26752 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -179,7 +179,7 @@ static void bmips_prepare_cpus(unsigned int max_cpus)
 /*
  * Tell the hardware to boot CPUx - runs on CPU0
  */
-static void bmips_boot_secondary(int cpu, struct task_struct *idle)
+static int bmips_boot_secondary(int cpu, struct task_struct *idle)
 {
         bmips_smp_boot_sp = __KSTK_TOS(idle);
         bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
@@ -231,6 +231,8 @@ static void bmips_boot_secondary(int cpu, struct task_struct *idle)
                 }
                 cpumask_set_cpu(cpu, &bmips_booted_mask);
         }
+
+        return 0;
 }
 
 /*
@@ -245,7 +247,7 @@ static void bmips_init_secondary(void)
                 break;
         case CPU_BMIPS5000:
                 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
-                current_cpu_data.core = (read_c0_brcm_config() >> 25) & 3;
+                cpu_set_core(&current_cpu_data, (read_c0_brcm_config() >> 25) & 3);
                 break;
         }
 }
@@ -409,7 +411,7 @@ void __ref play_dead(void)
 
 #endif /* CONFIG_HOTPLUG_CPU */
 
-struct plat_smp_ops bmips43xx_smp_ops = {
+const struct plat_smp_ops bmips43xx_smp_ops = {
         .smp_setup              = bmips_smp_setup,
         .prepare_cpus           = bmips_prepare_cpus,
         .boot_secondary         = bmips_boot_secondary,
@@ -423,7 +425,7 @@ struct plat_smp_ops bmips43xx_smp_ops = {
 #endif
 };
 
-struct plat_smp_ops bmips5000_smp_ops = {
+const struct plat_smp_ops bmips5000_smp_ops = {
         .smp_setup              = bmips_smp_setup,
         .prepare_cpus           = bmips_prepare_cpus,
         .boot_secondary         = bmips_boot_secondary,
diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c
index 76923349b4fe..05295a4909f1 100644
--- a/arch/mips/kernel/smp-cmp.c
+++ b/arch/mips/kernel/smp-cmp.c
@@ -24,7 +24,6 @@
 #include <linux/cpumask.h>
 #include <linux/interrupt.h>
 #include <linux/compiler.h>
-#include <linux/irqchip/mips-gic.h>
 
 #include <linux/atomic.h>
 #include <asm/cacheflush.h>
@@ -78,7 +77,7 @@ static void cmp_smp_finish(void)
  * __KSTK_TOS(idle) is apparently the stack pointer
  * (unsigned long)idle->thread_info the gp
  */
-static void cmp_boot_secondary(int cpu, struct task_struct *idle)
+static int cmp_boot_secondary(int cpu, struct task_struct *idle)
 {
         struct thread_info *gp = task_thread_info(idle);
         unsigned long sp = __KSTK_TOS(idle);
@@ -95,6 +94,7 @@ static void cmp_boot_secondary(int cpu, struct task_struct *idle)
 #endif
 
         amon_cpu_start(cpu, pc, sp, (unsigned long)gp, a0);
+        return 0;
 }
 
 /*
@@ -148,7 +148,7 @@ void __init cmp_prepare_cpus(unsigned int max_cpus)
 
 }
 
-struct plat_smp_ops cmp_smp_ops = {
+const struct plat_smp_ops cmp_smp_ops = {
         .send_ipi_single        = mips_smp_send_ipi_single,
         .send_ipi_mask          = mips_smp_send_ipi_mask,
         .init_secondary         = cmp_init_secondary,
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index f832e99ad4c3..0063122c85da 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -11,7 +11,6 @@
 #include <linux/cpu.h>
 #include <linux/delay.h>
 #include <linux/io.h>
-#include <linux/irqchip/mips-gic.h>
 #include <linux/sched/task_stack.h>
 #include <linux/sched/hotplug.h>
 #include <linux/slab.h>
@@ -19,8 +18,7 @@
 #include <linux/types.h>
 
 #include <asm/bcache.h>
-#include <asm/mips-cm.h>
-#include <asm/mips-cpc.h>
+#include <asm/mips-cps.h>
 #include <asm/mips_mt.h>
 #include <asm/mipsregs.h>
 #include <asm/pm-cps.h>
@@ -41,55 +39,58 @@ static int __init setup_nothreads(char *s)
 }
 early_param("nothreads", setup_nothreads);
 
-static unsigned core_vpe_count(unsigned core)
+static unsigned core_vpe_count(unsigned int cluster, unsigned core)
 {
-        unsigned cfg;
-
         if (threads_disabled)
                 return 1;
 
-        if ((!IS_ENABLED(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
-                && (!IS_ENABLED(CONFIG_CPU_MIPSR6) || !cpu_has_vp))
-                return 1;
-
-        mips_cm_lock_other(core, 0);
-        cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
-        mips_cm_unlock_other();
-        return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
+        return mips_cps_numvps(cluster, core);
 }
 
 static void __init cps_smp_setup(void)
 {
-        unsigned int ncores, nvpes, core_vpes;
+        unsigned int nclusters, ncores, nvpes, core_vpes;
         unsigned long core_entry;
-        int c, v;
+        int cl, c, v;
 
         /* Detect & record VPE topology */
-        ncores = mips_cm_numcores();
+        nvpes = 0;
+        nclusters = mips_cps_numclusters();
         pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE");
-        for (c = nvpes = 0; c < ncores; c++) {
-                core_vpes = core_vpe_count(c);
-                pr_cont("%c%u", c ? ',' : '{', core_vpes);
-
-                /* Use the number of VPEs in core 0 for smp_num_siblings */
-                if (!c)
-                        smp_num_siblings = core_vpes;
-
-                for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
-                        cpu_data[nvpes + v].core = c;
-#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
-                        cpu_data[nvpes + v].vpe_id = v;
-#endif
+        for (cl = 0; cl < nclusters; cl++) {
+                if (cl > 0)
+                        pr_cont(",");
+                pr_cont("{");
+
+                ncores = mips_cps_numcores(cl);
+                for (c = 0; c < ncores; c++) {
+                        core_vpes = core_vpe_count(cl, c);
+
+                        if (c > 0)
+                                pr_cont(",");
+                        pr_cont("%u", core_vpes);
+
+                        /* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */
+                        if (!cl && !c)
+                                smp_num_siblings = core_vpes;
+
+                        for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
+                                cpu_set_cluster(&cpu_data[nvpes + v], cl);
+                                cpu_set_core(&cpu_data[nvpes + v], c);
+                                cpu_set_vpe_id(&cpu_data[nvpes + v], v);
+                        }
+
+                        nvpes += core_vpes;
                 }
 
-                nvpes += core_vpes;
+                pr_cont("}");
         }
-        pr_cont("} total %u\n", nvpes);
+        pr_cont(" total %u\n", nvpes);
 
         /* Indicate present CPUs (CPU being synonymous with VPE) */
         for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
-                set_cpu_possible(v, true);
-                set_cpu_present(v, true);
+                set_cpu_possible(v, cpu_cluster(&cpu_data[v]) == 0);
+                set_cpu_present(v, cpu_cluster(&cpu_data[v]) == 0);
                 __cpu_number_map[v] = v;
                 __cpu_logical_map[v] = v;
         }
@@ -121,7 +122,7 @@ static void __init cps_smp_setup(void)
 static void __init cps_prepare_cpus(unsigned int max_cpus)
 {
         unsigned ncores, core_vpes, c, cca;
-        bool cca_unsuitable;
+        bool cca_unsuitable, cores_limited;
         u32 *entry_code;
 
         mips_mt_set_cpuoptions();
@@ -141,19 +142,22 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
         }
 
         /* Warn the user if the CCA prevents multi-core */
-        ncores = mips_cm_numcores();
-        if ((cca_unsuitable || cpu_has_dc_aliases) && ncores > 1) {
+        cores_limited = false;
+        if (cca_unsuitable || cpu_has_dc_aliases) {
+                for_each_present_cpu(c) {
+                        if (cpus_are_siblings(smp_processor_id(), c))
+                                continue;
+
+                        set_cpu_present(c, false);
+                        cores_limited = true;
+                }
+        }
+        if (cores_limited)
                 pr_warn("Using only one core due to %s%s%s\n",
                         cca_unsuitable ? "unsuitable CCA" : "",
                         (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "",
                         cpu_has_dc_aliases ? "dcache aliasing" : "");
 
-                for_each_present_cpu(c) {
-                        if (cpu_data[c].core)
-                                set_cpu_present(c, false);
-                }
-        }
-
         /*
          * Patch the start of mips_cps_core_entry to provide:
          *
@@ -168,6 +172,7 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
         __sync();
 
         /* Allocate core boot configuration structs */
+        ncores = mips_cps_numcores(0);
         mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
                                         GFP_KERNEL);
         if (!mips_cps_core_bootcfg) {
@@ -177,7 +182,7 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
 
         /* Allocate VPE boot configuration structs */
         for (c = 0; c < ncores; c++) {
-                core_vpes = core_vpe_count(c);
+                core_vpes = core_vpe_count(0, c);
                 mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
                                 sizeof(*mips_cps_core_bootcfg[c].vpe_config),
                                 GFP_KERNEL);
@@ -189,7 +194,7 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
         }
 
         /* Mark this CPU as booted */
-        atomic_set(&mips_cps_core_bootcfg[current_cpu_data.core].vpe_mask,
+        atomic_set(&mips_cps_core_bootcfg[cpu_core(&current_cpu_data)].vpe_mask,
                    1 << cpu_vpe_id(&current_cpu_data));
 
         return;
@@ -212,11 +217,11 @@ err_out:
 
 static void boot_core(unsigned int core, unsigned int vpe_id)
 {
-        u32 access, stat, seq_state;
+        u32 stat, seq_state;
         unsigned timeout;
 
         /* Select the appropriate core */
-        mips_cm_lock_other(core, 0);
+        mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
 
         /* Set its reset vector */
         write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
@@ -225,12 +230,10 @@ static void boot_core(unsigned int core, unsigned int vpe_id)
         write_gcr_co_coherence(0);
 
         /* Start it with the legacy memory map and exception base */
-        write_gcr_co_reset_ext_base(CM_GCR_RESET_EXT_BASE_UEB);
+        write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB);
 
         /* Ensure the core can access the GCRs */
-        access = read_gcr_access();
-        access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + core);
-        write_gcr_access(access);
+        set_gcr_access(1 << core);
 
         if (mips_cpc_present()) {
                 /* Reset the core */
@@ -253,7 +256,8 @@ static void boot_core(unsigned int core, unsigned int vpe_id)
                 timeout = 100;
                 while (true) {
                         stat = read_cpc_co_stat_conf();
-                        seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE_MSK;
+                        seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE;
+                        seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
 
                         /* U6 == coherent execution, ie. the core is up */
                         if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6)
@@ -285,15 +289,15 @@ static void boot_core(unsigned int core, unsigned int vpe_id)
 
 static void remote_vpe_boot(void *dummy)
 {
-        unsigned core = current_cpu_data.core;
+        unsigned core = cpu_core(&current_cpu_data);
         struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
 
         mips_cps_boot_vpes(core_cfg, cpu_vpe_id(&current_cpu_data));
 }
 
-static void cps_boot_secondary(int cpu, struct task_struct *idle)
+static int cps_boot_secondary(int cpu, struct task_struct *idle)
 {
-        unsigned core = cpu_data[cpu].core;
+        unsigned core = cpu_core(&cpu_data[cpu]);
         unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
         struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
         struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
@@ -301,6 +305,10 @@ static void cps_boot_secondary(int cpu, struct task_struct *idle)
         unsigned int remote;
         int err;
 
+        /* We don't yet support booting CPUs in other clusters */
+        if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(&current_cpu_data))
+                return -ENOSYS;
+
         vpe_cfg->pc = (unsigned long)&smp_bootstrap;
         vpe_cfg->sp = __KSTK_TOS(idle);
         vpe_cfg->gp = (unsigned long)task_thread_info(idle);
@@ -316,16 +324,16 @@ static void cps_boot_secondary(int cpu, struct task_struct *idle)
         }
 
         if (cpu_has_vp) {
-                mips_cm_lock_other(core, vpe_id);
+                mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
                 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
                 write_gcr_co_reset_base(core_entry);
                 mips_cm_unlock_other();
         }
 
-        if (core != current_cpu_data.core) {
+        if (!cpus_are_siblings(cpu, smp_processor_id())) {
                 /* Boot a VPE on another powered up core */
                 for (remote = 0; remote < NR_CPUS; remote++) {
-                        if (cpu_data[remote].core != core)
+                        if (!cpus_are_siblings(cpu, remote))
                                 continue;
                         if (cpu_online(remote))
                                 break;
@@ -349,6 +357,7 @@ static void cps_boot_secondary(int cpu, struct task_struct *idle)
         mips_cps_boot_vpes(core_cfg, vpe_id);
 out:
         preempt_enable();
+        return 0;
 }
 
 static void cps_init_secondary(void)
@@ -358,7 +367,7 @@ static void cps_init_secondary(void)
                 dmt();
 
         if (mips_cm_revision() >= CM_REV_CM3) {
-                unsigned ident = gic_read_local_vp_id();
+                unsigned int ident = read_gic_vl_ident();
 
                 /*
                  * Ensure that our calculation of the VP ID matches up with
@@ -402,7 +411,7 @@ static int cps_cpu_disable(void)
         if (!cps_pm_support_state(CPS_PM_POWER_GATED))
                 return -EINVAL;
 
-        core_cfg = &mips_cps_core_bootcfg[current_cpu_data.core];
+        core_cfg = &mips_cps_core_bootcfg[cpu_core(&current_cpu_data)];
         atomic_sub(1 << cpu_vpe_id(&current_cpu_data), &core_cfg->vpe_mask);
         smp_mb__after_atomic();
         set_cpu_online(cpu, false);
@@ -424,15 +433,17 @@ void play_dead(void)
         local_irq_disable();
         idle_task_exit();
         cpu = smp_processor_id();
-        core = cpu_data[cpu].core;
+        core = cpu_core(&cpu_data[cpu]);
         cpu_death = CPU_DEATH_POWER;
 
         pr_debug("CPU%d going offline\n", cpu);
 
         if (cpu_has_mipsmt || cpu_has_vp) {
+                core = cpu_core(&cpu_data[cpu]);
+
                 /* Look for another online VPE within the core */
                 for_each_online_cpu(cpu_death_sibling) {
-                        if (cpu_data[cpu_death_sibling].core != core)
+                        if (!cpus_are_siblings(cpu, cpu_death_sibling))
                                 continue;
 
                         /*
@@ -488,7 +499,7 @@ static void wait_for_sibling_halt(void *ptr_cpu)
 
 static void cps_cpu_die(unsigned int cpu)
 {
-        unsigned core = cpu_data[cpu].core;
+        unsigned core = cpu_core(&cpu_data[cpu]);
         unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]);
         ktime_t fail_time;
         unsigned stat;
@@ -519,10 +530,11 @@ static void cps_cpu_die(unsigned int cpu)
                  */
                 fail_time = ktime_add_ms(ktime_get(), 2000);
                 do {
-                        mips_cm_lock_other(core, 0);
+                        mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
                         mips_cpc_lock_other(core);
                         stat = read_cpc_co_stat_conf();
-                        stat &= CPC_Cx_STAT_CONF_SEQSTATE_MSK;
+                        stat &= CPC_Cx_STAT_CONF_SEQSTATE;
+                        stat >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
                         mips_cpc_unlock_other();
                         mips_cm_unlock_other();
 
@@ -544,7 +556,7 @@ static void cps_cpu_die(unsigned int cpu)
                          */
                         if (WARN(ktime_after(ktime_get(), fail_time),
                                  "CPU%u hasn't powered down, seq. state %u\n",
-                                 cpu, stat >> CPC_Cx_STAT_CONF_SEQSTATE_SHF))
+                                 cpu, stat))
                                 break;
                 } while (1);
 
@@ -562,7 +574,7 @@ static void cps_cpu_die(unsigned int cpu)
                         panic("Failed to call remote sibling CPU\n");
         } else if (cpu_has_vp) {
                 do {
-                        mips_cm_lock_other(core, vpe_id);
+                        mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
                         stat = read_cpc_co_vp_running();
                         mips_cm_unlock_other();
                 } while (stat & (1 << vpe_id));
@@ -571,7 +583,7 @@ static void cps_cpu_die(unsigned int cpu)
 
 #endif /* CONFIG_HOTPLUG_CPU */
 
-static struct plat_smp_ops cps_smp_ops = {
+static const struct plat_smp_ops cps_smp_ops = {
         .smp_setup              = cps_smp_setup,
         .prepare_cpus           = cps_prepare_cpus,
         .boot_secondary         = cps_boot_secondary,
@@ -587,7 +599,7 @@ static struct plat_smp_ops cps_smp_ops = {
 
 bool mips_cps_smp_in_use(void)
 {
-        extern struct plat_smp_ops *mp_ops;
+        extern const struct plat_smp_ops *mp_ops;
         return mp_ops == &cps_smp_ops;
 }
 
@@ -599,7 +611,7 @@ int register_cps_smp_ops(void)
         }
 
         /* check we have a GIC - we need one for IPIs */
-        if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) {
+        if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX)) {
                 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
                 return -ENODEV;
         }
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index ed6b4df583ea..94ab3276b48c 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -21,7 +21,6 @@
 #include <linux/sched.h>
 #include <linux/cpumask.h>
 #include <linux/interrupt.h>
-#include <linux/irqchip/mips-gic.h>
 #include <linux/compiler.h>
 #include <linux/sched/task_stack.h>
 #include <linux/smp.h>
@@ -36,6 +35,7 @@
 #include <asm/mipsregs.h>
 #include <asm/mipsmtregs.h>
 #include <asm/mips_mt.h>
+#include <asm/mips-cps.h>
 
 static void __init smvp_copy_vpe_config(void)
 {
@@ -83,7 +83,7 @@ static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
         if (tc != 0)
                 smvp_copy_vpe_config();
 
-        cpu_data[ncpu].vpe_id = tc;
+        cpu_set_vpe_id(&cpu_data[ncpu], tc);
 
         return ncpu;
 }
@@ -118,14 +118,12 @@ static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0)
 
 static void vsmp_init_secondary(void)
 {
-#ifdef CONFIG_MIPS_GIC
         /* This is Malta specific: IPI,performance and timer interrupts */
-        if (gic_present)
+        if (mips_gic_present())
                 change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
                                          STATUSF_IP4 | STATUSF_IP5 |
                                          STATUSF_IP6 | STATUSF_IP7);
         else
-#endif
                 change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
                                          STATUSF_IP6 | STATUSF_IP7);
 }
@@ -152,7 +150,7 @@ static void vsmp_smp_finish(void)
  * (unsigned long)idle->thread_info the gp
  * assumes a 1:1 mapping of TC => VPE
  */
-static void vsmp_boot_secondary(int cpu, struct task_struct *idle)
+static int vsmp_boot_secondary(int cpu, struct task_struct *idle)
 {
         struct thread_info *gp = task_thread_info(idle);
         dvpe();
@@ -184,6 +182,8 @@ static void vsmp_boot_secondary(int cpu, struct task_struct *idle)
         clear_c0_mvpcontrol(MVPCONTROL_VPC);
 
         evpe(EVPE_ENABLE);
+
+        return 0;
 }
 
 /*
@@ -239,7 +239,7 @@ static void __init vsmp_prepare_cpus(unsigned int max_cpus)
         mips_mt_set_cpuoptions();
 }
 
-struct plat_smp_ops vsmp_smp_ops = {
+const struct plat_smp_ops vsmp_smp_ops = {
         .send_ipi_single        = mips_smp_send_ipi_single,
         .send_ipi_mask          = mips_smp_send_ipi_mask,
         .init_secondary         = vsmp_init_secondary,
diff --git a/arch/mips/kernel/smp-up.c b/arch/mips/kernel/smp-up.c
index 17878d71ef2b..525d3196f793 100644
--- a/arch/mips/kernel/smp-up.c
+++ b/arch/mips/kernel/smp-up.c
@@ -39,8 +39,9 @@ static void up_smp_finish(void)
 /*
  * Firmware CPU startup hook
  */
-static void up_boot_secondary(int cpu, struct task_struct *idle)
+static int up_boot_secondary(int cpu, struct task_struct *idle)
 {
+        return 0;
 }
 
 static void __init up_smp_setup(void)
@@ -63,7 +64,7 @@ static void up_cpu_die(unsigned int cpu)
 }
 #endif
 
-struct plat_smp_ops up_smp_ops = {
+const struct plat_smp_ops up_smp_ops = {
         .send_ipi_single        = up_send_ipi_single,
         .send_ipi_mask          = up_send_ipi_mask,
         .init_secondary         = up_init_secondary,
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index c7cbddfcdc3b..bbe19b64def5 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -96,8 +96,7 @@ static inline void set_cpu_sibling_map(int cpu)
 
         if (smp_num_siblings > 1) {
                 for_each_cpu(i, &cpu_sibling_setup_map) {
-                        if (cpu_data[cpu].package == cpu_data[i].package &&
-                                    cpu_data[cpu].core == cpu_data[i].core) {
+                        if (cpus_are_siblings(cpu, i)) {
                                 cpumask_set_cpu(i, &cpu_sibling_map[cpu]);
                                 cpumask_set_cpu(cpu, &cpu_sibling_map[i]);
                         }
@@ -134,8 +133,7 @@ void calculate_cpu_foreign_map(void)
         for_each_online_cpu(i) {
                 core_present = 0;
                 for_each_cpu(k, &temp_foreign_map)
-                        if (cpu_data[i].package == cpu_data[k].package &&
-                            cpu_data[i].core == cpu_data[k].core)
+                        if (cpus_are_siblings(i, k))
                                 core_present = 1;
                 if (!core_present)
                         cpumask_set_cpu(i, &temp_foreign_map);
@@ -146,10 +144,10 @@ void calculate_cpu_foreign_map(void)
                                &temp_foreign_map, &cpu_sibling_map[i]);
 }
 
-struct plat_smp_ops *mp_ops;
+const struct plat_smp_ops *mp_ops;
 EXPORT_SYMBOL(mp_ops);
 
-void register_smp_ops(struct plat_smp_ops *ops)
+void register_smp_ops(const struct plat_smp_ops *ops)
 {
         if (mp_ops)
                 printk(KERN_WARNING "Overriding previously set SMP ops\n");
@@ -186,13 +184,13 @@ void mips_smp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
 
         if (mips_cpc_present()) {
                 for_each_cpu(cpu, mask) {
-                        core = cpu_data[cpu].core;
-
-                        if (core == current_cpu_data.core)
+                        if (cpus_are_siblings(cpu, smp_processor_id()))
                                 continue;
 
+                        core = cpu_core(&cpu_data[cpu]);
+
                         while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) {
-                                mips_cm_lock_other(core, 0);
+                                mips_cm_lock_other_cpu(cpu, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
                                 mips_cpc_lock_other(core);
                                 write_cpc_co_cmd(CPC_Cx_CMD_PWRUP);
                                 mips_cpc_unlock_other();
@@ -441,7 +439,11 @@ void smp_prepare_boot_cpu(void)
 
 int __cpu_up(unsigned int cpu, struct task_struct *tidle)
 {
-        mp_ops->boot_secondary(cpu, tidle);
+        int err;
+
+        err = mp_ops->boot_secondary(cpu, tidle);
+        if (err)
+                return err;
 
         /*
          * We must check for timeout here, as the CPU will not be marked
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index c036157fb891..a6ebc8135112 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -72,20 +72,6 @@ EXPORT_SYMBOL(perf_irq);
 unsigned int mips_hpt_frequency;
 EXPORT_SYMBOL_GPL(mips_hpt_frequency);
 
-/*
- * This function exists in order to cause an error due to a duplicate
- * definition if platform code should have its own implementation.  The hook
- * to use instead is plat_time_init.  plat_time_init does not receive the
- * irqaction pointer argument anymore.  This is because any function which
- * initializes an interrupt timer now takes care of its own request_irq rsp.
- * setup_irq calls and each clock_event_device should use its own
- * struct irqrequest.
- */
-void __init plat_timer_setup(void)
-{
-        BUG();
-}
-
 static __init int cpu_has_mfc0_count_bug(void)
 {
         switch (current_cpu_type()) {
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 2bf414993347..5669d3b8bd38 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -50,9 +50,8 @@
 #include <asm/fpu.h>
 #include <asm/fpu_emulator.h>
 #include <asm/idle.h>
-#include <asm/mips-cm.h>
+#include <asm/mips-cps.h>
 #include <asm/mips-r2-to-r6-emul.h>
-#include <asm/mips-cm.h>
 #include <asm/mipsregs.h>
 #include <asm/mipsmtregs.h>
 #include <asm/module.h>
@@ -734,8 +733,7 @@ void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
                 si.si_code = FPE_FLTUND;
         else if (fcr31 & FPU_CSR_INE_X)
                 si.si_code = FPE_FLTRES;
-        else
-                return; /* Broken hardware? */
+
         force_sig_info(SIGFPE, &si, tsk);
 }
 
@@ -1673,7 +1671,7 @@ static inline void parity_protection_init(void)
                 /* Probe L2 ECC support */
                 gcr_ectl = read_gcr_err_control();
 
-                if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT_MSK) ||
+                if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT) ||
                     !(cp0_ectl & ERRCTL_PE)) {
                         /*
                          * One of L1 or L2 ECC checking isn't supported,
@@ -1693,12 +1691,12 @@ static inline void parity_protection_init(void)
 
                 /* Configure L2 ECC checking */
                 if (l2parity)
-                        gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN_MSK;
+                        gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN;
                 else
-                        gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN_MSK;
+                        gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN;
                 write_gcr_err_control(gcr_ectl);
                 gcr_ectl = read_gcr_err_control();
-                gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN_MSK;
+                gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN;
                 WARN_ON(!!gcr_ectl != l2parity);
 
                 pr_info("Cache parity protection %sabled\n",
@@ -2428,21 +2426,6 @@ void __init trap_init(void)
         set_except_vector(EXCCODE_TR, handle_tr);
         set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe);
 
-        if (current_cpu_type() == CPU_R6000 ||
-            current_cpu_type() == CPU_R6000A) {
-                /*
-                 * The R6000 is the only R-series CPU that features a machine
-                 * check exception (similar to the R4000 cache error) and
-                 * unaligned ldc1/sdc1 exception.  The handlers have not been
-                 * written yet.  Well, anyway there is no R6000 machine on the
-                 * current list of targets for Linux/MIPS.
-                 * (Duh, crap, there is someone with a triple R6k machine)
-                 */
-                //set_except_vector(14, handle_mc);
-                //set_except_vector(15, handle_ndc);
-        }
-
-
         if (board_nmi_handler_setup)
                 board_nmi_handler_setup();
 
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 5eaf2578ac04..2d0b912f9e3e 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -1378,7 +1378,7 @@ sigill:
 const int reg16to32[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
 
 /* Recode table from 16-bit STORE register notation to 32-bit GPR. */
-const int reg16to32st[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
+static const int reg16to32st[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
 
 static void emulate_load_store_microMIPS(struct pt_regs *regs,
                                          void __user *addr)
diff --git a/arch/mips/kernel/vdso.c b/arch/mips/kernel/vdso.c
index 093517e85a6c..019035d7225c 100644
--- a/arch/mips/kernel/vdso.c
+++ b/arch/mips/kernel/vdso.c
@@ -13,13 +13,13 @@
 #include <linux/err.h>
 #include <linux/init.h>
 #include <linux/ioport.h>
-#include <linux/irqchip/mips-gic.h>
 #include <linux/mm.h>
 #include <linux/sched.h>
 #include <linux/slab.h>
 #include <linux/timekeeper_internal.h>
 
 #include <asm/abi.h>
+#include <asm/mips-cps.h>
 #include <asm/vdso.h>
 
 /* Kernel-provided data used by the VDSO. */
@@ -99,9 +99,8 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
 {
         struct mips_vdso_image *image = current->thread.abi->vdso;
         struct mm_struct *mm = current->mm;
-        unsigned long gic_size, vvar_size, size, base, data_addr, vdso_addr;
+        unsigned long gic_size, vvar_size, size, base, data_addr, vdso_addr, gic_pfn;
         struct vm_area_struct *vma;
-        struct resource gic_res;
         int ret;
 
         if (down_write_killable(&mm->mmap_sem))
@@ -125,7 +124,7 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
          * only map a page even though the total area is 64K, as we only need
          * the counter registers at the start.
          */
-        gic_size = gic_present ? PAGE_SIZE : 0;
+        gic_size = mips_gic_present() ? PAGE_SIZE : 0;
         vvar_size = gic_size + PAGE_SIZE;
         size = vvar_size + image->size;
 
@@ -148,13 +147,9 @@ int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
 
         /* Map GIC user page. */
         if (gic_size) {
-                ret = gic_get_usm_range(&gic_res);
-                if (ret)
-                        goto out;
+                gic_pfn = virt_to_phys(mips_gic_base + MIPS_GIC_USER_OFS) >> PAGE_SHIFT;
 
-                ret = io_remap_pfn_range(vma, base,
-                                         gic_res.start >> PAGE_SHIFT,
-                                         gic_size,
+                ret = io_remap_pfn_range(vma, base, gic_pfn, gic_size,
                                          pgprot_noncached(PAGE_READONLY));
                 if (ret)
                         goto out;
diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
index 177769dbb0e8..35bc69b78268 100644
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -17,6 +17,8 @@ config SOC_XWAY
         bool "XWAY"
         select SOC_TYPE_XWAY
         select HW_HAS_PCI
+        select MFD_SYSCON
+        select MFD_CORE
 
 config SOC_FALCON
         bool "FALCON"
diff --git a/arch/mips/lantiq/falcon/reset.c b/arch/mips/lantiq/falcon/reset.c
index 7a535d72f541..058b85578cf7 100644
--- a/arch/mips/lantiq/falcon/reset.c
+++ b/arch/mips/lantiq/falcon/reset.c
@@ -15,27 +15,14 @@
 
 #include <lantiq_soc.h>
 
-/* CPU0 Reset Source Register */
-#define SYS1_CPU0RS             0x0040
-/* reset cause mask */
-#define CPU0RS_MASK             0x0003
-/* CPU0 Boot Mode Register */
-#define SYS1_BM                 0x00a0
-/* boot mode mask */
-#define BM_MASK                 0x0005
-
-/* allow platform code to find out what surce we booted from */
+/*
+ * Dummy implementation.  Used to allow platform code to find out what
+ * source was booted from
+ */
 unsigned char ltq_boot_select(void)
 {
-        return ltq_sys1_r32(SYS1_BM) & BM_MASK;
-}
-
-/* allow the watchdog driver to find out what the boot reason was */
-int ltq_reset_cause(void)
-{
-        return ltq_sys1_r32(SYS1_CPU0RS) & CPU0RS_MASK;
+        return BS_SPI;
 }
-EXPORT_SYMBOL_GPL(ltq_reset_cause);
 
 #define BOOT_REG_BASE   (KSEG1 | 0x1F200000)
 #define BOOT_PW1_REG    (BOOT_REG_BASE | 0x20)
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index 33728b7af426..f0bc3312ed11 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -61,10 +61,6 @@
 /* we have a cascade of 8 irqs */
 #define MIPS_CPU_IRQ_CASCADE            8
 
-#ifdef CONFIG_MIPS_MT_SMP
-int gic_present;
-#endif
-
 static int exin_avail;
 static u32 ltq_eiu_irq[MAX_EIU];
 static void __iomem *ltq_icu_membase[MAX_IM];
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index 96773bed8a8a..9ff7ccde9de0 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -117,7 +117,7 @@ void __init prom_init(void)
 
 int __init plat_of_setup(void)
 {
-        return __dt_register_buses(soc_info.compatible, "simple-bus");
+        return of_platform_default_populate(NULL, NULL, NULL);
 }
 
 arch_initcall(plat_of_setup);
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index a2edc538f477..fbb0747c70b7 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,5 +1,3 @@
-obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
+obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o
 
 obj-y += vmmc.o
-
-obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
deleted file mode 100644
index 83fd65d76e81..000000000000
--- a/arch/mips/lantiq/xway/reset.c
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2010 John Crispin <john@phrozen.org>
- *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <linux/pm.h>
-#include <linux/export.h>
-#include <linux/delay.h>
-#include <linux/of_address.h>
-#include <linux/of_platform.h>
-#include <linux/reset-controller.h>
-
-#include <asm/reboot.h>
-
-#include <lantiq_soc.h>
-
-#include "../prom.h"
-
-/* reset request register */
-#define RCU_RST_REQ             0x0010
-/* reset status register */
-#define RCU_RST_STAT            0x0014
-/* vr9 gphy registers */
-#define RCU_GFS_ADD0_XRX200     0x0020
-#define RCU_GFS_ADD1_XRX200     0x0068
-/* xRX300 gphy registers */
-#define RCU_GFS_ADD0_XRX300     0x0020
-#define RCU_GFS_ADD1_XRX300     0x0058
-#define RCU_GFS_ADD2_XRX300     0x00AC
-/* xRX330 gphy registers */
-#define RCU_GFS_ADD0_XRX330     0x0020
-#define RCU_GFS_ADD1_XRX330     0x0058
-#define RCU_GFS_ADD2_XRX330     0x00AC
-#define RCU_GFS_ADD3_XRX330     0x0264
-
-/* xbar BE flag */
-#define RCU_AHB_ENDIAN          0x004C
-#define RCU_VR9_BE_AHB1S        0x00000008
-
-/* reboot bit */
-#define RCU_RD_GPHY0_XRX200     BIT(31)
-#define RCU_RD_SRST             BIT(30)
-#define RCU_RD_GPHY1_XRX200     BIT(29)
-/* xRX300 bits */
-#define RCU_RD_GPHY0_XRX300     BIT(31)
-#define RCU_RD_GPHY1_XRX300     BIT(29)
-#define RCU_RD_GPHY2_XRX300     BIT(28)
-/* xRX330 bits */
-#define RCU_RD_GPHY0_XRX330     BIT(31)
-#define RCU_RD_GPHY1_XRX330     BIT(29)
-#define RCU_RD_GPHY2_XRX330     BIT(28)
-#define RCU_RD_GPHY3_XRX330     BIT(10)
-
-/* reset cause */
-#define RCU_STAT_SHIFT          26
-/* boot selection */
-#define RCU_BOOT_SEL(x)         ((x >> 18) & 0x7)
-#define RCU_BOOT_SEL_XRX200(x)  (((x >> 17) & 0xf) | ((x >> 8) & 0x10))
-
-/* dwc2 USB configuration registers */
-#define RCU_USB1CFG             0x0018
-#define RCU_USB2CFG             0x0034
-
-/* USB DMA endianness bits */
-#define RCU_USBCFG_HDSEL_BIT    BIT(11)
-#define RCU_USBCFG_HOST_END_BIT BIT(10)
-#define RCU_USBCFG_SLV_END_BIT  BIT(9)
-
-/* USB reset bits */
-#define RCU_USBRESET            0x0010
-
-#define USBRESET_BIT            BIT(4)
-
-#define RCU_USBRESET2           0x0048
-
-#define USB1RESET_BIT           BIT(4)
-#define USB2RESET_BIT           BIT(5)
-
-#define RCU_CFG1A               0x0038
-#define RCU_CFG1B               0x003C
-
-/* USB PMU devices */
-#define PMU_AHBM                BIT(15)
-#define PMU_USB0                BIT(6)
-#define PMU_USB1                BIT(27)
-
-/* USB PHY PMU devices */
-#define PMU_USB0_P              BIT(0)
-#define PMU_USB1_P              BIT(26)
-
-/* remapped base addr of the reset control unit */
-static void __iomem *ltq_rcu_membase;
-static struct device_node *ltq_rcu_np;
-static DEFINE_SPINLOCK(ltq_rcu_lock);
-
-static void ltq_rcu_w32(uint32_t val, uint32_t reg_off)
-{
-        ltq_w32(val, ltq_rcu_membase + reg_off);
-}
-
-static uint32_t ltq_rcu_r32(uint32_t reg_off)
-{
-        return ltq_r32(ltq_rcu_membase + reg_off);
-}
-
-static void ltq_rcu_w32_mask(uint32_t clr, uint32_t set, uint32_t reg_off)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&ltq_rcu_lock, flags);
-        ltq_rcu_w32((ltq_rcu_r32(reg_off) & ~(clr)) | (set), reg_off);
-        spin_unlock_irqrestore(&ltq_rcu_lock, flags);
-}
-
-/* This function is used by the watchdog driver */
-int ltq_reset_cause(void)
-{
-        u32 val = ltq_rcu_r32(RCU_RST_STAT);
-        return val >> RCU_STAT_SHIFT;
-}
-EXPORT_SYMBOL_GPL(ltq_reset_cause);
-
-/* allow platform code to find out what source we booted from */
-unsigned char ltq_boot_select(void)
-{
-        u32 val = ltq_rcu_r32(RCU_RST_STAT);
-
-        if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
-                return RCU_BOOT_SEL_XRX200(val);
-
-        return RCU_BOOT_SEL(val);
-}
-
-struct ltq_gphy_reset {
-        u32 rd;
-        u32 addr;
-};
-
-/* reset / boot a gphy */
-static struct ltq_gphy_reset xrx200_gphy[] = {
-        {RCU_RD_GPHY0_XRX200, RCU_GFS_ADD0_XRX200},
-        {RCU_RD_GPHY1_XRX200, RCU_GFS_ADD1_XRX200},
-};
-
-/* reset / boot a gphy */
-static struct ltq_gphy_reset xrx300_gphy[] = {
-        {RCU_RD_GPHY0_XRX300, RCU_GFS_ADD0_XRX300},
-        {RCU_RD_GPHY1_XRX300, RCU_GFS_ADD1_XRX300},
-        {RCU_RD_GPHY2_XRX300, RCU_GFS_ADD2_XRX300},
-};
-
-/* reset / boot a gphy */
-static struct ltq_gphy_reset xrx330_gphy[] = {
-        {RCU_RD_GPHY0_XRX330, RCU_GFS_ADD0_XRX330},
-        {RCU_RD_GPHY1_XRX330, RCU_GFS_ADD1_XRX330},
-        {RCU_RD_GPHY2_XRX330, RCU_GFS_ADD2_XRX330},
-        {RCU_RD_GPHY3_XRX330, RCU_GFS_ADD3_XRX330},
-};
-
-static void xrx200_gphy_boot_addr(struct ltq_gphy_reset *phy_regs,
-                                  dma_addr_t dev_addr)
-{
-        ltq_rcu_w32_mask(0, phy_regs->rd, RCU_RST_REQ);
-        ltq_rcu_w32(dev_addr, phy_regs->addr);
-        ltq_rcu_w32_mask(phy_regs->rd, 0,  RCU_RST_REQ);
-}
-
-/* reset and boot a gphy. these phys only exist on xrx200 SoC */
-int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
-{
-        struct clk *clk;
-
-        if (!of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200")) {
-                dev_err(dev, "this SoC has no GPHY\n");
-                return -EINVAL;
-        }
-
-        if (of_machine_is_compatible("lantiq,vr9")) {
-                clk = clk_get_sys("1f203000.rcu", "gphy");
-                if (IS_ERR(clk))
-                        return PTR_ERR(clk);
-                clk_enable(clk);
-        }
-
-        dev_info(dev, "booting GPHY%u firmware at %X\n", id, dev_addr);
-
-        if (of_machine_is_compatible("lantiq,vr9")) {
-                if (id >= ARRAY_SIZE(xrx200_gphy)) {
-                        dev_err(dev, "%u is an invalid gphy id\n", id);
-                        return -EINVAL;
-                }
-                xrx200_gphy_boot_addr(&xrx200_gphy[id], dev_addr);
-        } else if (of_machine_is_compatible("lantiq,ar10")) {
-                if (id >= ARRAY_SIZE(xrx300_gphy)) {
-                        dev_err(dev, "%u is an invalid gphy id\n", id);
-                        return -EINVAL;
-                }
-                xrx200_gphy_boot_addr(&xrx300_gphy[id], dev_addr);
-        } else if (of_machine_is_compatible("lantiq,grx390")) {
-                if (id >= ARRAY_SIZE(xrx330_gphy)) {
-                        dev_err(dev, "%u is an invalid gphy id\n", id);
-                        return -EINVAL;
-                }
-                xrx200_gphy_boot_addr(&xrx330_gphy[id], dev_addr);
-        }
-        return 0;
-}
-
-/* reset a io domain for u micro seconds */
-void ltq_reset_once(unsigned int module, ulong u)
-{
-        ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
-        udelay(u);
-        ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
-}
-
-static int ltq_assert_device(struct reset_controller_dev *rcdev,
-                                unsigned long id)
-{
-        u32 val;
-
-        if (id < 8)
-                return -1;
-
-        val = ltq_rcu_r32(RCU_RST_REQ);
-        val |= BIT(id);
-        ltq_rcu_w32(val, RCU_RST_REQ);
-
-        return 0;
-}
-
-static int ltq_deassert_device(struct reset_controller_dev *rcdev,
-                                  unsigned long id)
-{
-        u32 val;
-
-        if (id < 8)
-                return -1;
-
-        val = ltq_rcu_r32(RCU_RST_REQ);
-        val &= ~BIT(id);
-        ltq_rcu_w32(val, RCU_RST_REQ);
-
-        return 0;
-}
-
-static int ltq_reset_device(struct reset_controller_dev *rcdev,
-                               unsigned long id)
-{
-        ltq_assert_device(rcdev, id);
-        return ltq_deassert_device(rcdev, id);
-}
-
-static const struct reset_control_ops reset_ops = {
-        .reset = ltq_reset_device,
-        .assert = ltq_assert_device,
-        .deassert = ltq_deassert_device,
-};
-
-static struct reset_controller_dev reset_dev = {
-        .ops                    = &reset_ops,
-        .owner                  = THIS_MODULE,
-        .nr_resets              = 32,
-        .of_reset_n_cells       = 1,
-};
-
-void ltq_rst_init(void)
-{
-        reset_dev.of_node = of_find_compatible_node(NULL, NULL,
-                                                "lantiq,xway-reset");
-        if (!reset_dev.of_node)
-                pr_err("Failed to find reset controller node");
-        else
-                reset_controller_register(&reset_dev);
-}
-
-static void ltq_machine_restart(char *command)
-{
-        u32 val = ltq_rcu_r32(RCU_RST_REQ);
-
-        if (of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200"))
-                val |= RCU_RD_GPHY1_XRX200 | RCU_RD_GPHY0_XRX200;
-
-        val |= RCU_RD_SRST;
-
-        local_irq_disable();
-        ltq_rcu_w32(val, RCU_RST_REQ);
-        unreachable();
-}
-
-static void ltq_machine_halt(void)
-{
-        local_irq_disable();
-        unreachable();
-}
-
-static void ltq_machine_power_off(void)
-{
-        local_irq_disable();
-        unreachable();
-}
-
-static void ltq_usb_init(void)
-{
-        /* Power for USB cores 1 & 2 */
-        ltq_pmu_enable(PMU_AHBM);
-        ltq_pmu_enable(PMU_USB0);
-        ltq_pmu_enable(PMU_USB1);
-
-        ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A);
-        ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B);
-
-        /* Enable USB PHY power for cores 1 & 2 */
-        ltq_pmu_enable(PMU_USB0_P);
-        ltq_pmu_enable(PMU_USB1_P);
-
-        /* Configure cores to host mode */
-        ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
-                RCU_USB1CFG);
-        ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
-                RCU_USB2CFG);
-
-        /* Select DMA endianness (Host-endian: big-endian) */
-        ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
-                | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
-        ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
-                | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
-
-        /* Hard reset USB state machines */
-        ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
-        udelay(50 * 1000);
-        ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
-
-        /* Soft reset USB state machines */
-        ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
-                | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
-        udelay(50 * 1000);
-        ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
-                & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
-}
-
-static int __init mips_reboot_setup(void)
-{
-        struct resource res;
-
-        ltq_rcu_np = of_find_compatible_node(NULL, NULL, "lantiq,rcu-xway");
-        if (!ltq_rcu_np)
-                ltq_rcu_np = of_find_compatible_node(NULL, NULL,
-                                                        "lantiq,rcu-xrx200");
-
-        /* check if all the reset register range is available */
-        if (!ltq_rcu_np)
-                panic("Failed to load reset resources from devicetree");
-
-        if (of_address_to_resource(ltq_rcu_np, 0, &res))
-                panic("Failed to get rcu memory range");
-
-        if (!request_mem_region(res.start, resource_size(&res), res.name))
-                pr_err("Failed to request rcu memory");
-
-        ltq_rcu_membase = ioremap_nocache(res.start, resource_size(&res));
-        if (!ltq_rcu_membase)
-                panic("Failed to remap core memory");
-
-        if (of_machine_is_compatible("lantiq,ar9") ||
-            of_machine_is_compatible("lantiq,vr9"))
-                ltq_usb_init();
-
-        if (of_machine_is_compatible("lantiq,vr9"))
-                ltq_rcu_w32(ltq_rcu_r32(RCU_AHB_ENDIAN) | RCU_VR9_BE_AHB1S,
-                            RCU_AHB_ENDIAN);
-
-        _machine_restart = ltq_machine_restart;
-        _machine_halt = ltq_machine_halt;
-        pm_power_off = ltq_machine_power_off;
-
-        return 0;
-}
-
-arch_initcall(mips_reboot_setup);
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 95bec460b651..7611c3013793 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -145,15 +145,7 @@ static u32 pmu_clk_cr_b[] = {
 #define pmu_w32(x, y)   ltq_w32((x), pmu_membase + (y))
 #define pmu_r32(x)      ltq_r32(pmu_membase + (x))
 
-#define XBAR_ALWAYS_LAST        0x430
-#define XBAR_FPI_BURST_EN       BIT(1)
-#define XBAR_AHB_BURST_EN       BIT(2)
-
-#define xbar_w32(x, y)  ltq_w32((x), ltq_xbar_membase + (y))
-#define xbar_r32(x)     ltq_r32(ltq_xbar_membase + (x))
-
 static void __iomem *pmu_membase;
-static void __iomem *ltq_xbar_membase;
 void __iomem *ltq_cgu_membase;
 void __iomem *ltq_ebu_membase;
 
@@ -293,16 +285,6 @@ static void pci_ext_disable(struct clk *clk)
         ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
 }
 
-static void xbar_fpi_burst_disable(void)
-{
-        u32 reg;
-
-        /* bit 1 as 1 --burst; bit 1 as 0 -- single */
-        reg = xbar_r32(XBAR_ALWAYS_LAST);
-        reg &= ~XBAR_FPI_BURST_EN;
-        xbar_w32(reg, XBAR_ALWAYS_LAST);
-}
-
 /* enable a clockout source */
 static int clkout_enable(struct clk *clk)
 {
@@ -459,26 +441,6 @@ void __init ltq_soc_init(void)
         if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
                 panic("Failed to remap core resources");
 
-        if (of_machine_is_compatible("lantiq,vr9")) {
-                struct resource res_xbar;
-                struct device_node *np_xbar =
-                                of_find_compatible_node(NULL, NULL,
-                                                        "lantiq,xbar-xway");
-
-                if (!np_xbar)
-                        panic("Failed to load xbar nodes from devicetree");
-                if (of_address_to_resource(np_xbar, 0, &res_xbar))
-                        panic("Failed to get xbar resources");
-                if (!request_mem_region(res_xbar.start, resource_size(&res_xbar),
-                        res_xbar.name))
-                        panic("Failed to get xbar resources");
-
-                ltq_xbar_membase = ioremap_nocache(res_xbar.start,
-                                                   resource_size(&res_xbar));
-                if (!ltq_xbar_membase)
-                        panic("Failed to remap xbar resources");
-        }
-
         /* make sure to unprotect the memory region where flash is located */
         ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
 
@@ -507,8 +469,8 @@ void __init ltq_soc_init(void)
 
         if (of_machine_is_compatible("lantiq,grx390") ||
             of_machine_is_compatible("lantiq,ar10")) {
-                clkdev_add_pmu("1e101000.usb", "phy", 1, 2, PMU_ANALOG_USB0_P);
-                clkdev_add_pmu("1e106000.usb", "phy", 1, 2, PMU_ANALOG_USB1_P);
+                clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB0_P);
+                clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB1_P);
                 /* rc 0 */
                 clkdev_add_pmu("1d900000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
                 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
@@ -528,8 +490,8 @@ void __init ltq_soc_init(void)
                 else
                         clkdev_add_static(CLOCK_133M, CLOCK_133M,
                                                 CLOCK_133M, CLOCK_133M);
-                clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
-                clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
+                clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
+                clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
                 clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
                 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
                 clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
@@ -538,8 +500,8 @@ void __init ltq_soc_init(void)
         } else if (of_machine_is_compatible("lantiq,grx390")) {
                 clkdev_add_static(ltq_grx390_cpu_hz(), ltq_grx390_fpi_hz(),
                                   ltq_grx390_fpi_hz(), ltq_grx390_pp32_hz());
-                clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
-                clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
+                clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
+                clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
                 /* rc 2 */
                 clkdev_add_pmu("1a800000.pcie", "phy", 1, 2, PMU_ANALOG_PCIE2_P);
                 clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);
@@ -551,22 +513,23 @@ void __init ltq_soc_init(void)
         } else if (of_machine_is_compatible("lantiq,ar10")) {
                 clkdev_add_static(ltq_ar10_cpu_hz(), ltq_ar10_fpi_hz(),
                                   ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());
-                clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
-                clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
+                clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
+                clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
                 clkdev_add_pmu("1e108000.eth", NULL, 0, 0, PMU_SWITCH |
                                PMU_PPE_DP | PMU_PPE_TC);
                 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
-                clkdev_add_pmu("1f203000.rcu", "gphy", 1, 0, PMU_GPHY);
+                clkdev_add_pmu("1f203020.gphy", NULL, 1, 0, PMU_GPHY);
+                clkdev_add_pmu("1f203068.gphy", NULL, 1, 0, PMU_GPHY);
                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
                 clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);
                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
         } else if (of_machine_is_compatible("lantiq,vr9")) {
                 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
                                 ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
-                clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
-                clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0 | PMU_AHBM);
-                clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
-                clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1 | PMU_AHBM);
+                clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
+                clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
+                clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
+                clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM);
                 clkdev_add_pmu("1d900000.pcie", "phy", 1, 1, PMU1_PCIE_PHY);
                 clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
                 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
@@ -579,17 +542,18 @@ void __init ltq_soc_init(void)
                                 PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
                                 PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
                                 PMU_PPE_QSB | PMU_PPE_TOP);
-                clkdev_add_pmu("1f203000.rcu", "gphy", 0, 0, PMU_GPHY);
+                clkdev_add_pmu("1f203020.gphy", NULL, 0, 0, PMU_GPHY);
+                clkdev_add_pmu("1f203068.gphy", NULL, 0, 0, PMU_GPHY);
                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
         } else if (of_machine_is_compatible("lantiq,ar9")) {
                 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
                                 ltq_ar9_fpi_hz(), CLOCK_250M);
-                clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
-                clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
-                clkdev_add_pmu("1e106000.usb", "ctl", 1, 0, PMU_USB1);
-                clkdev_add_pmu("1e106000.usb", "phy", 1, 0, PMU_USB1_P);
+                clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
+                clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
+                clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
+                clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
                 clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
@@ -598,14 +562,11 @@ void __init ltq_soc_init(void)
         } else {
                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
                                 ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
-                clkdev_add_pmu("1e101000.usb", "ctl", 1, 0, PMU_USB0);
-                clkdev_add_pmu("1e101000.usb", "phy", 1, 0, PMU_USB0_P);
+                clkdev_add_pmu("1f203018.usb2-phy", "ctrl", 1, 0, PMU_USB0);
+                clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
                 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
                 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
                 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
                 clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
         }
-
-        if (of_machine_is_compatible("lantiq,vr9"))
-                xbar_fpi_burst_disable();
 }
diff --git a/arch/mips/lantiq/xway/xrx200_phy_fw.c b/arch/mips/lantiq/xway/xrx200_phy_fw.c
deleted file mode 100644
index f0a0f2d431b2..000000000000
--- a/arch/mips/lantiq/xway/xrx200_phy_fw.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Lantiq XRX200 PHY Firmware Loader
- * Author: John Crispin
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License version 2 as published
- *  by the Free Software Foundation.
- *
- *  Copyright (C) 2012 John Crispin <john@phrozen.org>
- */
-
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/firmware.h>
-#include <linux/of_platform.h>
-
-#include <lantiq_soc.h>
-
-#define XRX200_GPHY_FW_ALIGN    (16 * 1024)
-
-static dma_addr_t xway_gphy_load(struct platform_device *pdev)
-{
-        const struct firmware *fw;
-        dma_addr_t dev_addr = 0;
-        const char *fw_name;
-        void *fw_addr;
-        size_t size;
-
-        if (of_get_property(pdev->dev.of_node, "firmware1", NULL) ||
-                of_get_property(pdev->dev.of_node, "firmware2", NULL)) {
-                switch (ltq_soc_type()) {
-                case SOC_TYPE_VR9:
-                        if (of_property_read_string(pdev->dev.of_node,
-                                                    "firmware1", &fw_name)) {
-                                dev_err(&pdev->dev,
-                                        "failed to load firmware filename\n");
-                                return 0;
-                        }
-                        break;
-                case SOC_TYPE_VR9_2:
-                        if (of_property_read_string(pdev->dev.of_node,
-                                                    "firmware2", &fw_name)) {
-                                dev_err(&pdev->dev,
-                                        "failed to load firmware filename\n");
-                                return 0;
-                        }
-                        break;
-                }
-        } else if (of_property_read_string(pdev->dev.of_node,
-                                         "firmware", &fw_name)) {
-                dev_err(&pdev->dev, "failed to load firmware filename\n");
-                return 0;
-        }
-
-        dev_info(&pdev->dev, "requesting %s\n", fw_name);
-        if (request_firmware(&fw, fw_name, &pdev->dev)) {
-                dev_err(&pdev->dev, "failed to load firmware: %s\n", fw_name);
-                return 0;
-        }
-
-        /*
-         * GPHY cores need the firmware code in a persistent and contiguous
-         * memory area with a 16 kB boundary aligned start address
-         */
-        size = fw->size + XRX200_GPHY_FW_ALIGN;
-
-        fw_addr = dma_alloc_coherent(&pdev->dev, size, &dev_addr, GFP_KERNEL);
-        if (fw_addr) {
-                fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
-                dev_addr = ALIGN(dev_addr, XRX200_GPHY_FW_ALIGN);
-                memcpy(fw_addr, fw->data, fw->size);
-        } else {
-                dev_err(&pdev->dev, "failed to alloc firmware memory\n");
-        }
-
-        release_firmware(fw);
-        return dev_addr;
-}
-
-static int xway_phy_fw_probe(struct platform_device *pdev)
-{
-        dma_addr_t fw_addr;
-        struct property *pp;
-        unsigned char *phyids;
-        int i, ret = 0;
-
-        fw_addr = xway_gphy_load(pdev);
-        if (!fw_addr)
-                return -EINVAL;
-        pp = of_find_property(pdev->dev.of_node, "phys", NULL);
-        if (!pp)
-                return -ENOENT;
-        phyids = pp->value;
-        for (i = 0; i < pp->length && !ret; i++)
-                ret = xrx200_gphy_boot(&pdev->dev, phyids[i], fw_addr);
-        if (!ret)
-                mdelay(100);
-        return ret;
-}
-
-static const struct of_device_id xway_phy_match[] = {
-        { .compatible = "lantiq,phy-xrx200" },
-        {},
-};
-
-static struct platform_driver xway_phy_driver = {
-        .probe = xway_phy_fw_probe,
-        .driver = {
-                .name = "phy-xrx200",
-                .of_match_table = xway_phy_match,
-        },
-};
-builtin_platform_driver(xway_phy_driver);
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index a37fe3d1ee2f..6ab430d24575 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -6,7 +6,7 @@ lib-y	+= bitops.o csum_partial.o delay.o memcpy.o memset.o \
            mips-atomic.o strncpy_user.o \
            strnlen_user.o uncached.o
 
-obj-y                   += iomap.o
+obj-y                   += iomap.o iomap_copy.o
 obj-$(CONFIG_PCI)       += iomap-pci.o
 lib-$(CONFIG_GENERIC_CSUM)      := $(filter-out csum_partial.o, $(lib-y))
 
diff --git a/arch/mips/lib/delay.c b/arch/mips/lib/delay.c
index 2307a3cb2714..68c495ed71e3 100644
--- a/arch/mips/lib/delay.c
+++ b/arch/mips/lib/delay.c
@@ -8,6 +8,7 @@
  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  * Copyright (C) 2007, 2014 Maciej W. Rozycki
  */
+#include <linux/delay.h>
 #include <linux/export.h>
 #include <linux/param.h>
 #include <linux/smp.h>
diff --git a/arch/mips/lib/iomap_copy.c b/arch/mips/lib/iomap_copy.c
new file mode 100644
index 000000000000..368bb38267c5
--- /dev/null
+++ b/arch/mips/lib/iomap_copy.c
@@ -0,0 +1,42 @@
+/*
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#include <linux/export.h>
+#include <linux/io.h>
+
+/**
+ * __ioread64_copy - copy data from MMIO space, in 64-bit units
+ * @to: destination (must be 64-bit aligned)
+ * @from: source, in MMIO space (must be 64-bit aligned)
+ * @count: number of 64-bit quantities to copy
+ *
+ * Copy data from MMIO space to kernel space, in units of 32 or 64 bits at a
+ * time.  Order of access is not guaranteed, nor is a memory barrier
+ * performed afterwards.
+ */
+void __ioread64_copy(void *to, const void __iomem *from, size_t count)
+{
+#ifdef CONFIG_64BIT
+        u64 *dst = to;
+        const u64 __iomem *src = from;
+        const u64 __iomem *end = src + count;
+
+        while (src < end)
+                *dst++ = __raw_readq(src++);
+#else
+        __ioread32_copy(to, from, count * 2);
+#endif
+}
+EXPORT_SYMBOL_GPL(__ioread64_copy);
diff --git a/arch/mips/loongson64/lemote-2f/clock.c b/arch/mips/loongson64/lemote-2f/clock.c
index a78fb657068c..8281334df9c8 100644
--- a/arch/mips/loongson64/lemote-2f/clock.c
+++ b/arch/mips/loongson64/lemote-2f/clock.c
@@ -80,6 +80,9 @@ EXPORT_SYMBOL(clk_disable);
 
 unsigned long clk_get_rate(struct clk *clk)
 {
+        if (!clk)
+                return 0;
+
         return (unsigned long)clk->rate;
 }
 EXPORT_SYMBOL(clk_get_rate);
diff --git a/arch/mips/loongson64/loongson-3/smp.c b/arch/mips/loongson64/loongson-3/smp.c
index b7a355c3c408..8501109bb0f0 100644
--- a/arch/mips/loongson64/loongson-3/smp.c
+++ b/arch/mips/loongson64/loongson-3/smp.c
@@ -319,8 +319,8 @@ static void loongson3_init_secondary(void)
                 loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(i)]);
 
         per_cpu(cpu_state, cpu) = CPU_ONLINE;
-        cpu_data[cpu].core =
-                cpu_logical_map(cpu) % loongson_sysconf.cores_per_package;
+        cpu_set_core(&cpu_data[cpu],
+                     cpu_logical_map(cpu) % loongson_sysconf.cores_per_package);
         cpu_data[cpu].package =
                 cpu_logical_map(cpu) / loongson_sysconf.cores_per_package;
 
@@ -386,7 +386,8 @@ static void __init loongson3_smp_setup(void)
         ipi_status0_regs_init();
         ipi_en0_regs_init();
         ipi_mailbox_buf_init();
-        cpu_data[0].core = cpu_logical_map(0) % loongson_sysconf.cores_per_package;
+        cpu_set_core(&cpu_data[0],
+                     cpu_logical_map(0) % loongson_sysconf.cores_per_package);
         cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package;
 }
 
@@ -399,7 +400,7 @@ static void __init loongson3_prepare_cpus(unsigned int max_cpus)
 /*
  * Setup the PC, SP, and GP of a secondary processor and start it runing!
  */
-static void loongson3_boot_secondary(int cpu, struct task_struct *idle)
+static int loongson3_boot_secondary(int cpu, struct task_struct *idle)
 {
         unsigned long startargs[4];
 
@@ -422,6 +423,7 @@ static void loongson3_boot_secondary(int cpu, struct task_struct *idle)
                         (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x8));
         loongson3_ipi_write64(startargs[0],
                         (void *)(ipi_mailbox_buf[cpu_logical_map(cpu)]+0x0));
+        return 0;
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
@@ -697,7 +699,7 @@ void play_dead(void)
 
 static int loongson3_disable_clock(unsigned int cpu)
 {
-        uint64_t core_id = cpu_data[cpu].core;
+        uint64_t core_id = cpu_core(&cpu_data[cpu]);
         uint64_t package_id = cpu_data[cpu].package;
 
         if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) {
@@ -711,7 +713,7 @@ static int loongson3_disable_clock(unsigned int cpu)
 
 static int loongson3_enable_clock(unsigned int cpu)
 {
-        uint64_t core_id = cpu_data[cpu].core;
+        uint64_t core_id = cpu_core(&cpu_data[cpu]);
         uint64_t package_id = cpu_data[cpu].package;
 
         if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) {
@@ -734,7 +736,7 @@ early_initcall(register_loongson3_notifier);
 
 #endif
 
-struct plat_smp_ops loongson3_smp_ops = {
+const struct plat_smp_ops loongson3_smp_ops = {
         .send_ipi_single = loongson3_send_ipi_single,
         .send_ipi_mask = loongson3_send_ipi_mask,
         .init_secondary = loongson3_init_secondary,
diff --git a/arch/mips/math-emu/Makefile b/arch/mips/math-emu/Makefile
index e9bbc2a6526f..e9f10b88b695 100644
--- a/arch/mips/math-emu/Makefile
+++ b/arch/mips/math-emu/Makefile
@@ -4,9 +4,11 @@
 
 obj-y   += cp1emu.o ieee754dp.o ieee754sp.o ieee754.o \
            dp_div.o dp_mul.o dp_sub.o dp_add.o dp_fsp.o dp_cmp.o dp_simple.o \
-           dp_tint.o dp_fint.o dp_maddf.o dp_2008class.o dp_fmin.o dp_fmax.o \
+           dp_tint.o dp_fint.o dp_rint.o dp_maddf.o dp_2008class.o dp_fmin.o \
+           dp_fmax.o                                                         \
            sp_div.o sp_mul.o sp_sub.o sp_add.o sp_fdp.o sp_cmp.o sp_simple.o \
-           sp_tint.o sp_fint.o sp_maddf.o sp_2008class.o sp_fmin.o sp_fmax.o \
+           sp_tint.o sp_fint.o sp_rint.o sp_maddf.o sp_2008class.o sp_fmin.o \
+           sp_fmax.o                                                         \
            dsemul.o
 
 lib-y   += ieee754d.o \
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index f08a7b4facb9..192542dbd972 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -58,7 +58,7 @@ static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
         mips_instruction);
 
 static int fpux_emu(struct pt_regs *,
-        struct mips_fpu_struct *, mips_instruction, void *__user *);
+        struct mips_fpu_struct *, mips_instruction, void __user **);
 
 /* Control registers */
 
@@ -830,12 +830,12 @@ do {									\
 } while (0)
 
 #define DIFROMREG(di, x)                                                \
-        ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) == 0)], 0))
+        ((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) ^ 1)], 0))
 
 #define DITOREG(di, x)                                                  \
 do {                                                                    \
         unsigned fpr, i;                                                \
-        fpr = (x) & ~(cop1_64bit(xcp) == 0);                            \
+        fpr = (x) & ~(cop1_64bit(xcp) ^ 1);                             \
         set_fpr64(&ctx->fpr[fpr], 0, di);                               \
         for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++)             \
                 set_fpr64(&ctx->fpr[fpr], i, 0);                        \
@@ -973,7 +973,7 @@ static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
  */
 
 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
-                struct mm_decoded_insn dec_insn, void *__user *fault_addr)
+                struct mm_decoded_insn dec_insn, void __user **fault_addr)
 {
         unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
         unsigned int cond, cbit, bit0;
@@ -1195,9 +1195,11 @@ emul:
                         bit0 = get_fpr32(fpr, 0) & 0x1;
                         switch (MIPSInst_RS(ir)) {
                         case bc1eqz_op:
+                                MIPS_FPU_EMU_INC_STATS(bc1eqz);
                                 cond = bit0 == 0;
                                 break;
                         case bc1nez_op:
+                                MIPS_FPU_EMU_INC_STATS(bc1nez);
                                 cond = bit0 != 0;
                                 break;
                         }
@@ -1230,6 +1232,7 @@ emul:
                                 break;
                         }
 branch_common:
+                        MIPS_FPU_EMU_INC_STATS(branches);
                         set_delay_slot(xcp);
                         if (cond) {
                                 /*
@@ -1460,7 +1463,7 @@ DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
 
 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
-        mips_instruction ir, void *__user *fault_addr)
+        mips_instruction ir, void __user **fault_addr)
 {
         unsigned rcsr = 0;      /* resulting csr */
 
@@ -1682,15 +1685,19 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                 switch (MIPSInst_FUNC(ir)) {
                         /* binary ops */
                 case fadd_op:
+                        MIPS_FPU_EMU_INC_STATS(add_s);
                         handler.b = ieee754sp_add;
                         goto scopbop;
                 case fsub_op:
+                        MIPS_FPU_EMU_INC_STATS(sub_s);
                         handler.b = ieee754sp_sub;
                         goto scopbop;
                 case fmul_op:
+                        MIPS_FPU_EMU_INC_STATS(mul_s);
                         handler.b = ieee754sp_mul;
                         goto scopbop;
                 case fdiv_op:
+                        MIPS_FPU_EMU_INC_STATS(div_s);
                         handler.b = ieee754sp_div;
                         goto scopbop;
 
@@ -1699,6 +1706,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         if (!cpu_has_mips_2_3_4_5_r)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(sqrt_s);
                         handler.u = ieee754sp_sqrt;
                         goto scopuop;
 
@@ -1711,6 +1719,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         if (!cpu_has_mips_4_5_64_r2_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(rsqrt_s);
                         handler.u = fpemu_sp_rsqrt;
                         goto scopuop;
 
@@ -1718,6 +1727,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         if (!cpu_has_mips_4_5_64_r2_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(recip_s);
                         handler.u = fpemu_sp_recip;
                         goto scopuop;
 
@@ -1754,6 +1764,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(seleqz_s);
                         SPFROMREG(rv.s, MIPSInst_FT(ir));
                         if (rv.w & 0x1)
                                 rv.w = 0;
@@ -1765,6 +1776,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(selnez_s);
                         SPFROMREG(rv.s, MIPSInst_FT(ir));
                         if (rv.w & 0x1)
                                 SPFROMREG(rv.s, MIPSInst_FS(ir));
@@ -1778,6 +1790,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(maddf_s);
                         SPFROMREG(ft, MIPSInst_FT(ir));
                         SPFROMREG(fs, MIPSInst_FS(ir));
                         SPFROMREG(fd, MIPSInst_FD(ir));
@@ -1791,6 +1804,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(msubf_s);
                         SPFROMREG(ft, MIPSInst_FT(ir));
                         SPFROMREG(fs, MIPSInst_FS(ir));
                         SPFROMREG(fd, MIPSInst_FD(ir));
@@ -1804,9 +1818,9 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(rint_s);
                         SPFROMREG(fs, MIPSInst_FS(ir));
-                        rv.l = ieee754sp_tlong(fs);
-                        rv.s = ieee754sp_flong(rv.l);
+                        rv.s = ieee754sp_rint(fs);
                         goto copcsr;
                 }
 
@@ -1816,6 +1830,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(class_s);
                         SPFROMREG(fs, MIPSInst_FS(ir));
                         rv.w = ieee754sp_2008class(fs);
                         rfmt = w_fmt;
@@ -1828,6 +1843,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(min_s);
                         SPFROMREG(ft, MIPSInst_FT(ir));
                         SPFROMREG(fs, MIPSInst_FS(ir));
                         rv.s = ieee754sp_fmin(fs, ft);
@@ -1840,6 +1856,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(mina_s);
                         SPFROMREG(ft, MIPSInst_FT(ir));
                         SPFROMREG(fs, MIPSInst_FS(ir));
                         rv.s = ieee754sp_fmina(fs, ft);
@@ -1852,6 +1869,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(max_s);
                         SPFROMREG(ft, MIPSInst_FT(ir));
                         SPFROMREG(fs, MIPSInst_FS(ir));
                         rv.s = ieee754sp_fmax(fs, ft);
@@ -1864,6 +1882,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(maxa_s);
                         SPFROMREG(ft, MIPSInst_FT(ir));
                         SPFROMREG(fs, MIPSInst_FS(ir));
                         rv.s = ieee754sp_fmaxa(fs, ft);
@@ -1871,15 +1890,18 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                 }
 
                 case fabs_op:
+                        MIPS_FPU_EMU_INC_STATS(abs_s);
                         handler.u = ieee754sp_abs;
                         goto scopuop;
 
                 case fneg_op:
+                        MIPS_FPU_EMU_INC_STATS(neg_s);
                         handler.u = ieee754sp_neg;
                         goto scopuop;
 
                 case fmov_op:
                         /* an easy one */
+                        MIPS_FPU_EMU_INC_STATS(mov_s);
                         SPFROMREG(rv.s, MIPSInst_FS(ir));
                         goto copcsr;
 
@@ -1922,12 +1944,14 @@ copcsr:
                         return SIGILL;  /* not defined */
 
                 case fcvtd_op:
+                        MIPS_FPU_EMU_INC_STATS(cvt_d_s);
                         SPFROMREG(fs, MIPSInst_FS(ir));
                         rv.d = ieee754dp_fsp(fs);
                         rfmt = d_fmt;
                         goto copcsr;
 
                 case fcvtw_op:
+                        MIPS_FPU_EMU_INC_STATS(cvt_w_s);
                         SPFROMREG(fs, MIPSInst_FS(ir));
                         rv.w = ieee754sp_tint(fs);
                         rfmt = w_fmt;
@@ -1940,6 +1964,15 @@ copcsr:
                         if (!cpu_has_mips_2_3_4_5_r)
                                 return SIGILL;
 
+                        if (MIPSInst_FUNC(ir) == fceil_op)
+                                MIPS_FPU_EMU_INC_STATS(ceil_w_s);
+                        if (MIPSInst_FUNC(ir) == ffloor_op)
+                                MIPS_FPU_EMU_INC_STATS(floor_w_s);
+                        if (MIPSInst_FUNC(ir) == fround_op)
+                                MIPS_FPU_EMU_INC_STATS(round_w_s);
+                        if (MIPSInst_FUNC(ir) == ftrunc_op)
+                                MIPS_FPU_EMU_INC_STATS(trunc_w_s);
+
                         oldrm = ieee754_csr.rm;
                         SPFROMREG(fs, MIPSInst_FS(ir));
                         ieee754_csr.rm = MIPSInst_FUNC(ir);
@@ -1952,6 +1985,7 @@ copcsr:
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(sel_s);
                         SPFROMREG(fd, MIPSInst_FD(ir));
                         if (fd.bits & 0x1)
                                 SPFROMREG(rv.s, MIPSInst_FT(ir));
@@ -1963,6 +1997,7 @@ copcsr:
                         if (!cpu_has_mips_3_4_5_64_r2_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(cvt_l_s);
                         SPFROMREG(fs, MIPSInst_FS(ir));
                         rv.l = ieee754sp_tlong(fs);
                         rfmt = l_fmt;
@@ -1975,6 +2010,15 @@ copcsr:
                         if (!cpu_has_mips_3_4_5_64_r2_r6)
                                 return SIGILL;
 
+                        if (MIPSInst_FUNC(ir) == fceill_op)
+                                MIPS_FPU_EMU_INC_STATS(ceil_l_s);
+                        if (MIPSInst_FUNC(ir) == ffloorl_op)
+                                MIPS_FPU_EMU_INC_STATS(floor_l_s);
+                        if (MIPSInst_FUNC(ir) == froundl_op)
+                                MIPS_FPU_EMU_INC_STATS(round_l_s);
+                        if (MIPSInst_FUNC(ir) == ftruncl_op)
+                                MIPS_FPU_EMU_INC_STATS(trunc_l_s);
+
                         oldrm = ieee754_csr.rm;
                         SPFROMREG(fs, MIPSInst_FS(ir));
                         ieee754_csr.rm = MIPSInst_FUNC(ir);
@@ -2016,15 +2060,19 @@ copcsr:
                 switch (MIPSInst_FUNC(ir)) {
                         /* binary ops */
                 case fadd_op:
+                        MIPS_FPU_EMU_INC_STATS(add_d);
                         handler.b = ieee754dp_add;
                         goto dcopbop;
                 case fsub_op:
+                        MIPS_FPU_EMU_INC_STATS(sub_d);
                         handler.b = ieee754dp_sub;
                         goto dcopbop;
                 case fmul_op:
+                        MIPS_FPU_EMU_INC_STATS(mul_d);
                         handler.b = ieee754dp_mul;
                         goto dcopbop;
                 case fdiv_op:
+                        MIPS_FPU_EMU_INC_STATS(div_d);
                         handler.b = ieee754dp_div;
                         goto dcopbop;
 
@@ -2033,6 +2081,7 @@ copcsr:
                         if (!cpu_has_mips_2_3_4_5_r)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(sqrt_d);
                         handler.u = ieee754dp_sqrt;
                         goto dcopuop;
                 /*
@@ -2044,12 +2093,14 @@ copcsr:
                         if (!cpu_has_mips_4_5_64_r2_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(rsqrt_d);
                         handler.u = fpemu_dp_rsqrt;
                         goto dcopuop;
                 case frecip_op:
                         if (!cpu_has_mips_4_5_64_r2_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(recip_d);
                         handler.u = fpemu_dp_recip;
                         goto dcopuop;
                 case fmovc_op:
@@ -2083,6 +2134,7 @@ copcsr:
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(seleqz_d);
                         DPFROMREG(rv.d, MIPSInst_FT(ir));
                         if (rv.l & 0x1)
                                 rv.l = 0;
@@ -2094,6 +2146,7 @@ copcsr:
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(selnez_d);
                         DPFROMREG(rv.d, MIPSInst_FT(ir));
                         if (rv.l & 0x1)
                                 DPFROMREG(rv.d, MIPSInst_FS(ir));
@@ -2107,6 +2160,7 @@ copcsr:
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(maddf_d);
                         DPFROMREG(ft, MIPSInst_FT(ir));
                         DPFROMREG(fs, MIPSInst_FS(ir));
                         DPFROMREG(fd, MIPSInst_FD(ir));
@@ -2120,6 +2174,7 @@ copcsr:
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(msubf_d);
                         DPFROMREG(ft, MIPSInst_FT(ir));
                         DPFROMREG(fs, MIPSInst_FS(ir));
                         DPFROMREG(fd, MIPSInst_FD(ir));
@@ -2133,9 +2188,9 @@ copcsr:
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(rint_d);
                         DPFROMREG(fs, MIPSInst_FS(ir));
-                        rv.l = ieee754dp_tlong(fs);
-                        rv.d = ieee754dp_flong(rv.l);
+                        rv.d = ieee754dp_rint(fs);
                         goto copcsr;
                 }
 
@@ -2145,9 +2200,10 @@ copcsr:
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(class_d);
                         DPFROMREG(fs, MIPSInst_FS(ir));
-                        rv.w = ieee754dp_2008class(fs);
-                        rfmt = w_fmt;
+                        rv.l = ieee754dp_2008class(fs);
+                        rfmt = l_fmt;
                         break;
                 }
 
@@ -2157,6 +2213,7 @@ copcsr:
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(min_d);
                         DPFROMREG(ft, MIPSInst_FT(ir));
                         DPFROMREG(fs, MIPSInst_FS(ir));
                         rv.d = ieee754dp_fmin(fs, ft);
@@ -2169,6 +2226,7 @@ copcsr:
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(mina_d);
                         DPFROMREG(ft, MIPSInst_FT(ir));
                         DPFROMREG(fs, MIPSInst_FS(ir));
                         rv.d = ieee754dp_fmina(fs, ft);
@@ -2181,6 +2239,7 @@ copcsr:
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(max_d);
                         DPFROMREG(ft, MIPSInst_FT(ir));
                         DPFROMREG(fs, MIPSInst_FS(ir));
                         rv.d = ieee754dp_fmax(fs, ft);
@@ -2193,6 +2252,7 @@ copcsr:
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(maxa_d);
                         DPFROMREG(ft, MIPSInst_FT(ir));
                         DPFROMREG(fs, MIPSInst_FS(ir));
                         rv.d = ieee754dp_fmaxa(fs, ft);
@@ -2200,15 +2260,18 @@ copcsr:
                 }
 
                 case fabs_op:
+                        MIPS_FPU_EMU_INC_STATS(abs_d);
                         handler.u = ieee754dp_abs;
                         goto dcopuop;
 
                 case fneg_op:
+                        MIPS_FPU_EMU_INC_STATS(neg_d);
                         handler.u = ieee754dp_neg;
                         goto dcopuop;
 
                 case fmov_op:
                         /* an easy one */
+                        MIPS_FPU_EMU_INC_STATS(mov_d);
                         DPFROMREG(rv.d, MIPSInst_FS(ir));
                         goto copcsr;
 
@@ -2228,6 +2291,7 @@ dcopuop:
                  * unary conv ops
                  */
                 case fcvts_op:
+                        MIPS_FPU_EMU_INC_STATS(cvt_s_d);
                         DPFROMREG(fs, MIPSInst_FS(ir));
                         rv.s = ieee754sp_fdp(fs);
                         rfmt = s_fmt;
@@ -2237,6 +2301,7 @@ dcopuop:
                         return SIGILL;  /* not defined */
 
                 case fcvtw_op:
+                        MIPS_FPU_EMU_INC_STATS(cvt_w_d);
                         DPFROMREG(fs, MIPSInst_FS(ir));
                         rv.w = ieee754dp_tint(fs);      /* wrong */
                         rfmt = w_fmt;
@@ -2249,6 +2314,15 @@ dcopuop:
                         if (!cpu_has_mips_2_3_4_5_r)
                                 return SIGILL;
 
+                        if (MIPSInst_FUNC(ir) == fceil_op)
+                                MIPS_FPU_EMU_INC_STATS(ceil_w_d);
+                        if (MIPSInst_FUNC(ir) == ffloor_op)
+                                MIPS_FPU_EMU_INC_STATS(floor_w_d);
+                        if (MIPSInst_FUNC(ir) == fround_op)
+                                MIPS_FPU_EMU_INC_STATS(round_w_d);
+                        if (MIPSInst_FUNC(ir) == ftrunc_op)
+                                MIPS_FPU_EMU_INC_STATS(trunc_w_d);
+
                         oldrm = ieee754_csr.rm;
                         DPFROMREG(fs, MIPSInst_FS(ir));
                         ieee754_csr.rm = MIPSInst_FUNC(ir);
@@ -2261,6 +2335,7 @@ dcopuop:
                         if (!cpu_has_mips_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(sel_d);
                         DPFROMREG(fd, MIPSInst_FD(ir));
                         if (fd.bits & 0x1)
                                 DPFROMREG(rv.d, MIPSInst_FT(ir));
@@ -2272,6 +2347,7 @@ dcopuop:
                         if (!cpu_has_mips_3_4_5_64_r2_r6)
                                 return SIGILL;
 
+                        MIPS_FPU_EMU_INC_STATS(cvt_l_d);
                         DPFROMREG(fs, MIPSInst_FS(ir));
                         rv.l = ieee754dp_tlong(fs);
                         rfmt = l_fmt;
@@ -2284,6 +2360,15 @@ dcopuop:
                         if (!cpu_has_mips_3_4_5_64_r2_r6)
                                 return SIGILL;
 
+                        if (MIPSInst_FUNC(ir) == fceill_op)
+                                MIPS_FPU_EMU_INC_STATS(ceil_l_d);
+                        if (MIPSInst_FUNC(ir) == ffloorl_op)
+                                MIPS_FPU_EMU_INC_STATS(floor_l_d);
+                        if (MIPSInst_FUNC(ir) == froundl_op)
+                                MIPS_FPU_EMU_INC_STATS(round_l_d);
+                        if (MIPSInst_FUNC(ir) == ftruncl_op)
+                                MIPS_FPU_EMU_INC_STATS(trunc_l_d);
+
                         oldrm = ieee754_csr.rm;
                         DPFROMREG(fs, MIPSInst_FS(ir));
                         ieee754_csr.rm = MIPSInst_FUNC(ir);
@@ -2325,12 +2410,14 @@ dcopuop:
                 switch (MIPSInst_FUNC(ir)) {
                 case fcvts_op:
                         /* convert word to single precision real */
+                        MIPS_FPU_EMU_INC_STATS(cvt_s_w);
                         SPFROMREG(fs, MIPSInst_FS(ir));
                         rv.s = ieee754sp_fint(fs.bits);
                         rfmt = s_fmt;
                         goto copcsr;
                 case fcvtd_op:
                         /* convert word to double precision real */
+                        MIPS_FPU_EMU_INC_STATS(cvt_d_w);
                         SPFROMREG(fs, MIPSInst_FS(ir));
                         rv.d = ieee754dp_fint(fs.bits);
                         rfmt = d_fmt;
@@ -2350,6 +2437,90 @@ dcopuop:
                             (MIPSInst_FUNC(ir) & 0x20))
                                 return SIGILL;
 
+                        if (!sig) {
+                                if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
+                                        switch (cmpop) {
+                                        case 0:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_af_s);
+                                        break;
+                                        case 1:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_un_s);
+                                        break;
+                                        case 2:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_eq_s);
+                                        break;
+                                        case 3:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_ueq_s);
+                                        break;
+                                        case 4:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_lt_s);
+                                        break;
+                                        case 5:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_ult_s);
+                                        break;
+                                        case 6:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_le_s);
+                                        break;
+                                        case 7:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_ule_s);
+                                        break;
+                                        }
+                                } else {
+                                        switch (cmpop) {
+                                        case 1:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_or_s);
+                                        break;
+                                        case 2:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_une_s);
+                                        break;
+                                        case 3:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_ne_s);
+                                        break;
+                                        }
+                                }
+                        } else {
+                                if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
+                                        switch (cmpop) {
+                                        case 0:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_saf_s);
+                                        break;
+                                        case 1:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_sun_s);
+                                        break;
+                                        case 2:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_seq_s);
+                                        break;
+                                        case 3:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_sueq_s);
+                                        break;
+                                        case 4:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_slt_s);
+                                        break;
+                                        case 5:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_sult_s);
+                                        break;
+                                        case 6:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_sle_s);
+                                        break;
+                                        case 7:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_sule_s);
+                                        break;
+                                        }
+                                } else {
+                                        switch (cmpop) {
+                                        case 1:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_sor_s);
+                                        break;
+                                        case 2:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_sune_s);
+                                        break;
+                                        case 3:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_sne_s);
+                                        break;
+                                        }
+                                }
+                        }
+
                         /* fmt is w_fmt for single precision so fix it */
                         rfmt = s_fmt;
                         /* default to false */
@@ -2394,6 +2565,7 @@ dcopuop:
                         break;
                         }
                 }
+                break;
         }
 
         case l_fmt:
@@ -2406,11 +2578,13 @@ dcopuop:
                 switch (MIPSInst_FUNC(ir)) {
                 case fcvts_op:
                         /* convert long to single precision real */
+                        MIPS_FPU_EMU_INC_STATS(cvt_s_l);
                         rv.s = ieee754sp_flong(bits);
                         rfmt = s_fmt;
                         goto copcsr;
                 case fcvtd_op:
                         /* convert long to double precision real */
+                        MIPS_FPU_EMU_INC_STATS(cvt_d_l);
                         rv.d = ieee754dp_flong(bits);
                         rfmt = d_fmt;
                         goto copcsr;
@@ -2424,6 +2598,90 @@ dcopuop:
                             (MIPSInst_FUNC(ir) & 0x20))
                                 return SIGILL;
 
+                        if (!sig) {
+                                if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
+                                        switch (cmpop) {
+                                        case 0:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_af_d);
+                                        break;
+                                        case 1:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_un_d);
+                                        break;
+                                        case 2:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_eq_d);
+                                        break;
+                                        case 3:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_ueq_d);
+                                        break;
+                                        case 4:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_lt_d);
+                                        break;
+                                        case 5:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_ult_d);
+                                        break;
+                                        case 6:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_le_d);
+                                        break;
+                                        case 7:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_ule_d);
+                                        break;
+                                        }
+                                } else {
+                                        switch (cmpop) {
+                                        case 1:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_or_d);
+                                        break;
+                                        case 2:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_une_d);
+                                        break;
+                                        case 3:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_ne_d);
+                                        break;
+                                        }
+                                }
+                        } else {
+                                if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
+                                        switch (cmpop) {
+                                        case 0:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_saf_d);
+                                        break;
+                                        case 1:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_sun_d);
+                                        break;
+                                        case 2:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_seq_d);
+                                        break;
+                                        case 3:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_sueq_d);
+                                        break;
+                                        case 4:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_slt_d);
+                                        break;
+                                        case 5:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_sult_d);
+                                        break;
+                                        case 6:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_sle_d);
+                                        break;
+                                        case 7:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_sule_d);
+                                        break;
+                                        }
+                                } else {
+                                        switch (cmpop) {
+                                        case 1:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_sor_d);
+                                        break;
+                                        case 2:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_sune_d);
+                                        break;
+                                        case 3:
+                                        MIPS_FPU_EMU_INC_STATS(cmp_sne_d);
+                                        break;
+                                        }
+                                }
+                        }
+
                         /* fmt is l_fmt for double precision so fix it */
                         rfmt = d_fmt;
                         /* default to false */
@@ -2468,6 +2726,8 @@ dcopuop:
                         break;
                         }
                 }
+                break;
+
         default:
                 return SIGILL;
         }
@@ -2553,7 +2813,7 @@ dcopuop:
  * For simplicity we always terminate upon an ISA mode switch.
  */
 int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
-        int has_fpu, void *__user *fault_addr)
+        int has_fpu, void __user **fault_addr)
 {
         unsigned long oldepc, prevepc;
         struct mm_decoded_insn dec_insn;
diff --git a/arch/mips/math-emu/dp_fmax.c b/arch/mips/math-emu/dp_fmax.c
index fd71b8daaaf2..5bec64f2884e 100644
--- a/arch/mips/math-emu/dp_fmax.c
+++ b/arch/mips/math-emu/dp_fmax.c
@@ -47,14 +47,26 @@ union ieee754dp ieee754dp_fmax(union ieee754dp x, union ieee754dp y)
         case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
                 return ieee754dp_nanxcpt(x);
 
-        /* numbers are preferred to NaNs */
+        /*
+         * Quiet NaN handling
+         */
+
+        /*
+         *    The case of both inputs quiet NaNs
+         */
+        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
+                return x;
+
+        /*
+         *    The cases of exactly one input quiet NaN (numbers
+         *    are here preferred as returned values to NaNs)
+         */
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
                 return x;
 
-        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
@@ -80,9 +92,7 @@ union ieee754dp ieee754dp_fmax(union ieee754dp x, union ieee754dp y)
                 return ys ? x : y;
 
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
-                if (xs == ys)
-                        return x;
-                return ieee754dp_zero(1);
+                return ieee754dp_zero(xs & ys);
 
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
                 DPDNORMX;
@@ -106,16 +116,32 @@ union ieee754dp ieee754dp_fmax(union ieee754dp x, union ieee754dp y)
         else if (xs < ys)
                 return x;
 
-        /* Compare exponent */
-        if (xe > ye)
-                return x;
-        else if (xe < ye)
-                return y;
+        /* Signs of inputs are equal, let's compare exponents */
+        if (xs == 0) {
+                /* Inputs are both positive */
+                if (xe > ye)
+                        return x;
+                else if (xe < ye)
+                        return y;
+        } else {
+                /* Inputs are both negative */
+                if (xe > ye)
+                        return y;
+                else if (xe < ye)
+                        return x;
+        }
 
-        /* Compare mantissa */
+        /* Signs and exponents of inputs are equal, let's compare mantissas */
+        if (xs == 0) {
+                /* Inputs are both positive, with equal signs and exponents */
+                if (xm <= ym)
+                        return y;
+                return x;
+        }
+        /* Inputs are both negative, with equal signs and exponents */
         if (xm <= ym)
-                return y;
-        return x;
+                return x;
+        return y;
 }
 
 union ieee754dp ieee754dp_fmaxa(union ieee754dp x, union ieee754dp y)
@@ -147,14 +173,26 @@ union ieee754dp ieee754dp_fmaxa(union ieee754dp x, union ieee754dp y)
         case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
                 return ieee754dp_nanxcpt(x);
 
-        /* numbers are preferred to NaNs */
+        /*
+         * Quiet NaN handling
+         */
+
+        /*
+         *    The case of both inputs quiet NaNs
+         */
+        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
+                return x;
+
+        /*
+         *    The cases of exactly one input quiet NaN (numbers
+         *    are here preferred as returned values to NaNs)
+         */
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
                 return x;
 
-        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
@@ -164,6 +202,9 @@ union ieee754dp ieee754dp_fmaxa(union ieee754dp x, union ieee754dp y)
         /*
          * Infinity and zero handling
          */
+        case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
+                return ieee754dp_inf(xs & ys);
+
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
@@ -171,7 +212,6 @@ union ieee754dp ieee754dp_fmaxa(union ieee754dp x, union ieee754dp y)
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
                 return x;
 
-        case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
         case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF):
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF):
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
@@ -180,9 +220,7 @@ union ieee754dp ieee754dp_fmaxa(union ieee754dp x, union ieee754dp y)
                 return y;
 
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
-                if (xs == ys)
-                        return x;
-                return ieee754dp_zero(1);
+                return ieee754dp_zero(xs & ys);
 
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
                 DPDNORMX;
@@ -207,7 +245,11 @@ union ieee754dp ieee754dp_fmaxa(union ieee754dp x, union ieee754dp y)
                 return y;
 
         /* Compare mantissa */
-        if (xm <= ym)
+        if (xm < ym)
                 return y;
-        return x;
+        else if (xm > ym)
+                return x;
+        else if (xs == 0)
+                return x;
+        return y;
 }
diff --git a/arch/mips/math-emu/dp_fmin.c b/arch/mips/math-emu/dp_fmin.c
index c1072b0dfb95..a287b23818d8 100644
--- a/arch/mips/math-emu/dp_fmin.c
+++ b/arch/mips/math-emu/dp_fmin.c
@@ -47,14 +47,26 @@ union ieee754dp ieee754dp_fmin(union ieee754dp x, union ieee754dp y)
         case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
                 return ieee754dp_nanxcpt(x);
 
-        /* numbers are preferred to NaNs */
+        /*
+         * Quiet NaN handling
+         */
+
+        /*
+         *    The case of both inputs quiet NaNs
+         */
+        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
+                return x;
+
+        /*
+         *    The cases of exactly one input quiet NaN (numbers
+         *    are here preferred as returned values to NaNs)
+         */
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
                 return x;
 
-        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
@@ -80,9 +92,7 @@ union ieee754dp ieee754dp_fmin(union ieee754dp x, union ieee754dp y)
                 return ys ? y : x;
 
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
-                if (xs == ys)
-                        return x;
-                return ieee754dp_zero(1);
+                return ieee754dp_zero(xs | ys);
 
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
                 DPDNORMX;
@@ -106,16 +116,32 @@ union ieee754dp ieee754dp_fmin(union ieee754dp x, union ieee754dp y)
         else if (xs < ys)
                 return y;
 
-        /* Compare exponent */
-        if (xe > ye)
-                return y;
-        else if (xe < ye)
-                return x;
+        /* Signs of inputs are the same, let's compare exponents */
+        if (xs == 0) {
+                /* Inputs are both positive */
+                if (xe > ye)
+                        return y;
+                else if (xe < ye)
+                        return x;
+        } else {
+                /* Inputs are both negative */
+                if (xe > ye)
+                        return x;
+                else if (xe < ye)
+                        return y;
+        }
 
-        /* Compare mantissa */
+        /* Signs and exponents of inputs are equal, let's compare mantissas */
+        if (xs == 0) {
+                /* Inputs are both positive, with equal signs and exponents */
+                if (xm <= ym)
+                        return x;
+                return y;
+        }
+        /* Inputs are both negative, with equal signs and exponents */
         if (xm <= ym)
-                return x;
-        return y;
+                return y;
+        return x;
 }
 
 union ieee754dp ieee754dp_fmina(union ieee754dp x, union ieee754dp y)
@@ -147,14 +173,26 @@ union ieee754dp ieee754dp_fmina(union ieee754dp x, union ieee754dp y)
         case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
                 return ieee754dp_nanxcpt(x);
 
-        /* numbers are preferred to NaNs */
+        /*
+         * Quiet NaN handling
+         */
+
+        /*
+         *    The case of both inputs quiet NaNs
+         */
+        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
+                return x;
+
+        /*
+         *    The cases of exactly one input quiet NaN (numbers
+         *    are here preferred as returned values to NaNs)
+         */
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
                 return x;
 
-        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
@@ -164,25 +202,25 @@ union ieee754dp ieee754dp_fmina(union ieee754dp x, union ieee754dp y)
         /*
          * Infinity and zero handling
          */
+        case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
+                return ieee754dp_inf(xs | ys);
+
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
         case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
-                return x;
+                return y;
 
-        case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
         case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF):
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF):
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM):
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM):
-                return y;
+                return x;
 
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
-                if (xs == ys)
-                        return x;
-                return ieee754dp_zero(1);
+                return ieee754dp_zero(xs | ys);
 
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
                 DPDNORMX;
@@ -207,7 +245,11 @@ union ieee754dp ieee754dp_fmina(union ieee754dp x, union ieee754dp y)
                 return x;
 
         /* Compare mantissa */
-        if (xm <= ym)
+        if (xm < ym)
+                return x;
+        else if (xm > ym)
+                return y;
+        else if (xs == 1)
                 return x;
         return y;
 }
diff --git a/arch/mips/math-emu/dp_maddf.c b/arch/mips/math-emu/dp_maddf.c
index caa62f20a888..e0d9be5fbf4c 100644
--- a/arch/mips/math-emu/dp_maddf.c
+++ b/arch/mips/math-emu/dp_maddf.c
@@ -14,22 +14,45 @@
 
 #include "ieee754dp.h"
 
-enum maddf_flags {
-        maddf_negate_product    = 1 << 0,
-};
+
+/* 128 bits shift right logical with rounding. */
+void srl128(u64 *hptr, u64 *lptr, int count)
+{
+        u64 low;
+
+        if (count >= 128) {
+                *lptr = *hptr != 0 || *lptr != 0;
+                *hptr = 0;
+        } else if (count >= 64) {
+                if (count == 64) {
+                        *lptr = *hptr | (*lptr != 0);
+                } else {
+                        low = *lptr;
+                        *lptr = *hptr >> (count - 64);
+                        *lptr |= (*hptr << (128 - count)) != 0 || low != 0;
+                }
+                *hptr = 0;
+        } else {
+                low = *lptr;
+                *lptr = low >> count | *hptr << (64 - count);
+                *lptr |= (low << (64 - count)) != 0;
+                *hptr = *hptr >> count;
+        }
+}
 
 static union ieee754dp _dp_maddf(union ieee754dp z, union ieee754dp x,
                                  union ieee754dp y, enum maddf_flags flags)
 {
         int re;
         int rs;
-        u64 rm;
         unsigned lxm;
         unsigned hxm;
         unsigned lym;
         unsigned hym;
         u64 lrm;
         u64 hrm;
+        u64 lzm;
+        u64 hzm;
         u64 t;
         u64 at;
         int s;
@@ -48,52 +71,34 @@ static union ieee754dp _dp_maddf(union ieee754dp z, union ieee754dp x,
 
         ieee754_clearcx();
 
-        switch (zc) {
-        case IEEE754_CLASS_SNAN:
-                ieee754_setcx(IEEE754_INVALID_OPERATION);
+        /*
+         * Handle the cases when at least one of x, y or z is a NaN.
+         * Order of precedence is sNaN, qNaN and z, x, y.
+         */
+        if (zc == IEEE754_CLASS_SNAN)
                 return ieee754dp_nanxcpt(z);
-        case IEEE754_CLASS_DNORM:
-                DPDNORMZ;
-        /* QNAN and ZERO cases are handled separately below */
-        }
-
-        switch (CLPAIR(xc, yc)) {
-        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
-        case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
-        case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
-        case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
-        case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
-                return ieee754dp_nanxcpt(y);
-
-        case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
-        case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
-        case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
-        case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
-        case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
-        case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
+        if (xc == IEEE754_CLASS_SNAN)
                 return ieee754dp_nanxcpt(x);
-
-        case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
-        case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
-        case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
-        case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
+        if (yc == IEEE754_CLASS_SNAN)
+                return ieee754dp_nanxcpt(y);
+        if (zc == IEEE754_CLASS_QNAN)
+                return z;
+        if (xc == IEEE754_CLASS_QNAN)
+                return x;
+        if (yc == IEEE754_CLASS_QNAN)
                 return y;
 
-        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
-        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
-        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
-        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
-        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF):
-                return x;
+        if (zc == IEEE754_CLASS_DNORM)
+                DPDNORMZ;
+        /* ZERO z cases are handled separately below */
 
+        switch (CLPAIR(xc, yc)) {
 
         /*
          * Infinity handling
          */
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
-                if (zc == IEEE754_CLASS_QNAN)
-                        return z;
                 ieee754_setcx(IEEE754_INVALID_OPERATION);
                 return ieee754dp_indef();
 
@@ -102,9 +107,27 @@ static union ieee754dp _dp_maddf(union ieee754dp z, union ieee754dp x,
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
-                if (zc == IEEE754_CLASS_QNAN)
-                        return z;
-                return ieee754dp_inf(xs ^ ys);
+                if ((zc == IEEE754_CLASS_INF) &&
+                    ((!(flags & MADDF_NEGATE_PRODUCT) && (zs != (xs ^ ys))) ||
+                     ((flags & MADDF_NEGATE_PRODUCT) && (zs == (xs ^ ys))))) {
+                        /*
+                         * Cases of addition of infinities with opposite signs
+                         * or subtraction of infinities with same signs.
+                         */
+                        ieee754_setcx(IEEE754_INVALID_OPERATION);
+                        return ieee754dp_indef();
+                }
+                /*
+                 * z is here either not an infinity, or an infinity having the
+                 * same sign as product (x*y) (in case of MADDF.D instruction)
+                 * or product -(x*y) (in MSUBF.D case). The result must be an
+                 * infinity, and its sign is determined only by the value of
+                 * (flags & MADDF_NEGATE_PRODUCT) and the signs of x and y.
+                 */
+                if (flags & MADDF_NEGATE_PRODUCT)
+                        return ieee754dp_inf(1 ^ (xs ^ ys));
+                else
+                        return ieee754dp_inf(xs ^ ys);
 
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM):
@@ -113,32 +136,42 @@ static union ieee754dp _dp_maddf(union ieee754dp z, union ieee754dp x,
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
                 if (zc == IEEE754_CLASS_INF)
                         return ieee754dp_inf(zs);
-                /* Multiplication is 0 so just return z */
+                if (zc == IEEE754_CLASS_ZERO) {
+                        /* Handle cases +0 + (-0) and similar ones. */
+                        if ((!(flags & MADDF_NEGATE_PRODUCT)
+                                        && (zs == (xs ^ ys))) ||
+                            ((flags & MADDF_NEGATE_PRODUCT)
+                                        && (zs != (xs ^ ys))))
+                                /*
+                                 * Cases of addition of zeros of equal signs
+                                 * or subtraction of zeroes of opposite signs.
+                                 * The sign of the resulting zero is in any
+                                 * such case determined only by the sign of z.
+                                 */
+                                return z;
+
+                        return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD);
+                }
+                /* x*y is here 0, and z is not 0, so just return z */
                 return z;
 
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
                 DPDNORMX;
 
         case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM):
-                if (zc == IEEE754_CLASS_QNAN)
-                        return z;
-                else if (zc == IEEE754_CLASS_INF)
+                if (zc == IEEE754_CLASS_INF)
                         return ieee754dp_inf(zs);
                 DPDNORMY;
                 break;
 
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM):
-                if (zc == IEEE754_CLASS_QNAN)
-                        return z;
-                else if (zc == IEEE754_CLASS_INF)
+                if (zc == IEEE754_CLASS_INF)
                         return ieee754dp_inf(zs);
                 DPDNORMX;
                 break;
 
         case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM):
-                if (zc == IEEE754_CLASS_QNAN)
-                        return z;
-                else if (zc == IEEE754_CLASS_INF)
+                if (zc == IEEE754_CLASS_INF)
                         return ieee754dp_inf(zs);
                 /* fall through to real computations */
         }
@@ -157,7 +190,7 @@ static union ieee754dp _dp_maddf(union ieee754dp z, union ieee754dp x,
 
         re = xe + ye;
         rs = xs ^ ys;
-        if (flags & maddf_negate_product)
+        if (flags & MADDF_NEGATE_PRODUCT)
                 rs ^= 1;
 
         /* shunt to top of word */
@@ -165,7 +198,7 @@ static union ieee754dp _dp_maddf(union ieee754dp z, union ieee754dp x,
         ym <<= 64 - (DP_FBITS + 1);
 
         /*
-         * Multiply 64 bits xm, ym to give high 64 bits rm with stickness.
+         * Multiply 64 bits xm and ym to give 128 bits result in hrm:lrm.
          */
 
         /* 32 * 32 => 64 */
@@ -195,81 +228,110 @@ static union ieee754dp _dp_maddf(union ieee754dp z, union ieee754dp x,
 
         hrm = hrm + (t >> 32);
 
-        rm = hrm | (lrm != 0);
-
-        /*
-         * Sticky shift down to normal rounding precision.
-         */
-        if ((s64) rm < 0) {
-                rm = (rm >> (64 - (DP_FBITS + 1 + 3))) |
-                     ((rm << (DP_FBITS + 1 + 3)) != 0);
+        /* Put explicit bit at bit 126 if necessary */
+        if ((int64_t)hrm < 0) {
+                lrm = (hrm << 63) | (lrm >> 1);
+                hrm = hrm >> 1;
                 re++;
-        } else {
-                rm = (rm >> (64 - (DP_FBITS + 1 + 3 + 1))) |
-                     ((rm << (DP_FBITS + 1 + 3 + 1)) != 0);
         }
-        assert(rm & (DP_HIDDEN_BIT << 3));
 
-        if (zc == IEEE754_CLASS_ZERO)
-                return ieee754dp_format(rs, re, rm);
+        assert(hrm & (1 << 62));
 
-        /* And now the addition */
-        assert(zm & DP_HIDDEN_BIT);
+        if (zc == IEEE754_CLASS_ZERO) {
+                /*
+                 * Move explicit bit from bit 126 to bit 55 since the
+                 * ieee754dp_format code expects the mantissa to be
+                 * 56 bits wide (53 + 3 rounding bits).
+                 */
+                srl128(&hrm, &lrm, (126 - 55));
+                return ieee754dp_format(rs, re, lrm);
+        }
 
-        /*
-         * Provide guard,round and stick bit space.
-         */
-        zm <<= 3;
+        /* Move explicit bit from bit 52 to bit 126 */
+        lzm = 0;
+        hzm = zm << 10;
+        assert(hzm & (1 << 62));
 
+        /* Make the exponents the same */
         if (ze > re) {
                 /*
                  * Have to shift y fraction right to align.
                  */
                 s = ze - re;
-                rm = XDPSRS(rm, s);
+                srl128(&hrm, &lrm, s);
                 re += s;
         } else if (re > ze) {
                 /*
                  * Have to shift x fraction right to align.
                  */
                 s = re - ze;
-                zm = XDPSRS(zm, s);
+                srl128(&hzm, &lzm, s);
                 ze += s;
         }
         assert(ze == re);
         assert(ze <= DP_EMAX);
 
+        /* Do the addition */
         if (zs == rs) {
                 /*
-                 * Generate 28 bit result of adding two 27 bit numbers
-                 * leaving result in xm, xs and xe.
+                 * Generate 128 bit result by adding two 127 bit numbers
+                 * leaving result in hzm:lzm, zs and ze.
                  */
-                zm = zm + rm;
-
-                if (zm >> (DP_FBITS + 1 + 3)) { /* carry out */
-                        zm = XDPSRS1(zm);
+                hzm = hzm + hrm + (lzm > (lzm + lrm));
+                lzm = lzm + lrm;
+                if ((int64_t)hzm < 0) {        /* carry out */
+                        srl128(&hzm, &lzm, 1);
                         ze++;
                 }
         } else {
-                if (zm >= rm) {
-                        zm = zm - rm;
+                if (hzm > hrm || (hzm == hrm && lzm >= lrm)) {
+                        hzm = hzm - hrm - (lzm < lrm);
+                        lzm = lzm - lrm;
                 } else {
-                        zm = rm - zm;
+                        hzm = hrm - hzm - (lrm < lzm);
+                        lzm = lrm - lzm;
                         zs = rs;
                 }
-                if (zm == 0)
+                if (lzm == 0 && hzm == 0)
                         return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD);
 
                 /*
-                 * Normalize to rounding precision.
+                 * Put explicit bit at bit 126 if necessary.
                  */
-                while ((zm >> (DP_FBITS + 3)) == 0) {
-                        zm <<= 1;
-                        ze--;
+                if (hzm == 0) {
+                        /* left shift by 63 or 64 bits */
+                        if ((int64_t)lzm < 0) {
+                                /* MSB of lzm is the explicit bit */
+                                hzm = lzm >> 1;
+                                lzm = lzm << 63;
+                                ze -= 63;
+                        } else {
+                                hzm = lzm;
+                                lzm = 0;
+                                ze -= 64;
+                        }
+                }
+
+                t = 0;
+                while ((hzm >> (62 - t)) == 0)
+                        t++;
+
+                assert(t <= 62);
+                if (t) {
+                        hzm = hzm << t | lzm >> (64 - t);
+                        lzm = lzm << t;
+                        ze -= t;
                 }
         }
 
-        return ieee754dp_format(zs, ze, zm);
+        /*
+         * Move explicit bit from bit 126 to bit 55 since the
+         * ieee754dp_format code expects the mantissa to be
+         * 56 bits wide (53 + 3 rounding bits).
+         */
+        srl128(&hzm, &lzm, (126 - 55));
+
+        return ieee754dp_format(zs, ze, lzm);
 }
 
 union ieee754dp ieee754dp_maddf(union ieee754dp z, union ieee754dp x,
@@ -281,5 +343,5 @@ union ieee754dp ieee754dp_maddf(union ieee754dp z, union ieee754dp x,
 union ieee754dp ieee754dp_msubf(union ieee754dp z, union ieee754dp x,
                                 union ieee754dp y)
 {
-        return _dp_maddf(z, x, y, maddf_negate_product);
+        return _dp_maddf(z, x, y, MADDF_NEGATE_PRODUCT);
 }
diff --git a/arch/mips/math-emu/dp_rint.c b/arch/mips/math-emu/dp_rint.c
new file mode 100644
index 000000000000..c3b9077ff357
--- /dev/null
+++ b/arch/mips/math-emu/dp_rint.c
@@ -0,0 +1,89 @@
+/* IEEE754 floating point arithmetic
+ * double precision: common utilities
+ */
+/*
+ * MIPS floating point support
+ * Copyright (C) 1994-2000 Algorithmics Ltd.
+ * Copyright (C) 2017 Imagination Technologies, Ltd.
+ * Author: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program.
+ */
+
+#include "ieee754dp.h"
+
+union ieee754dp ieee754dp_rint(union ieee754dp x)
+{
+        union ieee754dp ret;
+        u64 residue;
+        int sticky;
+        int round;
+        int odd;
+
+        COMPXDP;
+
+        ieee754_clearcx();
+
+        EXPLODEXDP;
+        FLUSHXDP;
+
+        if (xc == IEEE754_CLASS_SNAN)
+                return ieee754dp_nanxcpt(x);
+
+        if ((xc == IEEE754_CLASS_QNAN) ||
+            (xc == IEEE754_CLASS_INF) ||
+            (xc == IEEE754_CLASS_ZERO))
+                return x;
+
+        if (xe >= DP_FBITS)
+                return x;
+
+        if (xe < -1) {
+                residue = xm;
+                round = 0;
+                sticky = residue != 0;
+                xm = 0;
+        } else {
+                residue = xm << (64 - DP_FBITS + xe);
+                round = (residue >> 63) != 0;
+                sticky = (residue << 1) != 0;
+                xm >>= DP_FBITS - xe;
+        }
+
+        odd = (xm & 0x1) != 0x0;
+
+        switch (ieee754_csr.rm) {
+        case FPU_CSR_RN:        /* toward nearest */
+                if (round && (sticky || odd))
+                        xm++;
+                break;
+        case FPU_CSR_RZ:        /* toward zero */
+                break;
+        case FPU_CSR_RU:        /* toward +infinity */
+                if ((round || sticky) && !xs)
+                        xm++;
+                break;
+        case FPU_CSR_RD:        /* toward -infinity */
+                if ((round || sticky) && xs)
+                        xm++;
+                break;
+        }
+
+        if (round || sticky)
+                ieee754_setcx(IEEE754_INEXACT);
+
+        ret = ieee754dp_flong(xm);
+        DPSIGN(ret) = xs;
+
+        return ret;
+}
diff --git a/arch/mips/math-emu/ieee754.h b/arch/mips/math-emu/ieee754.h
index d3be351aed15..92dc8fa565cb 100644
--- a/arch/mips/math-emu/ieee754.h
+++ b/arch/mips/math-emu/ieee754.h
@@ -67,6 +67,7 @@ union ieee754sp ieee754sp_div(union ieee754sp x, union ieee754sp y);
 union ieee754sp ieee754sp_fint(int x);
 union ieee754sp ieee754sp_flong(s64 x);
 union ieee754sp ieee754sp_fdp(union ieee754dp x);
+union ieee754sp ieee754sp_rint(union ieee754sp x);
 
 int ieee754sp_tint(union ieee754sp x);
 s64 ieee754sp_tlong(union ieee754sp x);
@@ -101,6 +102,7 @@ union ieee754dp ieee754dp_neg(union ieee754dp x);
 union ieee754dp ieee754dp_fint(int x);
 union ieee754dp ieee754dp_flong(s64 x);
 union ieee754dp ieee754dp_fsp(union ieee754sp x);
+union ieee754dp ieee754dp_rint(union ieee754dp x);
 
 int ieee754dp_tint(union ieee754dp x);
 s64 ieee754dp_tlong(union ieee754dp x);
diff --git a/arch/mips/math-emu/ieee754int.h b/arch/mips/math-emu/ieee754int.h
index 8bc2f6963324..dd2071f430e0 100644
--- a/arch/mips/math-emu/ieee754int.h
+++ b/arch/mips/math-emu/ieee754int.h
@@ -26,6 +26,10 @@
 
 #define CLPAIR(x, y)    ((x)*6+(y))
 
+enum maddf_flags {
+        MADDF_NEGATE_PRODUCT    = 1 << 0,
+};
+
 static inline void ieee754_clearcx(void)
 {
         ieee754_csr.cx = 0;
diff --git a/arch/mips/math-emu/ieee754sp.h b/arch/mips/math-emu/ieee754sp.h
index 8476067075fe..0f63e4202cff 100644
--- a/arch/mips/math-emu/ieee754sp.h
+++ b/arch/mips/math-emu/ieee754sp.h
@@ -45,6 +45,10 @@ static inline int ieee754sp_finite(union ieee754sp x)
         return SPBEXP(x) != SP_EMAX + 1 + SP_EBIAS;
 }
 
+/* 64 bit right shift with rounding */
+#define XSPSRS64(v, rs)                                         \
+        (((rs) >= 64) ? ((v) != 0) : ((v) >> (rs)) | ((v) << (64-(rs)) != 0))
+
 /* 3bit extended single precision sticky right shift */
 #define XSPSRS(v, rs)                                           \
         ((rs > (SP_FBITS+3))?1:((v) >> (rs)) | ((v) << (32-(rs)) != 0))
diff --git a/arch/mips/math-emu/me-debugfs.c b/arch/mips/math-emu/me-debugfs.c
index be650ed7db59..8c0ec154aecc 100644
--- a/arch/mips/math-emu/me-debugfs.c
+++ b/arch/mips/math-emu/me-debugfs.c
@@ -28,14 +28,190 @@ static int fpuemu_stat_get(void *data, u64 *val)
 }
 DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n");
 
+/*
+ * Used to obtain names for a debugfs instruction counter, given field name
+ * in fpuemustats structure. For example, for input "cmp_sueq_d", the output
+ * would be "cmp.sueq.d". This is needed since dots are not allowed to be
+ * used in structure field names, and are, on the other hand, desired to be
+ * used in debugfs item names to be clearly associated to corresponding
+ * MIPS FPU instructions.
+ */
+static void adjust_instruction_counter_name(char *out_name, char *in_name)
+{
+        int i = 0;
+
+        strcpy(out_name, in_name);
+        while (in_name[i] != '\0') {
+                if (out_name[i] == '_')
+                        out_name[i] = '.';
+                i++;
+        }
+}
+
+static int fpuemustats_clear_show(struct seq_file *s, void *unused)
+{
+        __this_cpu_write((fpuemustats).emulated, 0);
+        __this_cpu_write((fpuemustats).loads, 0);
+        __this_cpu_write((fpuemustats).stores, 0);
+        __this_cpu_write((fpuemustats).branches, 0);
+        __this_cpu_write((fpuemustats).cp1ops, 0);
+        __this_cpu_write((fpuemustats).cp1xops, 0);
+        __this_cpu_write((fpuemustats).errors, 0);
+        __this_cpu_write((fpuemustats).ieee754_inexact, 0);
+        __this_cpu_write((fpuemustats).ieee754_underflow, 0);
+        __this_cpu_write((fpuemustats).ieee754_overflow, 0);
+        __this_cpu_write((fpuemustats).ieee754_zerodiv, 0);
+        __this_cpu_write((fpuemustats).ieee754_invalidop, 0);
+        __this_cpu_write((fpuemustats).ds_emul, 0);
+
+        __this_cpu_write((fpuemustats).abs_s, 0);
+        __this_cpu_write((fpuemustats).abs_d, 0);
+        __this_cpu_write((fpuemustats).add_s, 0);
+        __this_cpu_write((fpuemustats).add_d, 0);
+        __this_cpu_write((fpuemustats).bc1eqz, 0);
+        __this_cpu_write((fpuemustats).bc1nez, 0);
+        __this_cpu_write((fpuemustats).ceil_w_s, 0);
+        __this_cpu_write((fpuemustats).ceil_w_d, 0);
+        __this_cpu_write((fpuemustats).ceil_l_s, 0);
+        __this_cpu_write((fpuemustats).ceil_l_d, 0);
+        __this_cpu_write((fpuemustats).class_s, 0);
+        __this_cpu_write((fpuemustats).class_d, 0);
+        __this_cpu_write((fpuemustats).cmp_af_s, 0);
+        __this_cpu_write((fpuemustats).cmp_af_d, 0);
+        __this_cpu_write((fpuemustats).cmp_eq_s, 0);
+        __this_cpu_write((fpuemustats).cmp_eq_d, 0);
+        __this_cpu_write((fpuemustats).cmp_le_s, 0);
+        __this_cpu_write((fpuemustats).cmp_le_d, 0);
+        __this_cpu_write((fpuemustats).cmp_lt_s, 0);
+        __this_cpu_write((fpuemustats).cmp_lt_d, 0);
+        __this_cpu_write((fpuemustats).cmp_ne_s, 0);
+        __this_cpu_write((fpuemustats).cmp_ne_d, 0);
+        __this_cpu_write((fpuemustats).cmp_or_s, 0);
+        __this_cpu_write((fpuemustats).cmp_or_d, 0);
+        __this_cpu_write((fpuemustats).cmp_ueq_s, 0);
+        __this_cpu_write((fpuemustats).cmp_ueq_d, 0);
+        __this_cpu_write((fpuemustats).cmp_ule_s, 0);
+        __this_cpu_write((fpuemustats).cmp_ule_d, 0);
+        __this_cpu_write((fpuemustats).cmp_ult_s, 0);
+        __this_cpu_write((fpuemustats).cmp_ult_d, 0);
+        __this_cpu_write((fpuemustats).cmp_un_s, 0);
+        __this_cpu_write((fpuemustats).cmp_un_d, 0);
+        __this_cpu_write((fpuemustats).cmp_une_s, 0);
+        __this_cpu_write((fpuemustats).cmp_une_d, 0);
+        __this_cpu_write((fpuemustats).cmp_saf_s, 0);
+        __this_cpu_write((fpuemustats).cmp_saf_d, 0);
+        __this_cpu_write((fpuemustats).cmp_seq_s, 0);
+        __this_cpu_write((fpuemustats).cmp_seq_d, 0);
+        __this_cpu_write((fpuemustats).cmp_sle_s, 0);
+        __this_cpu_write((fpuemustats).cmp_sle_d, 0);
+        __this_cpu_write((fpuemustats).cmp_slt_s, 0);
+        __this_cpu_write((fpuemustats).cmp_slt_d, 0);
+        __this_cpu_write((fpuemustats).cmp_sne_s, 0);
+        __this_cpu_write((fpuemustats).cmp_sne_d, 0);
+        __this_cpu_write((fpuemustats).cmp_sor_s, 0);
+        __this_cpu_write((fpuemustats).cmp_sor_d, 0);
+        __this_cpu_write((fpuemustats).cmp_sueq_s, 0);
+        __this_cpu_write((fpuemustats).cmp_sueq_d, 0);
+        __this_cpu_write((fpuemustats).cmp_sule_s, 0);
+        __this_cpu_write((fpuemustats).cmp_sule_d, 0);
+        __this_cpu_write((fpuemustats).cmp_sult_s, 0);
+        __this_cpu_write((fpuemustats).cmp_sult_d, 0);
+        __this_cpu_write((fpuemustats).cmp_sun_s, 0);
+        __this_cpu_write((fpuemustats).cmp_sun_d, 0);
+        __this_cpu_write((fpuemustats).cmp_sune_s, 0);
+        __this_cpu_write((fpuemustats).cmp_sune_d, 0);
+        __this_cpu_write((fpuemustats).cvt_d_l, 0);
+        __this_cpu_write((fpuemustats).cvt_d_s, 0);
+        __this_cpu_write((fpuemustats).cvt_d_w, 0);
+        __this_cpu_write((fpuemustats).cvt_l_s, 0);
+        __this_cpu_write((fpuemustats).cvt_l_d, 0);
+        __this_cpu_write((fpuemustats).cvt_s_d, 0);
+        __this_cpu_write((fpuemustats).cvt_s_l, 0);
+        __this_cpu_write((fpuemustats).cvt_s_w, 0);
+        __this_cpu_write((fpuemustats).cvt_w_s, 0);
+        __this_cpu_write((fpuemustats).cvt_w_d, 0);
+        __this_cpu_write((fpuemustats).div_s, 0);
+        __this_cpu_write((fpuemustats).div_d, 0);
+        __this_cpu_write((fpuemustats).floor_w_s, 0);
+        __this_cpu_write((fpuemustats).floor_w_d, 0);
+        __this_cpu_write((fpuemustats).floor_l_s, 0);
+        __this_cpu_write((fpuemustats).floor_l_d, 0);
+        __this_cpu_write((fpuemustats).maddf_s, 0);
+        __this_cpu_write((fpuemustats).maddf_d, 0);
+        __this_cpu_write((fpuemustats).max_s, 0);
+        __this_cpu_write((fpuemustats).max_d, 0);
+        __this_cpu_write((fpuemustats).maxa_s, 0);
+        __this_cpu_write((fpuemustats).maxa_d, 0);
+        __this_cpu_write((fpuemustats).min_s, 0);
+        __this_cpu_write((fpuemustats).min_d, 0);
+        __this_cpu_write((fpuemustats).mina_s, 0);
+        __this_cpu_write((fpuemustats).mina_d, 0);
+        __this_cpu_write((fpuemustats).mov_s, 0);
+        __this_cpu_write((fpuemustats).mov_d, 0);
+        __this_cpu_write((fpuemustats).msubf_s, 0);
+        __this_cpu_write((fpuemustats).msubf_d, 0);
+        __this_cpu_write((fpuemustats).mul_s, 0);
+        __this_cpu_write((fpuemustats).mul_d, 0);
+        __this_cpu_write((fpuemustats).neg_s, 0);
+        __this_cpu_write((fpuemustats).neg_d, 0);
+        __this_cpu_write((fpuemustats).recip_s, 0);
+        __this_cpu_write((fpuemustats).recip_d, 0);
+        __this_cpu_write((fpuemustats).rint_s, 0);
+        __this_cpu_write((fpuemustats).rint_d, 0);
+        __this_cpu_write((fpuemustats).round_w_s, 0);
+        __this_cpu_write((fpuemustats).round_w_d, 0);
+        __this_cpu_write((fpuemustats).round_l_s, 0);
+        __this_cpu_write((fpuemustats).round_l_d, 0);
+        __this_cpu_write((fpuemustats).rsqrt_s, 0);
+        __this_cpu_write((fpuemustats).rsqrt_d, 0);
+        __this_cpu_write((fpuemustats).sel_s, 0);
+        __this_cpu_write((fpuemustats).sel_d, 0);
+        __this_cpu_write((fpuemustats).seleqz_s, 0);
+        __this_cpu_write((fpuemustats).seleqz_d, 0);
+        __this_cpu_write((fpuemustats).selnez_s, 0);
+        __this_cpu_write((fpuemustats).selnez_d, 0);
+        __this_cpu_write((fpuemustats).sqrt_s, 0);
+        __this_cpu_write((fpuemustats).sqrt_d, 0);
+        __this_cpu_write((fpuemustats).sub_s, 0);
+        __this_cpu_write((fpuemustats).sub_d, 0);
+        __this_cpu_write((fpuemustats).trunc_w_s, 0);
+        __this_cpu_write((fpuemustats).trunc_w_d, 0);
+        __this_cpu_write((fpuemustats).trunc_l_s, 0);
+        __this_cpu_write((fpuemustats).trunc_l_d, 0);
+
+        return 0;
+}
+
+static int fpuemustats_clear_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, fpuemustats_clear_show, inode->i_private);
+}
+
+static const struct file_operations fpuemustats_clear_fops = {
+        .open                   = fpuemustats_clear_open,
+        .read                   = seq_read,
+        .llseek                 = seq_lseek,
+        .release                = single_release,
+};
+
 static int __init debugfs_fpuemu(void)
 {
-        struct dentry *d, *dir;
+        struct dentry *fpuemu_debugfs_base_dir;
+        struct dentry *fpuemu_debugfs_inst_dir;
+        struct dentry *d, *reset_file;
 
         if (!mips_debugfs_dir)
                 return -ENODEV;
-        dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir);
-        if (!dir)
+
+        fpuemu_debugfs_base_dir = debugfs_create_dir("fpuemustats",
+                                                     mips_debugfs_dir);
+        if (!fpuemu_debugfs_base_dir)
+                return -ENOMEM;
+
+        reset_file = debugfs_create_file("fpuemustats_clear", 0444,
+                                         mips_debugfs_dir, NULL,
+                                         &fpuemustats_clear_fops);
+        if (!reset_file)
                 return -ENOMEM;
 
 #define FPU_EMU_STAT_OFFSET(m)                                          \
@@ -43,7 +219,7 @@ static int __init debugfs_fpuemu(void)
 
 #define FPU_STAT_CREATE(m)                                              \
 do {                                                                    \
-        d = debugfs_create_file(#m , S_IRUGO, dir,                      \
+        d = debugfs_create_file(#m, 0444, fpuemu_debugfs_base_dir,      \
                                 (void *)FPU_EMU_STAT_OFFSET(m),         \
                                 &fops_fpuemu_stat);                     \
         if (!d)                                                         \
@@ -53,6 +229,7 @@ do {									\
         FPU_STAT_CREATE(emulated);
         FPU_STAT_CREATE(loads);
         FPU_STAT_CREATE(stores);
+        FPU_STAT_CREATE(branches);
         FPU_STAT_CREATE(cp1ops);
         FPU_STAT_CREATE(cp1xops);
         FPU_STAT_CREATE(errors);
@@ -63,6 +240,139 @@ do {									\
         FPU_STAT_CREATE(ieee754_invalidop);
         FPU_STAT_CREATE(ds_emul);
 
+        fpuemu_debugfs_inst_dir = debugfs_create_dir("instructions",
+                                                     fpuemu_debugfs_base_dir);
+        if (!fpuemu_debugfs_inst_dir)
+                return -ENOMEM;
+
+#define FPU_STAT_CREATE_EX(m)                                           \
+do {                                                                    \
+        char name[32];                                                  \
+                                                                        \
+        adjust_instruction_counter_name(name, #m);                      \
+                                                                        \
+        d = debugfs_create_file(name, 0444, fpuemu_debugfs_inst_dir,    \
+                                (void *)FPU_EMU_STAT_OFFSET(m),         \
+                                &fops_fpuemu_stat);                     \
+        if (!d)                                                         \
+                return -ENOMEM;                                         \
+} while (0)
+
+        FPU_STAT_CREATE_EX(abs_s);
+        FPU_STAT_CREATE_EX(abs_d);
+        FPU_STAT_CREATE_EX(add_s);
+        FPU_STAT_CREATE_EX(add_d);
+        FPU_STAT_CREATE_EX(bc1eqz);
+        FPU_STAT_CREATE_EX(bc1nez);
+        FPU_STAT_CREATE_EX(ceil_w_s);
+        FPU_STAT_CREATE_EX(ceil_w_d);
+        FPU_STAT_CREATE_EX(ceil_l_s);
+        FPU_STAT_CREATE_EX(ceil_l_d);
+        FPU_STAT_CREATE_EX(class_s);
+        FPU_STAT_CREATE_EX(class_d);
+        FPU_STAT_CREATE_EX(cmp_af_s);
+        FPU_STAT_CREATE_EX(cmp_af_d);
+        FPU_STAT_CREATE_EX(cmp_eq_s);
+        FPU_STAT_CREATE_EX(cmp_eq_d);
+        FPU_STAT_CREATE_EX(cmp_le_s);
+        FPU_STAT_CREATE_EX(cmp_le_d);
+        FPU_STAT_CREATE_EX(cmp_lt_s);
+        FPU_STAT_CREATE_EX(cmp_lt_d);
+        FPU_STAT_CREATE_EX(cmp_ne_s);
+        FPU_STAT_CREATE_EX(cmp_ne_d);
+        FPU_STAT_CREATE_EX(cmp_or_s);
+        FPU_STAT_CREATE_EX(cmp_or_d);
+        FPU_STAT_CREATE_EX(cmp_ueq_s);
+        FPU_STAT_CREATE_EX(cmp_ueq_d);
+        FPU_STAT_CREATE_EX(cmp_ule_s);
+        FPU_STAT_CREATE_EX(cmp_ule_d);
+        FPU_STAT_CREATE_EX(cmp_ult_s);
+        FPU_STAT_CREATE_EX(cmp_ult_d);
+        FPU_STAT_CREATE_EX(cmp_un_s);
+        FPU_STAT_CREATE_EX(cmp_un_d);
+        FPU_STAT_CREATE_EX(cmp_une_s);
+        FPU_STAT_CREATE_EX(cmp_une_d);
+        FPU_STAT_CREATE_EX(cmp_saf_s);
+        FPU_STAT_CREATE_EX(cmp_saf_d);
+        FPU_STAT_CREATE_EX(cmp_seq_s);
+        FPU_STAT_CREATE_EX(cmp_seq_d);
+        FPU_STAT_CREATE_EX(cmp_sle_s);
+        FPU_STAT_CREATE_EX(cmp_sle_d);
+        FPU_STAT_CREATE_EX(cmp_slt_s);
+        FPU_STAT_CREATE_EX(cmp_slt_d);
+        FPU_STAT_CREATE_EX(cmp_sne_s);
+        FPU_STAT_CREATE_EX(cmp_sne_d);
+        FPU_STAT_CREATE_EX(cmp_sor_s);
+        FPU_STAT_CREATE_EX(cmp_sor_d);
+        FPU_STAT_CREATE_EX(cmp_sueq_s);
+        FPU_STAT_CREATE_EX(cmp_sueq_d);
+        FPU_STAT_CREATE_EX(cmp_sule_s);
+        FPU_STAT_CREATE_EX(cmp_sule_d);
+        FPU_STAT_CREATE_EX(cmp_sult_s);
+        FPU_STAT_CREATE_EX(cmp_sult_d);
+        FPU_STAT_CREATE_EX(cmp_sun_s);
+        FPU_STAT_CREATE_EX(cmp_sun_d);
+        FPU_STAT_CREATE_EX(cmp_sune_s);
+        FPU_STAT_CREATE_EX(cmp_sune_d);
+        FPU_STAT_CREATE_EX(cvt_d_l);
+        FPU_STAT_CREATE_EX(cvt_d_s);
+        FPU_STAT_CREATE_EX(cvt_d_w);
+        FPU_STAT_CREATE_EX(cvt_l_s);
+        FPU_STAT_CREATE_EX(cvt_l_d);
+        FPU_STAT_CREATE_EX(cvt_s_d);
+        FPU_STAT_CREATE_EX(cvt_s_l);
+        FPU_STAT_CREATE_EX(cvt_s_w);
+        FPU_STAT_CREATE_EX(cvt_w_s);
+        FPU_STAT_CREATE_EX(cvt_w_d);
+        FPU_STAT_CREATE_EX(div_s);
+        FPU_STAT_CREATE_EX(div_d);
+        FPU_STAT_CREATE_EX(floor_w_s);
+        FPU_STAT_CREATE_EX(floor_w_d);
+        FPU_STAT_CREATE_EX(floor_l_s);
+        FPU_STAT_CREATE_EX(floor_l_d);
+        FPU_STAT_CREATE_EX(maddf_s);
+        FPU_STAT_CREATE_EX(maddf_d);
+        FPU_STAT_CREATE_EX(max_s);
+        FPU_STAT_CREATE_EX(max_d);
+        FPU_STAT_CREATE_EX(maxa_s);
+        FPU_STAT_CREATE_EX(maxa_d);
+        FPU_STAT_CREATE_EX(min_s);
+        FPU_STAT_CREATE_EX(min_d);
+        FPU_STAT_CREATE_EX(mina_s);
+        FPU_STAT_CREATE_EX(mina_d);
+        FPU_STAT_CREATE_EX(mov_s);
+        FPU_STAT_CREATE_EX(mov_d);
+        FPU_STAT_CREATE_EX(msubf_s);
+        FPU_STAT_CREATE_EX(msubf_d);
+        FPU_STAT_CREATE_EX(mul_s);
+        FPU_STAT_CREATE_EX(mul_d);
+        FPU_STAT_CREATE_EX(neg_s);
+        FPU_STAT_CREATE_EX(neg_d);
+        FPU_STAT_CREATE_EX(recip_s);
+        FPU_STAT_CREATE_EX(recip_d);
+        FPU_STAT_CREATE_EX(rint_s);
+        FPU_STAT_CREATE_EX(rint_d);
+        FPU_STAT_CREATE_EX(round_w_s);
+        FPU_STAT_CREATE_EX(round_w_d);
+        FPU_STAT_CREATE_EX(round_l_s);
+        FPU_STAT_CREATE_EX(round_l_d);
+        FPU_STAT_CREATE_EX(rsqrt_s);
+        FPU_STAT_CREATE_EX(rsqrt_d);
+        FPU_STAT_CREATE_EX(sel_s);
+        FPU_STAT_CREATE_EX(sel_d);
+        FPU_STAT_CREATE_EX(seleqz_s);
+        FPU_STAT_CREATE_EX(seleqz_d);
+        FPU_STAT_CREATE_EX(selnez_s);
+        FPU_STAT_CREATE_EX(selnez_d);
+        FPU_STAT_CREATE_EX(sqrt_s);
+        FPU_STAT_CREATE_EX(sqrt_d);
+        FPU_STAT_CREATE_EX(sub_s);
+        FPU_STAT_CREATE_EX(sub_d);
+        FPU_STAT_CREATE_EX(trunc_w_s);
+        FPU_STAT_CREATE_EX(trunc_w_d);
+        FPU_STAT_CREATE_EX(trunc_l_s);
+        FPU_STAT_CREATE_EX(trunc_l_d);
+
         return 0;
 }
 arch_initcall(debugfs_fpuemu);
diff --git a/arch/mips/math-emu/sp_fmax.c b/arch/mips/math-emu/sp_fmax.c
index 4d000844e48e..74a5a00d2f22 100644
--- a/arch/mips/math-emu/sp_fmax.c
+++ b/arch/mips/math-emu/sp_fmax.c
@@ -47,14 +47,26 @@ union ieee754sp ieee754sp_fmax(union ieee754sp x, union ieee754sp y)
         case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
                 return ieee754sp_nanxcpt(x);
 
-        /* numbers are preferred to NaNs */
+        /*
+         * Quiet NaN handling
+         */
+
+        /*
+         *    The case of both inputs quiet NaNs
+         */
+        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
+                return x;
+
+        /*
+         *    The cases of exactly one input quiet NaN (numbers
+         *    are here preferred as returned values to NaNs)
+         */
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
                 return x;
 
-        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
@@ -80,9 +92,7 @@ union ieee754sp ieee754sp_fmax(union ieee754sp x, union ieee754sp y)
                 return ys ? x : y;
 
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
-                if (xs == ys)
-                        return x;
-                return ieee754sp_zero(1);
+                return ieee754sp_zero(xs & ys);
 
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
                 SPDNORMX;
@@ -106,16 +116,32 @@ union ieee754sp ieee754sp_fmax(union ieee754sp x, union ieee754sp y)
         else if (xs < ys)
                 return x;
 
-        /* Compare exponent */
-        if (xe > ye)
-                return x;
-        else if (xe < ye)
-                return y;
+        /* Signs of inputs are equal, let's compare exponents */
+        if (xs == 0) {
+                /* Inputs are both positive */
+                if (xe > ye)
+                        return x;
+                else if (xe < ye)
+                        return y;
+        } else {
+                /* Inputs are both negative */
+                if (xe > ye)
+                        return y;
+                else if (xe < ye)
+                        return x;
+        }
 
-        /* Compare mantissa */
+        /* Signs and exponents of inputs are equal, let's compare mantissas */
+        if (xs == 0) {
+                /* Inputs are both positive, with equal signs and exponents */
+                if (xm <= ym)
+                        return y;
+                return x;
+        }
+        /* Inputs are both negative, with equal signs and exponents */
         if (xm <= ym)
-                return y;
-        return x;
+                return x;
+        return y;
 }
 
 union ieee754sp ieee754sp_fmaxa(union ieee754sp x, union ieee754sp y)
@@ -147,14 +173,26 @@ union ieee754sp ieee754sp_fmaxa(union ieee754sp x, union ieee754sp y)
         case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
                 return ieee754sp_nanxcpt(x);
 
-        /* numbers are preferred to NaNs */
+        /*
+         * Quiet NaN handling
+         */
+
+        /*
+         *    The case of both inputs quiet NaNs
+         */
+        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
+                return x;
+
+        /*
+         *    The cases of exactly one input quiet NaN (numbers
+         *    are here preferred as returned values to NaNs)
+         */
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
                 return x;
 
-        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
@@ -164,6 +202,9 @@ union ieee754sp ieee754sp_fmaxa(union ieee754sp x, union ieee754sp y)
         /*
          * Infinity and zero handling
          */
+        case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
+                return ieee754sp_inf(xs & ys);
+
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
@@ -171,7 +212,6 @@ union ieee754sp ieee754sp_fmaxa(union ieee754sp x, union ieee754sp y)
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
                 return x;
 
-        case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
         case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF):
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF):
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
@@ -180,9 +220,7 @@ union ieee754sp ieee754sp_fmaxa(union ieee754sp x, union ieee754sp y)
                 return y;
 
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
-                if (xs == ys)
-                        return x;
-                return ieee754sp_zero(1);
+                return ieee754sp_zero(xs & ys);
 
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
                 SPDNORMX;
@@ -207,7 +245,11 @@ union ieee754sp ieee754sp_fmaxa(union ieee754sp x, union ieee754sp y)
                 return y;
 
         /* Compare mantissa */
-        if (xm <= ym)
+        if (xm < ym)
                 return y;
-        return x;
+        else if (xm > ym)
+                return x;
+        else if (xs == 0)
+                return x;
+        return y;
 }
diff --git a/arch/mips/math-emu/sp_fmin.c b/arch/mips/math-emu/sp_fmin.c
index 4eb1bb9e9dec..c51385f46b09 100644
--- a/arch/mips/math-emu/sp_fmin.c
+++ b/arch/mips/math-emu/sp_fmin.c
@@ -47,14 +47,26 @@ union ieee754sp ieee754sp_fmin(union ieee754sp x, union ieee754sp y)
         case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
                 return ieee754sp_nanxcpt(x);
 
-        /* numbers are preferred to NaNs */
+        /*
+         * Quiet NaN handling
+         */
+
+        /*
+         *    The case of both inputs quiet NaNs
+         */
+        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
+                return x;
+
+        /*
+         *    The cases of exactly one input quiet NaN (numbers
+         *    are here preferred as returned values to NaNs)
+         */
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
                 return x;
 
-        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
@@ -80,9 +92,7 @@ union ieee754sp ieee754sp_fmin(union ieee754sp x, union ieee754sp y)
                 return ys ? y : x;
 
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
-                if (xs == ys)
-                        return x;
-                return ieee754sp_zero(1);
+                return ieee754sp_zero(xs | ys);
 
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
                 SPDNORMX;
@@ -106,16 +116,32 @@ union ieee754sp ieee754sp_fmin(union ieee754sp x, union ieee754sp y)
         else if (xs < ys)
                 return y;
 
-        /* Compare exponent */
-        if (xe > ye)
-                return y;
-        else if (xe < ye)
-                return x;
+        /* Signs of inputs are the same, let's compare exponents */
+        if (xs == 0) {
+                /* Inputs are both positive */
+                if (xe > ye)
+                        return y;
+                else if (xe < ye)
+                        return x;
+        } else {
+                /* Inputs are both negative */
+                if (xe > ye)
+                        return x;
+                else if (xe < ye)
+                        return y;
+        }
 
-        /* Compare mantissa */
+        /* Signs and exponents of inputs are equal, let's compare mantissas */
+        if (xs == 0) {
+                /* Inputs are both positive, with equal signs and exponents */
+                if (xm <= ym)
+                        return x;
+                return y;
+        }
+        /* Inputs are both negative, with equal signs and exponents */
         if (xm <= ym)
-                return x;
-        return y;
+                return y;
+        return x;
 }
 
 union ieee754sp ieee754sp_fmina(union ieee754sp x, union ieee754sp y)
@@ -147,14 +173,26 @@ union ieee754sp ieee754sp_fmina(union ieee754sp x, union ieee754sp y)
         case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
                 return ieee754sp_nanxcpt(x);
 
-        /* numbers are preferred to NaNs */
+        /*
+         * Quiet NaN handling
+         */
+
+        /*
+         *    The case of both inputs quiet NaNs
+         */
+        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
+                return x;
+
+        /*
+         *    The cases of exactly one input quiet NaN (numbers
+         *    are here preferred as returned values to NaNs)
+         */
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
                 return x;
 
-        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
         case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
@@ -164,25 +202,25 @@ union ieee754sp ieee754sp_fmina(union ieee754sp x, union ieee754sp y)
         /*
          * Infinity and zero handling
          */
+        case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
+                return ieee754sp_inf(xs | ys);
+
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
         case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
-                return x;
+                return y;
 
-        case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
         case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF):
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF):
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM):
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM):
-                return y;
+                return x;
 
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
-                if (xs == ys)
-                        return x;
-                return ieee754sp_zero(1);
+                return ieee754sp_zero(xs | ys);
 
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
                 SPDNORMX;
@@ -207,7 +245,11 @@ union ieee754sp ieee754sp_fmina(union ieee754sp x, union ieee754sp y)
                 return x;
 
         /* Compare mantissa */
-        if (xm <= ym)
+        if (xm < ym)
+                return x;
+        else if (xm > ym)
+                return y;
+        else if (xs == 1)
                 return x;
         return y;
 }
diff --git a/arch/mips/math-emu/sp_maddf.c b/arch/mips/math-emu/sp_maddf.c
index c91d5e5d9b5f..7195fe785d81 100644
--- a/arch/mips/math-emu/sp_maddf.c
+++ b/arch/mips/math-emu/sp_maddf.c
@@ -14,9 +14,6 @@
 
 #include "ieee754sp.h"
 
-enum maddf_flags {
-        maddf_negate_product    = 1 << 0,
-};
 
 static union ieee754sp _sp_maddf(union ieee754sp z, union ieee754sp x,
                                  union ieee754sp y, enum maddf_flags flags)
@@ -24,14 +21,8 @@ static union ieee754sp _sp_maddf(union ieee754sp z, union ieee754sp x,
         int re;
         int rs;
         unsigned rm;
-        unsigned short lxm;
-        unsigned short hxm;
-        unsigned short lym;
-        unsigned short hym;
-        unsigned lrm;
-        unsigned hrm;
-        unsigned t;
-        unsigned at;
+        uint64_t rm64;
+        uint64_t zm64;
         int s;
 
         COMPXSP;
@@ -48,51 +39,35 @@ static union ieee754sp _sp_maddf(union ieee754sp z, union ieee754sp x,
 
         ieee754_clearcx();
 
-        switch (zc) {
-        case IEEE754_CLASS_SNAN:
-                ieee754_setcx(IEEE754_INVALID_OPERATION);
+        /*
+         * Handle the cases when at least one of x, y or z is a NaN.
+         * Order of precedence is sNaN, qNaN and z, x, y.
+         */
+        if (zc == IEEE754_CLASS_SNAN)
                 return ieee754sp_nanxcpt(z);
-        case IEEE754_CLASS_DNORM:
-                SPDNORMZ;
-        /* QNAN and ZERO cases are handled separately below */
-        }
-
-        switch (CLPAIR(xc, yc)) {
-        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_SNAN):
-        case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_SNAN):
-        case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_SNAN):
-        case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_SNAN):
-        case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_SNAN):
+        if (xc == IEEE754_CLASS_SNAN)
+                return ieee754sp_nanxcpt(x);
+        if (yc == IEEE754_CLASS_SNAN)
                 return ieee754sp_nanxcpt(y);
+        if (zc == IEEE754_CLASS_QNAN)
+                return z;
+        if (xc == IEEE754_CLASS_QNAN)
+                return x;
+        if (yc == IEEE754_CLASS_QNAN)
+                return y;
 
-        case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_SNAN):
-        case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_QNAN):
-        case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_ZERO):
-        case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_NORM):
-        case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_DNORM):
-        case CLPAIR(IEEE754_CLASS_SNAN, IEEE754_CLASS_INF):
-                return ieee754sp_nanxcpt(x);
+        if (zc == IEEE754_CLASS_DNORM)
+                SPDNORMZ;
+        /* ZERO z cases are handled separately below */
 
-        case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_QNAN):
-        case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_QNAN):
-        case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_QNAN):
-        case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_QNAN):
-                return y;
+        switch (CLPAIR(xc, yc)) {
 
-        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_QNAN):
-        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_ZERO):
-        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_NORM):
-        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_DNORM):
-        case CLPAIR(IEEE754_CLASS_QNAN, IEEE754_CLASS_INF):
-                return x;
 
         /*
          * Infinity handling
          */
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
-                if (zc == IEEE754_CLASS_QNAN)
-                        return z;
                 ieee754_setcx(IEEE754_INVALID_OPERATION);
                 return ieee754sp_indef();
 
@@ -101,9 +76,27 @@ static union ieee754sp _sp_maddf(union ieee754sp z, union ieee754sp x,
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
         case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
-                if (zc == IEEE754_CLASS_QNAN)
-                        return z;
-                return ieee754sp_inf(xs ^ ys);
+                if ((zc == IEEE754_CLASS_INF) &&
+                    ((!(flags & MADDF_NEGATE_PRODUCT) && (zs != (xs ^ ys))) ||
+                     ((flags & MADDF_NEGATE_PRODUCT) && (zs == (xs ^ ys))))) {
+                        /*
+                         * Cases of addition of infinities with opposite signs
+                         * or subtraction of infinities with same signs.
+                         */
+                        ieee754_setcx(IEEE754_INVALID_OPERATION);
+                        return ieee754sp_indef();
+                }
+                /*
+                 * z is here either not an infinity, or an infinity having the
+                 * same sign as product (x*y) (in case of MADDF.D instruction)
+                 * or product -(x*y) (in MSUBF.D case). The result must be an
+                 * infinity, and its sign is determined only by the value of
+                 * (flags & MADDF_NEGATE_PRODUCT) and the signs of x and y.
+                 */
+                if (flags & MADDF_NEGATE_PRODUCT)
+                        return ieee754sp_inf(1 ^ (xs ^ ys));
+                else
+                        return ieee754sp_inf(xs ^ ys);
 
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
         case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM):
@@ -112,32 +105,42 @@ static union ieee754sp _sp_maddf(union ieee754sp z, union ieee754sp x,
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
                 if (zc == IEEE754_CLASS_INF)
                         return ieee754sp_inf(zs);
-                /* Multiplication is 0 so just return z */
+                if (zc == IEEE754_CLASS_ZERO) {
+                        /* Handle cases +0 + (-0) and similar ones. */
+                        if ((!(flags & MADDF_NEGATE_PRODUCT)
+                                        && (zs == (xs ^ ys))) ||
+                            ((flags & MADDF_NEGATE_PRODUCT)
+                                        && (zs != (xs ^ ys))))
+                                /*
+                                 * Cases of addition of zeros of equal signs
+                                 * or subtraction of zeroes of opposite signs.
+                                 * The sign of the resulting zero is in any
+                                 * such case determined only by the sign of z.
+                                 */
+                                return z;
+
+                        return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD);
+                }
+                /* x*y is here 0, and z is not 0, so just return z */
                 return z;
 
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
                 SPDNORMX;
 
         case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM):
-                if (zc == IEEE754_CLASS_QNAN)
-                        return z;
-                else if (zc == IEEE754_CLASS_INF)
+                if (zc == IEEE754_CLASS_INF)
                         return ieee754sp_inf(zs);
                 SPDNORMY;
                 break;
 
         case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM):
-                if (zc == IEEE754_CLASS_QNAN)
-                        return z;
-                else if (zc == IEEE754_CLASS_INF)
+                if (zc == IEEE754_CLASS_INF)
                         return ieee754sp_inf(zs);
                 SPDNORMX;
                 break;
 
         case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM):
-                if (zc == IEEE754_CLASS_QNAN)
-                        return z;
-                else if (zc == IEEE754_CLASS_INF)
+                if (zc == IEEE754_CLASS_INF)
                         return ieee754sp_inf(zs);
                 /* fall through to real computations */
         }
@@ -158,111 +161,93 @@ static union ieee754sp _sp_maddf(union ieee754sp z, union ieee754sp x,
 
         re = xe + ye;
         rs = xs ^ ys;
-        if (flags & maddf_negate_product)
+        if (flags & MADDF_NEGATE_PRODUCT)
                 rs ^= 1;
 
-        /* shunt to top of word */
-        xm <<= 32 - (SP_FBITS + 1);
-        ym <<= 32 - (SP_FBITS + 1);
-
-        /*
-         * Multiply 32 bits xm, ym to give high 32 bits rm with stickness.
-         */
-        lxm = xm & 0xffff;
-        hxm = xm >> 16;
-        lym = ym & 0xffff;
-        hym = ym >> 16;
-
-        lrm = lxm * lym;        /* 16 * 16 => 32 */
-        hrm = hxm * hym;        /* 16 * 16 => 32 */
-
-        t = lxm * hym; /* 16 * 16 => 32 */
-        at = lrm + (t << 16);
-        hrm += at < lrm;
-        lrm = at;
-        hrm = hrm + (t >> 16);
+        /* Multiple 24 bit xm and ym to give 48 bit results */
+        rm64 = (uint64_t)xm * ym;
 
-        t = hxm * lym; /* 16 * 16 => 32 */
-        at = lrm + (t << 16);
-        hrm += at < lrm;
-        lrm = at;
-        hrm = hrm + (t >> 16);
+        /* Shunt to top of word */
+        rm64 = rm64 << 16;
 
-        rm = hrm | (lrm != 0);
-
-        /*
-         * Sticky shift down to normal rounding precision.
-         */
-        if ((int) rm < 0) {
-                rm = (rm >> (32 - (SP_FBITS + 1 + 3))) |
-                    ((rm << (SP_FBITS + 1 + 3)) != 0);
+        /* Put explicit bit at bit 62 if necessary */
+        if ((int64_t) rm64 < 0) {
+                rm64 = rm64 >> 1;
                 re++;
-        } else {
-                rm = (rm >> (32 - (SP_FBITS + 1 + 3 + 1))) |
-                     ((rm << (SP_FBITS + 1 + 3 + 1)) != 0);
         }
-        assert(rm & (SP_HIDDEN_BIT << 3));
-
-        if (zc == IEEE754_CLASS_ZERO)
-                return ieee754sp_format(rs, re, rm);
 
-        /* And now the addition */
+        assert(rm64 & (1 << 62));
 
-        assert(zm & SP_HIDDEN_BIT);
+        if (zc == IEEE754_CLASS_ZERO) {
+                /*
+                 * Move explicit bit from bit 62 to bit 26 since the
+                 * ieee754sp_format code expects the mantissa to be
+                 * 27 bits wide (24 + 3 rounding bits).
+                 */
+                rm = XSPSRS64(rm64, (62 - 26));
+                return ieee754sp_format(rs, re, rm);
+        }
 
-        /*
-         * Provide guard,round and stick bit space.
-         */
-        zm <<= 3;
+        /* Move explicit bit from bit 23 to bit 62 */
+        zm64 = (uint64_t)zm << (62 - 23);
+        assert(zm64 & (1 << 62));
 
+        /* Make the exponents the same */
         if (ze > re) {
                 /*
                  * Have to shift r fraction right to align.
                  */
                 s = ze - re;
-                rm = XSPSRS(rm, s);
+                rm64 = XSPSRS64(rm64, s);
                 re += s;
         } else if (re > ze) {
                 /*
                  * Have to shift z fraction right to align.
                  */
                 s = re - ze;
-                zm = XSPSRS(zm, s);
+                zm64 = XSPSRS64(zm64, s);
                 ze += s;
         }
         assert(ze == re);
         assert(ze <= SP_EMAX);
 
+        /* Do the addition */
         if (zs == rs) {
                 /*
-                 * Generate 28 bit result of adding two 27 bit numbers
-                 * leaving result in zm, zs and ze.
+                 * Generate 64 bit result by adding two 63 bit numbers
+                 * leaving result in zm64, zs and ze.
                  */
-                zm = zm + rm;
-
-                if (zm >> (SP_FBITS + 1 + 3)) { /* carry out */
-                        zm = XSPSRS1(zm);
+                zm64 = zm64 + rm64;
+                if ((int64_t)zm64 < 0) {        /* carry out */
+                        zm64 = XSPSRS1(zm64);
                         ze++;
                 }
         } else {
-                if (zm >= rm) {
-                        zm = zm - rm;
+                if (zm64 >= rm64) {
+                        zm64 = zm64 - rm64;
                 } else {
-                        zm = rm - zm;
+                        zm64 = rm64 - zm64;
                         zs = rs;
                 }
-                if (zm == 0)
+                if (zm64 == 0)
                         return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD);
 
                 /*
-                 * Normalize in extended single precision
+                 * Put explicit bit at bit 62 if necessary.
                  */
-                while ((zm >> (SP_MBITS + 3)) == 0) {
-                        zm <<= 1;
+                while ((zm64 >> 62) == 0) {
+                        zm64 <<= 1;
                         ze--;
                 }
-
         }
+
+        /*
+         * Move explicit bit from bit 62 to bit 26 since the
+         * ieee754sp_format code expects the mantissa to be
+         * 27 bits wide (24 + 3 rounding bits).
+         */
+        zm = XSPSRS64(zm64, (62 - 26));
+
         return ieee754sp_format(zs, ze, zm);
 }
 
@@ -275,5 +260,5 @@ union ieee754sp ieee754sp_maddf(union ieee754sp z, union ieee754sp x,
 union ieee754sp ieee754sp_msubf(union ieee754sp z, union ieee754sp x,
                                 union ieee754sp y)
 {
-        return _sp_maddf(z, x, y, maddf_negate_product);
+        return _sp_maddf(z, x, y, MADDF_NEGATE_PRODUCT);
 }
diff --git a/arch/mips/math-emu/sp_rint.c b/arch/mips/math-emu/sp_rint.c
new file mode 100644
index 000000000000..70765b17e196
--- /dev/null
+++ b/arch/mips/math-emu/sp_rint.c
@@ -0,0 +1,90 @@
+/* IEEE754 floating point arithmetic
+ * single precision
+ */
+/*
+ * MIPS floating point support
+ * Copyright (C) 1994-2000 Algorithmics Ltd.
+ * Copyright (C) 2017 Imagination Technologies, Ltd.
+ * Author: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program.
+ */
+
+#include "ieee754sp.h"
+
+union ieee754sp ieee754sp_rint(union ieee754sp x)
+{
+        union ieee754sp ret;
+        u32 residue;
+        int sticky;
+        int round;
+        int odd;
+
+        COMPXDP;                /* <-- DP needed for 64-bit mantissa tmp */
+
+        ieee754_clearcx();
+
+        EXPLODEXSP;
+        FLUSHXSP;
+
+        if (xc == IEEE754_CLASS_SNAN)
+                return ieee754sp_nanxcpt(x);
+
+        if ((xc == IEEE754_CLASS_QNAN) ||
+            (xc == IEEE754_CLASS_INF) ||
+            (xc == IEEE754_CLASS_ZERO))
+                return x;
+
+        if (xe >= SP_FBITS)
+                return x;
+
+        if (xe < -1) {
+                residue = xm;
+                round = 0;
+                sticky = residue != 0;
+                xm = 0;
+        } else {
+                residue = xm << (xe + 1);
+                residue <<= 31 - SP_FBITS;
+                round = (residue >> 31) != 0;
+                sticky = (residue << 1) != 0;
+                xm >>= SP_FBITS - xe;
+        }
+
+        odd = (xm & 0x1) != 0x0;
+
+        switch (ieee754_csr.rm) {
+        case FPU_CSR_RN:        /* toward nearest */
+                if (round && (sticky || odd))
+                        xm++;
+                break;
+        case FPU_CSR_RZ:        /* toward zero */
+                break;
+        case FPU_CSR_RU:        /* toward +infinity */
+                if ((round || sticky) && !xs)
+                        xm++;
+                break;
+        case FPU_CSR_RD:        /* toward -infinity */
+                if ((round || sticky) && xs)
+                        xm++;
+                break;
+        }
+
+        if (round || sticky)
+                ieee754_setcx(IEEE754_INEXACT);
+
+        ret = ieee754sp_flong(xm);
+        SPSIGN(ret) = xs;
+
+        return ret;
+}
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 81d6a15c93d0..6f534b209971 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -37,7 +37,7 @@
 #include <asm/cacheflush.h> /* for run_uncached() */
 #include <asm/traps.h>
 #include <asm/dma-coherence.h>
-#include <asm/mips-cm.h>
+#include <asm/mips-cps.h>
 
 /*
  * Bits describing what cache ops an SMP callback function may perform.
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 899e46279902..44ac64d51827 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -20,6 +20,7 @@
 #include <asm/processor.h>
 #include <asm/cpu.h>
 #include <asm/cpu-features.h>
+#include <asm/setup.h>
 
 /* Cache operations. */
 void (*flush_cache_all)(void);
@@ -44,7 +45,6 @@ void (*__flush_cache_vunmap)(void);
 
 void (*__flush_kernel_vmap_range)(unsigned long vaddr, int size);
 EXPORT_SYMBOL_GPL(__flush_kernel_vmap_range);
-void (*__invalidate_kernel_vmap_range)(unsigned long vaddr, int size);
 
 /* MIPS specific cache operations */
 void (*flush_cache_sigtramp)(unsigned long addr);
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 8e78251eccc2..c01bd20d0208 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -127,23 +127,6 @@ static gfp_t massage_gfp_flags(const struct device *dev, gfp_t gfp)
         return gfp | dma_flag;
 }
 
-static void *mips_dma_alloc_noncoherent(struct device *dev, size_t size,
-        dma_addr_t * dma_handle, gfp_t gfp)
-{
-        void *ret;
-
-        gfp = massage_gfp_flags(dev, gfp);
-
-        ret = (void *) __get_free_pages(gfp, get_order(size));
-
-        if (ret != NULL) {
-                memset(ret, 0, size);
-                *dma_handle = plat_map_dma_mem(dev, ret, size);
-        }
-
-        return ret;
-}
-
 static void *mips_dma_alloc_coherent(struct device *dev, size_t size,
         dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
 {
@@ -151,13 +134,6 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size,
         struct page *page = NULL;
         unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
 
-        /*
-         * XXX: seems like the coherent and non-coherent implementations could
-         * be consolidated.
-         */
-        if (attrs & DMA_ATTR_NON_CONSISTENT)
-                return mips_dma_alloc_noncoherent(dev, size, dma_handle, gfp);
-
         gfp = massage_gfp_flags(dev, gfp);
 
         if (IS_ENABLED(CONFIG_DMA_CMA) && gfpflags_allow_blocking(gfp))
@@ -172,7 +148,8 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size,
         ret = page_address(page);
         memset(ret, 0, size);
         *dma_handle = plat_map_dma_mem(dev, ret, size);
-        if (!plat_device_is_coherent(dev)) {
+        if (!(attrs & DMA_ATTR_NON_CONSISTENT) &&
+            !plat_device_is_coherent(dev)) {
                 dma_cache_wback_inv((unsigned long) ret, size);
                 ret = UNCAC_ADDR(ret);
         }
@@ -180,14 +157,6 @@ static void *mips_dma_alloc_coherent(struct device *dev, size_t size,
         return ret;
 }
 
-
-static void mips_dma_free_noncoherent(struct device *dev, size_t size,
-                void *vaddr, dma_addr_t dma_handle)
-{
-        plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
-        free_pages((unsigned long) vaddr, get_order(size));
-}
-
 static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
         dma_addr_t dma_handle, unsigned long attrs)
 {
@@ -195,14 +164,9 @@ static void mips_dma_free_coherent(struct device *dev, size_t size, void *vaddr,
         unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
         struct page *page = NULL;
 
-        if (attrs & DMA_ATTR_NON_CONSISTENT) {
-                mips_dma_free_noncoherent(dev, size, vaddr, dma_handle);
-                return;
-        }
-
         plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
 
-        if (!plat_device_is_coherent(dev))
+        if (!(attrs & DMA_ATTR_NON_CONSISTENT) && !plat_device_is_coherent(dev))
                 addr = CAC_ADDR(addr);
 
         page = virt_to_page((void *) addr);
@@ -409,12 +373,12 @@ static void mips_dma_sync_sg_for_device(struct device *dev,
         }
 }
 
-int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+static int mips_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 {
         return 0;
 }
 
-int mips_dma_supported(struct device *dev, u64 mask)
+static int mips_dma_supported(struct device *dev, u64 mask)
 {
         return plat_dma_supported(dev, mask);
 }
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 8ce2983a7015..5f6ea7d746de 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -31,6 +31,7 @@
 #include <linux/gfp.h>
 #include <linux/kcore.h>
 #include <linux/export.h>
+#include <linux/initrd.h>
 
 #include <asm/asm-offsets.h>
 #include <asm/bootinfo.h>
diff --git a/arch/mips/mm/mmap.c b/arch/mips/mm/mmap.c
index 28adeabe851f..33d3251ecd37 100644
--- a/arch/mips/mm/mmap.c
+++ b/arch/mips/mm/mmap.c
@@ -7,6 +7,7 @@
  *   written by Ralf Baechle <ralf@linux-mips.org>
  */
 #include <linux/compiler.h>
+#include <linux/elf-randomize.h>
 #include <linux/errno.h>
 #include <linux/mm.h>
 #include <linux/mman.h>
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index c909c3342729..acfb89273dad 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -14,7 +14,7 @@
 #include <asm/pgtable.h>
 #include <asm/mmu_context.h>
 #include <asm/r4kcache.h>
-#include <asm/mips-cm.h>
+#include <asm/mips-cps.h>
 
 /*
  * MIPS32/MIPS64 L2 cache handling
@@ -63,34 +63,25 @@ static void mips_sc_prefetch_enable(void)
          * prefetching for both code & data, for all ports.
          */
         pftctl = read_gcr_l2_pft_control();
-        if (pftctl & CM_GCR_L2_PFT_CONTROL_NPFT_MSK) {
-                pftctl &= ~CM_GCR_L2_PFT_CONTROL_PAGEMASK_MSK;
-                pftctl |= PAGE_MASK & CM_GCR_L2_PFT_CONTROL_PAGEMASK_MSK;
-                pftctl |= CM_GCR_L2_PFT_CONTROL_PFTEN_MSK;
+        if (pftctl & CM_GCR_L2_PFT_CONTROL_NPFT) {
+                pftctl &= ~CM_GCR_L2_PFT_CONTROL_PAGEMASK;
+                pftctl |= PAGE_MASK & CM_GCR_L2_PFT_CONTROL_PAGEMASK;
+                pftctl |= CM_GCR_L2_PFT_CONTROL_PFTEN;
                 write_gcr_l2_pft_control(pftctl);
 
-                pftctl = read_gcr_l2_pft_control_b();
-                pftctl |= CM_GCR_L2_PFT_CONTROL_B_PORTID_MSK;
-                pftctl |= CM_GCR_L2_PFT_CONTROL_B_CEN_MSK;
-                write_gcr_l2_pft_control_b(pftctl);
+                set_gcr_l2_pft_control_b(CM_GCR_L2_PFT_CONTROL_B_PORTID |
+                                         CM_GCR_L2_PFT_CONTROL_B_CEN);
         }
 }
 
 static void mips_sc_prefetch_disable(void)
 {
-        unsigned long pftctl;
-
         if (mips_cm_revision() < CM_REV_CM2_5)
                 return;
 
-        pftctl = read_gcr_l2_pft_control();
-        pftctl &= ~CM_GCR_L2_PFT_CONTROL_PFTEN_MSK;
-        write_gcr_l2_pft_control(pftctl);
-
-        pftctl = read_gcr_l2_pft_control_b();
-        pftctl &= ~CM_GCR_L2_PFT_CONTROL_B_PORTID_MSK;
-        pftctl &= ~CM_GCR_L2_PFT_CONTROL_B_CEN_MSK;
-        write_gcr_l2_pft_control_b(pftctl);
+        clear_gcr_l2_pft_control(CM_GCR_L2_PFT_CONTROL_PFTEN);
+        clear_gcr_l2_pft_control_b(CM_GCR_L2_PFT_CONTROL_B_PORTID |
+                                   CM_GCR_L2_PFT_CONTROL_B_CEN);
 }
 
 static bool mips_sc_prefetch_is_enabled(void)
@@ -101,9 +92,9 @@ static bool mips_sc_prefetch_is_enabled(void)
                 return false;
 
         pftctl = read_gcr_l2_pft_control();
-        if (!(pftctl & CM_GCR_L2_PFT_CONTROL_NPFT_MSK))
+        if (!(pftctl & CM_GCR_L2_PFT_CONTROL_NPFT))
                 return false;
-        return !!(pftctl & CM_GCR_L2_PFT_CONTROL_PFTEN_MSK);
+        return !!(pftctl & CM_GCR_L2_PFT_CONTROL_PFTEN);
 }
 
 static struct bcache_ops mips_sc_ops = {
@@ -160,21 +151,21 @@ static int __init mips_sc_probe_cm3(void)
         unsigned long cfg = read_gcr_l2_config();
         unsigned long sets, line_sz, assoc;
 
-        if (cfg & CM_GCR_L2_CONFIG_BYPASS_MSK)
+        if (cfg & CM_GCR_L2_CONFIG_BYPASS)
                 return 0;
 
-        sets = cfg & CM_GCR_L2_CONFIG_SET_SIZE_MSK;
-        sets >>= CM_GCR_L2_CONFIG_SET_SIZE_SHF;
+        sets = cfg & CM_GCR_L2_CONFIG_SET_SIZE;
+        sets >>= __ffs(CM_GCR_L2_CONFIG_SET_SIZE);
         if (sets)
                 c->scache.sets = 64 << sets;
 
-        line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE_MSK;
-        line_sz >>= CM_GCR_L2_CONFIG_LINE_SIZE_SHF;
+        line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE;
+        line_sz >>= __ffs(CM_GCR_L2_CONFIG_LINE_SIZE);
         if (line_sz)
                 c->scache.linesz = 2 << line_sz;
 
-        assoc = cfg & CM_GCR_L2_CONFIG_ASSOC_MSK;
-        assoc >>= CM_GCR_L2_CONFIG_ASSOC_SHF;
+        assoc = cfg & CM_GCR_L2_CONFIG_ASSOC;
+        assoc >>= __ffs(CM_GCR_L2_CONFIG_ASSOC);
         c->scache.ways = assoc + 1;
         c->scache.waysize = c->scache.sets * c->scache.linesz;
         c->scache.waybit = __ffs(c->scache.waysize);
diff --git a/arch/mips/mm/tlbex-fault.S b/arch/mips/mm/tlbex-fault.S
index 318855eb5f80..77db401fc620 100644
--- a/arch/mips/mm/tlbex-fault.S
+++ b/arch/mips/mm/tlbex-fault.S
@@ -12,14 +12,15 @@
 
         .macro tlb_do_page_fault, write
         NESTED(tlb_do_page_fault_\write, PT_SIZE, sp)
-        SAVE_ALL
+        .cfi_signal_frame
+        SAVE_ALL docfi=1
         MFC0    a2, CP0_BADVADDR
         KMODE
         move    a0, sp
         REG_S   a2, PT_BVADDR(sp)
         li      a1, \write
-        PTR_LA  ra, ret_from_exception
-        j       do_page_fault
+        jal     do_page_fault
+        j       ret_from_exception
         END(tlb_do_page_fault_\write)
         .endm
 
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 5aadc69c8ce3..79b9f2ad3ff5 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -2634,11 +2634,6 @@ void build_tlb_refill_handler(void)
 #endif
                 break;
 
-        case CPU_R6000:
-        case CPU_R6000A:
-                panic("No R6000 TLB refill handler yet");
-                break;
-
         case CPU_R8000:
                 panic("No R8000 TLB refill handler yet");
                 break;
diff --git a/arch/mips/mti-malta/malta-dtshim.c b/arch/mips/mti-malta/malta-dtshim.c
index c398582c316f..a6699c15277d 100644
--- a/arch/mips/mti-malta/malta-dtshim.c
+++ b/arch/mips/mti-malta/malta-dtshim.c
@@ -18,7 +18,7 @@
 #include <asm/fw/fw.h>
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/malta.h>
-#include <asm/mips-cm.h>
+#include <asm/mips-cps.h>
 #include <asm/page.h>
 
 #define ROCIT_REG_BASE                  0x1f403000
@@ -236,7 +236,7 @@ static void __init remove_gic(void *fdt)
 
         /* if we have a CM which reports a GIC is present, leave the DT alone */
         err = mips_cm_probe();
-        if (!err && (read_gcr_gic_status() & CM_GCR_GIC_STATUS_GICEX_MSK))
+        if (!err && (read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX))
                 return;
 
         if (malta_scon() == MIPS_REVISION_SCON_ROCIT) {
diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c
index 0f3b881a3190..009f2918b320 100644
--- a/arch/mips/mti-malta/malta-init.c
+++ b/arch/mips/mti-malta/malta-init.c
@@ -21,8 +21,7 @@
 #include <asm/smp-ops.h>
 #include <asm/traps.h>
 #include <asm/fw/fw.h>
-#include <asm/mips-cm.h>
-#include <asm/mips-cpc.h>
+#include <asm/mips-cps.h>
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/malta.h>
 
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index b0f9b188e833..a840e0c1642c 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -19,7 +19,6 @@
 #include <linux/smp.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
-#include <linux/irqchip/mips-gic.h>
 #include <linux/of_irq.h>
 #include <linux/kernel_stat.h>
 #include <linux/kernel.h>
@@ -29,9 +28,9 @@
 #include <asm/i8259.h>
 #include <asm/irq_cpu.h>
 #include <asm/irq_regs.h>
-#include <asm/mips-cm.h>
 #include <asm/mips-boards/malta.h>
 #include <asm/mips-boards/maltaint.h>
+#include <asm/mips-cps.h>
 #include <asm/gt64120.h>
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/msc01_pci.h>
@@ -215,7 +214,7 @@ void __init arch_init_irq(void)
                                         msc_nr_irqs);
         }
 
-        if (gic_present) {
+        if (mips_gic_present()) {
                 corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
         } else if (cpu_has_veic) {
                 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index a01d5debfcaf..de34adb76157 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -28,7 +28,7 @@
 
 #include <asm/fw/fw.h>
 #include <asm/mach-malta/malta-dtshim.h>
-#include <asm/mips-cm.h>
+#include <asm/mips-cps.h>
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/malta.h>
 #include <asm/mips-boards/maltaint.h>
@@ -128,7 +128,7 @@ static int __init plat_enable_iocoherency(void)
                                  BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
                         pr_info("Enabled Bonito IOBC coherency\n");
                 }
-        } else if (mips_cm_numiocu() != 0) {
+        } else if (mips_cps_numiocu(0) != 0) {
                 /* Nothing special needs to be done to enable coherency */
                 pr_info("CMP IOCU detected\n");
                 cfg = __raw_readl((u32 *)CKSEG1ADDR(ROCIT_CONFIG_GEN0));
diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index cea4ec909806..66c866740ff2 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -26,7 +26,6 @@
 #include <linux/sched.h>
 #include <linux/spinlock.h>
 #include <linux/interrupt.h>
-#include <linux/irqchip/mips-gic.h>
 #include <linux/timex.h>
 #include <linux/mc146818rtc.h>
 
@@ -40,6 +39,7 @@
 #include <asm/time.h>
 #include <asm/mc146818-time.h>
 #include <asm/msc01_ic.h>
+#include <asm/mips-cps.h>
 
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/maltaint.h>
@@ -85,8 +85,8 @@ static void __init estimate_frequencies(void)
 
         local_irq_save(flags);
 
-        if (gic_present)
-                gic_start_count();
+        if (mips_gic_present())
+                clear_gic_config(GIC_CONFIG_COUNTSTOP);
 
         /*
          * Read counters exactly on rising edge of update flag.
@@ -95,8 +95,8 @@ static void __init estimate_frequencies(void)
         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
         start = read_c0_count();
-        if (gic_present)
-                gicstart = gic_read_count();
+        if (mips_gic_present())
+                gicstart = read_gic_counter();
 
         /* Wait for falling edge before reading RTC. */
         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
@@ -105,8 +105,8 @@ static void __init estimate_frequencies(void)
         /* Read counters again exactly on rising edge of update flag. */
         while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
         count = read_c0_count();
-        if (gic_present)
-                giccount = gic_read_count();
+        if (mips_gic_present())
+                giccount = read_gic_counter();
 
         /* Wait for falling edge before reading RTC again. */
         while (CMOS_READ(RTC_REG_A) & RTC_UIP);
@@ -128,7 +128,7 @@ static void __init estimate_frequencies(void)
         count /= secs;
         mips_hpt_frequency = count;
 
-        if (gic_present) {
+        if (mips_gic_present()) {
                 giccount = div_u64(giccount - gicstart, secs);
                 gic_frequency = giccount;
         }
@@ -154,7 +154,7 @@ int get_c0_fdc_int(void)
 
         if (cpu_has_veic)
                 return -1;
-        else if (gic_present)
+        else if (mips_gic_present())
                 return gic_get_c0_fdc_int();
         else if (cp0_fdc_irq >= 0)
                 return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
@@ -167,7 +167,7 @@ int get_c0_perfcount_int(void)
         if (cpu_has_veic) {
                 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
                 mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
-        } else if (gic_present) {
+        } else if (mips_gic_present()) {
                 mips_cpu_perf_irq = gic_get_c0_perfcount_int();
         } else if (cp0_perfcount_irq >= 0) {
                 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
@@ -184,7 +184,7 @@ unsigned int get_c0_compare_int(void)
         if (cpu_has_veic) {
                 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
                 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
-        } else if (gic_present) {
+        } else if (mips_gic_present()) {
                 mips_cpu_timer_irq = gic_get_c0_compare_int();
         } else {
                 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
@@ -258,8 +258,7 @@ void __init plat_time_init(void)
         setup_pit_timer();
 #endif
 
-#ifdef CONFIG_MIPS_GIC
-        if (gic_present) {
+        if (mips_gic_present()) {
                 freq = freqround(gic_frequency, 5000);
                 printk("GIC frequency %d.%02d MHz\n", freq/1000000,
                        (freq%1000000)*100/1000000);
@@ -268,5 +267,4 @@ void __init plat_time_init(void)
                 timer_probe();
 #endif
         }
-#endif
 }
diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index bddf1ef553a4..39a300bd6cc2 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -122,7 +122,7 @@ static void nlm_init_secondary(void)
         int hwtid;
 
         hwtid = hard_smp_processor_id();
-        current_cpu_data.core = hwtid / NLM_THREADS_PER_CORE;
+        cpu_set_core(&current_cpu_data, hwtid / NLM_THREADS_PER_CORE);
         current_cpu_data.package = nlm_nodeid();
         nlm_percpu_init(hwtid);
         nlm_smp_irq_init(hwtid);
@@ -147,7 +147,7 @@ unsigned long nlm_next_gp;
 unsigned long nlm_next_sp;
 static cpumask_t phys_cpu_present_mask;
 
-void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
+int nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
 {
         uint64_t picbase;
         int hwtid;
@@ -161,6 +161,8 @@ void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
         /* barrier for sp/gp store above */
         __sync();
         nlm_pic_send_ipi(picbase, hwtid, 1, 1);  /* NMI */
+
+        return 0;
 }
 
 void __init nlm_smp_setup(void)
@@ -272,7 +274,7 @@ int nlm_wakeup_secondary_cpus(void)
         return 0;
 }
 
-struct plat_smp_ops nlm_smp_ops = {
+const struct plat_smp_ops nlm_smp_ops = {
         .send_ipi_single        = nlm_send_ipi_single,
         .send_ipi_mask          = nlm_send_ipi_mask,
         .init_secondary         = nlm_init_secondary,
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index c57da6f13929..c3e4c18ef8d4 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -38,9 +38,9 @@ static int perfcount_irq;
 #ifdef CONFIG_MIPS_MT_SMP
 static int cpu_has_mipsmt_pertccounters;
 #define WHAT            (MIPS_PERFCTRL_MT_EN_VPE | \
-                         M_PERFCTL_VPEID(cpu_data[smp_processor_id()].vpe_id))
+                         M_PERFCTL_VPEID(cpu_vpe_id(&current_cpu_data)))
 #define vpe_id()        (cpu_has_mipsmt_pertccounters ? \
-                        0 : cpu_data[smp_processor_id()].vpe_id)
+                        0 : cpu_vpe_id(&current_cpu_data))
 
 /*
  * The number of bits to shift to convert between counters per core and
diff --git a/arch/mips/paravirt/paravirt-smp.c b/arch/mips/paravirt/paravirt-smp.c
index 72eb1a56c645..107d9f90d668 100644
--- a/arch/mips/paravirt/paravirt-smp.c
+++ b/arch/mips/paravirt/paravirt-smp.c
@@ -100,11 +100,12 @@ static void paravirt_smp_finish(void)
         local_irq_enable();
 }
 
-static void paravirt_boot_secondary(int cpu, struct task_struct *idle)
+static int paravirt_boot_secondary(int cpu, struct task_struct *idle)
 {
         paravirt_smp_gp[cpu] = (unsigned long)task_thread_info(idle);
         smp_wmb();
         paravirt_smp_sp[cpu] = __KSTK_TOS(idle);
+        return 0;
 }
 
 static irqreturn_t paravirt_reched_interrupt(int irq, void *dev_id)
@@ -133,7 +134,7 @@ static void paravirt_prepare_cpus(unsigned int max_cpus)
         }
 }
 
-struct plat_smp_ops paravirt_smp_ops = {
+const struct plat_smp_ops paravirt_smp_ops = {
         .send_ipi_single        = paravirt_send_ipi_single,
         .send_ipi_mask          = paravirt_send_ipi_mask,
         .init_secondary         = paravirt_init_secondary,
diff --git a/arch/mips/paravirt/setup.c b/arch/mips/paravirt/setup.c
index cb8448b373a7..d2ffec1409a7 100644
--- a/arch/mips/paravirt/setup.c
+++ b/arch/mips/paravirt/setup.c
@@ -14,7 +14,7 @@
 #include <asm/smp-ops.h>
 #include <asm/time.h>
 
-extern struct plat_smp_ops paravirt_smp_ops;
+extern const struct plat_smp_ops paravirt_smp_ops;
 
 const char *get_system_type(void)
 {
diff --git a/arch/mips/pci/pci-legacy.c b/arch/mips/pci/pci-legacy.c
index fc7726088103..0c65c38e05d6 100644
--- a/arch/mips/pci/pci-legacy.c
+++ b/arch/mips/pci/pci-legacy.c
@@ -139,7 +139,7 @@ void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
         struct of_pci_range range;
         struct of_pci_range_parser parser;
 
-        pr_info("PCI host bridge %s ranges:\n", node->full_name);
+        pr_info("PCI host bridge %pOF ranges:\n", node);
         hose->of_node = node;
 
         if (of_pci_range_parser_init(&parser, node))
diff --git a/arch/mips/pci/pci-malta.c b/arch/mips/pci/pci-malta.c
index cfbbc3e3e914..88e625fb3a47 100644
--- a/arch/mips/pci/pci-malta.c
+++ b/arch/mips/pci/pci-malta.c
@@ -27,7 +27,7 @@
 #include <linux/init.h>
 
 #include <asm/gt64120.h>
-#include <asm/mips-cm.h>
+#include <asm/mips-cps.h>
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/bonito64.h>
 #include <asm/mips-boards/msc01_pci.h>
@@ -201,7 +201,7 @@ void __init mips_pcibios_init(void)
                 msc_mem_resource.start = start & mask;
                 msc_mem_resource.end = (start & mask) | ~mask;
                 msc_controller.mem_offset = (start & mask) - (map & mask);
-                if (mips_cm_numiocu()) {
+                if (mips_cps_numiocu(0)) {
                         write_gcr_reg0_base(start);
                         write_gcr_reg0_mask(mask |
                                             CM_GCR_REGn_MASK_CMTGT_IOCU0);
@@ -213,7 +213,7 @@ void __init mips_pcibios_init(void)
                 msc_io_resource.end = (map & mask) | ~mask;
                 msc_controller.io_offset = 0;
                 ioport_resource.end = ~mask;
-                if (mips_cm_numiocu()) {
+                if (mips_cps_numiocu(0)) {
                         write_gcr_reg1_base(start);
                         write_gcr_reg1_mask(mask |
                                             CM_GCR_REGn_MASK_CMTGT_IOCU0);
diff --git a/arch/mips/pci/pci-mt7620.c b/arch/mips/pci/pci-mt7620.c
index 628c5132b3d8..4e633c1e7ff3 100644
--- a/arch/mips/pci/pci-mt7620.c
+++ b/arch/mips/pci/pci-mt7620.c
@@ -291,7 +291,7 @@ static int mt7620_pci_probe(struct platform_device *pdev)
                                                           IORESOURCE_MEM, 1);
         u32 val = 0;
 
-        rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
+        rstpcie0 = devm_reset_control_get_exclusive(&pdev->dev, "pcie0");
         if (IS_ERR(rstpcie0))
                 return PTR_ERR(rstpcie0);
 
diff --git a/arch/mips/pci/pci-rt3883.c b/arch/mips/pci/pci-rt3883.c
index 3520e9b414e7..04f8ea953297 100644
--- a/arch/mips/pci/pci-rt3883.c
+++ b/arch/mips/pci/pci-rt3883.c
@@ -207,8 +207,7 @@ static int rt3883_pci_irq_init(struct device *dev,
 
         irq = irq_of_parse_and_map(rpc->intc_of_node, 0);
         if (irq == 0) {
-                dev_err(dev, "%s has no IRQ",
-                        of_node_full_name(rpc->intc_of_node));
+                dev_err(dev, "%pOF has no IRQ", rpc->intc_of_node);
                 return -EINVAL;
         }
 
@@ -438,8 +437,8 @@ static int rt3883_pci_probe(struct platform_device *pdev)
         }
 
         if (!rpc->intc_of_node) {
-                dev_err(dev, "%s has no %s child node",
-                        of_node_full_name(rpc->intc_of_node),
+                dev_err(dev, "%pOF has no %s child node",
+                        rpc->intc_of_node,
                         "interrupt controller");
                 return -EINVAL;
         }
@@ -454,8 +453,8 @@ static int rt3883_pci_probe(struct platform_device *pdev)
         }
 
         if (!rpc->pci_controller.of_node) {
-                dev_err(dev, "%s has no %s child node",
-                        of_node_full_name(rpc->intc_of_node),
+                dev_err(dev, "%pOF has no %s child node",
+                        rpc->intc_of_node,
                         "PCI host bridge");
                 err = -EINVAL;
                 goto err_put_intc_node;
diff --git a/arch/mips/pistachio/init.c b/arch/mips/pistachio/init.c
index 1c91cad7988f..0b06c953d293 100644
--- a/arch/mips/pistachio/init.c
+++ b/arch/mips/pistachio/init.c
@@ -19,8 +19,7 @@
 #include <asm/dma-coherence.h>
 #include <asm/fw/fw.h>
 #include <asm/mips-boards/generic.h>
-#include <asm/mips-cm.h>
-#include <asm/mips-cpc.h>
+#include <asm/mips-cps.h>
 #include <asm/prom.h>
 #include <asm/smp-ops.h>
 #include <asm/traps.h>
diff --git a/arch/mips/pistachio/irq.c b/arch/mips/pistachio/irq.c
index 0a6b24c24652..709a8219073a 100644
--- a/arch/mips/pistachio/irq.c
+++ b/arch/mips/pistachio/irq.c
@@ -10,7 +10,6 @@
 
 #include <linux/init.h>
 #include <linux/irqchip.h>
-#include <linux/irqchip/mips-gic.h>
 #include <linux/kernel.h>
 
 #include <asm/cpu-features.h>
diff --git a/arch/mips/pistachio/time.c b/arch/mips/pistachio/time.c
index 17a0f1dec05b..8a6af9b76202 100644
--- a/arch/mips/pistachio/time.c
+++ b/arch/mips/pistachio/time.c
@@ -12,9 +12,9 @@
 #include <linux/clk-provider.h>
 #include <linux/clocksource.h>
 #include <linux/init.h>
-#include <linux/irqchip/mips-gic.h>
 #include <linux/of.h>
 
+#include <asm/mips-cps.h>
 #include <asm/time.h>
 
 unsigned int get_c0_compare_int(void)
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index 710b04cf4851..b4627080b828 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -82,6 +82,16 @@ choice
                 depends on SOC_MT7620
                 select BUILTIN_DTB
 
+        config DTB_OMEGA2P
+                bool "Onion Omega2+"
+                depends on SOC_MT7620
+                select BUILTIN_DTB
+
+        config DTB_VOCORE2
+                bool "VoCore2"
+                depends on SOC_MT7620
+                select BUILTIN_DTB
+
 endchoice
 
 endif
diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c
index eb1c61917eb7..1b7df115eb60 100644
--- a/arch/mips/ralink/clk.c
+++ b/arch/mips/ralink/clk.c
@@ -53,6 +53,9 @@ EXPORT_SYMBOL_GPL(clk_disable);
 
 unsigned long clk_get_rate(struct clk *clk)
 {
+        if (!clk)
+                return 0;
+
         return clk->rate;
 }
 EXPORT_SYMBOL_GPL(clk_get_rate);
diff --git a/arch/mips/ralink/irq-gic.c b/arch/mips/ralink/irq-gic.c
index 2058280450b5..bda576f2cad8 100644
--- a/arch/mips/ralink/irq-gic.c
+++ b/arch/mips/ralink/irq-gic.c
@@ -11,7 +11,7 @@
 
 #include <linux/of.h>
 #include <linux/irqchip.h>
-#include <linux/irqchip/mips-gic.h>
+#include <asm/mips-cps.h>
 
 int get_c0_perfcount_int(void)
 {
diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c
index 0695c2d64e49..1b274742077d 100644
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
@@ -12,8 +12,7 @@
 
 #include <asm/mipsregs.h>
 #include <asm/smp-ops.h>
-#include <asm/mips-cm.h>
-#include <asm/mips-cpc.h>
+#include <asm/mips-cps.h>
 #include <asm/mach-ralink/ralink_regs.h>
 #include <asm/mach-ralink/mt7621.h>
 
@@ -199,7 +198,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
         mips_cm_probe();
         mips_cpc_probe();
 
-        if (mips_cm_numiocu()) {
+        if (mips_cps_numiocu(0)) {
                 /*
                  * mips_cm_probe() wipes out bootloader
                  * config for CM regions and we have to configure them
diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c
index 4cd47d23d81a..545446dfe7fa 100644
--- a/arch/mips/sgi-ip27/ip27-smp.c
+++ b/arch/mips/sgi-ip27/ip27-smp.c
@@ -195,7 +195,7 @@ static void ip27_smp_finish(void)
  * set sp to the kernel stack of the newly created idle process, gp to the proc
  * struct so that current_thread_info() will work.
  */
-static void ip27_boot_secondary(int cpu, struct task_struct *idle)
+static int ip27_boot_secondary(int cpu, struct task_struct *idle)
 {
         unsigned long gp = (unsigned long)task_thread_info(idle);
         unsigned long sp = __KSTK_TOS(idle);
@@ -203,6 +203,7 @@ static void ip27_boot_secondary(int cpu, struct task_struct *idle)
         LAUNCH_SLAVE(cputonasid(cpu), cputoslice(cpu),
                 (launch_proc_t)MAPPED_KERN_RW_TO_K0(smp_bootstrap),
                 0, (void *) sp, (void *) gp);
+        return 0;
 }
 
 static void __init ip27_smp_setup(void)
@@ -231,7 +232,7 @@ static void __init ip27_prepare_cpus(unsigned int max_cpus)
         /* We already did everything necessary earlier */
 }
 
-struct plat_smp_ops ip27_smp_ops = {
+const struct plat_smp_ops ip27_smp_ops = {
         .send_ipi_single        = ip27_send_ipi_single,
         .send_ipi_mask          = ip27_send_ipi_mask,
         .init_secondary         = ip27_init_secondary,
diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c
index d0e94ffcc1b8..90c9d1255ad7 100644
--- a/arch/mips/sibyte/bcm1480/smp.c
+++ b/arch/mips/sibyte/bcm1480/smp.c
@@ -117,7 +117,7 @@ static void bcm1480_smp_finish(void)
  * Setup the PC, SP, and GP of a secondary processor and start it
  * running!
  */
-static void bcm1480_boot_secondary(int cpu, struct task_struct *idle)
+static int bcm1480_boot_secondary(int cpu, struct task_struct *idle)
 {
         int retval;
 
@@ -126,6 +126,7 @@ static void bcm1480_boot_secondary(int cpu, struct task_struct *idle)
                                (unsigned long)task_thread_info(idle), 0);
         if (retval != 0)
                 printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval);
+        return retval;
 }
 
 /*
@@ -157,7 +158,7 @@ static void __init bcm1480_prepare_cpus(unsigned int max_cpus)
 {
 }
 
-struct plat_smp_ops bcm1480_smp_ops = {
+const struct plat_smp_ops bcm1480_smp_ops = {
         .send_ipi_single        = bcm1480_send_ipi_single,
         .send_ipi_mask          = bcm1480_send_ipi_mask,
         .init_secondary         = bcm1480_init_secondary,
diff --git a/arch/mips/sibyte/common/cfe.c b/arch/mips/sibyte/common/cfe.c
index c1a11a11db7f..115399202eab 100644
--- a/arch/mips/sibyte/common/cfe.c
+++ b/arch/mips/sibyte/common/cfe.c
@@ -229,8 +229,8 @@ static int __init initrd_setup(char *str)
 
 #endif
 
-extern struct plat_smp_ops sb_smp_ops;
-extern struct plat_smp_ops bcm1480_smp_ops;
+extern const struct plat_smp_ops sb_smp_ops;
+extern const struct plat_smp_ops bcm1480_smp_ops;
 
 /*
  * prom_init is called just after the cpu type is determined, from setup_arch()
diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c
index 0a4a2c3982d8..5baabca52f25 100644
--- a/arch/mips/sibyte/sb1250/smp.c
+++ b/arch/mips/sibyte/sb1250/smp.c
@@ -106,7 +106,7 @@ static void sb1250_smp_finish(void)
  * Setup the PC, SP, and GP of a secondary processor and start it
  * running!
  */
-static void sb1250_boot_secondary(int cpu, struct task_struct *idle)
+static int sb1250_boot_secondary(int cpu, struct task_struct *idle)
 {
         int retval;
 
@@ -115,6 +115,7 @@ static void sb1250_boot_secondary(int cpu, struct task_struct *idle)
                                (unsigned long)task_thread_info(idle), 0);
         if (retval != 0)
                 printk("cfe_start_cpu(%i) returned %i\n" , cpu, retval);
+        return retval;
 }
 
 /*
@@ -146,7 +147,7 @@ static void __init sb1250_prepare_cpus(unsigned int max_cpus)
 {
 }
 
-struct plat_smp_ops sb_smp_ops = {
+const struct plat_smp_ops sb_smp_ops = {
         .send_ipi_single        = sb1250_send_ipi_single,
         .send_ipi_mask          = sb1250_send_ipi_mask,
         .init_secondary         = sb1250_init_secondary,
diff --git a/arch/mips/tools/generic-board-config.sh b/arch/mips/tools/generic-board-config.sh
new file mode 100755
index 000000000000..5c4f93687039
--- /dev/null
+++ b/arch/mips/tools/generic-board-config.sh
@@ -0,0 +1,90 @@
+#!/bin/sh
+#
+# Copyright (C) 2017 Imagination Technologies
+# Author: Paul Burton <paul.burton@imgtec.com>
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the
+# Free Software Foundation;  either version 2 of the  License, or (at your
+# option) any later version.
+#
+# This script merges configuration fragments for boards supported by the
+# generic MIPS kernel. It checks each for requirements specified using
+# formatted comments, and then calls merge_config.sh to merge those
+# fragments which have no unmet requirements.
+#
+# An example of requirements in your board config fragment might be:
+#
+# # require CONFIG_CPU_MIPS32_R2=y
+# # require CONFIG_CPU_LITTLE_ENDIAN=y
+#
+# This would mean that your board is only included in kernels which are
+# configured for little endian MIPS32r2 CPUs, and not for example in kernels
+# configured for 64 bit or big endian systems.
+#
+
+srctree="$1"
+objtree="$2"
+ref_cfg="$3"
+cfg="$4"
+boards_origin="$5"
+shift 5
+
+cd "${srctree}"
+
+# Only print Skipping... lines if the user explicitly specified BOARDS=. In the
+# general case it only serves to obscure the useful output about what actually
+# was included.
+case ${boards_origin} in
+"command line")
+        print_skipped=1
+        ;;
+environment*)
+        print_skipped=1
+        ;;
+*)
+        print_skipped=0
+        ;;
+esac
+
+for board in $@; do
+        board_cfg="arch/mips/configs/generic/board-${board}.config"
+        if [ ! -f "${board_cfg}" ]; then
+                echo "WARNING: Board config '${board_cfg}' not found"
+                continue
+        fi
+
+        # For each line beginning with # require, cut out the field following
+        # it & search for that in the reference config file. If the requirement
+        # is not found then the subshell will exit with code 1, and we'll
+        # continue on to the next board.
+        grep -E '^# require ' "${board_cfg}" | \
+            cut -d' ' -f 3- | \
+            while read req; do
+                case ${req} in
+                *=y)
+                        # If we require something =y then we check that a line
+                        # containing it is present in the reference config.
+                        grep -Eq "^${req}\$" "${ref_cfg}" && continue
+                        ;;
+                *=n)
+                        # If we require something =n then we just invert that
+                        # check, considering the requirement met if there isn't
+                        # a line containing the value =y in the reference
+                        # config.
+                        grep -Eq "^${req/%=n/=y}\$" "${ref_cfg}" || continue
+                        ;;
+                *)
+                        echo "WARNING: Unhandled requirement '${req}'"
+                        ;;
+                esac
+
+                [ ${print_skipped} -eq 1 ] && echo "Skipping ${board_cfg}"
+                exit 1
+        done || continue
+
+        # Merge this board config fragment into our final config file
+        ./scripts/kconfig/merge_config.sh \
+                -m -O ${objtree} ${cfg} ${board_cfg} \
+                | grep -Ev '^(#|Using)'
+done
diff --git a/arch/mips/vdso/gettimeofday.c b/arch/mips/vdso/gettimeofday.c
index e2690d7ca4dd..e22b422f282c 100644
--- a/arch/mips/vdso/gettimeofday.c
+++ b/arch/mips/vdso/gettimeofday.c
@@ -11,12 +11,10 @@
 #include "vdso.h"
 
 #include <linux/compiler.h>
-#include <linux/irqchip/mips-gic.h>
 #include <linux/time.h>
 
 #include <asm/clocksource.h>
 #include <asm/io.h>
-#include <asm/mips-cm.h>
 #include <asm/unistd.h>
 #include <asm/vdso.h>
 
@@ -126,9 +124,9 @@ static __always_inline u64 read_gic_count(const union mips_vdso_data *data)
         u32 hi, hi2, lo;
 
         do {
-                hi = __raw_readl(gic + GIC_UMV_SH_COUNTER_63_32_OFS);
-                lo = __raw_readl(gic + GIC_UMV_SH_COUNTER_31_00_OFS);
-                hi2 = __raw_readl(gic + GIC_UMV_SH_COUNTER_63_32_OFS);
+                hi = __raw_readl(gic + sizeof(lo));
+                lo = __raw_readl(gic);
+                hi2 = __raw_readl(gic + sizeof(lo));
         } while (hi2 != hi);
 
         return (((u64)hi) << 32) + lo;
diff --git a/arch/mips/vdso/sigreturn.S b/arch/mips/vdso/sigreturn.S
index 715bf5993529..30c6219912ac 100644
--- a/arch/mips/vdso/sigreturn.S
+++ b/arch/mips/vdso/sigreturn.S
@@ -19,31 +19,21 @@
         .cfi_sections   .debug_frame
 
 LEAF(__vdso_rt_sigreturn)
-        .cfi_startproc
-        .frame  sp, 0, ra
-        .mask   0x00000000, 0
-        .fmask  0x00000000, 0
         .cfi_signal_frame
 
         li      v0, __NR_rt_sigreturn
         syscall
 
-        .cfi_endproc
         END(__vdso_rt_sigreturn)
 
 #if _MIPS_SIM == _MIPS_SIM_ABI32
 
 LEAF(__vdso_sigreturn)
-        .cfi_startproc
-        .frame  sp, 0, ra
-        .mask   0x00000000, 0
-        .fmask  0x00000000, 0
         .cfi_signal_frame
 
         li      v0, __NR_sigreturn
         syscall
 
-        .cfi_endproc
         END(__vdso_sigreturn)
 
 #endif
diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c
index 17b861ea2626..ae3167c28b12 100644
--- a/drivers/clocksource/mips-gic-timer.c
+++ b/drivers/clocksource/mips-gic-timer.c
@@ -10,25 +10,45 @@
 #include <linux/cpu.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
-#include <linux/irqchip/mips-gic.h>
 #include <linux/notifier.h>
 #include <linux/of_irq.h>
 #include <linux/percpu.h>
 #include <linux/smp.h>
 #include <linux/time.h>
+#include <asm/mips-cps.h>
 
 static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
 static int gic_timer_irq;
 static unsigned int gic_frequency;
 
+static u64 notrace gic_read_count(void)
+{
+        unsigned int hi, hi2, lo;
+
+        if (mips_cm_is64)
+                return read_gic_counter();
+
+        do {
+                hi = read_gic_counter_32h();
+                lo = read_gic_counter_32l();
+                hi2 = read_gic_counter_32h();
+        } while (hi2 != hi);
+
+        return (((u64) hi) << 32) + lo;
+}
+
 static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
 {
+        unsigned long flags;
         u64 cnt;
         int res;
 
         cnt = gic_read_count();
         cnt += (u64)delta;
-        gic_write_cpu_compare(cnt, cpumask_first(evt->cpumask));
+        local_irq_save(flags);
+        write_gic_vl_other(mips_cm_vp_id(cpumask_first(evt->cpumask)));
+        write_gic_vo_compare(cnt);
+        local_irq_restore(flags);
         res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
         return res;
 }
@@ -37,7 +57,7 @@ static irqreturn_t gic_compare_interrupt(int irq, void *dev_id)
 {
         struct clock_event_device *cd = dev_id;
 
-        gic_write_compare(gic_read_compare());
+        write_gic_vl_compare(read_gic_vl_compare());
         cd->event_handler(cd);
         return IRQ_HANDLED;
 }
@@ -139,10 +159,15 @@ static struct clocksource gic_clocksource = {
 
 static int __init __gic_clocksource_init(void)
 {
+        unsigned int count_width;
         int ret;
 
         /* Set clocksource mask. */
-        gic_clocksource.mask = CLOCKSOURCE_MASK(gic_get_count_width());
+        count_width = read_gic_config() & GIC_CONFIG_COUNTBITS;
+        count_width >>= __fls(GIC_CONFIG_COUNTBITS);
+        count_width *= 4;
+        count_width += 32;
+        gic_clocksource.mask = CLOCKSOURCE_MASK(count_width);
 
         /* Calculate a somewhat reasonable rating value. */
         gic_clocksource.rating = 200 + gic_frequency / 10000000;
@@ -159,7 +184,7 @@ static int __init gic_clocksource_of_init(struct device_node *node)
         struct clk *clk;
         int ret;
 
-        if (!gic_present || !node->parent ||
+        if (!mips_gic_present() || !node->parent ||
             !of_device_is_compatible(node->parent, "mti,gic")) {
                 pr_warn("No DT definition for the mips gic driver\n");
                 return -ENXIO;
@@ -197,7 +222,7 @@ static int __init gic_clocksource_of_init(struct device_node *node)
         }
 
         /* And finally start the counter */
-        gic_start_count();
+        clear_gic_config(GIC_CONFIG_COUNTSTOP);
 
         return 0;
 }
diff --git a/drivers/cpuidle/cpuidle-cps.c b/drivers/cpuidle/cpuidle-cps.c
index 12b9145913de..72b5e47286b4 100644
--- a/drivers/cpuidle/cpuidle-cps.c
+++ b/drivers/cpuidle/cpuidle-cps.c
@@ -37,7 +37,7 @@ static int cps_nc_enter(struct cpuidle_device *dev,
          * TODO: don't treat core 0 specially, just prevent the final core
          * TODO: remap interrupt affinity temporarily
          */
-        if (!cpu_data[dev->cpu].core && (index > STATE_NC_WAIT))
+        if (cpus_are_siblings(0, dev->cpu) && (index > STATE_NC_WAIT))
                 index = STATE_NC_WAIT;
 
         /* Select the appropriate cps_pm_state */
diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index 14461cbfab2f..66f97fde13d8 100644
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -101,7 +101,7 @@ static void mips_mt_send_ipi(struct irq_data *d, unsigned int cpu)
         local_irq_save(flags);
 
         /* We can only send IPIs to VPEs within the local core */
-        WARN_ON(cpu_data[cpu].core != current_cpu_data.core);
+        WARN_ON(!cpus_are_siblings(smp_processor_id(), cpu));
 
         vpflags = dvpe();
         settc(cpu_vpe_id(&cpu_data[cpu]));
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index b3a60da088db..6e52a88bbd9e 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -12,27 +12,38 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/irqchip.h>
-#include <linux/irqchip/mips-gic.h>
 #include <linux/of_address.h>
+#include <linux/percpu.h>
 #include <linux/sched.h>
 #include <linux/smp.h>
 
-#include <asm/mips-cm.h>
+#include <asm/mips-cps.h>
 #include <asm/setup.h>
 #include <asm/traps.h>
 
 #include <dt-bindings/interrupt-controller/mips-gic.h>
 
-unsigned int gic_present;
+#define GIC_MAX_INTRS           256
+#define GIC_MAX_LONGS           BITS_TO_LONGS(GIC_MAX_INTRS)
 
-struct gic_pcpu_mask {
-        DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS);
-};
+/* Add 2 to convert GIC CPU pin to core interrupt */
+#define GIC_CPU_PIN_OFFSET      2
+
+/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
+#define GIC_PIN_TO_VEC_OFFSET   1
+
+/* Convert between local/shared IRQ number and GIC HW IRQ number. */
+#define GIC_LOCAL_HWIRQ_BASE    0
+#define GIC_LOCAL_TO_HWIRQ(x)   (GIC_LOCAL_HWIRQ_BASE + (x))
+#define GIC_HWIRQ_TO_LOCAL(x)   ((x) - GIC_LOCAL_HWIRQ_BASE)
+#define GIC_SHARED_HWIRQ_BASE   GIC_NUM_LOCAL_INTRS
+#define GIC_SHARED_TO_HWIRQ(x)  (GIC_SHARED_HWIRQ_BASE + (x))
+#define GIC_HWIRQ_TO_SHARED(x)  ((x) - GIC_SHARED_HWIRQ_BASE)
+
+void __iomem *mips_gic_base;
 
-static unsigned long __gic_base_addr;
+DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);
 
-static void __iomem *gic_base;
-static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
 static DEFINE_SPINLOCK(gic_lock);
 static struct irq_domain *gic_irq_domain;
 static struct irq_domain *gic_ipi_domain;
@@ -44,202 +55,13 @@ static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
 DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS);
 DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS);
 
-static void __gic_irq_dispatch(void);
-
-static inline u32 gic_read32(unsigned int reg)
-{
-        return __raw_readl(gic_base + reg);
-}
-
-static inline u64 gic_read64(unsigned int reg)
-{
-        return __raw_readq(gic_base + reg);
-}
-
-static inline unsigned long gic_read(unsigned int reg)
-{
-        if (!mips_cm_is64)
-                return gic_read32(reg);
-        else
-                return gic_read64(reg);
-}
-
-static inline void gic_write32(unsigned int reg, u32 val)
-{
-        return __raw_writel(val, gic_base + reg);
-}
-
-static inline void gic_write64(unsigned int reg, u64 val)
-{
-        return __raw_writeq(val, gic_base + reg);
-}
-
-static inline void gic_write(unsigned int reg, unsigned long val)
-{
-        if (!mips_cm_is64)
-                return gic_write32(reg, (u32)val);
-        else
-                return gic_write64(reg, (u64)val);
-}
-
-static inline void gic_update_bits(unsigned int reg, unsigned long mask,
-                                   unsigned long val)
-{
-        unsigned long regval;
-
-        regval = gic_read(reg);
-        regval &= ~mask;
-        regval |= val;
-        gic_write(reg, regval);
-}
-
-static inline void gic_reset_mask(unsigned int intr)
-{
-        gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr),
-                  1ul << GIC_INTR_BIT(intr));
-}
-
-static inline void gic_set_mask(unsigned int intr)
-{
-        gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr),
-                  1ul << GIC_INTR_BIT(intr));
-}
-
-static inline void gic_set_polarity(unsigned int intr, unsigned int pol)
-{
-        gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) +
-                        GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr),
-                        (unsigned long)pol << GIC_INTR_BIT(intr));
-}
-
-static inline void gic_set_trigger(unsigned int intr, unsigned int trig)
-{
-        gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) +
-                        GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr),
-                        (unsigned long)trig << GIC_INTR_BIT(intr));
-}
-
-static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual)
-{
-        gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr),
-                        1ul << GIC_INTR_BIT(intr),
-                        (unsigned long)dual << GIC_INTR_BIT(intr));
-}
-
-static inline void gic_map_to_pin(unsigned int intr, unsigned int pin)
-{
-        gic_write32(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) +
-                    GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin);
-}
-
-static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe)
-{
-        gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) +
-                  GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe),
-                  GIC_SH_MAP_TO_VPE_REG_BIT(vpe));
-}
-
-#ifdef CONFIG_CLKSRC_MIPS_GIC
-u64 notrace gic_read_count(void)
-{
-        unsigned int hi, hi2, lo;
-
-        if (mips_cm_is64)
-                return (u64)gic_read(GIC_REG(SHARED, GIC_SH_COUNTER));
-
-        do {
-                hi = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
-                lo = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_31_00));
-                hi2 = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
-        } while (hi2 != hi);
-
-        return (((u64) hi) << 32) + lo;
-}
-
-unsigned int gic_get_count_width(void)
-{
-        unsigned int bits, config;
-
-        config = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
-        bits = 32 + 4 * ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >>
-                         GIC_SH_CONFIG_COUNTBITS_SHF);
-
-        return bits;
-}
-
-void notrace gic_write_compare(u64 cnt)
-{
-        if (mips_cm_is64) {
-                gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE), cnt);
-        } else {
-                gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
-                                        (int)(cnt >> 32));
-                gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
-                                        (int)(cnt & 0xffffffff));
-        }
-}
-
-void notrace gic_write_cpu_compare(u64 cnt, int cpu)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), mips_cm_vp_id(cpu));
-
-        if (mips_cm_is64) {
-                gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE), cnt);
-        } else {
-                gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI),
-                                        (int)(cnt >> 32));
-                gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO),
-                                        (int)(cnt & 0xffffffff));
-        }
-
-        local_irq_restore(flags);
-}
-
-u64 gic_read_compare(void)
-{
-        unsigned int hi, lo;
-
-        if (mips_cm_is64)
-                return (u64)gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE));
-
-        hi = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI));
-        lo = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO));
-
-        return (((u64) hi) << 32) + lo;
-}
-
-void gic_start_count(void)
+static void gic_clear_pcpu_masks(unsigned int intr)
 {
-        u32 gicconfig;
-
-        /* Start the counter */
-        gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
-        gicconfig &= ~(1 << GIC_SH_CONFIG_COUNTSTOP_SHF);
-        gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
-}
-
-void gic_stop_count(void)
-{
-        u32 gicconfig;
-
-        /* Stop the counter */
-        gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
-        gicconfig |= 1 << GIC_SH_CONFIG_COUNTSTOP_SHF;
-        gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
-}
-
-#endif
-
-unsigned gic_read_local_vp_id(void)
-{
-        unsigned long ident;
+        unsigned int i;
 
-        ident = gic_read(GIC_REG(VPE_LOCAL, GIC_VP_IDENT));
-        return ident & GIC_VP_IDENT_VCNUM_MSK;
+        /* Clear the interrupt's bit in all pcpu_masks */
+        for_each_possible_cpu(i)
+                clear_bit(intr, per_cpu_ptr(pcpu_masks, i));
 }
 
 static bool gic_local_irq_is_routable(int intr)
@@ -250,17 +72,17 @@ static bool gic_local_irq_is_routable(int intr)
         if (cpu_has_veic)
                 return true;
 
-        vpe_ctl = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_CTL));
+        vpe_ctl = read_gic_vl_ctl();
         switch (intr) {
         case GIC_LOCAL_INT_TIMER:
-                return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK;
+                return vpe_ctl & GIC_VX_CTL_TIMER_ROUTABLE;
         case GIC_LOCAL_INT_PERFCTR:
-                return vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK;
+                return vpe_ctl & GIC_VX_CTL_PERFCNT_ROUTABLE;
         case GIC_LOCAL_INT_FDC:
-                return vpe_ctl & GIC_VPE_CTL_FDC_RTBL_MSK;
+                return vpe_ctl & GIC_VX_CTL_FDC_ROUTABLE;
         case GIC_LOCAL_INT_SWINT0:
         case GIC_LOCAL_INT_SWINT1:
-                return vpe_ctl & GIC_VPE_CTL_SWINT_RTBL_MSK;
+                return vpe_ctl & GIC_VX_CTL_SWINT_ROUTABLE;
         default:
                 return true;
         }
@@ -272,15 +94,14 @@ static void gic_bind_eic_interrupt(int irq, int set)
         irq -= GIC_PIN_TO_VEC_OFFSET;
 
         /* Set irq to use shadow set */
-        gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_EIC_SHADOW_SET_BASE) +
-                  GIC_VPE_EIC_SS(irq), set);
+        write_gic_vl_eic_shadow_set(irq, set);
 }
 
 static void gic_send_ipi(struct irq_data *d, unsigned int cpu)
 {
         irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d));
 
-        gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_SET(hwirq));
+        write_gic_wedge(GIC_WEDGE_RW | hwirq);
 }
 
 int gic_get_c0_compare_int(void)
@@ -316,47 +137,22 @@ int gic_get_c0_fdc_int(void)
                                   GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
 }
 
-int gic_get_usm_range(struct resource *gic_usm_res)
-{
-        if (!gic_present)
-                return -1;
-
-        gic_usm_res->start = __gic_base_addr + USM_VISIBLE_SECTION_OFS;
-        gic_usm_res->end = gic_usm_res->start + (USM_VISIBLE_SECTION_SIZE - 1);
-
-        return 0;
-}
-
 static void gic_handle_shared_int(bool chained)
 {
-        unsigned int i, intr, virq, gic_reg_step = mips_cm_is64 ? 8 : 4;
+        unsigned int intr, virq;
         unsigned long *pcpu_mask;
-        unsigned long pending_reg, intrmask_reg;
         DECLARE_BITMAP(pending, GIC_MAX_INTRS);
-        DECLARE_BITMAP(intrmask, GIC_MAX_INTRS);
 
         /* Get per-cpu bitmaps */
-        pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
-
-        pending_reg = GIC_REG(SHARED, GIC_SH_PEND);
-        intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK);
-
-        for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) {
-                pending[i] = gic_read(pending_reg);
-                intrmask[i] = gic_read(intrmask_reg);
-                pending_reg += gic_reg_step;
-                intrmask_reg += gic_reg_step;
-
-                if (!IS_ENABLED(CONFIG_64BIT) || mips_cm_is64)
-                        continue;
+        pcpu_mask = this_cpu_ptr(pcpu_masks);
 
-                pending[i] |= (u64)gic_read(pending_reg) << 32;
-                intrmask[i] |= (u64)gic_read(intrmask_reg) << 32;
-                pending_reg += gic_reg_step;
-                intrmask_reg += gic_reg_step;
-        }
+        if (mips_cm_is64)
+                __ioread64_copy(pending, addr_gic_pend(),
+                                DIV_ROUND_UP(gic_shared_intrs, 64));
+        else
+                __ioread32_copy(pending, addr_gic_pend(),
+                                DIV_ROUND_UP(gic_shared_intrs, 32));
 
-        bitmap_and(pending, pending, intrmask, gic_shared_intrs);
         bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs);
 
         for_each_set_bit(intr, pending, gic_shared_intrs) {
@@ -371,19 +167,30 @@ static void gic_handle_shared_int(bool chained)
 
 static void gic_mask_irq(struct irq_data *d)
 {
-        gic_reset_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
+        unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
+
+        write_gic_rmask(BIT(intr));
+        gic_clear_pcpu_masks(intr);
 }
 
 static void gic_unmask_irq(struct irq_data *d)
 {
-        gic_set_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
+        struct cpumask *affinity = irq_data_get_affinity_mask(d);
+        unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
+        unsigned int cpu;
+
+        write_gic_smask(BIT(intr));
+
+        gic_clear_pcpu_masks(intr);
+        cpu = cpumask_first_and(affinity, cpu_online_mask);
+        set_bit(intr, per_cpu_ptr(pcpu_masks, cpu));
 }
 
 static void gic_ack_irq(struct irq_data *d)
 {
         unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
 
-        gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_CLR(irq));
+        write_gic_wedge(irq);
 }
 
 static int gic_set_type(struct irq_data *d, unsigned int type)
@@ -395,34 +202,34 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
         spin_lock_irqsave(&gic_lock, flags);
         switch (type & IRQ_TYPE_SENSE_MASK) {
         case IRQ_TYPE_EDGE_FALLING:
-                gic_set_polarity(irq, GIC_POL_NEG);
-                gic_set_trigger(irq, GIC_TRIG_EDGE);
-                gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
+                change_gic_pol(irq, GIC_POL_FALLING_EDGE);
+                change_gic_trig(irq, GIC_TRIG_EDGE);
+                change_gic_dual(irq, GIC_DUAL_SINGLE);
                 is_edge = true;
                 break;
         case IRQ_TYPE_EDGE_RISING:
-                gic_set_polarity(irq, GIC_POL_POS);
-                gic_set_trigger(irq, GIC_TRIG_EDGE);
-                gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
+                change_gic_pol(irq, GIC_POL_RISING_EDGE);
+                change_gic_trig(irq, GIC_TRIG_EDGE);
+                change_gic_dual(irq, GIC_DUAL_SINGLE);
                 is_edge = true;
                 break;
         case IRQ_TYPE_EDGE_BOTH:
                 /* polarity is irrelevant in this case */
-                gic_set_trigger(irq, GIC_TRIG_EDGE);
-                gic_set_dual_edge(irq, GIC_TRIG_DUAL_ENABLE);
+                change_gic_trig(irq, GIC_TRIG_EDGE);
+                change_gic_dual(irq, GIC_DUAL_DUAL);
                 is_edge = true;
                 break;
         case IRQ_TYPE_LEVEL_LOW:
-                gic_set_polarity(irq, GIC_POL_NEG);
-                gic_set_trigger(irq, GIC_TRIG_LEVEL);
-                gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
+                change_gic_pol(irq, GIC_POL_ACTIVE_LOW);
+                change_gic_trig(irq, GIC_TRIG_LEVEL);
+                change_gic_dual(irq, GIC_DUAL_SINGLE);
                 is_edge = false;
                 break;
         case IRQ_TYPE_LEVEL_HIGH:
         default:
-                gic_set_polarity(irq, GIC_POL_POS);
-                gic_set_trigger(irq, GIC_TRIG_LEVEL);
-                gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
+                change_gic_pol(irq, GIC_POL_ACTIVE_HIGH);
+                change_gic_trig(irq, GIC_TRIG_LEVEL);
+                change_gic_dual(irq, GIC_DUAL_SINGLE);
                 is_edge = false;
                 break;
         }
@@ -443,32 +250,28 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
                             bool force)
 {
         unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
-        cpumask_t       tmp = CPU_MASK_NONE;
-        unsigned long   flags;
-        int             i, cpu;
+        unsigned long flags;
+        unsigned int cpu;
 
-        cpumask_and(&tmp, cpumask, cpu_online_mask);
-        if (cpumask_empty(&tmp))
+        cpu = cpumask_first_and(cpumask, cpu_online_mask);
+        if (cpu >= NR_CPUS)
                 return -EINVAL;
 
-        cpu = cpumask_first(&tmp);
-
         /* Assumption : cpumask refers to a single CPU */
         spin_lock_irqsave(&gic_lock, flags);
 
         /* Re-route this IRQ */
-        gic_map_to_vpe(irq, mips_cm_vp_id(cpu));
+        write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu)));
 
         /* Update the pcpu_masks */
-        for (i = 0; i < min(gic_vpes, NR_CPUS); i++)
-                clear_bit(irq, pcpu_masks[i].pcpu_mask);
-        set_bit(irq, pcpu_masks[cpu].pcpu_mask);
+        gic_clear_pcpu_masks(irq);
+        if (read_gic_mask(irq))
+                set_bit(irq, per_cpu_ptr(pcpu_masks, cpu));
 
-        cpumask_copy(irq_data_get_affinity_mask(d), cpumask);
         irq_data_update_effective_affinity(d, cpumask_of(cpu));
         spin_unlock_irqrestore(&gic_lock, flags);
 
-        return IRQ_SET_MASK_OK_NOCOPY;
+        return IRQ_SET_MASK_OK;
 }
 #endif
 
@@ -499,8 +302,8 @@ static void gic_handle_local_int(bool chained)
         unsigned long pending, masked;
         unsigned int intr, virq;
 
-        pending = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_PEND));
-        masked = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_MASK));
+        pending = read_gic_vl_pend();
+        masked = read_gic_vl_mask();
 
         bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
 
@@ -518,14 +321,14 @@ static void gic_mask_local_irq(struct irq_data *d)
 {
         int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 
-        gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr);
+        write_gic_vl_rmask(BIT(intr));
 }
 
 static void gic_unmask_local_irq(struct irq_data *d)
 {
         int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
 
-        gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr);
+        write_gic_vl_smask(BIT(intr));
 }
 
 static struct irq_chip gic_local_irq_controller = {
@@ -542,9 +345,8 @@ static void gic_mask_local_irq_all_vpes(struct irq_data *d)
 
         spin_lock_irqsave(&gic_lock, flags);
         for (i = 0; i < gic_vpes; i++) {
-                gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR),
-                          mips_cm_vp_id(i));
-                gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr);
+                write_gic_vl_other(mips_cm_vp_id(i));
+                write_gic_vo_rmask(BIT(intr));
         }
         spin_unlock_irqrestore(&gic_lock, flags);
 }
@@ -557,9 +359,8 @@ static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
 
         spin_lock_irqsave(&gic_lock, flags);
         for (i = 0; i < gic_vpes; i++) {
-                gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR),
-                          mips_cm_vp_id(i));
-                gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr);
+                write_gic_vl_other(mips_cm_vp_id(i));
+                write_gic_vo_smask(BIT(intr));
         }
         spin_unlock_irqrestore(&gic_lock, flags);
 }
@@ -582,103 +383,50 @@ static void gic_irq_dispatch(struct irq_desc *desc)
         gic_handle_shared_int(true);
 }
 
-static void __init gic_basic_init(void)
-{
-        unsigned int i;
-
-        board_bind_eic_interrupt = &gic_bind_eic_interrupt;
-
-        /* Setup defaults */
-        for (i = 0; i < gic_shared_intrs; i++) {
-                gic_set_polarity(i, GIC_POL_POS);
-                gic_set_trigger(i, GIC_TRIG_LEVEL);
-                gic_reset_mask(i);
-        }
-
-        for (i = 0; i < gic_vpes; i++) {
-                unsigned int j;
-
-                gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR),
-                          mips_cm_vp_id(i));
-                for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) {
-                        if (!gic_local_irq_is_routable(j))
-                                continue;
-                        gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j);
-                }
-        }
-}
-
 static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq,
                                     irq_hw_number_t hw)
 {
         int intr = GIC_HWIRQ_TO_LOCAL(hw);
-        int ret = 0;
         int i;
         unsigned long flags;
+        u32 val;
 
         if (!gic_local_irq_is_routable(intr))
                 return -EPERM;
 
+        if (intr > GIC_LOCAL_INT_FDC) {
+                pr_err("Invalid local IRQ %d\n", intr);
+                return -EINVAL;
+        }
+
+        if (intr == GIC_LOCAL_INT_TIMER) {
+                /* CONFIG_MIPS_CMP workaround (see __gic_init) */
+                val = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin;
+        } else {
+                val = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin;
+        }
+
         spin_lock_irqsave(&gic_lock, flags);
         for (i = 0; i < gic_vpes; i++) {
-                u32 val = GIC_MAP_TO_PIN_MSK | gic_cpu_pin;
-
-                gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR),
-                          mips_cm_vp_id(i));
-
-                switch (intr) {
-                case GIC_LOCAL_INT_WD:
-                        gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val);
-                        break;
-                case GIC_LOCAL_INT_COMPARE:
-                        gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP),
-                                    val);
-                        break;
-                case GIC_LOCAL_INT_TIMER:
-                        /* CONFIG_MIPS_CMP workaround (see __gic_init) */
-                        val = GIC_MAP_TO_PIN_MSK | timer_cpu_pin;
-                        gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
-                                    val);
-                        break;
-                case GIC_LOCAL_INT_PERFCTR:
-                        gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
-                                    val);
-                        break;
-                case GIC_LOCAL_INT_SWINT0:
-                        gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP),
-                                    val);
-                        break;
-                case GIC_LOCAL_INT_SWINT1:
-                        gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP),
-                                    val);
-                        break;
-                case GIC_LOCAL_INT_FDC:
-                        gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val);
-                        break;
-                default:
-                        pr_err("Invalid local IRQ %d\n", intr);
-                        ret = -EINVAL;
-                        break;
-                }
+                write_gic_vl_other(mips_cm_vp_id(i));
+                write_gic_vo_map(intr, val);
         }
         spin_unlock_irqrestore(&gic_lock, flags);
 
-        return ret;
+        return 0;
 }
 
 static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
-                                     irq_hw_number_t hw, unsigned int vpe)
+                                     irq_hw_number_t hw, unsigned int cpu)
 {
         int intr = GIC_HWIRQ_TO_SHARED(hw);
         unsigned long flags;
-        int i;
 
         spin_lock_irqsave(&gic_lock, flags);
-        gic_map_to_pin(intr, gic_cpu_pin);
-        gic_map_to_vpe(intr, mips_cm_vp_id(vpe));
-        for (i = 0; i < min(gic_vpes, NR_CPUS); i++)
-                clear_bit(intr, pcpu_masks[i].pcpu_mask);
-        set_bit(intr, pcpu_masks[vpe].pcpu_mask);
+        write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin);
+        write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu)));
+        gic_clear_pcpu_masks(intr);
+        set_bit(intr, per_cpu_ptr(pcpu_masks, cpu));
         spin_unlock_irqrestore(&gic_lock, flags);
 
         return 0;
@@ -885,34 +633,69 @@ static const struct irq_domain_ops gic_ipi_domain_ops = {
         .match = gic_ipi_domain_match,
 };
 
-static void __init __gic_init(unsigned long gic_base_addr,
-                              unsigned long gic_addrspace_size,
-                              unsigned int cpu_vec, unsigned int irqbase,
-                              struct device_node *node)
+
+static int __init gic_of_init(struct device_node *node,
+                              struct device_node *parent)
 {
-        unsigned int gicconfig, cpu;
-        unsigned int v[2];
+        unsigned int cpu_vec, i, j, gicconfig, cpu, v[2];
+        unsigned long reserved;
+        phys_addr_t gic_base;
+        struct resource res;
+        size_t gic_len;
+
+        /* Find the first available CPU vector. */
+        i = 0;
+        reserved = (C_SW0 | C_SW1) >> __fls(C_SW0);
+        while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
+                                           i++, &cpu_vec))
+                reserved |= BIT(cpu_vec);
+
+        cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM));
+        if (cpu_vec == hweight_long(ST0_IM)) {
+                pr_err("No CPU vectors available for GIC\n");
+                return -ENODEV;
+        }
+
+        if (of_address_to_resource(node, 0, &res)) {
+                /*
+                 * Probe the CM for the GIC base address if not specified
+                 * in the device-tree.
+                 */
+                if (mips_cm_present()) {
+                        gic_base = read_gcr_gic_base() &
+                                ~CM_GCR_GIC_BASE_GICEN;
+                        gic_len = 0x20000;
+                } else {
+                        pr_err("Failed to get GIC memory range\n");
+                        return -ENODEV;
+                }
+        } else {
+                gic_base = res.start;
+                gic_len = resource_size(&res);
+        }
 
-        __gic_base_addr = gic_base_addr;
+        if (mips_cm_present()) {
+                write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN);
+                /* Ensure GIC region is enabled before trying to access it */
+                __sync();
+        }
 
-        gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size);
+        mips_gic_base = ioremap_nocache(gic_base, gic_len);
 
-        gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
-        gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
-                   GIC_SH_CONFIG_NUMINTRS_SHF;
-        gic_shared_intrs = ((gic_shared_intrs + 1) * 8);
+        gicconfig = read_gic_config();
+        gic_shared_intrs = gicconfig & GIC_CONFIG_NUMINTERRUPTS;
+        gic_shared_intrs >>= __fls(GIC_CONFIG_NUMINTERRUPTS);
+        gic_shared_intrs = (gic_shared_intrs + 1) * 8;
 
-        gic_vpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
-                  GIC_SH_CONFIG_NUMVPES_SHF;
+        gic_vpes = gicconfig & GIC_CONFIG_PVPS;
+        gic_vpes >>= __fls(GIC_CONFIG_PVPS);
         gic_vpes = gic_vpes + 1;
 
         if (cpu_has_veic) {
                 /* Set EIC mode for all VPEs */
                 for_each_present_cpu(cpu) {
-                        gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR),
-                                  mips_cm_vp_id(cpu));
-                        gic_write(GIC_REG(VPE_OTHER, GIC_VPE_CTL),
-                                  GIC_VPE_CTL_EIC_MODE_MSK);
+                        write_gic_vl_other(mips_cm_vp_id(cpu));
+                        write_gic_vo_ctl(GIC_VX_CTL_EIC);
                 }
 
                 /* Always use vector 1 in EIC mode */
@@ -937,9 +720,7 @@ static void __init __gic_init(unsigned long gic_base_addr,
                  */
                 if (IS_ENABLED(CONFIG_MIPS_CMP) &&
                     gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
-                        timer_cpu_pin = gic_read32(GIC_REG(VPE_LOCAL,
-                                                         GIC_VPE_TIMER_MAP)) &
-                                        GIC_MAP_MSK;
+                        timer_cpu_pin = read_gic_vl_timer_map() & GIC_MAP_PIN_MAP;
                         irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
                                                 GIC_CPU_PIN_OFFSET +
                                                 timer_cpu_pin,
@@ -950,17 +731,21 @@ static void __init __gic_init(unsigned long gic_base_addr,
         }
 
         gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +
-                                               gic_shared_intrs, irqbase,
+                                               gic_shared_intrs, 0,
                                                &gic_irq_domain_ops, NULL);
-        if (!gic_irq_domain)
-                panic("Failed to add GIC IRQ domain");
+        if (!gic_irq_domain) {
+                pr_err("Failed to add GIC IRQ domain");
+                return -ENXIO;
+        }
 
         gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
                                                   IRQ_DOMAIN_FLAG_IPI_PER_CPU,
                                                   GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
                                                   node, &gic_ipi_domain_ops, NULL);
-        if (!gic_ipi_domain)
-                panic("Failed to add GIC IPI domain");
+        if (!gic_ipi_domain) {
+                pr_err("Failed to add GIC IPI domain");
+                return -ENXIO;
+        }
 
         irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI);
 
@@ -975,64 +760,25 @@ static void __init __gic_init(unsigned long gic_base_addr,
         }
 
         bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS);
-        gic_basic_init();
-}
-
-void __init gic_init(unsigned long gic_base_addr,
-                     unsigned long gic_addrspace_size,
-                     unsigned int cpu_vec, unsigned int irqbase)
-{
-        __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL);
-}
 
-static int __init gic_of_init(struct device_node *node,
-                              struct device_node *parent)
-{
-        struct resource res;
-        unsigned int cpu_vec, i = 0, reserved = 0;
-        phys_addr_t gic_base;
-        size_t gic_len;
+        board_bind_eic_interrupt = &gic_bind_eic_interrupt;
 
-        /* Find the first available CPU vector. */
-        while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
-                                           i++, &cpu_vec))
-                reserved |= BIT(cpu_vec);
-        for (cpu_vec = 2; cpu_vec < 8; cpu_vec++) {
-                if (!(reserved & BIT(cpu_vec)))
-                        break;
-        }
-        if (cpu_vec == 8) {
-                pr_err("No CPU vectors available for GIC\n");
-                return -ENODEV;
+        /* Setup defaults */
+        for (i = 0; i < gic_shared_intrs; i++) {
+                change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
+                change_gic_trig(i, GIC_TRIG_LEVEL);
+                write_gic_rmask(BIT(i));
         }
 
-        if (of_address_to_resource(node, 0, &res)) {
-                /*
-                 * Probe the CM for the GIC base address if not specified
-                 * in the device-tree.
-                 */
-                if (mips_cm_present()) {
-                        gic_base = read_gcr_gic_base() &
-                                ~CM_GCR_GIC_BASE_GICEN_MSK;
-                        gic_len = 0x20000;
-                } else {
-                        pr_err("Failed to get GIC memory range\n");
-                        return -ENODEV;
+        for (i = 0; i < gic_vpes; i++) {
+                write_gic_vl_other(mips_cm_vp_id(i));
+                for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) {
+                        if (!gic_local_irq_is_routable(j))
+                                continue;
+                        write_gic_vo_rmask(BIT(j));
                 }
-        } else {
-                gic_base = res.start;
-                gic_len = resource_size(&res);
         }
 
-        if (mips_cm_present()) {
-                write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK);
-                /* Ensure GIC region is enabled before trying to access it */
-                __sync();
-        }
-        gic_present = true;
-
-        __gic_init(gic_base, gic_len, cpu_vec, 0, node);
-
         return 0;
 }
 IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init);
diff --git a/drivers/mtd/maps/lantiq-flash.c b/drivers/mtd/maps/lantiq-flash.c
index 3e33ab66eb24..77b1d8013295 100644
--- a/drivers/mtd/maps/lantiq-flash.c
+++ b/drivers/mtd/maps/lantiq-flash.c
@@ -114,12 +114,6 @@ ltq_mtd_probe(struct platform_device *pdev)
         struct cfi_private *cfi;
         int err;
 
-        if (of_machine_is_compatible("lantiq,falcon") &&
-                        (ltq_boot_select() != BS_FLASH)) {
-                dev_err(&pdev->dev, "invalid bootstrap options\n");
-                return -ENODEV;
-        }
-
         ltq_mtd = devm_kzalloc(&pdev->dev, sizeof(struct ltq_mtd), GFP_KERNEL);
         if (!ltq_mtd)
                 return -ENOMEM;
diff --git a/drivers/pcmcia/db1xxx_ss.c b/drivers/pcmcia/db1xxx_ss.c
index 944674ee3464..19e17829f515 100644
--- a/drivers/pcmcia/db1xxx_ss.c
+++ b/drivers/pcmcia/db1xxx_ss.c
@@ -131,22 +131,27 @@ static irqreturn_t db1000_pcmcia_stschgirq(int irq, void *data)
         return IRQ_HANDLED;
 }
 
+/* Db/Pb1200 have separate per-socket insertion and ejection
+ * interrupts which stay asserted as long as the card is
+ * inserted/missing.  The one which caused us to be called
+ * needs to be disabled and the other one enabled.
+ */
 static irqreturn_t db1200_pcmcia_cdirq(int irq, void *data)
 {
+        disable_irq_nosync(irq);
+        return IRQ_WAKE_THREAD;
+}
+
+static irqreturn_t db1200_pcmcia_cdirq_fn(int irq, void *data)
+{
         struct db1x_pcmcia_sock *sock = data;
 
-        /* Db/Pb1200 have separate per-socket insertion and ejection
-         * interrupts which stay asserted as long as the card is
-         * inserted/missing.  The one which caused us to be called
-         * needs to be disabled and the other one enabled.
-         */
-        if (irq == sock->insert_irq) {
-                disable_irq_nosync(sock->insert_irq);
+        /* Wait a bit for the signals to stop bouncing. */
+        msleep(100);
+        if (irq == sock->insert_irq)
                 enable_irq(sock->eject_irq);
-        } else {
-                disable_irq_nosync(sock->eject_irq);
+        else
                 enable_irq(sock->insert_irq);
-        }
 
         pcmcia_parse_events(&sock->socket, SS_DETECT);
 
@@ -172,13 +177,13 @@ static int db1x_pcmcia_setup_irqs(struct db1x_pcmcia_sock *sock)
          */
         if ((sock->board_type == BOARD_TYPE_DB1200) ||
             (sock->board_type == BOARD_TYPE_DB1300)) {
-                ret = request_irq(sock->insert_irq, db1200_pcmcia_cdirq,
-                                  0, "pcmcia_insert", sock);
+                ret = request_threaded_irq(sock->insert_irq, db1200_pcmcia_cdirq,
+                        db1200_pcmcia_cdirq_fn, 0, "pcmcia_insert", sock);
                 if (ret)
                         goto out1;
 
-                ret = request_irq(sock->eject_irq, db1200_pcmcia_cdirq,
-                                  0, "pcmcia_eject", sock);
+                ret = request_threaded_irq(sock->eject_irq, db1200_pcmcia_cdirq,
+                        db1200_pcmcia_cdirq_fn, 0, "pcmcia_eject", sock);
                 if (ret) {
                         free_irq(sock->insert_irq, sock);
                         goto out1;
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 441912c10b82..5c8d452e35e2 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -44,6 +44,7 @@ source "drivers/phy/allwinner/Kconfig"
 source "drivers/phy/amlogic/Kconfig"
 source "drivers/phy/broadcom/Kconfig"
 source "drivers/phy/hisilicon/Kconfig"
+source "drivers/phy/lantiq/Kconfig"
 source "drivers/phy/marvell/Kconfig"
 source "drivers/phy/mediatek/Kconfig"
 source "drivers/phy/motorola/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 06f3c500030d..3a52dcb09566 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -6,9 +6,9 @@ obj-$(CONFIG_GENERIC_PHY)		+= phy-core.o
 obj-$(CONFIG_PHY_LPC18XX_USB_OTG)       += phy-lpc18xx-usb-otg.o
 obj-$(CONFIG_PHY_XGENE)                 += phy-xgene.o
 obj-$(CONFIG_PHY_PISTACHIO_USB)         += phy-pistachio-usb.o
-
 obj-$(CONFIG_ARCH_SUNXI)                += allwinner/
 obj-$(CONFIG_ARCH_MESON)                += amlogic/
+obj-$(CONFIG_LANTIQ)                    += lantiq/
 obj-$(CONFIG_ARCH_MEDIATEK)             += mediatek/
 obj-$(CONFIG_ARCH_RENESAS)              += renesas/
 obj-$(CONFIG_ARCH_ROCKCHIP)             += rockchip/
diff --git a/drivers/phy/lantiq/Kconfig b/drivers/phy/lantiq/Kconfig
new file mode 100644
index 000000000000..326d88a6417d
--- /dev/null
+++ b/drivers/phy/lantiq/Kconfig
@@ -0,0 +1,9 @@
+#
+# Phy drivers for Lantiq / Intel platforms
+#
+config PHY_LANTIQ_RCU_USB2
+        tristate "Lantiq XWAY SoC RCU based USB PHY"
+        depends on OF && (SOC_TYPE_XWAY || COMPILE_TEST)
+        select GENERIC_PHY
+        help
+          Support for the USB PHY(s) on the Lantiq / Intel XWAY family SoCs.
diff --git a/drivers/phy/lantiq/Makefile b/drivers/phy/lantiq/Makefile
new file mode 100644
index 000000000000..f73eb56a5416
--- /dev/null
+++ b/drivers/phy/lantiq/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PHY_LANTIQ_RCU_USB2)       += phy-lantiq-rcu-usb2.o
diff --git a/drivers/phy/lantiq/phy-lantiq-rcu-usb2.c b/drivers/phy/lantiq/phy-lantiq-rcu-usb2.c
new file mode 100644
index 000000000000..986224fca9e9
--- /dev/null
+++ b/drivers/phy/lantiq/phy-lantiq-rcu-usb2.c
@@ -0,0 +1,254 @@
+/*
+ * Lantiq XWAY SoC RCU module based USB 1.1/2.0 PHY driver
+ *
+ * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+/* Transmitter HS Pre-Emphasis Enable */
+#define RCU_CFG1_TX_PEE         BIT(0)
+/* Disconnect Threshold */
+#define RCU_CFG1_DIS_THR_MASK   0x00038000
+#define RCU_CFG1_DIS_THR_SHIFT  15
+
+struct ltq_rcu_usb2_bits {
+        u8 hostmode;
+        u8 slave_endianness;
+        u8 host_endianness;
+        bool have_ana_cfg;
+};
+
+struct ltq_rcu_usb2_priv {
+        struct regmap                   *regmap;
+        unsigned int                    phy_reg_offset;
+        unsigned int                    ana_cfg1_reg_offset;
+        const struct ltq_rcu_usb2_bits  *reg_bits;
+        struct device                   *dev;
+        struct phy                      *phy;
+        struct clk                      *phy_gate_clk;
+        struct reset_control            *ctrl_reset;
+        struct reset_control            *phy_reset;
+};
+
+static const struct ltq_rcu_usb2_bits xway_rcu_usb2_reg_bits = {
+        .hostmode = 11,
+        .slave_endianness = 9,
+        .host_endianness = 10,
+        .have_ana_cfg = false,
+};
+
+static const struct ltq_rcu_usb2_bits xrx100_rcu_usb2_reg_bits = {
+        .hostmode = 11,
+        .slave_endianness = 17,
+        .host_endianness = 10,
+        .have_ana_cfg = false,
+};
+
+static const struct ltq_rcu_usb2_bits xrx200_rcu_usb2_reg_bits = {
+        .hostmode = 11,
+        .slave_endianness = 9,
+        .host_endianness = 10,
+        .have_ana_cfg = true,
+};
+
+static const struct of_device_id ltq_rcu_usb2_phy_of_match[] = {
+        {
+                .compatible = "lantiq,ase-usb2-phy",
+                .data = &xway_rcu_usb2_reg_bits,
+        },
+        {
+                .compatible = "lantiq,danube-usb2-phy",
+                .data = &xway_rcu_usb2_reg_bits,
+        },
+        {
+                .compatible = "lantiq,xrx100-usb2-phy",
+                .data = &xrx100_rcu_usb2_reg_bits,
+        },
+        {
+                .compatible = "lantiq,xrx200-usb2-phy",
+                .data = &xrx200_rcu_usb2_reg_bits,
+        },
+        {
+                .compatible = "lantiq,xrx300-usb2-phy",
+                .data = &xrx200_rcu_usb2_reg_bits,
+        },
+        { },
+};
+MODULE_DEVICE_TABLE(of, ltq_rcu_usb2_phy_of_match);
+
+static int ltq_rcu_usb2_phy_init(struct phy *phy)
+{
+        struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
+
+        if (priv->reg_bits->have_ana_cfg) {
+                regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
+                        RCU_CFG1_TX_PEE, RCU_CFG1_TX_PEE);
+                regmap_update_bits(priv->regmap, priv->ana_cfg1_reg_offset,
+                        RCU_CFG1_DIS_THR_MASK, 7 << RCU_CFG1_DIS_THR_SHIFT);
+        }
+
+        /* Configure core to host mode */
+        regmap_update_bits(priv->regmap, priv->phy_reg_offset,
+                           BIT(priv->reg_bits->hostmode), 0);
+
+        /* Select DMA endianness (Host-endian: big-endian) */
+        regmap_update_bits(priv->regmap, priv->phy_reg_offset,
+                BIT(priv->reg_bits->slave_endianness), 0);
+        regmap_update_bits(priv->regmap, priv->phy_reg_offset,
+                BIT(priv->reg_bits->host_endianness),
+                BIT(priv->reg_bits->host_endianness));
+
+        return 0;
+}
+
+static int ltq_rcu_usb2_phy_power_on(struct phy *phy)
+{
+        struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
+        struct device *dev = priv->dev;
+        int ret;
+
+        reset_control_deassert(priv->phy_reset);
+
+        ret = clk_prepare_enable(priv->phy_gate_clk);
+        if (ret)
+                dev_err(dev, "failed to enable PHY gate\n");
+
+        return ret;
+}
+
+static int ltq_rcu_usb2_phy_power_off(struct phy *phy)
+{
+        struct ltq_rcu_usb2_priv *priv = phy_get_drvdata(phy);
+
+        reset_control_assert(priv->phy_reset);
+
+        clk_disable_unprepare(priv->phy_gate_clk);
+
+        return 0;
+}
+
+static struct phy_ops ltq_rcu_usb2_phy_ops = {
+        .init           = ltq_rcu_usb2_phy_init,
+        .power_on       = ltq_rcu_usb2_phy_power_on,
+        .power_off      = ltq_rcu_usb2_phy_power_off,
+        .owner          = THIS_MODULE,
+};
+
+static int ltq_rcu_usb2_of_parse(struct ltq_rcu_usb2_priv *priv,
+                                 struct platform_device *pdev)
+{
+        struct device *dev = priv->dev;
+        const __be32 *offset;
+        int ret;
+
+        priv->reg_bits = of_device_get_match_data(dev);
+
+        priv->regmap = syscon_node_to_regmap(dev->of_node->parent);
+        if (IS_ERR(priv->regmap)) {
+                dev_err(dev, "Failed to lookup RCU regmap\n");
+                return PTR_ERR(priv->regmap);
+        }
+
+        offset = of_get_address(dev->of_node, 0, NULL, NULL);
+        if (!offset) {
+                dev_err(dev, "Failed to get RCU PHY reg offset\n");
+                return -ENOENT;
+        }
+        priv->phy_reg_offset = __be32_to_cpu(*offset);
+
+        if (priv->reg_bits->have_ana_cfg) {
+                offset = of_get_address(dev->of_node, 1, NULL, NULL);
+                if (!offset) {
+                        dev_err(dev, "Failed to get RCU ANA CFG1 reg offset\n");
+                        return -ENOENT;
+                }
+                priv->ana_cfg1_reg_offset = __be32_to_cpu(*offset);
+        }
+
+        priv->phy_gate_clk = devm_clk_get(dev, "phy");
+        if (IS_ERR(priv->phy_gate_clk)) {
+                dev_err(dev, "Unable to get USB phy gate clk\n");
+                return PTR_ERR(priv->phy_gate_clk);
+        }
+
+        priv->ctrl_reset = devm_reset_control_get_shared(dev, "ctrl");
+        if (IS_ERR(priv->ctrl_reset)) {
+                if (PTR_ERR(priv->ctrl_reset) != -EPROBE_DEFER)
+                        dev_err(dev, "failed to get 'ctrl' reset\n");
+                return PTR_ERR(priv->ctrl_reset);
+        }
+
+        priv->phy_reset = devm_reset_control_get_optional(dev, "phy");
+        if (IS_ERR(priv->phy_reset))
+                return PTR_ERR(priv->phy_reset);
+
+        return 0;
+}
+
+static int ltq_rcu_usb2_phy_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct ltq_rcu_usb2_priv *priv;
+        struct phy_provider *provider;
+        int ret;
+
+        priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+        if (!priv)
+                return -ENOMEM;
+
+        priv->dev = dev;
+
+        ret = ltq_rcu_usb2_of_parse(priv, pdev);
+        if (ret)
+                return ret;
+
+        /* Reset USB core through reset controller */
+        reset_control_deassert(priv->ctrl_reset);
+
+        reset_control_assert(priv->phy_reset);
+
+        priv->phy = devm_phy_create(dev, dev->of_node, &ltq_rcu_usb2_phy_ops);
+        if (IS_ERR(priv->phy)) {
+                dev_err(dev, "failed to create PHY\n");
+                return PTR_ERR(priv->phy);
+        }
+
+        phy_set_drvdata(priv->phy, priv);
+
+        provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+        if (IS_ERR(provider))
+                return PTR_ERR(provider);
+
+        dev_set_drvdata(priv->dev, priv);
+        return 0;
+}
+
+static struct platform_driver ltq_rcu_usb2_phy_driver = {
+        .probe  = ltq_rcu_usb2_phy_probe,
+        .driver = {
+                .name   = "lantiq-rcu-usb2-phy",
+                .of_match_table = ltq_rcu_usb2_phy_of_match,
+        }
+};
+module_platform_driver(ltq_rcu_usb2_phy_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Lantiq XWAY USB2 PHY driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 52d5251660b9..e0c393214264 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -47,6 +47,12 @@ config RESET_IMX7
         help
           This enables the reset controller driver for i.MX7 SoCs.
 
+config RESET_LANTIQ
+        bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
+        default SOC_TYPE_XWAY
+        help
+          This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
+
 config RESET_LPC18XX
         bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
         default ARCH_LPC18XX
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index b62783f50fe5..d368367110e5 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
 obj-$(CONFIG_RESET_HSDK_V1) += reset-hsdk-v1.o
 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
+obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
 obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
diff --git a/drivers/reset/reset-lantiq.c b/drivers/reset/reset-lantiq.c
new file mode 100644
index 000000000000..11a582e50d30
--- /dev/null
+++ b/drivers/reset/reset-lantiq.c
@@ -0,0 +1,212 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@phrozen.org>
+ *  Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
+ *  Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *  Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+
+#define LANTIQ_RCU_RESET_TIMEOUT        10000
+
+struct lantiq_rcu_reset_priv {
+        struct reset_controller_dev rcdev;
+        struct device *dev;
+        struct regmap *regmap;
+        u32 reset_offset;
+        u32 status_offset;
+};
+
+static struct lantiq_rcu_reset_priv *to_lantiq_rcu_reset_priv(
+        struct reset_controller_dev *rcdev)
+{
+        return container_of(rcdev, struct lantiq_rcu_reset_priv, rcdev);
+}
+
+static int lantiq_rcu_reset_status(struct reset_controller_dev *rcdev,
+                                   unsigned long id)
+{
+        struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev);
+        unsigned int status = (id >> 8) & 0x1f;
+        u32 val;
+        int ret;
+
+        ret = regmap_read(priv->regmap, priv->status_offset, &val);
+        if (ret)
+                return ret;
+
+        return !!(val & BIT(status));
+}
+
+static int lantiq_rcu_reset_status_timeout(struct reset_controller_dev *rcdev,
+                                           unsigned long id, bool assert)
+{
+        int ret;
+        int retry = LANTIQ_RCU_RESET_TIMEOUT;
+
+        do {
+                ret = lantiq_rcu_reset_status(rcdev, id);
+                if (ret < 0)
+                        return ret;
+                if (ret == assert)
+                        return 0;
+                usleep_range(20, 40);
+        } while (--retry);
+
+        return -ETIMEDOUT;
+}
+
+static int lantiq_rcu_reset_update(struct reset_controller_dev *rcdev,
+                                   unsigned long id, bool assert)
+{
+        struct lantiq_rcu_reset_priv *priv = to_lantiq_rcu_reset_priv(rcdev);
+        unsigned int set = id & 0x1f;
+        u32 val = assert ? BIT(set) : 0;
+        int ret;
+
+        ret = regmap_update_bits(priv->regmap, priv->reset_offset, BIT(set),
+                                 val);
+        if (ret) {
+                dev_err(priv->dev, "Failed to set reset bit %u\n", set);
+                return ret;
+        }
+
+
+        ret = lantiq_rcu_reset_status_timeout(rcdev, id, assert);
+        if (ret)
+                dev_err(priv->dev, "Failed to %s bit %u\n",
+                        assert ? "assert" : "deassert", set);
+
+        return ret;
+}
+
+static int lantiq_rcu_reset_assert(struct reset_controller_dev *rcdev,
+                             unsigned long id)
+{
+        return lantiq_rcu_reset_update(rcdev, id, true);
+}
+
+static int lantiq_rcu_reset_deassert(struct reset_controller_dev *rcdev,
+                               unsigned long id)
+{
+        return lantiq_rcu_reset_update(rcdev, id, false);
+}
+
+static int lantiq_rcu_reset_reset(struct reset_controller_dev *rcdev,
+                            unsigned long id)
+{
+        int ret;
+
+        ret = lantiq_rcu_reset_assert(rcdev, id);
+        if (ret)
+                return ret;
+
+        return lantiq_rcu_reset_deassert(rcdev, id);
+}
+
+static const struct reset_control_ops lantiq_rcu_reset_ops = {
+        .assert = lantiq_rcu_reset_assert,
+        .deassert = lantiq_rcu_reset_deassert,
+        .status = lantiq_rcu_reset_status,
+        .reset  = lantiq_rcu_reset_reset,
+};
+
+static int lantiq_rcu_reset_of_parse(struct platform_device *pdev,
+                               struct lantiq_rcu_reset_priv *priv)
+{
+        struct device *dev = &pdev->dev;
+        const __be32 *offset;
+
+        priv->regmap = syscon_node_to_regmap(dev->of_node->parent);
+        if (IS_ERR(priv->regmap)) {
+                dev_err(&pdev->dev, "Failed to lookup RCU regmap\n");
+                return PTR_ERR(priv->regmap);
+        }
+
+        offset = of_get_address(dev->of_node, 0, NULL, NULL);
+        if (!offset) {
+                dev_err(&pdev->dev, "Failed to get RCU reset offset\n");
+                return -ENOENT;
+        }
+        priv->reset_offset = __be32_to_cpu(*offset);
+
+        offset = of_get_address(dev->of_node, 1, NULL, NULL);
+        if (!offset) {
+                dev_err(&pdev->dev, "Failed to get RCU status offset\n");
+                return -ENOENT;
+        }
+        priv->status_offset = __be32_to_cpu(*offset);
+
+        return 0;
+}
+
+static int lantiq_rcu_reset_xlate(struct reset_controller_dev *rcdev,
+                                  const struct of_phandle_args *reset_spec)
+{
+        unsigned int status, set;
+
+        set = reset_spec->args[0];
+        status = reset_spec->args[1];
+
+        if (set >= rcdev->nr_resets || status >= rcdev->nr_resets)
+                return -EINVAL;
+
+        return (status << 8) | set;
+}
+
+static int lantiq_rcu_reset_probe(struct platform_device *pdev)
+{
+        struct lantiq_rcu_reset_priv *priv;
+        int err;
+
+        priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+        if (!priv)
+                return -ENOMEM;
+
+        priv->dev = &pdev->dev;
+        platform_set_drvdata(pdev, priv);
+
+        err = lantiq_rcu_reset_of_parse(pdev, priv);
+        if (err)
+                return err;
+
+        priv->rcdev.ops = &lantiq_rcu_reset_ops;
+        priv->rcdev.owner = THIS_MODULE;
+        priv->rcdev.of_node = pdev->dev.of_node;
+        priv->rcdev.nr_resets = 32;
+        priv->rcdev.of_xlate = lantiq_rcu_reset_xlate;
+        priv->rcdev.of_reset_n_cells = 2;
+
+        return reset_controller_register(&priv->rcdev);
+}
+
+static const struct of_device_id lantiq_rcu_reset_dt_ids[] = {
+        { .compatible = "lantiq,danube-reset", },
+        { .compatible = "lantiq,xrx200-reset", },
+        { },
+};
+MODULE_DEVICE_TABLE(of, lantiq_rcu_reset_dt_ids);
+
+static struct platform_driver lantiq_rcu_reset_driver = {
+        .probe  = lantiq_rcu_reset_probe,
+        .driver = {
+                .name           = "lantiq-reset",
+                .of_match_table = lantiq_rcu_reset_dt_ids,
+        },
+};
+module_platform_driver(lantiq_rcu_reset_driver);
+
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Lantiq XWAY RCU Reset Controller Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 280a6a91a9e2..2fcaff864584 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_ARCH_DOVE)		+= dove/
 obj-$(CONFIG_MACH_DOVE)         += dove/
 obj-y                           += fsl/
 obj-$(CONFIG_ARCH_MXC)          += imx/
+obj-$(CONFIG_SOC_XWAY)          += lantiq/
 obj-$(CONFIG_ARCH_MEDIATEK)     += mediatek/
 obj-$(CONFIG_ARCH_MESON)        += amlogic/
 obj-$(CONFIG_ARCH_QCOM)         += qcom/
diff --git a/drivers/soc/lantiq/Makefile b/drivers/soc/lantiq/Makefile
new file mode 100644
index 000000000000..be9e866d53e5
--- /dev/null
+++ b/drivers/soc/lantiq/Makefile
@@ -0,0 +1,2 @@
+obj-y                           += fpi-bus.o
+obj-$(CONFIG_XRX200_PHY_FW)     += gphy.o
diff --git a/drivers/soc/lantiq/fpi-bus.c b/drivers/soc/lantiq/fpi-bus.c
new file mode 100644
index 000000000000..a671c9984c4c
--- /dev/null
+++ b/drivers/soc/lantiq/fpi-bus.c
@@ -0,0 +1,87 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2011-2015 John Crispin <blogic@phrozen.org>
+ *  Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *  Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
+ */
+
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/regmap.h>
+
+#include <lantiq_soc.h>
+
+#define XBAR_ALWAYS_LAST        0x430
+#define XBAR_FPI_BURST_EN       BIT(1)
+#define XBAR_AHB_BURST_EN       BIT(2)
+
+#define RCU_VR9_BE_AHB1S        0x00000008
+
+static int ltq_fpi_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct device_node *np = dev->of_node;
+        struct resource *res_xbar;
+        struct regmap *rcu_regmap;
+        void __iomem *xbar_membase;
+        u32 rcu_ahb_endianness_reg_offset;
+        int ret;
+
+        res_xbar = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        xbar_membase = devm_ioremap_resource(dev, res_xbar);
+        if (IS_ERR(xbar_membase))
+                return PTR_ERR(xbar_membase);
+
+        /* RCU configuration is optional */
+        rcu_regmap = syscon_regmap_lookup_by_phandle(np, "lantiq,rcu");
+        if (IS_ERR(rcu_regmap))
+                return PTR_ERR(rcu_regmap);
+
+        ret = device_property_read_u32(dev, "lantiq,offset-endianness",
+                                       &rcu_ahb_endianness_reg_offset);
+        if (ret) {
+                dev_err(&pdev->dev, "Failed to get RCU reg offset\n");
+                return ret;
+        }
+
+        ret = regmap_update_bits(rcu_regmap, rcu_ahb_endianness_reg_offset,
+                                 RCU_VR9_BE_AHB1S, RCU_VR9_BE_AHB1S);
+        if (ret) {
+                dev_warn(&pdev->dev,
+                         "Failed to configure RCU AHB endianness\n");
+                return ret;
+        }
+
+        /* disable fpi burst */
+        ltq_w32_mask(XBAR_FPI_BURST_EN, 0, xbar_membase + XBAR_ALWAYS_LAST);
+
+        return of_platform_populate(dev->of_node, NULL, NULL, dev);
+}
+
+static const struct of_device_id ltq_fpi_match[] = {
+        { .compatible = "lantiq,xrx200-fpi" },
+        {},
+};
+MODULE_DEVICE_TABLE(of, ltq_fpi_match);
+
+static struct platform_driver ltq_fpi_driver = {
+        .probe = ltq_fpi_probe,
+        .driver = {
+                .name = "fpi-xway",
+                .of_match_table = ltq_fpi_match,
+        },
+};
+
+module_platform_driver(ltq_fpi_driver);
+
+MODULE_DESCRIPTION("Lantiq FPI bus driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/soc/lantiq/gphy.c b/drivers/soc/lantiq/gphy.c
new file mode 100644
index 000000000000..8d8659463b3e
--- /dev/null
+++ b/drivers/soc/lantiq/gphy.c
@@ -0,0 +1,260 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2012 John Crispin <blogic@phrozen.org>
+ *  Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *  Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/firmware.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/reboot.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/property.h>
+#include <dt-bindings/mips/lantiq_rcu_gphy.h>
+
+#include <lantiq_soc.h>
+
+#define XRX200_GPHY_FW_ALIGN    (16 * 1024)
+
+struct xway_gphy_priv {
+        struct clk *gphy_clk_gate;
+        struct reset_control *gphy_reset;
+        struct reset_control *gphy_reset2;
+        struct notifier_block gphy_reboot_nb;
+        void __iomem *membase;
+        char *fw_name;
+};
+
+struct xway_gphy_match_data {
+        char *fe_firmware_name;
+        char *ge_firmware_name;
+};
+
+static const struct xway_gphy_match_data xrx200a1x_gphy_data = {
+        .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin",
+        .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin",
+};
+
+static const struct xway_gphy_match_data xrx200a2x_gphy_data = {
+        .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin",
+        .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin",
+};
+
+static const struct xway_gphy_match_data xrx300_gphy_data = {
+        .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin",
+        .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin",
+};
+
+static const struct of_device_id xway_gphy_match[] = {
+        { .compatible = "lantiq,xrx200a1x-gphy", .data = &xrx200a1x_gphy_data },
+        { .compatible = "lantiq,xrx200a2x-gphy", .data = &xrx200a2x_gphy_data },
+        { .compatible = "lantiq,xrx300-gphy", .data = &xrx300_gphy_data },
+        { .compatible = "lantiq,xrx330-gphy", .data = &xrx300_gphy_data },
+        {},
+};
+MODULE_DEVICE_TABLE(of, xway_gphy_match);
+
+static struct xway_gphy_priv *to_xway_gphy_priv(struct notifier_block *nb)
+{
+        return container_of(nb, struct xway_gphy_priv, gphy_reboot_nb);
+}
+
+static int xway_gphy_reboot_notify(struct notifier_block *reboot_nb,
+                                   unsigned long code, void *unused)
+{
+        struct xway_gphy_priv *priv = to_xway_gphy_priv(reboot_nb);
+
+        if (priv) {
+                reset_control_assert(priv->gphy_reset);
+                reset_control_assert(priv->gphy_reset2);
+        }
+
+        return NOTIFY_DONE;
+}
+
+static int xway_gphy_load(struct device *dev, struct xway_gphy_priv *priv,
+                          dma_addr_t *dev_addr)
+{
+        const struct firmware *fw;
+        void *fw_addr;
+        dma_addr_t dma_addr;
+        size_t size;
+        int ret;
+
+        ret = request_firmware(&fw, priv->fw_name, dev);
+        if (ret) {
+                dev_err(dev, "failed to load firmware: %s, error: %i\n",
+                        priv->fw_name, ret);
+                return ret;
+        }
+
+        /*
+         * GPHY cores need the firmware code in a persistent and contiguous
+         * memory area with a 16 kB boundary aligned start address.
+         */
+        size = fw->size + XRX200_GPHY_FW_ALIGN;
+
+        fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL);
+        if (fw_addr) {
+                fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN);
+                *dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN);
+                memcpy(fw_addr, fw->data, fw->size);
+        } else {
+                dev_err(dev, "failed to alloc firmware memory\n");
+                ret = -ENOMEM;
+        }
+
+        release_firmware(fw);
+
+        return ret;
+}
+
+static int xway_gphy_of_probe(struct platform_device *pdev,
+                              struct xway_gphy_priv *priv)
+{
+        struct device *dev = &pdev->dev;
+        const struct xway_gphy_match_data *gphy_fw_name_cfg;
+        u32 gphy_mode;
+        int ret;
+        struct resource *res_gphy;
+
+        gphy_fw_name_cfg = of_device_get_match_data(dev);
+
+        priv->gphy_clk_gate = devm_clk_get(dev, NULL);
+        if (IS_ERR(priv->gphy_clk_gate)) {
+                dev_err(dev, "Failed to lookup gate clock\n");
+                return PTR_ERR(priv->gphy_clk_gate);
+        }
+
+        res_gphy = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        priv->membase = devm_ioremap_resource(dev, res_gphy);
+        if (IS_ERR(priv->membase))
+                return PTR_ERR(priv->membase);
+
+        priv->gphy_reset = devm_reset_control_get(dev, "gphy");
+        if (IS_ERR(priv->gphy_reset)) {
+                if (PTR_ERR(priv->gphy_reset) != -EPROBE_DEFER)
+                        dev_err(dev, "Failed to lookup gphy reset\n");
+                return PTR_ERR(priv->gphy_reset);
+        }
+
+        priv->gphy_reset2 = devm_reset_control_get_optional(dev, "gphy2");
+        if (IS_ERR(priv->gphy_reset2))
+                return PTR_ERR(priv->gphy_reset2);
+
+        ret = device_property_read_u32(dev, "lantiq,gphy-mode", &gphy_mode);
+        /* Default to GE mode */
+        if (ret)
+                gphy_mode = GPHY_MODE_GE;
+
+        switch (gphy_mode) {
+        case GPHY_MODE_FE:
+                priv->fw_name = gphy_fw_name_cfg->fe_firmware_name;
+                break;
+        case GPHY_MODE_GE:
+                priv->fw_name = gphy_fw_name_cfg->ge_firmware_name;
+                break;
+        default:
+                dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode);
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int xway_gphy_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct xway_gphy_priv *priv;
+        dma_addr_t fw_addr = 0;
+        int ret;
+
+        priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+        if (!priv)
+                return -ENOMEM;
+
+        ret = xway_gphy_of_probe(pdev, priv);
+        if (ret)
+                return ret;
+
+        ret = clk_prepare_enable(priv->gphy_clk_gate);
+        if (ret)
+                return ret;
+
+        ret = xway_gphy_load(dev, priv, &fw_addr);
+        if (ret) {
+                clk_disable_unprepare(priv->gphy_clk_gate);
+                return ret;
+        }
+
+        reset_control_assert(priv->gphy_reset);
+        reset_control_assert(priv->gphy_reset2);
+
+        iowrite32be(fw_addr, priv->membase);
+
+        reset_control_deassert(priv->gphy_reset);
+        reset_control_deassert(priv->gphy_reset2);
+
+        /* assert the gphy reset because it can hang after a reboot: */
+        priv->gphy_reboot_nb.notifier_call = xway_gphy_reboot_notify;
+        priv->gphy_reboot_nb.priority = -1;
+
+        ret = register_reboot_notifier(&priv->gphy_reboot_nb);
+        if (ret)
+                dev_warn(dev, "Failed to register reboot notifier\n");
+
+        platform_set_drvdata(pdev, priv);
+
+        return ret;
+}
+
+static int xway_gphy_remove(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct xway_gphy_priv *priv = platform_get_drvdata(pdev);
+        int ret;
+
+        reset_control_assert(priv->gphy_reset);
+        reset_control_assert(priv->gphy_reset2);
+
+        iowrite32be(0, priv->membase);
+
+        clk_disable_unprepare(priv->gphy_clk_gate);
+
+        ret = unregister_reboot_notifier(&priv->gphy_reboot_nb);
+        if (ret)
+                dev_warn(dev, "Failed to unregister reboot notifier\n");
+
+        return 0;
+}
+
+static struct platform_driver xway_gphy_driver = {
+        .probe = xway_gphy_probe,
+        .remove = xway_gphy_remove,
+        .driver = {
+                .name = "xway-rcu-gphy",
+                .of_match_table = xway_gphy_match,
+        },
+};
+
+module_platform_driver(xway_gphy_driver);
+
+MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin");
+MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin");
+MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin");
+MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
+MODULE_DESCRIPTION("Lantiq XWAY GPHY Firmware Loader");
+MODULE_LICENSE("GPL");
diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c
index e0823677d8c1..7f43cefa0eae 100644
--- a/drivers/watchdog/lantiq_wdt.c
+++ b/drivers/watchdog/lantiq_wdt.c
@@ -4,6 +4,7 @@
  *  by the Free Software Foundation.
  *
  *  Copyright (C) 2010 John Crispin <john@phrozen.org>
+ *  Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
  *  Based on EP93xx wdt driver
  */
 
@@ -17,9 +18,20 @@
 #include <linux/uaccess.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
 
 #include <lantiq_soc.h>
 
+#define LTQ_XRX_RCU_RST_STAT            0x0014
+#define LTQ_XRX_RCU_RST_STAT_WDT        BIT(31)
+
+/* CPU0 Reset Source Register */
+#define LTQ_FALCON_SYS1_CPU0RS          0x0060
+/* reset cause mask */
+#define LTQ_FALCON_SYS1_CPU0RS_MASK     0x0007
+#define LTQ_FALCON_SYS1_CPU0RS_WDT      0x02
+
 /*
  * Section 3.4 of the datasheet
  * The password sequence protects the WDT control register from unintended
@@ -186,16 +198,70 @@ static struct miscdevice ltq_wdt_miscdev = {
         .fops   = &ltq_wdt_fops,
 };
 
+typedef int (*ltq_wdt_bootstatus_set)(struct platform_device *pdev);
+
+static int ltq_wdt_bootstatus_xrx(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct regmap *rcu_regmap;
+        u32 val;
+        int err;
+
+        rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
+        if (IS_ERR(rcu_regmap))
+                return PTR_ERR(rcu_regmap);
+
+        err = regmap_read(rcu_regmap, LTQ_XRX_RCU_RST_STAT, &val);
+        if (err)
+                return err;
+
+        if (val & LTQ_XRX_RCU_RST_STAT_WDT)
+                ltq_wdt_bootstatus = WDIOF_CARDRESET;
+
+        return 0;
+}
+
+static int ltq_wdt_bootstatus_falcon(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct regmap *rcu_regmap;
+        u32 val;
+        int err;
+
+        rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
+                                                     "lantiq,rcu");
+        if (IS_ERR(rcu_regmap))
+                return PTR_ERR(rcu_regmap);
+
+        err = regmap_read(rcu_regmap, LTQ_FALCON_SYS1_CPU0RS, &val);
+        if (err)
+                return err;
+
+        if ((val & LTQ_FALCON_SYS1_CPU0RS_MASK) == LTQ_FALCON_SYS1_CPU0RS_WDT)
+                ltq_wdt_bootstatus = WDIOF_CARDRESET;
+
+        return 0;
+}
+
 static int
 ltq_wdt_probe(struct platform_device *pdev)
 {
         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         struct clk *clk;
+        ltq_wdt_bootstatus_set ltq_wdt_bootstatus_set;
+        int ret;
 
         ltq_wdt_membase = devm_ioremap_resource(&pdev->dev, res);
         if (IS_ERR(ltq_wdt_membase))
                 return PTR_ERR(ltq_wdt_membase);
 
+        ltq_wdt_bootstatus_set = of_device_get_match_data(&pdev->dev);
+        if (ltq_wdt_bootstatus_set) {
+                ret = ltq_wdt_bootstatus_set(pdev);
+                if (ret)
+                        return ret;
+        }
+
         /* we do not need to enable the clock as it is always running */
         clk = clk_get_io();
         if (IS_ERR(clk)) {
@@ -205,10 +271,6 @@ ltq_wdt_probe(struct platform_device *pdev)
         ltq_io_region_clk_rate = clk_get_rate(clk);
         clk_put(clk);
 
-        /* find out if the watchdog caused the last reboot */
-        if (ltq_reset_cause() == LTQ_RST_CAUSE_WDTRST)
-                ltq_wdt_bootstatus = WDIOF_CARDRESET;
-
         dev_info(&pdev->dev, "Init done\n");
         return misc_register(&ltq_wdt_miscdev);
 }
@@ -222,7 +284,9 @@ ltq_wdt_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id ltq_wdt_match[] = {
-        { .compatible = "lantiq,wdt" },
+        { .compatible = "lantiq,wdt", .data = NULL},
+        { .compatible = "lantiq,xrx100-wdt", .data = ltq_wdt_bootstatus_xrx },
+        { .compatible = "lantiq,falcon-wdt", .data = ltq_wdt_bootstatus_falcon },
         {},
 };
 MODULE_DEVICE_TABLE(of, ltq_wdt_match);
diff --git a/drivers/watchdog/octeon-wdt-main.c b/drivers/watchdog/octeon-wdt-main.c
index b5cdceb36cff..0ec419a3f7ed 100644
--- a/drivers/watchdog/octeon-wdt-main.c
+++ b/drivers/watchdog/octeon-wdt-main.c
@@ -1,7 +1,7 @@
 /*
  * Octeon Watchdog driver
  *
- * Copyright (C) 2007, 2008, 2009, 2010 Cavium Networks
+ * Copyright (C) 2007-2017 Cavium, Inc.
  *
  * Converted to use WATCHDOG_CORE by Aaro Koskinen <aaro.koskinen@iki.fi>.
  *
@@ -59,20 +59,23 @@
 #include <linux/interrupt.h>
 #include <linux/watchdog.h>
 #include <linux/cpumask.h>
-#include <linux/bitops.h>
-#include <linux/kernel.h>
 #include <linux/module.h>
-#include <linux/string.h>
 #include <linux/delay.h>
 #include <linux/cpu.h>
-#include <linux/smp.h>
-#include <linux/fs.h>
 #include <linux/irq.h>
 
 #include <asm/mipsregs.h>
 #include <asm/uasm.h>
 
 #include <asm/octeon/octeon.h>
+#include <asm/octeon/cvmx-boot-vector.h>
+#include <asm/octeon/cvmx-ciu2-defs.h>
+#include <asm/octeon/cvmx-rst-defs.h>
+
+/* Watchdog interrupt major block number (8 MSBs of intsn) */
+#define WD_BLOCK_NUMBER         0x01
+
+static int divisor;
 
 /* The count needed to achieve timeout_sec. */
 static unsigned int timeout_cnt;
@@ -84,7 +87,7 @@ static unsigned int max_timeout_sec;
 static unsigned int timeout_sec;
 
 /* Set to non-zero when userspace countdown mode active */
-static int do_coundown;
+static bool do_countdown;
 static unsigned int countdown_reset;
 static unsigned int per_cpu_countdown[NR_CPUS];
 
@@ -92,152 +95,38 @@ static cpumask_t irq_enabled_cpus;
 
 #define WD_TIMO 60                      /* Default heartbeat = 60 seconds */
 
+#define CVMX_GSERX_SCRATCH(offset) (CVMX_ADD_IO_SEG(0x0001180090000020ull) + ((offset) & 15) * 0x1000000ull)
+
 static int heartbeat = WD_TIMO;
-module_param(heartbeat, int, S_IRUGO);
+module_param(heartbeat, int, 0444);
 MODULE_PARM_DESC(heartbeat,
         "Watchdog heartbeat in seconds. (0 < heartbeat, default="
                                 __MODULE_STRING(WD_TIMO) ")");
 
 static bool nowayout = WATCHDOG_NOWAYOUT;
-module_param(nowayout, bool, S_IRUGO);
+module_param(nowayout, bool, 0444);
 MODULE_PARM_DESC(nowayout,
         "Watchdog cannot be stopped once started (default="
                                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
 
-static u32 nmi_stage1_insns[64] __initdata;
-/* We need one branch and therefore one relocation per target label. */
-static struct uasm_label labels[5] __initdata;
-static struct uasm_reloc relocs[5] __initdata;
-
-enum lable_id {
-        label_enter_bootloader = 1
-};
+static int disable;
+module_param(disable, int, 0444);
+MODULE_PARM_DESC(disable,
+        "Disable the watchdog entirely (default=0)");
 
-/* Some CP0 registers */
-#define K0              26
-#define C0_CVMMEMCTL 11, 7
-#define C0_STATUS 12, 0
-#define C0_EBASE 15, 1
-#define C0_DESAVE 31, 0
+static struct cvmx_boot_vector_element *octeon_wdt_bootvector;
 
 void octeon_wdt_nmi_stage2(void);
 
-static void __init octeon_wdt_build_stage1(void)
-{
-        int i;
-        int len;
-        u32 *p = nmi_stage1_insns;
-#ifdef CONFIG_HOTPLUG_CPU
-        struct uasm_label *l = labels;
-        struct uasm_reloc *r = relocs;
-#endif
-
-        /*
-         * For the next few instructions running the debugger may
-         * cause corruption of k0 in the saved registers. Since we're
-         * about to crash, nobody probably cares.
-         *
-         * Save K0 into the debug scratch register
-         */
-        uasm_i_dmtc0(&p, K0, C0_DESAVE);
-
-        uasm_i_mfc0(&p, K0, C0_STATUS);
-#ifdef CONFIG_HOTPLUG_CPU
-        if (octeon_bootloader_entry_addr)
-                uasm_il_bbit0(&p, &r, K0, ilog2(ST0_NMI),
-                              label_enter_bootloader);
-#endif
-        /* Force 64-bit addressing enabled */
-        uasm_i_ori(&p, K0, K0, ST0_UX | ST0_SX | ST0_KX);
-        uasm_i_mtc0(&p, K0, C0_STATUS);
-
-#ifdef CONFIG_HOTPLUG_CPU
-        if (octeon_bootloader_entry_addr) {
-                uasm_i_mfc0(&p, K0, C0_EBASE);
-                /* Coreid number in K0 */
-                uasm_i_andi(&p, K0, K0, 0xf);
-                /* 8 * coreid in bits 16-31 */
-                uasm_i_dsll_safe(&p, K0, K0, 3 + 16);
-                uasm_i_ori(&p, K0, K0, 0x8001);
-                uasm_i_dsll_safe(&p, K0, K0, 16);
-                uasm_i_ori(&p, K0, K0, 0x0700);
-                uasm_i_drotr_safe(&p, K0, K0, 32);
-                /*
-                 * Should result in: 0x8001,0700,0000,8*coreid which is
-                 * CVMX_CIU_WDOGX(coreid) - 0x0500
-                 *
-                 * Now ld K0, CVMX_CIU_WDOGX(coreid)
-                 */
-                uasm_i_ld(&p, K0, 0x500, K0);
-                /*
-                 * If bit one set handle the NMI as a watchdog event.
-                 * otherwise transfer control to bootloader.
-                 */
-                uasm_il_bbit0(&p, &r, K0, 1, label_enter_bootloader);
-                uasm_i_nop(&p);
-        }
-#endif
-
-        /* Clear Dcache so cvmseg works right. */
-        uasm_i_cache(&p, 1, 0, 0);
-
-        /* Use K0 to do a read/modify/write of CVMMEMCTL */
-        uasm_i_dmfc0(&p, K0, C0_CVMMEMCTL);
-        /* Clear out the size of CVMSEG */
-        uasm_i_dins(&p, K0, 0, 0, 6);
-        /* Set CVMSEG to its largest value */
-        uasm_i_ori(&p, K0, K0, 0x1c0 | 54);
-        /* Store the CVMMEMCTL value */
-        uasm_i_dmtc0(&p, K0, C0_CVMMEMCTL);
-
-        /* Load the address of the second stage handler */
-        UASM_i_LA(&p, K0, (long)octeon_wdt_nmi_stage2);
-        uasm_i_jr(&p, K0);
-        uasm_i_dmfc0(&p, K0, C0_DESAVE);
-
-#ifdef CONFIG_HOTPLUG_CPU
-        if (octeon_bootloader_entry_addr) {
-                uasm_build_label(&l, p, label_enter_bootloader);
-                /* Jump to the bootloader and restore K0 */
-                UASM_i_LA(&p, K0, (long)octeon_bootloader_entry_addr);
-                uasm_i_jr(&p, K0);
-                uasm_i_dmfc0(&p, K0, C0_DESAVE);
-        }
-#endif
-        uasm_resolve_relocs(relocs, labels);
-
-        len = (int)(p - nmi_stage1_insns);
-        pr_debug("Synthesized NMI stage 1 handler (%d instructions)\n", len);
-
-        pr_debug("\t.set push\n");
-        pr_debug("\t.set noreorder\n");
-        for (i = 0; i < len; i++)
-                pr_debug("\t.word 0x%08x\n", nmi_stage1_insns[i]);
-        pr_debug("\t.set pop\n");
-
-        if (len > 32)
-                panic("NMI stage 1 handler exceeds 32 instructions, was %d\n",
-                      len);
-}
-
 static int cpu2core(int cpu)
 {
 #ifdef CONFIG_SMP
-        return cpu_logical_map(cpu);
+        return cpu_logical_map(cpu) & 0x3f;
 #else
         return cvmx_get_core_num();
 #endif
 }
 
-static int core2cpu(int coreid)
-{
-#ifdef CONFIG_SMP
-        return cpu_number_map(coreid);
-#else
-        return 0;
-#endif
-}
-
 /**
  * Poke the watchdog when an interrupt is received
  *
@@ -248,13 +137,14 @@ static int core2cpu(int coreid)
  */
 static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id)
 {
-        unsigned int core = cvmx_get_core_num();
-        int cpu = core2cpu(core);
+        int cpu = raw_smp_processor_id();
+        unsigned int core = cpu2core(cpu);
+        int node = cpu_to_node(cpu);
 
-        if (do_coundown) {
+        if (do_countdown) {
                 if (per_cpu_countdown[cpu] > 0) {
                         /* We're alive, poke the watchdog */
-                        cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
+                        cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
                         per_cpu_countdown[cpu]--;
                 } else {
                         /* Bad news, you are about to reboot. */
@@ -263,7 +153,7 @@ static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id)
                 }
         } else {
                 /* Not open, just ping away... */
-                cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
+                cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
         }
         return IRQ_HANDLED;
 }
@@ -338,10 +228,10 @@ void octeon_wdt_nmi_stage3(u64 reg[32])
         u64 cp0_epc = read_c0_epc();
 
         /* Delay so output from all cores output is not jumbled together. */
-        __delay(100000000ull * coreid);
+        udelay(85000 * coreid);
 
         octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x");
-        octeon_wdt_write_hex(coreid, 1);
+        octeon_wdt_write_hex(coreid, 2);
         octeon_wdt_write_string(" ***\r\n");
         for (i = 0; i < 32; i++) {
                 octeon_wdt_write_string("\t");
@@ -364,33 +254,98 @@ void octeon_wdt_nmi_stage3(u64 reg[32])
         octeon_wdt_write_hex(cp0_cause, 16);
         octeon_wdt_write_string("\r\n");
 
-        octeon_wdt_write_string("\tsum0\t0x");
-        octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16);
-        octeon_wdt_write_string("\ten0\t0x");
-        octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16);
-        octeon_wdt_write_string("\r\n");
+        /* The CIU register is different for each Octeon model. */
+        if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
+                octeon_wdt_write_string("\tsrc_wd\t0x");
+                octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_WDOG(coreid)), 16);
+                octeon_wdt_write_string("\ten_wd\t0x");
+                octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_WDOG(coreid)), 16);
+                octeon_wdt_write_string("\r\n");
+                octeon_wdt_write_string("\tsrc_rml\t0x");
+                octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SRC_PPX_IP2_RML(coreid)), 16);
+                octeon_wdt_write_string("\ten_rml\t0x");
+                octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_EN_PPX_IP2_RML(coreid)), 16);
+                octeon_wdt_write_string("\r\n");
+                octeon_wdt_write_string("\tsum\t0x");
+                octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU2_SUM_PPX_IP2(coreid)), 16);
+                octeon_wdt_write_string("\r\n");
+        } else if (!octeon_has_feature(OCTEON_FEATURE_CIU3)) {
+                octeon_wdt_write_string("\tsum0\t0x");
+                octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16);
+                octeon_wdt_write_string("\ten0\t0x");
+                octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16);
+                octeon_wdt_write_string("\r\n");
+        }
 
         octeon_wdt_write_string("*** Chip soft reset soon ***\r\n");
+
+        /*
+         * G-30204: We must trigger a soft reset before watchdog
+         * does an incomplete job of doing it.
+         */
+        if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX)) {
+                u64 scr;
+                unsigned int node = cvmx_get_node_num();
+                unsigned int lcore = cvmx_get_local_core_num();
+                union cvmx_ciu_wdogx ciu_wdog;
+
+                /*
+                 * Wait for other cores to print out information, but
+                 * not too long.  Do the soft reset before watchdog
+                 * can trigger it.
+                 */
+                do {
+                        ciu_wdog.u64 = cvmx_read_csr_node(node, CVMX_CIU_WDOGX(lcore));
+                } while (ciu_wdog.s.cnt > 0x10000);
+
+                scr = cvmx_read_csr_node(0, CVMX_GSERX_SCRATCH(0));
+                scr |= 1 << 11; /* Indicate watchdog in bit 11 */
+                cvmx_write_csr_node(0, CVMX_GSERX_SCRATCH(0), scr);
+                cvmx_write_csr_node(0, CVMX_RST_SOFT_RST, 1);
+        }
+}
+
+static int octeon_wdt_cpu_to_irq(int cpu)
+{
+        unsigned int coreid;
+        int node;
+        int irq;
+
+        coreid = cpu2core(cpu);
+        node = cpu_to_node(cpu);
+
+        if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
+                struct irq_domain *domain;
+                int hwirq;
+
+                domain = octeon_irq_get_block_domain(node,
+                                                     WD_BLOCK_NUMBER);
+                hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | coreid;
+                irq = irq_find_mapping(domain, hwirq);
+        } else {
+                irq = OCTEON_IRQ_WDOG0 + coreid;
+        }
+        return irq;
 }
 
 static int octeon_wdt_cpu_pre_down(unsigned int cpu)
 {
         unsigned int core;
-        unsigned int irq;
+        int node;
         union cvmx_ciu_wdogx ciu_wdog;
 
         core = cpu2core(cpu);
 
-        irq = OCTEON_IRQ_WDOG0 + core;
+        node = cpu_to_node(cpu);
 
         /* Poke the watchdog to clear out its state */
-        cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
+        cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
 
         /* Disable the hardware. */
         ciu_wdog.u64 = 0;
-        cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64);
+        cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
 
-        free_irq(irq, octeon_wdt_poke_irq);
+        free_irq(octeon_wdt_cpu_to_irq(cpu), octeon_wdt_poke_irq);
         return 0;
 }
 
@@ -399,31 +354,56 @@ static int octeon_wdt_cpu_online(unsigned int cpu)
         unsigned int core;
         unsigned int irq;
         union cvmx_ciu_wdogx ciu_wdog;
+        int node;
+        struct irq_domain *domain;
+        int hwirq;
 
         core = cpu2core(cpu);
+        node = cpu_to_node(cpu);
+
+        octeon_wdt_bootvector[core].target_ptr = (u64)octeon_wdt_nmi_stage2;
 
         /* Disable it before doing anything with the interrupts. */
         ciu_wdog.u64 = 0;
-        cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64);
+        cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
 
         per_cpu_countdown[cpu] = countdown_reset;
 
-        irq = OCTEON_IRQ_WDOG0 + core;
+        if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
+                /* Must get the domain for the watchdog block */
+                domain = octeon_irq_get_block_domain(node, WD_BLOCK_NUMBER);
+
+                /* Get a irq for the wd intsn (hardware interrupt) */
+                hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | core;
+                irq = irq_create_mapping(domain, hwirq);
+                irqd_set_trigger_type(irq_get_irq_data(irq),
+                                      IRQ_TYPE_EDGE_RISING);
+        } else
+                irq = OCTEON_IRQ_WDOG0 + core;
 
         if (request_irq(irq, octeon_wdt_poke_irq,
                         IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq))
                 panic("octeon_wdt: Couldn't obtain irq %d", irq);
 
+        /* Must set the irq affinity here */
+        if (octeon_has_feature(OCTEON_FEATURE_CIU3)) {
+                cpumask_t mask;
+
+                cpumask_clear(&mask);
+                cpumask_set_cpu(cpu, &mask);
+                irq_set_affinity(irq, &mask);
+        }
+
         cpumask_set_cpu(cpu, &irq_enabled_cpus);
 
         /* Poke the watchdog to clear out its state */
-        cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
+        cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(core), 1);
 
         /* Finally enable the watchdog now that all handlers are installed */
         ciu_wdog.u64 = 0;
         ciu_wdog.s.len = timeout_cnt;
         ciu_wdog.s.mode = 3;    /* 3 = Interrupt + NMI + Soft-Reset */
-        cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64);
+        cvmx_write_csr_node(node, CVMX_CIU_WDOGX(core), ciu_wdog.u64);
 
         return 0;
 }
@@ -432,17 +412,20 @@ static int octeon_wdt_ping(struct watchdog_device __always_unused *wdog)
 {
         int cpu;
         int coreid;
+        int node;
+
+        if (disable)
+                return 0;
 
         for_each_online_cpu(cpu) {
                 coreid = cpu2core(cpu);
-                cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1);
+                node = cpu_to_node(cpu);
+                cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
                 per_cpu_countdown[cpu] = countdown_reset;
-                if ((countdown_reset || !do_coundown) &&
+                if ((countdown_reset || !do_countdown) &&
                     !cpumask_test_cpu(cpu, &irq_enabled_cpus)) {
                         /* We have to enable the irq */
-                        int irq = OCTEON_IRQ_WDOG0 + coreid;
-
-                        enable_irq(irq);
+                        enable_irq(octeon_wdt_cpu_to_irq(cpu));
                         cpumask_set_cpu(cpu, &irq_enabled_cpus);
                 }
         }
@@ -472,7 +455,7 @@ static void octeon_wdt_calc_parameters(int t)
 
         countdown_reset = periods > 2 ? periods - 2 : 0;
         heartbeat = t;
-        timeout_cnt = ((octeon_get_io_clock_rate() >> 8) * timeout_sec) >> 8;
+        timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * timeout_sec) >> 8;
 }
 
 static int octeon_wdt_set_timeout(struct watchdog_device *wdog,
@@ -481,20 +464,25 @@ static int octeon_wdt_set_timeout(struct watchdog_device *wdog,
         int cpu;
         int coreid;
         union cvmx_ciu_wdogx ciu_wdog;
+        int node;
 
         if (t <= 0)
                 return -1;
 
         octeon_wdt_calc_parameters(t);
 
+        if (disable)
+                return 0;
+
         for_each_online_cpu(cpu) {
                 coreid = cpu2core(cpu);
-                cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1);
+                node = cpu_to_node(cpu);
+                cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
                 ciu_wdog.u64 = 0;
                 ciu_wdog.s.len = timeout_cnt;
                 ciu_wdog.s.mode = 3;    /* 3 = Interrupt + NMI + Soft-Reset */
-                cvmx_write_csr(CVMX_CIU_WDOGX(coreid), ciu_wdog.u64);
-                cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1);
+                cvmx_write_csr_node(node, CVMX_CIU_WDOGX(coreid), ciu_wdog.u64);
+                cvmx_write_csr_node(node, CVMX_CIU_PP_POKEX(coreid), 1);
         }
         octeon_wdt_ping(wdog); /* Get the irqs back on. */
         return 0;
@@ -503,13 +491,13 @@ static int octeon_wdt_set_timeout(struct watchdog_device *wdog,
 static int octeon_wdt_start(struct watchdog_device *wdog)
 {
         octeon_wdt_ping(wdog);
-        do_coundown = 1;
+        do_countdown = 1;
         return 0;
 }
 
 static int octeon_wdt_stop(struct watchdog_device *wdog)
 {
-        do_coundown = 0;
+        do_countdown = 0;
         octeon_wdt_ping(wdog);
         return 0;
 }
@@ -540,14 +528,25 @@ static enum cpuhp_state octeon_wdt_online;
  */
 static int __init octeon_wdt_init(void)
 {
-        int i;
         int ret;
-        u64 *ptr;
+
+        octeon_wdt_bootvector = cvmx_boot_vector_get();
+        if (!octeon_wdt_bootvector) {
+                pr_err("Error: Cannot allocate boot vector.\n");
+                return -ENOMEM;
+        }
+
+        if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+                divisor = 0x200;
+        else if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+                divisor = 0x400;
+        else
+                divisor = 0x100;
 
         /*
          * Watchdog time expiration length = The 16 bits of LEN
          * represent the most significant bits of a 24 bit decrementer
-         * that decrements every 256 cycles.
+         * that decrements every divisor cycle.
          *
          * Try for a timeout of 5 sec, if that fails a smaller number
          * of even seconds,
@@ -555,8 +554,7 @@ static int __init octeon_wdt_init(void)
         max_timeout_sec = 6;
         do {
                 max_timeout_sec--;
-                timeout_cnt = ((octeon_get_io_clock_rate() >> 8) *
-                              max_timeout_sec) >> 8;
+                timeout_cnt = ((octeon_get_io_clock_rate() / divisor) * max_timeout_sec) >> 8;
         } while (timeout_cnt > 65535);
 
         BUG_ON(timeout_cnt == 0);
@@ -576,16 +574,10 @@ static int __init octeon_wdt_init(void)
                 return ret;
         }
 
-        /* Build the NMI handler ... */
-        octeon_wdt_build_stage1();
-
-        /* ... and install it. */
-        ptr = (u64 *) nmi_stage1_insns;
-        for (i = 0; i < 16; i++) {
-                cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8);
-                cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, ptr[i]);
+        if (disable) {
+                pr_notice("disabled\n");
+                return 0;
         }
-        cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000);
 
         cpumask_clear(&irq_enabled_cpus);
 
@@ -607,6 +599,10 @@ err:
 static void __exit octeon_wdt_cleanup(void)
 {
         watchdog_unregister_device(&octeon_wdt);
+
+        if (disable)
+                return;
+
         cpuhp_remove_state(octeon_wdt_online);
 
         /*
@@ -617,7 +613,7 @@ static void __exit octeon_wdt_cleanup(void)
 }
 
 MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Cavium Networks <support@caviumnetworks.com>");
-MODULE_DESCRIPTION("Cavium Networks Octeon Watchdog driver.");
+MODULE_AUTHOR("Cavium Inc. <support@cavium.com>");
+MODULE_DESCRIPTION("Cavium Inc. OCTEON Watchdog driver.");
 module_init(octeon_wdt_init);
 module_exit(octeon_wdt_cleanup);
diff --git a/drivers/watchdog/octeon-wdt-nmi.S b/drivers/watchdog/octeon-wdt-nmi.S
index 8a900a5e3233..97f6eb7b5a8e 100644
--- a/drivers/watchdog/octeon-wdt-nmi.S
+++ b/drivers/watchdog/octeon-wdt-nmi.S
@@ -3,20 +3,40 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2007 Cavium Networks
+ * Copyright (C) 2007-2017 Cavium, Inc.
  */
 #include <asm/asm.h>
 #include <asm/regdef.h>
 
-#define SAVE_REG(r)     sd $r, -32768+6912-(32-r)*8($0)
+#define CVMSEG_BASE     -32768
+#define CVMSEG_SIZE     6912
+#define SAVE_REG(r)     sd $r, CVMSEG_BASE + CVMSEG_SIZE - ((32 - r) * 8)($0)
 
         NESTED(octeon_wdt_nmi_stage2, 0, sp)
         .set    push
         .set    noreorder
         .set    noat
-        /* Save all registers to the top CVMSEG. This shouldn't
+        /* Clear Dcache so cvmseg works right. */
+        cache   1,0($0)
+        /* Use K0 to do a read/modify/write of CVMMEMCTL */
+        dmfc0   k0, $11, 7
+        /* Clear out the size of CVMSEG */
+        dins    k0, $0, 0, 6
+        /* Set CVMSEG to its largest value */
+        ori     k0, k0, 0x1c0 | 54
+        /* Store the CVMMEMCTL value */
+        dmtc0   k0, $11, 7
+        /*
+         * Restore K0 from the debug scratch register, it was saved in
+         * the boot-vector code.
+         */
+        dmfc0   k0, $31
+
+        /*
+         * Save all registers to the top CVMSEG. This shouldn't
          * corrupt any state used by the kernel. Also all registers
-         * should have the value right before the NMI. */
+         * should have the value right before the NMI.
+         */
         SAVE_REG(0)
         SAVE_REG(1)
         SAVE_REG(2)
@@ -49,16 +69,22 @@
         SAVE_REG(29)
         SAVE_REG(30)
         SAVE_REG(31)
+        /* Write zero to all CVMSEG locations per Core-15169 */
+        dli     a0, CVMSEG_SIZE - (33 * 8)
+1:      sd      zero, CVMSEG_BASE(a0)
+        daddiu  a0, a0, -8
+        bgez    a0, 1b
+        nop
         /* Set the stack to begin right below the registers */
-        li      sp, -32768+6912-32*8
+        dli     sp, CVMSEG_BASE + CVMSEG_SIZE - (32 * 8)
         /* Load the address of the third stage handler */
-        dla     a0, octeon_wdt_nmi_stage3
+        dla     $25, octeon_wdt_nmi_stage3
         /* Call the third stage handler */
-        jal     a0
+        jal     $25
         /* a0 is the address of the saved registers */
          move   a0, sp
         /* Loop forvever if we get here. */
-1:      b       1b
+2:      b       2b
         nop
         .set pop
         END(octeon_wdt_nmi_stage2)
diff --git a/include/dt-bindings/mips/lantiq_rcu_gphy.h b/include/dt-bindings/mips/lantiq_rcu_gphy.h
new file mode 100644
index 000000000000..fa1a63773342
--- /dev/null
+++ b/include/dt-bindings/mips/lantiq_rcu_gphy.h
@@ -0,0 +1,15 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
+ *  Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
+ */
+#ifndef _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H
+#define _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H
+
+#define GPHY_MODE_GE    1
+#define GPHY_MODE_FE    2
+
+#endif /* _DT_BINDINGS_MIPS_LANTIQ_RCU_GPHY_H */
diff --git a/include/linux/irqchip/mips-gic.h b/include/linux/irqchip/mips-gic.h
deleted file mode 100644
index 2b0e56619e53..000000000000
--- a/include/linux/irqchip/mips-gic.h
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000, 07 MIPS Technologies, Inc.
- */
-#ifndef __LINUX_IRQCHIP_MIPS_GIC_H
-#define __LINUX_IRQCHIP_MIPS_GIC_H
-
-#include <linux/clocksource.h>
-#include <linux/ioport.h>
-
-#define GIC_MAX_INTRS                   256
-
-/* Constants */
-#define GIC_POL_POS                     1
-#define GIC_POL_NEG                     0
-#define GIC_TRIG_EDGE                   1
-#define GIC_TRIG_LEVEL                  0
-#define GIC_TRIG_DUAL_ENABLE            1
-#define GIC_TRIG_DUAL_DISABLE           0
-
-#define MSK(n) ((1 << (n)) - 1)
-
-/* Accessors */
-#define GIC_REG(segment, offset) (segment##_##SECTION_OFS + offset##_##OFS)
-
-/* GIC Address Space */
-#define SHARED_SECTION_OFS              0x0000
-#define SHARED_SECTION_SIZE             0x8000
-#define VPE_LOCAL_SECTION_OFS           0x8000
-#define VPE_LOCAL_SECTION_SIZE          0x4000
-#define VPE_OTHER_SECTION_OFS           0xc000
-#define VPE_OTHER_SECTION_SIZE          0x4000
-#define USM_VISIBLE_SECTION_OFS         0x10000
-#define USM_VISIBLE_SECTION_SIZE        0x10000
-
-/* Register Map for Shared Section */
-
-#define GIC_SH_CONFIG_OFS               0x0000
-
-/* Shared Global Counter */
-#define GIC_SH_COUNTER_31_00_OFS        0x0010
-/* 64-bit counter register for CM3 */
-#define GIC_SH_COUNTER_OFS              GIC_SH_COUNTER_31_00_OFS
-#define GIC_SH_COUNTER_63_32_OFS        0x0014
-#define GIC_SH_REVISIONID_OFS           0x0020
-
-/* Convert an interrupt number to a byte offset/bit for multi-word registers */
-#define GIC_INTR_OFS(intr) ({                           \
-        unsigned bits = mips_cm_is64 ? 64 : 32;         \
-        unsigned reg_idx = (intr) / bits;               \
-        unsigned reg_width = bits / 8;                  \
-                                                        \
-        reg_idx * reg_width;                            \
-})
-#define GIC_INTR_BIT(intr)              ((intr) % (mips_cm_is64 ? 64 : 32))
-
-/* Polarity : Reset Value is always 0 */
-#define GIC_SH_SET_POLARITY_OFS         0x0100
-
-/* Triggering : Reset Value is always 0 */
-#define GIC_SH_SET_TRIGGER_OFS          0x0180
-
-/* Dual edge triggering : Reset Value is always 0 */
-#define GIC_SH_SET_DUAL_OFS             0x0200
-
-/* Set/Clear corresponding bit in Edge Detect Register */
-#define GIC_SH_WEDGE_OFS                0x0280
-
-/* Mask manipulation */
-#define GIC_SH_RMASK_OFS                0x0300
-#define GIC_SH_SMASK_OFS                0x0380
-
-/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
-#define GIC_SH_MASK_OFS                 0x0400
-
-/* Pending Global Interrupts (RO) */
-#define GIC_SH_PEND_OFS                 0x0480
-
-/* Maps Interrupt X to a Pin */
-#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
-#define GIC_SH_MAP_TO_PIN(intr)         (4 * (intr))
-
-/* Maps Interrupt X to a VPE */
-#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
-#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
-        ((32 * (intr)) + (((vpe) / 32) * 4))
-#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe)  (1 << ((vpe) % 32))
-
-/* Register Map for Local Section */
-#define GIC_VPE_CTL_OFS                 0x0000
-#define GIC_VPE_PEND_OFS                0x0004
-#define GIC_VPE_MASK_OFS                0x0008
-#define GIC_VPE_RMASK_OFS               0x000c
-#define GIC_VPE_SMASK_OFS               0x0010
-#define GIC_VPE_WD_MAP_OFS              0x0040
-#define GIC_VPE_COMPARE_MAP_OFS         0x0044
-#define GIC_VPE_TIMER_MAP_OFS           0x0048
-#define GIC_VPE_FDC_MAP_OFS             0x004c
-#define GIC_VPE_PERFCTR_MAP_OFS         0x0050
-#define GIC_VPE_SWINT0_MAP_OFS          0x0054
-#define GIC_VPE_SWINT1_MAP_OFS          0x0058
-#define GIC_VPE_OTHER_ADDR_OFS          0x0080
-#define GIC_VP_IDENT_OFS                0x0088
-#define GIC_VPE_WD_CONFIG0_OFS          0x0090
-#define GIC_VPE_WD_COUNT0_OFS           0x0094
-#define GIC_VPE_WD_INITIAL0_OFS         0x0098
-#define GIC_VPE_COMPARE_LO_OFS          0x00a0
-/* 64-bit Compare register on CM3 */
-#define GIC_VPE_COMPARE_OFS             GIC_VPE_COMPARE_LO_OFS
-#define GIC_VPE_COMPARE_HI_OFS          0x00a4
-
-#define GIC_VPE_EIC_SHADOW_SET_BASE_OFS 0x0100
-#define GIC_VPE_EIC_SS(intr)            (4 * (intr))
-
-#define GIC_VPE_EIC_VEC_BASE_OFS        0x0800
-#define GIC_VPE_EIC_VEC(intr)           (4 * (intr))
-
-#define GIC_VPE_TENABLE_NMI_OFS         0x1000
-#define GIC_VPE_TENABLE_YQ_OFS          0x1004
-#define GIC_VPE_TENABLE_INT_31_0_OFS    0x1080
-#define GIC_VPE_TENABLE_INT_63_32_OFS   0x1084
-
-/* User Mode Visible Section Register Map */
-#define GIC_UMV_SH_COUNTER_31_00_OFS    0x0000
-#define GIC_UMV_SH_COUNTER_63_32_OFS    0x0004
-
-/* Masks */
-#define GIC_SH_CONFIG_COUNTSTOP_SHF     28
-#define GIC_SH_CONFIG_COUNTSTOP_MSK     (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
-
-#define GIC_SH_CONFIG_COUNTBITS_SHF     24
-#define GIC_SH_CONFIG_COUNTBITS_MSK     (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
-
-#define GIC_SH_CONFIG_NUMINTRS_SHF      16
-#define GIC_SH_CONFIG_NUMINTRS_MSK      (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
-
-#define GIC_SH_CONFIG_NUMVPES_SHF       0
-#define GIC_SH_CONFIG_NUMVPES_MSK       (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
-
-#define GIC_SH_WEDGE_SET(intr)          ((intr) | (0x1 << 31))
-#define GIC_SH_WEDGE_CLR(intr)          ((intr) & ~(0x1 << 31))
-
-#define GIC_MAP_TO_PIN_SHF              31
-#define GIC_MAP_TO_PIN_MSK              (MSK(1) << GIC_MAP_TO_PIN_SHF)
-#define GIC_MAP_TO_NMI_SHF              30
-#define GIC_MAP_TO_NMI_MSK              (MSK(1) << GIC_MAP_TO_NMI_SHF)
-#define GIC_MAP_TO_YQ_SHF               29
-#define GIC_MAP_TO_YQ_MSK               (MSK(1) << GIC_MAP_TO_YQ_SHF)
-#define GIC_MAP_SHF                     0
-#define GIC_MAP_MSK                     (MSK(6) << GIC_MAP_SHF)
-
-/* GIC_VPE_CTL Masks */
-#define GIC_VPE_CTL_FDC_RTBL_SHF        4
-#define GIC_VPE_CTL_FDC_RTBL_MSK        (MSK(1) << GIC_VPE_CTL_FDC_RTBL_SHF)
-#define GIC_VPE_CTL_SWINT_RTBL_SHF      3
-#define GIC_VPE_CTL_SWINT_RTBL_MSK      (MSK(1) << GIC_VPE_CTL_SWINT_RTBL_SHF)
-#define GIC_VPE_CTL_PERFCNT_RTBL_SHF    2
-#define GIC_VPE_CTL_PERFCNT_RTBL_MSK    (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
-#define GIC_VPE_CTL_TIMER_RTBL_SHF      1
-#define GIC_VPE_CTL_TIMER_RTBL_MSK      (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
-#define GIC_VPE_CTL_EIC_MODE_SHF        0
-#define GIC_VPE_CTL_EIC_MODE_MSK        (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
-
-/* GIC_VPE_PEND Masks */
-#define GIC_VPE_PEND_WD_SHF             0
-#define GIC_VPE_PEND_WD_MSK             (MSK(1) << GIC_VPE_PEND_WD_SHF)
-#define GIC_VPE_PEND_CMP_SHF            1
-#define GIC_VPE_PEND_CMP_MSK            (MSK(1) << GIC_VPE_PEND_CMP_SHF)
-#define GIC_VPE_PEND_TIMER_SHF          2
-#define GIC_VPE_PEND_TIMER_MSK          (MSK(1) << GIC_VPE_PEND_TIMER_SHF)
-#define GIC_VPE_PEND_PERFCOUNT_SHF      3
-#define GIC_VPE_PEND_PERFCOUNT_MSK      (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
-#define GIC_VPE_PEND_SWINT0_SHF         4
-#define GIC_VPE_PEND_SWINT0_MSK         (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
-#define GIC_VPE_PEND_SWINT1_SHF         5
-#define GIC_VPE_PEND_SWINT1_MSK         (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
-#define GIC_VPE_PEND_FDC_SHF            6
-#define GIC_VPE_PEND_FDC_MSK            (MSK(1) << GIC_VPE_PEND_FDC_SHF)
-
-/* GIC_VPE_RMASK Masks */
-#define GIC_VPE_RMASK_WD_SHF            0
-#define GIC_VPE_RMASK_WD_MSK            (MSK(1) << GIC_VPE_RMASK_WD_SHF)
-#define GIC_VPE_RMASK_CMP_SHF           1
-#define GIC_VPE_RMASK_CMP_MSK           (MSK(1) << GIC_VPE_RMASK_CMP_SHF)
-#define GIC_VPE_RMASK_TIMER_SHF         2
-#define GIC_VPE_RMASK_TIMER_MSK         (MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
-#define GIC_VPE_RMASK_PERFCNT_SHF       3
-#define GIC_VPE_RMASK_PERFCNT_MSK       (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
-#define GIC_VPE_RMASK_SWINT0_SHF        4
-#define GIC_VPE_RMASK_SWINT0_MSK        (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
-#define GIC_VPE_RMASK_SWINT1_SHF        5
-#define GIC_VPE_RMASK_SWINT1_MSK        (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
-#define GIC_VPE_RMASK_FDC_SHF           6
-#define GIC_VPE_RMASK_FDC_MSK           (MSK(1) << GIC_VPE_RMASK_FDC_SHF)
-
-/* GIC_VPE_SMASK Masks */
-#define GIC_VPE_SMASK_WD_SHF            0
-#define GIC_VPE_SMASK_WD_MSK            (MSK(1) << GIC_VPE_SMASK_WD_SHF)
-#define GIC_VPE_SMASK_CMP_SHF           1
-#define GIC_VPE_SMASK_CMP_MSK           (MSK(1) << GIC_VPE_SMASK_CMP_SHF)
-#define GIC_VPE_SMASK_TIMER_SHF         2
-#define GIC_VPE_SMASK_TIMER_MSK         (MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
-#define GIC_VPE_SMASK_PERFCNT_SHF       3
-#define GIC_VPE_SMASK_PERFCNT_MSK       (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
-#define GIC_VPE_SMASK_SWINT0_SHF        4
-#define GIC_VPE_SMASK_SWINT0_MSK        (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
-#define GIC_VPE_SMASK_SWINT1_SHF        5
-#define GIC_VPE_SMASK_SWINT1_MSK        (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
-#define GIC_VPE_SMASK_FDC_SHF           6
-#define GIC_VPE_SMASK_FDC_MSK           (MSK(1) << GIC_VPE_SMASK_FDC_SHF)
-
-/* GIC_VP_IDENT fields */
-#define GIC_VP_IDENT_VCNUM_SHF          0
-#define GIC_VP_IDENT_VCNUM_MSK          (MSK(6) << GIC_VP_IDENT_VCNUM_SHF)
-
-/* GIC nomenclature for Core Interrupt Pins. */
-#define GIC_CPU_INT0            0 /* Core Interrupt 2 */
-#define GIC_CPU_INT1            1 /* .                */
-#define GIC_CPU_INT2            2 /* .                */
-#define GIC_CPU_INT3            3 /* .                */
-#define GIC_CPU_INT4            4 /* .                */
-#define GIC_CPU_INT5            5 /* Core Interrupt 7 */
-
-/* Add 2 to convert GIC CPU pin to core interrupt */
-#define GIC_CPU_PIN_OFFSET      2
-
-/* Add 2 to convert non-EIC hardware interrupt to EIC vector number. */
-#define GIC_CPU_TO_VEC_OFFSET   2
-
-/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
-#define GIC_PIN_TO_VEC_OFFSET   1
-
-/* Local GIC interrupts. */
-#define GIC_LOCAL_INT_WD        0 /* GIC watchdog */
-#define GIC_LOCAL_INT_COMPARE   1 /* GIC count and compare timer */
-#define GIC_LOCAL_INT_TIMER     2 /* CPU timer interrupt */
-#define GIC_LOCAL_INT_PERFCTR   3 /* CPU performance counter */
-#define GIC_LOCAL_INT_SWINT0    4 /* CPU software interrupt 0 */
-#define GIC_LOCAL_INT_SWINT1    5 /* CPU software interrupt 1 */
-#define GIC_LOCAL_INT_FDC       6 /* CPU fast debug channel */
-#define GIC_NUM_LOCAL_INTRS     7
-
-/* Convert between local/shared IRQ number and GIC HW IRQ number. */
-#define GIC_LOCAL_HWIRQ_BASE    0
-#define GIC_LOCAL_TO_HWIRQ(x)   (GIC_LOCAL_HWIRQ_BASE + (x))
-#define GIC_HWIRQ_TO_LOCAL(x)   ((x) - GIC_LOCAL_HWIRQ_BASE)
-#define GIC_SHARED_HWIRQ_BASE   GIC_NUM_LOCAL_INTRS
-#define GIC_SHARED_TO_HWIRQ(x)  (GIC_SHARED_HWIRQ_BASE + (x))
-#define GIC_HWIRQ_TO_SHARED(x)  ((x) - GIC_SHARED_HWIRQ_BASE)
-
-#ifdef CONFIG_MIPS_GIC
-
-extern unsigned int gic_present;
-
-extern void gic_init(unsigned long gic_base_addr,
-        unsigned long gic_addrspace_size, unsigned int cpu_vec,
-        unsigned int irqbase);
-extern u64 gic_read_count(void);
-extern unsigned int gic_get_count_width(void);
-extern u64 gic_read_compare(void);
-extern void gic_write_compare(u64 cnt);
-extern void gic_write_cpu_compare(u64 cnt, int cpu);
-extern void gic_start_count(void);
-extern void gic_stop_count(void);
-extern int gic_get_c0_compare_int(void);
-extern int gic_get_c0_perfcount_int(void);
-extern int gic_get_c0_fdc_int(void);
-extern int gic_get_usm_range(struct resource *gic_usm_res);
-
-#else /* CONFIG_MIPS_GIC */
-
-#define gic_present     0
-
-static inline int gic_get_usm_range(struct resource *gic_usm_res)
-{
-        /* Shouldn't be called. */
-        return -1;
-}
-
-#endif /* CONFIG_MIPS_GIC */
-
-/**
- * gic_read_local_vp_id() - read the local VPs VCNUM
- *
- * Read the VCNUM of the local VP from the GIC_VP_IDENT register and
- * return it to the caller. This ID should be used to refer to the VP
- * via the GICs VP-other region, or when calculating an offset to a
- * bit representing the VP in interrupt masks.
- *
- * Return: The VCNUM value for the local VP.
- */
-extern unsigned gic_read_local_vp_id(void);
-
-#endif /* __LINUX_IRQCHIP_MIPS_GIC_H */